content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library fsl_v20_v2_10_a;
use fsl_v20_v2_10_a.all;
entity plb_hwt_tb is
gener... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity univ_bin_counter is
generic(N: natural := 8;
count_max : INTEGER := 8);
port(
clk : in std_logic;
syn_clr, en, up : in std_logic;
clk_en : in std_logic := '1';... |
------------------------------------------------------------------------------
---- ----
---- Tewb_stbench for the ZPU Wishbone bridge ----
---- ----
-... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY midi_tb IS
END midi_tb;
ARCHITECTURE behavior OF midi_tb IS
-- Component Declaration for the Unit Under Test (UUT)
com... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity blinkoflow is
generic (data_bits : integer := 14;
mon_bits : integer := 4;
count_bits : integer := 25);
port (d : in signed(data_bits - 1 downto 0);
good : out std_logic;
bad : out std_logic;
c... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY quad_bit_alu IS
port(
a: IN SIGNED (3 DOWNTO 0);
b: IN SIGNED (3 DOWNTO 0);
s: IN UNSIGNED (2 DOWNTO 0);
z: OUT std_logic;
r: OUT SIGNED (7 DOWNTO 0)
);
END quad_bit_alu;
ARCHITECTURE alu OF quad_bi... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; use ocpi.wci.all;
package worker is
type control_in_t is record
clk : std_logic;
reset : bool_t;
control_op : control_op_t; -- what control op is in progre... |
-- created based on http://neil.franklin.ch/Info_Texts/Instruction_Set_8080
-- 20|30: unused in 8080, RIM and SIM only in 8085
-- 40|49|52|5B|64|6D|7F: are all NOPs
-- 76: would be MOV M,M (3 cycle NOP) but used for HLT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package opcodes is
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:44 07/06/2016
-- Design Name:
-- Module Name: keyboard-main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity square is
Port ( number : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC);
end square;
architecture Behavioral of square is
type FSM is (IN... |
--!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end i... |
--!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confident... |
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modi... |
-- Title : On Board Programer Package (OBP, WB-debuger simplification)
-- Project : OBP
-------------------------------------------------------------------------------
-- File : obp.vhd
-- Author : Jose Jimenez Montañez, Miguel Jimenez Lopez
-- Company : University of Granada (UGR)
-- Created : ... |
--------------------------------------------------------------------------------
-- Engineer: Klimann Wendlin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: i2s_in_tb
-- Description:
--
-- VHDL Test Bench for module: i2s_in
--
--
-------------------------------------------------------------------------... |
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest --(fum)
port map (
a => a,
... |
entity e is
port (
x : in bit_vector(8+23+2 downto 0) ); -- Error with prefer-explicit
end entity;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TernaryInConcatExample IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TernaryInConcatExample IS
BEGI... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
--lab3-Part1
--FSM with 0-8 state
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23.05.2016 06:48:08
-- Design Name:
-- Module Name: tb_defragment_and_check_crc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dep... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
process(ALUop, a, b)
begin
case ALUop is
when "000" =>
res <= a + b;
when "001" =>
res <= a - b;
when "010" =>
res <= a and b;
when "011" =>
res <= a or b;
when "100" =>
res <= not a;
when others =>
res <= (others => '0');
end case;
end process; |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ... |
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ... |
package p is
type ft is file of natural; -- OK
type int_ptr is access integer;
type bad1 is file of int_ptr; -- Error
type bad2 is file of ft; -- Error
file f1 : ft is "foo.txt" ; -- OK
file f2 : integer is "bar.txt"; -- Error
file f3 : ft open READ... |
entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
signal en : std_logic := '0';
signal rst : std_logic := '0';
begin
dut: entity work.dff02
port map (
q => dout,
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Test_sum32b IS
END Test_sum32b;
ARCHITECTURE behavior OF Test_sum32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sum32b
PORT(
Op1 : IN std_logic_vector(31 downto 0);
Op2 : IN std_logic_vector(31 downto 0)... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot.vhd,v 1.11 2007-08-08 00:39:10 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthe... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:32)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT... |
library verilog;
use verilog.vl_types.all;
entity MF_cycloneiiigl_pll is
generic(
operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock: string := "clock0";
inclk0_input_frequency: integer := 0;
inclk1_input_frequency: integer := 0;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity adder_ctrl is
port (
function_i : in std_logic_vector(2 downto 0);
opa_sign_i : in std_logic;
mx_opa_inv_o : out std_logic;
mx_ci_o : out std_logic_vector(1 downto 0));
end adder_ctrl;
architecture adder_ctrl_rtl of adder_ctrl is
begin --... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:30:05
-- Nombre del módulo: clk0_0625Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproxi... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:30:05
-- Nombre del módulo: clk0_0625Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproxi... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
------------------------------------------------------... |
architecture RTL of FIFO is
attribute max_delay : time;
attribute max_delay : time;
-- Violations below
attribute max_delay: time;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
a : inout std_logic;
enable : in std_logic;
d_in : in std_logic;
d_out : out std_logic
);
end;
architecture a of ent is
begin
process(all)
begin
if enable then
a <= d_in;
... |
entity tb_func05 is
end tb_func05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func05 is
signal r : std_logic_vector(15 downto 0);
signal s : natural;
begin
dut: entity work.func05
port map (s, r);
process
begin
s <= 2;
wait for 1 ns;
assert r = x"1234" severity fail... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NANDGATE IS
PORT (A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END NANDGATE;
ARCHITECTURE NANDG OF NANDGATE IS
BEGIN
C <= A NAND B;
END NANDG;
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_jed;
architecture behaviour of planet_jed is
constant st0: std_logic_vector(5 downto ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 12.12.2013 10:41:20
-- Design Name:
-- Module Name: switch_output_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool V... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 12.12.2013 10:41:20
-- Design Name:
-- Module Name: switch_output_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool V... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Without integer boolean operations, the generated code is very ugly
-- (see test_opt.s for the resulting assembly code)
entity test_opt is end test_opt;
architecture test of test_opt is
begin
process
variable a, b, c, d, e, f : integer := 1;
function decalage_droit(a,i : integer) return integer is
b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
library IEEE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity TREE_PG is
port(
PG0: in std_logic_vector(1 downto 0);
PG1: in std_logic_vector(1 downto 0);
PGO: out std_logic_vector(1 downto 0)
);
end TREE_PG;
architecture BEHAVIORAL of TREE_PG is
begin
PGO(0) ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end arc... |
-- Twofish_cbc_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at y... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the Licens... |
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant an... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
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