content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrspa is
generic (
fabtech : integer := virtex2;
memtech : integer := 0;
rs... |
--------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 09-04-2017
-- Package Name: alu
-- Module Name: ALU
------------------------------... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2013 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- f... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2013 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- f... |
architecture structure of ErrorIndicator is
component ErrorBit
Port ( Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
ErrorBit_i : in STD_LOGIC;
ErrorIndicatorBit_o : out STD_LOGIC);
end compo... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- revision history:
-- 2015-08-06 Carlos Minamisava Faria created
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_cpu_control is
end entity tb_cpu_control;
architecture behavioural of tb_cpu_control is
-- -------- SI... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco (fpgaddicted)
--
-- Create Date: 13:05:35 04/27/2017
-- Design Name:
-- Module Name: turnsignals_anim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Desc... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:02:41 10/09/2011
-- Design Name:
-- Module Name: BCD2Binary - BCD2BinaryArchitecture
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-14
... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:47:53 11/03/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testTest.vhd
-- Project Na... |
--SETCARRY NEEDS TO BE FIXED!!!
---------------------------------------------------
--APx-ARCH AP9 Micro-processor---------------------
--16-bits width bus--------------------------------
--External clock-----------------------------------
--Builded by MicroENIX, copyright (r) 2011---------
--For detailed description ... |
--SETCARRY NEEDS TO BE FIXED!!!
---------------------------------------------------
--APx-ARCH AP9 Micro-processor---------------------
--16-bits width bus--------------------------------
--External clock-----------------------------------
--Builded by MicroENIX, copyright (r) 2011---------
--For detailed description ... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer :=... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer :=... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer :=... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture ... |
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture ... |
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-----------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-----------------... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken... |
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken... |
---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : wb_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organiz... |
------------------------------------------------------------------------------
-- TLB arbiter implementation
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity one_wire is
generic
(
-- Number of clock cycles for 1us delay
US_D : positive
);
port
(
clk : in std_logic;
reset ... |
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.... |
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.... |
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : Syst... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:57 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_ShiftRegister.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Des... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:58 2017
-- Host : EffulgentTome running 64-bit maj... |
architecture rtl of fifo is
alias designator_a is name;
alias designator is name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_579;
architecture augh of mul_579 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_579;
architecture augh of mul_579 is
signal tmp_res : signed(... |
entity if4 is
end;
architecture behav of if4 is
begin
process
variable i : natural := 0;
begin
report "hello";
if i = 10 then
wait for 1 ns;
else
report "hello2";
end if;
report "SUCCESS";
wait;
end process;
end behav;
|
entity if4 is
end;
architecture behav of if4 is
begin
process
variable i : natural := 0;
begin
report "hello";
if i = 10 then
wait for 1 ns;
else
report "hello2";
end if;
report "SUCCESS";
wait;
end process;
end behav;
|
-- $Id: opb_v20_wrap.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIME... |
-- $Id: opb_v20_wrap.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIME... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:10 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
-- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
-- http://ece320web.groups.et.byu.net/labs/VGATextGeneration/list_ch13_01_font_rom.vhd
libr... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_nov;
architecture behaviour of bbsse_nov is
constant st0: std_logic_vector(3 downto 0) :... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM2_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM2_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:10:35 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Auth... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C... |
--------------------------------------------------------------------------------
-- Entity: microwire_eeprom
-- Date:2018-08-13
-- Author: gideon
--
-- Description: Emulation of ST M93C86 Microwire EEPROM.
-- The I/O interface enables the software to read/write directly to
-- the 2K embed... |
-------------------------------------------------------------------------------
-- Title : ALU log_nor
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Log_Nor.vhd
-- Author : Robert... |
----------------------------------------------------------------------------------
--this is an parallel to serial converter
--takes command_in and serilize it for the LED driver
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:21:57 01/15/2015
-- Design Name:
-- Module Name: componant_2_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:21:57 01/15/2015
-- Design Name:
-- Module Name: componant_2_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
entity FIFO is
end ENTITY fifo;
entity FIFO is
end ENTITY FIFO;
entity FIFO is
end ENTITY FIFO;
|
library ieee;
use ieee.std_logic_1164.all;
entity TbdFIR is
port(
-- Clock
Clock_50 : in std_logic;
-- KEYs
KEY : in std_logic_vector(0 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AU... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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