text stringlengths 183 150k | path stringlengths 15 112 | bucket stringclasses 4
values | source stringclasses 14
values | group stringclasses 121
values | spdx stringclasses 11
values | repo_license stringclasses 11
values | commit stringclasses 13
values | lang stringclasses 4
values | def_heavy bool 1
class | comment_ratio float64 0 1 | restricted bool 2
classes | fresh bool 1
class | n_bytes int64 183 150k | n_tokens int64 -1 -1 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
`define SALU_SOPP_FORMAT 8'h01
`define SALU_SOP1_FORMAT 8'h02
`define SALU_SOPC_FORMAT 8'h04
`define SALU_SOP2_FORMAT 8'h08
`define SALU_SOPK_FORMAT 8'h10
module salu_controller(
control_en,
dst_reg,
opcode,
alu_control,
branch_on_cc,
exec_en,
vcc_en,
scc_en,
m0_en,
sgpr_en,
vcc_wordsel,
exec_wordsel,
exe... | miaow/src/verilog/rtl/salu/salu_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.26 | false | false | 7,657 | -1 |
module fpga_memory
(
// input
// LSU
mem_wr_en, mem_rd_en,
mem_addr, mem_wr_data, mem_tag_req,
// MB
mb_data_in, mb_data_we, mb_ack, mb_done,
clk, rst,
// output
// LSU
mem_tag_resp, mem_rd_data, mem_ack,
// MB
mb_op, mb_data_out, mb_addr
);
input clk;
input rst;
input mem_wr_en;
inpu... | miaow/src/verilog/rtl/fpga/fpga_memory.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.054 | false | false | 3,089 | -1 |
`define DECODE_BIT0 3'b111
`define DECODE_BIT32 3'b000
`define DECODE_BIT64 3'b001
`define DECODE_BIT128 3'b010
`define DECODE_BIT256 3'b011
`define DECODE_BIT512 3'b100
`define DECODE_BIT96 3'b101
//VIN
`define EXT_LIT_255 10'b1011111111 // 255
//`define EXT_LIT_128 10'b1010000000 // 128 - INT 0
//`define EXT_LIT_2... | miaow/src/verilog/rtl/decode/decode_definitions.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.273 | false | false | 354 | -1 |
module exec(
lsu_rd_wfid,
salu_wr_exec_en,
salu_wr_vcc_en,
salu_wr_exec_value,
salu_wr_vcc_value,
salu_wr_wfid,
salu_rd_en,
salu_rd_wfid,
salu_wr_m0_en,
salu_wr_m0_value,
salu_wr_scc_en,
salu_wr_scc_value,
simd0_rd_wfid,
simd1_rd_wfid,
... | miaow/src/verilog/rtl/exec/exec.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.025 | false | false | 7,503 | -1 |
#include "helper.h"
FILE *config_file;
FILE *instrmem_file;
FILE *datamem_file;
configValues configs;
#ifdef WIN32
#include <vector>
char *optarg = nullptr;
char getopt(int argc, char **argv, const char* pattern)
{
std::vector<std::string> options;
char return_value;
static int arg_post = 1;
if (arg... | miaow/src/sw/siagen/helper.cpp | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | cpp | false | 0.169 | false | false | 8,839 | -1 |
module adder6bit (
sum,
cout,
in1,
in2
);
output[5:0] sum;
output cout;
input[5:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4;
adder1bit add0(sum[0], cout0, in1[0], in2[0], 1'b0);
adder1bit add1(sum[1], cout1, in1[1], in2[1], cout0);
adder1bit add2(sum[2], cout2, in1[2], in2[2], cout1);
adder1bit add3(sum... | miaow/src/verilog/rtl/fetch/adder6bit.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 474 | -1 |
module round_robin (
fetch_valid,
pc_select,
queue_vfull,
icache_ack,
vacant,
clk,
rst
);
output fetch_valid;
output[5:0] pc_select;
input[39:0] queue_vfull;
input icache_ack;
input[39:0] vacant;
input clk, rst;
wire[5:0] icache_req_out, icache_req_in;
wire[5:0] icache_req_plus1, icache_req_minus1;
wire ign_c... | miaow/src/verilog/rtl/fetch/round_robin.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.053 | false | false | 1,491 | -1 |
module alu_controller
(/*AUTOARG*/
// Outputs
out_alu_ready, out_vcc_wr_en, out_instr_done, out_vgpr_wr_en,
out_vgpr_dest_addr, out_sgpr_wr_en, out_sgpr_dest_addr,
out_alu_control, out_alu_start, out_src_buffer_wr_en,
out_source1_mux_select, out_source2_mux_select,
out_source3_mux_select, out_sourc... | miaow/src/verilog/rtl/alu/alu_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.01 | false | false | 11,605 | -1 |
module wfid_generator(
halt,
WF_tag,
WF_id_done,
vacant,
vacant_next,
WF_id,
WF_tag_done,
clk,
wr,
rst
);
input clk;
input rst;
input halt;
input wr;
input [14:0] WF_tag;
input [5:0] WF_id_done; //rename
input [39:0] vacant;
output [39:0] vacant_next;
output [5:0] WF_id; //new id generated
output [... | miaow/src/verilog/rtl/fetch/wfid_generator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 554 | -1 |
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM );
input [0:575] SUMMAND;
input RST;
input CLK;
output [0:62] CARRY;
output [0:63] SUM;
wire [0:7] LATCHED_PP;
wire [0:523] INT_CARRY;
wire [0:669] INT_SUM;
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SA... | miaow/src/verilog/rtl/simd/amultp2_32x32.v#p2 | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.002 | false | false | 140,640 | -1 |
module lsu_op_manager
(
lsu_wfid,
instr_pc,
mem_op_cnt,
mem_op_rd,
mem_op_wr,
mem_gpr,
gm_or_lds,
sgpr_wr_mask,
gpr_op_depth,
exec_mask,
mem_in_addr,
mem_ack,
mem_rd_data,
vgpr_source1_data,
free_mem_slots,
decoded_sgpr_s... | miaow/src/verilog/rtl/lsu/lsu_op_manager.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.052 | false | false | 16,940 | -1 |
module adder7bit (
sum,
cout,
in1,
in2
);
output[6:0] sum;
output cout;
input[6:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4, cout5;
adder1bit add0(sum[0], cout0, in1[0], in2[0], 1'b0);
adder1bit add1(sum[1], cout1, in1[1], in2[1], cout0);
adder1bit add2(sum[2], cout2, in1[2], in2[2], cout1);
adder1bit a... | miaow/src/verilog/rtl/fetch/adder7bit.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 535 | -1 |
module queue_param_1r_1w(
in_wr_en,
in_wr_addr,
in_wr_data,
in_rd_addr,
out_rd_data,
clk,
rst
);
parameter BITS = 2;
para... | miaow/src/verilog/rtl/common/queue_param_1r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,084 | -1 |
module dff_clr (q, d, clk, rst);
output q;
input d;
input clk;
input rst;
reg state;
assign q = state;
always @(posedge clk or posedge rst)
begin
state <= rst? 1 : d;
end
`ifdef dump_flops
always @(posedge gpu_tb.rst)
begin
... | miaow/src/verilog/rtl/fetch/dff_clr.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 432 | -1 |
module vgpr_busy_table_mux
(
in,
select,
out
);
parameter MAX_NUMBER_WORDS = 4;
input[`NUMBER_VGPR-1:0] in;
wire[`NUMBER_VGPR+4-1:0] in_rotated;
input [`VGPR_ADDR_LENGTH-1:0] select;
output [MAX_NUMBER_WORDS-1:0] out;
assign in_rotated = {in[3:0], in};
assign out = in_rotated >>... | miaow/src/verilog/rtl/issue/vgpr_busy_table_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 339 | -1 |
module vgpr_tb;
//wires
reg clk;
reg rst;
reg simd0_source1_rd_en, simd1_source1_rd_en, simd2_source1_rd_en,
simd3_source1_rd_en, simd0_source2_rd_en, simd1_source2_rd_en, simd2_source2_rd_en,
simd3_source2_rd_en, simd0_source3_rd_en, simd1_source3_rd_en, simd2_source3_rd_en,
simd3_sou... | miaow/src/verilog/tb/vgpr/vgpr_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.086 | false | false | 10,561 | -1 |
module add_wraparound_after40 (
out_value,
in_value_1,
in_value_2
);
output[5:0] out_value;
input[5:0] in_value_1, in_value_2;
wire[5:0] inter_sum;
wire[6:0] inter_sub_40;
wire cout1, cout2, is_less_than_40;
adder6bit a6b(inter_sum, cout1, in_value_1, in_value_2); // adding two inputs
adder7bit a7b(inter_sub_40, ... | miaow/src/verilog/rtl/fetch/add_wraparound_after40.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 519 | -1 |
module mux4to1_6bit (
out,
input0,
input1,
input2,
input3,
select
);
output[5:0] out;
input[5:0] input0, input1, input2, input3;
input[1:0] select;
assign out = (input0 & {6{(select == 2'b00)}}) |
(input1 & {6{(select == 2'b01)}}) |
(input2 & {6{(select == 2'b10)}}) |
(input3 & {6{(select == 2'b11)... | miaow/src/verilog/rtl/fetch/mux4to1_6bit.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 336 | -1 |
module issue_tb();
parameter MAX_INFLIGHT_TB = 8;
parameter STORED_INSTR_INFO_LENGTH = (1 + 6 + 1 + 9 + 1 + 10 + 1 + 6 + 1 + 9 + 1 + 10);
wire clk, rst;
reg decode_barrier;
reg decode_branch;
reg [13:0] decode_dest_reg1;
reg [12:0] decode_dest_reg2;
reg decode_exec_rd;
... | miaow/src/verilog/tb/issue/issue_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.112 | false | false | 18,647 | -1 |
module test_round_robin();
reg[39:0] queue_vfull;
reg icache_ack;
reg[39:0] vacant;
reg clk, rst;
wire fetch_valid;
wire[5:0] pc_select;
round_robin rr(fetch_valid, pc_select, queue_vfull, icache_ack, vacant, clk, rst);
initial begin
clk = 0;
while (1) begin
#2;
clk = ~clk;
end
end
initial begin
rst <= ... | miaow/src/verilog/tb/fetch/test_round_robin.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.109 | false | false | 1,204 | -1 |
module simf(
issue_source_reg1,
issue_source_reg2,
issue_source_reg3,
issue_dest_reg1,
issue_dest_reg2,
issue_imm_value0,
issue_imm_value1,
issue_opcode,
issue_wfid,
issue_alu_select,
vgpr_source1_data,
vgpr_source2_data,
vgpr_source3_data,
... | miaow/src/verilog/rtl/simf/simf.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 4,131 | -1 |
module arbiter(
// Inputs
input_arry,
issued_en,
issued_wf_id,
// Outputs
choosen_valid,
choosen_wf_id,
clk,
rst
);
input clk,rst;
input issued_en;
input[5:0] issued_wf_id;
input[39:0] input_arry;
output choosen_valid;
output[5:0] choosen_wf_id;
wire[5:0] last_issued_wf_... | miaow/src/verilog/rtl/issue/arbiter.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.038 | false | false | 1,383 | -1 |
#include "siagen.h"
#include <time.h>
#ifdef WIN32
#include <Windows.h>
#include <strsafe.h>
#endif
extern configValues configs;
int instr_arr[MAX_INSTR];
int main(int argc, char *argv[])
{
// populate configs
parseArgs(argc, argv);
srand((unsigned int)time(NULL));
int i, j;
if (configs.unit_t... | miaow/src/sw/siagen/main.cpp | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | cpp | false | 0.362 | false | false | 1,552 | -1 |
`timescale 1 ns / 1 ps
module axi_slave_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH =... | miaow/scripts/xilinx/axi_slave_v1_0_S00_AXI.v | arch_code | miaow | miaow/scripts/xilinx | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.128 | false | false | 43,118 | -1 |
module decoder_6b_40b_en(
addr_in,
en,
out);
input[5:0] addr_in;
wire[5:0] addr_in;
output[39:0] out;
wire[39:0] out;
input en;
wire en;
reg[39:0] decoded_out;
always@(addr_in)
begin
decoded_out = 40'd0;
case (addr_in)
0: decoded_out[0]=1'b1;
1: decoded_out[1]=1'b1;
2: ... | miaow/src/verilog/rtl/common/decoder_6b_40b_en.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,688 | -1 |
module simf_instr_decoder
(/*AUTOARG*/
// Outputs
out_vcc_wr_en, out_vgpr_wr_en, out_sgpr_wr_en,
// Inputs
in_opcode, in_sgpr_dest_addr
);
input [31:0] in_opcode;
input [11:0] in_sgpr_dest_addr;
output out_vcc_wr_en;
output out_vgpr_wr_en;
output out_sgpr_wr_en;
reg out_vcc_wr_en;
reg out_vgpr_wr_e... | miaow/src/verilog/rtl/simf/simf_instr_decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.007 | false | false | 9,264 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_pre_norm_mul ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_pre_norm_mul.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.468 | false | false | 4,377 | -1 |
module dff_set_en_rst(
d,
q,
en,
clk,
set,
rst );
output q;
input d;
input en;
input clk;
input set;
input rst;
wire d_int;
reg state;
assign d_int = en ? d : state;
assign q = state;
always @(posedge clk or posedge rst)
begin
if(rst)
state <= 0;
... | miaow/src/verilog/rtl/common/dff_set_en_rst.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 545 | -1 |
module busy_gpr_table
(/*AUTOARG*/
// Outputs
decode_dest_reg1_busy_bits, decode_source_reg1_busy_bits,
decode_source_reg4_busy_bits, decode_source_reg2_busy_bits,
decode_source_reg3_busy_bits, decode_dest_reg2_busy_bits,
// Inputs
clk, rst, alu_valid, lsu_valid, f_decode_source_reg2,
f_decode_so... | miaow/src/verilog/rtl/issue/busy_gpr_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.074 | false | false | 13,057 | -1 |
module sgpr_simxlsu_wr_port_mux
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_addr, muxed_port_wr_data,
muxed_port_wr_mask,
// Inputs
//**CHANGE [PSP]
//**add ports 9 for SALU integration
wr_port_select, port0_wr_en, port0_wr_addr, port0_wr_data,
port0_wr_mask, port1_wr_en, port1_w... | miaow/src/verilog/rtl/sgpr/sgpr_simxlsu_wr_port_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.062 | false | false | 6,132 | -1 |
module cu_simulator (/*AUTOARG*/
// Outputs
cu2dispatch_wf_done, cu2dispatch_wf_tag_done,
// Inputs
clk, rst, all_wf_dispatched, dispatch2cu_wf_dispatch,
dispatch2cu_lds_base_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_start_pc_dispatch, dispatch2cu_vgpr_base_dispatch,
dispatch2cu_wf_size... | miaow/src/verilog/rtl/dispatcher/sim/src/cu_simulator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.059 | false | false | 3,585 | -1 |
module valu
(
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
alu_control,
alu_start,
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_dest_exec_value,
valu_done,
clk,
rst
);
parameter MODULE = `MODULE_S... | miaow/src/verilog/rtl/alu/valu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,226 | -1 |
module decoder_param (out, in);
parameter BITS = 2;
parameter SIZE = 4;
output [SIZE - 1:0] out;
input [BITS - 1:0] in;
reg [SIZE -1: 0] out;
integer i;
always @ (in)
begin
for(i = 0; i < SIZE; i = i + 1)
begin
out[i] = (in == i) ? 1'b1 : 1'b0;
end
... | miaow/src/verilog/rtl/common/decoder_param.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 340 | -1 |
/*
* MIAOW
* Adapted from Multi2Sim
* Modified by Pradip Harindran Vallathol (pradip16@cs.wisc.edu)
* Original Copyright below
*/
/*
* Multi2Sim
* Copyright (C) 2012 Rafael Ubal (ubal@ece.neu.edu)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Ge... | miaow/src/sw/siagen/asm.h | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | c | false | 0.135 | false | false | 10,890 | -1 |
// D-flipflop
// Copied from http://pages.cs.wisc.edu/~karu/courses/cs552/spring2009/handouts/verilog_code/dff.v
module dff_set (q, d, clk, set);
output q;
input d;
input clk;
input set;
reg state;
assign q = state;
always @(posedge clk)
begin
... | miaow/src/verilog/rtl/common/dff_set.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.087 | false | false | 529 | -1 |
module functional_unit_reg_bank
(/*AUTOARG*/
// Outputs
fu_simd, fu_salu, fu_lsu, fu_simf,
// Inputs
clk, rst, f_decode_valid, f_decode_fu, f_decode_wfid
);
input clk,rst;
input f_decode_valid;
input [1:0] f_decode_fu;
input [`WF_ID_LENGTH-1:0] f_decode_wfid;
output [`WF_PER_CU-1:0] ... | miaow/src/verilog/rtl/issue/functional_unit_reg_bank.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.061 | false | false | 932 | -1 |
module simf_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1,... | miaow/src/verilog/tb/simf/simf_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.144 | false | false | 7,151 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../")
// End:
module resource_table_tb ();
localparam CU_ID_WIDTH = 1;
localparam NUMBER_CU = 2;
localparam WF_SLOT_ID_WIDTH = 4;
localparam NUMBER_WF_SLOTS_PER_CU = 4;
localparam RES_ID_WIDTH = 4;
localparam NUMBER_RES_SLOTS = 16;
... | miaow/src/verilog/rtl/dispatcher/sim/src/resource_table_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.115 | false | false | 4,699 | -1 |
extern "C" int ScheduleWavefront();
extern "C" void DescheduleWavefront(int cuid, int wfTag);
extern "C" int getTotalWavefronts();
extern "C" int getCuId();
//extern "C" int getWgId();
//extern "C" int getWfId();
extern "C" int getWfTag();
extern "C" int getWfCnt();
extern "C" int getWfNumThrds();
extern "C" int getVre... | miaow/src/verilog/tb/dispatcher_wrapper/dispatcher_soft.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.101 | false | false | 5,640 | -1 |
module scoreboard
(/*AUTOARG*/
// Outputs
lsu_source_reg1, lsu_source_reg2, lsu_source_reg3, lsu_dest_reg,
lsu_mem_sgpr, alu_source_reg1, alu_source_reg2, alu_source_reg3,
alu_dest_reg1, alu_dest_reg2, lsu_imm_value0, alu_imm_value0,
lsu_lds_base, lsu_imm_value1, lsu_opcode, alu_imm_value1,
alu_opco... | miaow/src/verilog/rtl/issue/scoreboard.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.096 | false | false | 17,693 | -1 |
module dispatcher_wrapper (/*AUTOARG*/
// Outputs
dispatch2cu_wf_dispatch, dispatch2cu_wg_wf_count,
dispatch2cu_wf_size_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_vgpr_base_dispatch, dispatch2cu_wf_tag_dispatch,
dispatch2cu_lds_base_dispatch, dispatch2cu_start_pc_dispatch,
ldssize_out, vreg... | miaow/src/verilog/tb/dispatcher_wrapper/dispatcher_wrapper.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.089 | false | false | 5,365 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_pre_norm_div ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_pre_norm_div.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.267 | false | false | 8,308 | -1 |
module rd_port_mux_8to1 (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
rd_data,
muxed_port_rd_ad... | miaow/src/verilog/rtl/vgpr/rd_port_mux_8to1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,994 | -1 |
module sgpr_simx_rd_port_mux (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
port_rd_data,
rd... | miaow/src/verilog/rtl/sgpr/sgpr_simx_rd_port_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,543 | -1 |
module fetch_controller (
WF_dispatch_i,
fetch_valid,
wr,
inst_buff_rd,
wave_reserve_valid
);
input WF_dispatch_i;
input fetch_valid;
output wr;
output inst_buff_rd;
output wave_reserve_valid;
assign wr = WF_dispatch_i;
assign wave_reserve_valid = fetch_valid;
assign inst_buff_rd = fetch_valid;
endmodule
| miaow/src/verilog/rtl/fetch/fetch_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 319 | -1 |
module rfa(/*AUTOARG*/
// Outputs
simd0_queue_entry_serviced, simd1_queue_entry_serviced,
simd2_queue_entry_serviced, simd3_queue_entry_serviced,
simf0_queue_entry_serviced, simf1_queue_entry_serviced,
simf2_queue_entry_serviced, simf3_queue_entry_serviced,
execvgprsgpr_select_fu,
//**CHANGE [PSP]
... | miaow/src/verilog/rtl/rfa/rfa.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.185 | false | false | 3,983 | -1 |
/**
* global_definitions.v
* File with al global definitions of the miaow project.
* This file does not need to be included within the modules but it needs to be
* listed for compilation/syntesys.
*/
`ifndef _global_definitions_v_
`define _global_definitions_v_
// Maximum number of wavefronts per compute unit
`def... | miaow/src/verilog/rtl/common/global_definitions.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.5 | false | false | 855 | -1 |
module tester(
clk,
rst
);
parameter end_simulation = 32'hffff;
output clk,rst;
reg clk, rst;
integer clk_count;
integer tests_done;
integer tests_failed;
initial begin
forever begin
#10 clk <= ~clk;
if(clk) clk_count = clk_count + 1;
if(clk_count == end_simulation) begin
... | miaow/src/verilog/tb/issue/tester.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.013 | false | false | 1,819 | -1 |
`timescale 1 ns / 1 ps
module axi_slave_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
)
(
... | miaow/scripts/xilinx/axi_slave_v1_0.v | arch_code | miaow | miaow/scripts/xilinx | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.133 | false | false | 3,235 | -1 |
module wr_port_40x64b_8_to_1 (
select,
port0_wr_en,
port0_wr_addr,
port0_wr_data,
port1_wr_en,
port1_wr_addr,
port1_wr_data,
port2_wr_en,
port2_wr_addr,
port2_wr_data,
port3_wr_en,
port3_wr_addr,
port3_wr_data,
port4_wr_en,
port4_wr_addr,
port4_wr_data,
port5_wr_... | miaow/src/verilog/rtl/exec/wr_port_40x64b_8_to_1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 3,909 | -1 |
module sgpr(
lsu_source1_addr,
lsu_source2_addr,
lsu_dest_addr,
lsu_dest_data,
lsu_dest_wr_en,
lsu_instr_done_wfid,
lsu_instr_done,
lsu_source1_rd_en,
lsu_source2_rd_en,
simd0_rd_addr,
simd0_rd_en,
simd1_rd_addr,
simd1_rd_en,
simd2_rd_... | miaow/src/verilog/rtl/sgpr/sgpr.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.046 | false | false | 12,268 | -1 |
module mux_40xPARAMb_to_1xPARAMb(
out,
in,
select );
parameter WORD_WIDTH = 12;
input[40*WORD_WIDTH-1:0] in;
input[5:0] select;
output[WORD_WIDTH-1:0] out;
reg[WORD_WIDTH-1:0] out;
always @(in or select) begin
casex(select)
6'h00: o... | miaow/src/verilog/rtl/issue/mux_40xPARAMb_to_1xPARAMb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,764 | -1 |
module wg_resource_table (/*AUTOARG*/
// Outputs
wg_res_tbl_wg_slot_id, wg_res_tbl_wg_count_out,
// Inputs
rst, clk, wg_res_tbl_alloc_en, wg_res_tbl_dealloc_en,
wg_res_tbl_cu_id, wg_res_tbl_wg_id, wg_res_tbl_alloc_wg_wf_count,
wg_res_tbl_inflight_res_tbl_id
) ;
parameter NUMBER_CU = 64;
para... | miaow/src/verilog/rtl/dispatcher/wg_resource_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.184 | false | false | 13,946 | -1 |
module issue_flow_control
(/*AUTOARG*/
// Outputs
wave_valid_entries,
// Inputs
clk, rst, tracemon_barrier_retire_en, valid_entry_out,
tracemon_barrier_retire_wf_bitmap, f_decode_wfid,
f_salu_branch_wfid, alu_wfid, f_decode_valid, f_decode_waitcnt,
f_salu_branch_en, alu_valid, alu_branch
);
... | miaow/src/verilog/rtl/issue/issue_flow_control.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.075 | false | false | 2,415 | -1 |
module priority_encoder_16_to_4 (
out,
in,
enable
);
output[3:0] out;
input[15:0] in;
input enable;
assign out =
(!enable) ? 4'd0 : (
(in[0]) ? 4'd0 :
(in[1]) ? 4'd1 :
(in[2]) ? 4'd2 :
(in[3]) ? 4'd3 :
(in[4]) ? 4'd4 :
(in[5]) ? 4'd5 :
(in[6]) ? 4'd6 :
(i... | miaow/src/verilog/rtl/rfa/priority_encoder_16_to_4.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 555 | -1 |
module memory(
gm_or_lds,
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
// wr_mask,
rd_data,
output_tag,
ack,
clk,
rst
);
input clk;
input rst;
input gm_or_lds;
input rd_en, wr_en;
input [31:0] addresses;
input [31:0] wr_data;
input [6:0] input_ta... | miaow/src/verilog/rtl/memory/memory.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.143 | false | false | 2,085 | -1 |
//rd0 - 128/64/32 bits wide (can be unaligned)
//rd1 - 32 bits wide
//rd2 - 32 bits wide
//wr0 - 128/64/32 bits wide (4 bit enable) (can be unaligned)
module reg_1024x32b_3r_1w (/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_d... | miaow/src/verilog/rtl/vgpr/reg_1024x32b_3r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.171 | false | false | 2,306 | -1 |
#ifndef __TRACEMON_H__
#define __TRACEMON_H__
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <pthread.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#define MAX_NUM_OF_CU 4
#define MAX_WFS_IN_CU 40
#define MAX_INSTR_FLIGHT 20
#define MAX_STR 400
#define MA... | miaow/src/verilog/rtl/tracemon/tracemon.h | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | c | false | 0.294 | false | false | 3,013 | -1 |
module wq_pool (
q_vtail_incr,
q_rd,
q_wr,
q_reset,
q_empty,
stop_fetch,
instr_pc_in,
instr_pc_out,
wf_select,
clk,
rst
);
input [39:0] q_vtail_incr;
input [39:0] q_rd;
input [39:0] q_wr;
input [39:0] q_reset;
output [39:0] q_empty;
output [39:0] stop_fetch;
input [63:0] instr_pc_in;
output [63... | miaow/src/verilog/rtl/wavepool/wq_pool.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 800 | -1 |
module lsu
(/*AUTOARG*/
// Outputs
issue_ready,
vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en,
mem_gm_or_lds, tracemon_gm_or_lds,
vgpr_dest_wr_en,
mem_rd_en, mem_wr_en,
sgpr_dest_wr_en,
exec_rd_wfid,
mem_tag_req,
sgpr_source1_addr, sgpr_source... | miaow/src/verilog/rtl/lsu/lsu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.067 | false | false | 7,760 | -1 |
module fpu_tb ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire div_zero_o; // From DUT of fpu_arith.v
wire ine_o; // From DUT of fpu_arith.v
wire inf_o; // From DUT of fpu_arith.v
wire [32-1:0] output_o; // From DUT of fpu_arith.v
wire ... | miaow/src/verilog/tb/fpu/fpu_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.181 | false | false | 2,874 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../")
// End:
module dis_controller_tb
(/*AUTOARG*/);
localparam NUMBER_CU = 8;
localparam RES_TABLE_ADDR_WIDTH = 1;
localparam CU_ID_WIDTH = 3;
localparam WG_ID_WIDTH = 10;
localparam WG_SLOT_ID_WIDTH = 6;
localparam NUMBER_WF_SLOT... | miaow/src/verilog/rtl/dispatcher/sim/dis_controller/src/dis_controller_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.108 | false | false | 16,918 | -1 |
module wavegrp_info (
wf_wr_en,
wr_wf_tag,
wr_wg_wf_count,
wr_wfid,
halt,
halt_wfid,
rd_wfid,
rd_wgid,
rd_wf_count,
clk,
rst
);
input clk;
input rst;
input wf_wr_en;
input [14:0] wr_wf_tag;
input [3:0] wr_wg_wf_count;
input [5:0] wr_wfid;
input [5:0] rd_wfid;
input halt;
input [5:0] halt_wfid;
output [5:0... | miaow/src/verilog/rtl/fetch/wavegrp_info.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.038 | false | false | 1,750 | -1 |
module rd_port_9_to_1 (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
port8_rd_en,
port8_rd_addr,
... | miaow/src/verilog/rtl/exec/rd_port_9_to_1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,065 | -1 |
module dispatcher
(/*AUTOARG*/
// Outputs
inflight_wg_buffer_host_wf_done_wg_id,
inflight_wg_buffer_host_wf_done, inflight_wg_buffer_host_rcvd_ack,
dispatch2cu_lds_base_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_start_pc_dispatch, dispatch2cu_vgpr_base_dispatch,
dispatch2cu_wf_dispatch, ... | miaow/src/verilog/rtl/dispatcher/dispatcher.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.086 | false | false | 23,655 | -1 |
module exec_tb;
//wires
reg clk;
reg rst;
reg salu_wr_exec_en, salu_wr_vcc_en, salu_rd_en, salu_wr_m0_en, salu_wr_scc_en,
salu_wr_scc_value, simd0_rd_en, simd1_rd_en, simd2_rd_en, simd3_rd_en,
simd0_vcc_wr_en, simd1_vcc_wr_en, simd2_vcc_wr_en, simd3_vcc_wr_en,
simf0_rd_en, simf1_rd_en, s... | miaow/src/verilog/tb/exec/exec_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.074 | false | false | 10,311 | -1 |
module encoder_5b_3b(
in,
out
);
input[4:0] in;
output[2:0] out;
reg[2:0] out;
always @(in) begin
out = 3'h0;
case(in)
5'b00001: out = 3'h0;
5'b00010: out = 3'h1;
5'b00100: out = 3'h2;
5'b01000: out = 3'h3;
5'b10000: out = 3'h4;
default: out = 3'h0... | miaow/src/verilog/rtl/common/encoder_5b_3b.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 348 | -1 |
module reg_field_encoder (
in,
sgpr_base,
vgpr_base,
out,
literal_required,
explicit_vcc,
explicit_exec,
explicit_scc,
explicit_M0,
fp_constant
);
input [9:0] in;
input [8:0] sgpr_base;
input [9:0] vgpr_base;
output [11:0] out;
output literal_required;
output explicit_vcc;
output explicit_exec;
output explic... | miaow/src/verilog/rtl/decode/reg_field_encoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.09 | false | false | 9,914 | -1 |
module alu_issue_logic
(/*AUTOARG*/
// Outputs
c_issued_valid, c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select, c_simf0_alu_select,
c_simf1_alu_select, c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select, c_issued_wfid,
// Inputs
clk, rs... | miaow/src/verilog/rtl/issue/alu_issue_logic.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.031 | false | false | 6,708 | -1 |
module finished_wf
(/*AUTOARG*/
// Outputs
fetchwave_wf_done_en, fetchwave_wf_done_wf_id,
max_instr_inflight_array,
// Inputs
clk, rst, f_decode_wfid, f_sgpr_alu_wr_done_wfid,
f_vgpr_alu_wr_done_wfid, alu_wfid, f_salu_branch_wfid, f_decode_valid,
f_decode_wf_halt, f_vgpr_alu_wr_done, f_sgpr_alu_w... | miaow/src/verilog/rtl/issue/finished_wf.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.104 | false | false | 4,034 | -1 |
extern "C" int Initialize(int num_of_cu, int iter);
extern "C" int getTotalWavefronts();
extern "C" int ScheduleWavefront();
extern "C" void DescheduleWavefront(int cuid, int wfTag);
extern "C" int getCuId();
//extern "C" int getWgId();
//extern "C" int getWfId();
extern "C" int getWfTag();
extern "C" int getWfCnt();
... | miaow/src/verilog/tb/gpu_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.123 | false | false | 33,871 | -1 |
module regblock(
readdata,
clk,
rst,
readregsel,
writeregsel,
writedata,
write
);
parameter BITWIDTH = 11;
input clk, rst;
input [5:0] readregsel;
input [5:0] writeregsel;
input [(BITWIDTH-1):0] writedata;
input write;
output [(BITWIDTH-1):0] readdata;
wire write_dff;
wire [(BITWIDTH-1):0] data0,data... | miaow/src/verilog/rtl/fetch/regblock.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 9,301 | -1 |
module wfid_mux_8to1 (
wr_port_select,
wfid_done_0,
wfid_0,
wfid_done_1,
wfid_1,
wfid_done_2,
wfid_2,
wfid_done_3,
wfid_3,
wfid_done_4,
wfid_4,
wfid_done_5,
wfid_5,
wfid_done_6,
wfid_6,
wfid_done_7,
wfid_7,
muxed_wfid,
muxed_wfid_done
);
output [5:0] muxed_wfid;
output muxed_... | miaow/src/verilog/rtl/vgpr/wfid_mux_8to1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,381 | -1 |
module PS_flops_wavepool_decode (
wave_instr_pc,
wave_instr_valid,
wave_instr,
wave_wfid,
wave_vgpr_base,
wave_sgpr_base,
wave_lds_base,
flopped_instr_pc,
flopped_instr_valid,
flopped_instr,
flopped_wfid,
flopped_vgpr_base,
flopped_sgpr_base,
flopped_lds_base,
clk,
rst
);
input clk;
input rst;
input [... | miaow/src/verilog/rtl/decode/PS_flops_wavepool_decode.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,336 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../")
// End:
module inflight_wg_buffer_tb
(/*AUTOARG*/);
localparam WG_ID_WIDTH = 6;
localparam WG_SLOT_ID_WIDTH = 6;
localparam CU_ID_WIDTH = 2;
localparam VGPR_ID_WIDTH = 8;
localparam SGPR_ID_WIDTH = 8;
localparam LDS_ID_WI... | miaow/src/verilog/rtl/dispatcher/sim/inflight_wg_buffer/src/inflight_wg_buffer_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.077 | false | false | 12,969 | -1 |
module simf_alu
(
alu_source1_data,
alu_source2_data,
alu_source3_data, //TODO
alu_source_vcc_value,
alu_source_exec_value,
alu_control,
alu_start,
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_done,
clk,
rst
);
//TODO check overflow for signed and unsig... | miaow/src/verilog/rtl/simf/simf_alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.01 | false | false | 22,624 | -1 |
// -*- Mode: Verilog -*-
// Filename : vgpr_contention_tracker.v
// Description : Implements a contention tracker for the vgpr register file
// Author : Mario Paulo Drumond
// Created On : Sat Aug 31 21:57:26 2013
// Last Modified By: Mario Paulo Drumond
// Last Mod... | miaow/src/verilog/rtl/tracemon/vgpr_contention_tracker.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.076 | false | false | 9,285 | -1 |
module circular_barrel_shift (
output_val,
input_val,
shift_amt
);
output[39:0] output_val;
input[39:0] input_val;
input[5:0] shift_amt;
wire[39:0] shift_1, shift_2, shift_4, shift_8, shift_16;
assign shift_1 = shift_amt[0] ? (input_val >> 1 | input_val << 39) : input_val;
assign shift_2 = shift_amt[1] ? (shi... | miaow/src/verilog/rtl/common/circular_barrel_shift.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 675 | -1 |
`define SALU_SOPP_FORMAT 8'h01
`define SALU_SOP1_FORMAT 8'h02
`define SALU_SOPC_FORMAT 8'h04
`define SALU_SOP2_FORMAT 8'h08
`define SALU_SOPK_FORMAT 8'h10
module scalar_alu(
s1,
s2,
exec,
control,
scc,
b64_op,
out,
scc_val
);
integer i;
input[63:0] s1, s2, exec;
input[31:0] control;
i... | miaow/src/verilog/rtl/salu/scalar_alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.195 | false | false | 17,399 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../rtl/dispatcher" "../../src")
// End:
module dispatcher_hard (/*AUTOARG*/
// Outputs
dispatch2cu_wg_wf_count, dispatch2cu_wf_tag_dispatch,
dispatch2cu_wf_size_dispatch, dispatch2cu_wf_dispatch,
dispatch2cu_vgpr_base_dispatch, dispatch2cu_start_pc... | miaow/src/verilog/tb/dispatcher_wrapper/dispatcher_hard.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.141 | false | false | 8,723 | -1 |
module addr_calc_test;
wire[2047:0] out_addr;
reg[127:0] resource_buffer;
reg[2047:0] vreg_value;
reg[31:0] sreg_value;
reg[15:0] imm_value;
reg[15:0] opcode;
address_calculation adcal(out_addr, resource_buffer, vreg_value, sreg_value, imm_value, opcode);
initial
begin
// sbuff_load test
resource_buffer <= 128... | miaow/src/verilog/tb/lsu/addr_calc_test.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.194 | false | false | 728 | -1 |
module shift_in (
data_in,
wr_en,
shift_en,
data_out,
clk,
rst
);
parameter WIDTH=1;
input [(64*WIDTH)-1:0] data_in;
input wr_en;
input shift_en;
output [(16*WIDTH)-1:0] data_out;
input clk;
input rst;
wire [(64*WIDTH)-1:0] reg_in;
wire [(64*WIDTH)-1:0] reg_out;
reg line_wr_en;
reg s_or_w_;
always @ (shift_en... | miaow/src/verilog/rtl/alu/shift_in.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,506 | -1 |
module decode(
wave_instr_pc,
wave_instr_valid,
wave_instr,
wave_wfid,
wave_vgpr_base,
wave_sgpr_base,
wave_lds_base,
issue_wf_halt,
issue_fu,
issue_wfid,
issue_opcode,
issue_source_reg1,
issue_source_reg2,
issue_source_reg3,
iss... | miaow/src/verilog/rtl/decode/decode.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.07 | false | false | 13,643 | -1 |
module gpu_interface
(/*AUTOARG*/
// Outputs
gpu_interface_alloc_available, gpu_interface_dealloc_available,
gpu_interface_cu_id, gpu_interface_dealloc_wg_id,
dispatch2cu_wf_dispatch, dispatch2cu_wg_wf_count,
dispatch2cu_wf_size_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_vgpr_base_dispat... | miaow/src/verilog/rtl/dispatcher/gpu_interface.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.084 | false | false | 16,448 | -1 |
#include "asm.h"
operandValues opvals;
extern configValues configs;
int setSregSrc() {
int r = rand()%5;
if(r < 3) {
return rand() % configs.scalar_reg;
}
else {
switch(rand()%7) {
// vcc_hi or vcc_lo
case 0: return (106 + rand()%2);
// m0
... | miaow/src/sw/siagen/asm.cpp | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | cpp | false | 0.075 | false | false | 10,123 | -1 |
module spr_dependency_table
(/*AUTOARG*/
// Outputs
ready_arry_spr,
// Inputs
f_decode_wfid, f_exec_salu_wr_wfid, f_exec_valu_wr_vcc_wfid,
issued_wfid, f_decode_valid, f_decode_vcc_wr, f_decode_vcc_rd,
f_decode_scc_wr, f_decode_scc_rd, f_decode_exec_rd,
f_decode_exec_wr, f_decode_m0_rd, f_decode_m0... | miaow/src/verilog/rtl/issue/spr_dependency_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.13 | false | false | 9,999 | -1 |
module inflight_instr_counter
(/*AUTOARG*/
// Outputs
no_inflight_instr_flag, max_inflight_instr_flag,
// Inputs
clk, rst, retire_vgpr_1_en, retire_branch_en, retire_sgpr_en,
issued_en
);
// Inputs and outputs
input clk,rst, retire_vgpr_1_en,
retire_branch_en, retire_sgpr_en,
issued_en;
... | miaow/src/verilog/rtl/issue/inflight_instr_counter.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.2 | false | false | 2,031 | -1 |
module instr_collate (
in_wfid,
in_instr,
in_valid,
in_pc,
out_instr,
out_valid,
out_pc,
in_long,
out_long,
clk,
rst
);
input [5:0] in_wfid;
input [31:0] in_instr;
input in_valid;
input [31:0] in_pc;
output [63:0] out_instr;
output out_valid;
output [31:0] out_pc;
input in_long;
output out_long... | miaow/src/verilog/rtl/decode/instr_collate.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 924 | -1 |
module queue_controller (
q_vtail_incr,
q_rd,
q_wr,
q_reset,
q_empty,
stop_fetch,
buff_rd_addr,
buff_wr_addr,
buff_wr_en,
clk,
rst
);
input q_vtail_incr;
input q_rd;
input q_wr;
input q_reset;
output q_empty;
output stop_fetch;
output [2:0] buff_rd_addr;
output [2:0] buff_wr_addr;
output buff_wr... | miaow/src/verilog/rtl/wavepool/queue_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,546 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../" "../../src")
// End:
module gpu_interface_tb (/*AUTOARG*/) ;
localparam WG_ID_WIDTH = 15;
localparam NUMBER_WG_ID = 2**WG_ID_WIDTH;
localparam WF_COUNT_WIDTH = 4;
localparam MAX_WF_PER_WG = 2**WF_COUNT_WIDTH;
localparam WG_SLOT_... | miaow/src/verilog/rtl/dispatcher/sim/gpu_interface/src/gpu_interface_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.094 | false | false | 14,064 | -1 |
// add check for wg out of inflight wg buffer
module host_test (/*AUTOARG*/
// Outputs
host_wg_valid, host_wg_id, host_num_wf, host_vgpr_size_per_wf,
host_vgpr_size_total, host_sgpr_size_per_wf, host_sgpr_size_total,
host_lds_size_total, host_gds_size_total, host_wf_size,
host_start_pc, all_wf_dispatched... | miaow/src/verilog/rtl/dispatcher/sim/src/host_test.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.03 | false | false | 5,681 | -1 |
module lsu_opcode_decoder(
lsu_selected,
lsu_opcode,
issue_source_reg1,
issue_source_reg2,
issue_source_reg3,
issue_mem_sgpr,
sgpr_source1_rd_en,
sgpr_source2_rd_en,
sgpr_source1_addr,
sgpr_source2_addr,
vgpr_source2_rd_en,
vgpr_source1_addr,
vgpr_source2_a... | miaow/src/verilog/rtl/lsu/lsu_opcode_decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.091 | false | false | 8,656 | -1 |
module wavepool_tb;
//wires
reg clk;
reg rst;
reg fetch_reserve_valid, fetch_basereg_wr, buff2fetchwave_ack, issue_wf_done_en,
salu_branch_en, salu_branch_taken;
reg[5:0] fetch_reserve_slotid, fetch_basereg_wfid, issue_wf_done_wf_id,
salu_branch_wfid;
reg[8:0] fetch_sgpr_base;
reg[9... | miaow/src/verilog/tb/wavepool/wavepool_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.172 | false | false | 3,379 | -1 |
module mux_param (out, in, select);
parameter BITS = 2;
parameter SIZE = 4;
parameter WIDTH = 1;
output [WIDTH - 1:0] out;
input [(SIZE * WIDTH) - 1:0] in;
input [BITS - 1:0] select;
reg [WIDTH - 1:0] out;
integer i;
always @ (in or select)
begin
out = {WIDTH{1'bx}};
... | miaow/src/verilog/rtl/common/mux_param.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 520 | -1 |
module instruction_arbiter
(/*AUTOARG*/
// Outputs
simd0_alu_select, simd1_alu_select, simd2_alu_select,
simd3_alu_select, simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select, lsu_lsu_select,
salu_alu_select, lsu_wfid, alu_wfid, issued_wfid, alu_valid,
lsu_valid, issued_valid,
... | miaow/src/verilog/rtl/issue/instruction_arbiter.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.033 | false | false | 7,459 | -1 |
module memory_tb();
reg clk;
reg rst;
reg[3:0] rd_en, wr_en;
reg[6:0] input_tag;
reg[63:0] wr_mask;
reg[2047:0] addresses;
reg[8191:0] wr_data;
wire ack;
wire[6:0] output_tag;
wire[2047:0] tracemon_addr;
wire[8191:0] rd_data, tracemon_store_data;
memory mem(
rd_en,
wr_en,
addresses,
wr_data,... | miaow/src/verilog/tb/memory/memory_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.1 | false | false | 1,495 | -1 |
/*
* SIAGen: Random Program Generator
* Currently supports [scalar | vector] - [alu | memory] ops
* Only for a limitted set of opcodes
*
* To increase support for operations looks at the following fns:
* initialize[scalar|vector][alu|mem]ops
*
* To increse the formats of operations supported (in above mention... | miaow/src/sw/siagen/siagen.cpp | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | cpp | false | 0.169 | false | false | 12,004 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's 32x32 multiply for ASIC ////
//// ////
//// This file is part of the OpenR... | miaow/src/verilog/rtl/simd/amultp2_32x32.v#p0 | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.474 | false | false | 4,553 | -1 |
module circular_shift (
out,
in,
shift_amount
);
output[15:0] out;
input[15:0] in;
input[3:0] shift_amount;
wire[15:0] shift_1, shift_2, shift_4;
assign shift_1 = shift_amount[0] ? (in >> 1 | in << 15) : in;
assign shift_2 = shift_amount[1] ? (shift_1 >> 2 | shift_1 << 14) : shift_1;
assign shift_4 = sh... | miaow/src/verilog/rtl/rfa/circular_shift.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 462 | -1 |
module instr_buffer(
fetch_rd_en,
fetch_addr,
fetch_tag,
fetchwave_ack,
wave_instr,
wave_tag,
clk,
rst
);
parameter NUMOFCU = 1;
input clk;
input rst;
input [(NUMOFCU - 1):0] fetch_rd_en;
input [(NUMOFCU*32 - 1):0] fetch_addr;
input [(NUMOFCU*39 - 1):0] fetch_tag;
o... | miaow/src/verilog/rtl/instr_buffer/instr_buffer.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.111 | false | false | 1,453 | -1 |
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