text stringlengths 183 150k | path stringlengths 15 112 | bucket stringclasses 4
values | source stringclasses 14
values | group stringclasses 121
values | spdx stringclasses 11
values | repo_license stringclasses 11
values | commit stringclasses 13
values | lang stringclasses 4
values | def_heavy bool 1
class | comment_ratio float64 0 1 | restricted bool 2
classes | fresh bool 1
class | n_bytes int64 183 150k | n_tokens int64 -1 -1 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
module inflight_wg_buffer
(/*AUTOARG*/
// Outputs
inflight_wg_buffer_host_rcvd_ack, inflight_wg_buffer_host_wf_done,
inflight_wg_buffer_host_wf_done_wg_id,
inflight_wg_buffer_alloc_valid, inflight_wg_buffer_alloc_available,
inflight_wg_buffer_alloc_wg_id, inflight_wg_buffer_alloc_num_wf,
inflight_... | miaow/src/verilog/rtl/dispatcher/inflight_wg_buffer.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.108 | false | false | 25,468 | -1 |
module scbd_feeder(
valid_wf,
ins_half_reqd,
ins_half_wfid,
issue_vacant,
q_empty,
q_reset,
feed_valid,
feed_wfid,
clk,
rst
);
input [39:0] valid_wf;
input ins_half_reqd;
input [5:0] ins_half_wfid;
input [39:0] issue_vacant;
input [39:0] q_empty;
input [39:0] q_reset;
output feed_valid;
output [5... | miaow/src/verilog/rtl/wavepool/scbd_feeder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,098 | -1 |
module wave_queue (
q_vtail_incr,
q_rd,
q_wr,
q_reset,
q_empty,
stop_fetch,
instr_pc_in,
instr_pc_out,
clk,
rst
);
input q_vtail_incr;
input q_rd;
input q_wr;
input q_reset;
output q_empty;
output stop_fetch;
input [63:0] instr_pc_in;
output [63:0] instr_pc_out;
input clk;
input rst;
wire [2:0]... | miaow/src/verilog/rtl/wavepool/wave_queue.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 844 | -1 |
#ifndef MIAOW_SIAGEN_H
#define MIAOW_SIAGEN_H
#include <stdio.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <string>
#include "asm.h"
#include "helper.h"
#define MAX_INSTR 1000
#define MAX_OPS 50
#define INSTR_TYPES 4
#define SCALAR_ALU 0
#define VECTOR_ALU 1
#define SCALAR_MEM 2
#def... | miaow/src/sw/siagen/siagen.h | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | c | false | 0.5 | false | false | 874 | -1 |
module global_resource_table
(/*AUTOARG*/
// Outputs
grt_cam_up_valid, grt_cam_up_wg_count, grt_cam_up_cu_id,
grt_cam_up_vgpr_strt, grt_cam_up_vgpr_size, grt_cam_up_sgpr_strt,
grt_cam_up_sgpr_size, grt_cam_up_lds_strt, grt_cam_up_lds_size,
grt_cam_up_gds_strt, grt_cam_up_gds_size, grt_wg_alloc_done,
... | miaow/src/verilog/rtl/dispatcher/global_resource_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.138 | false | false | 26,303 | -1 |
module issue
(/*AUTOARG*/
// Outputs
salu_alu_select, simd0_alu_select, simd1_alu_select,
simd2_alu_select, simd3_alu_select, simf0_alu_select,
simf1_alu_select, simf2_alu_select, simf3_alu_select,
lsu_lsu_select, fetchwave_wf_done_en, tracemon_barrier_retire_en,
tracemon_waitcnt_retire_en, lsu_... | miaow/src/verilog/rtl/issue/issue.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.058 | false | false | 20,101 | -1 |
module reg_8x64b_1r_1w (
rd_addr,
rd_data,
wr_en,
wr_addr,
wr_data,
clk,
rst
);
output [63:0] rd_data;
input [2:0] rd_addr;
input [2:0] wr_addr;
input wr_en;
input [63:0] wr_data;
input clk;
input rst;
wire [511:0] word_out;
wire [7:0] wr_word_select;
wire [7:0] wr_en_word;
mu... | miaow/src/verilog/rtl/wavepool/reg_8x64b_1r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 627 | -1 |
extern "C" int checkWgAvailable();
extern "C" void prepareNextWg();
extern "C" int hardDisGetWgId();
extern "C" int hardDisGetWfCnt();
extern "C" int hardDisGetWfNumThrds();
extern "C" int hardDisGetVregSize();
extern "C" int hardDisGetVregSizePerWf();
extern "C" int hardDisGetSregSize() ;
extern "C" int hardDisGetS... | miaow/src/verilog/tb/dispatcher_wrapper/dispatcher_hard_host.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.045 | false | false | 4,861 | -1 |
module salu_tb();
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value;
reg[5:0] issue_wfid;
reg[11:0] issue_source_reg1, issue_source_reg2, issue_dest_reg;
reg[15:0] issue_imm_value;
reg[31:0] exec_rd_m0_value, issue_instr_pc, issue_opcode;
reg[63:0] sgpr_source2_data, sgpr_source1_data,
exec_rd_exec... | miaow/src/verilog/tb/salu/salu_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.078 | false | false | 6,761 | -1 |
module reg_40xX_2r_1w (
rd0_addr,
rd0_data,
rd1_addr,
rd1_data,
wr_en,
wr_addr,
wr_data,
clk,
rst
);
parameter WIDTH = 1;
output [WIDTH-1:0] rd0_data;
output [WIDTH-1:0] rd1_data;
input [5:0] rd0_addr;
input [5:0] rd1_addr;
input [5:0] wr_addr;
input wr_en;
input [WIDTH-1:0] wr_da... | miaow/src/verilog/rtl/common/reg_40xX_2r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 868 | -1 |
module reg_256x32b_3r_1w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data
);
input clk;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1... | miaow/src/verilog/rtl/fpga/reg_256x32b_3r_1w_fpga.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.119 | false | false | 2,014 | -1 |
module reg_40xX_1r_1w (
rd_addr,
rd_data,
wr_en,
wr_addr,
wr_data,
clk,
rst
);
parameter WIDTH = 1;
output [WIDTH-1:0] rd_data;
input [5:0] rd_addr;
input [5:0] wr_addr;
input wr_en;
input [WIDTH-1:0] wr_data;
input clk;
input rst;
wire [(40*WIDTH)-1:0] word_out;
wire [39:0] wr_w... | miaow/src/verilog/rtl/common/reg_40xX_1r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 688 | -1 |
module priority_encoder_40to6 (
binary_out,
valid,
encoder_in,
enable
);
output[5:0] binary_out;
output valid;
input[39:0] encoder_in;
input enable;
assign valid = (|encoder_in) & enable;
assign binary_out = (!enable) ? 6'd0 : (
(encoder_in[0]) ? 6'd0 :
(encoder_in[1]) ? 6'd1 :
(encoder_in[2]) ? 6'd2 : ... | miaow/src/verilog/rtl/common/priority_encoder_40to6.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,440 | -1 |
module mem_wait
(/*AUTOARG*/
// Outputs
mem_wait_arry,
// Inputs
clk, rst, lsu_valid, lsu_done,
lsu_wfid, lsu_done_wfid
);
input clk,rst;
input lsu_valid, lsu_done;
input [5:0] lsu_wfid, lsu_done_wfid;
output [`WF_PER_CU-1:0] mem_wait_arry;
wire [`WF_PER_CU-1:0] decoded_issue_value, decoded_lsu... | miaow/src/verilog/rtl/issue/mem_wait.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.053 | false | false | 947 | -1 |
module vgpr_busy_table_decoder
(
vgpr_addr,
vgpr_valid,
output_decoded
);
parameter MAX_NUMBER_WORDS = 4;
input[`VGPR_ADDR_LENGTH-1:0] vgpr_addr;
input [MAX_NUMBER_WORDS-1:0] vgpr_valid;
output [`NUMBER_VGPR-1:0] output_decoded;
wire [`NUMBER_VGPR+4-1:0] output_decoded_2;
... | miaow/src/verilog/rtl/issue/vgpr_busy_table_decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 548 | -1 |
module dispatcher_checker (/*AUTOARG*/
// Inputs
clk, rst, inflight_wg_buffer_host_rcvd_ack, host_wg_id,
host_num_wf, host_wf_size, host_vgpr_size_total,
host_sgpr_size_total, host_lds_size_total, host_gds_size_t... | miaow/src/verilog/rtl/dispatcher/sim/src/dispatcher_checker.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.046 | false | false | 22,151 | -1 |
module sgpr_simx_wr_port_mux (
wr_port_select,
port0_wr_en,
port0_wr_addr,
port0_wr_data,
port0_wr_mask,
port1_wr_en,
port1_wr_addr,
port1_wr_data,
port1_wr_mask,
port2_wr_en,
port2_wr_addr,
port2_wr_data,
port2_wr_mask,
port3_wr_en,
port3_wr_addr,
port3_wr_data,
port3_wr_mask,
... | miaow/src/verilog/rtl/sgpr/sgpr_simx_wr_port_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 4,844 | -1 |
module decoder(in,out);
input [5:0] in;
output [39:0] out;
reg [39:0]out;
always@(in)
begin
out = 40'd0;
case (in)
0: out[0]=1'b1;
1: out[1]=1'b1;
2: out[2]=1'b1;
3: out[3]=1'b1;
4: out[4]=1'b1;
5: out[5]=1'b1;
6: out[6]=1'b1;
7: out[7]=1'b1;
8: out[8]=1'b1;
9: out[9]=1'b1;
10: out[10]=1'b1;
11: out[11]=1'b1;
12: ou... | miaow/src/verilog/rtl/fetch/decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 840 | -1 |
module functional_unit_reg
(/*AUTOARG*/
// Outputs
rd_fu_simd, rd_fu_salu, rd_fu_lsu, rd_fu_simf,
// Inputs
clk, rst, wr_fu_en, wr_fu_value
);
input clk,rst;
input wr_fu_en;
input [1:0] wr_fu_value;
output rd_fu_simd, rd_fu_salu, rd_fu_lsu, rd_fu_simf;
reg [3:0] decoded_wr_fu_... | miaow/src/verilog/rtl/issue/functional_unit_reg.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.115 | false | false | 893 | -1 |
module instr_buffer_tb();
reg clk;
reg rst;
reg fetch_rd_en;
reg[31:0] fetch_addr;
reg[38:0] fetch_tag;
wire fetchwave_ack;
wire[31:0] wave_instr;
wire[38:0] wave_tag;
instr_buffer ibuf(fetch_rd_en, fetch_addr, fetch_tag, fetchwave_ack, wave_instr, wave_tag, clk, rst);
initial begin
clk = 0;
while (1) begin
... | miaow/src/verilog/tb/instr_buffer/instr_buffer_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.14 | false | false | 850 | -1 |
`timescale 1 ns / 1 ps
module compute_unit_fpga #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 11
)
(
... | miaow/src/verilog/rtl/fpga/compute_unit_fpga.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.14 | false | false | 44,776 | -1 |
#ifndef MIAOW_HELPER_H
#define MIAOW_HELPER_H
#include <stdio.h>
#include <stdlib.h>
#ifndef WIN32
#include <unistd.h>
#endif
#include <string.h>
#define MAX_IMM_VAL 50
// populate according to commandline values
// only one variable of this type
struct _configValues
{
int scalar_alu;
int vector_alu;
int scalar... | miaow/src/sw/siagen/helper.h | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | c | false | 0.316 | false | false | 836 | -1 |
module cam_allocator
(/*AUTOARG*/
// Outputs
res_search_out,
// Inputs
clk, rst, res_search_en, res_search_size, cam_wr_en, cam_wr_addr,
cam_wr_data
);
parameter CU_ID_WIDTH = 6;
parameter NUMBER_CU = 64;
parameter RES_ID_WIDTH = 10;
parameter NUMBER_RES_SLOTS = 1024;
// Search por... | miaow/src/verilog/rtl/dispatcher/cam_allocator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.121 | false | false | 1,713 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_addsub ////
//// ////
//// This file is part of the OpenR... | miaow/src/verilog/rtl/simf/fpu_addsub.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.426 | false | false | 4,787 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_addsub ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_post_norm_addsub.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.245 | false | false | 10,097 | -1 |
module PS_flops_EX_WB_alu (
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
in_sgpr_dest_addr,
in_instr_done,
in_vgpr_wr_en,
in_sgpr_wr_en,
in_vcc_wr_en,
out_wfid,
out_instr_pc,
out_vgpr_dest_addr,
out_sgpr_dest_addr,
out_instr_done,
out_vgpr_dest_wr_en,
out_sgpr_dest_wr_en,
out_vcc_wr_en,
clk,
rst
);
input... | miaow/src/verilog/rtl/alu/PS_flops_EX_WB_alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,453 | -1 |
module reg_256x32b_3r_1w
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data
);
input clk;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1_addr... | miaow/src/verilog/rtl/vgpr/reg_256x32b_3r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.101 | false | false | 2,029 | -1 |
module regfile(
d_in,
wr_en,
d_out,
clk,
rst
);
parameter BITWIDTH = 11;
input [BITWIDTH-1:0] d_in;
input wr_en, clk, rst;
output [BITWIDTH-1:0] d_out;
wire [BITWIDTH-1:0] out;
dff d1[BITWIDTH-1:0](.q(d_out), .d(out), .clk(clk), .rst(rst));
mux2_1 m1[BITWIDTH-1:0](.InA(d_out), .InB(d_in), .out(out), ... | miaow/src/verilog/rtl/common/regfile.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 344 | -1 |
module reg_40x35b_1r_1w (
rd_addr,
rd_data,
wr_en,
wr_addr,
wr_data,
clk,
rst
);
output [34:0] rd_data;
input [5:0] rd_addr;
input [5:0] wr_addr;
input wr_en;
input [34:0] wr_data;
input clk;
input rst;
wire [1399:0] word_out;
wire [39:0] wr_word_select;
wire [39:0] wr_en_word;
... | miaow/src/verilog/rtl/wavepool/reg_40x35b_1r_1w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 634 | -1 |
module wr_port_mux_9to1
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_mask, muxed_port_wr_addr,
muxed_port_wr_data,
// Inputs
wr_port_select, port0_wr_en, port0_wr_mask, port0_wr_addr,
port0_wr_data, port1_wr_en, port1_wr_mask, port1_wr_addr,
port1_wr_data, port2_wr_en, port2_wr_mask, ... | miaow/src/verilog/rtl/vgpr/wr_port_mux_9to1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.059 | false | false | 5,581 | -1 |
module sgpr_tb;
//wires and regs
reg clk;
reg rst;
reg lsu_instr_done, simd0_rd_en, simd1_rd_en, simd2_rd_en,
simd3_rd_en, simd0_wr_en, simd1_wr_en, simd2_wr_en, simd3_wr_en, simf0_rd_en,
simf1_rd_en, simf2_rd_en, simf3_rd_en, simf0_wr_en, simf1_wr_en, simf2_wr_en,
simf3_wr_en, salu_instr_d... | miaow/src/verilog/tb/sgpr/sgpr_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.134 | false | false | 7,177 | -1 |
module dff_en_fixed_reset_value (
out_value,
in_value,
reset_value,
en,
clk,
rst
);
output[5:0] out_value;
input[5:0] reset_value, in_value;
input en, clk, rst;
wire[5:0] dff_in_value;
assign dff_in_value = rst ? reset_value : in_value;
dff_en ff[5:0](out_value, dff_in_value, en, clk, 1'b0);
endmodule
| miaow/src/verilog/rtl/fetch/dff_en_fixed_reset_value.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 314 | -1 |
module vgpr_comparator
(/*AUTOARG*/
// Outputs
result,
// Inputs
retired_operand_mask, retired_operand_addr, src1_gpr_info,
src4_gpr_info, dst1_gpr_info, src2_gpr_info, src3_gpr_info,
dst2_gpr_info
);
wire src1_cmp_en, src2_cmp_en, src3_cmp_en, src4_cmp_en,
dst1_cmp_en, dst2_cmp_en;
... | miaow/src/verilog/rtl/issue/vgpr_comparator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.05 | false | false | 5,320 | -1 |
module reg_128x32b_3r_2w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr1_addr, wr0_en,
wr1_en, wr0_data, wr1_data
);
input clk;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [6:0] rd0_addr;
input [6... | miaow/src/verilog/rtl/fpga/reg_128x32b_3r_2w_fpga.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.103 | false | false | 2,328 | -1 |
//rd0 - 128bit, aligned (also supports unaligned)
//rd1 - 64bit, aligned (also supports unaligned)
//rd2 - 64bit, aligned (also supports unaligned)
//wr0 - 128/64/32bit (4 bit enable), aligned
//wr1 - 64/32bit (2 bit enable), aligned
module reg_512x32b_3r_2w
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_d... | miaow/src/verilog/rtl/sgpr/reg_512x32b_3r_2w.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.033 | false | false | 17,268 | -1 |
module BOOTHCODER_33_32 ( OPA, OPB, SUMMAND );
input [0:32] OPA;
input [0:31] OPB;
output [0:575] SUMMAND;
wire [0:32] INV_MULTIPLICAND;
wire [0:63] INT_MULTIPLIER;
wire LOGIC_ONE, LOGIC_ZERO;
assign LOGIC_ONE = 1;
assign LOGIC_ZERO = 0;
DECODER DEC_0 (.INA (LOGIC_ZERO) , .INB (OP... | miaow/src/verilog/rtl/simd/amultp2_32x32.v#p1 | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 148,551 | -1 |
module wavepool_controller (
buff_wfid,
buff_first,
buff_ack,
q_wr,
reserve_slotid,
reserve_valid,
q_vtail_incr,
halt_wfid,
wf_halt,
branch_wfid,
branch_en,
branch_taken,
q_reset,
feed_wfid,
feed_valid,
q_rd,
valid_wf,
decode_wfid,
decode_instr_valid,
clk,
rst
);
input [5:0] b... | miaow/src/verilog/rtl/wavepool/wavepool_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,939 | -1 |
module PS_flops_issue_alu (/*AUTOARG*/
// Outputs
out_alu_select, out_wfid, out_instr_pc, out_opcode, out_imm_value0,
out_imm_value1, out_dest1_addr, out_dest2_addr,
// Inputs
in_alu_select, in_wfid, in_instr_pc, in_opcode, in_imm_value0,
in_imm_value1, in_dest1_addr, in_dest2_addr, clk, rst
);
in... | miaow/src/verilog/rtl/alu/PS_flops_issue_alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.057 | false | false | 1,623 | -1 |
module resource_table
(/*AUTOARG*/
// Outputs
res_table_done, cam_biggest_space_size, cam_biggest_space_addr,
// Inputs
clk, rst, alloc_res_en, dealloc_res_en, alloc_cu_id, dealloc_cu_id,
alloc_wg_slot_id, dealloc_wg_slot_id, alloc_res_size,
alloc_res_start
);
parameter CU_ID_WIDTH = 1;
par... | miaow/src/verilog/rtl/dispatcher/resource_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.106 | false | false | 21,863 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../")
// End:
module global_resource_table_tb (/*AUTOARG*/) ;
localparam NUMBER_CU = 8;
localparam CU_ID_WIDTH = 3;
localparam WG_ID_WIDTH = 10;
localparam WF_ID_WIDTH = 15;
localparam WG_SLOT_ID_WIDTH = 6;
localparam NUMBER_WF_SLOTS = 40... | miaow/src/verilog/rtl/dispatcher/sim/global_resource_table/src/global_resource_table_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.085 | false | false | 9,143 | -1 |
module resource_update_buffer
(/*AUTOARG*/
// Outputs
res_table_waiting, serviced_cam_biggest_space_size,
serviced_cam_biggest_space_addr,
// Inputs
clk, rst, res_table_done, res_tbl_cam_biggest_space_size,
res_tbl_cam_biggest_space_addr, serviced_table
) ;
parameter RES_ID_WIDTH = 10;
p... | miaow/src/verilog/rtl/dispatcher/resource_update_buffer.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.113 | false | false | 4,785 | -1 |
module mask_gen(in,out);
input [5:0]in;
output [63:0]out;
assign out = (in == 6'd0) ? 64'h0000000000000001:
(in == 6'd1) ? 64'h0000000000000003:
(in == 6'd2) ? 64'h0000000000000007:
(in == 6'd3) ? 64'h000000000000000f:
(in == 6'd4) ? 64'h000000000000001f:
(in == 6'd5) ? 64'h00000000000000... | miaow/src/verilog/rtl/fetch/mask_gen.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 2,781 | -1 |
module barrier_wait
(/*AUTOARG*/
// Outputs
tracemon_barrier_retire_en, fetch_wg_wfid, barrier_wait_arry,
tracemon_barrier_retire_wf_bitmap, tracemon_barrier_retire_pc,
// Inputs
clk, rst, f_decode_valid, f_decode_barrier, f_decode_wfid,
f_decode_instr_pc, fetch_wg_wgid, fetch_wg_wf_count
);
/... | miaow/src/verilog/rtl/issue/barrier_wait.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.204 | false | false | 4,798 | -1 |
`define LSU_SMRD_FORMAT 8'h01
`define LSU_DS_FORMAT 8'h02
`define LSU_MTBUF_FORMAT 8'h04
`define LSU_SMRD_IMM_POS 23
`define LSU_DS_GDS_POS 23
`define LSU_MTBUF_IDXEN_POS 12
`define LSU_MTBUF_OFFEN_POS 11
module lsu_addr_calculator(
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_opcode,
in_l... | miaow/src/verilog/rtl/lsu/lsu_addr_calculator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.122 | false | false | 6,561 | -1 |
module mtbuf_addr_calc (
out_addr,
vector_source_b,
scalar_source_a,
scalar_source_b,
imm_value0,
idx_en,
off_en,
tid
);
output[31:0] out_addr;
input [31:0] vector_source_b;
input [127:0] scalar_source_a;
input [31:0] scalar_source_b;
input [15:0] imm_value0;
input idx_en;
input off_en;
input[5:0] ... | miaow/src/verilog/rtl/lsu/mtbuf_addr_calc.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.077 | false | false | 792 | -1 |
module regfile_clr(d_in,wr_en,d_out,clk,rst);
parameter BITWIDTH=11;
input [BITWIDTH-1:0]d_in;
output [BITWIDTH-1:0]d_out;
input wr_en,clk,rst;
wire [BITWIDTH-1:0]out;
dff_clr d1[BITWIDTH-1:0](.q(d_out), .d(out), .clk(clk), .rst(rst));
mux2_1 m1[BITWIDTH-1:0](.InA(d_out),.InB(d_in),.out(out... | miaow/src/verilog/rtl/fetch/regfile_clr.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 346 | -1 |
module sgpr_comparator
(/*AUTOARG*/
// Outputs
result,
// Inputs
retired_operand_mask, retired_operand_addr, src1_gpr_info,
src4_gpr_info, dst1_gpr_info, src2_gpr_info, src3_gpr_info,
dst2_gpr_info
);
wire src1_cmp_en, src2_cmp_en, src3_cmp_en, src4_cmp_en,
dst1_cmp_en, dst2_cmp_en;
... | miaow/src/verilog/rtl/issue/sgpr_comparator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.05 | false | false | 5,375 | -1 |
module allocator
(/*AUTOARG*/
// Outputs
allocator_cu_valid, allocator_cu_rejected, allocator_wg_id_out,
allocator_cu_id_out, allocator_wf_count, allocator_vgpr_size_out,
allocator_sgpr_size_out, allocator_lds_size_out,
allocator_gds_size_out, allocator_vgpr_start_out,
allocator_sgpr_start_out, allo... | miaow/src/verilog/rtl/dispatcher/allocator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.106 | false | false | 18,380 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../")
// End:
module allocator_tb();
localparam WG_ID_WIDTH = 8;
localparam CU_ID_WIDTH = 2;
localparam NUMBER_CU = 4;
localparam VGPR_ID_WIDTH = 8;
localparam NUMBER_VGPR_SLOTS = 256;
localparam SGPR_ID_WIDTH = 8;
localparam NUMBER_SG... | miaow/src/verilog/rtl/dispatcher/sim/allocator/src/allocator_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.123 | false | false | 9,239 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../")
// End:
module resource_table_tb ();
localparam CU_ID_WIDTH = 1;
localparam NUMBER_CU = 2;
localparam WG_SLOT_ID_WIDTH = 4;
localparam NUMBER_WG_SLOTS_PER_CU = 4;
localparam RES_ID_WIDTH = 4;
localparam NUMBER_RES_SLOTS = 16;... | miaow/src/verilog/rtl/dispatcher/sim/resource_table/src/resource_table_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.142 | false | false | 4,615 | -1 |
module alu_wb_queue(
in_rfa_queue_entry_serviced,
in_vgpr_dest_data,
in_sgpr_dest_data,
in_exec_wr_vcc_value,
in_vgpr_wr_mask,
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
... | miaow/src/verilog/rtl/alu/alu_wb_queue.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 3,881 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 FPU arith ////
//// ////
//// This file is part of the OpenR... | miaow/src/verilog/rtl/simf/fpu_arith.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.194 | false | false | 14,334 | -1 |
module rfa_tb;
reg clk;
reg rst;
reg simd0_queue_entry_valid, simd1_queue_entry_valid, simd2_queue_entry_valid,
simd3_queue_entry_valid, simf0_queue_entry_valid, simf1_queue_entry_valid,
simf2_queue_entry_valid, simf3_queue_entry_valid;
wire simd0_queue_entry_serviced, simd1_queue_entry_serviced, ... | miaow/src/verilog/tb/rfa/rfa_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.131 | false | false | 5,593 | -1 |
module circular_barrel_shift_9b(
output_val,
input_val,
shift_amt
);
output[8:0] output_val;
input[8:0] input_val;
input[3:0] shift_amt;
wire[8:0] shift_1, shift_2, shift_4, shift_8, shift_16;
assign shift_1 = shift_amt[0] ? (input_val >> 1 | input_val << 8) : input_val;
assign shift_2 = shift_amt[1]... | miaow/src/verilog/rtl/issue/circular_barrel_shift_5b.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 526 | -1 |
module flag_generator(
opcode,
fu,
wf_halt,
wf_barrier,
wf_branch,
wf_waitcnt,
scc_write,
scc_read,
vcc_write,
vcc_read,
exec_write,
exec_read,
M0_write,
M0_read,
s1_width,
s2_width,
s3_width,
s4_width,
dest1_width,
dest2_width,
fp_instr,
copy_d1_to_s4,
copy_d1_to_s3,
cop... | miaow/src/verilog/rtl/decode/flag_generator.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.128 | false | false | 60,929 | -1 |
module wr_port_mux_8to1 (
wr_port_select,
port0_wr_en,
port0_wr_mask,
port0_wr_addr,
port0_wr_data,
port1_wr_en,
port1_wr_mask,
port1_wr_addr,
port1_wr_data,
port2_wr_en,
port2_wr_mask,
port2_wr_addr,
port2_wr_data,
port3_wr_en,
port3_wr_mask,
port3_wr_addr,
port3_wr_data,
port4... | miaow/src/verilog/rtl/vgpr/wr_port_mux_8to1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 5,007 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_mul ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_post_norm_mul.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.17 | false | false | 16,266 | -1 |
module adder_param(
in1,
in2,
cin,
sum,
cout
);
parameter WIDTH = 32;
input cin;
input[WIDTH-1:0] in1,in2;
output[WIDTH-1:0] sum;
output cout;
wire[WIDTH-1:0] cout_adders;
adder1bit adders[WIDTH-1:0](
.sum(sum),
.cout(cout_adders),
.in1(in1),
.in2(in2),
.cin({cout_adders[WIDTH-2:0],cin})
);... | miaow/src/verilog/rtl/common/adder_param.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 369 | -1 |
`define VD 1'b1
`define IN 1'b0
module decode_core(
collated_instr,
collate_done,
collate_required,
fu,
opcode,
imm_value0,
imm_value1,
s1_field,
s2_field,
s3_field,
s4_field,
dest1_field,
dest2_field
);
input [63:0] collated_instr;
input collate_done;
output collate_required;
output [1:0] fu;
output [3... | miaow/src/verilog/rtl/decode/decode_core.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.063 | false | false | 14,283 | -1 |
/////////////////////////////////////////////////////////////////////
//// ////
//// fpu_intfloat_conv_except ////
//// ////
//// Author: Rudolf Usselmann ... | miaow/src/verilog/rtl/simf/fpu_intfloat_conv_except.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.249 | false | false | 7,034 | -1 |
module pc_block (
new_pc_init,
wf_id,
wr,
rd_en,
wf_id_rd,
pc_read2ibuff,
clk,
rst
);
parameter BITWIDTH = 32;
input [31:0] new_pc_init;
input [5:0] wf_id;
input wr;
input clk, rst;
input rd_en;
input [5:0] wf_id_rd;
output [32:0]pc_read2ibuff;
wire write;
wire [31:0] pc_read;
wire [32:0] data0, data... | miaow/src/verilog/rtl/fetch/pc_block.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 10,383 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_div ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_post_norm_div.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.217 | false | false | 10,500 | -1 |
module decoder_param_en (out, in, en);
parameter BITS = 2;
parameter SIZE = 4;
output [SIZE - 1:0] out;
input [BITS - 1:0] in;
input en;
reg [SIZE -1: 0] out;
integer i;
always @ (in or en)
begin
for(i = 0; i < SIZE; i = i + 1)
begin
out[i] = en ? ((in == ... | miaow/src/verilog/rtl/common/decoder_param_en.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 380 | -1 |
module simd_instr_decoder
(/*AUTOARG*/
// Outputs
out_vcc_wr_en, out_vgpr_wr_en, out_sgpr_wr_en,
// Inputs
in_opcode, in_sgpr_dest_addr
);
input [31:0] in_opcode;
input [11:0] in_sgpr_dest_addr;
output out_vcc_wr_en;
output out_vgpr_wr_en;
output out_sgpr_wr_en;
reg out_vcc_wr... | miaow/src/verilog/rtl/simd/simd_instr_decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.005 | false | false | 10,673 | -1 |
module flop (q, d, clk);
output q;
input d;
input clk;
reg state;
assign q = state;
always @(posedge clk)
begin
state <= d;
end
`ifdef dump_flops
always @(posedge gpu_tb.rst)
begin
if ($test$plusargs("dump_flops"))
begin
$... | miaow/src/verilog/rtl/common/flop.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 375 | -1 |
module fetch_tb();
reg dispatch2cu_wf_dispatch;
reg [14:0]dispatch2cu_wf_tag_dispatch;
reg [31:0]dispatch2cu_start_pc_dispatch;
reg [9:0]dispatch2cu_vgpr_base_dispatch;
reg [8:0]dispatch2cu_sgpr_base_dispatch;
reg [15:0]dispatch2cu_lds_base_dispatch;
reg [5:0]dispatch2cu_wf_size_disp... | miaow/src/verilog/tb/fetch/fetch_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.099 | false | false | 6,327 | -1 |
module fetch(
dispatch2cu_wf_dispatch,
dispatch2cu_wf_tag_dispatch,
dispatch2cu_start_pc_dispatch,
dispatch2cu_vgpr_base_dispatch,
dispatch2cu_sgpr_base_dispatch,
dispatch2cu_lds_base_dispatch,
dispatch2cu_wf_size_dispatch,
dispatch2cu_wg_wf_count,
buff_ack,
w... | miaow/src/verilog/rtl/fetch/fetch.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.034 | false | false | 4,833 | -1 |
module encoder(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1... | miaow/src/verilog/rtl/common/encoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,164 | -1 |
/////////////////////////////////////////////////////////////////////
//// ////
//// fpu_intfloat_conv ////
//// Only conversion between 32-bit integer and single ////
//// precision floating point format ... | miaow/src/verilog/rtl/simf/fpu_intfloat_conv.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.247 | false | false | 11,058 | -1 |
#ifndef __WAVE_H__
#define __WAVE_H__
// comment in release code
//#define __DEBUG_WAVE__
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#ifndef __DEBUG_WAVE__
#include "acc_user.h"
#include "vpi_user.h"
#endif
#defin... | miaow/src/verilog/tb/wave.h | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | c | false | 0.339 | false | false | 2,429 | -1 |
module dis_controller (/*AUTOARG*/
// Outputs
dis_controller_start_alloc, dis_controller_alloc_ack,
dis_controller_wg_alloc_valid, dis_controller_wg_dealloc_valid,
dis_controller_wg_rejected_valid, dis_controller_cu_busy,
// Inputs
clk, rst, inflight_wg_buffer_alloc_valid,
inflight_wg_buffer_alloc_... | miaow/src/verilog/rtl/dispatcher/dis_controller.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.1 | false | false | 6,290 | -1 |
module tracemon_tb();
reg[31:0] wave2decode_instr_pc;
reg[31:0] wave2decode_instr;
reg wave2decode_instr_valid;
reg[8:0] wave2decode_sgpr_base;
reg[9:0] wave2decode_vgpr_base;
reg[9:0] wave2decode_lds_base;
reg salu2exec_wr_exec_en;
reg[63:0] salu2exec_wr_exec_value;
reg salu2exec_wr_vcc_en;
reg[63:0] salu2exec_wr_v... | miaow/src/verilog/tb/tracemon/tracemon_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.068 | false | false | 5,247 | -1 |
// Local Variables:
// verilog-library-directories:("." "../../../" "../../src")
// End:
module dispatcher_tb (/*AUTOARG*/) ;
// Resource accounting localparams
localparam NUMBER_CU = 8;
localparam CU_ID_WIDTH = 3;
localparam WG_ID_WIDTH = 6;
localparam WG_SLOT_ID_WIDTH = 6;
localparam NUMBER_WF_SLO... | miaow/src/verilog/rtl/dispatcher/sim/dispatcher/src/dispatcher_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.111 | false | false | 15,915 | -1 |
/////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_intfloat_conv ////
//// Floating Point Post Normalisation Unit ////
//// ... | miaow/src/verilog/rtl/simf/fpu_post_norm_intfloat_conv.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.261 | false | false | 17,178 | -1 |
module decode_tb;
//wires
reg clk;
reg rst;
reg wave_instr_valid;
reg[5:0] wave_wfid;
reg[8:0] wave_sgpr_base;
reg[9:0] wave_vgpr_base;
reg[15:0] wave_lds_base;
reg[31:0] wave_instr_pc, wave_instr;
wire issue_wf_halt, issue_valid, issue_vcc_wr, issue_vcc_rd, issue_scc_wr,
issue_scc_rd, issue_exec_rd, i... | miaow/src/verilog/tb/decode/decode_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.228 | false | false | 5,031 | -1 |
module lsu_tb ();
reg clk;
reg rst;
reg issue_lsu_select, mem_ack;
reg[5:0] issue_wfid;
reg[6:0] mem2lsu_tag;
reg[7:0] issue_imm_value1;
reg[11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,issue_dest_reg, issue_mem_sgpr;
reg[15:0] issue_imm_value0, issue_opdcode;
reg[31:0] sgpr_source2_data, issue_instr_... | miaow/src/verilog/tb/lsu/lsu_tb.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.053 | false | false | 8,949 | -1 |
module vgpr(
simd0_source1_rd_en,
simd1_source1_rd_en,
simd2_source1_rd_en,
simd3_source1_rd_en,
simd0_source2_rd_en,
simd1_source2_rd_en,
simd2_source2_rd_en,
simd3_source2_rd_en,
simd0_source3_rd_en,
simd1_source3_rd_en,
simd2_source3_rd_en,
sim... | miaow/src/verilog/rtl/vgpr/vgpr.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.051 | false | false | 14,062 | -1 |
module vgpr_2to1_rd_port_mux (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port_rd_data,
rd_addr,
rd_data
);
// S: changed to 2k (parameter passed)
parameter DATAWIDTH = 2048;
input port0_rd_en;
input [9:0] port0_rd_addr;
input port1_rd_en;
input [9:0] port1_... | miaow/src/verilog/rtl/vgpr/vgpr_2to1_rd_port_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.024 | false | false | 908 | -1 |
module gds_resource_table (/*AUTOARG*/
// Outputs
gds_res_tbl_wg_gds_size,
// Inputs
rst, clk, gds_res_tbl_alloc_en, gds_res_tbl_dealloc_en,
gds_res_tbl_cu_id, gds_res_tbl_wg_id, gds_res_tbl_alloc_gds_size,
gds_res_tbl_inflight_res_tbl_id
) ;
parameter NUMBER_CU = 64;
parameter CU_ID_WIDTH =... | miaow/src/verilog/rtl/dispatcher/gds_resource_table.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.153 | false | false | 2,698 | -1 |
module dff (q, d, clk, rst);
output q;
input d;
input clk;
input rst;
reg state;
assign q = state;
always @(posedge clk)
begin
if (rst)
state <= 1'b0;
else
state <= d;
end
`ifdef dump_flops
always @(posedge gp... | miaow/src/verilog/rtl/common/dff.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 456 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_mul ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_mul.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.246 | false | false | 6,857 | -1 |
`define IDLE 3'b000
`define STATE_RD 3'b001
`define STATE_EX1 3'b010
`define STATE_EX2 3'b011
`define STATE_EX3 3'b100
`define STATE_EX4 3'b101
module alu_fsm (
in_alu_select,
out_alu_start,
in_valu_done,
out_alu_ready,
RD,
EX,
WB,
clk,
rst
);
input in_alu_select;
input in_valu_done;
output out_... | miaow/src/verilog/rtl/alu/alu_fsm.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 3,042 | -1 |
module sgpr_busy_table_mux
(
in,
select,
out
);
parameter MAX_NUMBER_WORDS = 4;
input[`NUMBER_SGPR-1:0] in;
wire [`NUMBER_SGPR+4-1:0] in_rotated;
input [`SGPR_ADDR_LENGTH-1:0] select;
output [MAX_NUMBER_WORDS-1:0] out;
assign in_rotated = {in[3:0],in};
assign out = in_rotated >>... | miaow/src/verilog/rtl/issue/sgpr_busy_table_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 339 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_div ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_div.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.244 | false | false | 5,963 | -1 |
module src_mux (
src_constant,
sgpr_rd_data,
vgpr_source_data,
exec_rd_exec_value,
exec_rd_vcc_value,
exec_rd_m0_value,
exec_rd_scc_value,
literal_constant,
source_mux_select,
source_data
);
input [9:0] src_constant;
input [31:0] sgpr_rd_data;
input [2047:0] vgpr_source_data;
input [63:0] exec_rd_exec_value;... | miaow/src/verilog/rtl/alu/src_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,457 | -1 |
module ram_2_port
(/*AUTOARG*/
// Outputs
rd_word,
// Inputs
rst, clk, wr_en, wr_addr, wr_word, rd_en, rd_addr
);
parameter WORD_SIZE = 16;
parameter ADDR_SIZE = 5;
parameter NUM_WORDS = 2**5;
input rst, clk;
input wr_en;
input [ADDR_SIZE-1 :0] wr_addr;
input [WORD_SIZE-1 :0]... | miaow/src/verilog/rtl/dispatcher/ram_2_port.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.065 | false | false | 752 | -1 |
module dest_shift_reg (
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_dest_exec_value,
dest_buffer_wr_en,
dest_buffer_shift_en,
vgpr_dest_data,
sgpr_dest_data,
exec_wr_vcc_value,
vgpr_wr_mask,
clk,
rst
);
input [511:0] alu_vgpr_dest_data;
input [15:0] alu_sgpr_dest_data;
input [15:0]... | miaow/src/verilog/rtl/alu/dest_shift_reg.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,372 | -1 |
module sgpr_busy_table_decoder
(
sgpr_addr,
sgpr_valid,
output_decoded
);
parameter MAX_NUMBER_WORDS = 4;
input[`SGPR_ADDR_LENGTH-1:0] sgpr_addr;
input [MAX_NUMBER_WORDS-1:0] sgpr_valid;
output [`NUMBER_SGPR-1:0] output_decoded;
wire [`NUMBER_SGPR+4-1:0] output_decoded_2;
assign output_dec... | miaow/src/verilog/rtl/issue/sgpr_busy_table_decoder.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 530 | -1 |
module valid_entry
(/*AUTOARG*/
// Outputs
valid_entry_out,
// Inputs
clk, rst, f_decode_valid, f_decode_wf_halt, f_decode_barrier,
f_salu_branch_en, f_salu_branch_taken, issued_valid,
f_decode_waitcnt, f_decode_wfid, issued_wfid, f_salu_branch_wfid
);
// Valid entry is set at decode and clea... | miaow/src/verilog/rtl/issue/valid_entry.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.064 | false | false | 1,651 | -1 |
module shift_out (
data_in,
wr_en,
shift_en,
data_out,
clk,
rst
);
parameter WIDTH=1;
input [(16*WIDTH)-1:0] data_in;
input wr_en;
input shift_en;
output [(64*WIDTH)-1:0] data_out;
input clk;
input rst;
wire [(64*WIDTH)-1:0] reg_in;
wire [3:0] line_wr_en;
assign reg_in[(WIDTH*16)-1:0] = data_out[(WIDTH*32)-1:... | miaow/src/verilog/rtl/alu/shift_out.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 727 | -1 |
#include "ut.hpp"
using namespace madd;
int
MADD::setupMADD()
{
cl_uint inputSizeBytes;
cl_uint input2SizeBytes;
// allocate and init memory used by host
inputSizeBytes = width * height * sizeof(cl_int);
input = (cl_int *) malloc(inputSizeBytes);
CHECK_ALLOCATION(input, "Failed to allocate ... | miaow/src/sw/miaow_unit_tests/common/ut.cpp | arch_code | miaow | miaow/src/sw | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | cpp | false | 0.103 | false | false | 16,998 | -1 |
module cu_handler (/*AUTOARG*/
// Outputs
dispatch2cu_wf_dispatch, dispatch2cu_wf_tag_dispatch,
wg_done_valid, wg_done_wg_id,
// Inputs
clk, rst, wg_alloc_en, wg_alloc_wg_id, wg_alloc_wf_count,
cu2dispatch_wf_done_i, cu2dispatch_wf_tag_done_i, wg_done_ack
) ;
parameter WF_COUNT_WIDTH = 4;
pa... | miaow/src/verilog/rtl/dispatcher/cu_handler.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.1 | false | false | 9,397 | -1 |
module sgpr_3to1_rd_port_mux (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port_rd_data,
rd_addr,
rd_data
);
input port0_rd_en;
input [8:0] port0_rd_addr;
input port1_rd_en;
input [8:0] port1_rd_addr;
input port2_rd_e... | miaow/src/verilog/rtl/sgpr/sgpr_3to1_rd_port_mux.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,054 | -1 |
/**
* alu_definitions.v
* File that contains all definitions used throughout alu
* stage
***/
`ifndef _alu_definitions_v_
`define _alu_definitions_v_
`define MODULE_SIMD 0
`define MODULE_SIMF 1
`define ALU_VOPC_FORMAT 8'h01
`define ALU_VOP1_FORMAT 8'h02
`define ALU_VOP2_FORMAT 8'h04
`define ALU_VOP3B_FORMAT 8'h0... | miaow/src/verilog/rtl/alu/alu_definitions.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.172 | false | false | 811 | -1 |
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_pre_norm_addsub ////
//// ////
//// This file is part of the OpenRISC 120... | miaow/src/verilog/rtl/simf/fpu_pre_norm_addsub.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.272 | false | false | 8,280 | -1 |
module branch_wait
(/*AUTOARG*/
// Outputs
pending_branches_arry,
// Inputs
clk, rst, alu_valid, alu_branch, alu_wfid, f_salu_branch_en,
f_salu_branch_wfid
);
input clk, rst;
// Issued alu info
input alu_valid, alu_branch;
input [`WF_ID_LENGTH-1:0] alu_wfid;
// Salu signals with ... | miaow/src/verilog/rtl/issue/branch_wait.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.226 | false | false | 1,671 | -1 |
module src_shift_reg (
source1_data,
source2_data,
source3_data,
source_vcc_value,
source_exec_value,
src_buffer_wr_en,
src_buffer_shift_en,
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
clk,
rst
);
input [2047:0] source1_data;
input [2047:0] source2_d... | miaow/src/verilog/rtl/alu/src_shift_reg.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 1,605 | -1 |
module simd_alu
(
alu_source1_data,
alu_source2_data,
alu_source3_data, //TODO
alu_source_vcc_value,
alu_source_exec_value,
alu_control,
alu_start,
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_done,
clk,
rst
);
//TODO check overflow for signed and unsig... | miaow/src/verilog/rtl/simd/simd_alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.029 | false | false | 26,664 | -1 |
module mux_2_to_1 (out, in, select);
parameter WIDTH = 1;
output [WIDTH-1:0] out;
input [(2*WIDTH)-1:0] in;
input select;
reg [WIDTH-1:0] out;
always @ (in or select) begin
casex(select)
1'b0: out <= in[WIDTH-1:0];
1'b1: out <= in[(2*WIDTH)-1:WIDTH];
default: out <= {WIDTH{1'bx}};
... | miaow/src/verilog/rtl/alu/mux_2_to_1.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0 | false | false | 347 | -1 |
module alu(
issue_source_reg1,
issue_source_reg2,
issue_source_reg3,
issue_dest_reg1,
issue_dest_reg2,
issue_imm_value0,
issue_imm_value1,
issue_opcode,
issue_wfid,
issue_alu_select,
vgpr_source1_dat... | miaow/src/verilog/rtl/alu/alu.v | arch_code | miaow | miaow/src/verilog | BSD-3-Clause | BSD-3-Clause | dbc5d7cc6e5fd58828239b59491eeb4f66503074 | other | false | 0.055 | false | false | 13,942 | -1 |
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