module_content stringlengths 18 1.05M |
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module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock... |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock... |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
/////////////////////////////////////////////////////////////////////////... |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output ... |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output... |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
out... |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
... |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb... |
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
o... |
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
outpu... |
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
outpu... |
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
out... |
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
out... |
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
ou... |
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
ou... |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire... |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire... |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
... |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
... |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
... |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
... |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side o... |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side o... |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side o... |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side o... |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else ... |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else ... |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else ... |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else ... |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else ... |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0... |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0... |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0... |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hdll__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31oi base (
... |
module sky130_fd_sc_hdll__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1... |
module synch_2 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk // clock to synchronize on
);
reg [WIDTH-1:0] stage_1;
always @(posedge clk)
{o, stage_1} <= {stage_1, i};
endmodule |
module synch_3 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk // clock to synchronize on
);
reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;
always @(posedge clk) ... |
module synch_3r #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk, // clock to synchronize on
output wire rise // one-cycle rising edge pulse
);
reg [WIDTH-1:0] stage_1;
reg [WIDT... |
module sky130_fd_sc_hs__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__d... |
module sky130_fd_sc_hs__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_... |
module outputs)
wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v
wire [PW-1:0] etx_packe... |
module multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
wire [WIDTH : 0] _a;
wire [WIDTH : 0] _b;
wire [2 * WIDTH - 1 : 0] _c;
assign _a = { {a[WIDTH - 1]}, {a[WIDTH - 1 :... |
module _multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
localparam M_WIDTH = WIDTH;
localparam P_WIDTH = 2 * M_WIDTH;
reg [P_WIDTH - 1 : 0] P [M_WIDTH : 0];
reg signed [M_WIDTH - 1... |
module Decodificador(
input [6:0] Cuenta,
output reg [7:0] catodo1,catodo2,catodo3,catodo4
);
always @(*)
begin
case (Cuenta)
6'd0: begin
catodo1 <= 8'b00000011;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
en... |
module bmu (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
// outputs
output [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
// inputs
input cx0, cx1;
// registers
reg [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
always@ (cx0 or cx1)
begin
if (cx0==0 && cx1==0)
begin
... |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
... |
module core_top(
input clk, rst, run_n,
input [3:0] reg_addr_d,
output [15:0] reg_out
);
//wire clk;
wire reg_we, sram_we_n, ram_wren;
wire [2:0] alu_operator;
wire [3:0] reg_addr_a, reg_addr_b, reg_addr_c;
wire [15:0] ram_addr, ram_data, reg_data_a, reg_data_b, reg_data_c, reg_data_d, alu_op_a,al... |
module sky130_fd_sc_ms__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd... |
module sky130_fd_sc_ms__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxbp ... |
module sky130_fd_sc_ls__xor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
... |
module sky130_fd_sc_ls__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
... |
module mig_7series_v2_0_ddr_phy_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter DQ_WIDTH = 64, // # of DQ (data)
paramet... |
module ThingMuxOH
#(
parameter NTHINGS = 1,
parameter M = 5 )
(
input logic [NTHINGS-1:0] select_oh,
the_intf.t things_in [NTHINGS-1:0],
the_intf.i thing_out
);
endmodule |
module Thinker
#(
parameter M = 5,
parameter N = 2)
(
input logic clk,
input logic reset,
input unique_id_t uids[0:N-1],
the_intf.t thing_inp,
the_intf.i thing_out
);
the_intf #(.M(M)) curr_things [N-1:0] ();
the_intf #(.M(M)) prev_things [N-1:0] ();
the_intf #(.M(M)) cur... |
module t
(
input logic clk,
input logic reset
);
localparam M = 5;
localparam N = 2;
unique_id_t uids[0:N-1];
the_intf #(.M(M)) thing_inp();
the_intf #(.M(M)) thing_out();
Thinker #(
.M ( M ),
.N ( N ))
thinker(
.clk ( clk ),
.... |
module testbench();
reg tb_clk;
reg SCK;
reg MOSI;
reg SSEL;
wire MISO;
wire [7:0] MSG;
spi_slave spi1(.CLK(tb_clk),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting te... |
module zynq_design_1_xbar_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
(\s_axi_arready[0] ,
aa_mi_arvalid,
D,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
s_axi_rlast_i0,
\m_axi_arqos[7] ,
E,
\gen_axi.s_axi_rid_i_reg[11] ,
\gen_no_arbiter.m_valid_i_reg_0 ,
\gen_no_arbiter.s_ready_i_reg[0]_... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
(ss_aa_awready,
aa_sa_awvalid,
\m_ready_d_reg[0] ,
\m_ready_d_reg[1] ,
aa_mi_awtarget_hot,
D,
\gen_master_slots[1].w_issuing_cnt_reg[9] ,
\gen_master_slots[0].w_issuing_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
D,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
\chosen_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
SR,
E,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
(D,
\gen_multi_thread.accept_cnt_reg[2] ,
E,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
(S_AXI_ARREADY,
Q,
\m_axi_arqos[7] ,
m_axi_bready,
M_AXI_RREADY,
m_axi_awvalid,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_awready,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
m_... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
(mi_awready_2,
p_14_in,
p_21_in,
p_15_in,
p_17_in,
\gen_axi.write_cs_reg[1]_0 ,
mi_arready_2,
\gen_axi.s_axi_arready_i_reg_0 ,
Q,
\skid_buffer_reg[46] ,
SR,
aclk,
aa_mi_awtarget_hot,
aa_sa_awvalid,
m... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_multi_thread.accept_cnt_reg[2]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_artarget_hot,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ,
\gen_multi_thread.gen... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
chosen,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_awtarget_enc,
D,
SR,
\gen_multi_thread.gen_thread_loop[7].act... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
(s_axi_awready,
m_ready_d,
\gen_multi_thread.accept_cnt_reg[3] ,
ss_wr_awvalid,
ss_aa_awready,
ss_wr_awready,
s_axi_awvalid,
aresetn_d,
aclk);
output [0:0]s_axi_awready;
output [1:0]m_ready_d;
output \gen_multi_thread.acc... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
(m_ready_d,
aa_sa_awvalid,
aresetn_d,
\m_ready_d_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[1] ,
aa_mi_awtarget_hot,
\m_ready_d_reg[0]_1 ,
aclk);
output [1:0]m_ready_d;
input aa_sa_awvalid;
input aresetn_d;
input \m_re... |
module zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
(ss_wr_awready,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlas... |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
(s_ready_i_reg_0,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_... |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0
(\storage_data1_reg[0] ,
push,
st_aa_awtarget_enc,
fifoaddr,
aclk);
output \storage_data1_reg[0] ;
input push;
input [0:0]st_aa_awtarget_enc;
input [2:0]fifoaddr;
input aclk;
wire aclk;
wire [2:0]fifoaddr;
wi... |
module zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4
(push,
\storage_data1_reg[1] ,
s_ready_i_reg,
\gen_rep[0].fifoaddr_reg[0] ,
D,
fifoaddr,
aclk,
st_aa_awtarget_enc,
st_aa_awtarget_hot,
out0,
load_s1,
\storage_data1_reg[1]_0 ,
s_ready_i_reg_0... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
(p_80_out,
m_axi_bready,
p_74_out,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_th... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
(p_60_out,
m_axi_bready,
p_1_in,
p_54_out,
\m_axi_rready[1] ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
(p_38_out,
m_valid_i_reg,
mi_bready_2,
p_32_out,
mi_rready_2,
s_ready_i_reg,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
Q,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(\m_payload_i_reg[2]_0 ,
m_valid_i_reg_0,
mi_bready_2,
s_ready_i_reg_0,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
p_1_in,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\ge... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(m_valid_i_reg_0,
\skid_buffer_reg[34]_0 ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
\aresetn_d_reg[1] ,
a... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7
(s_ready_i_reg_0,
\m_axi_rready[1] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
... |
module zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9
(m_valid_i_reg_0,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_T... |
module sky130_fd_sc_lp__inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
param... |
module lsu_addr_calculator(
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_opcode,
in_lds_base,
in_imm_value0,
out_ld_st_addr,
out_gm_or_lds
);
input [2047:0] in_vector_source_b;
input [127:0] in_scalar_source_a;
input [31:0] in_scalar_source_b;
input [31:0] in_opcode;
input [15:0] in_l... |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram7 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
... |
module sky130_fd_sc_hdll__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module affine_block_ieee754_fp_multiplier_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule |
module or1200_genpc(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_rty_i, icpu_adr_i,
// Internal i/f
branch_op, except_type, except_prefix,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, ge... |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ... |
module custom(
input RESET,
input CLK,
input [2:0] COL,
output [3:0] ROW,
output OPEN,
output [255:0] W,
output [7:0] DEBUG
);
nand(OPEN,W[240],W[242]);
nand(ROW[0],W[9],W[9]);
nand(ROW[1],W[8],W[8]);
nand(ROW[2],W[6],W[6]);
nand(ROW[3],W[2],W[2]);
nand(W[0],CLK,CLK);
nand(W[1],W[0],W[0]);
... |
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module alink_slave(
// system clock and reset
input clk ,
input rst ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_... |
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