module_content stringlengths 18 1.05M |
|---|
module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i or negedge rst_i)
//always @(posedge wb_clk_i)//Bob: Here the... |
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule |
module xilinx_v6_pcie_wrapper
(
// Outputs
trn_terr_drop_n, trn_tdst_rdy_n, trn_tcfg_req_n, trn_tbuf_av,
trn_rsrc_rdy_n, trn_rsrc_dsc_n, trn_rsof_n, trn_rrem_n,
trn_reset_n, trn_rerrfwd_n, trn_reof_n, trn_rd, trn_rbar_hit_n,
trn_lnk_up_n, trn_fc_ph, trn_fc_pd, trn_fc_nph, trn_fc_npd,
trn_fc_cplh... |
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg ... |
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
... |
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1... |
module CPU
(
clk_i,
rst_i,
start_i,
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o
);
//input
input clk_i;
input rst_i;
input start_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_... |
module hps_design_SMP_HPS_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_... |
module fifo_four(clk,rstp,din,readp,writep,dout,emptyp,fullp);
input clk; //时钟
input rstp; //复位
input[15:0]din; //16位输入信号
input readp; //读指令
input writep; //写指令
output[15:0]dout; //16位输出信号
output emptyp; ... |
module regs_testbench();
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// indica o numero de testes a serem feitos
parameter N_TESTES = 11;
// contador de testes a serem feitos
integer testes;
// declaracao input / output
reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, ... |
module mig_7series_v2_0_qdr_rld_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, ... |
module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o;
output done;
reg [197:0]... |
module BCD7segment(
input [3:0] IN,
input select,
output reg [6:0] OUT
);
always @ (IN or select)
begin
if(select)
begin
case (IN)
0: OUT = 7'b0000001;
1: OUT = 7'b1001111;
2: OUT = 7'b0010010;
3: OUT = 7'b0000110;
4: OUT = 7'b1001100;
5: OUT = 7'b0100100;
6: OUT = 7'b0100000;
7: O... |
module gtwizard_ultrascale_v1_7_1_gtye4_delay_powergood # (
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
parameter C_PCIE_ENABLE = "FALSE"
)(
input wire GT_TXOUTCLKPCS,
input wire GT_GTPOWERGOOD,
input wire [2:0] USER_TXRATE,
input wire USER_TXRATEMODE,
input wire USER_GTTXRESET,
input wire USE... |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
... |
module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module log2_table
(
input clk, // Drawing engine clock.
input trilinear_en, // Trilinear Enable.
input [31:0] val, // Current Largest delta 23.9.
output [9:0] log2
);
reg [3:0] int_mm_no;
reg [5:0] lod_fract;
wire over_flow;
wire [9:0] log_in;
// assign log_in = val[26:17];
// assign o... |
module EtherPBI(
inout tri [15:0] SysAddr,
input wire Phi2,
output tri MPD,
inout tri RdWr,
output wire OE,
output wire RamCS,
output wire RomCS,
output wire [13:8] RamAddrOut,
output wire [15:10] RomAddrOut,
inout tri [7:0] Data,
inout tri Dx,
output tri IRQ,
output ... |
module sky130_fd_sc_ls__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
... |
module sky130_fd_sc_ls__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
... |
module TBCTRL_2 (
input HRESETn,
input HCLK,
// input
input HREADYin,
input HREADYout,
input HWRITEin,
input HWRITEout,
input HSEL,
//input [3:0] HMASTER,
input HGRANT,
// Output
output MAPSn,
output MDPSn,
output DENn,
output SDPSn,
output SRSn
);
// Master
wire MasterReadData;
wire Slave... |
module system_xlconstant_0_0
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module upd77c25_datram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [10:0] address_b;
input clock;
input [15:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QI... |
module sensor_interface_v1_0 #
(
// Users to add parameters here
parameter integer C_SYSTEM_CLOCK = 100_000_000,
parameter integer C_BUS_CLOCK = 400_000,
// User parameters ends
// THESE AREN'T USER CONFIGURABLE
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_D... |
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
out... |
module LCD(
input clk,
input rst,
input [127:0] row_A,
input [127:0] row_B,
output LCD_E,
output LCD_RS,
output LCD_RW,
output [3:0] LCD_D
);
reg lcd_inited;
reg [3:0] init_d,icode,tcode,text_d;
reg init_rs,init_rw,init_e;
reg text_rs,text_rw,text_e;
reg [23:0]in... |
module clock_divider(
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 8_000;
reg [63:0] count;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
count <= 32'd0;
else if (count == (constantNumber - 32'd1))
... |
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// TX clock
output tx_clk_o,
// JTAG ... |
module sky130_fd_sc_lp__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR... |
module sky130_fd_sc_lp__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule |
module sky130_fd_sc_hdll__inv_12 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VP... |
module sky130_fd_sc_hdll__inv_12 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule |
module testbench;
`include "test_management.v"
reg [31:0] read_word;
wire TX;
wire RX;
wire wb_clk = clk;
wire wb_rst = reset;
soc_template dut(
// Outputs
.uart_tx(TX),
// Inputs
.clk_sys... |
module pcie3_7x_0_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_... |
module mux4to1_beh_1_tb;
// Inputs
reg [3:0] data_in;
reg [1:0] ctrl_sel;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
mux4to1_beh_1 uut (
.data_in(data_in),
.ctrl_sel(ctrl_sel),
.data_out(data_out)
);
task expect;
input exp_out;
if (data... |
module sky130_fd_sc_hs__or2_4 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule |
module GeAr_N16_R2_P4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_26_CI, intadd_26_n4, intadd_26_n3, intadd_26_n2, intadd_26_n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27,... |
module sky130_fd_sc_ls__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out... |
module TDP18K_FIFO (
RMODE_A,
RMODE_B,
WMODE_A,
WMODE_B,
WEN_A,
WEN_B,
REN_A,
REN_B,
CLK_A,
CLK_B,
BE_A,
BE_B,
ADDR_A,
ADDR_B,
WDATA_A,
WDATA_B,
RDATA_A,
RDATA_B,
EMPTY,
EPO,
EWM,
UNDERRUN,
FULL,
FMO,
FWM,
OVERRUN,
FLUSH,
RAM_ID,
FMODE,
PL_INIT,
PL_ENA,
PL_WEN,
PL_REN,
PL_CLK,
PL_ADDR... |
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
... |
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll... |
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q... |
module sky130_fd_sc_lp__dlybuf4s50kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
... |
module sparc_exu_ecl_cnt6 (/*AUTOARG*/
// Outputs
cntr,
// Inputs
reset, clk, se
) ;
input reset;
input clk;
input se;
output [5:0] cntr;
wire [5:0] next_cntr;
wire tog1;
wire tog2;
wire tog3;
wire tog4;
wire tog5;
assign ... |
module ay_note_ram(addr, data);
input wire [6:0] addr;
output wire [11:0] data; //12 бит - максимум
reg [11:0] note_ram [0:127];
initial begin
note_ram[0] <= 12'd03977;
note_ram[1] <= 12'd03977;
note_ram[2] <= 12'd03977;
note_ram[3] <= 12'd03977;
note_ram[4] <= 12'd03977;
note_ram[5] <= 12'd03977;
note_ra... |
module system_auto_us_1
(s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_ax... |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
(rd_cmd_valid,
CO,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ,
E,
D,
\current_word_1_reg[3] ,
Q,
first_word_reg,
firs... |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
(m_axi_arlen,
m_axi_rready,
s_axi_rlast,
Q,
s_axi_arready,
s_axi_rdata,
s_axi_rvalid,
m_axi_arvalid,
s_axi_rresp,
m_axi_arsize,
m_axi_arburst,
m_axi_araddr,
s_axi_rready,
out,
m_axi_rlast,
m_a... |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
(first_mi_word_q,
\M_AXI_RDATA_I_reg[0]_0 ,
first_word,
s_axi_rlast,
use_wrap_buffer,
wrap_buffer_available,
\pre_next_word_1_reg[3]_0 ,
\current_word_1_reg[3]_0 ,
\pre_next_word_1_reg[3]_1 ,
wrap_buffer_available_reg_... |
module system_auto_us_1_axi_dwidth_converter_v2_1_11_top
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_... |
module system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
(m_axi_rready,
mr_rvalid,
\s_axi_rdata[0] ,
Q,
\s_axi_rdata[1] ,
\s_axi_rdata[2] ,
\s_axi_rdata[3] ,
\s_axi_rdata[4] ,
\s_axi_rdata[5] ,
\s_axi_rdata[6] ,
\s_axi_rdata[7] ,
\s_axi_rdata[8] ,
\s_axi_r... |
module system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0
(\aresetn_d_reg[1] ,
s_ready_i_reg,
sr_arvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
s_axi_arready,
Q,
m_axi_arsize,
in,
m_axi_arburst,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MES... |
module system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
(\aresetn_d_reg[1]_0 ,
s_ready_i_reg_0,
sr_arvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31] ,
s_axi_arready,
Q,
m_axi_arsize,
in,
m_axi_arburst,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]... |
module system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
(m_axi_rready,
mr_rvalid,
\s_axi_rdata[0] ,
Q,
\s_axi_rdata[1] ,
\s_axi_rdata[2] ,
\s_axi_rdata[3] ,
\s_axi_rdata[4] ,
\s_axi_rdata[5] ,
\s_axi_rdata[6] ,
\s_axi_rdata[7] ,
\s_axi_rdata[... |
module system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
(\M_AXI_RDATA_I_reg[127] ,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ,
E,
D,
\current_word_1_reg[3] ,
Q,
first_word_reg,
first_word_reg_0,
\s_axi_rdata[31] ,
\s_axi_rdata[3... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module encoder(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
... |
module fifo_tx(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input rst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.... |
module soc_system_key_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
... |
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
... |
module ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
a... |
module sky130_fd_sc_ms__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
... |
module sky130_fd_sc_ms__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
... |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.r... |
module NIOS_SYSTEMV3_RAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_r... |
module sky130_fd_sc_hs__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sirv_qspi_4cs(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
in... |
module sky130_fd_sc_ls__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodu... |
module basic_rom (address, instruction, enable, rdl, clk);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "7S";
parameter integer C_RAM_SIZE_KWORDS = 1;
//
input clk;
input [11:0] address; ... |
module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "V6";
parameter integer C_NUM_PICOBLAZE = 1;
p... |
module sky130_fd_sc_ms__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule |
module win_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys ... |
module uart_v3 #(
parameter DEFAULT_BAUDRATE = 115200,
parameter STOP_BITS = 1
)(
input clk,
input rst,
output reg tx,
input transmit,
input [7:0] tx_byte,
output is_transmitting,
input rx,
output reg ... |
module axis_switch #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal wi... |
module blk_mem_gen_inputMem(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [16 : 0] addra;
input [7 : 0] dina;
input clkb;
input [16 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
... |
module primogen #(
parameter WIDTH_LOG = 4
) (clk, go, rst, ready, error, res);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
output reg ready;
output reg error;
output reg [HI:0] res;
localparam MAX = {WIDTH{1'b1}};
// Note that incrementing address width
// by 1 b... |
module rf_2p_be (
clka ,
cena_i ,
addra_i ,
dataa_o ,
clkb ,
cenb_i ,
wenb_i ,
addrb_i ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION ... |
module zap_core #(
// Number of branch predictor entries.
parameter [31:0] BP_ENTRIES = 1024,
// Depth of FIFO.
parameter [31:0] FIFO_DEPTH = 4
)
(
// ------------------------------------------------
// Clock and reset. Reset is synchronous.
// ----------------------------------------... |
module's pkt waiting for transmit
input exe2disp_data_wr,
input [133:0] exe2disp_data,
input exe2disp_valid_wr,
input exe2disp_valid,
output reg disp2exe_alf,
//execute's tranmit direction request
input exe2disp_direction_req,
input exe2disp_direction,//0:up cpu 1: down port
//tra... |
module oh_memory
#(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter TYPE = "soft", // hard=hard macro,soft=synth... |
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB... |
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clo... |
module sky130_fd_sc_hvl__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module system_microblaze_0_xlconcat_0(In0, In1, In2, In3, In4, In5, In6, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],dout[6:0]" */;
input [0:0]In0;
input [0:0]In1;
input [0:0]In2;
input [0:0]In3;
input [0:0]In4;
input [0:0]In5;
input [... |
module sky130_fd_sc_ms__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hd__lpflow_decapkapwr (
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module pcie3_7x_0_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, ... |
module Platform (
clk_clk,
dds_left_strobe_export,
dds_right_strobe_export,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_... |
module sky130_fd_sc_ls__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Judge_Test;
// Inputs
reg kind;
reg [15:0] data_in;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
Condition_Judge uut (
.data_out(data_out),
.kind(kind),
.data_in(data_in)
);
initial begin
// Initialize Inputs
kind = 0;
data_in = 0;
// Wait 100 ns for global res... |
module pcx2mb_sm (
// Outputs
load_data,
shift_data,
entry1_active,
pcx_fsl_m_control,
pcx_fsl_m_write,
pcx_spc_grant_px,
// Inputs
rclk,
reset_l,
any_req_pq,
any_req_pa,
spc_pcx_atom_pq,
entry1_dest,
entry2_active,
entry2_atom,
fsl_pcx_m_full
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH... |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Loca... |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Loca... |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Loca... |
module lpm_ff_v1 (
clock,
data,
q);
input clock;
input [63:0] data;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_ff lpm_ff_component (
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload ... |
module sky130_fd_sc_hdll__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module axi_ad9152_channel (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// paramete... |
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule |
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