module_content stringlengths 18 1.05M |
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module OXIDE_COMB(
input A, B, C, D, // LUT inputs
input SEL, // mux select input
input F1, // output from LUT 1 for mux
input FCI, // carry input
input WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs
input WD, // LUTRAM write data input
input WCK, WRE, // LUTRAM write clock and enable
output F, // LUT/c... |
module DPR16X4(
input [3:0] RAD, DI, WAD,
input WRE, WCK,
output [3:0] DO
);
parameter INITVAL = "0x0000000000000000";
`include "parse_init.vh"
localparam [63:0] parsed_init = parse_init_64(INITVAL);
reg [3:0] mem[0:15];
integer i;
initial begin
for (i = 0; i < 15; i++)
mem[i] = parsed_init[i * 4 +: 4];
... |
module OXIDE_DSP_REG #(
parameter W = 18,
parameter USED = "REGISTER",
parameter RESETMODE = "SYNC"
) (
input CLK, CE, RST,
input [W-1:0] D,
output reg [W-1:0] Q
);
generate
if (USED == "BYPASS")
always @* Q = D;
else if (USED == "REGISTER") begin
initial Q = 0;
if (RESETMODE == "ASYNC")
always ... |
module OXIDE_DSP_SIM #(
// User facing parameters
parameter REGINPUTA = "BYPASS",
parameter REGINPUTB = "BYPASS",
parameter REGINPUTC = "BYPASS",
parameter REGADDSUB = "BYPASS",
parameter REGLOADC = "BYPASS",
parameter REGLOADC2 = "BYPASS",
parameter REGCIN = "BYPASS",
parameter REGPIPELINE = "BYPASS",
parame... |
module MULT9X9 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [8:0] A,
input [8:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
input RS... |
module MULT18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [17:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
inpu... |
module MULT18X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [35:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
inpu... |
module MULT36X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [35:0] A,
input [35:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
inpu... |
module MULTPREADD9X9 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [8:0] A,
input [8:0] B,
input [8:0] C,
input CLK,
input CEA,
input RSTA,
input CE... |
module MULTPREADD18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [17:0] B,
input [17:0] C,
input CLK,
input CEA,
input RSTA,
inp... |
module MULTADDSUB18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGADDSUB = "REGISTER",
parameter REGLOADC = "REGISTER",
parameter REGLOADC2 = "REGISTER",
parameter REGCIN = "REGISTER",
parameter REGPIPELINE = "REGISTER",
parameter REGOU... |
module MULTADDSUB36X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGADDSUB = "REGISTER",
parameter REGLOADC = "REGISTER",
parameter REGLOADC2 = "REGISTER",
parameter REGCIN = "REGISTER",
parameter REGPIPELINE = "REGISTER",
parameter REGOU... |
module arb_test();
reg clk, reset_n, wreq, fifo_full;
reg [7:0] memadrs, memdata;
wire [7:0] synth_ctrl, synth_data;
reg [7:0] test_state;
reg [7:0] wait_cnt;
synth_arb arb1(
.clk(clk),
.reset_n(reset_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wreq),
.s... |
module shiftll (busSLL, busA, sel, zSLL, oSLL, cSLL, nSLL);
output [31:0] busSLL;
input [31:0] busA, sel;
output zSLL, nSLL;
output reg oSLL, cSLL;
assign busSLL = busA << sel[2:0];
assign zSLL = ~|busSLL[31:0];
assign nSLL = busSLL[31];
always @(*) begin
if (sel[2:0] == 3'b0) begin
... |
module player1 (
address,
clock,
q);
input [10:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_compo... |
module sky130_fd_sc_ms__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_s... |
module sky130_fd_sc_ms__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32a base (
.... |
module sky130_fd_sc_ms__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
... |
module sky130_fd_sc_ms__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
... |
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply... |
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 ... |
module sky130_fd_sc_hs__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
... |
module axi_register_slice #(
parameter DATA_WIDTH = 32,
parameter FORWARD_REGISTERED = 0,
parameter BACKWARD_REGISTERED = 0)(
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_... |
module lpf_tb;
// inputs
reg clk;
reg reset_n;
wire clken;
reg[31:0] in_data;
wire[31:0] out_data;
wire[1:0] in_error;
wire[1:0] out_error;
reg in_valid;
wire out_ready;
wire in_ready;
wire out_valid;
reg start;
reg end_test;
integer data_in_int,data_file_in,data_file_out;
... |
module sky130_fd_sc_lp__or4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(... |
module sky130_fd_sc_lp__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),... |
module control (
input [5:0] op,
output [1:0] alu_op,
output regDst, aluSrc, memToReg, regWrite,
output memRead, memWrite, branch
);
wire int0, op0_bar, op1_bar, op2_bar, op3_bar, op4_bar, op5_bar;
not (op0_bar, op[0]);
not (op1_bar, op[1]);
not (op2_bar, op[2]);
not (op3_bar, op[3]);
not (op4_bar, ... |
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X,... |
module RCA_N20 ( in1, in2, res );
input [19:0] in1;
input [19:0] in2;
output [20:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n... |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s... |
module protection_sim;
reg [3:0] a, b;
wire [7:0] c;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvar... |
module pfengine_wp (
input clk
,input reset
,input logic pfgtopfe_op_valid
,output logic pfgtopfe_op_retry
,input PF_delta_type pfgtopfe_op_delta
,input PF_weigth_type pfgtopfe_op_w1
,input PF_weigth_type pfgtopfe_op_w2
,input ... |
module sd_sd4_phy (
input clk,
input rst,
// input ddr_en, //ALWAYS ENABLED FOR NOW!
input i_en,
input i_write_flag,
output reg o_crc_err, //Detected a CRC error during read
//Debug
... |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// ... |
module SRAM(read, // Specifies if we want to read from the FIFO
write, // Specifies if we want to write form the FIFO
address, // Specifies the address for read/write
dataIn, // The input packet
dataOut, // The output packet
clk // Clock input
);
... |
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been... |
module sim();
reg CLK, RST;
initial CLK = 1'b0;
always #5 CLK = ~CLK; /* 100 MHz */
wire tb_enable;
wire[7:0] tb_wcount;
reg[7:0] tb_word;
reg[7:0] tb_key_length;
reg[7:0] tb_interval;
wire tb_valid;
wire[31:0] tb_hashkey;
wire tb_onloop;
reg[31:0] ROM7[0:6];
reg[31:0] ROM12[0:11];
reg[31:... |
module xilinx_ddr2
(
// Inputs
input [31:0] wbm0_adr_i,
input [1:0] wbm0_bte_i,
input [2:0] wbm0_cti_i,
input wbm0_cyc_i,
input [31:0] wbm0_dat_i,
input [3:0] wbm0_sel_i,
input wbm0_stb_i,
input wbm0_we_i,
// Outputs
output wbm0_ack_o,
output wbm... |
module usb_system_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
... |
module sky130_fd_sc_hs__nand4b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire nand0_out_Y ... |
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_... |
module test();
reg out_o;
reg inp_o;
reg ddr_o;
reg stb_o;
wire q_i;
/* We have a clock, but the mux doesn't use it. I use it for test
* synchronization only.
*/
reg clk_o;
/* Scenario tag for knowing which test is running when viewing waveforms. */
reg [7:0] scenario_o;
/* Device Under Test */
GPIA_BIT_IN dut... |
module outputs)
wire elink_en; // From elink of elink.v
wire elink_reset; // From eclocks of eclocks.v
wire rx_lclk; // From eclocks of eclocks.v
wire rx_lclk_div4; // From eclocks of eclocks.v
wire rx_lclk_pll; // From elink of elink.v
wire rxrd_access; // From elink of elink.v
w... |
module bitec_reconfig_alt_a10
#(
parameter [3:0] TX_LANES = 4,
parameter [3:0] RX_LANES = 4,
parameter [2:0] TX_RATES_NUM = 3, // Number of TX link rates (0: no TX support, 1: up to RBR, 2: up to HBR, etc.)
parameter [2:0] RX_RATES_NUM = 3, // Number of RX link rates (0: no TX support, 1: up to RBR, 2: up to H... |
module bitec_reconfig_avalon_mm_master
#(
parameter XCVR = 1 // Usage: 0 = TXPLL, 1 = XCVR
)
(
input wire clk,
input wire reset,
// Command strobes
input wire rcnf_req_cbus, // Assert for 1 clk cycle to get access to internal config bus
input wire rcnf_rel_cbus, // Assert fo... |
module dp_analog_mappings
(
input wire [1:0] vod,
input wire [1:0] pree,
output reg [4:0] out_vod,
output reg [5:0] out_pree_post_tap1 // bit5 is polarity, 1=neg 2=pos
);
always @(*)
case (vod)
2'b00 : // 400mv
begin
case(pree)
2'b00 : // (0db)
begin
... |
module logshiftright(distance,
data,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input wire [lpm_width-1 :0] data;
ou... |
module sky130_fd_sc_lp__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
inp... |
module bw_clk_gclk_inv_224x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule |
module rgmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("B... |
module inputs)
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg [23:0] address; ... |
module in_dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (cl... |
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.... |
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule |
module CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
input clk, rs... |
module limbus_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
... |
module fifo_spi_dpram (clk, nrst, we, din, dout, sck, ss);
input clk;
input nrst;
input we;
input [31:0] din;
output dout;
output sck;
output reg ss;
// States
parameter state_rst = 4'd0;
parameter state_wait = 4'd1;
parameter state_start = 4'd2;
parameter state_get_data = 4'd3;
parameter state_send ... |
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module hex_to_7seg
(
input i_Clk,
input [3:0] i_Value,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] out = 7'b0000000;
always @(pose... |
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VN... |
module sky130_fd_sc_ls__mux4 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
input A2 ,
input A3 ,
output X ,
//# {{control|Control Signals}}
input S0 ,
input S1 ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
... |
module fast_cycle(
input CLK_24M,
input LSPC_12M,
input LSPC_6M,
input LSPC_3M,
input LSPC_1_5M,
input RESETP,
input nVRAM_WRITE_REQ,
input [15:0] VRAM_ADDR,
input [15:0] VRAM_WRITE,
input REG_VRAMADDR_MSB,
input FLIP, nFLIP,
input [8:0] PIXELC,
input [8:0] RASTERC,
input P50_CO,
output nC... |
module MAIN(
input clk,
input clkb,
input Reset,
input Write_Reg,
input Mem_Write, // Disable
input [15:0] offset, // 16 bit (offset)
input [2:0] ALU_OP,
// input [5:0] STORAGE_Addr_R,
input wire [4:0] W_Addr,
input wire [4:0] RS,
input wire [4:0] RT, // Disable
output wire [31:0] A... |
module TESTSTORAGE(
input [5:0] Mem_Addr,
input [1:0] CS,
input Mem_Write,
input Clk,
output reg [7:0] LED
);
wire [31:0] F;
reg [31:0] dina;
RAM_B STORAGE (
.clka(Clk), // input clka
.wea(Mem_Write), // input [0 : 0] wea
.addra(Mem_Addr), // input [5 : 0] addra
.dina(din... |
module register(clk, Reset, R_Addr_A, R_Addr_B, W_Addr, W_Data, Write_Reg, R_Data_A, R_Data_B
);
input clk;
input Reset;
input Write_Reg;
input [4:0] R_Addr_A, R_Addr_B, W_Addr;
input [31:0] W_Data;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0] REGISTERS[31:0];
integer i;
ass... |
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
... |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule |
module ucb_flow_spi (/*AUTOARG*/
// Outputs
ucb_iob_stall, rd_req_vld, wr_req_vld, ifill_req_vld, thr_id_in,
buf_id_in, size_in, addr_in, data_in, ack_busy, int_busy,
ucb_iob_vld, ucb_iob_data,
// Inputs
clk, rst_l, iob_ucb_vld, iob_ucb_data, req_acpted, rd_ack_vld,
rd_nack_vld, ifill_ack_vld, ... |
module ddr3_s4_uniphy_example_if0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi... |
module
/////////////////////////////////////////////////////////////////////////////////
clock_generator my_clock_gen(
// inputs
clock2_50,
reset,
// outputs
aud_xck
);
audio_and_video_config cfg(
// Inputs
clock50,
reset,
// Bidirectionals
fpga_i2c_sdat,
fpga_i2c_sclk
);... |
module control(clock, reset, write_ready, write, frequency,
writedata_left, writedata_right);
input clock, reset, write_ready;
input [3:0] switches;
output reg write;
output reg [23:0] writedata_left, writedata_right;
// output reg [3:0] frequency;
reg [7:0] counter;
// reg [2:0] c... |
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module
//---------------------------------------------------------------------------
// NOTE: Because we need to clear it in the cycle after a flit / credit has
// been transmitted, this register cannot be included in any of the other
// clock gating domains. If we could change things such that flits ... |
module m_download(//input
clk,
rst,
IN_flit_mem,
v_IN_flit_mem,
In_flit_ctrl,
mem_done_access,
//output
v_m_download,
m_download_flits,
... |
module CRC5_D5(
nextCRC5_D5,
Data,
crc
);
// polynomial: x^5 + x^2 + 1
// data width: 5
// convention: t he first serial bit is D[4]
output [4:0] nextCRC5_D5;
input [4:0] Data;
input [4:0] crc;
reg [4:0] d;
reg [4:0] c;
reg [4:0] newcrc;
begin
d = Data;
c = crc;
new... |
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ ... |
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
... |
module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS... |
module sky130_fd_sc_ls__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_s... |
module sky130_fd_sc_ls__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41a base (
.... |
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS... |
module sky130_fd_sc_hs__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule |
module ddr3_s4_uniphy_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseud... |
module fpalu(
input [0:39] t,
input [0:39] c,
input faa,
input fab,
input fra,
input frb,
input p_16,
input p_32,
input p_40,
output fp0_,
output fp16_,
output p32_,
output [0:39] sum
);
wor __NC;
wire g0a, g1a, g2a, g3a;
wire p0a, p1a, p2a, p3a;
alu181 M52(
.a(t[0:3]),
.b(c[0:3]),
.m(1'b0),
... |
module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o,
output wire[`DataBus] check,
input wire[2:0] di... |
module umult8(reg_A, reg_B, result);
// INPUTS
input [0:7] reg_A, reg_B;
// OUTPUTS
output [0:15] result;
// REGISTERS
reg [0:15] p8a_0;
reg [0:15] p8b_0;
reg [0:15] pt;
reg [0:15] result;
// INTEGERS (contols for loops)
integer i;
always @ (reg_A or reg_B)
begin
// reg_B
/... |
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
... |
module FIFO_image_filter_img_4_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [... |
module FIFO_image_filter_img_4_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input ... |
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out of sync and error
output ... |
module system_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
... |
module apu
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire [ 3:0] mute_in, // disable specific audio channels
input wire [15:0] a_in, // addr input bus
input wire [ 7:0] d_in, // data input bus
input wire r_nw_in, // re... |
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;... |
module lab3_15s_tb(
);
reg INPUT,Clk, reset;
parameter DELAY=7.5;
parameter TIME=150;
wire OUT;
integer i;
lab3_15s DUT (.INPUT(INPUT), .Clk(Clk), .OUT(OUT), .reset(reset));
initial
begin
#TIME $finish;
end
initial begin
Clk = 0;
for (i = 0; i ... |
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;... |
module sky130_fd_sc_hd__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module mig_7series_v1_9_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG",
// May be assigned unique name when
// multiple IP cores used in des... |
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
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