module_content stringlengths 18 1.05M |
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module SD_CMD (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
... |
module ddrOutput2#(
parameter nbo = 12,
parameter i2o = 4,
parameter nbi = nbo*i2o)
( input ddrClk, // SE DAC DDR clock 250MHz (ddr500) input_clock ddr
input dcmResetN, // DCM Reset async active-low
output dcmLocked,... |
module pwm #(CLK_PERIOD = 1000)(
input clk,
input enable,
input [31:0] pwm_period,
output out
);
reg clk_out=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < pwm_period)
begin
clk_out <= 1'b1;
counter <=... |
module outputs
wire [152 : 0] c0_request_get, c1_request_get, s_response_get;
wire RDY_c0_request_get,
RDY_c0_response_put,
RDY_c1_request_get,
RDY_c1_response_put,
RDY_s_request_put,
RDY_s_response_get;
// ports of submodule pktFork
wire [152 : 0] pktFork_iport_put, pktFork_... |
module test;
reg nss;
reg mosi;
reg sck;
wire miso;
wire [6:0] address_bus;
wire [7:0] data_bus;
wire read_n;
wire write_n;
spi_ctl s1(nss, mosi, sck, miso, address_bus, data_bus, read_n, write_n);
// There are no devices connected to the bus for this test
// bench so here we use writ... |
module usb_cdc_core
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input [ 7:0] utmi_data_in_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [ 1:0]... |
module sky130_fd_sc_hs__dlymetal6s2s (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule |
module ecg_top_stim;
reg [15:0] data_in;
reg clk, nReset;
wire [15:0] q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_peak_ref,s_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,
p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,t_peak_pos;
ecg_top top (q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_pe... |
module system_vga_color_test_0_0
(clk_25,
xaddr,
yaddr,
rgb);
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
wire clk_25;
wire [23:3]\^rgb ;
wire [9:0]xaddr;
wire [9:0]yaddr;
assign rgb[23:22] = \^rgb [23:22];
assign rgb[21] = \^rgb [20];
assign rgb[20] = \^rg... |
module system_vga_color_test_0_0_vga_color_test
(rgb,
yaddr,
xaddr,
clk_25);
output [9:0]rgb;
input [6:0]yaddr;
input [9:0]xaddr;
input clk_25;
wire clk_25;
wire [9:0]rgb;
wire \rgb[13]_i_1_n_0 ;
wire \rgb[14]_i_1_n_0 ;
wire \rgb[14]_i_2_n_0 ;
wire \rgb[14]_i_3_n_0 ;
wire \rgb[14]_... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
... |
module outputs)
wire [129:0] pcx_col0_data_px_l; // From mac0 of pcx_dp_maca_r.v
wire [129:0] pcx_col1_data_px_l; // From mac1 of pcx_dp_macb_r.v
wire [129:0] pcx_col2_data_px_l; // From mac2 of pcx_dp_macb_r.v
wire [129:0] pcx_col4_data_px_l; // From mac4 of pcx_... |
module soc_testbench;
`include "test_management.v"
reg [31:0] read_word;
//
// Display
//
wire [3:0] anode; // From dut of display.v
wire [7:0] cathode; // From dut of display.v
wire [15:0] leds;
reg [15:0] switches_reg = 16'h0000;
wire [15:0] switches = s... |
module sky130_fd_sc_lp__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(V... |
module sky130_fd_sc_lp__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule |
module tty(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input... |
module tto(input wire clk,
input wire tto_clock,
input wire [8:1] iob,
input wire tty_data_clr,
input wire tty_data_set,
output wire tx,
output reg tto_done = 0
);
reg [8:1] tto;
reg tto_out_line;
reg tto_enable = 0;
reg tto_active = 0;
reg tto_active0;
reg tto_div2 = 0;
reg tto_div20;
wire tto_4count;
... |
module tti(input wire clk,
input wire tti_clock,
input wire rx,
output wire [8:1] iob,
output reg tti_active = 0,
output reg tti_done = 0,
output reg [8:1] tti = 0
);
assign iob = tti;
wire tti_shift = tti_4count_rise & ~tti_last_unit;
reg tti_last_unit = 0;
reg tti_active0;
wire tti_4count;
reg tti_4count... |
module clk14khz(input wire inclk,
output wire outclk);
reg [11:0] cnt = 0;
assign outclk = cnt == 3551;
always @(posedge inclk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 12'b1;
endmodule |
module clk16div(input wire clk,
input wire inclk,
output wire outclk
);
reg [4:0] cnt = 0;
assign outclk = cnt == 16;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 5'b1;
endmodule |
module div8(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [2:0] cnt = 4;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable)
cnt <= cnt + 3'b1;
assign out = cnt[2];
endmodule |
module count4(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [1:0] cnt = 0;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable && cnt != 3)
cnt <= cnt + 2'b1;
assign out = cnt == 3;
endmodule |
module clk4div(input wire clk,
input wire inclk,
output wire outclk
);
reg [2:0] cnt = 0;
assign outclk = cnt == 4;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 3'b1;
endmodule |
module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_mas... |
module RXTX_BITSLICE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter ENABLE_PRE_EMPHASIS = "FALSE",
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_RX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_INVERTE... |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write2_tasks tasks ();
integer cyc; initial cyc=0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n"... |
module velocityControlHdl_Convert_Data_Type1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En24
output signed [35:0] Out1; // sfix36_En23
wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23
// <S10>/Data Type Conversion
assign Data_Type_Conver... |
module sky130_fd_sc_hs__nand4bb (
VPWR,
VGND,
Y ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nand0_out ;
wire or0_out_Y ... |
module test;
reg [0:0] io_in_valid;
reg [31:0] io_in_bits;
reg [0:0] io_out_ready;
reg [0:0] io_pcIn_valid;
reg [0:0] io_pcIn_bits_request;
reg [15:0] io_pcIn_bits_moduleId;
reg [7:0] io_pcIn_bits_portId;
reg [15:0] io_pcIn_bits_pcValue;
reg [3:0] io_pcIn_bits_pcType;
wire [0:0]... |
module encode_ctl(/*AUTOARG*/
// Outputs
hraddr, cnt_output_enable, cnt_len, cnt_output,
cnt_finish,
// Inputs
clk, rst, data_valid, data_empty, hash_data, hash_data1,
data_d1, data_d2, hash_ref, iidx, hdata, data, hash_d1,
hash_data_d1
);
parameter LZF_WIDTH = 20;
input clk, rst;
... |
module DoubleRegisters(
clk,
bus_in, bus_out1, bus_out2,
num1, num2,
cs_h_in, cs_l_in, cs_16_in,
cs_h_out1, cs_l_out1, cs_16_out1,
cs_h_out2, cs_l_out2, cs_16_out2);
input [15:0] bus_in;
output reg [15:0] bus_out1, bus_out2;
input [1:0] num1, num2;
input c... |
module sky130_fd_sc_hs__nor3b (
VPWR,
VGND,
Y ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
... |
module processor_test (input wire clk,
input wire pc_reset,
input wire pc_enable
);
// Step 1
wire [31:0] pc_in;
wire [31:0] pc_out;
// Step 2
wire [31:0] pc_plus_four;
wire [31:0] add0_in1;
assign add0_in1 = 32'd4;
// Step 3
wire [31:0] alu_data_output;
wire [31:0] readData2;
wire [31:0] mem_da... |
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd... |
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
... |
module ik_swift_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // ... |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX... |
module sky130_fd_sc_lp__a41o_0 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_s... |
module sky130_fd_sc_lp__a41o_0 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.... |
module sync_master(
input wire clk, // clock input
input wire clk_2x, // clock 90 input
input wire datain, // data inputs
input wire rst, // reset input
output wire useaout, // useA outp... |
module des_node #(
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2
)
(
input wire clk,
input wire reset,
// -- puertos de entrada ------------------------------------- >>>>>
output wire credit_out_xpos_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_xpos_din,
output wire credit_out_ypos_dout,... |
module uart_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock (12MHz in the ICEstick)
input wire rstn, //-- Reset (Active low)
input wire rx, //-- Serial data input
output reg rcv, //-- Data is av... |
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_br... |
module sky130_fd_sc_hs__udp_dff$P_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module sky130_fd_sc_hs__nand2b (
VPWR,
VGND,
Y ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// ... |
module arbiter
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire [3:0] port_request_din,
input wire arbiter_strobe_din,
input wire clear_arbiter_din,
// -- output ------------------------------------------------- >>>>>
output wire [3:0] xbar_conf_ve... |
module system_clock_splitter_1_0(clk_in, latch_edge, clk_out)
/* synthesis syn_black_box black_box_pad_pin="clk_in,latch_edge,clk_out" */;
input clk_in;
input latch_edge;
output clk_out;
endmodule |
module quadrature_decoder(
CLOCK,
RESET,
A,
B,
COUNT_ENABLE,
DIRECTION,
SPEED
);
input CLOCK, RESET, A, B;
output COUNT_ENABLE;
output DIRECTION;
output [3:0] SPEED;
reg [2:0] A_delayed;
reg [2:0] B_delayed;
always @(posedge CLOCK or posedge RESET) begin... |
module pseudo_entropy(
input wire clk,
input wire reset_n,
input wire enable,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] stats,
output wire ... |
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wir... |
module top();
// Inputs are registered
reg D;
reg SET;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
... |
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
... |
module edge_detector(
clk,
reset_n,
in, // detector input
out, // detector output
edge_detect // spcifies whether rising or falling edge it to detect
);
`include "parameters_global.v"
input clk;
input reset_n;
input in;
input edge_detect;
output reg out;
... |
module system_clk_wiz_0_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule |
module convolve_kernel (
ap_clk,
ap_rst_n,
bufw_0_Addr_A,
bufw_0_EN_A,
bufw_0_WEN_A,
bufw_0_Din_A,
bufw_0_Dout_A,
bufw_0_Clk_A,
bufw_0_Rst_A,
bufw_0_Addr_B,
bufw_0_EN_B,
bufw_0_WEN_B,
bufw_0_Din_B,
bufw_0_Dou... |
module dividerp1(input wire clk,
input wire timer_ena,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo... |
module sky130_fd_sc_hs__bufbuf_8 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_output... |
module sky130_fd_sc_hd__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output ... |
module sky130_fd_sc_lp__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module main;
reg clk = 0;
always #300 clk = !clk;
reg [4:0] in = "11111";
reg [1:0] out;
reg [1:0] out_golden;
integer seed = 1234;
integer rvec_file;
integer ret;
integer soe0 = 0;
integer soe1 = 0;
initial begin
$sdf_annotate("mydesign.sdf",DUT,... |
module up_adc_channel (
// adc interface
adc_clk,
adc_rst,
adc_enable,
adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,
adc_dfmt_type,
adc_dfmt_enable,
adc_dcfilt_offset,
adc_dcfilt_coeff,
adc_iqcor_coeff_1,
adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel,
adc_pn_err,
adc_pn_oos,
adc_or,... |
module doubleAddWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
input dummy_enable;
doubleAdd doubleAdd_component (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule |
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FI... |
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FI... |
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FI... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;... |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;... |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of ch... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
p... |
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