module_content stringlengths 18 1.05M |
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module system_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.I... |
module sky130_fd_sc_ms__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module TB_CT;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg chip_select;
// Outputs
wire signal_out;
wire [3:0] ciclo_actual;
// Instantiate the Unit Under Test (UUT)
Modificacion_Ciclo_Trabajo uut (
.clk_100MHz(clk_100MHz),
.clk_de_trabajo(clk_de_trabajo),
.rst(rst... |
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
... |
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
parameter Tp = 1;
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
output sync_out;
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
wire z;... |
module BIOS_ROM
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) ... |
module BIOS_ROM_blk_mem_gen_generic_cstr
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_... |
module BIOS_ROM_blk_mem_gen_prim_width
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_bl... |
module BIOS_ROM_blk_mem_gen_prim_wrapper_init
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ;
wire [11:0]addra;
wire clka;
wire [7:... |
module BIOS_ROM_blk_mem_gen_top
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_g... |
module BIOS_ROM_blk_mem_gen_v8_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
... |
module BIOS_ROM_blk_mem_gen_v8_2_synth
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_bl... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module counter #(
parameter MAX = 15,
parameter START = 0,
parameter signed INC = 1
) (
input clk,
input reset,
input ce,
output reg [$clog2(MAX+1)-1:0] count = START
);
localparam TCQ = 1;
always @(posedge clk)
if (reset)
count <= #TCQ START;
else if (ce)
count <= #TCQ count + INC;
endmodule |
module pipeline_ce_reset #(
parameter STAGES = 0
) (
input clk,
input ce,
input reset,
input i,
output o
);
localparam TCQ = 1;
if (!STAGES)
assign o = i;
else begin
reg [STAGES-1:0] pipeline = 0;
assign o = pipeline[STAGES-1];
always @(posedge clk)
if (reset)
pipeline <= #TCQ pipeline << 1;
... |
module pipeline_ce #(
parameter STAGES = 0
) (
input clk,
input ce,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, ce, 1'b0, i, o);
endmodule |
module pipeline_reset #(
parameter STAGES = 0
) (
input clk,
input reset,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, reset, i, o);
endmodule |
module pipeline #(
parameter STAGES = 0
) (
input clk,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, 1'b0, i, o);
endmodule |
module reverse_words #(
parameter M = 4,
parameter WORDS = 1
) (
input [M*WORDS-1:0] in,
output [M*WORDS-1:0] out
);
genvar i;
for (i = 0; i < WORDS; i = i + 1) begin : REV
assign out[i*M+:M] = in[(WORDS-i-1)*M+:M];
end
endmodule |
module rotate_right #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[S%M+:M];
endmodule |
module rotate_left #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[M-(S%M)+:M];
endmodule |
module mux_one #(
parameter WIDTH = 2,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output out
);
assign out = in[sel];
endmodule |
module mux_shuffle #(
parameter U = 2,
parameter V = 2
) (
input [U*V-1:0] in,
output [V*U-1:0] out
);
genvar u, v;
generate
for (u = 0; u < U; u = u + 1) begin : _U
for (v = 0; v < V; v = v + 1) begin : _V
assign out[v*U+u] = in[u*V+v];
end
end
endgenerate
endmodule |
module mux #(
parameter WIDTH = 2,
parameter BITS = 1,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [BITS*WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output [BITS-1:0] out
);
wire [WIDTH*BITS-1:0] shuffled;
mux_shuffle #(WIDTH, BITS) u_mux_shuffle(in, shuffled);
mux_one #(WIDTH) u_mux_one [BITS-1:0] (shuffled, ... |
module
//============================================================================
// vga_test debug_unit ( .clk(clk), .clr(clr), .hsync(hsync), .vsync(vsync), .red(red), .green(green), .blue(blue) );
//============================================================================
// Instantiation
//===========... |
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
wire tmp;
assign tmp = ~(a&b);
wire tmp2 = tmp;
reg tmp3;
always @*tmp3 = tmp2;
always @* q = tmp3;
endmodule |
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOTA[0]... |
module sha2_sec_ti2_rm0 (
input wire i_reset,
input wire i_clk,
input wire i_sha512,
input wire i_write,//1 cycle pulse each time i_dat is valid for message input.
input wire i_write_state,//1 cycle pulse each time i_dat is valid for state input.
input wire i_read,
input wire i_init_mask,//p... |
module sha2_sec_ti2_rm0_masked_maj #(
parameter WIDTH = 1
)(
input wire i_clk,
input wire [3*2*WIDTH-1:0] i_rnd,
input wire [WIDTH-1:0] i_x_mdat,
input wire [WIDTH-1:0] i_x_mask,
input wire [WIDTH-1:0] i_y_mdat,
input wire [WIDTH-1:0] i_y_mask,
input wire [WIDTH-1:0] i_z_mdat,//all input... |
module sha2_sec_ti2_rm0_serial_masked_ch(
input wire i_clk,
input wire [2-1:0] i_rnd,
input wire i_x_mdat,
input wire i_x_mask,
input wire i_y_mdat,
input wire i_y_mask,
input wire i_z_mdat,
input wire i_z_mask,
output reg o_mdat,
output reg o_mask
);
//ch_256 = z ^ (x & ... |
module sha2_sec_ti2_rm0_serial_masked_add_5op (
input wire i_clk,
input wire i_start,
input wire [16-1:0] i_rnd,
input wire [3:0] i_c_mdat,
input wire [3:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op4_mdat... |
module sha2_sec_ti2_rm0_serial_masked_add_4op (
input wire i_clk,
input wire i_start,
input wire [12-1:0] i_rnd,
input wire [2:0] i_c_mdat,
input wire [2:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op0_mask... |
module sha2_sec_ti2_rm0_serial_masked_add_2op (
input wire i_clk,
input wire i_start,
input wire [4-1:0] i_rnd,
input wire i_c_mdat,
input wire i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
output reg o_dat_mdat,
output... |
module sha2_sec_ti2_rm0_masked_full_adder_ti(
input wire i_clk,
input wire [2-1:0] i_a,
input wire [2-1:0] i_b,
input wire [2-1:0] i_c,
input wire [3:0] i_rnd,
output reg [2-1:0] o_q,
output reg [2-1:0] o_c
);
wire [2-1:0] x0 = i_a ^ i_b;
wire [2-1:0] n0,n1;
sha2_sec_ti2_rm0_ti2_and u0(.i_clk(i_clk), .i_a(x0), .... |
module sha2_sec_ti2_rm0_remask(
input wire [1:0] a,
input wire r,
output wire [1:0] y
);
sha2_sec_ti2_rm0_xor u0(.a(a[0]), .b(r), .y(y[0]));
sha2_sec_ti2_rm0_xor u1(.a(a[1]), .b(r), .y(y[1]));
endmodule |
module sha2_sec_ti2_rm0_xor_impl #(
parameter WIDTH = 1,
parameter NOTY = 0
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output reg [WIDTH-1:0] y
);
always @* y = NOTY ^ a ^ b;
endmodule |
module sha2_sec_ti2_rm0_xor #(
parameter WIDTH = 1
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output wire [WIDTH-1:0] y
);
sha2_sec_ti2_rm0_xor_impl #(.WIDTH(WIDTH)) u_ITK(.a(a), .b(b), .y(y));
endmodule |
module sha2_sec_ti2_rm0_plain_and(
input wire a,
input wire b,
output reg q
);
always @* q = a&b;
endmodule |
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
always @* q = ~(a&b);
endmodule |
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOT... |
module sha2_sec_ti2_rm0_ti2_and_l1 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire i_clk,
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
input wire [1:0] i_rnd,
output wire [1:0] o_y //SAF... |
module sha2_sec_ti2_rm0_ti2_and(
input wire i_clk,
input wire [1:0] i_a,
input wire [1:0] i_b,
input wire [1:0] i_rnd,
output wire[1:0] o_y
);
sha2_sec_ti2_rm0_ti2_and_l1 #(.NOTA(0), .NOTB(0), .NOTY(0)) impl_ITK(.i_clk(i_clk),.i_a(i_a),.i_b(i_b),.i_rnd(i_rnd),.o_y(o_y));
endmodule |
module dcfifo_32in_32out_8kb
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd... |
module dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\... |
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_width
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc... |
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\... |
module dcfifo_32in_32out_8kb_blk_mem_gen_top
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count... |
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.coun... |
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc... |
module dcfifo_32in_32out_8kb_clk_x_pntrs
(ram_empty_i_reg,
WR_PNTR_RD,
ram_empty_i_reg_0,
RD_PNTR_WR,
ram_full_i,
Q,
\gic0.gc0.count_reg[7] ,
\gic0.gc0.count_d1_reg[7] ,
rst_full_gen_i,
\rd_pntr_bin_reg[0]_0 ,
\gic0.gc0.count_d2_reg[7] ,
wr_clk,
\ngwrdrst.grst.g7serrst... |
module dcfifo_32in_32out_8kb_fifo_generator_ramfifo
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [3... |
module dcfifo_32in_32out_8kb_fifo_generator_top
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]... |
module dcfifo_32in_32out_8kb_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert... |
module dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
inpu... |
module dcfifo_32in_32out_8kb_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7... |
module dcfifo_32in_32out_8kb_rd_bin_cntr
(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
ram_empty_i_reg,
WR_PNTR_RD,
rd_en,
p_18_out,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] ,
E,
rd_clk,
Q);
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output ram_empty_i... |
module dcfifo_32in_32out_8kb_rd_logic
(empty,
p_18_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
rd_clk,
Q,
WR_PNTR_RD,
rd_en,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] );
output empty;
output p_18_out;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
inp... |
module dcfifo_32in_32out_8kb_rd_status_flags_as
(empty,
p_18_out,
E,
\wr_pntr_bin_reg[6] ,
rd_clk,
Q,
rd_en);
output empty;
output p_18_out;
output [0:0]E;
input \wr_pntr_bin_reg[6] ;
input rd_clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire [0:0]Q;
wire empty;
wire p_... |
module dcfifo_32in_32out_8kb_reset_blk_ramfifo
(rst_full_ff_i,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_reg[0] ,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_full_ff_i;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]\gic0.gc0.count_... |
module dcfifo_32in_32out_8kb_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [7:0]D;
input [7:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
w... |
module dcfifo_32in_32out_8kb_synchronizer_ff_0
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [7:0]D;
input [7:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
... |
module dcfifo_32in_32out_8kb_synchronizer_ff_1
(out,
\wr_pntr_bin_reg[6] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [6:0]\wr_pntr_bin_reg[6] ;
input [7:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]D;
wire [7:... |
module dcfifo_32in_32out_8kb_synchronizer_ff_2
(out,
\rd_pntr_bin_reg[6] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [6:0]\rd_pntr_bin_reg[6] ;
input [7:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]D;
wire [7:... |
module dcfifo_32in_32out_8kb_wr_bin_cntr
(ram_full_fb_i_reg,
\wr_data_count_i_reg[7] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
S,
Q,
\gic0.gc0.count_d2_reg[7]_0 ,
RD_PNTR_WR,
wr_en,
p_1_out,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output ram_ful... |
module dcfifo_32in_32out_8kb_wr_dc_as
(wr_data_count,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
\gic0.gc0.count_d2_reg[6] ,
S,
\gic0.gc0.count_d2_reg[7] );
output [1:0]wr_data_count;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [6:0]\gic0.gc0.count_... |
module dcfifo_32in_32out_8kb_wr_logic
(full,
ram_full_fb_i_reg,
Q,
WEBWE,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\gic0.gc0.count_d2_reg[7] ,
wr_data_count,
ram_full_i,
wr_clk,
rst_full_ff_i,
RD_PNTR_WR,
wr_en,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
o... |
module dcfifo_32in_32out_8kb_wr_status_flags_as
(full,
p_1_out,
E,
ram_full_i,
wr_clk,
rst_full_ff_i,
wr_en);
output full;
output p_1_out;
output [0:0]E;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input wr_en;
wire [0:0]E;
wire full;
wire p_1_out;
wire ram_ful... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ... |
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// ... |
module BLE_v3_10_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
... |
module SCB_P4_v3_20_1 (
interrupt,
clock,
rx_tr_out,
tx_tr_out,
s_mosi,
s_sclk,
s_ss,
m_miso,
m_mosi,
m_sclk,
m_ss0,
m_ss1,
m_ss2,
m_ss3,
s_miso,
rx_in,
cts_in,
tx_out,
rts_out);
output interrupt;
input clock;
output ... |
module top ;
wire Net_3181;
electrical Net_3175;
wire Net_3180;
wire Net_3179;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3701;
electrical Net_3702;
electrical Net_2323;
electrical Net_290;
wire Net_3... |
module image_filter_AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM... |
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fahcin base (
... |
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fahcin base (
.... |
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
... |
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module eg_step_ram(
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
reg [7:0] step_idx;
reg [7:0] step_ram;
always @(*)
case( { rate_V[5:4]==2'b11, rate_V[1:0]} )
3'd0: step_ram = 8'b00000000;
3'd1: st... |
module soc
(
// General - Clocking & Reset
clk_i,
rst_i,
ext_intr_i,
intr_o,
// Memory interface
io_addr_i,
io_data_i,
io_data_o,
io_we_i,
io_stb_i,
io_ack_o
);
//-----------------------------------------------------------------
// Params
//-------------------------... |
module DSP_OUT_REGISTERED (clk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire clk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Combinational logic */
(* pack="DSP-DFF" *)
wire [DATA_WIDTH-1:0] c_out;
DSP_COMBINATIONAL comb (.a(a... |
module sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module spu_maaeqb (
/*outputs*/
spu_maaeqb_memren,
spu_maaeqb_memwen,
spu_maaeqb_rst_iptr,
spu_maaeqb_rst_jptr,
spu_maaeqb_incr_iptr,
spu_maaeqb_incr_jptr,
spu_maaeqb_a_rd_oprnd_sel,
spu_maaeqb_ax_rd_oprnd_sel,
spu_maaeqb_m_rd_oprnd_sel,
spu_maaeqb_me_rd_oprnd_sel,
spu_maaeqb_n_rd_oprnd_sel,
spu_maaeqb_m_wr_oprnd_s... |
module sky130_fd_sc_ms__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
... |
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module rj45_led_controller(
input wire clk, // 150 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//-------------------------------------------------------------... |
module sky130_fd_sc_hdll__diode_4 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
)... |
module sky130_fd_sc_hdll__diode_4 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule |
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input V... |
module sky130_fd_sc_ls__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule |
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_traffic_tracking_check ( .error(1'b1) );
end
endgenerate
altera_avlmm_slv_freeze_bridge #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0),
.ENABLE... |
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// ... |
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module fabric2_decoder #(
parameter PORTNO_WIDTH = 11
)
(
i_addr,
o_addr,
o_portno
);
localparam PORT_BITS = PORTNO_WIDTH + 1;
input wire [`ADDR_WIDTH-1:0] i_addr;
output wire [`ADDR_WIDTH-1:0] o_addr;
output wire [PORTNO_WIDTH-1:0] o_portno;
/* Decode address */
assign o_addr = (!i_addr[`ADDR_WIDTH-1] ? { 1'... |
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module quick_fifo #(
parameter FIFO_WIDTH = 32,
parameter FIFO_DEPTH_BITS = 8,
parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
) (
input wire clk,
input wire reset_n,
input wire we, // input... |
module or1200_dpram
(
// Generic synchronous double-port RAM interface
clk_a, ce_a, addr_a, do_a,
clk_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
... |
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