module_content stringlengths 18 1.05M |
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module sky130_fd_sc_ls__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_s... |
module sky130_fd_sc_ls__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32a base (
.... |
module muladd_wrap (
input ck,
input [63:0] i_a, i_b, i_c,
input [6:0] i_htId,
input i_vld,
output [63:0] o_res,
output [6:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t19_res;
reg [6:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId, r_t7_htId, r_t8_htId, r_t9_h... |
module OC_Buff(in, out);
input in;
output out;
assign out = in ? 1'bz : 1'b0;
endmodule |
module pluto_spi_stepper_opendrain(clk, SCK, MOSI, MISO, SSEL, nRESET, nPE, LED, nConfig, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig = 1'bZ, nPE;
output LED;
input [15:0] din;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
a... |
module RX_BITSLICE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE = "FALSE",
parameter DATA_TYPE = "DATA",
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter integer DELAY_VALUE_EXT = ... |
module sky130_fd_sc_hs__nand4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
... |
module sky130_fd_sc_hs__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
... |
module scorecopymux (
data0x,
data1x,
data2x,
data3x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input [3:0] data2x;
input [3:0] data3x;
input [1:0] sel;
output [3:0] result;
endmodule |
module sky130_fd_sc_hd__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module fifo(datain, rd, wr, rst, clk, full, empty,led_n,wei);
input [3:0] datain;
input rd, wr, rst, clk;
output [6:0] led_n;
output full, empty, wei;
reg [3:0] dataout;
reg full_in, empty_in,wei_in,div;
reg [3:0] mem [15:0];
reg [23:0]cnt;
reg [3:0] rp, wp;
reg [6:0] led_n;
assign full = full_in;
assign empty = em... |
module outputs)
wire clear_spif; // From regs of spi_regs.v
wire clear_wcol; // From regs of spi_regs.v
wire rfre; // From regs of spi_regs.v
wire [7:0] spcr; // From regs of spi_regs.v
w... |
module mig_7series_v2_0_data_gen_chk # (
parameter C_AXI_DATA_WIDTH = 32 // Width of the AXI write and read data
)
(
input clk,
input data_en,
input [2:0] data_pattern,
input pattern_init, // when... |
module ps2_keyb(
input wire clk,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [8:0] rows,
output wire [7:0] cols,
output wire rst_out_n,
output wire nmi_out_n,
output wire mrst_out_n,
output wire [1:0] user_toggles,
//-----------------... |
module sky130_fd_sc_hs__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module *
* *
**********************************************************************************/
endmodule |
module SPImaster(
rst,
clk,
start,
rxdata,
done,
transmit,
txdata,
x_axis_data,
y_axis_data,
z_axis_data
);
// ====================================================================================
// Port Declarations
// =====================================================================... |
module mouse_painter(
input [4:0] line_number,
output reg [7:0] line_code
);
parameter [7:0] line00 = 8'h01;
parameter [7:0] line01 = 8'h03;
parameter [7:0] line02 = 8'h07;
parameter [7:0] line03 = 8'h0F;
parameter [7:0] line04 = 8'h1F;
parameter [7:0] line05 = 8'h3F;
parameter [7:0] line06 = 8... |
module abc(
input clk,
input ce,
input [11:0] a,
input [11:0] b,
input [11:0] c,
output [24:0] y
);
wire signed [12:0] sum_ab;
wire signed [11:0] del_c;
// Latency = 2
delay_line #(
.DELAY(2),
... |
module level2arch (data_in,clk,nReset);
reg signed [15:0] cD_l2,cA_l2;
input [15:0] data_in;
input clk, nReset;
wire clk, nReset;
reg [15:0] data0, data1;
reg [2:0] count1;
reg [8:0] count2;
reg [8:0] count3;
reg [15:0] cD_store [0:`n2-2];
integer i;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
... |
module LCD(
input clk,
input rst,
input [127:0] upRow,
input [127:0] doRow,
output e,
output rs,
output rw,
output [3:0] sf
);
reg [23:0] count = 0;
reg refresh;
reg [5:0] Code;
assign {e, rs, rw, sf} = {refresh, Code};
// count
always@(posedge clk, posedge rst)
begin
if(rst)... |
module cpu_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rv... |
module gpr_file(
input wire clock,
input wire reset,
input wire write_enable,
input wire[`REGS_ADDR_BUS] write_addr,
input wire[`REGS_DATA_BUS] write_data,
input wire read_enab... |
module sky130_fd_sc_hvl__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
endmodule |
module sumcomp_test;
// Inputs
reg xi;
reg yi;
reg ci;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
sumcomp uut (
.xi(xi),
.yi(yi),
.ci(ci),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
ci ... |
module sky130_fd_sc_ls__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_s... |
module sky130_fd_sc_ls__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.... |
module GS_cpld(
output wire config_n, // ACEX1K config pins
input wire status_n, //
input wire conf_done, //
output wire cs, //
input wire init_done, //
input wire clk24in, // 24mhz in
input wire clk20in, // 20mhz in
input wire c... |
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'... |
module LZD_48bit(in, out, valid
);
input [47:0]in;
output reg [5:0]out;
output reg valid;
wire v1,v2;
wire [4:0]l1;
wire [3:0]l2;
initial
begin
out<=5'b00000;
valid<=0;
end
LZD_32bit d9( .in(in[31:0]), .out(l1), .valid(v1)); //instantiation of 16bit and 32bit Leading zero detectors
LZD_... |
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$s (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule |
module execute_shift #(
parameter P_N = 32
)(
//Control
input wire [2:0] iCONTROL_MODE,
//iDATA
input wire [P_N-1:0] iDATA_0,
input wire [P_N-1:0] iDATA_1,
//oDATA
output wire [P_N-1:0] oDATA,
output wire oSF,
output wire oOF,
output wire oCF,
output wire oPF,
output wire oZF
);
fu... |
module sky130_fd_sc_hs__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter ... |
module sky130_fd_sc_ms__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
... |
module sky130_fd_sc_ms__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
... |
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_a... |
module sky130_fd_sc_lp__xnor2_m (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VP... |
module sky130_fd_sc_lp__xnor2_m (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule |
module ad_tdd_control(
// clock and reset
clk,
rst,
// TDD timming signals
tdd_enable,
tdd_secondary,
tdd_tx_only,
tdd_rx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
td... |
module sky130_fd_sc_hs__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module sky130_fd_sc_lp__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tapvgnd2 base ();
endmodule |
module system_vga_sync_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xad... |
module system_vga_sync_0_0_vga_sync
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active0;
wire active_i_3_n_0;
wire clear;
wire clk;
wire \h_c... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module led_capture(
led_input,clk,rst_n,tx_start,tx_data
);
input led_input;
input clk;
input rst_n;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg pos_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
/*********... |
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
... |
module axi_interconnect #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
)(
//control signals
input clk,
input rst,
//bus write addr path
output [3:0] i_awid, //Write ID
output [ADDR_WIDTH -... |
module sram (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [71:0] data;
input [9:0] rdaddress;
input rden;
input [9:0] wraddress;
input wren;
output [71:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef... |
module sky130_fd_sc_lp__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule |
module simplez #(
parameter BAUD = `B115200, //-- Velocidad de comunicacion de la pantalla / Teclado
parameter WAIT_DELAY = `T_200ms, //-- Tiempo de espera para la instruccion WAIT (Debug)
parameter ROMFILE = "", //-- Fichero con el contenido de la RAM a cargar
para... |
module FIFO_DETECTION_YN (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [109:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [109:0] q;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
c... |
module One;
wire one = 1'b1;
endmodule |
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "gener... |
module lpddr2_cntrlr_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
res... |
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module axilite2regctl #
(
// Width of S_AXI data bus
parameter integer C_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_ADDR_WIDTH = 10,
// Width of REG address
parameter integer C_REG_IDX_WIDTH = 8
)
(
input wire clk,
input wire resetn,
/// reg ctl interface
output rd_en,
output [C_R... |
module FBModule(
input clk,
input store_strb,
input [1:0] sel,
input signed[12:0] ai_in,
input signed [12:0] aq_in,
input signed [12:0] bi_in,
... |
module nios_tester_jtagdebug (
output wire [25:0] mm_write_address, // mm_write.address
output wire mm_write_write, // .write
output wire [7:0] mm_write_writedata, // .writedata
input wire mm_write_waitrequest, ... |
module sky130_fd_sc_ms__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4 base (
.... |
module sky130_fd_sc_ms__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B... |
module supersaw (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_comp... |
module uart_light_tx_ctrl
#(
parameter STATE_COUNT = 2,
parameter IDLE = 2'b00,
parameter LOAD = 2'b01,
parameter TRANSMITTING = 2'b10
)(
input wire reset,
input wire clk_tx,
//Interfaces zum SPMC
input wire word_ready,
output wire fifo_tx_full,
output wire fifo_tx_empty,
//Interfaces zum Datenpfad-Mod... |
module WcaLimeIF
(
input clock_dsp, //DSP Sampling Clock, which can be substantially faster than the other clocks.
input clock_rx, //Rx Clock Interface 2x Sample rate
input clock_tx, //Tx Clock Interface 2x Sample rate
input reset, //Resets configuration and clear... |
module
en, // if zero will reset transpose memory page njumbers
start, // single-cycle start pulse that goes with the first pixel data. Other 63 should follow
xin, // [7:0] - input data
last_in, // output high during input of the last of 64 pixels in a 8x8 block
pre_first_out,... |
module dct_stage1 ( clk,
en,
start, // single-cycle start pulse to replace RST
xin, // [7:0]
we, // write to transpose memory
wr_cntr, // [6:0] transpose memory write address
z_out, //data to transpose memory
page, // transpose memory page just filled (va... |
module dct_stage2 ( clk,
en,
start, // stage 1 finished, data available in transpose memory
page, // transpose memory page finished, valid at start
rd_cntr, // [6:0] transpose memory read address
tdin, // [15:0] - data from transpose memory
endv, // one... |
module mac_test();
reg reset;
reg [31:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
reg tx_clock;
reg carrier_sense;
reg collision;
wire tx_enable;
wire [7:0] tx_data;
reg [31:0] packet [0:380];
i... |
module ovl_always_on_edge (clock, reset, enable, sampling_event, test_expr, fire, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter edge_type = `OVL_EDGE_TYPE_DEFAULT;
//OVL_POSEDGE = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAU... |
module IDELAYCTRL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter SIM_DEVICE = "7SERIES"
)(
output RDY,
input REFCLK,
input RST
);
// define constants
localparam MODULE_NAME = "IDELAYCTRL";
// Parameter encodings and registers
localparam SIM_DEVICE_7SERIES = 0;
localparam SIM_DEVICE... |
module vio_0(clk, probe_out0, probe_out1, probe_out2, probe_out3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0]" */;
input clk;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
endmodule |
module processing_system7_bfm_v2_0_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
... |
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A ... |
module ZUMA_TB_wrapper
(
reset,
clk,
inputs,
outputs
);
parameter LUT_SIZE = ZUMA_LUT_SIZE;
parameter NUM_STAGES = NUM_CONFIG_STAGES;
input clk;
input reset;
input [NUM_INPUTS-1:0] inputs;
output [NUM_OUTPUTS-1:0] outputs;
reg [31:0] next_address;
reg [3... |
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
... |
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_... |
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a221oi base (
... |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ... |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45... |
module sky130_fd_sc_lp__dlybuf4s25kapwr_1 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s25kapwr base (
.X(X),
.A(A)... |
module sky130_fd_sc_lp__dlybuf4s25kapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s25kapwr base (
.X(X),
.A(A)
);
endmodule |
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock ... |
module PA (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys transla... |
module sdram_0_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
... |
module sdram_0_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
z... |
module system_clock_splitter_1_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_1_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodu... |
module system_clock_splitter_1_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edg... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module Byte_to_rgb(color, r, g, b);
input [7:0] color;
output reg[2:0] r, g, b;
always @(color) begin
case(color)
8'b00000000: {r, g, b} = 9'b101000000;
8'b00000001: {r, g, b} = 9'b100011000;
8'b00000010: {r, g, b} = 9'b110000000;
8'b00000011: {r, g, b} = 9'b010110000;
8'b00000100: {r, g, b} = 9'b01... |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba... |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)],... |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;... |
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