module_content stringlengths 18 1.05M |
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module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.... |
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.... |
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.... |
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
a... |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule |
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output ... |
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output ... |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
o... |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
o... |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
o... |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
o... |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
o... |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => S... |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => S... |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => S... |
module axi_infrastructure_v1_1_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module axi_infrastructure_v1_1_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command,... |
module LZD#(parameter SWR=26, parameter EWR=5)(
//#(parameter SWR=55, parameter EWR=6)(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Add_subt_result_i,
/////////////////////////////////////////////7
output wire [EWR-1:0] Shift_Value_o
);
wire [EWR-1:0] Codec_t... |
module LZD#(parameter SWR=26, parameter EWR=5)(
//#(parameter SWR=55, parameter EWR=6)(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Add_subt_result_i,
/////////////////////////////////////////////7
output wire [EWR-1:0] Shift_Value_o
);
wire [EWR-1:0] Codec_t... |
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.... |
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.... |
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;... |
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;... |
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;... |
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;... |
module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
/////////////////////////////////////////////////////////... |
module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
/////////////////////////////////////////////////////////... |
module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
/////////////////////////////////////////////////////////... |
module
wire [W-1:0] intDX; //Output of register DATA_X
wire [W-1:0] intDY; //Output of register DATA_Y
wire intAS; //Output of register add_subt
wire gtXY; //Output for magntiude_comparator (X>Y)
wire eqXY; //Output for magntiude_comparator (X=Y)
wire [W-2:0] intM; //Output of MuxXY for bigger value
wire [W-2:0] intm... |
module
wire [W-1:0] intDX; //Output of register DATA_X
wire [W-1:0] intDY; //Output of register DATA_Y
wire intAS; //Output of register add_subt
wire gtXY; //Output for magntiude_comparator (X>Y)
wire eqXY; //Output for magntiude_comparator (X=Y)
wire [W-2:0] intM; //Output of MuxXY for bigger value
wire [W-2:0] intm... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module soc_design_niosII_core_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
cl... |
module soc_design_JTAG_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
... |
module soc_design_JTAG_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
... |
module soc_design_JTAG_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_... |
module soc_design_JTAG_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
... |
module soc_design_JTAG (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
... |
module soc_design_JTAG_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
... |
module soc_design_JTAG_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
... |
module soc_design_JTAG_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_... |
module soc_design_JTAG_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
... |
module soc_design_JTAG (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
... |
module soc_design_JTAG_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
... |
module soc_design_JTAG_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
... |
module soc_design_JTAG_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_... |
module soc_design_JTAG_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
... |
module soc_design_JTAG (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
... |
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI si... |
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI si... |
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI si... |
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI si... |
module axi_protocol_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI si... |
module salsa (clk, B, Bx, Bo, X0out, Xaddr);
// Latency 16 clock cycles, approx 20nS propagation delay (SLOW!)
input clk;
// input feedback;
input [511:0]B;
input [511:0]Bx;
// output reg [511:0]Bo; // Output is registered
output [511:0]Bo; // Output is async
output [511:0]X0out; // Becomes new X0
output [9:0] Xad... |
module salsa_core (clk, xx, out, Xaddr);
input clk;
input [511:0]xx;
output reg [511:0]out; // Output is registered
output [9:0] Xaddr; // Address output unregistered
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire... |
module axi_protocol_converter_v2_1_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNA... |
module axi_protocol_converter_v2_1_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNA... |
module axi_protocol_converter_v2_1_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNA... |
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register c... |
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register c... |
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register c... |
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register c... |
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_r... |
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_r... |
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_r... |
module processing_system7_v5_5_aw_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side ... |
module processing_system7_v5_5_aw_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side ... |
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