module_content stringlengths 18 1.05M |
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module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module rcn_ram
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter ADDR_BASE = 0;
wire cs;
wire wr;
wire [3:0] mask;
wire [23:0] addr;
wire [31:0] wdata;
wire [31:0] rdata;
rcn_slave #(.ADDR_MASK(24'hFF0000), .ADDR_BASE(ADDR_BASE)) rcn_slave... |
module DataMemory(
output reg [31:0] ReadData,
output reg [31:0] DATO1,
output reg [31:0] DATO2,
output reg [31:0] RESULTADO,
input [31:0] Address,
input [31:0] WriteData,
input [31:0] MouseData,
input MouseEnable,
input WriteEnable,
input CLK
);
reg [31:0] block [0:9];
always @ (*... |
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin... |
module URAM288 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer AUTO_SLEEP_LATENCY = 8,
parameter integer AVG_CONS_INACTIVE_CYCLES = 10,
parameter BWE_MODE_A = "PARITY_INTERLEAVED",
parameter BWE_MODE_B = "PARITY_INTERLEAVED",
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_... |
module pcx_buf_pm_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inp... |
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
re... |
module regfile_tb;
reg clk;
wire [`N-1:0] a,b;
reg [`N-1:0] x;
reg [`K-1:0] sa, sb, d;
reg ld;
regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b);
initial begin
clk = 0;
end
initial begin
$monitor("time:%t\tld: %b\tsa: %d\tsb: %d\td %d\tx: %d\ta: %d\tb: %d", $time, ld, sa, sb,... |
module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves... |
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ... |
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;... |
module mor1kx_branch_prediction
#(
parameter FEATURE_BRANCH_PREDICTOR = "NONE"
)
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
input op_bf_i, // from decode stage, brn is bf
input op_bnf_i, // from decode stage, brn is bn... |
module fir_inj (x_in,clk,y,p_desc0_p_O_FD,p_desc1_p_O_FD,p_desc2_p_O_FD,p_desc3_p_O_FD,p_desc4_p_O_FD,p_desc5_p_O_FD,p_desc6_p_O_FD,p_desc7_p_O_FD,p_desc8_p_O_FD,p_desc9_p_O_FD,p_desc10_p_O_FD,p_desc11_p_O_FD,p_desc12_p_O_FD,p_desc13_p_O_FD,p_desc14_p_O_FD,p_desc15_p_O_FD,p_desc16_p_O_FD,p_desc17_p_O_FD,p_desc18_p_O_FD... |
module mig_7series_v4_0_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = c... |
module carads(
clk,
rst_n_key,
echo1,
echo2,
switch1,
switch2,
key1,
uart_rx,
to_sr,
led7,
led6,
voice,
sda,
scl,
MotorA,
MotorB,
ServoPPM,
uart_tx,
clkout,
MotorPWM,
led5,
num,
sel,
testICC
);
input wire clk;
input wire rst_n_key;
input wire echo1;
input wire echo2;
input wire switch1;
input ... |
module ADT7310P32S16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* inters... |
module escritor_lector_rtc(
input clk,reset,
input [7:0]port_id,in_dato,
input write_strobe,read_strobe,
output reg_a_d,reg_cs,reg_rd,reg_wr,
output reg[7:0]out_dato,
output flag_done,
inout [7:0]dato
);
reg en_funcion;
reg [7:0]addr_RAM,dato_escribir;
wire [7:0]dato_leido;
reg [7:0]next_out_dato;
reg [... |
module Test (
address,
clock,
q);
input [0:0] address;
input clock;
output [15:0] q;
endmodule |
module test_axis_async_frame_fifo_64;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_trea... |
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input ... |
module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule |
module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule |
module HeadFieldExtractor (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
output wire[63:0] headers_data,
output wire headers_last,
... |
module PatternMatch (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] match_data,
output wire match_last,
input wire match_ready,
output wire match_valid
);
assign din_ready = 1'bx;
assign match_data = 64'bxxxxxxxxxxx... |
module Filter (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire cfg_b_ready,
output wire[1:0] cfg... |
module Exporter (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid
);
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxx... |
module AxiSSplitCopy #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 0,
parameter ID_WIDTH = 0,
parameter INTF_CLS = "<class 'hwtLib.amba.axis.AxiStream'>",
parameter IS_BIGENDIAN = 0,
parameter OUTPUTS = 2,
parameter USER_WIDTH = 0,
parameter USE_KEEP = 0,
parameter USE_STRB = ... |
module NetFilter #(
parameter DATA_WIDTH = 64
) (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire... |
module barrel_shifter_synthesis (
rotate, sra, ain, bin, yout
);
input rotate;
input sra;
input [15 : 0] ain;
input [4 : 0] bin;
output [15 : 0] yout;
wire ain_0_IBUF_0;
wire ain_14_IBUF_1;
wire ain_1_IBUF_2;
wire ain_13_IBUF_3;
wire ain_2_IBUF_4;
wire ain_12_IBUF_5;
wire ain_3_IBUF_6;
wire ... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS... |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rda... |
module PeakCurrentHB(clk, cmp, DT, MaxCount, High, Low);
//Inputs and outputs
input clk, cmp;
input [7:0] DT, MaxCount;
output reg High, Low;
//Internal variables
reg [7:0] Counter = 0;
reg [7:0] DTCount = 0;
reg [7:0] MaxDuty = 0;
reg Flag;
//Wires
wire [7:0] Counter_Next, DTCount_Next, MaxDuty_Next;
... |
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
*/
initial
forever #50 clock = ~clock;
initial
begin
four = 4;
yesItAlwaysTure = 1;
yesItAlwyasFalse = 0;
clock = 0;
clear = 1;
/* we may not connect clear to register file and memory becaus... |
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:... |
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
inp... |
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_... |
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module/*{{{*/
FIFO F0 (
.m_aclk(m_aclk), // input m_aclk
.s_aclk(s_aclk), // input s_aclk
.s_aresetn(s_aresetn), // input s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_ax... |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
... |
module main #(
parameter v771499 = "v771499.list"
) (
input vclk,
output [3:0] v894180,
output [0:0] vinit
);
localparam p0 = v771499;
wire [0:7] w1;
wire [0:3] w2;
wire [0:7] w3;
wire w4;
assign v894180 = w2;
assign w4 = vclk;
v6809d2 #(
.v9298ae(p0)
) v60d27e (
.v6d8c97(w1),
.vc4e0ba(w3),
.v6dda2... |
module v6809d2 #(
parameter v9298ae = "v9298ae.list"
) (
input v6dda25,
input [7:0] v6d8c97,
output [7:0] vc4e0ba
);
localparam p3 = v9298ae;
wire w0;
wire w1;
wire w2;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:7] w8;
wire [0:7] w9;
wire w10;
wire [0:31] w11;
wire [0:31] w12;
wire [0:31] w13;
wire ... |
module vf1cffe (
input v6dda25,
input v27dec4,
input [31:0] va0e119,
input v79476f,
input ve9ba68,
output [31:0] v9231ba,
output [31:0] vfc9252,
output [3:0] ve17e80,
output v8d2eee
);
wire w0;
wire [0:31] w1;
wire w2;
wire w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
wire w8;
assign w... |
module vf1cffe_v172245 (
input clk,
input reset,
input [31:0] mem_rdata,
input mem_rbusy,
input mem_wbusy,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [3:0] mem_wmask,
output mem_rstrb
);
localparam RESET_ADDR = 0;
parameter ADDR_WIDTH = 24;
localparam ADDR_PAD = {(32... |
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule |
module v893ac6 #(
parameter vba98fe = "vba98fe.list"
) (
input v6dda25,
input [31:0] v5d7e06,
output [31:0] v9a5b8a
);
localparam p6 = vba98fe;
wire w0;
wire [0:31] w1;
wire w2;
wire [0:31] w3;
wire [0:9] w4;
wire [0:31] w5;
wire w7;
wire [0:31] w8;
wire [0:31] w9;
assign w7 = v6dda25;
assign v9a5b8a = ... |
module v2c97f6 #(
parameter vfffc23 = 0
) (
output [31:0] v7c9bd8
);
localparam p0 = vfffc23;
wire [0:31] w1;
assign v7c9bd8 = w1;
v959751 #(
.vc5c8ea(p0)
) v9f49e7 (
.vbc97e4(w1)
);
endmodule |
module v959751 #(
parameter vc5c8ea = 0
) (
output [31:0] vbc97e4
);
localparam p0 = vc5c8ea;
wire [0:31] w1;
assign vbc97e4 = w1;
v959751_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module v959751_v465065 #(
parameter VALUE = 0
) (
output [31:0] k
);
assign k = VALUE;
endmodule |
module v675d07 #(
parameter v5a4ee6 = "v5a4ee6.list"
) (
input v922e3d,
input [9:0] vb261ad,
input [31:0] v6f4b70,
input v23dc54,
output [31:0] vddff9f
);
localparam p2 = v5a4ee6;
wire w0;
wire w1;
wire [0:9] w3;
wire [0:31] w4;
wire [0:31] w5;
assign w0 = v922e3d;
assign w1 = v23dc54;
assign w3 = vb261a... |
module v675d07_vbaa912 #(
parameter ROMF = 0
) (
input clk,
input [9:0] addr,
input [31:0] data_in,
input wr,
output [31:0] data_out
);
//-- Address with
localparam ADDR_WIDTH = 10;
//-- Data with
localparam DATA_WIDTH = 32;
//-- Size of the memory
localparam SIZE = 1 << ADDR_WIDTH;
//-- Memory itself
... |
module v794b6d (
input [31:0] ve841af,
output [21:0] v51fb1f,
output [9:0] vef1612
);
wire [0:31] w0;
wire [0:9] w1;
wire [0:21] w2;
assign w0 = ve841af;
assign vef1612 = w1;
assign v51fb1f = w2;
v794b6d_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module v794b6d_v9a2a06 (
input [31:0] i,
output [21:0] o1,
output [9:0] o0
);
assign o1 = i[31:10];
assign o0 = i[9:0];
endmodule |
module vaaf5c4 (
input v712289,
input [31:0] v4f6beb,
output [31:0] v51eedb,
output v7e4f0f
);
wire [0:31] w0;
wire w1;
wire w2;
wire [0:30] w3;
wire [0:31] w4;
assign w0 = v4f6beb;
assign v7e4f0f = w1;
assign w2 = v712289;
assign v51eedb = w4;
vecd30a vd4273f (
.ve841af(w0),
.v8d1a42(w1),
.v11ef80(... |
module vecd30a (
input [31:0] ve841af,
output [30:0] v11ef80,
output v8d1a42
);
wire [0:31] w0;
wire w1;
wire [0:30] w2;
assign w0 = ve841af;
assign v8d1a42 = w1;
assign v11ef80 = w2;
vecd30a_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module vecd30a_v9a2a06 (
input [31:0] i,
output [30:0] o1,
output o0
);
assign o1 = i[31:1];
assign o0 = i[0];
endmodule |
module v51b3c0 (
input v411a12,
input [30:0] vd40455,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:30] w1;
wire w2;
assign v7d0a31 = w0;
assign w1 = vd40455;
assign w2 = v411a12;
v51b3c0_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule |
module v51b3c0_v9a2a06 (
input i1,
input [30:0] i0,
output [31:0] o
);
assign o = {i1, i0};
endmodule |
module ve4c3a8 #(
parameter v389bd1 = 5'h1F
) (
input [31:0] v5c832d,
output v4642b6,
output vafdfa0,
output vd02149
);
localparam p8 = v389bd1;
wire w0;
wire w1;
wire w2;
wire [0:14] w3;
wire [0:4] w4;
wire [0:4] w5;
wire [0:4] w6;
wire [0:4] w7;
wire [0:2] w9;
wire [0:31] w10;
wire [0:31] w11;
wire ... |
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule |
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule |
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule |
module v9a2795 (
input [2:0] vdee7c7,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:2] w2;
wire w3;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = vdee7c7;
assign vda577d = w3;
v9a2795_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2),
.o2(w3)
);
endmodule |
module v9a2795_v9a2a06 (
input [2:0] i,
output o2,
output o1,
output o0
);
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module va7b832 (
input [31:0] ve841af,
output [16:0] v62a8c1,
output [14:0] v29a212
);
wire [0:31] w0;
wire [0:14] w1;
wire [0:16] w2;
assign w0 = ve841af;
assign v29a212 = w1;
assign v62a8c1 = w2;
va7b832_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module va7b832_v9a2a06 (
input [31:0] i,
output [16:0] o1,
output [14:0] o0
);
assign o1 = i[31:15];
assign o0 = i[14:0];
endmodule |
module vef0f91 (
input [14:0] vcbe66f,
output [4:0] vfa86aa,
output [9:0] vbdb2c8
);
wire [0:14] w0;
wire [0:9] w1;
wire [0:4] w2;
assign w0 = vcbe66f;
assign vbdb2c8 = w1;
assign vfa86aa = w2;
vef0f91_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module vef0f91_v9a2a06 (
input [14:0] i,
output [4:0] o1,
output [9:0] o0
);
assign o1 = i[14:10];
assign o0 = i[9:0];
endmodule |
module v1cc648 (
input [4:0] vd80e4f,
input [4:0] vfad888,
output v4642b6
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w1 = vfad888;
assign w2 = vd80e4f;
v23b15b vc1b29d (
.v4642b6(w3),
.v27dec4(w5),
.v6848e... |
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule |
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule |
module v91f34c (
input [4:0] v427dd1,
output v53baa6,
output [3:0] v479af4
);
wire [0:3] w0;
wire [0:4] w1;
wire w2;
assign v479af4 = w0;
assign w1 = v427dd1;
assign v53baa6 = w2;
v91f34c_v9a2a06 v9a2a06 (
.o0(w0),
.i(w1),
.o1(w2)
);
endmodule |
module v91f34c_v9a2a06 (
input [4:0] i,
output o1,
output [3:0] o0
);
assign o1 = i[4];
assign o0 = i[3:0];
endmodule |
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15... |
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w... |
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0... |
module v108a6d #(
parameter vfffc23 = 0
) (
output [4:0] v6ece80
);
localparam p0 = vfffc23;
wire [0:4] w1;
assign v6ece80 = w1;
v3693fc #(
.vc5c8ea(p0)
) ve88537 (
.vc8d3b9(w1)
);
endmodule |
module v3693fc #(
parameter vc5c8ea = 0
) (
output [4:0] vc8d3b9
);
localparam p0 = vc5c8ea;
wire [0:4] w1;
assign vc8d3b9 = w1;
v3693fc_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module v3693fc_v465065 #(
parameter VALUE = 0
) (
output [4:0] k
);
assign k = VALUE;
endmodule |
module ve500df (
input [31:0] ve841af,
output [28:0] vfc82fb,
output [2:0] vbb2522
);
wire [0:31] w0;
wire [0:2] w1;
wire [0:28] w2;
assign w0 = ve841af;
assign vbb2522 = w1;
assign vfc82fb = w2;
ve500df_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module ve500df_v9a2a06 (
input [31:0] i,
output [28:0] o1,
output [2:0] o0
);
assign o1 = i[31:3];
assign o0 = i[2:0];
endmodule |
module vf68661 (
input v6dda25,
input [31:0] vf837fe,
input [3:0] ve9e5a1,
input ve146f6,
output [7:0] vfeb41a
);
wire w0;
wire [0:7] w1;
wire w2;
wire [0:7] w3;
wire w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
assign vfeb41a = w3;
assign w4 = v6dda25;
assign w5 = vf837fe;
assign w6 = ve9e5a1;
assign ... |
module vf61fa3 (
input [3:0] vaf45b8,
output vcbab45
);
wire w0;
wire [0:3] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign vcbab45 = w0;
assign w1 = vaf45b8;
vc4f23a v5f4674 (
.v985fcb(w1),
.v4f1fd3(w2),
.vda577d(w3),
.v3f8943(w4),
.v64d863(w5)
);
vf49321 vea932e (
.vcbab45(w0),
.ve86251(w2),... |
module vf49321 (
input ve86251,
input v0e28cb,
input v3ca442,
input v8b2684,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = ve86251;
assign w1 = v0e28cb;
assign w3 = v3ca442;
assign vcbab45 = w5;
assign w6 = v8b2684;
v873425 v1edc96 (
.v0e28cb(w0),
.v3... |
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule |
module v468a05 (
input [31:0] ve841af,
output [7:0] vdd0469,
output [7:0] v4ba85d,
output [7:0] vf93ecb,
output [7:0] vc6471a
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign w0 = ve841af;
assign vc6471a = w1;
assign vf93ecb = w2;
assign v4ba85d = w3;
assign vdd0469 =... |
module v468a05_v9a2a06 (
input [31:0] i,
output [7:0] o3,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o3 = i[32:24];
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule |
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
... |
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule |
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule |
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule |
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule |
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
a... |
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 ... |
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