Add float32 circuits and 32-bit arithmetic support
CharlesCNorton
1493f19
Increase float16 randomized test coverage
CharlesCNorton
d7c41b6
Raise sample sizes for float16 arithmetic, conversion, unary, and pow tests.
Fix float16.mul normalization/rounding gates
CharlesCNorton
ae83247
Add wider product shifts and subnormal mux/sticky handling; separate exp overflow/underflow gates; regenerate arithmetic.safetensors.
Run input-coverage sweep by default
CharlesCNorton
7ba34aa
- Always evaluate gates via .inputs to cover routing tensors\n- Make full coverage the standard eval behavior
Add implicit multiplication to expression parser
CharlesCNorton
7b8a56c
- Tokenize infix expressions with identifiers and scientific notation\n- Insert implicit '*' between adjacent values (e.g., 2pi, 3(4+5))\n- Keep function calls intact when followed by parentheses
Add float16 classification LUT ops
CharlesCNorton
ce521af
- Generate LUT-backed is_nan/is_inf/is_finite/is_zero/is_subnormal/is_normal/is_negative circuits\n- Extend float16 unary eval expectations and tests for classification ops\n- Expose classification functions in calculator dispatch\n- Rebuild arithmetic.safetensors with new classification tensors
Add float16 deg2rad/rad2deg circuits
CharlesCNorton
7fc245f
- Add deg2rad/rad2deg to unary op LUT build and gate input inference\n- Extend eval expected-value logic and float16 unary tests for deg2rad/rad2deg\n- Wire calculator function dispatch for deg2rad/rad2deg\n- Rebuild arithmetic.safetensors with the new LUT tensors
Add float16 constant circuits
CharlesCNorton
313da7e
Add checked outputs for domain ops
CharlesCNorton
ad82d36
Add float16 domain flags
CharlesCNorton
55eb692
Add degree-mode trig LUTs
CharlesCNorton
3c7f544
Add float16 scientific LUT ops
CharlesCNorton
b8c48ca
Batch per-level gate evaluation
CharlesCNorton
ca6659c
Cache circuits and add RPN evaluator
CharlesCNorton
81c511c
- Precompile gate ops and external specs for faster evaluation
- Add RPN evaluation to support front-end parsing
Add gate-level calculator UI and CLI expr mode
CharlesCNorton
58a9bad
- Add calculator.py expression evaluator with JSON/strict output for float16 gate-only eval
- Add Gradio Space app.py + requirements.txt for proof-of-concept UI
- Update README with Space notes and expanded TODO/caveats
Refresh README format + repro details
CharlesCNorton
ca99a3e
- fix encoding artifacts and ASCII-only notation
- add float16 architecture overview and step-by-step
- document format_version, signal registry, and .inputs resolution
- add reproduce steps with expected runtimes
- normalize subnormal inputs via CLZ+1 and 11-bit barrel shifters (a_norm_s/b_norm_s)
- add raw implicit signals and shift gating for subnormal-only normalization
- adjust exponent math with exp_sub_a/exp_sub_ab (subtract a_shift, add b_shift)
- correct shift encoding to clz+1 and align shift_raw bit maps
- detect underflow via exp_norm sign bit or zero to drive subnormal/zero outputs
- rewire div inference to new normalization/exp paths and rebuild arithmetic.safetensors
- update README counts + TODO list
Rebuild float16.mul normalization/subnormal rounding; invert div subtractor inputs
CharlesCNorton
f9d40cf
- float16.mul: add norm_shift detection (CLZ-style) and 12-bit left barrel shifter stages (lshift_s0..s3) feeding normalization and rounding guard/sticky paths.
- float16.mul: compute exp_dec using not_norm_shift_sub, introduce sub_shift_base/sub_shift adders and subnormal right barrel shifter (sub_rshift_s0..s3) to drive sub_mant/sub_guard/sub_sticky.
- float16.mul: adjust norm_mant selection to use lshift_s3 and add eq10 special path for edge subnormal normalization cases; wire norm_shifted_out/sticky_norm_ext for rounding.
- float16.mul: fix exp_overflow_to_inf to use exp_overflow_any + round_exp_all_ones and gate result_is_inf via overflow path; add exp_sub_borrow/exp_underflow and subnorm_enable plumbing.
- float16.div: add not_div_b/not_implicit_b inverters and route subtractor b inputs through complements (+1) to enable proper remainder subtraction in long division.
- build outputs: add weights/biases for new gates (norm_shift_eq10, sub_shift, subnorm_enable, exp_overflow_to_inf…
Add randomized float16 tests and document open issues
CharlesCNorton
10e432e
Make inputs coverage strict and document full verbose runs
CharlesCNorton
e669ef2
Add semantic tests for orphan selector/comparator tensors
CharlesCNorton
5ad204f
Add inputs-coverage sweep and document coverage run
CharlesCNorton
d4442da
Fix multiplier8x8 signal registry to use full gate names
CharlesCNorton
f9ba712
Problem:
The signal registry used canonical names like 'stage0.bit0' for inter-stage
connections in the 8x8 multiplier, but the actual gates that produce these
outputs are named 'stage0.bit0.ha2.sum.layer2'. This mismatch prevented
the evaluator from properly tracing signal flow through the multiplier's
adder tree.
Changes to infer_multiplier_inputs() in build.py:
1. Changed prev_bit registration from canonical to full gate name:
- Before: f'{prefix}.stage{stage-1}.bit{bit}'
- After: f'{prefix}.stage{stage-1}.bit{bit}.ha2.sum.layer2'
The ha2.sum.layer2 suffix reflects that the bit output comes from
the second half-adder's XOR (sum) gate, which is a 2-layer network
where layer2 is the final AND of the OR and NAND outputs.
2. Added bounds check for stage 0 partial products:
- Before: Always registered f'{prefix}.pp.r0.c{bit}'
- After: Only if bit < size, otherwise use constant #0
This handles the case where bit positions exceed the partial
product array …
Fix signal registry to use actual gate names instead of canonical aliases
CharlesCNorton
86302ab
Problem: The signal registry used canonical names (e.g., 'ha1.sum', 'cout')
but the actual gates have different names (e.g., 'ha1.sum.layer2', 'carry_or').
This caused eval to fail when storing gate outputs because name_to_id lookups
returned None for the actual gate names.
Changes to build.py:
1. infer_fulladder_inputs():
- Changed ha1.sum -> ha1.sum.layer2
- The XOR gate's final output is layer2, not a bare 'sum'
2. infer_ripplecarry_inputs():
- Changed fa{idx-1}.cout -> fa{idx-1}.carry_or
- The carry output gate is named carry_or, not cout
- Changed ha1.sum -> ha1.sum.layer2
- Added .or_carry to carry gate detection (some circuits use this variant)
3. infer_multiplier_inputs():
- Changed bit{bit-1}.cout -> bit{bit-1}.carry_or
- Changed ha1.sum -> ha1.sum.layer2
- Added .or_carry to carry gate detection
4. main():
- Added registry.register(gate) after inferring inputs
- This ensures every gate with inferred inputs is registered
- Allows eval t…
Remove dead routing code from eval.py
CharlesCNorton
947fcab
Rename build script, delete dead routing.json
CharlesCNorton
88fca93
Rewrite README: cut marketing fluff, focus on float16
CharlesCNorton
65db75b
Fix sbc8bit test: pass borrow input to subtractor eval
CharlesCNorton
b933255
PROBLEM:
- arithmetic.sbc8bit was failing 67/134 tests
- Test had borrow variable but never passed it to eval_subtractor
- eval_subtractor defaulted to carry_in=1, which is correct for sub8bit
but wrong for sbc8bit which takes external borrow input
ANALYSIS:
- sbc8bit has $cin input (signal 2355) for borrow
- $cin goes directly into fa0.xor2 (first full adder's carry input)
- No carry_in gate like sub8bit has
FIX:
1. Modified eval_subtractor() to accept optional initial_carry parameter
2. Updated sbc8bit test to compute: initial_carry = 1.0 - borrow
- When borrow=0: carry_in=1, computes a - b
- When borrow=1: carry_in=0, computes a - b - 1
MATH:
- sbc computes: a - b - borrow
- Using two's complement: a + ~b + ~borrow
- So carry_in = ~borrow (inverted borrow)
RESULT:
- arithmetic.sbc8bit: 67/134 -> 134/134 PASS
- Overall: 206,124/206,124 (100.0000%)
- Fitness: 1.000000
All circuits now pass!
CIRCUIT FIXES (convert_to_explicit_inputs.py):
1. BITWISE SHIFT CIRCUITS (asr8bit, rol8bit, ror8bit):
- Old weights were all [1.0] selecting only x[0] for every output
- Added build_bitwise_shift_tensors() with correct weights:
* ASR: bit[i] = x[i+1] for i<7, bit[7] = x[7] (sign extension)
* ROL: bit[0] = x[7], bit[i] = x[i-1] for i>0
* ROR: bit[i] = x[i+1] for i<7, bit[7] = x[0]
- Each output gate now has proper weight vector to select correct input bit
2. SYMMETRY8BIT CIRCUIT:
- Old XNOR gates had weights [1,1] with no bias (acted as OR, not XNOR)
- Added build_symmetry8bit_tensors() with proper 2-layer XNOR:
* Layer 1: AND gate (weight selects pair, bias -1.5 requires both)
* Layer 1: NOR gate (negative weights, bias 0 fires when both 0)
* Layer 2: OR of AND and NOR outputs (fires when a==b)
- Final AND gate combines 4 XNOR results (bias -3.5 requires all 4)
3. SUBTRACTOR EVAL FIX (eval.py):
- eval_subtractor() now properly handl…
EVAL.PY CHANGES:
- Add eval_subtractor() helper for 8-bit subtraction via full adders
- Add eval_negation() helper for two's complement negation
- Add eval_xnor_gate() helper for XNOR evaluation
- Add test_bitwise() for asr8bit, rol8bit, ror8bit circuits
- Add "bitwise" category to CATEGORIES
ADDER TESTS:
- Add arithmetic.sub8bit test (8-bit subtractor)
- Add arithmetic.neg8bit test (two's complement negation)
- Add arithmetic.adc8bit test (add with carry)
- Add arithmetic.sbc8bit test (subtract with borrow)
COMPARATOR TESTS:
- Add arithmetic.cmp8bit test (8-bit comparator via subtraction)
- Add arithmetic.equality8bit test (8-bit equality via XNOR chain)
MULTIPLIER TESTS:
- Add arithmetic.multiplier2x2 test (2x2 partial products)
MODULAR TESTS:
- Fix test_modular() to handle power-of-2 mods (mod2/4/8) separately
- Power-of-2 mods use simple bit extraction (out0, out1, out2)
- Non-power-of-2 mods use layer1.geq/leq structure
PATTERN RECOGNITION:
- Add proper symmetry8bit test (pal…
Integrate roadmap into README, clarify LLM runtime purpose
CharlesCNorton
7090afb
Expand TODO with comprehensive LLM coprocessor operations
CharlesCNorton
c94d9ea
Fix float16.mul/div circuit bugs and eval tests
CharlesCNorton
1a5962e
- float16.mul: Fix signal registration order for carry_acc_carry gates
Signals were being returned before registration, causing prod2_fa
gates to reference non-existent signals (ID: -1)
- float16.div: Fix result_is_inf/result_is_zero logic gates
Changed from OR gate (bias=-1) to proper AND gate (weights=[1,1,2],
bias=-2.5) to prevent firing when only not_result_is_nan=1
- eval.py: Replace placeholder tests with actual circuit evaluation
for float16.mul and float16.div using signal registry
All 7177 tests now pass (100%)
Fix float16.mul multi-bit carry propagation with two-pass ripple carry
CharlesCNorton
acf0072
Added prod2_fa (22 full adders) as second pass after prod_fa to incorporate
carry_acc_carry signals. This resolves the issue where secondary carries from
column accumulation were not being propagated into the final product bits.
Changes:
- Added prod2_fa0-21 full adders in build_float16_mul()
- Added inference logic for prod2_fa gates in infer_inputs()
- Updated prod_overflow and norm_mant to use prod2_fa output
Unify eval.py and arithmetic_eval.py into single evaluator
CharlesCNorton
84bf860
Merge both evaluation scripts into a unified eval.py with CLI args:
- --category/-c: run specific test categories
- --circuit: filter by circuit name
- --quick/-q: fast smoke test mode
- --verbose/-v: detailed output
- --json/-j: CI-friendly JSON output
- --coverage: tensor coverage report
- --list/-l: list available categories
Categories: boolean, threshold, clz, adders, comparators,
multiplier, divider, modular, combinational, pattern,
float16_basic, float16_arith, float16_conv
Remove redundant arithmetic_eval.py.
Remove tensors_arithmetic_only.txt
CharlesCNorton
54bb20f
Remove legacy safetensors file
CharlesCNorton
930f9bd
Add multi-bit carry infrastructure for float16.mul/div
PortfolioAI
32f7c0d
- Add col_bit2 (floor/4 mod 2) and col_bit3 (floor/8 mod 2) gates
- Add carry accumulator gates for positions receiving multiple carries
- Update TODO.md with detailed remaining work documentation
- Move completed float16 circuits to Completed section
Mul/div still failing due to carry_acc_carry propagation issue.
Proper fix requires Wallace/Dadda tree or secondary carry chain.
Fix toint, fromint; improve mul/div inference
PortfolioAI
fd6cf07
- float16.toint: 93/93 (fixed not_mag regex, added output gating)
- float16.fromint: 53/53 (fixed clz_and/not_in regex, added not_is_zero)
- float16.mul: 3/84 -> 13/84 (fixed not_15_bits, carry logic, NaN bit 9)
- float16.div: 2/53 -> 5/53 (fixed NaN bit 9)
Remaining: mul/div col_sum precision needs full adder trees
Update TODO.md with toint progress
PortfolioAI
4479be9
Rewrite float16.toint with right-shift barrel shifter
PortfolioAI
48421e0
- Changed from left-shift to right-shift (25-exp positions)
- Improved from 31/93 to 54/93 tests passing
- Still needs debugging for remaining edge cases
Note algorithm bugs in mul/div/toint/fromint build functions
PortfolioAI
1bcc911
- toint: needs right-shift support (only has left-shift)
- mul/div/fromint: similar algorithm issues
Working: add (125/125), sub (115/115), all supporting ops
Fix inference functions for mul/div/toint/fromint
PortfolioAI
d8cb687
- Fixed prod_fa column references for single-PP columns (0,20)
- Pre-register subtractor outputs for div q_bit
- Register all needed not_ge values for fromint CLZ
- Register float16.add outputs for sub circuit
Tests now run but produce wrong results (circuit logic bugs remain)
Add float16.sub tests (115/115 passing)
PortfolioAI
b409c55
- float16.sub tested via float16.add with negated b
- Test functions added for mul/div/toint/fromint (disabled pending inference fixes)
Add inference functions for float16 sub/mul/div/toint/fromint
PortfolioAI
c89bccf
All 7269 gates now have inferred inputs (0 missing).
Add build functions for float16 sub/mul/div/toint/fromint
float16.add: add subnormal support (125/125 tests)
PortfolioAI
d0106fe
- Added adjusted exponent bit 0: a_adj_exp0 = a_exp[0] OR exp_a_zero
- Subnormals (exp=0) now treated with effective exponent=1
- Updated exponent comparison, diff, and larger selection
- Full IEEE 754 compliance for float16 addition
float16.add: include guard bit in arithmetic (123/125 tests)
PortfolioAI
c757635
- Extended mantissa operands to 12 bits (11 mant + 1 guard)
- Extended adder from 12-bit to 13-bit for overflow handling
- Updated CLZ and barrel shifter to operate on 12 bits
- Fixed rounding bug in subtraction by proper guard bit propagation
- Remaining failures are subnormal numbers (documented limitation)
Fix float16.add zero+zero case (94/125 tests)
PortfolioAI
aaeb609
- Added both_are_zero special case detection
- is_normal_result now checks NOT nan AND NOT inf AND NOT both_zero
- Zero+zero now correctly outputs 0x0000
Remaining: subtraction (different signs) still has bugs
