id
int64 0
755k
| file_name
stringlengths 3
109
| file_path
stringlengths 13
185
| content
stringlengths 31
9.38M
| size
int64 31
9.38M
| language
stringclasses 1
value | extension
stringclasses 11
values | total_lines
int64 1
340k
| avg_line_length
float64 2.18
149k
| max_line_length
int64 7
2.22M
| alphanum_fraction
float64 0
1
| repo_name
stringlengths 6
65
| repo_stars
int64 100
47.3k
| repo_forks
int64 0
12k
| repo_open_issues
int64 0
3.4k
| repo_license
stringclasses 9
values | repo_extraction_date
stringclasses 92
values | exact_duplicates_redpajama
bool 2
classes | near_duplicates_redpajama
bool 2
classes | exact_duplicates_githubcode
bool 2
classes | exact_duplicates_stackv2
bool 1
class | exact_duplicates_stackv1
bool 2
classes | near_duplicates_githubcode
bool 2
classes | near_duplicates_stackv1
bool 2
classes | near_duplicates_stackv2
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15,876
|
ajm_error.h
|
shadps4-emu_shadPS4/src/core/libraries/ajm/ajm_error.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
constexpr int ORBIS_AJM_ERROR_UNKNOWN = 0x80930001;
constexpr int ORBIS_AJM_ERROR_INVALID_CONTEXT = 0x80930002;
constexpr int ORBIS_AJM_ERROR_INVALID_INSTANCE = 0x80930003;
constexpr int ORBIS_AJM_ERROR_INVALID_BATCH = 0x80930004;
constexpr int ORBIS_AJM_ERROR_INVALID_PARAMETER = 0x80930005;
constexpr int ORBIS_AJM_ERROR_OUT_OF_MEMORY = 0x80930006;
constexpr int ORBIS_AJM_ERROR_OUT_OF_RESOURCES = 0x80930007;
constexpr int ORBIS_AJM_ERROR_CODEC_NOT_SUPPORTED = 0x80930008;
constexpr int ORBIS_AJM_ERROR_CODEC_ALREADY_REGISTERED = 0x80930009;
constexpr int ORBIS_AJM_ERROR_CODEC_NOT_REGISTERED = 0x8093000A;
constexpr int ORBIS_AJM_ERROR_WRONG_REVISION_FLAG = 0x8093000B;
constexpr int ORBIS_AJM_ERROR_FLAG_NOT_SUPPORTED = 0x8093000C;
constexpr int ORBIS_AJM_ERROR_BUSY = 0x8093000D;
constexpr int ORBIS_AJM_ERROR_BAD_PRIORITY = 0x8093000E;
constexpr int ORBIS_AJM_ERROR_IN_PROGRESS = 0x8093000F;
constexpr int ORBIS_AJM_ERROR_RETRY = 0x80930010;
constexpr int ORBIS_AJM_ERROR_MALFORMED_BATCH = 0x80930011;
constexpr int ORBIS_AJM_ERROR_JOB_CREATION = 0x80930012;
constexpr int ORBIS_AJM_ERROR_INVALID_OPCODE = 0x80930013;
constexpr int ORBIS_AJM_ERROR_PRIORITY_VIOLATION = 0x80930014;
constexpr int ORBIS_AJM_ERROR_BUFFER_TOO_BIG = 0x80930015;
constexpr int ORBIS_AJM_ERROR_INVALID_ADDRESS = 0x80930016;
constexpr int ORBIS_AJM_ERROR_CANCELLED = 0x80930017;
| 1,488
|
C++
|
.h
| 26
| 56.153846
| 68
| 0.823973
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,877
|
ajm_at9.h
|
shadps4-emu_shadPS4/src/core/libraries/ajm/ajm_at9.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
#include "core/libraries/ajm/ajm_instance.h"
#include "libatrac9.h"
#include <span>
namespace Libraries::Ajm {
constexpr s32 ORBIS_AJM_DEC_AT9_MAX_CHANNELS = 8;
enum AjmAt9CodecFlags : u32 {
ParseRiffHeader = 1 << 0,
NonInterleavedOutput = 1 << 8,
};
DECLARE_ENUM_FLAG_OPERATORS(AjmAt9CodecFlags)
struct AjmSidebandDecAt9CodecInfo {
u32 super_frame_size;
u32 frames_in_super_frame;
u32 next_frame_size;
u32 frame_samples;
};
struct AjmAt9Decoder final : AjmCodec {
explicit AjmAt9Decoder(AjmFormatEncoding format, AjmAt9CodecFlags flags);
~AjmAt9Decoder() override;
void Reset() override;
void Initialize(const void* buffer, u32 buffer_size) override;
void GetInfo(void* out_info) const override;
AjmSidebandFormat GetFormat() const override;
u32 GetNextFrameSize(const AjmInstanceGapless& gapless) const override;
std::tuple<u32, u32> ProcessData(std::span<u8>& input, SparseOutputBuffer& output,
AjmInstanceGapless& gapless) override;
private:
template <class T>
size_t WriteOutputSamples(SparseOutputBuffer& output, u32 skipped_samples, u32 max_samples) {
std::span<T> pcm_data{reinterpret_cast<T*>(m_pcm_buffer.data()),
m_pcm_buffer.size() / sizeof(T)};
pcm_data = pcm_data.subspan(skipped_samples * m_codec_info.channels);
const auto pcm_size = std::min(u32(pcm_data.size()), max_samples);
return output.Write(pcm_data.subspan(0, pcm_size));
}
const AjmFormatEncoding m_format;
const AjmAt9CodecFlags m_flags;
void* m_handle{};
u8 m_config_data[ORBIS_AT9_CONFIG_DATA_SIZE]{};
u32 m_superframe_bytes_remain{};
u32 m_num_frames{};
Atrac9CodecInfo m_codec_info{};
std::vector<u8> m_pcm_buffer;
};
} // namespace Libraries::Ajm
| 1,992
|
C++
|
.h
| 49
| 35.326531
| 97
| 0.709326
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,878
|
screenshot.h
|
shadps4-emu_shadPS4/src/core/libraries/screenshot/screenshot.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Core::Loader {
class SymbolsResolver;
}
namespace Libraries::ScreenShot {
int PS4_SYSV_ABI _Z5dummyv();
int PS4_SYSV_ABI sceScreenShotCapture();
int PS4_SYSV_ABI sceScreenShotDisable();
int PS4_SYSV_ABI sceScreenShotDisableNotification();
int PS4_SYSV_ABI sceScreenShotEnable();
int PS4_SYSV_ABI sceScreenShotEnableNotification();
int PS4_SYSV_ABI sceScreenShotGetAppInfo();
int PS4_SYSV_ABI sceScreenShotGetDrcParam();
int PS4_SYSV_ABI sceScreenShotIsDisabled();
int PS4_SYSV_ABI sceScreenShotIsVshScreenCaptureDisabled();
int PS4_SYSV_ABI sceScreenShotSetOverlayImage();
int PS4_SYSV_ABI sceScreenShotSetOverlayImageWithOrigin();
int PS4_SYSV_ABI sceScreenShotSetParam();
int PS4_SYSV_ABI sceScreenShotSetDrcParam();
void RegisterlibSceScreenShot(Core::Loader::SymbolsResolver* sym);
} // namespace Libraries::ScreenShot
| 989
|
C++
|
.h
| 24
| 40
| 66
| 0.834375
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,879
|
fiber.h
|
shadps4-emu_shadPS4/src/core/libraries/fiber/fiber.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/assert.h"
#include "common/types.h"
namespace Core::Loader {
class SymbolsResolver;
}
namespace Libraries::Fiber {
#define ORBIS_FIBER_MAX_NAME_LENGTH (31)
typedef void PS4_SYSV_ABI (*SceFiberEntry)(u64 argOnInitialize, u64 argOnRun);
enum FiberState : u32 {
None = 0u,
Init = 1u,
Run = 2u,
Suspend = 3u,
};
struct SceFiber {
u64 signature;
FiberState state;
SceFiberEntry entry;
u64 argOnInitialize;
u64 argRun;
u64* pArgRun;
u64 argReturn;
u64* pArgReturn;
u64 sizeContext;
char name[ORBIS_FIBER_MAX_NAME_LENGTH];
void* handle;
};
static_assert(sizeof(SceFiber) <= 256);
struct SceFiberInfo {
u64 size;
SceFiberEntry entry;
u64 argOnInitialize;
void* addrContext;
u64 sizeContext;
char name[ORBIS_FIBER_MAX_NAME_LENGTH + 1];
u64 sizeContextMargin;
};
static_assert(sizeof(SceFiberInfo) <= 128);
typedef void* SceFiberOptParam;
s32 PS4_SYSV_ABI sceFiberInitialize(SceFiber* fiber, const char* name, SceFiberEntry entry,
u64 argOnInitialize, void* addrContext, u64 sizeContext,
const SceFiberOptParam* optParam);
s32 PS4_SYSV_ABI sceFiberOptParamInitialize(SceFiberOptParam* optParam);
s32 PS4_SYSV_ABI sceFiberFinalize(SceFiber* fiber);
s32 PS4_SYSV_ABI sceFiberRun(SceFiber* fiber, u64 argOnRunTo, u64* argOnReturn);
s32 PS4_SYSV_ABI sceFiberSwitch(SceFiber* fiber, u64 argOnRunTo, u64* argOnRun);
s32 PS4_SYSV_ABI sceFiberGetSelf(SceFiber** fiber);
s32 PS4_SYSV_ABI sceFiberReturnToThread(u64 argOnReturn, u64* argOnRun);
s32 PS4_SYSV_ABI sceFiberGetInfo(SceFiber* fiber, SceFiberInfo* fiberInfo);
s32 PS4_SYSV_ABI sceFiberStartContextSizeCheck(u32 flags);
s32 PS4_SYSV_ABI sceFiberStopContextSizeCheck(void);
s32 PS4_SYSV_ABI sceFiberRename(SceFiber* fiber, const char* name);
void RegisterlibSceFiber(Core::Loader::SymbolsResolver* sym);
} // namespace Libraries::Fiber
| 2,184
|
C++
|
.h
| 57
| 32.631579
| 93
| 0.728805
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,880
|
symbols_resolver.h
|
shadps4-emu_shadPS4/src/core/loader/symbols_resolver.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <filesystem>
#include <span>
#include <string>
#include <vector>
#include "common/types.h"
namespace Core::Loader {
enum class SymbolType {
Unknown,
Function,
Object,
Tls,
NoType,
};
struct SymbolRecord {
std::string name;
std::string nid_name;
u64 virtual_address;
};
struct SymbolResolver {
std::string name;
std::string nidName;
std::string library;
u16 library_version;
std::string module;
u8 module_version_major;
u8 module_version_minor;
SymbolType type;
};
class SymbolsResolver {
public:
SymbolsResolver() = default;
virtual ~SymbolsResolver() = default;
void AddSymbol(const SymbolResolver& s, u64 virtual_addr);
const SymbolRecord* FindSymbol(const SymbolResolver& s) const;
void DebugDump(const std::filesystem::path& file_name);
std::span<const SymbolRecord> GetSymbols() const {
return m_symbols;
}
size_t GetSize() const noexcept {
return m_symbols.size();
}
static std::string GenerateName(const SymbolResolver& s);
static std::string_view SymbolTypeToS(SymbolType sym_type) {
switch (sym_type) {
case SymbolType::Unknown:
return "Unknown";
case SymbolType::Function:
return "Function";
case SymbolType::Object:
return "Object";
case SymbolType::Tls:
return "Tls";
case SymbolType::NoType:
return "NoType";
}
}
private:
std::vector<SymbolRecord> m_symbols;
};
} // namespace Core::Loader
| 1,700
|
C++
|
.h
| 63
| 21.809524
| 66
| 0.674476
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,881
|
elf.h
|
shadps4-emu_shadPS4/src/core/loader/elf.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include <string>
#include <vector>
#include "common/io_file.h"
#include "common/types.h"
struct self_header {
static constexpr u32 signature = 0x1D3D154Fu;
u32 magic;
u8 version;
u8 mode;
u8 endian; // 1 is little endian
u8 attributes;
u8 category;
u8 program_type;
u16 padding1;
u16 header_size;
u16 meta_size;
u32 file_size;
u32 padding2;
u16 segment_count;
u16 unknown1A; // always 0x22
u32 padding3;
};
struct self_segment_header {
bool IsBlocked() const {
return (flags & 0x800) != 0; // 0 or 0x800
}
u32 GetId() const {
return (flags >> 20u) & 0xFFFu;
}
bool IsOrdered() const {
return (flags & 1) != 0; // 0 or 1
}
bool IsEncrypted() const {
return (flags & 2) != 0; // 0 or 2
}
bool IsSigned() const {
return (flags & 4) != 0; // 0 or 4
}
bool IsCompressed() const {
return (flags & 8) != 0; // 0 or 8
}
u64 flags;
u64 file_offset;
u64 file_size;
u64 memory_size;
};
constexpr u8 EI_MAG0 = 0; /* e_ident[] indexes */
constexpr u8 EI_MAG1 = 1;
constexpr u8 EI_MAG2 = 2;
constexpr u8 EI_MAG3 = 3;
constexpr u8 EI_CLASS = 4;
constexpr u8 EI_DATA = 5;
constexpr u8 EI_VERSION = 6;
constexpr u8 EI_OSABI = 7;
constexpr u8 EI_ABIVERSION = 8;
// Magic number
constexpr u8 ELFMAG0 = 0x7F;
constexpr u8 ELFMAG1 = 'E';
constexpr u8 ELFMAG2 = 'L';
constexpr u8 ELFMAG3 = 'F';
typedef enum : u16 {
ET_NONE = 0x0,
ET_REL = 0x1,
ET_EXEC = 0x2,
ET_DYN = 0x3,
ET_CORE = 0x4,
ET_SCE_EXEC = 0xfe00,
ET_SCE_STUBLIB = 0xfe0c,
ET_SCE_DYNEXEC = 0xfe10,
ET_SCE_DYNAMIC = 0xfe18
} e_type_s;
typedef enum : u16 {
EM_NONE = 0, /* No machine */
EM_M32 = 1, /* AT&T WE 32100 */
EM_SPARC = 2, /* SPARC */
EM_386 = 3, /* Intel 80386 */
EM_68K = 4, /* Motorola 68000 */
EM_88K = 5, /* Motorola 88000 */
EM_860 = 7, /* Intel 80860 */
EM_MIPS = 8, /* MIPS I Architecture */
EM_S370 = 9, /* IBM System/370 Processor */
EM_MIPS_RS3_LE = 10, /* MIPS RS3000 Little-endian */
EM_PARISC = 15, /* Hewlett-Packard PA-RISC */
EM_VPP500 = 17, /* Fujitsu VPP500 */
EM_SPARC32PLUS = 18, /* Enhanced instruction set SPARC */
EM_960 = 19, /* Intel 80960 */
EM_PPC = 20, /* PowerPC */
EM_PPC64 = 21, /* 64-bit PowerPC */
EM_S390 = 22, /* IBM System/390 Processor */
EM_V800 = 36, /* NEC V800 */
EM_FR20 = 37, /* Fujitsu FR20 */
EM_RH32 = 38, /* TRW RH-32 */
EM_RCE = 39, /* Motorola RCE */
EM_ARM = 40, /* Advanced RISC Machines ARM */
EM_ALPHA = 41, /* Digital Alpha */
EM_SH = 42, /* Hitachi SH */
EM_SPARCV9 = 43, /* SPARC Version 9 */
EM_TRICORE = 44, /* Siemens TriCore embedded processor */
EM_ARC = 45, /* Argonaut RISC Core, Argonaut Technologies Inc. */
EM_H8_300 = 46, /* Hitachi H8/300 */
EM_H8_300H = 47, /* Hitachi H8/300H */
EM_H8S = 48, /* Hitachi H8S */
EM_H8_500 = 49, /* Hitachi H8/500 */
EM_IA_64 = 50, /* Intel IA-64 processor architecture */
EM_MIPS_X = 51, /* Stanford MIPS-X */
EM_COLDFIRE = 52, /* Motorola ColdFire */
EM_68HC12 = 53, /* Motorola M68HC12 */
EM_MMA = 54, /* Fujitsu MMA Multimedia Accelerator */
EM_PCP = 55, /* Siemens PCP */
EM_NCPU = 56, /* Sony nCPU embedded RISC processor */
EM_NDR1 = 57, /* Denso NDR1 microprocessor */
EM_STARCORE = 58, /* Motorola Star*Core processor */
EM_ME16 = 59, /* Toyota ME16 processor */
EM_ST100 = 60, /* STMicroelectronics ST100 processor */
EM_TINYJ = 61, /* Advanced Logic Corp. TinyJ embedded processor family */
EM_X86_64 = 62, /* AMD x86-64 architecture (PS4) */
EM_PDSP = 63, /* Sony DSP Processor */
EM_PDP10 = 64, /* Digital Equipment Corp. PDP-10 */
EM_PDP11 = 65, /* Digital Equipment Corp. PDP-11 */
EM_FX66 = 66, /* Siemens FX66 microcontroller */
EM_ST9PLUS = 67, /* STMicroelectronics ST9+ 8/16 bit microcontroller */
EM_ST7 = 68, /* STMicroelectronics ST7 8-bit microcontroller */
EM_68HC16 = 69, /* Motorola MC68HC16 Microcontroller */
EM_68HC11 = 70, /* Motorola MC68HC11 Microcontroller */
EM_68HC08 = 71, /* Motorola MC68HC08 Microcontroller */
EM_68HC05 = 72, /* Motorola MC68HC05 Microcontroller */
EM_SVX = 73, /* Silicon Graphics SVx */
EM_ST19 = 75, /* Digital VAX */
EM_CRIS = 76, /* Axis Communications 32-bit embedded processor */
EM_JAVELIN = 77, /* Infineon Technologies 32-bit embedded processor */
EM_FIREPATH = 78, /* Element 14 64-bit DSP Processor */
EM_ZSP = 79, /* LSI Logic 16-bit DSP Processor */
EM_MMIX = 80, /* Donald Knuth's educational 64-bit processor */
EM_HUANY = 81, /* Harvard University machine-independent object files */
EM_PRISM = 82, /* SiTera Prism */
EM_AVR = 83, /* Atmel AVR 8-bit microcontroller */
EM_FR30 = 84, /* Fujitsu FR30 */
EM_D10V = 85, /* Mitsubishi D10V */
EM_D30V = 86, /* Mitsubishi D30V */
EM_V850 = 87, /* NEC v850 */
EM_M32R = 88, /* Mitsubishi M32R */
EM_MN10300 = 89, /* Matsushita MN10300 */
EM_MN10200 = 90, /* Matsushita MN10200 */
EM_PJ = 91, /* PicoJava */
EM_OPENRISC = 92, /* OpenRISC 32-bit embedded processor */
EM_ARC_A5 = 93, /* ARC Cores Tangent-A5 */
EM_XTENSA = 94, /* Tensilica Xtensa Architecture */
EM_VIDEOCORE = 95, /* Alphamosaic VideoCore processor */
EM_TMM_GPP = 96, /* Thompson Multimedia General Purpose Processor */
EM_NS32K = 97, /* National Semiconductor 32000 series */
EM_TPC = 98, /* Tenor Network TPC processor */
EM_SNP1K = 99, /* Trebia SNP 1000 processor */
EM_ST200 = 100, /* STMicroelectronics (www.st.com) ST200 microcontroller */
EM_IP2K = 101, /* Ubicom IP2xxx microcontroller family */
EM_MAX = 102, /* MAX Processor */
EM_CR = 103, /* National Semiconductor CompactRISC microprocessor */
EM_F2MC16 = 104, /* Fujitsu F2MC16 */
EM_MSP430 = 105, /* Texas Instruments embedded microcontroller msp430 */
EM_BLACKFIN = 106, /* Analog Devices Blackfin (DSP) processor */
EM_SE_C33 = 107, /* S1C33 Family of Seiko Epson processors */
EM_SEP = 108, /* Sharp embedded microprocessor */
EM_ARCA = 109, /* Arca RISC Microprocessor */
EM_UNICORE = 110 /* Microprocessor series from PKU-Unity Ltd. and MPRC */
} e_machine_es;
typedef enum : u32 { EV_NONE = 0x0, EV_CURRENT = 0x1 } e_version_es;
typedef enum : u8 {
ELF_CLASS_NONE = 0x0,
ELF_CLASS_32 = 0x1,
ELF_CLASS_64 = 0x2,
ELF_CLASS_NUM = 0x3
} ident_class_es;
typedef enum : u8 {
ELF_DATA_NONE = 0x0,
ELF_DATA_2LSB = 0x1,
ELF_DATA_2MSB = 0x2,
ELF_DATA_NUM = 0x3
} ident_endian_es;
typedef enum : u8 {
ELF_VERSION_NONE = 0x0,
ELF_VERSION_CURRENT = 0x1,
ELF_VERSION_NUM = 0x2
} ident_version_es;
typedef enum : u8 {
ELF_OSABI_NONE = 0x0, /* No extensions or unspecified */
ELF_OSABI_HPUX = 0x1, /* Hewlett-Packard HP-UX */
ELF_OSABI_NETBSD = 0x2, /* NetBSD */
ELF_OSABI_LINUX = 0x3, /* Linux */
ELF_OSABI_SOLARIS = 0x6, /* Sun Solaris */
ELF_OSABI_AIX = 0x7, /* AIX */
ELF_OSABI_IRIX = 0x8, /* IRIX */
ELF_OSABI_FREEBSD = 0x9, /* FreeBSD (PS4) */
ELF_OSABI_TRU64 = 0xA, /* Compaq TRU64 UNIX */
ELF_OSABI_MODESTO = 0xB, /* Novell Modesto */
ELF_OSABI_OPENBSD = 0xC, /* Open BSD */
ELF_OSABI_OPENVMS = 0xD, /* Open VMS */
ELF_OSABI_NSK = 0xE, /* Hewlett-Packard Non-Stop Kernel */
ELF_OSABI_AROS = 0xF, /* Amiga Research OS */
ELF_OSABI_ARM_AEABI = 0x40, /* ARM EABI */
ELF_OSABI_ARM = 0x61, /* ARM */
ELF_OSABI_STANDALONE = 0xFF /* Standalone (embedded applications) */
} ident_osabi_es;
typedef enum : u8 {
ELF_ABI_VERSION_AMDGPU_HSA_V2 = 0x0,
ELF_ABI_VERSION_AMDGPU_HSA_V3 = 0x1,
ELF_ABI_VERSION_AMDGPU_HSA_V4 = 0x2,
ELF_ABI_VERSION_AMDGPU_HSA_V5 = 0x3
} ident_abiversion_es;
struct elf_ident {
u8 magic[4];
ident_class_es ei_class;
ident_endian_es ei_data;
ident_version_es ei_version;
ident_osabi_es ei_osabi;
ident_abiversion_es ei_abiversion;
u8 pad[6];
};
struct elf_header {
static const u32 signature = 0x7F454C46u;
elf_ident e_ident; /* ELF identification */
e_type_s e_type; /* Object file type */
e_machine_es e_machine; /* Machine type */
e_version_es e_version; /* Object file version */
u64 e_entry; /* Entry point address */
u64 e_phoff; /* Program header offset */
u64 e_shoff; /* Section header offset */
u32 e_flags; /* Processor-specific flags */
u16 e_ehsize; /* ELF header size */
u16 e_phentsize; /* Size of program header entry */
u16 e_phnum; /* Number of program header entries */
u16 e_shentsize; /* Size of section header entry */
u16 e_shnum; /* Number of section header entries */
u16 e_shstrndx; /* Section name string table index */
};
typedef enum : u32 {
PT_NULL = 0x0,
PT_LOAD = 0x1,
PT_DYNAMIC = 0x2,
PT_INTERP = 0x3,
PT_NOTE = 0x4,
PT_SHLIB = 0x5,
PT_PHDR = 0x6,
PT_TLS = 0x7,
PT_NUM = 0x8,
PT_SCE_RELA = 0x60000000,
PT_SCE_DYNLIBDATA = 0x61000000,
PT_SCE_PROCPARAM = 0x61000001,
PT_SCE_MODULE_PARAM = 0x61000002,
PT_SCE_RELRO = 0x61000010,
PT_GNU_EH_FRAME = 0x6474e550,
PT_GNU_STACK = 0x6474e551,
PT_GNU_RELRO = 0x6474e552,
PT_SCE_COMMENT = 0x6fffff00,
PT_SCE_LIBVERSION = 0x6fffff01,
PT_LOSUNW = 0x6ffffffa,
PT_SUNWBSS = 0x6ffffffa,
PT_SUNWSTACK = 0x6ffffffb,
PT_HISUNW = 0x6fffffff,
PT_HIOS = 0x6fffffff,
PT_LOPROC = 0x70000000,
PT_HIPROC = 0x7fffffff
} elf_program_type;
typedef enum : u32 {
PF_NONE = 0x0,
PF_EXEC = 0x1,
PF_WRITE = 0x2,
PF_WRITE_EXEC = 0x3,
PF_READ = 0x4,
PF_READ_EXEC = 0x5,
PF_READ_WRITE = 0x6,
PF_READ_WRITE_EXEC = 0x7
} elf_program_flags;
struct elf_program_header {
elf_program_type p_type; /* Type of segment */
elf_program_flags p_flags; /* Segment attributes */
u64 p_offset; /* Offset in file */
u64 p_vaddr; /* Virtual address in memory */
u64 p_paddr; /* Reserved */
u64 p_filesz; /* Size of segment in file */
u64 p_memsz; /* Size of segment in memory */
u64 p_align; /* Alignment of segment */
};
struct elf_section_header {
u32 sh_name; /* Section name */
u32 sh_type; /* Section type */
u64 sh_flags; /* Section attributes */
u64 sh_addr; /* Virtual address in memory */
u64 sh_offset; /* Offset in file */
u64 sh_size; /* Size of section */
u32 sh_link; /* Link to other section */
u32 sh_info; /* Miscellaneous information */
u64 sh_addralign; /* Address alignment boundary */
u64 sh_entsize; /* Size of entries, if section has table */
};
typedef enum : u64 {
PT_FAKE = 0x1,
PT_NPDRM_EXEC = 0x4,
PT_NPDRM_DYNLIB = 0x5,
PT_SYSTEM_EXEC = 0x8,
PT_SYSTEM_DYNLIB = 0x9,
PT_HOST_KERNEL = 0xC,
PT_SECURE_MODULE = 0xE,
PT_SECURE_KERNEL = 0xF
} program_type_es;
struct elf_program_id_header {
u64 authid;
program_type_es program_type;
u64 appver;
u64 firmver;
u8 digest[32];
};
constexpr s64 DT_NULL = 0;
constexpr s64 DT_NEEDED = 0x00000001;
constexpr s64 DT_RELA = 0x00000007;
constexpr s64 DT_INIT = 0x0000000c;
constexpr s64 DT_FINI = 0x0000000d;
constexpr s64 DT_DEBUG = 0x00000015;
constexpr s64 DT_TEXTREL = 0x00000016;
constexpr s64 DT_INIT_ARRAY = 0x00000019;
constexpr s64 DT_FINI_ARRAY = 0x0000001a;
constexpr s64 DT_INIT_ARRAYSZ = 0x0000001b;
constexpr s64 DT_FINI_ARRAYSZ = 0x0000001c;
constexpr s64 DT_FLAGS = 0x0000001e;
constexpr s64 DT_PREINIT_ARRAY = 0x00000020;
constexpr s64 DT_PREINIT_ARRAYSZ = 0x00000021;
constexpr s64 DT_SCE_FINGERPRINT = 0x61000007;
constexpr s64 DT_SCE_ORIGINAL_FILENAME = 0x61000009;
constexpr s64 DT_SCE_MODULE_INFO = 0x6100000d;
constexpr s64 DT_SCE_NEEDED_MODULE = 0x6100000f;
constexpr s64 DT_SCE_MODULE_ATTR = 0x61000011;
constexpr s64 DT_SCE_EXPORT_LIB = 0x61000013;
constexpr s64 DT_SCE_IMPORT_LIB = 0x61000015;
constexpr s64 DT_SCE_IMPORT_LIB_ATTR = 0x61000019;
constexpr s64 DT_SCE_HASH = 0x61000025;
constexpr s64 DT_SCE_PLTGOT = 0x61000027;
constexpr s64 DT_SCE_JMPREL = 0x61000029;
constexpr s64 DT_SCE_PLTREL = 0x6100002b;
constexpr s64 DT_SCE_PLTRELSZ = 0x6100002d;
constexpr s64 DT_SCE_RELA = 0x6100002f;
constexpr s64 DT_SCE_RELASZ = 0x61000031;
constexpr s64 DT_SCE_RELAENT = 0x61000033;
constexpr s64 DT_SCE_SYMENT = 0x6100003b;
constexpr s64 DT_SCE_HASHSZ = 0x6100003d;
constexpr s64 DT_SCE_STRTAB = 0x61000035;
constexpr s64 DT_SCE_STRSZ = 0x61000037;
constexpr s64 DT_SCE_SYMTAB = 0x61000039;
constexpr s64 DT_SCE_SYMTABSZ = 0x6100003f;
struct elf_dynamic {
s64 d_tag;
union {
u64 d_val;
u64 d_ptr;
} d_un;
};
constexpr u8 STB_LOCAL = 0;
constexpr u8 STB_GLOBAL = 1;
constexpr u8 STB_WEAK = 2;
constexpr u8 STT_NOTYPE = 0;
constexpr u8 STT_OBJECT = 1;
constexpr u8 STT_FUN = 2;
constexpr u8 STT_SECTION = 3;
constexpr u8 STT_FILE = 4;
constexpr u8 STT_COMMON = 5;
constexpr u8 STT_TLS = 6;
constexpr u8 STT_LOOS = 10;
constexpr u8 STT_SCE = 11; // module_start/module_stop
constexpr u8 STT_HIOS = 12;
constexpr u8 STT_LOPRO = 13;
constexpr u8 STT_SPARC_REGISTER = 13;
constexpr u8 STT_HIPROC = 15;
constexpr u8 STV_DEFAULT = 0;
constexpr u8 STV_INTERNAL = 1;
constexpr u8 STV_HIDDEN = 2;
constexpr u8 STV_PROTECTED = 3;
struct elf_symbol {
u8 GetBind() const {
return st_info >> 4u;
}
u8 GetType() const {
return st_info & 0xfu;
}
u8 GetVisibility() const {
return st_other & 3u;
}
u32 st_name;
u8 st_info;
u8 st_other;
u16 st_shndx;
u64 st_value;
u64 st_size;
};
struct elf_relocation {
u32 GetSymbol() const {
return static_cast<u32>(rel_info >> 32u);
}
u32 GetType() const {
return static_cast<u32>(rel_info & 0xffffffff);
}
u64 rel_offset;
u64 rel_info;
s64 rel_addend;
};
constexpr u32 R_X86_64_64 = 1; // Direct 64 bit
constexpr u32 R_X86_64_GLOB_DAT = 6;
constexpr u32 R_X86_64_JUMP_SLOT = 7; // Create PLT entry
constexpr u32 R_X86_64_RELATIVE = 8; // Adjust by program base
constexpr u32 R_X86_64_DTPMOD64 = 16;
struct eh_frame_hdr {
uint8_t version;
uint8_t eh_frame_ptr_enc;
uint8_t fde_count_enc;
uint8_t table_enc;
uint32_t eh_frame_ptr;
uint32_t fde_count;
};
namespace Core::Loader {
class Elf {
public:
Elf() = default;
~Elf();
void Open(const std::filesystem::path& file_name);
bool IsSelfFile() const;
bool IsElfFile() const;
[[nodiscard]] self_header GetSElfHeader() const {
return m_self;
}
[[nodiscard]] elf_header GetElfHeader() const {
return m_elf_header;
}
[[nodiscard]] std::span<const elf_program_header> GetProgramHeader() const {
return m_elf_phdr;
}
[[nodiscard]] std::span<const self_segment_header> GetSegmentHeader() const {
return m_self_segments;
}
[[nodiscard]] u64 GetElfEntry() const {
return m_elf_header.e_entry;
}
[[nodiscard]] bool IsSharedLib() const {
return m_elf_header.e_type == ET_SCE_DYNAMIC;
}
std::string SElfHeaderStr();
std::string SELFSegHeader(u16 no);
std::string ElfHeaderStr();
std::string ElfPHeaderStr(u16 no);
std::string_view ElfPheaderTypeStr(u32 type);
std::string ElfPheaderFlagsStr(u32 flags);
void LoadSegment(u64 virtual_addr, u64 file_offset, u64 size);
bool IsSharedLib();
void ElfHeaderDebugDump(const std::filesystem::path& file_name);
void SelfHeaderDebugDump(const std::filesystem::path& file_name);
void SelfSegHeaderDebugDump(const std::filesystem::path& file_name);
void PHeaderDebugDump(const std::filesystem::path& file_name);
private:
Common::FS::IOFile m_f{};
bool is_self{};
self_header m_self{};
std::vector<self_segment_header> m_self_segments;
elf_header m_elf_header{};
std::vector<elf_program_header> m_elf_phdr;
std::vector<elf_section_header> m_elf_shdr;
elf_program_id_header m_self_id_header{};
};
} // namespace Core::Loader
| 17,112
|
C++
|
.h
| 467
| 32.494647
| 84
| 0.622627
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,882
|
dwarf.h
|
shadps4-emu_shadPS4/src/core/loader/dwarf.h
|
// SPDX-FileCopyrightText: Copyright (C) 2001-2024 Free Software Foundation, Inc.
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Dwarf {
enum {
DW_EH_PE_ptr = 0x00,
DW_EH_PE_uleb128 = 0x01,
DW_EH_PE_udata2 = 0x02,
DW_EH_PE_udata4 = 0x03,
DW_EH_PE_udata8 = 0x04,
DW_EH_PE_signed = 0x08,
DW_EH_PE_sleb128 = 0x09,
DW_EH_PE_sdata2 = 0x0A,
DW_EH_PE_sdata4 = 0x0B,
DW_EH_PE_sdata8 = 0x0C,
DW_EH_PE_absptr = 0x00,
DW_EH_PE_pcrel = 0x10,
DW_EH_PE_textrel = 0x20,
DW_EH_PE_datarel = 0x30,
DW_EH_PE_funcrel = 0x40,
DW_EH_PE_aligned = 0x50,
DW_EH_PE_indirect = 0x80,
DW_EH_PE_omit = 0xFF
};
/// Information encoded in the EH frame header.
struct EHHeaderInfo {
uintptr_t eh_frame_ptr;
size_t fde_count;
uintptr_t table;
u8 table_enc;
};
bool DecodeEHHdr(uintptr_t ehHdrStart, uintptr_t ehHdrEnd, EHHeaderInfo& ehHdrInfo);
} // namespace Dwarf
| 974
|
C++
|
.h
| 34
| 24.852941
| 84
| 0.670954
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,883
|
aerolib.h
|
shadps4-emu_shadPS4/src/core/aerolib/aerolib.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <cstdint>
namespace Core::AeroLib {
struct NidEntry {
const char* nid;
const char* name;
};
const NidEntry* FindByNid(const char* nid);
} // namespace Core::AeroLib
| 313
|
C++
|
.h
| 11
| 26.181818
| 66
| 0.763514
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,884
|
stubs.h
|
shadps4-emu_shadPS4/src/core/aerolib/stubs.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Core::AeroLib {
u64 UnresolvedStub();
u64 GetStub(const char* nid);
} // namespace Core::AeroLib
| 264
|
C++
|
.h
| 8
| 31.25
| 66
| 0.788
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,885
|
crypto.h
|
shadps4-emu_shadPS4/src/core/crypto/crypto.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include <cryptopp/aes.h>
#include <cryptopp/filters.h>
#include <cryptopp/modes.h>
#include <cryptopp/oaep.h>
#include <cryptopp/osrng.h>
#include <cryptopp/rsa.h>
#include <cryptopp/sha.h>
#include "common/types.h"
#include "keys.h"
class Crypto {
public:
CryptoPP::RSA::PrivateKey key_pkg_derived_key3_keyset_init();
CryptoPP::RSA::PrivateKey FakeKeyset_keyset_init();
CryptoPP::RSA::PrivateKey DebugRifKeyset_init();
void RSA2048Decrypt(std::span<CryptoPP::byte, 32> dk3,
std::span<const CryptoPP::byte, 256> ciphertext,
bool is_dk3); // RSAES_PKCS1v15_
void ivKeyHASH256(std::span<const CryptoPP::byte, 64> cipher_input,
std::span<CryptoPP::byte, 32> ivkey_result);
void aesCbcCfb128Decrypt(std::span<const CryptoPP::byte, 32> ivkey,
std::span<const CryptoPP::byte, 256> ciphertext,
std::span<CryptoPP::byte, 256> decrypted);
void aesCbcCfb128DecryptEntry(std::span<const CryptoPP::byte, 32> ivkey,
std::span<CryptoPP::byte> ciphertext,
std::span<CryptoPP::byte> decrypted);
void decryptEFSM(std::span<CryptoPP::byte, 16>, std::span<CryptoPP::byte, 16> efsmIv,
std::span<CryptoPP::byte> ciphertext, std::span<CryptoPP::byte> decrypted);
void PfsGenCryptoKey(std::span<const CryptoPP::byte, 32> ekpfs,
std::span<const CryptoPP::byte, 16> seed,
std::span<CryptoPP::byte, 16> dataKey,
std::span<CryptoPP::byte, 16> tweakKey);
void decryptPFS(std::span<const CryptoPP::byte, 16> dataKey,
std::span<const CryptoPP::byte, 16> tweakKey, std::span<const u8> src_image,
std::span<CryptoPP::byte> dst_image, u64 sector);
void xtsXorBlock(CryptoPP::byte* x, const CryptoPP::byte* a, const CryptoPP::byte* b) {
for (int i = 0; i < 16; i++) {
x[i] = a[i] ^ b[i];
}
}
void xtsMult(std::span<CryptoPP::byte, 16> encryptedTweak) {
int feedback = 0;
for (int k = 0; k < encryptedTweak.size(); k++) {
const auto tmp = (encryptedTweak[k] >> 7) & 1;
encryptedTweak[k] = ((encryptedTweak[k] << 1) + feedback) & 0xFF;
feedback = tmp;
}
if (feedback != 0) {
encryptedTweak[0] ^= 0x87;
}
}
};
| 2,626
|
C++
|
.h
| 55
| 37.454545
| 96
| 0.596334
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,887
|
fs.h
|
shadps4-emu_shadPS4/src/core/file_sys/fs.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <atomic>
#include <mutex>
#include <string>
#include <vector>
#include <tsl/robin_map.h>
#include "common/io_file.h"
namespace Core::FileSys {
class MntPoints {
#ifdef _WIN64
static constexpr bool NeedsCaseInsensitiveSearch = false;
#else
static constexpr bool NeedsCaseInsensitiveSearch = true;
#endif
public:
struct MntPair {
std::filesystem::path host_path;
std::string mount; // e.g /app0/
bool read_only;
};
explicit MntPoints() = default;
~MntPoints() = default;
void Mount(const std::filesystem::path& host_folder, const std::string& guest_folder,
bool read_only = false);
void Unmount(const std::filesystem::path& host_folder, const std::string& guest_folder);
void UnmountAll();
std::filesystem::path GetHostPath(std::string_view guest_directory,
bool* is_read_only = nullptr);
const MntPair* GetMount(const std::string& guest_path) {
std::scoped_lock lock{m_mutex};
const auto it = std::ranges::find_if(
m_mnt_pairs, [&](const auto& mount) { return guest_path.starts_with(mount.mount); });
return it == m_mnt_pairs.end() ? nullptr : &*it;
}
private:
std::vector<MntPair> m_mnt_pairs;
std::vector<std::filesystem::path> path_parts;
tsl::robin_map<std::filesystem::path, std::filesystem::path> path_cache;
std::mutex m_mutex;
};
struct DirEntry {
std::string name;
bool isFile;
};
struct File {
std::atomic_bool is_opened{};
std::atomic_bool is_directory{};
std::filesystem::path m_host_name;
std::string m_guest_name;
Common::FS::IOFile f;
std::vector<DirEntry> dirents;
u32 dirents_index;
std::mutex m_mutex;
};
class HandleTable {
public:
HandleTable() = default;
virtual ~HandleTable() = default;
int CreateHandle();
void DeleteHandle(int d);
File* GetFile(int d);
File* GetFile(const std::filesystem::path& host_name);
private:
std::vector<File*> m_files;
std::mutex m_mutex;
};
} // namespace Core::FileSys
| 2,219
|
C++
|
.h
| 69
| 27.333333
| 97
| 0.671194
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,888
|
trp.h
|
shadps4-emu_shadPS4/src/core/file_format/trp.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <vector>
#include "common/endian.h"
#include "common/io_file.h"
#include "common/types.h"
#include "core/crypto/crypto.h"
struct TrpHeader {
u32_be magic; // (0xDCA24D00)
u32_be version;
u64_be file_size; // size of full trp file
u32_be entry_num; // num entries
u32_be entry_size; // size of entry
u32_be dev_flag; // 1: dev
unsigned char digest[20]; // sha1 hash
u32_be key_index; // 3031300?
unsigned char padding[44];
};
struct TrpEntry {
char entry_name[32];
u64_be entry_pos;
u64_be entry_len;
u32_be flag; // 3 = CONFIG/ESFM , 0 = PNG
unsigned char padding[12];
};
class TRP {
public:
TRP();
~TRP();
bool Extract(const std::filesystem::path& trophyPath, const std::string titleId);
void GetNPcommID(const std::filesystem::path& trophyPath, int index);
private:
Crypto crypto;
std::vector<u8> NPcommID = std::vector<u8>(12);
std::array<u8, 16> np_comm_id{};
std::array<u8, 16> esfmIv{};
std::filesystem::path trpFilesPath;
static constexpr int iv_len = 16;
};
| 1,241
|
C++
|
.h
| 40
| 27.5
| 85
| 0.658027
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,889
|
playgo_chunk.h
|
shadps4-emu_shadPS4/src/core/file_format/playgo_chunk.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <filesystem>
#include <mutex>
#include <vector>
#include "common/io_file.h"
#include "core/libraries/playgo/playgo_types.h"
constexpr u32 PLAYGO_MAGIC = 0x6F676C70;
struct chunk_t {
u32 offset;
u32 length;
} __attribute__((packed));
struct PlaygoHeader {
u32 magic;
u16 version_major;
u16 version_minor;
u16 image_count; // [0;1]
u16 chunk_count; // [0;1000]
u16 mchunk_count; // [0;8000]
u16 scenario_count; // [0;32]
u32 file_size;
u16 default_scenario_id;
u16 attrib;
u32 sdk_version;
u16 disc_count; // [0;2] (if equals to 0 then disc count = 1)
u16 layer_bmp;
u8 reserved[32];
char content_id[128];
chunk_t chunk_attrs; // [0;32000]
chunk_t chunk_mchunks;
chunk_t chunk_labels; // [0;16000]
chunk_t mchunk_attrs; // [0;12800]
chunk_t scenario_attrs; // [0;1024]
chunk_t scenario_chunks;
chunk_t scenario_labels;
chunk_t inner_mchunk_attrs; // [0;12800]
} __attribute__((packed));
struct playgo_scenario_attr_entry_t {
u8 _type;
u8 _unk[19];
u16 initial_chunk_count;
u16 chunk_count;
u32 chunks_offset; //<-scenario_chunks
u32 label_offset; //<-scenario_labels
} __attribute__((packed));
struct image_disc_layer_no_t {
u8 layer_no : 2;
u8 disc_no : 2;
u8 image_no : 4;
} __attribute__((packed));
struct playgo_chunk_attr_entry_t {
u8 flag;
image_disc_layer_no_t image_disc_layer_no;
u8 req_locus;
u8 unk[11];
u16 mchunk_count;
u64 language_mask;
u32 mchunks_offset; //<-chunk_mchunks
u32 label_offset; //<-chunk_labels
} __attribute__((packed));
struct playgo_chunk_loc_t {
u64 offset : 48;
u64 _align1 : 8;
u64 image_no : 4;
u64 _align2 : 4;
} __attribute__((packed));
struct playgo_chunk_size_t {
u64 size : 48;
u64 _align : 16;
} __attribute__((packed));
struct playgo_mchunk_attr_entry_t {
playgo_chunk_loc_t loc;
playgo_chunk_size_t size;
} __attribute__((packed));
struct PlaygoChunk {
u64 req_locus;
u64 language_mask;
u64 total_size;
std::string label_name;
};
class PlaygoFile {
public:
bool initialized;
OrbisPlayGoHandle handle;
OrbisPlayGoChunkId id;
OrbisPlayGoLocus locus;
OrbisPlayGoInstallSpeed speed;
s64 speed_tick;
OrbisPlayGoEta eta;
OrbisPlayGoLanguageMask langMask;
std::vector<PlaygoChunk> chunks;
public:
PlaygoFile()
: initialized(false), handle(0), id(0), locus(0), speed(ORBIS_PLAYGO_INSTALL_SPEED_TRICKLE),
speed_tick(0), eta(0), langMask(0), playgoHeader{0} {}
~PlaygoFile() = default;
bool Open(const std::filesystem::path& filepath);
bool LoadChunks(const Common::FS::IOFile& file);
PlaygoHeader& GetPlaygoHeader() {
return playgoHeader;
}
std::mutex& GetSpeedMutex() {
return speed_mutex;
}
private:
bool load_chunk_data(const Common::FS::IOFile& file, const chunk_t chunk, std::string& data);
private:
PlaygoHeader playgoHeader;
std::mutex speed_mutex;
};
| 3,192
|
C++
|
.h
| 111
| 24.603604
| 100
| 0.667429
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,890
|
splash.h
|
shadps4-emu_shadPS4/src/core/file_format/splash.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <filesystem>
#include <string>
#include <vector>
#include "common/types.h"
class Splash {
public:
struct ImageInfo {
u32 width;
u32 height;
u32 num_channels;
u32 GetSizeBytes() const {
return width * height * 4; // we always forcing rgba8 for simplicity
}
};
Splash() = default;
~Splash() = default;
bool Open(const std::filesystem::path& filepath);
[[nodiscard]] bool IsLoaded() const {
return img_data.size();
}
const auto& GetImageData() const {
return img_data;
}
ImageInfo GetImageInfo() const {
return img_info;
}
private:
ImageInfo img_info{};
std::vector<u8> img_data{};
};
| 853
|
C++
|
.h
| 33
| 20.69697
| 80
| 0.642417
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,891
|
psf.h
|
shadps4-emu_shadPS4/src/core/file_format/psf.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <filesystem>
#include <span>
#include <string>
#include <string_view>
#include <unordered_map>
#include <vector>
#include "common/endian.h"
constexpr u32 PSF_MAGIC = 0x00505346;
constexpr u32 PSF_VERSION_1_1 = 0x00000101;
constexpr u32 PSF_VERSION_1_0 = 0x00000100;
struct PSFHeader {
u32_be magic;
u32_le version;
u32_le key_table_offset;
u32_le data_table_offset;
u32_le index_table_entries;
};
static_assert(sizeof(PSFHeader) == 0x14);
struct PSFRawEntry {
u16_le key_offset;
u16_be param_fmt;
u32_le param_len;
u32_le param_max_len;
u32_le data_offset;
};
static_assert(sizeof(PSFRawEntry) == 0x10);
enum class PSFEntryFmt : u16 {
Binary = 0x0004, // Binary data
Text = 0x0204, // String in UTF-8 format and NULL terminated
Integer = 0x0404, // Signed 32-bit integer
};
class PSF {
struct Entry {
std::string key;
PSFEntryFmt param_fmt;
u32 max_len;
};
public:
PSF() = default;
~PSF() = default;
PSF(const PSF& other) = default;
PSF(PSF&& other) noexcept = default;
PSF& operator=(const PSF& other) = default;
PSF& operator=(PSF&& other) noexcept = default;
bool Open(const std::filesystem::path& filepath);
bool Open(const std::vector<u8>& psf_buffer);
[[nodiscard]] std::vector<u8> Encode() const;
void Encode(std::vector<u8>& buf) const;
bool Encode(const std::filesystem::path& filepath) const;
std::optional<std::span<const u8>> GetBinary(std::string_view key) const;
std::optional<std::string_view> GetString(std::string_view key) const;
std::optional<s32> GetInteger(std::string_view key) const;
void AddBinary(std::string key, std::vector<u8> value, bool update = false);
void AddBinary(std::string key, uint64_t value, bool update = false); // rsv4 format
void AddString(std::string key, std::string value, bool update = false);
void AddInteger(std::string key, s32 value, bool update = false);
[[nodiscard]] std::filesystem::file_time_type GetLastWrite() const {
return last_write;
}
[[nodiscard]] const std::vector<Entry>& GetEntries() const {
return entry_list;
}
private:
mutable std::filesystem::file_time_type last_write;
std::vector<Entry> entry_list;
std::unordered_map<size_t, std::vector<u8>> map_binaries;
std::unordered_map<size_t, std::string> map_strings;
std::unordered_map<size_t, s32> map_integers;
[[nodiscard]] std::pair<std::vector<Entry>::iterator, size_t> FindEntry(std::string_view key);
[[nodiscard]] std::pair<std::vector<Entry>::const_iterator, size_t> FindEntry(
std::string_view key) const;
};
| 2,816
|
C++
|
.h
| 75
| 33.306667
| 98
| 0.692138
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,892
|
pkg_type.h
|
shadps4-emu_shadPS4/src/core/file_format/pkg_type.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string_view>
#include "common/types.h"
/// Retrieves the PKG entry name from its type identifier.
std::string_view GetEntryNameByType(u32 type);
| 283
|
C++
|
.h
| 7
| 39
| 66
| 0.798535
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,893
|
pfs.h
|
shadps4-emu_shadPS4/src/core/file_format/pfs.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <cstddef>
#include <string>
#include "common/types.h"
#define PFS_FILE 2
#define PFS_DIR 3
#define PFS_CURRENT_DIR 4
#define PFS_PARENT_DIR 5
enum PfsMode : unsigned short {
None = 0,
Signed = 0x1,
Is64Bit = 0x2,
Encrypted = 0x4,
UnknownFlagAlwaysSet = 0x8
};
struct PSFHeader_ {
s64 version;
s64 magic;
s64 id;
u8 fmode;
u8 clean;
u8 read_only;
u8 rsv;
PfsMode mode;
s16 unk1;
s32 block_size;
s32 n_backup;
s64 n_block;
s64 dinode_count;
s64 nd_block;
s64 dinode_block_count;
s64 superroot_ino;
};
struct PFSCHdr {
s32 magic;
s32 unk4;
s32 unk8;
s32 block_sz;
s64 block_sz2;
s64 block_offsets;
u64 data_start;
s64 data_length;
};
enum InodeMode : u16 {
o_read = 1,
o_write = 2,
o_execute = 4,
g_read = 8,
g_write = 16,
g_execute = 32,
u_read = 64,
u_write = 128,
u_execute = 256,
dir = 16384,
file = 32768,
};
enum InodeFlags : u32 {
compressed = 0x1,
unk1 = 0x2,
unk2 = 0x4,
unk3 = 0x8,
readonly = 0x10,
unk4 = 0x20,
unk5 = 0x40,
unk6 = 0x80,
unk7 = 0x100,
unk8 = 0x200,
unk9 = 0x400,
unk10 = 0x800,
unk11 = 0x1000,
unk12 = 0x2000,
unk13 = 0x4000,
unk14 = 0x8000,
unk15 = 0x10000,
internal = 0x20000
};
struct Inode {
u16 Mode;
u16 Nlink;
u32 Flags;
s64 Size;
s64 SizeCompressed;
s64 Time1_sec;
s64 Time2_sec;
s64 Time3_sec;
s64 Time4_sec;
u32 Time1_nsec;
u32 Time2_nsec;
u32 Time3_nsec;
u32 Time4_nsec;
u32 Uid;
u32 Gid;
u64 Unk1;
u64 Unk2;
u32 Blocks;
u32 loc;
};
struct pfs_fs_table {
std::string name;
u32 inode;
u32 type;
};
struct Dirent {
s32 ino;
s32 type;
s32 namelen;
s32 entsize;
char name[512];
};
| 1,998
|
C++
|
.h
| 111
| 13.828829
| 66
| 0.616533
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,894
|
pkg.h
|
shadps4-emu_shadPS4/src/core/file_format/pkg.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <array>
#include <filesystem>
#include <string>
#include <unordered_map>
#include <vector>
#include "common/endian.h"
#include "core/crypto/crypto.h"
#include "pfs.h"
#include "trp.h"
struct PKGHeader {
u32_be magic; // Magic
u32_be pkg_type;
u32_be pkg_0x8; // unknown field
u32_be pkg_file_count;
u32_be pkg_table_entry_count;
u16_be pkg_sc_entry_count;
u16_be pkg_table_entry_count_2; // same as pkg_entry_count
u32_be pkg_table_entry_offset; // file table offset
u32_be pkg_sc_entry_data_size;
u64_be pkg_body_offset; // offset of PKG entries
u64_be pkg_body_size; // length of all PKG entries
u64_be pkg_content_offset;
u64_be pkg_content_size;
u8 pkg_content_id[0x24]; // packages' content ID as a 36-byte string
u8 pkg_padding[0xC]; // padding
u32_be pkg_drm_type; // DRM type
u32_be pkg_content_type; // Content type
u32_be pkg_content_flags; // Content flags
u32_be pkg_promote_size;
u32_be pkg_version_date;
u32_be pkg_version_hash;
u32_be pkg_0x088;
u32_be pkg_0x08C;
u32_be pkg_0x090;
u32_be pkg_0x094;
u32_be pkg_iro_tag;
u32_be pkg_drm_type_version;
u8 pkg_zeroes_1[0x60];
/* Digest table */
u8 digest_entries1[0x20]; // sha256 digest for main entry 1
u8 digest_entries2[0x20]; // sha256 digest for main entry 2
u8 digest_table_digest[0x20]; // sha256 digest for digest table
u8 digest_body_digest[0x20]; // sha256 digest for main table
u8 pkg_zeroes_2[0x280];
u32_be pkg_0x400;
u32_be pfs_image_count; // count of PFS images
u64_be pfs_image_flags; // PFS flags
u64_be pfs_image_offset; // offset to start of external PFS image
u64_be pfs_image_size; // size of external PFS image
u64_be mount_image_offset;
u64_be mount_image_size;
u64_be pkg_size;
u32_be pfs_signed_size;
u32_be pfs_cache_size;
u8 pfs_image_digest[0x20];
u8 pfs_signed_digest[0x20];
u64_be pfs_split_size_nth_0;
u64_be pfs_split_size_nth_1;
u8 pkg_zeroes_3[0xB50];
u8 pkg_digest[0x20];
};
enum class PKGContentFlag {
FIRST_PATCH = 0x100000,
PATCHGO = 0x200000,
REMASTER = 0x400000,
PS_CLOUD = 0x800000,
GD_AC = 0x2000000,
NON_GAME = 0x4000000,
UNKNOWN_0x8000000 = 0x8000000,
SUBSEQUENT_PATCH = 0x40000000,
DELTA_PATCH = 0x41000000,
CUMULATIVE_PATCH = 0x60000000
};
struct PKGEntry {
u32_be id; // File ID, useful for files without a filename entry
u32_be filename_offset; // Offset into the filenames table (ID 0x200) where this file's name is
// located
u32_be flags1; // Flags including encrypted flag, etc
u32_be flags2; // Flags including encryption key index, etc
u32_be offset; // Offset into PKG to find the file
u32_be size; // Size of the file
u64_be padding; // blank padding
};
static_assert(sizeof(PKGEntry) == 32);
class PKG {
public:
PKG();
~PKG();
bool Open(const std::filesystem::path& filepath, std::string& failreason);
void ExtractFiles(const int index);
bool Extract(const std::filesystem::path& filepath, const std::filesystem::path& extract,
std::string& failreason);
std::vector<u8> sfo;
u32 GetNumberOfFiles() {
return fsTable.size();
}
u64 GetPkgSize() {
return pkgSize;
}
std::string GetPkgFlags() {
return pkgFlags;
}
std::string_view GetTitleID() {
return std::string_view(pkgTitleID, 9);
}
PKGHeader GetPkgHeader() {
return pkgheader;
}
static bool isFlagSet(u32_be variable, PKGContentFlag flag) {
return (variable) & static_cast<u32>(flag);
}
static constexpr std::array<std::pair<PKGContentFlag, std::string_view>, 10> flagNames = {
{{PKGContentFlag::FIRST_PATCH, "FIRST_PATCH"},
{PKGContentFlag::PATCHGO, "PATCHGO"},
{PKGContentFlag::REMASTER, "REMASTER"},
{PKGContentFlag::PS_CLOUD, "PS_CLOUD"},
{PKGContentFlag::GD_AC, "GD_AC"},
{PKGContentFlag::NON_GAME, "NON_GAME"},
{PKGContentFlag::UNKNOWN_0x8000000, "UNKNOWN_0x8000000"},
{PKGContentFlag::SUBSEQUENT_PATCH, "SUBSEQUENT_PATCH"},
{PKGContentFlag::DELTA_PATCH, "DELTA_PATCH"},
{PKGContentFlag::CUMULATIVE_PATCH, "CUMULATIVE_PATCH"}}};
private:
Crypto crypto;
TRP trp;
u64 pkgSize = 0;
char pkgTitleID[9];
PKGHeader pkgheader;
std::string pkgFlags;
std::unordered_map<int, std::filesystem::path> extractPaths;
std::vector<pfs_fs_table> fsTable;
std::vector<Inode> iNodeBuf;
std::vector<u64> sectorMap;
u64 pfsc_offset;
std::array<u8, 32> dk3_;
std::array<u8, 32> ivKey;
std::array<u8, 256> imgKey;
std::array<u8, 32> ekpfsKey;
std::array<u8, 16> dataKey;
std::array<u8, 16> tweakKey;
std::vector<u8> decNp;
std::filesystem::path pkgpath;
std::filesystem::path current_dir;
std::filesystem::path extract_path;
};
| 5,239
|
C++
|
.h
| 148
| 30.101351
| 99
| 0.657058
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,895
|
layer.h
|
shadps4-emu_shadPS4/src/core/devtools/layer.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "imgui/imgui_layer.h"
namespace Core::Devtools {
class Layer final : public ImGui::Layer {
static void DrawMenuBar();
static void DrawAdvanced();
static void DrawSimple();
public:
static void SetupSettings();
void Draw() override;
};
} // namespace Core::Devtools
| 428
|
C++
|
.h
| 14
| 27.428571
| 66
| 0.75
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,896
|
options.h
|
shadps4-emu_shadPS4/src/core/devtools/options.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string>
struct ImGuiTextBuffer;
namespace Core::Devtools {
struct TOptions {
std::string disassembly_cli{};
bool frame_dump_render_on_collapse{false};
};
extern TOptions Options;
void LoadOptionsConfig(const char* line);
void SerializeOptionsConfig(ImGuiTextBuffer* buf);
} // namespace Core::Devtools
| 455
|
C++
|
.h
| 14
| 30.357143
| 67
| 0.796767
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,897
|
frame_dump.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/frame_dump.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <memory>
#include <vector>
#include "cmd_list.h"
#include "core/debug_state.h"
namespace Core::Devtools::Widget {
class CmdListViewer;
class FrameDumpViewer {
friend class CmdListViewer;
std::shared_ptr<DebugStateType::FrameDump> frame_dump;
int id;
std::vector<CmdListViewer> cmd_list_viewer;
std::array<bool, 3> has_queue_type;
DebugStateType::QueueType selected_queue_type;
s32 selected_submit_num;
s32 selected_queue_num2;
s32 selected_cmd = -1;
public:
bool is_open = true;
explicit FrameDumpViewer(const DebugStateType::FrameDump& frame_dump);
~FrameDumpViewer();
void Draw();
};
} // namespace Core::Devtools::Widget
| 825
|
C++
|
.h
| 26
| 28.230769
| 74
| 0.744275
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,899
|
reg_popup.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/reg_popup.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <variant>
#include <imgui.h>
#include "common/types.h"
#include "video_core/renderer_vulkan/liverpool_to_vk.h"
namespace Core::Devtools::Widget {
class RegPopup {
int id;
ImGuiWindowFlags flags{ImGuiWindowFlags_NoSavedSettings};
using DepthBuffer = std::tuple<AmdGpu::Liverpool::DepthBuffer, AmdGpu::Liverpool::DepthControl>;
ImVec2 last_pos;
std::variant<AmdGpu::Liverpool::ColorBuffer, DepthBuffer> data;
std::string title{};
static void DrawColorBuffer(const AmdGpu::Liverpool::ColorBuffer& buffer);
static void DrawDepthBuffer(const DepthBuffer& depth_data);
public:
bool open = false;
bool moved = false;
RegPopup();
void SetData(const std::string& base_title, AmdGpu::Liverpool::ColorBuffer color_buffer,
u32 cb_id);
void SetData(const std::string& base_title, AmdGpu::Liverpool::DepthBuffer depth_buffer,
AmdGpu::Liverpool::DepthControl depth_control);
void SetPos(ImVec2 pos, bool auto_resize = false);
void Draw();
};
} // namespace Core::Devtools::Widget
| 1,212
|
C++
|
.h
| 29
| 36.965517
| 100
| 0.733276
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,901
|
frame_graph.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/frame_graph.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Core::Devtools::Widget {
class FrameGraph {
static constexpr u32 FRAME_BUFFER_SIZE = 1024;
struct FrameInfo {
u32 num;
float delta;
};
std::array<FrameInfo, FRAME_BUFFER_SIZE> frame_list{};
public:
bool is_open = true;
void Draw();
void AddFrame(u32 num, float delta) {
frame_list[num % FRAME_BUFFER_SIZE] = FrameInfo{num, delta};
}
};
} // namespace Core::Devtools::Widget
| 601
|
C++
|
.h
| 20
| 25.85
| 68
| 0.691099
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,902
|
reg_view.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/reg_view.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "core/debug_state.h"
#include "imgui_memory_editor.h"
#include "reg_popup.h"
#include "text_editor.h"
namespace Core::Devtools::Widget {
struct ShaderCache {
MemoryEditor hex_view;
TextEditor dis_view;
Vulkan::Liverpool::UserData user_data;
};
class RegView {
int id;
std::string title;
DebugStateType::RegDump data;
u32 batch_id{~0u};
ImVec2 last_pos;
std::unordered_map<int, ShaderCache> shader_decomp;
int selected_shader{-1};
RegPopup default_reg_popup;
int last_selected_cb{-1};
std::vector<RegPopup> extra_reg_popup;
bool show_registers{true};
bool show_user_data{true};
bool show_disassembly{true};
void ProcessShader(int shader_id);
void SelectShader(int shader_id);
void DrawComputeRegs();
void DrawGraphicsRegs();
public:
bool open = false;
bool moved = false;
RegView();
void SetData(DebugStateType::RegDump data, const std::string& base_title, u32 batch_id);
void SetPos(ImVec2 pos);
void Draw();
};
} // namespace Core::Devtools::Widget
| 1,206
|
C++
|
.h
| 40
| 26.15
| 92
| 0.715652
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,903
|
common.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/common.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string>
#include <type_traits>
#include <variant>
#include <magic_enum.hpp>
#include "common/bit_field.h"
#include "common/types.h"
#include "video_core/amdgpu/pm4_opcodes.h"
namespace Core::Devtools::Widget {
/*
* Generic PM4 header
*/
union PM4Header {
struct {
u32 reserved : 16;
u32 count : 14;
u32 type : 2; // PM4_TYPE
};
u32 u32All;
};
struct PushMarker {
std::string name{};
};
struct PopMarker {};
struct BatchBegin {
u32 id;
};
struct BatchInfo {
u32 id;
std::string marker{};
size_t start_addr;
size_t end_addr;
size_t command_addr;
AmdGpu::PM4ItOpcode type;
bool bypass{false};
};
using GPUEvent = std::variant<PushMarker, PopMarker, BatchBegin, BatchInfo>;
template <typename... Args>
void DrawRow(const char* text, const char* fmt, Args... args) {
ImGui::TableNextColumn();
ImGui::TextUnformatted(text);
ImGui::TableNextColumn();
char buf[128];
snprintf(buf, sizeof(buf), fmt, args...);
ImGui::TextUnformatted(buf);
}
template <typename T>
void DrawValueRow(const char* text, T value) {
if constexpr (std::is_enum_v<T>) {
return DrawRow(text, "%X (%s)", value, magic_enum::enum_name(value).data());
} else if constexpr (std::is_integral_v<T>) {
return DrawRow(text, "%X", value);
} else if constexpr (std::is_base_of_v<BitField<T::position, T::bits, typename T::Type>, T>) {
return DrawValueRow(text, value.Value());
} else {
static_assert(false, "Unsupported type");
}
}
template <typename V, typename... Extra>
void DrawValueRowList(const char* text, V arg, Extra&&... extra_args) {
DrawValueRow(text, arg);
if constexpr (sizeof...(extra_args) > 0) {
DrawValueRowList(std::forward<Extra>(extra_args)...);
}
}
template <typename... Args>
static void DoTooltip(const char* str_id, Args&&... args) {
if (ImGui::BeginTooltip()) {
if (ImGui::BeginTable(str_id, 2, ImGuiTableFlags_Borders | ImGuiTableFlags_RowBg)) {
DrawMultipleRow(std::forward<Args>(args)...);
ImGui::EndTable();
}
ImGui::EndTooltip();
}
}
static bool IsDrawCall(AmdGpu::PM4ItOpcode opcode) {
using AmdGpu::PM4ItOpcode;
switch (opcode) {
case PM4ItOpcode::DrawIndex2:
case PM4ItOpcode::DrawIndexOffset2:
case PM4ItOpcode::DrawIndexAuto:
case PM4ItOpcode::DrawIndirect:
case PM4ItOpcode::DrawIndexIndirect:
case PM4ItOpcode::DispatchDirect:
case PM4ItOpcode::DispatchIndirect:
return true;
default:
return false;
}
}
} // namespace Core::Devtools::Widget
| 2,771
|
C++
|
.h
| 93
| 25.55914
| 98
| 0.671799
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,904
|
cmd_list.h
|
shadps4-emu_shadPS4/src/core/devtools/widget/cmd_list.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
// Credits to https://github.com/psucien/tlg-emu-tools/
#pragma once
#include <memory>
#include <vector>
#include <imgui.h>
#include "common.h"
#include "common/types.h"
#include "imgui_memory_editor.h"
#include "reg_view.h"
namespace AmdGpu {
union PM4Type3Header;
enum class PM4ItOpcode : u32;
} // namespace AmdGpu
namespace Core::Devtools::Widget {
class FrameDumpViewer;
void ParsePolygonControl(u32 value, bool begin_table = true);
void ParseAaConfig(u32 value, bool begin_table = true);
void ParseViewportControl(u32 value, bool begin_table = true);
void ParseColorControl(u32 value, bool begin_table = true);
void ParseColor0Info(u32 value, bool begin_table = true);
void ParseColor0Attrib(u32 value, bool begin_table = true);
void ParseBlendControl(u32 value, bool begin_table = true);
void ParseDepthRenderControl(u32 value, bool begin_table = true);
void ParseDepthControl(u32 value, bool begin_table = true);
void ParseEqaa(u32 value, bool begin_table = true);
void ParseZInfo(u32 value, bool begin_table = true);
class CmdListViewer {
DebugStateType::FrameDump* frame_dump;
uintptr_t base_addr;
std::string name;
std::vector<GPUEvent> events{};
uintptr_t cmdb_addr;
size_t cmdb_size;
std::string cmdb_view_name;
MemoryEditor cmdb_view;
int batch_bp{-1};
int vqid{255};
u32 highlight_batch{~0u};
RegView batch_view;
int last_selected_batch{-1};
std::vector<RegView> extra_batch_view;
static void OnNop(AmdGpu::PM4Type3Header const* header, u32 const* body);
static void OnSetBase(AmdGpu::PM4Type3Header const* header, u32 const* body);
static void OnSetContextReg(AmdGpu::PM4Type3Header const* header, u32 const* body);
static void OnSetShReg(AmdGpu::PM4Type3Header const* header, u32 const* body);
static void OnDispatch(AmdGpu::PM4Type3Header const* header, u32 const* body);
public:
static void LoadConfig(const char* line);
static void SerializeConfig(ImGuiTextBuffer* buf);
explicit CmdListViewer(DebugStateType::FrameDump* frame_dump, const std::vector<u32>& cmd_list,
uintptr_t base_addr = 0, std::string name = "");
void Draw(bool only_batches_view = false);
};
} // namespace Core::Devtools::Widget
| 2,373
|
C++
|
.h
| 56
| 38.892857
| 99
| 0.748367
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,905
|
renderdoc.h
|
shadps4-emu_shadPS4/src/video_core/renderdoc.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string>
namespace VideoCore {
/// Loads renderdoc dynamic library module.
void LoadRenderDoc();
/// Begins a capture if a renderdoc instance is attached.
void StartCapture();
/// Ends current renderdoc capture.
void EndCapture();
/// Triggers capturing process.
void TriggerCapture();
/// Sets output directory for captures
void SetOutputDir(const std::filesystem::path& path, const std::string& prefix);
} // namespace VideoCore
| 574
|
C++
|
.h
| 16
| 34.3125
| 80
| 0.790528
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,906
|
multi_level_page_table.h
|
shadps4-emu_shadPS4/src/video_core/multi_level_page_table.h
|
// SPDX-FileCopyrightText: 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <type_traits>
#include <utility>
#include <vector>
#include "common/object_pool.h"
#include "common/types.h"
namespace VideoCore {
template <class Traits>
class MultiLevelPageTable final {
using Entry = typename Traits::Entry;
static constexpr size_t AddressSpaceBits = Traits::AddressSpaceBits;
static constexpr size_t FirstLevelBits = Traits::FirstLevelBits;
static constexpr size_t PageBits = Traits::PageBits;
static constexpr size_t FirstLevelShift = AddressSpaceBits - FirstLevelBits;
static constexpr size_t SecondLevelBits = FirstLevelShift - PageBits;
static constexpr size_t NumEntriesPerL1Page = 1ULL << SecondLevelBits;
using L1Page = std::array<Entry, NumEntriesPerL1Page>;
public:
explicit MultiLevelPageTable() : first_level_map{1ULL << FirstLevelBits, nullptr} {}
~MultiLevelPageTable() noexcept = default;
[[nodiscard]] Entry* find(size_t page) {
const size_t l1_page = page >> SecondLevelBits;
const size_t l2_page = page & (NumEntriesPerL1Page - 1);
if (!first_level_map[l1_page]) {
return nullptr;
}
return &(*first_level_map[l1_page])[l2_page];
}
[[nodiscard]] const Entry& operator[](size_t page) const {
const size_t l1_page = page >> SecondLevelBits;
const size_t l2_page = page & (NumEntriesPerL1Page - 1);
if (!first_level_map[l1_page]) {
first_level_map[l1_page] = page_alloc.Create();
}
return (*first_level_map[l1_page])[l2_page];
}
[[nodiscard]] Entry& operator[](size_t page) {
const size_t l1_page = page >> SecondLevelBits;
const size_t l2_page = page & (NumEntriesPerL1Page - 1);
if (!first_level_map[l1_page]) {
first_level_map[l1_page] = page_alloc.Create();
}
return (*first_level_map[l1_page])[l2_page];
}
private:
std::vector<L1Page*> first_level_map{};
Common::ObjectPool<L1Page> page_alloc;
};
} // namespace VideoCore
| 2,126
|
C++
|
.h
| 51
| 35.941176
| 88
| 0.679282
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,907
|
page_manager.h
|
shadps4-emu_shadPS4/src/video_core/page_manager.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <memory>
#include <mutex>
#include <boost/icl/interval_map.hpp>
#include "common/types.h"
namespace Vulkan {
class Rasterizer;
}
namespace VideoCore {
class PageManager {
public:
explicit PageManager(Vulkan::Rasterizer* rasterizer);
~PageManager();
/// Register a range of mapped gpu memory.
void OnGpuMap(VAddr address, size_t size);
/// Unregister a range of gpu memory that was unmapped.
void OnGpuUnmap(VAddr address, size_t size);
/// Increase/decrease the number of surface in pages touching the specified region
void UpdatePagesCachedCount(VAddr addr, u64 size, s32 delta);
private:
struct Impl;
std::unique_ptr<Impl> impl;
Vulkan::Rasterizer* rasterizer;
std::mutex mutex;
boost::icl::interval_map<VAddr, s32> cached_pages;
};
} // namespace VideoCore
| 956
|
C++
|
.h
| 29
| 29.827586
| 86
| 0.750273
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,908
|
vk_descriptor_update_queue.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_descriptor_update_queue.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include <memory>
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
class Instance;
struct DescriptorInfoUnion {
DescriptorInfoUnion() {}
union {
vk::DescriptorImageInfo image_info;
vk::DescriptorBufferInfo buffer_info;
vk::BufferView buffer_view;
};
};
class DescriptorUpdateQueue {
public:
explicit DescriptorUpdateQueue(const Instance& instance, u32 descriptor_write_max = 2048);
~DescriptorUpdateQueue() = default;
void Flush();
void AddStorageImage(vk::DescriptorSet target, u8 binding, vk::ImageView image_view,
vk::ImageLayout image_layout = vk::ImageLayout::eGeneral);
void AddImageSampler(vk::DescriptorSet target, u8 binding, u8 array_index,
vk::ImageView image_view, vk::Sampler sampler,
vk::ImageLayout imageLayout = vk::ImageLayout::eGeneral);
void AddBuffer(vk::DescriptorSet target, u8 binding, vk::Buffer buffer, vk::DeviceSize offset,
vk::DeviceSize size = VK_WHOLE_SIZE,
vk::DescriptorType type = vk::DescriptorType::eUniformBufferDynamic);
void AddTexelBuffer(vk::DescriptorSet target, u8 binding, vk::BufferView buffer_view);
private:
const vk::Device device;
const u32 descriptor_write_max;
std::unique_ptr<DescriptorInfoUnion[]> descriptor_infos;
std::unique_ptr<vk::WriteDescriptorSet[]> descriptor_writes;
u32 descriptor_write_end = 0;
};
} // namespace Vulkan
| 1,653
|
C++
|
.h
| 37
| 37.972973
| 98
| 0.707241
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,909
|
renderer_vulkan.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/renderer_vulkan.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <condition_variable>
#include "video_core/amdgpu/liverpool.h"
#include "video_core/renderer_vulkan/vk_instance.h"
#include "video_core/renderer_vulkan/vk_scheduler.h"
#include "video_core/renderer_vulkan/vk_swapchain.h"
#include "video_core/texture_cache/texture_cache.h"
namespace Frontend {
class WindowSDL;
}
namespace AmdGpu {
struct Liverpool;
}
namespace Vulkan {
struct Frame {
u32 width;
u32 height;
VmaAllocation allocation;
vk::Image image;
vk::ImageView image_view;
vk::Fence present_done;
vk::Semaphore ready_semaphore;
u64 ready_tick;
};
enum SchedulerType {
Draw,
Present,
CpuFlip,
};
class Rasterizer;
class RendererVulkan {
public:
explicit RendererVulkan(Frontend::WindowSDL& window, AmdGpu::Liverpool* liverpool);
~RendererVulkan();
Frame* PrepareFrame(const Libraries::VideoOut::BufferAttributeGroup& attribute,
VAddr cpu_address, bool is_eop) {
const auto info = VideoCore::ImageInfo{attribute, cpu_address};
const auto image_id = texture_cache.FindImage(info);
texture_cache.UpdateImage(image_id, is_eop ? nullptr : &flip_scheduler);
auto& image = texture_cache.GetImage(image_id);
return PrepareFrameInternal(image, is_eop);
}
Frame* PrepareBlankFrame(bool is_eop) {
auto& image = texture_cache.GetImage(VideoCore::NULL_IMAGE_ID);
return PrepareFrameInternal(image, is_eop);
}
VideoCore::Image& RegisterVideoOutSurface(
const Libraries::VideoOut::BufferAttributeGroup& attribute, VAddr cpu_address) {
vo_buffers_addr.emplace_back(cpu_address);
const auto info = VideoCore::ImageInfo{attribute, cpu_address};
const auto image_id = texture_cache.FindImage(info);
return texture_cache.GetImage(image_id);
}
bool IsVideoOutSurface(const AmdGpu::Liverpool::ColorBuffer& color_buffer) {
return std::ranges::find_if(vo_buffers_addr, [&](VAddr vo_buffer) {
return vo_buffer == color_buffer.Address();
}) != vo_buffers_addr.cend();
}
bool ShowSplash(Frame* frame = nullptr);
void Present(Frame* frame);
void RecreateFrame(Frame* frame, u32 width, u32 height);
void FlushDraw() {
SubmitInfo info{};
draw_scheduler.Flush(info);
}
private:
Frame* PrepareFrameInternal(VideoCore::Image& image, bool is_eop = true);
Frame* GetRenderFrame();
private:
Frontend::WindowSDL& window;
AmdGpu::Liverpool* liverpool;
Instance instance;
Scheduler draw_scheduler;
Scheduler present_scheduler;
Scheduler flip_scheduler;
Swapchain swapchain;
std::unique_ptr<Rasterizer> rasterizer;
VideoCore::TextureCache& texture_cache;
vk::UniqueCommandPool command_pool;
std::vector<Frame> present_frames;
std::queue<Frame*> free_queue;
std::mutex free_mutex;
std::condition_variable free_cv;
std::condition_variable_any frame_cv;
std::optional<VideoCore::Image> splash_img;
std::vector<VAddr> vo_buffers_addr;
};
} // namespace Vulkan
| 3,230
|
C++
|
.h
| 90
| 30.7
| 88
| 0.710349
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,910
|
vk_rasterizer.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_rasterizer.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "video_core/buffer_cache/buffer_cache.h"
#include "video_core/page_manager.h"
#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
#include "video_core/texture_cache/texture_cache.h"
namespace AmdGpu {
struct Liverpool;
}
namespace Core {
class MemoryManager;
}
namespace Vulkan {
class Scheduler;
class GraphicsPipeline;
class Rasterizer {
public:
explicit Rasterizer(const Instance& instance, Scheduler& scheduler,
AmdGpu::Liverpool* liverpool);
~Rasterizer();
[[nodiscard]] VideoCore::TextureCache& GetTextureCache() noexcept {
return texture_cache;
}
void Draw(bool is_indexed, u32 index_offset = 0);
void DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 size);
void DispatchDirect();
void DispatchIndirect(VAddr address, u32 offset, u32 size);
void ScopeMarkerBegin(const std::string_view& str);
void ScopeMarkerEnd();
void ScopedMarkerInsert(const std::string_view& str);
void ScopedMarkerInsertColor(const std::string_view& str, const u32 color);
void InlineData(VAddr address, const void* value, u32 num_bytes, bool is_gds);
u32 ReadDataFromGds(u32 gsd_offset);
void InvalidateMemory(VAddr addr, u64 size);
void MapMemory(VAddr addr, u64 size);
void UnmapMemory(VAddr addr, u64 size);
void CpSync();
u64 Flush();
void Finish();
private:
void BeginRendering(const GraphicsPipeline& pipeline);
void Resolve();
void UpdateDynamicState(const GraphicsPipeline& pipeline);
void UpdateViewportScissorState();
void UpdateDepthStencilState();
bool FilterDraw();
private:
const Instance& instance;
Scheduler& scheduler;
VideoCore::PageManager page_manager;
VideoCore::BufferCache buffer_cache;
VideoCore::TextureCache texture_cache;
AmdGpu::Liverpool* liverpool;
Core::MemoryManager* memory;
PipelineCache pipeline_cache;
};
} // namespace Vulkan
| 2,082
|
C++
|
.h
| 58
| 31.689655
| 82
| 0.747258
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,911
|
vk_scheduler.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_scheduler.h
|
// SPDX-FileCopyrightText: Copyright 2019 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <condition_variable>
#include <boost/container/static_vector.hpp>
#include "common/types.h"
#include "common/unique_function.h"
#include "video_core/renderer_vulkan/vk_master_semaphore.h"
#include "video_core/renderer_vulkan/vk_resource_pool.h"
namespace Vulkan {
class Instance;
struct RenderState {
std::array<vk::RenderingAttachmentInfo, 8> color_attachments{};
std::array<vk::Image, 8> color_images{};
vk::RenderingAttachmentInfo depth_attachment{};
vk::Image depth_image{};
u32 num_color_attachments{};
bool has_depth{};
bool has_stencil{};
u32 width = std::numeric_limits<u32>::max();
u32 height = std::numeric_limits<u32>::max();
bool operator==(const RenderState& other) const noexcept {
return std::memcmp(this, &other, sizeof(RenderState)) == 0;
}
};
struct SubmitInfo {
boost::container::static_vector<vk::Semaphore, 3> wait_semas;
boost::container::static_vector<u64, 3> wait_ticks;
boost::container::static_vector<vk::Semaphore, 3> signal_semas;
boost::container::static_vector<u64, 3> signal_ticks;
vk::Fence fence;
void AddWait(vk::Semaphore semaphore, u64 tick = 1) {
wait_semas.emplace_back(semaphore);
wait_ticks.emplace_back(tick);
}
void AddSignal(vk::Semaphore semaphore, u64 tick = 1) {
signal_semas.emplace_back(semaphore);
signal_ticks.emplace_back(tick);
}
void AddSignal(vk::Fence fence) {
this->fence = fence;
}
};
class Scheduler {
public:
explicit Scheduler(const Instance& instance);
~Scheduler();
/// Sends the current execution context to the GPU
/// and increments the scheduler timeline semaphore.
void Flush(SubmitInfo& info);
/// Sends the current execution context to the GPU and waits for it to complete.
void Finish();
/// Waits for the given tick to trigger on the GPU.
void Wait(u64 tick);
/// Starts a new rendering scope with provided state.
void BeginRendering(const RenderState& new_state);
/// Ends current rendering scope.
void EndRendering();
/// Returns the current render state.
const RenderState& GetRenderState() const {
return render_state;
}
/// Returns the current command buffer.
vk::CommandBuffer CommandBuffer() const {
return current_cmdbuf;
}
/// Returns the current command buffer tick.
[[nodiscard]] u64 CurrentTick() const noexcept {
return master_semaphore.CurrentTick();
}
/// Returns true when a tick has been triggered by the GPU.
[[nodiscard]] bool IsFree(u64 tick) const noexcept {
return master_semaphore.IsFree(tick);
}
/// Returns the master timeline semaphore.
[[nodiscard]] MasterSemaphore* GetMasterSemaphore() noexcept {
return &master_semaphore;
}
/// Defers an operation until the gpu has reached the current cpu tick.
void DeferOperation(Common::UniqueFunction<void>&& func) {
pending_ops.emplace(std::move(func), CurrentTick());
}
static std::mutex submit_mutex;
private:
void AllocateWorkerCommandBuffers();
void SubmitExecution(SubmitInfo& info);
private:
const Instance& instance;
MasterSemaphore master_semaphore;
CommandPool command_pool;
vk::CommandBuffer current_cmdbuf;
std::condition_variable_any event_cv;
struct PendingOp {
Common::UniqueFunction<void> callback;
u64 gpu_tick;
};
std::queue<PendingOp> pending_ops;
RenderState render_state;
bool is_rendering = false;
tracy::VkCtxScope* profiler_scope{};
};
} // namespace Vulkan
| 3,759
|
C++
|
.h
| 102
| 31.862745
| 84
| 0.702479
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,912
|
vk_compute_pipeline.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_compute_pipeline.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "video_core/renderer_vulkan/vk_common.h"
#include "video_core/renderer_vulkan/vk_pipeline_common.h"
namespace VideoCore {
class BufferCache;
class TextureCache;
} // namespace VideoCore
namespace Vulkan {
class Instance;
class Scheduler;
class DescriptorHeap;
class ComputePipeline : public Pipeline {
public:
ComputePipeline(const Instance& instance, Scheduler& scheduler, DescriptorHeap& desc_heap,
vk::PipelineCache pipeline_cache, u64 compute_key, const Shader::Info& info,
vk::ShaderModule module);
~ComputePipeline();
bool BindResources(VideoCore::BufferCache& buffer_cache,
VideoCore::TextureCache& texture_cache) const;
private:
u64 compute_key;
const Shader::Info* info;
bool uses_push_descriptors{};
};
} // namespace Vulkan
| 965
|
C++
|
.h
| 27
| 31.185185
| 96
| 0.741658
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,913
|
vk_master_semaphore.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_master_semaphore.h
|
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <atomic>
#include <condition_variable>
#include <thread>
#include <queue>
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
class Instance;
class Scheduler;
class MasterSemaphore {
public:
explicit MasterSemaphore(const Instance& instance_);
~MasterSemaphore();
[[nodiscard]] u64 CurrentTick() const noexcept {
return current_tick.load(std::memory_order_acquire);
}
[[nodiscard]] u64 KnownGpuTick() const noexcept {
return gpu_tick.load(std::memory_order_acquire);
}
[[nodiscard]] bool IsFree(u64 tick) const noexcept {
return KnownGpuTick() >= tick;
}
[[nodiscard]] u64 NextTick() noexcept {
return current_tick.fetch_add(1, std::memory_order_release);
}
[[nodiscard]] vk::Semaphore Handle() const noexcept {
return semaphore.get();
}
/// Refresh the known GPU tick
void Refresh();
/// Waits for a tick to be hit on the GPU
void Wait(u64 tick);
protected:
const Instance& instance;
vk::UniqueSemaphore semaphore; ///< Timeline semaphore.
std::atomic<u64> gpu_tick{0}; ///< Current known GPU tick.
std::atomic<u64> current_tick{1}; ///< Current logical tick.
};
} // namespace Vulkan
| 1,401
|
C++
|
.h
| 42
| 29.166667
| 68
| 0.694424
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,914
|
vk_resource_pool.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_resource_pool.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <deque>
#include <vector>
#include <boost/container/static_vector.hpp>
#include <tsl/robin_map.h>
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
class Instance;
class MasterSemaphore;
/**
* Handles a pool of resources protected by fences. Manages resource overflow allocating more
* resources.
*/
class ResourcePool {
public:
explicit ResourcePool() = default;
explicit ResourcePool(MasterSemaphore* master_semaphore, std::size_t grow_step);
virtual ~ResourcePool() = default;
ResourcePool& operator=(ResourcePool&&) noexcept = default;
ResourcePool(ResourcePool&&) noexcept = default;
ResourcePool& operator=(const ResourcePool&) = default;
ResourcePool(const ResourcePool&) = default;
protected:
std::size_t CommitResource();
/// Called when a chunk of resources have to be allocated.
virtual void Allocate(std::size_t begin, std::size_t end) = 0;
private:
/// Manages pool overflow allocating new resources.
std::size_t ManageOverflow();
protected:
MasterSemaphore* master_semaphore{nullptr};
std::size_t grow_step = 0; ///< Number of new resources created after an overflow
std::size_t hint_iterator = 0; ///< Hint to where the next free resources is likely to be found
std::vector<u64> ticks; ///< Ticks for each resource
};
class CommandPool final : public ResourcePool {
public:
explicit CommandPool(const Instance& instance, MasterSemaphore* master_semaphore);
~CommandPool() override;
void Allocate(std::size_t begin, std::size_t end) override;
vk::CommandBuffer Commit();
private:
const Instance& instance;
vk::UniqueCommandPool cmd_pool;
std::vector<vk::CommandBuffer> cmd_buffers;
};
class DescriptorHeap final {
static constexpr u32 DescriptorSetBatch = 32;
public:
explicit DescriptorHeap(const Instance& instance, MasterSemaphore* master_semaphore,
std::span<const vk::DescriptorPoolSize> pool_sizes,
u32 descriptor_heap_count = 1024);
~DescriptorHeap();
vk::DescriptorSet Commit(vk::DescriptorSetLayout set_layout);
private:
void CreateDescriptorPool();
private:
vk::Device device;
MasterSemaphore* master_semaphore;
u32 descriptor_heap_count;
std::span<const vk::DescriptorPoolSize> pool_sizes;
vk::DescriptorPool curr_pool;
std::deque<std::pair<vk::DescriptorPool, u64>> pending_pools;
using DescSetBatch = boost::container::static_vector<vk::DescriptorSet, DescriptorSetBatch>;
tsl::robin_map<u64, DescSetBatch> descriptor_sets;
};
} // namespace Vulkan
| 2,791
|
C++
|
.h
| 70
| 35.657143
| 99
| 0.735458
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,915
|
liverpool_to_vk.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/liverpool_to_vk.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include "common/assert.h"
#include "video_core/amdgpu/liverpool.h"
#include "video_core/amdgpu/pixel_format.h"
#include "video_core/amdgpu/resource.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan::LiverpoolToVK {
using Liverpool = AmdGpu::Liverpool;
vk::StencilOp StencilOp(Liverpool::StencilFunc op);
vk::CompareOp CompareOp(Liverpool::CompareFunc func);
vk::PrimitiveTopology PrimitiveType(AmdGpu::PrimitiveType type);
vk::PolygonMode PolygonMode(Liverpool::PolygonMode mode);
vk::CullModeFlags CullMode(Liverpool::CullMode mode);
vk::BlendFactor BlendFactor(Liverpool::BlendControl::BlendFactor factor);
vk::BlendOp BlendOp(Liverpool::BlendControl::BlendFunc func);
vk::SamplerAddressMode ClampMode(AmdGpu::ClampMode mode);
vk::CompareOp DepthCompare(AmdGpu::DepthCompare comp);
vk::Filter Filter(AmdGpu::Filter filter);
vk::SamplerReductionMode FilterMode(AmdGpu::FilterMode mode);
vk::SamplerMipmapMode MipFilter(AmdGpu::MipFilter filter);
vk::BorderColor BorderColor(AmdGpu::BorderColor color);
struct SurfaceFormatInfo {
AmdGpu::DataFormat data_format;
AmdGpu::NumberFormat number_format;
vk::Format vk_format;
vk::FormatFeatureFlags2 flags;
};
std::span<const SurfaceFormatInfo> SurfaceFormats();
vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_format);
vk::Format AdjustColorBufferFormat(vk::Format base_format,
Liverpool::ColorBuffer::SwapMode comp_swap, bool is_vo_surface);
struct DepthFormatInfo {
Liverpool::DepthBuffer::ZFormat z_format;
Liverpool::DepthBuffer::StencilFormat stencil_format;
vk::Format vk_format;
vk::FormatFeatureFlags2 flags;
};
std::span<const DepthFormatInfo> DepthFormats();
vk::Format DepthFormat(Liverpool::DepthBuffer::ZFormat z_format,
Liverpool::DepthBuffer::StencilFormat stencil_format);
vk::ClearValue ColorBufferClearValue(const AmdGpu::Liverpool::ColorBuffer& color_buffer);
vk::SampleCountFlagBits NumSamples(u32 num_samples, vk::SampleCountFlags supported_flags);
void EmitQuadToTriangleListIndices(u8* out_indices, u32 num_vertices);
static inline vk::Format PromoteFormatToDepth(vk::Format fmt) {
if (fmt == vk::Format::eR32Sfloat) {
return vk::Format::eD32Sfloat;
} else if (fmt == vk::Format::eR16Unorm) {
return vk::Format::eD16Unorm;
}
UNREACHABLE();
}
} // namespace Vulkan::LiverpoolToVK
| 2,592
|
C++
|
.h
| 55
| 43.418182
| 99
| 0.778884
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,916
|
vk_graphics_pipeline.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_graphics_pipeline.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include <xxhash.h>
#include "common/types.h"
#include "video_core/renderer_vulkan/liverpool_to_vk.h"
#include "video_core/renderer_vulkan/vk_common.h"
#include "video_core/renderer_vulkan/vk_pipeline_common.h"
namespace VideoCore {
class BufferCache;
class TextureCache;
} // namespace VideoCore
namespace Vulkan {
static constexpr u32 MaxVertexBufferCount = 32;
static constexpr u32 MaxShaderStages = 5;
class Instance;
class Scheduler;
class DescriptorHeap;
using Liverpool = AmdGpu::Liverpool;
struct GraphicsPipelineKey {
std::array<size_t, MaxShaderStages> stage_hashes;
std::array<vk::Format, Liverpool::NumColorBuffers> color_formats;
std::array<AmdGpu::NumberFormat, Liverpool::NumColorBuffers> color_num_formats;
std::array<Liverpool::ColorBuffer::SwapMode, Liverpool::NumColorBuffers> mrt_swizzles;
vk::Format depth_format;
vk::Format stencil_format;
Liverpool::DepthControl depth_stencil;
u32 depth_bias_enable;
u32 num_samples;
u32 mrt_mask;
Liverpool::StencilControl stencil;
AmdGpu::PrimitiveType prim_type;
u32 enable_primitive_restart;
u32 primitive_restart_index;
Liverpool::PolygonMode polygon_mode;
Liverpool::CullMode cull_mode;
Liverpool::FrontFace front_face;
Liverpool::ClipSpace clip_space;
Liverpool::ColorBufferMask cb_shader_mask;
std::array<Liverpool::BlendControl, Liverpool::NumColorBuffers> blend_controls;
std::array<vk::ColorComponentFlags, Liverpool::NumColorBuffers> write_masks;
std::array<vk::Format, MaxVertexBufferCount> vertex_buffer_formats;
bool operator==(const GraphicsPipelineKey& key) const noexcept {
return std::memcmp(this, &key, sizeof(key)) == 0;
}
};
class GraphicsPipeline : public Pipeline {
public:
GraphicsPipeline(const Instance& instance, Scheduler& scheduler, DescriptorHeap& desc_heap,
const GraphicsPipelineKey& key, vk::PipelineCache pipeline_cache,
std::span<const Shader::Info*, MaxShaderStages> stages,
std::span<const vk::ShaderModule> modules);
~GraphicsPipeline();
void BindResources(const Liverpool::Regs& regs, VideoCore::BufferCache& buffer_cache,
VideoCore::TextureCache& texture_cache) const;
const Shader::Info& GetStage(Shader::Stage stage) const noexcept {
return *stages[u32(stage)];
}
bool IsEmbeddedVs() const noexcept {
static constexpr size_t EmbeddedVsHash = 0x9b2da5cf47f8c29f;
return key.stage_hashes[u32(Shader::Stage::Vertex)] == EmbeddedVsHash;
}
auto GetWriteMasks() const {
return key.write_masks;
}
auto GetMrtMask() const {
return key.mrt_mask;
}
bool IsDepthEnabled() const {
return key.depth_stencil.depth_enable.Value();
}
[[nodiscard]] bool IsPrimitiveListTopology() const {
return key.prim_type == AmdGpu::PrimitiveType::PointList ||
key.prim_type == AmdGpu::PrimitiveType::LineList ||
key.prim_type == AmdGpu::PrimitiveType::TriangleList ||
key.prim_type == AmdGpu::PrimitiveType::AdjLineList ||
key.prim_type == AmdGpu::PrimitiveType::AdjTriangleList ||
key.prim_type == AmdGpu::PrimitiveType::RectList ||
key.prim_type == AmdGpu::PrimitiveType::QuadList;
}
private:
void BuildDescSetLayout();
private:
std::array<const Shader::Info*, MaxShaderStages> stages{};
GraphicsPipelineKey key;
bool uses_push_descriptors{};
};
} // namespace Vulkan
template <>
struct std::hash<Vulkan::GraphicsPipelineKey> {
std::size_t operator()(const Vulkan::GraphicsPipelineKey& key) const noexcept {
return XXH3_64bits(&key, sizeof(key));
}
};
| 3,886
|
C++
|
.h
| 93
| 35.956989
| 95
| 0.713415
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,917
|
vk_instance.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_instance.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include <unordered_map>
#include "video_core/renderer_vulkan/vk_platform.h"
#define TRACY_VK_USE_SYMBOL_TABLE
#include <tracy/TracyVulkan.hpp>
namespace Frontend {
class WindowSDL;
}
VK_DEFINE_HANDLE(VmaAllocator)
namespace Vulkan {
class Instance {
public:
explicit Instance(bool validation = false, bool crash_diagnostic = false);
explicit Instance(Frontend::WindowSDL& window, s32 physical_device_index,
bool enable_validation = false, bool enable_crash_diagnostic = false);
~Instance();
/// Returns a formatted string for the driver version
std::string GetDriverVersionName();
/// Gets a compatibility format if the format is not supported.
[[nodiscard]] vk::Format GetSupportedFormat(vk::Format format,
vk::FormatFeatureFlags2 flags) const;
/// Re-orders a component swizzle for format compatibility, if needed.
[[nodiscard]] vk::ComponentMapping GetSupportedComponentSwizzle(
vk::Format format, vk::ComponentMapping swizzle, vk::FormatFeatureFlags2 flags) const;
/// Returns the Vulkan instance
vk::Instance GetInstance() const {
return *instance;
}
/// Returns the current physical device
vk::PhysicalDevice GetPhysicalDevice() const {
return physical_device;
}
/// Returns the Vulkan device
vk::Device GetDevice() const {
return *device;
}
/// Returns the VMA allocator handle
VmaAllocator GetAllocator() const {
return allocator;
}
/// Returns a list of the available physical devices
std::span<const vk::PhysicalDevice> GetPhysicalDevices() const {
return physical_devices;
}
/// Retrieve queue information
u32 GetGraphicsQueueFamilyIndex() const {
return queue_family_index;
}
u32 GetPresentQueueFamilyIndex() const {
return queue_family_index;
}
vk::Queue GetGraphicsQueue() const {
return graphics_queue;
}
vk::Queue GetPresentQueue() const {
return present_queue;
}
TracyVkCtx GetProfilerContext() const {
return profiler_context;
}
/// Returns true when a known debugging tool is attached.
bool HasDebuggingToolAttached() const {
return has_renderdoc || has_nsight_graphics;
}
/// Returns true if anisotropic filtering is supported
bool IsAnisotropicFilteringSupported() const {
return features.samplerAnisotropy;
}
/// Returns true when VK_EXT_custom_border_color is supported
bool IsCustomBorderColorSupported() const {
return custom_border_color;
}
/// Returns true when VK_EXT_fragment_shader_interlock is supported
bool IsFragmentShaderInterlockSupported() const {
return fragment_shader_interlock;
}
/// Returns true when VK_EXT_pipeline_creation_cache_control is supported
bool IsPipelineCreationCacheControlSupported() const {
return pipeline_creation_cache_control;
}
/// Returns true when VK_EXT_shader_stencil_export is supported
bool IsShaderStencilExportSupported() const {
return shader_stencil_export;
}
/// Returns true when VK_EXT_external_memory_host is supported
bool IsExternalMemoryHostSupported() const {
return external_memory_host;
}
/// Returns true when VK_EXT_depth_clip_control is supported
bool IsDepthClipControlSupported() const {
return depth_clip_control;
}
/// Returns true when VK_EXT_color_write_enable is supported
bool IsColorWriteEnableSupported() const {
return color_write_en;
}
/// Returns true when VK_EXT_vertex_input_dynamic_state is supported.
bool IsVertexInputDynamicState() const {
return vertex_input_dynamic_state;
}
/// Returns true when the nullDescriptor feature of VK_EXT_robustness2 is supported.
bool IsNullDescriptorSupported() const {
return null_descriptor;
}
/// Returns true when VK_KHR_maintenance5 is supported.
bool IsMaintenance5Supported() const {
return maintenance5;
}
bool IsListRestartSupported() const {
return list_restart;
}
/// Returns true when geometry shaders are supported by the device
bool IsGeometryStageSupported() const {
return features.geometryShader;
}
/// Returns true when tessellation is supported by the device
bool IsTessellationSupported() const {
return features.tessellationShader;
}
/// Returns the vendor ID of the physical device
u32 GetVendorID() const {
return properties.vendorID;
}
/// Returns the device ID of the physical device
u32 GetDeviceID() const {
return properties.deviceID;
}
/// Returns the driver ID.
vk::DriverId GetDriverID() const {
return driver_id;
}
/// Returns the current driver version provided in Vulkan-formatted version numbers.
u32 GetDriverVersion() const {
return properties.driverVersion;
}
/// Returns the current Vulkan API version provided in Vulkan-formatted version numbers.
u32 ApiVersion() const {
return properties.apiVersion;
}
/// Returns the vendor name reported from Vulkan.
std::string_view GetVendorName() const {
return vendor_name;
}
/// Returns the list of available extensions.
std::span<const std::string> GetAvailableExtensions() const {
return available_extensions;
}
/// Returns the device name.
std::string_view GetModelName() const {
return properties.deviceName;
}
/// Returns the pipeline cache unique identifier
const auto GetPipelineCacheUUID() const {
return properties.pipelineCacheUUID;
}
/// Returns the minimum required alignment for uniforms
vk::DeviceSize UniformMinAlignment() const {
return properties.limits.minUniformBufferOffsetAlignment;
}
/// Returns the minimum required alignment for storage buffers
vk::DeviceSize StorageMinAlignment() const {
return properties.limits.minStorageBufferOffsetAlignment;
}
/// Returns the minimum required alignment for texel buffers
vk::DeviceSize TexelBufferMinAlignment() const {
return properties.limits.minTexelBufferOffsetAlignment;
}
/// Returns the minimum alignemt required for accessing host-mapped device memory
vk::DeviceSize NonCoherentAtomSize() const {
return properties.limits.nonCoherentAtomSize;
}
/// Returns the subgroup size of the selected physical device.
u32 SubgroupSize() const {
return subgroup_size;
}
/// Returns the maximum supported elements in a texel buffer
u32 MaxTexelBufferElements() const {
return properties.limits.maxTexelBufferElements;
}
/// Returns the maximum sampler LOD bias.
float MaxSamplerLodBias() const {
return properties.limits.maxSamplerLodBias;
}
/// Returns the maximum number of push descriptors.
u32 MaxPushDescriptors() const {
return push_descriptor_props.maxPushDescriptors;
}
/// Returns the vulkan 1.2 physical device properties.
const vk::PhysicalDeviceVulkan12Properties& GetVk12Properties() const noexcept {
return vk12_props;
}
/// Returns true if shaders can declare the ClipDistance attribute
bool IsShaderClipDistanceSupported() const {
return features.shaderClipDistance;
}
/// Returns the minimum imported host pointer alignment
u64 GetMinImportedHostPointerAlignment() const {
return min_imported_host_pointer_alignment;
}
/// Returns the sample count flags supported by framebuffers.
vk::SampleCountFlags GetFramebufferSampleCounts() const {
return properties.limits.framebufferColorSampleCounts &
properties.limits.framebufferDepthSampleCounts &
properties.limits.framebufferStencilSampleCounts;
}
private:
/// Creates the logical device opportunistically enabling extensions
bool CreateDevice();
/// Creates the VMA allocator handle
void CreateAllocator();
/// Collects telemetry information from the device.
void CollectDeviceParameters();
void CollectToolingInfo();
/// Gets the supported feature flags for a format.
[[nodiscard]] vk::FormatFeatureFlags2 GetFormatFeatureFlags(vk::Format format) const;
/// Determines if a format is supported for a set of feature flags.
[[nodiscard]] bool IsFormatSupported(vk::Format format, vk::FormatFeatureFlags2 flags) const;
private:
vk::UniqueInstance instance;
vk::PhysicalDevice physical_device;
vk::UniqueDevice device;
vk::PhysicalDeviceProperties properties;
vk::PhysicalDevicePushDescriptorPropertiesKHR push_descriptor_props;
vk::PhysicalDeviceVulkan12Properties vk12_props;
vk::PhysicalDeviceFeatures features;
vk::DriverIdKHR driver_id;
vk::UniqueDebugUtilsMessengerEXT debug_callback{};
std::string vendor_name;
VmaAllocator allocator{};
vk::Queue present_queue;
vk::Queue graphics_queue;
std::vector<vk::PhysicalDevice> physical_devices;
std::vector<std::string> available_extensions;
std::unordered_map<vk::Format, vk::FormatProperties3> format_properties;
TracyVkCtx profiler_context{};
u32 queue_family_index{0};
bool image_view_reinterpretation{true};
bool timeline_semaphores{};
bool custom_border_color{};
bool fragment_shader_interlock{};
bool pipeline_creation_cache_control{};
bool fragment_shader_barycentric{};
bool shader_stencil_export{};
bool external_memory_host{};
bool depth_clip_control{};
bool workgroup_memory_explicit_layout{};
bool color_write_en{};
bool vertex_input_dynamic_state{};
bool null_descriptor{};
bool maintenance5{};
bool list_restart{};
u64 min_imported_host_pointer_alignment{};
u32 subgroup_size{};
bool tooling_info{};
bool debug_utils_supported{};
bool has_nsight_graphics{};
bool has_renderdoc{};
};
} // namespace Vulkan
| 10,264
|
C++
|
.h
| 262
| 33.183206
| 97
| 0.717649
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,918
|
vk_platform.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_platform.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <memory>
#include <variant>
#include <fmt/format.h>
#include "common/logging/log.h"
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Frontend {
enum class WindowSystemType : u8;
class WindowSDL;
} // namespace Frontend
namespace Vulkan {
constexpr u32 TargetVulkanApiVersion = VK_API_VERSION_1_2;
vk::SurfaceKHR CreateSurface(vk::Instance instance, const Frontend::WindowSDL& emu_window);
vk::UniqueInstance CreateInstance(Frontend::WindowSystemType window_type, bool enable_validation,
bool enable_crash_diagnostic);
vk::UniqueDebugUtilsMessengerEXT CreateDebugCallback(vk::Instance instance);
template <typename T>
concept VulkanHandleType = vk::isVulkanHandleType<T>::value;
template <VulkanHandleType HandleType>
void SetObjectName(vk::Device device, const HandleType& handle, std::string_view debug_name) {
const vk::DebugUtilsObjectNameInfoEXT name_info = {
.objectType = HandleType::objectType,
.objectHandle = reinterpret_cast<u64>(static_cast<typename HandleType::NativeType>(handle)),
.pObjectName = debug_name.data(),
};
auto result = device.setDebugUtilsObjectNameEXT(name_info);
if (result != vk::Result::eSuccess) {
LOG_DEBUG(Render_Vulkan, "Could not set object debug name: {}", vk::to_string(result));
}
}
template <VulkanHandleType HandleType, typename... Args>
void SetObjectName(vk::Device device, const HandleType& handle, const char* format,
const Args&... args) {
const std::string debug_name = fmt::vformat(format, fmt::make_format_args(args...));
SetObjectName(device, handle, debug_name);
}
} // namespace Vulkan
| 1,835
|
C++
|
.h
| 40
| 41.725
| 100
| 0.74523
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,919
|
vk_common.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_common.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#if defined(__APPLE__) && !USE_SYSTEM_VULKAN_LOADER
#define VULKAN_HPP_ENABLE_DYNAMIC_LOADER_TOOL 0
#endif
// Include vulkan-hpp header
#define VK_ENABLE_BETA_EXTENSIONS
#define VK_NO_PROTOTYPES
#define VULKAN_HPP_DISPATCH_LOADER_DYNAMIC 1
#define VULKAN_HPP_NO_CONSTRUCTORS
#define VULKAN_HPP_NO_STRUCT_SETTERS
#define VULKAN_HPP_HAS_SPACESHIP_OPERATOR
#define VULKAN_HPP_NO_EXCEPTIONS
// Define assert-on-result to nothing to instead return the result for our handling.
#define VULKAN_HPP_ASSERT_ON_RESULT
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wunused-value"
#include <vulkan/vulkan.hpp>
#pragma clang diagnostic pop
#define VMA_STATIC_VULKAN_FUNCTIONS 0
#define VMA_DYNAMIC_VULKAN_FUNCTIONS 1
| 853
|
C++
|
.h
| 22
| 37.545455
| 84
| 0.818402
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,920
|
vk_shader_util.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_shader_util.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
/**
* @brief Creates a vulkan shader module from GLSL by converting it to SPIR-V using glslang.
* @param code The string containing GLSL code.
* @param stage The pipeline stage the shader will be used in.
* @param device The vulkan device handle.
*/
vk::ShaderModule Compile(std::string_view code, vk::ShaderStageFlagBits stage, vk::Device device);
/**
* @brief Creates a vulkan shader module from SPIR-V bytecode.
* @param code The SPIR-V bytecode data.
* @param device The vulkan device handle
*/
vk::ShaderModule CompileSPV(std::span<const u32> code, vk::Device device);
} // namespace Vulkan
| 848
|
C++
|
.h
| 21
| 38.619048
| 98
| 0.767073
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,921
|
vk_swapchain.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_swapchain.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <mutex>
#include <vector>
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Frontend {
class WindowSDL;
}
namespace Vulkan {
class Instance;
class Scheduler;
class Swapchain {
public:
explicit Swapchain(const Instance& instance, const Frontend::WindowSDL& window);
~Swapchain();
/// Creates (or recreates) the swapchain with a given size.
void Create(u32 width, u32 height, vk::SurfaceKHR surface);
/// Recreates the swapchain with a given size and current surface.
void Recreate(u32 width, u32 height);
/// Acquires the next image in the swapchain.
bool AcquireNextImage();
/// Presents the current image and move to the next one
void Present();
vk::SurfaceKHR GetSurface() const {
return surface;
}
vk::Image Image() const {
return images[image_index];
}
vk::SurfaceFormatKHR GetSurfaceFormat() const {
return surface_format;
}
vk::SwapchainKHR GetHandle() const {
return swapchain;
}
u32 GetWidth() const {
return width;
}
u32 GetHeight() const {
return height;
}
u32 GetImageCount() const {
return image_count;
}
u32 GetFrameIndex() const {
return frame_index;
}
vk::Extent2D GetExtent() const {
return extent;
}
[[nodiscard]] vk::Semaphore GetImageAcquiredSemaphore() const {
return image_acquired[frame_index];
}
[[nodiscard]] vk::Semaphore GetPresentReadySemaphore() const {
return present_ready[image_index];
}
private:
/// Selects the best available swapchain image format
void FindPresentFormat();
/// Sets the surface properties according to device capabilities
void SetSurfaceProperties();
/// Destroys current swapchain resources
void Destroy();
/// Performs creation of image views and framebuffers from the swapchain images
void SetupImages();
/// Creates the image acquired and present ready semaphores
void RefreshSemaphores();
private:
const Instance& instance;
vk::SwapchainKHR swapchain{};
vk::SurfaceKHR surface{};
vk::SurfaceFormatKHR surface_format;
vk::Extent2D extent;
vk::SurfaceTransformFlagBitsKHR transform;
vk::CompositeAlphaFlagBitsKHR composite_alpha;
std::vector<vk::Image> images;
std::vector<vk::Semaphore> image_acquired;
std::vector<vk::Semaphore> present_ready;
u32 width = 0;
u32 height = 0;
u32 image_count = 0;
u32 image_index = 0;
u32 frame_index = 0;
bool needs_recreation = true;
};
} // namespace Vulkan
| 2,767
|
C++
|
.h
| 88
| 26.488636
| 84
| 0.698982
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,922
|
vk_pipeline_cache.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_pipeline_cache.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <tsl/robin_map.h>
#include "shader_recompiler/profile.h"
#include "shader_recompiler/recompiler.h"
#include "shader_recompiler/specialization.h"
#include "video_core/renderer_vulkan/vk_compute_pipeline.h"
#include "video_core/renderer_vulkan/vk_graphics_pipeline.h"
#include "video_core/renderer_vulkan/vk_resource_pool.h"
namespace Shader {
struct Info;
}
namespace Vulkan {
class Instance;
class Scheduler;
class ShaderCache;
struct Program {
struct Module {
vk::ShaderModule module;
Shader::StageSpecialization spec;
};
Shader::Info info;
boost::container::small_vector<Module, 8> modules;
explicit Program(Shader::Stage stage, Shader::ShaderParams params) : info{stage, params} {}
void AddPermut(vk::ShaderModule module, const Shader::StageSpecialization&& spec) {
modules.emplace_back(module, std::move(spec));
}
};
class PipelineCache {
static constexpr size_t MaxShaderStages = 5;
public:
explicit PipelineCache(const Instance& instance, Scheduler& scheduler,
AmdGpu::Liverpool* liverpool);
~PipelineCache();
const GraphicsPipeline* GetGraphicsPipeline();
const ComputePipeline* GetComputePipeline();
std::tuple<const Shader::Info*, vk::ShaderModule, u64> GetProgram(
Shader::Stage stage, Shader::ShaderParams params, Shader::Backend::Bindings& binding);
private:
bool RefreshGraphicsKey();
bool RefreshComputeKey();
void DumpShader(std::span<const u32> code, u64 hash, Shader::Stage stage, size_t perm_idx,
std::string_view ext);
vk::ShaderModule CompileModule(Shader::Info& info, const Shader::RuntimeInfo& runtime_info,
std::span<const u32> code, size_t perm_idx,
Shader::Backend::Bindings& binding);
Shader::RuntimeInfo BuildRuntimeInfo(Shader::Stage stage);
private:
const Instance& instance;
Scheduler& scheduler;
AmdGpu::Liverpool* liverpool;
DescriptorHeap desc_heap;
vk::UniquePipelineCache pipeline_cache;
vk::UniquePipelineLayout pipeline_layout;
Shader::Profile profile{};
Shader::Pools pools;
tsl::robin_map<size_t, Program*> program_cache;
Common::ObjectPool<Program> program_pool;
Common::ObjectPool<GraphicsPipeline> graphics_pipeline_pool;
Common::ObjectPool<ComputePipeline> compute_pipeline_pool;
tsl::robin_map<size_t, ComputePipeline*> compute_pipelines;
tsl::robin_map<GraphicsPipelineKey, GraphicsPipeline*> graphics_pipelines;
std::array<const Shader::Info*, MaxShaderStages> infos{};
std::array<vk::ShaderModule, MaxShaderStages> modules{};
GraphicsPipelineKey graphics_key{};
u64 compute_key{};
};
} // namespace Vulkan
| 2,898
|
C++
|
.h
| 69
| 36.492754
| 95
| 0.725009
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,923
|
vk_pipeline_common.h
|
shadps4-emu_shadPS4/src/video_core/renderer_vulkan/vk_pipeline_common.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/backend/bindings.h"
#include "shader_recompiler/info.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace VideoCore {
class BufferCache;
class TextureCache;
} // namespace VideoCore
namespace Vulkan {
class Instance;
class Scheduler;
class DescriptorHeap;
class Pipeline {
public:
Pipeline(const Instance& instance, Scheduler& scheduler, DescriptorHeap& desc_heap,
vk::PipelineCache pipeline_cache);
virtual ~Pipeline();
vk::Pipeline Handle() const noexcept {
return *pipeline;
}
vk::PipelineLayout GetLayout() const noexcept {
return *pipeline_layout;
}
using DescriptorWrites = boost::container::small_vector<vk::WriteDescriptorSet, 16>;
using BufferBarriers = boost::container::small_vector<vk::BufferMemoryBarrier2, 16>;
void BindBuffers(VideoCore::BufferCache& buffer_cache, VideoCore::TextureCache& texture_cache,
const Shader::Info& stage, Shader::Backend::Bindings& binding,
Shader::PushData& push_data, DescriptorWrites& set_writes,
BufferBarriers& buffer_barriers) const;
void BindTextures(VideoCore::TextureCache& texture_cache, const Shader::Info& stage,
Shader::Backend::Bindings& binding, DescriptorWrites& set_writes) const;
protected:
const Instance& instance;
Scheduler& scheduler;
DescriptorHeap& desc_heap;
vk::UniquePipeline pipeline;
vk::UniquePipelineLayout pipeline_layout;
vk::UniqueDescriptorSetLayout desc_layout;
static boost::container::static_vector<vk::DescriptorImageInfo, 32> image_infos;
static boost::container::static_vector<vk::BufferView, 8> buffer_views;
static boost::container::static_vector<vk::DescriptorBufferInfo, 32> buffer_infos;
};
} // namespace Vulkan
| 1,967
|
C++
|
.h
| 45
| 38.2
| 98
| 0.737035
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,924
|
tile_manager.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/tile_manager.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
#include "video_core/buffer_cache/buffer.h"
#include "video_core/texture_cache/image.h"
namespace VideoCore {
class TextureCache;
/// Converts tiled texture data to linear format.
void ConvertTileToLinear(u8* dst, const u8* src, u32 width, u32 height, bool neo);
/// Converts image format to the one used internally by detiler.
vk::Format DemoteImageFormatForDetiling(vk::Format format);
enum DetilerType : u32 {
Micro8x1,
Micro8x2,
Micro32x1,
Micro32x2,
Micro32x4,
Max
};
struct DetilerContext {
vk::UniquePipeline pl;
vk::UniquePipelineLayout pl_layout;
};
class TileManager {
public:
using ScratchBuffer = std::pair<vk::Buffer, VmaAllocation>;
TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler);
~TileManager();
std::pair<vk::Buffer, u32> TryDetile(vk::Buffer in_buffer, u32 in_offset, Image& image);
ScratchBuffer AllocBuffer(u32 size, bool is_storage = false);
void Upload(ScratchBuffer buffer, const void* data, size_t size);
void FreeBuffer(ScratchBuffer buffer);
private:
const DetilerContext* GetDetiler(const Image& image) const;
private:
const Vulkan::Instance& instance;
Vulkan::Scheduler& scheduler;
vk::UniqueDescriptorSetLayout desc_layout;
std::array<DetilerContext, DetilerType::Max> detilers;
};
} // namespace VideoCore
| 1,511
|
C++
|
.h
| 42
| 32.690476
| 92
| 0.759807
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,925
|
image_view.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/image_view.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/info.h"
#include "video_core/amdgpu/liverpool.h"
#include "video_core/amdgpu/resource.h"
#include "video_core/renderer_vulkan/vk_common.h"
#include "video_core/texture_cache/types.h"
namespace Vulkan {
class Instance;
class Scheduler;
} // namespace Vulkan
namespace VideoCore {
struct ImageViewInfo {
ImageViewInfo() = default;
ImageViewInfo(const AmdGpu::Image& image, const Shader::ImageResource& desc) noexcept;
ImageViewInfo(const AmdGpu::Liverpool::ColorBuffer& col_buffer, bool is_vo_surface) noexcept;
ImageViewInfo(const AmdGpu::Liverpool::DepthBuffer& depth_buffer,
AmdGpu::Liverpool::DepthView view, AmdGpu::Liverpool::DepthControl ctl);
vk::ImageViewType type = vk::ImageViewType::e2D;
vk::Format format = vk::Format::eR8G8B8A8Unorm;
SubresourceRange range;
vk::ComponentMapping mapping{};
bool is_storage = false;
auto operator<=>(const ImageViewInfo&) const = default;
};
struct Image;
constexpr Common::SlotId NULL_IMAGE_VIEW_ID{0};
struct ImageView {
ImageView(const Vulkan::Instance& instance, const ImageViewInfo& info, Image& image,
ImageId image_id);
~ImageView();
ImageView(const ImageView&) = delete;
ImageView& operator=(const ImageView&) = delete;
ImageView(ImageView&&) = default;
ImageView& operator=(ImageView&&) = default;
ImageId image_id{};
Extent3D size{0, 0, 0};
ImageViewInfo info{};
vk::UniqueImageView image_view;
};
} // namespace VideoCore
| 1,656
|
C++
|
.h
| 42
| 35.428571
| 97
| 0.739375
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,926
|
texture_cache.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/texture_cache.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <boost/container/small_vector.hpp>
#include <tsl/robin_map.h>
#include "common/slot_vector.h"
#include "video_core/amdgpu/resource.h"
#include "video_core/multi_level_page_table.h"
#include "video_core/texture_cache/image.h"
#include "video_core/texture_cache/image_view.h"
#include "video_core/texture_cache/sampler.h"
#include "video_core/texture_cache/tile_manager.h"
namespace Core::Libraries::VideoOut {
struct BufferAttributeGroup;
}
namespace VideoCore {
class BufferCache;
class PageManager;
enum class FindFlags {
NoCreate = 1 << 0, ///< Do not create an image if searching for one fails.
RelaxDim = 1 << 1, ///< Do not check the dimentions of image, only address.
RelaxSize = 1 << 2, ///< Do not check that the size matches exactly.
RelaxFmt = 1 << 3, ///< Do not check that format is compatible.
};
DECLARE_ENUM_FLAG_OPERATORS(FindFlags)
static constexpr u32 MaxInvalidateDist = 12_MB;
class TextureCache {
struct Traits {
using Entry = boost::container::small_vector<ImageId, 16>;
static constexpr size_t AddressSpaceBits = 39;
static constexpr size_t FirstLevelBits = 9;
static constexpr size_t PageBits = 20;
};
using PageTable = MultiLevelPageTable<Traits>;
public:
explicit TextureCache(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler,
BufferCache& buffer_cache, PageManager& tracker);
~TextureCache();
/// Invalidates any image in the logical page range.
void InvalidateMemory(VAddr address, size_t size);
/// Marks an image as dirty if it exists at the provided address.
void InvalidateMemoryFromGPU(VAddr address, size_t max_size);
/// Evicts any images that overlap the unmapped range.
void UnmapMemory(VAddr cpu_addr, size_t size);
/// Retrieves the image handle of the image with the provided attributes.
[[nodiscard]] ImageId FindImage(const ImageInfo& info, FindFlags flags = {});
/// Retrieves an image view with the properties of the specified image id.
[[nodiscard]] ImageView& FindTexture(ImageId image_id, const ImageViewInfo& view_info);
/// Retrieves the render target with specified properties
[[nodiscard]] ImageView& FindRenderTarget(const ImageInfo& image_info,
const ImageViewInfo& view_info);
/// Retrieves the depth target with specified properties
[[nodiscard]] ImageView& FindDepthTarget(const ImageInfo& image_info,
const ImageViewInfo& view_info);
/// Updates image contents if it was modified by CPU.
void UpdateImage(ImageId image_id, Vulkan::Scheduler* custom_scheduler = nullptr) {
Image& image = slot_images[image_id];
TrackImage(image_id);
RefreshImage(image, custom_scheduler);
}
[[nodiscard]] ImageId ResolveOverlap(const ImageInfo& info, ImageId cache_img_id,
ImageId merged_image_id);
/// Resolves depth overlap and either re-creates the image or returns existing one
[[nodiscard]] ImageId ResolveDepthOverlap(const ImageInfo& requested_info,
ImageId cache_img_id);
[[nodiscard]] ImageId ExpandImage(const ImageInfo& info, ImageId image_id);
/// Reuploads image contents.
void RefreshImage(Image& image, Vulkan::Scheduler* custom_scheduler = nullptr);
/// Retrieves the sampler that matches the provided S# descriptor.
[[nodiscard]] vk::Sampler GetSampler(const AmdGpu::Sampler& sampler);
/// Retrieves the image with the specified id.
[[nodiscard]] Image& GetImage(ImageId id) {
return slot_images[id];
}
/// Retrieves the image view with the specified id.
[[nodiscard]] ImageView& GetImageView(ImageId id) {
return slot_image_views[id];
}
bool IsMeta(VAddr address) const {
return surface_metas.contains(address);
}
bool IsMetaCleared(VAddr address) const {
const auto& it = surface_metas.find(address);
if (it != surface_metas.end()) {
return it.value().is_cleared;
}
return false;
}
bool TouchMeta(VAddr address, bool is_clear) {
auto it = surface_metas.find(address);
if (it != surface_metas.end()) {
it.value().is_cleared = is_clear;
return true;
}
return false;
}
template <typename Func>
void ForEachImageInRegion(VAddr cpu_addr, size_t size, Func&& func) {
using FuncReturn = typename std::invoke_result<Func, ImageId, Image&>::type;
static constexpr bool BOOL_BREAK = std::is_same_v<FuncReturn, bool>;
boost::container::small_vector<ImageId, 32> images;
ForEachPage(cpu_addr, size, [this, &images, cpu_addr, size, func](u64 page) {
const auto it = page_table.find(page);
if (it == nullptr) {
if constexpr (BOOL_BREAK) {
return false;
} else {
return;
}
}
for (const ImageId image_id : *it) {
Image& image = slot_images[image_id];
if (image.flags & ImageFlagBits::Picked) {
continue;
}
if (!image.Overlaps(cpu_addr, size)) {
continue;
}
image.flags |= ImageFlagBits::Picked;
images.push_back(image_id);
if constexpr (BOOL_BREAK) {
if (func(image_id, image)) {
return true;
}
} else {
func(image_id, image);
}
}
if constexpr (BOOL_BREAK) {
return false;
}
});
for (const ImageId image_id : images) {
slot_images[image_id].flags &= ~ImageFlagBits::Picked;
}
}
private:
/// Iterate over all page indices in a range
template <typename Func>
static void ForEachPage(PAddr addr, size_t size, Func&& func) {
static constexpr bool RETURNS_BOOL = std::is_same_v<std::invoke_result<Func, u64>, bool>;
const u64 page_end = (addr + size - 1) >> Traits::PageBits;
for (u64 page = addr >> Traits::PageBits; page <= page_end; ++page) {
if constexpr (RETURNS_BOOL) {
if (func(page)) {
break;
}
} else {
func(page);
}
}
}
/// Registers an image view for provided image
ImageView& RegisterImageView(ImageId image_id, const ImageViewInfo& view_info);
/// Create an image from the given parameters
[[nodiscard]] ImageId InsertImage(const ImageInfo& info, VAddr cpu_addr);
/// Register image in the page table
void RegisterImage(ImageId image);
/// Unregister image from the page table
void UnregisterImage(ImageId image);
/// Track CPU reads and writes for image
void TrackImage(ImageId image_id);
/// Stop tracking CPU reads and writes for image
void UntrackImage(ImageId image_id);
/// Removes the image and any views/surface metas that reference it.
void DeleteImage(ImageId image_id);
void FreeImage(ImageId image_id) {
UntrackImage(image_id);
UnregisterImage(image_id);
DeleteImage(image_id);
}
private:
const Vulkan::Instance& instance;
Vulkan::Scheduler& scheduler;
BufferCache& buffer_cache;
PageManager& tracker;
TileManager tile_manager;
Common::SlotVector<Image> slot_images;
Common::SlotVector<ImageView> slot_image_views;
tsl::robin_map<u64, Sampler> samplers;
PageTable page_table;
std::mutex mutex;
struct MetaDataInfo {
enum class Type {
CMask,
FMask,
HTile,
};
Type type;
bool is_cleared;
};
tsl::robin_map<VAddr, MetaDataInfo> surface_metas;
};
} // namespace VideoCore
| 8,202
|
C++
|
.h
| 194
| 33.438144
| 97
| 0.629472
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,927
|
image_info.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/image_info.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
#include "core/libraries/videoout/buffer.h"
#include "shader_recompiler/info.h"
#include "video_core/amdgpu/liverpool.h"
#include "video_core/texture_cache/types.h"
#include <boost/container/small_vector.hpp>
namespace VideoCore {
struct ImageInfo {
ImageInfo() = default;
ImageInfo(const Libraries::VideoOut::BufferAttributeGroup& group, VAddr cpu_address) noexcept;
ImageInfo(const AmdGpu::Liverpool::ColorBuffer& buffer,
const AmdGpu::Liverpool::CbDbExtent& hint = {}) noexcept;
ImageInfo(const AmdGpu::Liverpool::DepthBuffer& buffer, u32 num_slices, VAddr htile_address,
const AmdGpu::Liverpool::CbDbExtent& hint = {}) noexcept;
ImageInfo(const AmdGpu::Image& image, const Shader::ImageResource& desc) noexcept;
bool IsTiled() const {
return tiling_mode != AmdGpu::TilingMode::Display_Linear;
}
bool IsBlockCoded() const;
bool IsPacked() const;
bool IsDepthStencil() const;
bool IsMipOf(const ImageInfo& info) const;
bool IsSliceOf(const ImageInfo& info) const;
/// Verifies if images are compatible for subresource merging.
bool IsCompatible(const ImageInfo& info) const {
return (pixel_format == info.pixel_format && tiling_idx == info.tiling_idx &&
num_samples == info.num_samples && num_bits == info.num_bits);
}
void UpdateSize();
struct {
VAddr cmask_addr;
VAddr fmask_addr;
VAddr htile_addr;
} meta_info{};
struct {
u32 texture : 1;
u32 storage : 1;
u32 render_target : 1;
u32 depth_target : 1;
u32 stencil : 1;
u32 vo_buffer : 1;
} usage{}; // Usage data tracked during image lifetime
struct {
u32 is_cube : 1;
u32 is_volume : 1;
u32 is_tiled : 1;
u32 is_pow2 : 1;
u32 is_block : 1;
} props{}; // Surface properties with impact on various calculation factors
vk::Format pixel_format = vk::Format::eUndefined;
vk::ImageType type = vk::ImageType::e1D;
SubresourceExtent resources;
Extent3D size{1, 1, 1};
u32 num_bits{};
u32 num_samples = 1;
u32 pitch = 0;
AmdGpu::TilingMode tiling_mode{AmdGpu::TilingMode::Display_Linear};
struct MipInfo {
u32 size;
u32 pitch;
u32 height;
u32 offset;
};
boost::container::small_vector<MipInfo, 14> mips_layout;
VAddr guest_address{0};
u32 guest_size_bytes{0};
u32 tiling_idx{0}; // TODO: merge with existing!
};
} // namespace VideoCore
| 2,696
|
C++
|
.h
| 72
| 31.416667
| 98
| 0.667433
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,928
|
host_compatibility.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/host_compatibility.h
|
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright © 2023 Skyline Team and Contributors (https://github.com/skyline-emu/)
// Copyright © 2015-2023 The Khronos Group Inc.
// Copyright © 2015-2023 Valve Corporation
// Copyright © 2015-2023 LunarG, Inc.
#pragma once
#include <unordered_map>
#include "video_core/renderer_vulkan/vk_common.h"
namespace VideoCore {
/**
* @brief All classes of format compatibility according to the Vulkan specification
* @url
* https://github.com/KhronosGroup/Vulkan-ValidationLayers/blob/d37c676f75f545a3e5a98d7dfb89864391a1db1e/layers/generated/vk_format_utils.h#L47-L131
* @note This is copied directly from Vulkan Validation Layers and doesn't follow the Skyline naming
* conventions
*/
enum class FORMAT_COMPATIBILITY_CLASS {
NONE = 0,
_10BIT_2PLANE_420,
_10BIT_2PLANE_422,
_10BIT_2PLANE_444,
_10BIT_3PLANE_420,
_10BIT_3PLANE_422,
_10BIT_3PLANE_444,
_12BIT_2PLANE_420,
_12BIT_2PLANE_422,
_12BIT_2PLANE_444,
_12BIT_3PLANE_420,
_12BIT_3PLANE_422,
_12BIT_3PLANE_444,
_128BIT,
_16BIT,
_16BIT_2PLANE_420,
_16BIT_2PLANE_422,
_16BIT_2PLANE_444,
_16BIT_3PLANE_420,
_16BIT_3PLANE_422,
_16BIT_3PLANE_444,
_192BIT,
_24BIT,
_256BIT,
_32BIT,
_32BIT_B8G8R8G8,
_32BIT_G8B8G8R8,
_48BIT,
_64BIT,
_64BIT_B10G10R10G10,
_64BIT_B12G12R12G12,
_64BIT_B16G16R16G16,
_64BIT_G10B10G10R10,
_64BIT_G12B12G12R12,
_64BIT_G16B16G16R16,
_64BIT_R10G10B10A10,
_64BIT_R12G12B12A12,
_8BIT,
_8BIT_2PLANE_420,
_8BIT_2PLANE_422,
_8BIT_2PLANE_444,
_8BIT_3PLANE_420,
_8BIT_3PLANE_422,
_8BIT_3PLANE_444,
_96BIT,
ASTC_10X10,
ASTC_10X5,
ASTC_10X6,
ASTC_10X8,
ASTC_12X10,
ASTC_12X12,
ASTC_4X4,
ASTC_5X4,
ASTC_5X5,
ASTC_6X5,
ASTC_6X6,
ASTC_8X5,
ASTC_8X6,
ASTC_8X8,
BC1_RGB,
BC1_RGBA,
BC2,
BC3,
BC4,
BC5,
BC6H,
BC7,
D16,
D16S8,
D24,
D24S8,
D32,
D32S8,
EAC_R,
EAC_RG,
ETC2_EAC_RGBA,
ETC2_RGB,
ETC2_RGBA,
PVRTC1_2BPP,
PVRTC1_4BPP,
PVRTC2_2BPP,
PVRTC2_4BPP,
S8
};
/**
* @brief The format compatibility class according to the Vulkan specification
* @url
* https://registry.khronos.org/vulkan/specs/1.3-extensions/html/vkspec.html#formats-compatibility-classes
* @url
* https://github.com/KhronosGroup/Vulkan-ValidationLayers/blob/d37c676f75f545a3e5a98d7dfb89864391a1db1e/layers/generated/vk_format_utils.cpp#L70-L812
* @note This is copied directly from Vulkan Validation Layers and doesn't follow the Skyline naming
* conventions
*/
static const std::unordered_map<VkFormat, FORMAT_COMPATIBILITY_CLASS> vkFormatClassTable{
{VK_FORMAT_A1R5G5B5_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_A2B10G10R10_SINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2B10G10R10_SNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2B10G10R10_SSCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2B10G10R10_UINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2B10G10R10_UNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2B10G10R10_USCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_SINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_SNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_SSCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_UINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_UNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A2R10G10B10_USCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A4B4G4R4_UNORM_PACK16_EXT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_A4R4G4B4_UNORM_PACK16_EXT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_A8B8G8R8_SINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_SNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_SRGB_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_SSCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_UINT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_UNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_A8B8G8R8_USCALED_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_ASTC_10x10_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_10X10},
{VK_FORMAT_ASTC_10x10_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X10},
{VK_FORMAT_ASTC_10x10_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X10},
{VK_FORMAT_ASTC_10x5_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_10X5},
{VK_FORMAT_ASTC_10x5_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X5},
{VK_FORMAT_ASTC_10x5_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X5},
{VK_FORMAT_ASTC_10x6_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_10X6},
{VK_FORMAT_ASTC_10x6_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X6},
{VK_FORMAT_ASTC_10x6_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X6},
{VK_FORMAT_ASTC_10x8_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_10X8},
{VK_FORMAT_ASTC_10x8_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X8},
{VK_FORMAT_ASTC_10x8_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_10X8},
{VK_FORMAT_ASTC_12x10_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_12X10},
{VK_FORMAT_ASTC_12x10_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_12X10},
{VK_FORMAT_ASTC_12x10_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_12X10},
{VK_FORMAT_ASTC_12x12_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_12X12},
{VK_FORMAT_ASTC_12x12_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_12X12},
{VK_FORMAT_ASTC_12x12_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_12X12},
{VK_FORMAT_ASTC_4x4_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_4X4},
{VK_FORMAT_ASTC_4x4_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_4X4},
{VK_FORMAT_ASTC_4x4_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_4X4},
{VK_FORMAT_ASTC_5x4_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_5X4},
{VK_FORMAT_ASTC_5x4_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_5X4},
{VK_FORMAT_ASTC_5x4_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_5X4},
{VK_FORMAT_ASTC_5x5_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_5X5},
{VK_FORMAT_ASTC_5x5_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_5X5},
{VK_FORMAT_ASTC_5x5_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_5X5},
{VK_FORMAT_ASTC_6x5_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_6X5},
{VK_FORMAT_ASTC_6x5_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_6X5},
{VK_FORMAT_ASTC_6x5_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_6X5},
{VK_FORMAT_ASTC_6x6_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_6X6},
{VK_FORMAT_ASTC_6x6_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_6X6},
{VK_FORMAT_ASTC_6x6_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_6X6},
{VK_FORMAT_ASTC_8x5_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_8X5},
{VK_FORMAT_ASTC_8x5_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X5},
{VK_FORMAT_ASTC_8x5_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X5},
{VK_FORMAT_ASTC_8x6_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_8X6},
{VK_FORMAT_ASTC_8x6_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X6},
{VK_FORMAT_ASTC_8x6_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X6},
{VK_FORMAT_ASTC_8x8_SFLOAT_BLOCK_EXT, FORMAT_COMPATIBILITY_CLASS::ASTC_8X8},
{VK_FORMAT_ASTC_8x8_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X8},
{VK_FORMAT_ASTC_8x8_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ASTC_8X8},
{VK_FORMAT_B10G11R11_UFLOAT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16,
FORMAT_COMPATIBILITY_CLASS::_64BIT_B10G10R10G10},
{VK_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16,
FORMAT_COMPATIBILITY_CLASS::_64BIT_B12G12R12G12},
{VK_FORMAT_B16G16R16G16_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_64BIT_B16G16R16G16},
{VK_FORMAT_B4G4R4A4_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_B5G5R5A1_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_B5G6R5_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_B8G8R8A8_SINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_SNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_SRGB, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_UINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_UNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8A8_USCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_B8G8R8G8_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT_B8G8R8G8},
{VK_FORMAT_B8G8R8_SINT, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_SNORM, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_SRGB, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_UINT, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_UNORM, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_B8G8R8_USCALED, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_BC1_RGBA_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC1_RGBA},
{VK_FORMAT_BC1_RGBA_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC1_RGBA},
{VK_FORMAT_BC1_RGB_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC1_RGB},
{VK_FORMAT_BC1_RGB_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC1_RGB},
{VK_FORMAT_BC2_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC2},
{VK_FORMAT_BC2_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC2},
{VK_FORMAT_BC3_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC3},
{VK_FORMAT_BC3_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC3},
{VK_FORMAT_BC4_SNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC4},
{VK_FORMAT_BC4_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC4},
{VK_FORMAT_BC5_SNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC5},
{VK_FORMAT_BC5_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC5},
{VK_FORMAT_BC6H_SFLOAT_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC6H},
{VK_FORMAT_BC6H_UFLOAT_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC6H},
{VK_FORMAT_BC7_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC7},
{VK_FORMAT_BC7_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::BC7},
{VK_FORMAT_D16_UNORM, FORMAT_COMPATIBILITY_CLASS::D16},
{VK_FORMAT_D16_UNORM_S8_UINT, FORMAT_COMPATIBILITY_CLASS::D16S8},
{VK_FORMAT_D24_UNORM_S8_UINT, FORMAT_COMPATIBILITY_CLASS::D24S8},
{VK_FORMAT_D32_SFLOAT, FORMAT_COMPATIBILITY_CLASS::D32},
{VK_FORMAT_D32_SFLOAT_S8_UINT, FORMAT_COMPATIBILITY_CLASS::D32S8},
{VK_FORMAT_E5B9G9R9_UFLOAT_PACK32, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_EAC_R11G11_SNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::EAC_RG},
{VK_FORMAT_EAC_R11G11_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::EAC_RG},
{VK_FORMAT_EAC_R11_SNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::EAC_R},
{VK_FORMAT_EAC_R11_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::EAC_R},
{VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_RGBA},
{VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_RGBA},
{VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_EAC_RGBA},
{VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_EAC_RGBA},
{VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_RGB},
{VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK, FORMAT_COMPATIBILITY_CLASS::ETC2_RGB},
{VK_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16,
FORMAT_COMPATIBILITY_CLASS::_64BIT_G10B10G10R10},
{VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_10BIT_2PLANE_420},
{VK_FORMAT_G10X6_B10X6R10X6_2PLANE_422_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_10BIT_2PLANE_422},
{VK_FORMAT_G10X6_B10X6R10X6_2PLANE_444_UNORM_3PACK16_EXT,
FORMAT_COMPATIBILITY_CLASS::_10BIT_2PLANE_444},
{VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_420_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_10BIT_3PLANE_420},
{VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_422_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_10BIT_3PLANE_422},
{VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_444_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_10BIT_3PLANE_444},
{VK_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16,
FORMAT_COMPATIBILITY_CLASS::_64BIT_G12B12G12R12},
{VK_FORMAT_G12X4_B12X4R12X4_2PLANE_420_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_12BIT_2PLANE_420},
{VK_FORMAT_G12X4_B12X4R12X4_2PLANE_422_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_12BIT_2PLANE_422},
{VK_FORMAT_G12X4_B12X4R12X4_2PLANE_444_UNORM_3PACK16_EXT,
FORMAT_COMPATIBILITY_CLASS::_12BIT_2PLANE_444},
{VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_420_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_12BIT_3PLANE_420},
{VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_422_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_12BIT_3PLANE_422},
{VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_444_UNORM_3PACK16,
FORMAT_COMPATIBILITY_CLASS::_12BIT_3PLANE_444},
{VK_FORMAT_G16B16G16R16_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_64BIT_G16B16G16R16},
{VK_FORMAT_G16_B16R16_2PLANE_420_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT_2PLANE_420},
{VK_FORMAT_G16_B16R16_2PLANE_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT_2PLANE_422},
{VK_FORMAT_G16_B16R16_2PLANE_444_UNORM_EXT, FORMAT_COMPATIBILITY_CLASS::_16BIT_2PLANE_444},
{VK_FORMAT_G16_B16_R16_3PLANE_420_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT_3PLANE_420},
{VK_FORMAT_G16_B16_R16_3PLANE_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT_3PLANE_422},
{VK_FORMAT_G16_B16_R16_3PLANE_444_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT_3PLANE_444},
{VK_FORMAT_G8B8G8R8_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT_G8B8G8R8},
{VK_FORMAT_G8_B8R8_2PLANE_420_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT_2PLANE_420},
{VK_FORMAT_G8_B8R8_2PLANE_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT_2PLANE_422},
{VK_FORMAT_G8_B8R8_2PLANE_444_UNORM_EXT, FORMAT_COMPATIBILITY_CLASS::_8BIT_2PLANE_444},
{VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT_3PLANE_420},
{VK_FORMAT_G8_B8_R8_3PLANE_422_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT_3PLANE_422},
{VK_FORMAT_G8_B8_R8_3PLANE_444_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT_3PLANE_444},
{VK_FORMAT_PVRTC1_2BPP_SRGB_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC1_2BPP},
{VK_FORMAT_PVRTC1_2BPP_UNORM_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC1_2BPP},
{VK_FORMAT_PVRTC1_4BPP_SRGB_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC1_4BPP},
{VK_FORMAT_PVRTC1_4BPP_UNORM_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC1_4BPP},
{VK_FORMAT_PVRTC2_2BPP_SRGB_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC2_2BPP},
{VK_FORMAT_PVRTC2_2BPP_UNORM_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC2_2BPP},
{VK_FORMAT_PVRTC2_4BPP_SRGB_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC2_4BPP},
{VK_FORMAT_PVRTC2_4BPP_UNORM_BLOCK_IMG, FORMAT_COMPATIBILITY_CLASS::PVRTC2_4BPP},
{VK_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16, FORMAT_COMPATIBILITY_CLASS::_64BIT_R10G10B10A10},
{VK_FORMAT_R10X6G10X6_UNORM_2PACK16, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R10X6_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16, FORMAT_COMPATIBILITY_CLASS::_64BIT_R12G12B12A12},
{VK_FORMAT_R12X4G12X4_UNORM_2PACK16, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R12X4_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16G16B16A16_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_SINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_SNORM, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_SSCALED, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_UINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_UNORM, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16A16_USCALED, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R16G16B16_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_SINT, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_SNORM, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_SSCALED, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_UINT, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_UNORM, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16B16_USCALED, FORMAT_COMPATIBILITY_CLASS::_48BIT},
{VK_FORMAT_R16G16_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_SINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_SNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_SSCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_UINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_UNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16G16_USCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R16_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_SINT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_SNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_SSCALED, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_UINT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R16_USCALED, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R32G32B32A32_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R32G32B32A32_SINT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R32G32B32A32_UINT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R32G32B32_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_96BIT},
{VK_FORMAT_R32G32B32_SINT, FORMAT_COMPATIBILITY_CLASS::_96BIT},
{VK_FORMAT_R32G32B32_UINT, FORMAT_COMPATIBILITY_CLASS::_96BIT},
{VK_FORMAT_R32G32_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R32G32_SINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R32G32_UINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R32_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R32_SINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R32_UINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R4G4B4A4_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R4G4_UNORM_PACK8, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R5G5B5A1_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R5G6B5_UNORM_PACK16, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R64G64B64A64_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_256BIT},
{VK_FORMAT_R64G64B64A64_SINT, FORMAT_COMPATIBILITY_CLASS::_256BIT},
{VK_FORMAT_R64G64B64A64_UINT, FORMAT_COMPATIBILITY_CLASS::_256BIT},
{VK_FORMAT_R64G64B64_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_192BIT},
{VK_FORMAT_R64G64B64_SINT, FORMAT_COMPATIBILITY_CLASS::_192BIT},
{VK_FORMAT_R64G64B64_UINT, FORMAT_COMPATIBILITY_CLASS::_192BIT},
{VK_FORMAT_R64G64_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R64G64_SINT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R64G64_UINT, FORMAT_COMPATIBILITY_CLASS::_128BIT},
{VK_FORMAT_R64_SFLOAT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R64_SINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R64_UINT, FORMAT_COMPATIBILITY_CLASS::_64BIT},
{VK_FORMAT_R8G8B8A8_SINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_SNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_SRGB, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_UINT, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_UNORM, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8A8_USCALED, FORMAT_COMPATIBILITY_CLASS::_32BIT},
{VK_FORMAT_R8G8B8_SINT, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_SNORM, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_SRGB, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_UINT, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_UNORM, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8B8_USCALED, FORMAT_COMPATIBILITY_CLASS::_24BIT},
{VK_FORMAT_R8G8_SINT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_SNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_SRGB, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_UINT, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_UNORM, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8G8_USCALED, FORMAT_COMPATIBILITY_CLASS::_16BIT},
{VK_FORMAT_R8_SINT, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_SNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_SRGB, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_SSCALED, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_UINT, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_UNORM, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_R8_USCALED, FORMAT_COMPATIBILITY_CLASS::_8BIT},
{VK_FORMAT_S8_UINT, FORMAT_COMPATIBILITY_CLASS::S8},
{VK_FORMAT_X8_D24_UNORM_PACK32, FORMAT_COMPATIBILITY_CLASS::D24},
{VK_FORMAT_UNDEFINED, FORMAT_COMPATIBILITY_CLASS::NONE},
};
/**
* @return If the two formats are compatible according to Vulkan's format compatibility rules
* @url
* https://registry.khronos.org/vulkan/specs/1.3-extensions/html/vkspec.html#formats-compatibility
*/
static bool IsVulkanFormatCompatible(vk::Format lhs, vk::Format rhs) {
if (lhs == rhs) {
return true;
}
return vkFormatClassTable.at(VkFormat(lhs)) == vkFormatClassTable.at(VkFormat(rhs));
}
} // namespace VideoCore
| 21,975
|
C++
|
.h
| 387
| 52.043928
| 150
| 0.743176
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,929
|
sampler.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/sampler.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "video_core/amdgpu/resource.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
class Instance;
}
namespace VideoCore {
class Sampler {
public:
explicit Sampler(const Vulkan::Instance& instance, const AmdGpu::Sampler& sampler);
~Sampler();
Sampler(const Sampler&) = delete;
Sampler& operator=(const Sampler&) = delete;
Sampler(Sampler&&) = default;
Sampler& operator=(Sampler&&) = default;
vk::Sampler Handle() const noexcept {
return *handle;
}
private:
vk::UniqueSampler handle;
};
} // namespace VideoCore
| 717
|
C++
|
.h
| 24
| 26.625
| 87
| 0.733529
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,930
|
image.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/image.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/enum.h"
#include "common/types.h"
#include "video_core/renderer_vulkan/vk_common.h"
#include "video_core/texture_cache/image_info.h"
#include "video_core/texture_cache/image_view.h"
#include <optional>
namespace Vulkan {
class Instance;
class Scheduler;
} // namespace Vulkan
VK_DEFINE_HANDLE(VmaAllocation)
VK_DEFINE_HANDLE(VmaAllocator)
namespace VideoCore {
enum ImageFlagBits : u32 {
CpuDirty = 1 << 1, ///< Contents have been modified from the CPU
GpuDirty = 1 << 2, ///< Contents have been modified from the GPU (valid data in buffer cache)
Dirty = CpuDirty | GpuDirty,
GpuModified = 1 << 3, ///< Contents have been modified from the GPU
Tracked = 1 << 4, ///< Writes and reads are being hooked from the CPU
Registered = 1 << 6, ///< True when the image is registered
Picked = 1 << 7, ///< Temporary flag to mark the image as picked
MetaRegistered = 1 << 8, ///< True when metadata for this surface is known and registered
Bound = 1 << 9, ///< True when the image is bound to a descriptor set
NeedsRebind = 1 << 10, ///< True when the image needs to be rebound
};
DECLARE_ENUM_FLAG_OPERATORS(ImageFlagBits)
struct UniqueImage {
explicit UniqueImage(vk::Device device, VmaAllocator allocator);
~UniqueImage();
UniqueImage(const UniqueImage&) = delete;
UniqueImage& operator=(const UniqueImage&) = delete;
UniqueImage(UniqueImage&& other)
: allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)},
image{std::exchange(other.image, VK_NULL_HANDLE)} {}
UniqueImage& operator=(UniqueImage&& other) {
image = std::exchange(other.image, VK_NULL_HANDLE);
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
allocation = std::exchange(other.allocation, VK_NULL_HANDLE);
return *this;
}
void Create(const vk::ImageCreateInfo& image_ci);
operator vk::Image() const {
return image;
}
private:
vk::Device device;
VmaAllocator allocator;
VmaAllocation allocation;
vk::Image image{};
};
constexpr Common::SlotId NULL_IMAGE_ID{0};
struct Image {
Image(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler, const ImageInfo& info);
~Image();
Image(const Image&) = delete;
Image& operator=(const Image&) = delete;
Image(Image&&) = default;
Image& operator=(Image&&) = default;
[[nodiscard]] bool Overlaps(VAddr overlap_cpu_addr, size_t overlap_size) const noexcept {
const VAddr overlap_end = overlap_cpu_addr + overlap_size;
return cpu_addr < overlap_end && overlap_cpu_addr < cpu_addr_end;
}
ImageViewId FindView(const ImageViewInfo& info) const {
const auto it = std::ranges::find(image_view_infos, info);
if (it == image_view_infos.end()) {
return {};
}
return image_view_ids[std::distance(image_view_infos.begin(), it)];
}
boost::container::small_vector<vk::ImageMemoryBarrier2, 32> GetBarriers(
vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits2> dst_mask,
vk::PipelineStageFlags2 dst_stage, std::optional<SubresourceRange> subres_range);
void Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits2> dst_mask,
std::optional<SubresourceRange> range, vk::CommandBuffer cmdbuf = {});
void Upload(vk::Buffer buffer, u64 offset);
void CopyImage(const Image& image);
void CopyMip(const Image& image, u32 mip);
const Vulkan::Instance* instance;
Vulkan::Scheduler* scheduler;
ImageInfo info;
UniqueImage image;
vk::ImageAspectFlags aspect_mask = vk::ImageAspectFlagBits::eColor;
ImageFlagBits flags = ImageFlagBits::Dirty;
VAddr cpu_addr = 0;
VAddr cpu_addr_end = 0;
std::vector<ImageViewInfo> image_view_infos;
std::vector<ImageViewId> image_view_ids;
// Resource state tracking
vk::ImageUsageFlags usage;
vk::FormatFeatureFlags2 format_features;
struct State {
vk::Flags<vk::PipelineStageFlagBits2> pl_stage = vk::PipelineStageFlagBits2::eAllCommands;
vk::Flags<vk::AccessFlagBits2> access_mask = vk::AccessFlagBits2::eNone;
vk::ImageLayout layout = vk::ImageLayout::eUndefined;
};
State last_state{};
std::vector<State> subresource_states{};
boost::container::small_vector<u64, 14> mip_hashes{};
u64 tick_accessed_last{0};
};
} // namespace VideoCore
| 4,654
|
C++
|
.h
| 105
| 39.12381
| 98
| 0.69326
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,931
|
types.h
|
shadps4-emu_shadPS4/src/video_core/texture_cache/types.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/slot_vector.h"
#include "common/types.h"
namespace VideoCore {
using ImageId = Common::SlotId;
using ImageViewId = Common::SlotId;
struct Offset2D {
s32 x;
s32 y;
};
struct Offset3D {
s32 x;
s32 y;
s32 z;
};
struct Region2D {
Offset2D start;
Offset2D end;
};
struct Extent2D {
u32 width;
u32 height;
};
struct Extent3D {
u32 width;
u32 height;
u32 depth;
auto operator<=>(const Extent3D&) const = default;
bool operator==(const Extent3D& other) const {
return width == other.width && height == other.height && depth == other.depth;
}
};
struct SubresourceLayers {
s32 base_level = 0;
s32 base_layer = 0;
s32 num_layers = 1;
};
struct SubresourceBase {
u32 level = 0;
u32 layer = 0;
auto operator<=>(const SubresourceBase&) const = default;
};
struct SubresourceExtent {
u32 levels = 1;
u32 layers = 1;
auto operator<=>(const SubresourceExtent&) const = default;
};
struct SubresourceRange {
SubresourceBase base;
SubresourceExtent extent;
auto operator<=>(const SubresourceRange&) const = default;
};
struct ImageCopy {
SubresourceLayers src_subresource;
SubresourceLayers dst_subresource;
Offset3D src_offset;
Offset3D dst_offset;
Extent3D extent;
};
struct BufferImageCopy {
std::size_t buffer_offset;
std::size_t buffer_size;
u32 buffer_row_length;
u32 buffer_image_height;
SubresourceLayers image_subresource;
Offset3D image_offset;
Extent3D image_extent;
};
struct BufferCopy {
u64 src_offset;
u64 dst_offset;
std::size_t size;
};
} // namespace VideoCore
| 1,801
|
C++
|
.h
| 76
| 20.092105
| 86
| 0.704052
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,932
|
memory_tracker_base.h
|
shadps4-emu_shadPS4/src/video_core/buffer_cache/memory_tracker_base.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <deque>
#include <type_traits>
#include <vector>
#include "common/types.h"
#include "video_core/buffer_cache/word_manager.h"
namespace VideoCore {
class MemoryTracker {
public:
static constexpr size_t MAX_CPU_PAGE_BITS = 39;
static constexpr size_t HIGHER_PAGE_BITS = 22;
static constexpr size_t HIGHER_PAGE_SIZE = 1ULL << HIGHER_PAGE_BITS;
static constexpr size_t HIGHER_PAGE_MASK = HIGHER_PAGE_SIZE - 1ULL;
static constexpr size_t NUM_HIGH_PAGES = 1ULL << (MAX_CPU_PAGE_BITS - HIGHER_PAGE_BITS);
static constexpr size_t MANAGER_POOL_SIZE = 32;
static constexpr size_t WORDS_STACK_NEEDED = HIGHER_PAGE_SIZE / BYTES_PER_WORD;
using Manager = WordManager<WORDS_STACK_NEEDED>;
public:
explicit MemoryTracker(PageManager* tracker_) : tracker{tracker_} {}
~MemoryTracker() = default;
/// Returns true if a region has been modified from the CPU
[[nodiscard]] bool IsRegionCpuModified(VAddr query_cpu_addr, u64 query_size) noexcept {
return IteratePages<true>(
query_cpu_addr, query_size, [](Manager* manager, u64 offset, size_t size) {
return manager->template IsRegionModified<Type::CPU>(offset, size);
});
}
/// Returns true if a region has been modified from the GPU
[[nodiscard]] bool IsRegionGpuModified(VAddr query_cpu_addr, u64 query_size) noexcept {
return IteratePages<false>(
query_cpu_addr, query_size, [](Manager* manager, u64 offset, size_t size) {
return manager->template IsRegionModified<Type::GPU>(offset, size);
});
}
/// Mark region as CPU modified, notifying the device_tracker about this change
void MarkRegionAsCpuModified(VAddr dirty_cpu_addr, u64 query_size) {
IteratePages<true>(dirty_cpu_addr, query_size,
[](Manager* manager, u64 offset, size_t size) {
manager->template ChangeRegionState<Type::CPU, true>(
manager->GetCpuAddr() + offset, size);
});
}
/// Unmark region as CPU modified, notifying the device_tracker about this change
void UnmarkRegionAsCpuModified(VAddr dirty_cpu_addr, u64 query_size) {
IteratePages<true>(dirty_cpu_addr, query_size,
[](Manager* manager, u64 offset, size_t size) {
manager->template ChangeRegionState<Type::CPU, false>(
manager->GetCpuAddr() + offset, size);
});
}
/// Mark region as modified from the host GPU
void MarkRegionAsGpuModified(VAddr dirty_cpu_addr, u64 query_size) noexcept {
IteratePages<true>(dirty_cpu_addr, query_size,
[](Manager* manager, u64 offset, size_t size) {
manager->template ChangeRegionState<Type::GPU, true>(
manager->GetCpuAddr() + offset, size);
});
}
/// Unmark region as modified from the host GPU
void UnmarkRegionAsGpuModified(VAddr dirty_cpu_addr, u64 query_size) noexcept {
IteratePages<true>(dirty_cpu_addr, query_size,
[](Manager* manager, u64 offset, size_t size) {
manager->template ChangeRegionState<Type::GPU, false>(
manager->GetCpuAddr() + offset, size);
});
}
/// Call 'func' for each CPU modified range and unmark those pages as CPU modified
template <typename Func>
void ForEachUploadRange(VAddr query_cpu_range, u64 query_size, Func&& func) {
IteratePages<true>(query_cpu_range, query_size,
[&func](Manager* manager, u64 offset, size_t size) {
manager->template ForEachModifiedRange<Type::CPU, true>(
manager->GetCpuAddr() + offset, size, func);
});
}
/// Call 'func' for each GPU modified range and unmark those pages as GPU modified
template <bool clear, typename Func>
void ForEachDownloadRange(VAddr query_cpu_range, u64 query_size, Func&& func) {
IteratePages<false>(query_cpu_range, query_size,
[&func](Manager* manager, u64 offset, size_t size) {
if constexpr (clear) {
manager->template ForEachModifiedRange<Type::GPU, true>(
manager->GetCpuAddr() + offset, size, func);
} else {
manager->template ForEachModifiedRange<Type::GPU, false>(
manager->GetCpuAddr() + offset, size, func);
}
});
}
private:
/**
* @brief IteratePages Iterates L2 word manager page table.
* @param cpu_address Start byte cpu address
* @param size Size in bytes of the region of iterate.
* @param func Callback for each word manager.
* @return
*/
template <bool create_region_on_fail, typename Func>
bool IteratePages(VAddr cpu_address, size_t size, Func&& func) {
using FuncReturn = typename std::invoke_result<Func, Manager*, u64, size_t>::type;
static constexpr bool BOOL_BREAK = std::is_same_v<FuncReturn, bool>;
std::size_t remaining_size{size};
std::size_t page_index{cpu_address >> HIGHER_PAGE_BITS};
u64 page_offset{cpu_address & HIGHER_PAGE_MASK};
while (remaining_size > 0) {
const std::size_t copy_amount{
std::min<std::size_t>(HIGHER_PAGE_SIZE - page_offset, remaining_size)};
auto* manager{top_tier[page_index]};
if (manager) {
if constexpr (BOOL_BREAK) {
if (func(manager, page_offset, copy_amount)) {
return true;
}
} else {
func(manager, page_offset, copy_amount);
}
} else if constexpr (create_region_on_fail) {
CreateRegion(page_index);
manager = top_tier[page_index];
if constexpr (BOOL_BREAK) {
if (func(manager, page_offset, copy_amount)) {
return true;
}
} else {
func(manager, page_offset, copy_amount);
}
}
page_index++;
page_offset = 0;
remaining_size -= copy_amount;
}
return false;
}
void CreateRegion(std::size_t page_index) {
const VAddr base_cpu_addr = page_index << HIGHER_PAGE_BITS;
if (free_managers.empty()) {
manager_pool.emplace_back();
auto& last_pool = manager_pool.back();
for (size_t i = 0; i < MANAGER_POOL_SIZE; i++) {
std::construct_at(&last_pool[i], tracker, 0, HIGHER_PAGE_SIZE);
free_managers.push_back(&last_pool[i]);
}
}
// Each manager tracks a 4_MB virtual address space.
auto* new_manager = free_managers.back();
new_manager->SetCpuAddress(base_cpu_addr);
free_managers.pop_back();
top_tier[page_index] = new_manager;
}
PageManager* tracker;
std::deque<std::array<Manager, MANAGER_POOL_SIZE>> manager_pool;
std::vector<Manager*> free_managers;
std::array<Manager*, NUM_HIGH_PAGES> top_tier{};
};
} // namespace VideoCore
| 7,984
|
C++
|
.h
| 158
| 36.43038
| 94
| 0.561088
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,933
|
word_manager.h
|
shadps4-emu_shadPS4/src/video_core/buffer_cache/word_manager.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <span>
#include <utility>
#include "common/div_ceil.h"
#include "common/types.h"
#include "video_core/page_manager.h"
namespace VideoCore {
constexpr u64 PAGES_PER_WORD = 64;
constexpr u64 BYTES_PER_PAGE = 4_KB;
constexpr u64 BYTES_PER_WORD = PAGES_PER_WORD * BYTES_PER_PAGE;
enum class Type {
CPU,
GPU,
Untracked,
};
/// Vector tracking modified pages tightly packed with small vector optimization
template <size_t stack_words = 1>
struct WordsArray {
/// Returns the pointer to the words state
[[nodiscard]] const u64* Pointer(bool is_short) const noexcept {
return is_short ? stack.data() : heap;
}
/// Returns the pointer to the words state
[[nodiscard]] u64* Pointer(bool is_short) noexcept {
return is_short ? stack.data() : heap;
}
std::array<u64, stack_words> stack{}; ///< Small buffers storage
u64* heap; ///< Not-small buffers pointer to the storage
};
template <size_t stack_words = 1>
struct Words {
explicit Words() = default;
explicit Words(u64 size_bytes_) : size_bytes{size_bytes_} {
num_words = Common::DivCeil(size_bytes, BYTES_PER_WORD);
if (IsShort()) {
cpu.stack.fill(~u64{0});
gpu.stack.fill(0);
untracked.stack.fill(~u64{0});
} else {
// Share allocation between CPU and GPU pages and set their default values
u64* const alloc = new u64[num_words * 3];
cpu.heap = alloc;
gpu.heap = alloc + num_words;
untracked.heap = alloc + num_words * 2;
std::fill_n(cpu.heap, num_words, ~u64{0});
std::fill_n(gpu.heap, num_words, 0);
std::fill_n(untracked.heap, num_words, ~u64{0});
}
// Clean up tailing bits
const u64 last_word_size = size_bytes % BYTES_PER_WORD;
const u64 last_local_page = Common::DivCeil(last_word_size, BYTES_PER_PAGE);
const u64 shift = (PAGES_PER_WORD - last_local_page) % PAGES_PER_WORD;
const u64 last_word = (~u64{0} << shift) >> shift;
cpu.Pointer(IsShort())[NumWords() - 1] = last_word;
untracked.Pointer(IsShort())[NumWords() - 1] = last_word;
}
~Words() {
Release();
}
Words& operator=(Words&& rhs) noexcept {
Release();
size_bytes = rhs.size_bytes;
num_words = rhs.num_words;
cpu = rhs.cpu;
gpu = rhs.gpu;
untracked = rhs.untracked;
rhs.cpu.heap = nullptr;
return *this;
}
Words(Words&& rhs) noexcept
: size_bytes{rhs.size_bytes}, num_words{rhs.num_words}, cpu{rhs.cpu}, gpu{rhs.gpu},
untracked{rhs.untracked} {
rhs.cpu.heap = nullptr;
}
Words& operator=(const Words&) = delete;
Words(const Words&) = delete;
/// Returns true when the buffer fits in the small vector optimization
[[nodiscard]] bool IsShort() const noexcept {
return num_words <= stack_words;
}
/// Returns the number of words of the buffer
[[nodiscard]] size_t NumWords() const noexcept {
return num_words;
}
/// Release buffer resources
void Release() {
if (!IsShort()) {
// CPU written words is the base for the heap allocation
delete[] cpu.heap;
}
}
template <Type type>
std::span<u64> Span() noexcept {
if constexpr (type == Type::CPU) {
return std::span<u64>(cpu.Pointer(IsShort()), num_words);
} else if constexpr (type == Type::GPU) {
return std::span<u64>(gpu.Pointer(IsShort()), num_words);
} else if constexpr (type == Type::Untracked) {
return std::span<u64>(untracked.Pointer(IsShort()), num_words);
}
}
template <Type type>
std::span<const u64> Span() const noexcept {
if constexpr (type == Type::CPU) {
return std::span<const u64>(cpu.Pointer(IsShort()), num_words);
} else if constexpr (type == Type::GPU) {
return std::span<const u64>(gpu.Pointer(IsShort()), num_words);
} else if constexpr (type == Type::Untracked) {
return std::span<const u64>(untracked.Pointer(IsShort()), num_words);
}
}
u64 size_bytes = 0;
size_t num_words = 0;
WordsArray<stack_words> cpu;
WordsArray<stack_words> gpu;
WordsArray<stack_words> untracked;
};
template <size_t stack_words = 1>
class WordManager {
public:
explicit WordManager(PageManager* tracker_, VAddr cpu_addr_, u64 size_bytes)
: tracker{tracker_}, cpu_addr{cpu_addr_}, words{size_bytes} {}
explicit WordManager() = default;
void SetCpuAddress(VAddr new_cpu_addr) {
cpu_addr = new_cpu_addr;
}
VAddr GetCpuAddr() const {
return cpu_addr;
}
static u64 ExtractBits(u64 word, size_t page_start, size_t page_end) {
constexpr size_t number_bits = sizeof(u64) * 8;
const size_t limit_page_end = number_bits - std::min(page_end, number_bits);
u64 bits = (word >> page_start) << page_start;
bits = (bits << limit_page_end) >> limit_page_end;
return bits;
}
static std::pair<size_t, size_t> GetWordPage(VAddr address) {
const size_t converted_address = static_cast<size_t>(address);
const size_t word_number = converted_address / BYTES_PER_WORD;
const size_t amount_pages = converted_address % BYTES_PER_WORD;
return std::make_pair(word_number, amount_pages / BYTES_PER_PAGE);
}
template <typename Func>
void IterateWords(size_t offset, size_t size, Func&& func) const {
using FuncReturn = std::invoke_result_t<Func, std::size_t, u64>;
static constexpr bool BOOL_BREAK = std::is_same_v<FuncReturn, bool>;
const size_t start = static_cast<size_t>(std::max<s64>(static_cast<s64>(offset), 0LL));
const size_t end = static_cast<size_t>(std::max<s64>(static_cast<s64>(offset + size), 0LL));
if (start >= SizeBytes() || end <= start) {
return;
}
auto [start_word, start_page] = GetWordPage(start);
auto [end_word, end_page] = GetWordPage(end + BYTES_PER_PAGE - 1ULL);
const size_t num_words = NumWords();
start_word = std::min(start_word, num_words);
end_word = std::min(end_word, num_words);
const size_t diff = end_word - start_word;
end_word += (end_page + PAGES_PER_WORD - 1ULL) / PAGES_PER_WORD;
end_word = std::min(end_word, num_words);
end_page += diff * PAGES_PER_WORD;
constexpr u64 base_mask{~0ULL};
for (size_t word_index = start_word; word_index < end_word; word_index++) {
const u64 mask = ExtractBits(base_mask, start_page, end_page);
start_page = 0;
end_page -= PAGES_PER_WORD;
if constexpr (BOOL_BREAK) {
if (func(word_index, mask)) {
return;
}
} else {
func(word_index, mask);
}
}
}
template <typename Func>
void IteratePages(u64 mask, Func&& func) const {
size_t offset = 0;
while (mask != 0) {
const size_t empty_bits = std::countr_zero(mask);
offset += empty_bits;
mask = mask >> empty_bits;
const size_t continuous_bits = std::countr_one(mask);
func(offset, continuous_bits);
mask = continuous_bits < PAGES_PER_WORD ? (mask >> continuous_bits) : 0;
offset += continuous_bits;
}
}
/**
* Change the state of a range of pages
*
* @param dirty_addr Base address to mark or unmark as modified
* @param size Size in bytes to mark or unmark as modified
*/
template <Type type, bool enable>
void ChangeRegionState(u64 dirty_addr, u64 size) noexcept(type == Type::GPU) {
std::span<u64> state_words = words.template Span<type>();
[[maybe_unused]] std::span<u64> untracked_words = words.template Span<Type::Untracked>();
IterateWords(dirty_addr - cpu_addr, size, [&](size_t index, u64 mask) {
if constexpr (type == Type::CPU) {
NotifyPageTracker<!enable>(index, untracked_words[index], mask);
}
if constexpr (enable) {
state_words[index] |= mask;
if constexpr (type == Type::CPU) {
untracked_words[index] |= mask;
}
} else {
state_words[index] &= ~mask;
if constexpr (type == Type::CPU) {
untracked_words[index] &= ~mask;
}
}
});
}
/**
* Loop over each page in the given range, turn off those bits and notify the tracker if
* needed. Call the given function on each turned off range.
*
* @param query_cpu_range Base CPU address to loop over
* @param size Size in bytes of the CPU range to loop over
* @param func Function to call for each turned off region
*/
template <Type type, bool clear, typename Func>
void ForEachModifiedRange(VAddr query_cpu_range, s64 size, Func&& func) {
static_assert(type != Type::Untracked);
std::span<u64> state_words = words.template Span<type>();
[[maybe_unused]] std::span<u64> untracked_words = words.template Span<Type::Untracked>();
const size_t offset = query_cpu_range - cpu_addr;
bool pending = false;
size_t pending_offset{};
size_t pending_pointer{};
const auto release = [&]() {
func(cpu_addr + pending_offset * BYTES_PER_PAGE,
(pending_pointer - pending_offset) * BYTES_PER_PAGE);
};
IterateWords(offset, size, [&](size_t index, u64 mask) {
if constexpr (type == Type::GPU) {
mask &= ~untracked_words[index];
}
const u64 word = state_words[index] & mask;
if constexpr (clear) {
if constexpr (type == Type::CPU) {
NotifyPageTracker<true>(index, untracked_words[index], mask);
}
state_words[index] &= ~mask;
if constexpr (type == Type::CPU) {
untracked_words[index] &= ~mask;
}
}
const size_t base_offset = index * PAGES_PER_WORD;
IteratePages(word, [&](size_t pages_offset, size_t pages_size) {
const auto reset = [&]() {
pending_offset = base_offset + pages_offset;
pending_pointer = base_offset + pages_offset + pages_size;
};
if (!pending) {
reset();
pending = true;
return;
}
if (pending_pointer == base_offset + pages_offset) {
pending_pointer += pages_size;
return;
}
release();
reset();
});
});
if (pending) {
release();
}
}
/**
* Returns true when a region has been modified
*
* @param offset Offset in bytes from the start of the buffer
* @param size Size in bytes of the region to query for modifications
*/
template <Type type>
[[nodiscard]] bool IsRegionModified(u64 offset, u64 size) const noexcept {
static_assert(type != Type::Untracked);
const std::span<const u64> state_words = words.template Span<type>();
[[maybe_unused]] const std::span<const u64> untracked_words =
words.template Span<Type::Untracked>();
bool result = false;
IterateWords(offset, size, [&](size_t index, u64 mask) {
if constexpr (type == Type::GPU) {
mask &= ~untracked_words[index];
}
const u64 word = state_words[index] & mask;
if (word != 0) {
result = true;
return true;
}
return false;
});
return result;
}
/// Returns the number of words of the manager
[[nodiscard]] size_t NumWords() const noexcept {
return words.NumWords();
}
/// Returns the size in bytes of the manager
[[nodiscard]] u64 SizeBytes() const noexcept {
return words.size_bytes;
}
/// Returns true when the buffer fits in the small vector optimization
[[nodiscard]] bool IsShort() const noexcept {
return words.IsShort();
}
private:
template <Type type>
u64* Array() noexcept {
if constexpr (type == Type::CPU) {
return words.cpu.Pointer(IsShort());
} else if constexpr (type == Type::GPU) {
return words.gpu.Pointer(IsShort());
} else if constexpr (type == Type::Untracked) {
return words.untracked.Pointer(IsShort());
}
}
template <Type type>
const u64* Array() const noexcept {
if constexpr (type == Type::CPU) {
return words.cpu.Pointer(IsShort());
} else if constexpr (type == Type::GPU) {
return words.gpu.Pointer(IsShort());
} else if constexpr (type == Type::Untracked) {
return words.untracked.Pointer(IsShort());
}
}
/**
* Notify tracker about changes in the CPU tracking state of a word in the buffer
*
* @param word_index Index to the word to notify to the tracker
* @param current_bits Current state of the word
* @param new_bits New state of the word
*
* @tparam add_to_tracker True when the tracker should start tracking the new pages
*/
template <bool add_to_tracker>
void NotifyPageTracker(u64 word_index, u64 current_bits, u64 new_bits) const {
u64 changed_bits = (add_to_tracker ? current_bits : ~current_bits) & new_bits;
VAddr addr = cpu_addr + word_index * BYTES_PER_WORD;
IteratePages(changed_bits, [&](size_t offset, size_t size) {
tracker->UpdatePagesCachedCount(addr + offset * BYTES_PER_PAGE, size * BYTES_PER_PAGE,
add_to_tracker ? 1 : -1);
});
}
PageManager* tracker;
VAddr cpu_addr = 0;
Words<stack_words> words;
};
} // namespace VideoCore
| 14,945
|
C++
|
.h
| 357
| 31.666667
| 101
| 0.564249
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,934
|
buffer.h
|
shadps4-emu_shadPS4/src/video_core/buffer_cache/buffer.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <cstddef>
#include <optional>
#include <utility>
#include <vector>
#include "common/types.h"
#include "video_core/amdgpu/resource.h"
#include "video_core/renderer_vulkan/vk_common.h"
namespace Vulkan {
class Instance;
class Scheduler;
} // namespace Vulkan
VK_DEFINE_HANDLE(VmaAllocation)
VK_DEFINE_HANDLE(VmaAllocator)
struct VmaAllocationInfo;
namespace VideoCore {
/// Hints and requirements for the backing memory type of a commit
enum class MemoryUsage {
DeviceLocal, ///< Requests device local buffer.
Upload, ///< Requires a host visible memory type optimized for CPU to GPU uploads
Download, ///< Requires a host visible memory type optimized for GPU to CPU readbacks
Stream, ///< Requests device local host visible buffer, falling back host memory.
};
constexpr vk::BufferUsageFlags ReadFlags =
vk::BufferUsageFlagBits::eTransferSrc | vk::BufferUsageFlagBits::eUniformTexelBuffer |
vk::BufferUsageFlagBits::eUniformBuffer | vk::BufferUsageFlagBits::eIndexBuffer |
vk::BufferUsageFlagBits::eVertexBuffer | vk::BufferUsageFlagBits::eIndirectBuffer;
constexpr vk::BufferUsageFlags AllFlags = ReadFlags | vk::BufferUsageFlagBits::eTransferDst |
vk::BufferUsageFlagBits::eStorageTexelBuffer |
vk::BufferUsageFlagBits::eStorageBuffer;
struct UniqueBuffer {
explicit UniqueBuffer(vk::Device device, VmaAllocator allocator);
~UniqueBuffer();
UniqueBuffer(const UniqueBuffer&) = delete;
UniqueBuffer& operator=(const UniqueBuffer&) = delete;
UniqueBuffer(UniqueBuffer&& other)
: allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)},
buffer{std::exchange(other.buffer, VK_NULL_HANDLE)} {}
UniqueBuffer& operator=(UniqueBuffer&& other) {
buffer = std::exchange(other.buffer, VK_NULL_HANDLE);
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
allocation = std::exchange(other.allocation, VK_NULL_HANDLE);
return *this;
}
void Create(const vk::BufferCreateInfo& image_ci, MemoryUsage usage,
VmaAllocationInfo* out_alloc_info);
operator vk::Buffer() const {
return buffer;
}
vk::Device device;
VmaAllocator allocator;
VmaAllocation allocation;
vk::Buffer buffer{};
};
class Buffer {
public:
explicit Buffer(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler,
MemoryUsage usage, VAddr cpu_addr_, vk::BufferUsageFlags flags,
u64 size_bytes_);
Buffer& operator=(const Buffer&) = delete;
Buffer(const Buffer&) = delete;
Buffer& operator=(Buffer&&) = default;
Buffer(Buffer&&) = default;
vk::BufferView View(u32 offset, u32 size, bool is_written, AmdGpu::DataFormat dfmt,
AmdGpu::NumberFormat nfmt);
/// Increases the likeliness of this being a stream buffer
void IncreaseStreamScore(int score) noexcept {
stream_score += score;
}
/// Returns the likeliness of this being a stream buffer
[[nodiscard]] int StreamScore() const noexcept {
return stream_score;
}
/// Returns true when vaddr -> vaddr+size is fully contained in the buffer
[[nodiscard]] bool IsInBounds(VAddr addr, u64 size) const noexcept {
return addr >= cpu_addr && addr + size <= cpu_addr + SizeBytes();
}
/// Returns the base CPU address of the buffer
[[nodiscard]] VAddr CpuAddr() const noexcept {
return cpu_addr;
}
/// Returns the offset relative to the given CPU address
[[nodiscard]] u32 Offset(VAddr other_cpu_addr) const noexcept {
return static_cast<u32>(other_cpu_addr - cpu_addr);
}
size_t SizeBytes() const {
return size_bytes;
}
vk::Buffer Handle() const noexcept {
return buffer;
}
std::optional<vk::BufferMemoryBarrier2> GetBarrier(vk::AccessFlagBits2 dst_acess_mask,
vk::PipelineStageFlagBits2 dst_stage) {
if (dst_acess_mask == access_mask && stage == dst_stage) {
return {};
}
auto barrier = vk::BufferMemoryBarrier2{
.srcStageMask = stage,
.srcAccessMask = access_mask,
.dstStageMask = dst_stage,
.dstAccessMask = dst_acess_mask,
.buffer = buffer.buffer,
.size = size_bytes,
};
access_mask = dst_acess_mask;
stage = dst_stage;
return barrier;
}
public:
VAddr cpu_addr = 0;
bool is_picked{};
bool is_coherent{};
bool is_deleted{};
int stream_score = 0;
size_t size_bytes = 0;
std::span<u8> mapped_data;
const Vulkan::Instance* instance;
Vulkan::Scheduler* scheduler;
MemoryUsage usage;
UniqueBuffer buffer;
vk::AccessFlagBits2 access_mask{vk::AccessFlagBits2::eNone};
vk::PipelineStageFlagBits2 stage{vk::PipelineStageFlagBits2::eNone};
};
class StreamBuffer : public Buffer {
public:
explicit StreamBuffer(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler,
MemoryUsage usage, u64 size_bytes_);
/// Reserves a region of memory from the stream buffer.
std::pair<u8*, u64> Map(u64 size, u64 alignment = 0);
/// Ensures that reserved bytes of memory are available to the GPU.
void Commit();
/// Maps and commits a memory region with user provided data
u64 Copy(VAddr src, size_t size, size_t alignment = 0) {
const auto [data, offset] = Map(size, alignment);
std::memcpy(data, reinterpret_cast<const void*>(src), size);
Commit();
return offset;
}
u64 GetFreeSize() const {
return size_bytes - offset - mapped_size;
}
private:
struct Watch {
u64 tick{};
u64 upper_bound{};
};
/// Increases the amount of watches available.
void ReserveWatches(std::vector<Watch>& watches, std::size_t grow_size);
/// Waits pending watches until requested upper bound.
void WaitPendingOperations(u64 requested_upper_bound);
private:
u64 offset{};
u64 mapped_size{};
std::vector<Watch> current_watches;
std::size_t current_watch_cursor{};
std::optional<size_t> invalidation_mark;
std::vector<Watch> previous_watches;
std::size_t wait_cursor{};
u64 wait_bound{};
};
} // namespace VideoCore
| 6,836
|
C++
|
.h
| 164
| 33.689024
| 95
| 0.654534
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,935
|
range_set.h
|
shadps4-emu_shadPS4/src/video_core/buffer_cache/range_set.h
|
// SPDX-FileCopyrightText: 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <boost/icl/interval_map.hpp>
#include <boost/pool/pool.hpp>
#include <boost/pool/pool_alloc.hpp>
#include <boost/pool/poolfwd.hpp>
#include "common/types.h"
namespace VideoCore {
template <class T>
using RangeSetsAllocator =
boost::fast_pool_allocator<T, boost::default_user_allocator_new_delete,
boost::details::pool::default_mutex, 1024, 2048>;
struct RangeSet {
using IntervalSet =
boost::icl::interval_set<VAddr, std::less,
ICL_INTERVAL_INSTANCE(ICL_INTERVAL_DEFAULT, VAddr, std::less),
RangeSetsAllocator>;
using IntervalType = typename IntervalSet::interval_type;
explicit RangeSet() = default;
~RangeSet() = default;
void Add(VAddr base_address, size_t size) {
const VAddr end_address = base_address + size;
IntervalType interval{base_address, end_address};
m_ranges_set.add(interval);
}
void Subtract(VAddr base_address, size_t size) {
const VAddr end_address = base_address + size;
IntervalType interval{base_address, end_address};
m_ranges_set.subtract(interval);
}
template <typename Func>
void ForEach(Func&& func) const {
if (m_ranges_set.empty()) {
return;
}
for (const auto& set : m_ranges_set) {
const VAddr inter_addr_end = set.upper();
const VAddr inter_addr = set.lower();
func(inter_addr, inter_addr_end);
}
}
template <typename Func>
void ForEachInRange(VAddr base_addr, size_t size, Func&& func) const {
if (m_ranges_set.empty()) {
return;
}
const VAddr start_address = base_addr;
const VAddr end_address = start_address + size;
const IntervalType search_interval{start_address, end_address};
auto it = m_ranges_set.lower_bound(search_interval);
if (it == m_ranges_set.end()) {
return;
}
auto end_it = m_ranges_set.upper_bound(search_interval);
for (; it != end_it; it++) {
VAddr inter_addr_end = it->upper();
VAddr inter_addr = it->lower();
if (inter_addr_end > end_address) {
inter_addr_end = end_address;
}
if (inter_addr < start_address) {
inter_addr = start_address;
}
func(inter_addr, inter_addr_end);
}
}
IntervalSet m_ranges_set;
};
class RangeMap {
public:
using IntervalMap =
boost::icl::interval_map<VAddr, u64, boost::icl::partial_absorber, std::less,
boost::icl::inplace_plus, boost::icl::inter_section,
ICL_INTERVAL_INSTANCE(ICL_INTERVAL_DEFAULT, VAddr, std::less),
RangeSetsAllocator>;
using IntervalType = typename IntervalMap::interval_type;
public:
RangeMap() = default;
~RangeMap() = default;
RangeMap(RangeMap const&) = delete;
RangeMap& operator=(RangeMap const&) = delete;
RangeMap(RangeMap&& other);
RangeMap& operator=(RangeMap&& other);
void Add(VAddr base_address, size_t size, u64 value) {
const VAddr end_address = base_address + size;
IntervalType interval{base_address, end_address};
m_ranges_map.add({interval, value});
}
void Subtract(VAddr base_address, size_t size) {
const VAddr end_address = base_address + size;
IntervalType interval{base_address, end_address};
m_ranges_map -= interval;
}
template <typename Func>
void ForEachInRange(VAddr base_addr, size_t size, Func&& func) const {
if (m_ranges_map.empty()) {
return;
}
const VAddr start_address = base_addr;
const VAddr end_address = start_address + size;
const IntervalType search_interval{start_address, end_address};
auto it = m_ranges_map.lower_bound(search_interval);
if (it == m_ranges_map.end()) {
return;
}
auto end_it = m_ranges_map.upper_bound(search_interval);
for (; it != end_it; it++) {
VAddr inter_addr_end = it->first.upper();
VAddr inter_addr = it->first.lower();
if (inter_addr_end > end_address) {
inter_addr_end = end_address;
}
if (inter_addr < start_address) {
inter_addr = start_address;
}
func(inter_addr, inter_addr_end, it->second);
}
}
template <typename Func>
void ForEachNotInRange(VAddr base_addr, size_t size, Func&& func) const {
const VAddr end_addr = base_addr + size;
ForEachInRange(base_addr, size, [&](VAddr range_addr, VAddr range_end, u64) {
if (size_t gap_size = range_addr - base_addr; gap_size != 0) {
func(base_addr, gap_size);
}
base_addr = range_end;
});
if (base_addr != end_addr) {
func(base_addr, end_addr - base_addr);
}
}
private:
IntervalMap m_ranges_map;
};
} // namespace VideoCore
| 5,283
|
C++
|
.h
| 136
| 29.683824
| 95
| 0.59239
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,936
|
buffer_cache.h
|
shadps4-emu_shadPS4/src/video_core/buffer_cache/buffer_cache.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <mutex>
#include <boost/container/small_vector.hpp>
#include <boost/icl/interval_map.hpp>
#include <tsl/robin_map.h>
#include "common/div_ceil.h"
#include "common/slot_vector.h"
#include "common/types.h"
#include "video_core/buffer_cache/buffer.h"
#include "video_core/buffer_cache/memory_tracker_base.h"
#include "video_core/buffer_cache/range_set.h"
#include "video_core/multi_level_page_table.h"
namespace AmdGpu {
struct Liverpool;
}
namespace Shader {
struct Info;
}
namespace VideoCore {
using BufferId = Common::SlotId;
static constexpr BufferId NULL_BUFFER_ID{0};
class TextureCache;
class BufferCache {
public:
static constexpr u32 CACHING_PAGEBITS = 12;
static constexpr u64 CACHING_PAGESIZE = u64{1} << CACHING_PAGEBITS;
static constexpr u64 DEVICE_PAGESIZE = 4_KB;
struct Traits {
using Entry = BufferId;
static constexpr size_t AddressSpaceBits = 39;
static constexpr size_t FirstLevelBits = 14;
static constexpr size_t PageBits = CACHING_PAGEBITS;
};
using PageTable = MultiLevelPageTable<Traits>;
struct OverlapResult {
boost::container::small_vector<BufferId, 16> ids;
VAddr begin;
VAddr end;
bool has_stream_leap = false;
};
public:
explicit BufferCache(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler,
AmdGpu::Liverpool* liverpool, TextureCache& texture_cache,
PageManager& tracker);
~BufferCache();
/// Returns a pointer to GDS device local buffer.
[[nodiscard]] const Buffer* GetGdsBuffer() const noexcept {
return &gds_buffer;
}
/// Retrieves the buffer with the specified id.
[[nodiscard]] Buffer& GetBuffer(BufferId id) {
return slot_buffers[id];
}
[[nodiscard]] vk::BufferView& NullBufferView() {
return null_buffer_view;
}
/// Invalidates any buffer in the logical page range.
void InvalidateMemory(VAddr device_addr, u64 size);
/// Binds host vertex buffers for the current draw.
bool BindVertexBuffers(const Shader::Info& vs_info);
/// Bind host index buffer for the current draw.
u32 BindIndexBuffer(bool& is_indexed, u32 index_offset);
/// Writes a value to GPU buffer.
void InlineData(VAddr address, const void* value, u32 num_bytes, bool is_gds);
[[nodiscard]] std::pair<Buffer*, u32> ObtainHostUBO(std::span<const u32> data);
/// Obtains a buffer for the specified region.
[[nodiscard]] std::pair<Buffer*, u32> ObtainBuffer(VAddr gpu_addr, u32 size, bool is_written,
bool is_texel_buffer = false,
BufferId buffer_id = {});
/// Attempts to obtain a buffer without modifying the cache contents.
[[nodiscard]] std::pair<Buffer*, u32> ObtainViewBuffer(VAddr gpu_addr, u32 size);
/// Return true when a region is registered on the cache
[[nodiscard]] bool IsRegionRegistered(VAddr addr, size_t size);
/// Return true when a CPU region is modified from the CPU
[[nodiscard]] bool IsRegionCpuModified(VAddr addr, size_t size);
/// Return true when a CPU region is modified from the GPU
[[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size);
[[nodiscard]] BufferId FindBuffer(VAddr device_addr, u32 size);
private:
template <typename Func>
void ForEachBufferInRange(VAddr device_addr, u64 size, Func&& func) {
const u64 page_end = Common::DivCeil(device_addr + size, CACHING_PAGESIZE);
for (u64 page = device_addr >> CACHING_PAGEBITS; page < page_end;) {
const BufferId buffer_id = page_table[page];
if (!buffer_id) {
++page;
continue;
}
Buffer& buffer = slot_buffers[buffer_id];
func(buffer_id, buffer);
const VAddr end_addr = buffer.CpuAddr() + buffer.SizeBytes();
page = Common::DivCeil(end_addr, CACHING_PAGESIZE);
}
}
void DownloadBufferMemory(Buffer& buffer, VAddr device_addr, u64 size);
[[nodiscard]] OverlapResult ResolveOverlaps(VAddr device_addr, u32 wanted_size);
void JoinOverlap(BufferId new_buffer_id, BufferId overlap_id, bool accumulate_stream_score);
[[nodiscard]] BufferId CreateBuffer(VAddr device_addr, u32 wanted_size);
void Register(BufferId buffer_id);
void Unregister(BufferId buffer_id);
template <bool insert>
void ChangeRegister(BufferId buffer_id);
void SynchronizeBuffer(Buffer& buffer, VAddr device_addr, u32 size, bool is_texel_buffer);
bool SynchronizeBufferFromImage(Buffer& buffer, VAddr device_addr, u32 size);
void DeleteBuffer(BufferId buffer_id);
const Vulkan::Instance& instance;
Vulkan::Scheduler& scheduler;
AmdGpu::Liverpool* liverpool;
TextureCache& texture_cache;
PageManager& tracker;
StreamBuffer staging_buffer;
StreamBuffer stream_buffer;
Buffer gds_buffer;
std::mutex mutex;
Common::SlotVector<Buffer> slot_buffers;
RangeSet gpu_modified_ranges;
vk::BufferView null_buffer_view;
MemoryTracker memory_tracker;
PageTable page_table;
};
} // namespace VideoCore
| 5,547
|
C++
|
.h
| 123
| 37.146341
| 98
| 0.673466
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,937
|
liverpool.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/liverpool.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <array>
#include <condition_variable>
#include <coroutine>
#include <exception>
#include <mutex>
#include <span>
#include <thread>
#include <vector>
#include <queue>
#include "common/assert.h"
#include "common/bit_field.h"
#include "common/polyfill_thread.h"
#include "common/types.h"
#include "common/unique_function.h"
#include "shader_recompiler/params.h"
#include "types.h"
#include "video_core/amdgpu/pixel_format.h"
#include "video_core/amdgpu/resource.h"
namespace Vulkan {
class Rasterizer;
}
namespace Libraries::VideoOut {
struct VideoOutPort;
}
namespace AmdGpu {
#define GFX6_3D_REG_INDEX(field_name) (offsetof(AmdGpu::Liverpool::Regs, field_name) / sizeof(u32))
#define CONCAT2(x, y) DO_CONCAT2(x, y)
#define DO_CONCAT2(x, y) x##y
#define INSERT_PADDING_WORDS(num_words) \
[[maybe_unused]] std::array<u32, num_words> CONCAT2(pad, __LINE__)
struct Liverpool {
static constexpr u32 GfxQueueId = 0u;
static constexpr u32 NumGfxRings = 1u; // actually 2, but HP is reserved by system software
static constexpr u32 NumComputePipes = 7u; // actually 8, but #7 is reserved by system software
static constexpr u32 NumQueuesPerPipe = 8u;
static constexpr u32 NumTotalQueues = NumGfxRings + (NumComputePipes * NumQueuesPerPipe);
static_assert(NumTotalQueues < 64u); // need to fit into u64 bitmap for ffs
static constexpr u32 NumColorBuffers = 8;
static constexpr u32 NumViewports = 16;
static constexpr u32 NumClipPlanes = 6;
static constexpr u32 NumShaderUserData = 16;
static constexpr u32 UconfigRegWordOffset = 0xC000;
static constexpr u32 ContextRegWordOffset = 0xA000;
static constexpr u32 ConfigRegWordOffset = 0x2000;
static constexpr u32 ShRegWordOffset = 0x2C00;
static constexpr u32 NumRegs = 0xD000;
using UserData = std::array<u32, NumShaderUserData>;
struct BinaryInfo {
static constexpr u8 signature_ref[] = {0x4f, 0x72, 0x62, 0x53, 0x68, 0x64, 0x72}; // OrbShdr
std::array<u8, sizeof(signature_ref)> signature;
u8 version;
u32 pssl_or_cg : 1;
u32 cached : 1;
u32 type : 4;
u32 source_type : 2;
u32 length : 24;
u8 chunk_usage_base_offset_in_dw;
u8 num_input_usage_slots;
u8 is_srt : 1;
u8 is_srt_used_info_valid : 1;
u8 is_extended_usage_info : 1;
u8 reserved2 : 5;
u8 reserved3;
u64 shader_hash;
u32 crc32;
bool Valid() const {
return shader_hash && crc32 &&
(std::memcmp(signature.data(), signature_ref, sizeof(signature_ref)) == 0);
}
};
struct ShaderProgram {
u32 address_lo;
BitField<0, 8, u32> address_hi;
union {
BitField<0, 6, u64> num_vgprs;
BitField<6, 4, u64> num_sgprs;
BitField<10, 2, u64> priority;
BitField<12, 2, FpRoundMode> fp_round_mode32;
BitField<14, 2, FpRoundMode> fp_round_mode64;
BitField<16, 2, FpDenormMode> fp_denorm_mode32;
BitField<18, 2, FpDenormMode> fp_denorm_mode64;
BitField<12, 8, u64> float_mode;
BitField<24, 2, u64> vgpr_comp_cnt; // SPI provided per-thread inputs
BitField<33, 5, u64> num_user_regs;
} settings;
UserData user_data;
template <typename T = u8*>
const T Address() const {
const uintptr_t addr = uintptr_t(address_hi) << 40 | uintptr_t(address_lo) << 8;
return reinterpret_cast<const T>(addr);
}
std::span<const u32> Code() const {
const u32* code = Address<u32*>();
BinaryInfo bininfo;
std::memcpy(&bininfo, code + (code[1] + 1) * 2, sizeof(bininfo));
const u32 num_dwords = bininfo.length / sizeof(u32);
return std::span{code, num_dwords};
}
};
struct ComputeProgram {
u32 dispatch_initiator;
u32 dim_x;
u32 dim_y;
u32 dim_z;
u32 start_x;
u32 start_y;
u32 start_z;
struct {
u16 full;
u16 partial;
} num_thread_x, num_thread_y, num_thread_z;
INSERT_PADDING_WORDS(1);
BitField<0, 12, u32> max_wave_id;
u32 address_lo;
BitField<0, 8, u32> address_hi;
INSERT_PADDING_WORDS(4);
union {
BitField<0, 6, u64> num_vgprs;
BitField<6, 4, u64> num_sgprs;
BitField<33, 5, u64> num_user_regs;
BitField<39, 3, u64> tgid_enable;
BitField<47, 9, u64> lds_dwords;
} settings;
INSERT_PADDING_WORDS(1);
u32 resource_limits;
INSERT_PADDING_WORDS(0x2A);
UserData user_data;
template <typename T = u8*>
const T Address() const {
const uintptr_t addr = uintptr_t(address_hi) << 40 | uintptr_t(address_lo) << 8;
return reinterpret_cast<const T>(addr);
}
u32 SharedMemSize() const noexcept {
// lds_dwords is in units of 128 dwords. We return bytes.
return settings.lds_dwords.Value() * 128 * 4;
}
bool IsTgidEnabled(u32 i) const noexcept {
return (settings.tgid_enable.Value() >> i) & 1;
}
std::span<const u32> Code() const {
const u32* code = Address<u32*>();
BinaryInfo bininfo;
std::memcpy(&bininfo, code + (code[1] + 1) * 2, sizeof(bininfo));
const u32 num_dwords = bininfo.length / sizeof(u32);
return std::span{code, num_dwords};
}
};
template <typename Shader>
static constexpr auto* GetBinaryInfo(const Shader& sh) {
const auto* code = sh.template Address<u32*>();
const auto* bininfo = std::bit_cast<const BinaryInfo*>(code + (code[1] + 1) * 2);
// ASSERT_MSG(bininfo->Valid(), "Invalid shader binary header");
return bininfo;
}
static constexpr Shader::ShaderParams GetParams(const auto& sh) {
auto* bininfo = GetBinaryInfo(sh);
return {
.user_data = sh.user_data,
.code = sh.Code(),
.hash = bininfo->shader_hash,
};
}
union PsInputControl {
u32 raw;
BitField<0, 5, u32> input_offset;
BitField<5, 1, u32> use_default;
BitField<8, 2, u32> default_value;
BitField<10, 1, u32> flat_shade;
};
enum class ShaderExportComp : u32 {
None = 0,
OneComp = 1,
TwoComp = 2,
FourCompCompressed = 3,
FourComp = 4,
};
union ShaderPosFormat {
u32 raw;
BitField<0, 4, ShaderExportComp> pos0;
BitField<4, 4, ShaderExportComp> pos1;
BitField<8, 4, ShaderExportComp> pos2;
BitField<12, 4, ShaderExportComp> pos3;
};
enum class ShaderExportFormat : u32 {
Zero = 0,
R_32 = 1,
GR_32 = 2,
AR_32 = 3,
ABGR_FP16 = 4,
ABGR_UNORM16 = 5,
ABGR_SNORM16 = 6,
ABGR_UINT16 = 7,
ABGR_SINT16 = 8,
ABGR_32 = 9,
};
union ColorExportFormat {
u32 raw;
BitField<0, 4, ShaderExportFormat> col0;
BitField<4, 4, ShaderExportFormat> col1;
BitField<8, 4, ShaderExportFormat> col2;
BitField<12, 4, ShaderExportFormat> col3;
BitField<16, 4, ShaderExportFormat> col4;
BitField<20, 4, ShaderExportFormat> col5;
BitField<24, 4, ShaderExportFormat> col6;
BitField<28, 4, ShaderExportFormat> col7;
};
union VsOutputControl {
u32 raw;
BitField<0, 8, u32> clip_distance_enable;
BitField<8, 8, u32> cull_distance_enable;
BitField<16, 1, u32> use_vtx_point_size;
BitField<17, 1, u32> use_vtx_edge_flag;
BitField<18, 1, u32> use_vtx_render_target_idx;
BitField<19, 1, u32> use_vtx_viewport_idx;
BitField<20, 1, u32> use_vtx_kill_flag;
BitField<21, 1, u32> vs_out_misc_enable;
BitField<22, 1, u32> vs_out_ccdist0_enable;
BitField<23, 1, u32> vs_out_ccdist1_enable;
BitField<25, 1, u32> use_vtx_gs_cut_flag;
bool IsClipDistEnabled(u32 index) const {
return (clip_distance_enable.Value() >> index) & 1;
}
bool IsCullDistEnabled(u32 index) const {
return (cull_distance_enable.Value() >> index) & 1;
}
};
struct ModeControl {
s32 msaa_enable : 1;
s32 vport_scissor_enable : 1;
s32 line_stripple_enable : 1;
s32 send_unlit_stiles_to_pkr : 1;
};
enum class ZOrder : u32 {
LateZ = 0,
EarlyZLateZ = 1,
ReZ = 2,
EarlyZReZ = 3,
};
enum class ConservativeDepth : u32 {
Any = 0,
LessThanZ = 1,
GreaterThanZ = 2,
};
union DepthBufferControl {
u32 raw;
BitField<0, 1, u32> z_export_enable;
BitField<1, 1, u32> stencil_test_val_export_enable;
BitField<2, 1, u32> stencil_op_val_export_enable;
BitField<4, 2, ZOrder> z_order;
BitField<6, 1, u32> kill_enable;
BitField<7, 1, u32> coverage_to_mask_enable;
BitField<8, 1, u32> mask_export_enable;
BitField<9, 1, u32> exec_on_hier_fail;
BitField<10, 1, u32> exec_on_noop;
BitField<11, 1, u32> alpha_to_mask_disable;
BitField<12, 1, u32> depth_before_shader;
BitField<13, 2, ConservativeDepth> conservative_z_export;
};
enum class CompareFunc : u32 {
Never = 0,
Less = 1,
Equal = 2,
LessEqual = 3,
Greater = 4,
NotEqual = 5,
GreaterEqual = 6,
Always = 7,
};
union DepthControl {
u32 raw;
BitField<0, 1, u32> stencil_enable;
BitField<1, 1, u32> depth_enable;
BitField<2, 1, u32> depth_write_enable;
BitField<3, 1, u32> depth_bounds_enable;
BitField<4, 3, CompareFunc> depth_func;
BitField<7, 1, u32> backface_enable;
BitField<8, 3, CompareFunc> stencil_ref_func;
BitField<20, 3, CompareFunc> stencil_bf_func;
BitField<30, 1, u32> enable_color_writes_on_depth_fail;
BitField<31, 1, u32> disable_color_writes_on_depth_pass;
};
enum class StencilFunc : u32 {
Keep = 0,
Zero = 1,
Ones = 2,
ReplaceTest = 3,
ReplaceOp = 4,
AddClamp = 5,
SubClamp = 6,
Invert = 7,
AddWrap = 8,
SubWrap = 9,
And = 10,
Or = 11,
Xor = 12,
Nand = 13,
Nor = 14,
Xnor = 15,
};
union StencilControl {
u32 raw;
BitField<0, 4, StencilFunc> stencil_fail_front;
BitField<4, 4, StencilFunc> stencil_zpass_front;
BitField<8, 4, StencilFunc> stencil_zfail_front;
BitField<12, 4, StencilFunc> stencil_fail_back;
BitField<16, 4, StencilFunc> stencil_zpass_back;
BitField<20, 4, StencilFunc> stencil_zfail_back;
};
union StencilRefMask {
u32 raw;
BitField<0, 8, u32> stencil_test_val;
BitField<8, 8, u32> stencil_mask;
BitField<16, 8, u32> stencil_write_mask;
BitField<24, 8, u32> stencil_op_val;
};
struct DepthBuffer {
enum class ZFormat : u32 {
Invalid = 0,
Z16 = 1,
Z32Float = 3,
};
enum class StencilFormat : u32 {
Invalid = 0,
Stencil8 = 1,
};
union ZInfo {
BitField<0, 2, ZFormat> format;
BitField<2, 2, u32> num_samples;
BitField<13, 3, u32> tile_split;
BitField<20, 3, u32> tile_mode_index;
BitField<23, 4, u32> decompress_on_n_zplanes;
BitField<27, 1, u32> allow_expclear;
BitField<28, 1, u32> read_size;
BitField<29, 1, u32> tile_surface_en;
BitField<30, 1, u32> clear_disallowed;
BitField<31, 1, u32> zrange_precision;
} z_info;
union {
BitField<0, 1, StencilFormat> format;
} stencil_info;
u32 z_read_base;
u32 stencil_read_base;
u32 z_write_base;
u32 stencil_write_base;
union {
BitField<0, 11, u32> pitch_tile_max;
BitField<11, 11, u32> height_tile_max;
} depth_size;
union {
BitField<0, 22, u32> tile_max;
} depth_slice;
u32 Pitch() const {
return (depth_size.pitch_tile_max + 1) << 3;
}
u32 Height() const {
return (depth_size.height_tile_max + 1) << 3;
}
u64 Address() const {
return u64(z_read_base) << 8;
}
u32 NumSamples() const {
return 1u << z_info.num_samples; // spec doesn't say it is a log2
}
u32 NumBits() const {
return z_info.format == ZFormat::Z32Float ? 32 : 16;
}
size_t GetDepthSliceSize() const {
ASSERT(z_info.format != ZFormat::Invalid);
const auto bpe = NumBits() >> 3; // in bytes
return (depth_slice.tile_max + 1) * 64 * bpe * NumSamples();
}
};
enum class ClipSpace : u32 {
MinusWToW = 0,
ZeroToW = 1,
};
enum class PrimKillCond : u32 {
AllVtx = 0,
AnyVtx = 1,
};
union ClipperControl {
u32 raw;
BitField<0, 6, u32> user_clip_plane_enable;
BitField<16, 1, u32> clip_disable;
BitField<19, 1, ClipSpace> clip_space;
BitField<21, 1, PrimKillCond> vtx_kill_or;
BitField<22, 1, u32> dx_rasterization_kill;
BitField<23, 1, u32> dx_linear_attr_clip_enable;
BitField<26, 1, u32> zclip_near_disable;
BitField<26, 1, u32> zclip_far_disable;
};
enum class PolygonMode : u32 {
Point = 0,
Line = 1,
Fill = 2,
};
enum class ProvokingVtxLast : u32 {
First = 0,
Last = 1,
};
enum class CullMode : u32 {
None = 0,
Front = 1,
Back = 2,
FrontAndBack = 3,
};
enum class FrontFace : u32 {
CounterClockwise = 0,
Clockwise = 1,
};
union PolygonControl {
u32 raw;
BitField<0, 1, u32> cull_front;
BitField<1, 1, u32> cull_back;
BitField<2, 1, FrontFace> front_face;
BitField<3, 2, u32> enable_polygon_mode;
BitField<5, 3, PolygonMode> polygon_mode_front;
BitField<8, 3, PolygonMode> polygon_mode_back;
BitField<11, 1, u32> enable_polygon_offset_front;
BitField<12, 1, u32> enable_polygon_offset_back;
BitField<13, 1, u32> enable_polygon_offset_para;
BitField<16, 1, u32> enable_window_offset;
BitField<19, 1, ProvokingVtxLast> provoking_vtx_last;
BitField<20, 1, u32> persp_corr_dis;
BitField<21, 1, u32> multi_prim_ib_ena;
PolygonMode PolyMode() const {
return enable_polygon_mode ? polygon_mode_front.Value() : PolygonMode::Fill;
}
CullMode CullingMode() const {
return static_cast<CullMode>(cull_front | cull_back << 1);
}
bool NeedsBias() const {
return enable_polygon_offset_back || enable_polygon_offset_front ||
enable_polygon_offset_para;
}
};
union VsOutputConfig {
u32 raw;
BitField<1, 5, u32> export_count_min_one;
BitField<6, 1, u32> half_pack;
u32 NumExports() const {
return export_count_min_one.Value() + 1;
}
};
union ColorBufferMask {
enum ColorComponent : u32 {
ComponentR = (1u << 0),
ComponentG = (1u << 1),
ComponentB = (1u << 2),
ComponentA = (1u << 3),
};
u32 raw;
BitField<0, 4, u32> output0_mask;
BitField<4, 4, u32> output1_mask;
BitField<8, 4, u32> output2_mask;
BitField<12, 4, u32> output3_mask;
BitField<16, 4, u32> output4_mask;
BitField<20, 4, u32> output5_mask;
BitField<24, 4, u32> output6_mask;
BitField<28, 4, u32> output7_mask;
u32 GetMask(int buf_id) const {
return (raw >> (buf_id * 4)) & 0xfu;
}
void SetMask(int buf_id, u32 mask) {
raw &= ~(0xf << (buf_id * 4));
raw |= (mask << (buf_id * 4));
}
};
struct IndexBufferBase {
BitField<0, 8, u32> base_addr_hi;
u32 base_addr_lo;
template <typename T = VAddr>
T Address() const {
return std::bit_cast<T>((base_addr_lo & ~1U) | u64(base_addr_hi) << 32);
}
};
enum class IndexType : u32 {
Index16 = 0,
Index32 = 1,
};
enum class IndexSwapMode : u32 {
None = 0,
Swap16 = 1,
Swap32 = 2,
SwapWord = 3,
};
union IndexBufferType {
u32 raw;
BitField<0, 2, IndexType> index_type;
BitField<2, 2, IndexSwapMode> swap_mode;
};
union VgtNumInstances {
u32 num_instances;
u32 NumInstances() const {
return num_instances == 0 ? 1 : num_instances;
}
};
struct Scissor {
struct {
s16 top_left_x;
s16 top_left_y;
};
struct {
s16 bottom_right_x;
s16 bottom_right_y;
};
// From AMD spec: 'Negative numbers clamped to 0'
static s16 Clamp(s16 value) {
return std::max(s16(0), value);
}
u32 GetWidth() const {
return static_cast<u32>(Clamp(bottom_right_x) - Clamp(top_left_x));
}
u32 GetHeight() const {
return static_cast<u32>(Clamp(bottom_right_y) - Clamp(top_left_y));
}
};
struct WindowOffset {
s32 window_x_offset : 16;
s32 window_y_offset : 16;
};
struct ViewportScissor {
union {
BitField<0, 15, s32> top_left_x;
BitField<16, 15, s32> top_left_y;
BitField<31, 1, s32> window_offset_disable;
};
struct {
s16 bottom_right_x;
s16 bottom_right_y;
};
u32 GetWidth() const {
return bottom_right_x - top_left_x;
}
u32 GetHeight() const {
return bottom_right_y - top_left_y;
}
};
struct ViewportDepth {
float zmin;
float zmax;
};
struct ViewportBounds {
float xscale;
float xoffset;
float yscale;
float yoffset;
float zscale;
float zoffset;
};
union ViewportControl {
BitField<0, 1, u32> xscale_enable;
BitField<1, 1, u32> xoffset_enable;
BitField<2, 1, u32> yscale_enable;
BitField<3, 1, u32> yoffset_enable;
BitField<4, 1, u32> zscale_enable;
BitField<5, 1, u32> zoffset_enable;
BitField<8, 1, u32> xy_transformed;
BitField<9, 1, u32> z_transformed;
BitField<10, 1, u32> w_transformed;
BitField<11, 1, u32> perfcounter_ref;
};
struct ClipUserData {
u32 data_x;
u32 data_y;
u32 data_z;
u32 data_w;
};
struct BlendConstants {
float red;
float green;
float blue;
float alpha;
};
union BlendControl {
enum class BlendFactor : u32 {
Zero = 0,
One = 1,
SrcColor = 2,
OneMinusSrcColor = 3,
SrcAlpha = 4,
OneMinusSrcAlpha = 5,
DstAlpha = 6,
OneMinusDstAlpha = 7,
DstColor = 8,
OneMinusDstColor = 9,
SrcAlphaSaturate = 10,
ConstantColor = 13,
OneMinusConstantColor = 14,
Src1Color = 15,
InvSrc1Color = 16,
Src1Alpha = 17,
InvSrc1Alpha = 18,
ConstantAlpha = 19,
OneMinusConstantAlpha = 20,
};
enum class BlendFunc : u32 {
Add = 0,
Subtract = 1,
Min = 2,
Max = 3,
ReverseSubtract = 4,
};
BitField<0, 5, BlendFactor> color_src_factor;
BitField<5, 3, BlendFunc> color_func;
BitField<8, 5, BlendFactor> color_dst_factor;
BitField<16, 5, BlendFactor> alpha_src_factor;
BitField<21, 3, BlendFunc> alpha_func;
BitField<24, 5, BlendFactor> alpha_dst_factor;
BitField<29, 1, u32> separate_alpha_blend;
BitField<30, 1, u32> enable;
BitField<31, 1, u32> disable_rop3;
};
union ColorControl {
enum class OperationMode : u32 {
Disable = 0u,
Normal = 1u,
EliminateFastClear = 2u,
Resolve = 3u,
Err = 4u,
FmaskDecompress = 5u,
};
BitField<0, 1, u32> disable_dual_quad;
BitField<3, 1, u32> degamma_enable;
BitField<4, 3, OperationMode> mode;
BitField<16, 8, u32> rop3;
};
struct ColorBuffer {
enum class EndianSwap : u32 {
None = 0,
Swap8In16 = 1,
Swap8In32 = 2,
Swap8In64 = 3,
};
enum class SwapMode : u32 {
Standard = 0,
Alternate = 1,
StandardReverse = 2,
AlternateReverse = 3,
};
enum class RoundMode : u32 {
ByHalf = 0,
Truncate = 1,
};
u32 base_address;
union {
BitField<0, 11, u32> tile_max;
BitField<20, 11, u32> fmask_tile_max;
} pitch;
union {
BitField<0, 22, u32> tile_max;
} slice;
union {
BitField<0, 11, u32> slice_start;
BitField<13, 11, u32> slice_max;
} view;
union Color0Info {
BitField<0, 2, EndianSwap> endian;
BitField<2, 5, DataFormat> format;
BitField<7, 1, u32> linear_general;
BitField<8, 3, NumberFormat> number_type;
BitField<11, 2, SwapMode> comp_swap;
BitField<13, 1, u32> fast_clear;
BitField<14, 1, u32> compression;
BitField<15, 1, u32> blend_clamp;
BitField<16, 1, u32> blend_bypass;
BitField<17, 1, u32> simple_float;
BitField<18, 1, RoundMode> round_mode;
BitField<19, 1, u32> cmask_is_linear;
BitField<20, 3, u32> blend_opt_dont_rd_dst;
BitField<23, 3, u32> blend_opt_discard_pixel;
BitField<26, 1, u32> fmask_compression_disable_ci;
BitField<27, 1, u32> fmask_compress_1frag_only;
BitField<28, 1, u32> dcc_enable;
BitField<29, 1, u32> cmask_addr_type;
u32 u32all;
} info;
union Color0Attrib {
BitField<0, 5, TilingMode> tile_mode_index;
BitField<5, 5, u32> fmask_tile_mode_index;
BitField<10, 2, u32> fmask_bank_height;
BitField<12, 3, u32> num_samples_log2;
BitField<15, 2, u32> num_fragments_log2;
BitField<17, 1, u32> force_dst_alpha_1;
u32 u32all;
} attrib;
INSERT_PADDING_WORDS(1);
u32 cmask_base_address;
union {
BitField<0, 14, u32> tile_max;
} cmask_slice;
u32 fmask_base_address;
union {
BitField<0, 14, u32> tile_max;
} fmask_slice;
u32 clear_word0;
u32 clear_word1;
INSERT_PADDING_WORDS(2);
operator bool() const {
return info.format != DataFormat::FormatInvalid;
}
u32 Pitch() const {
return (pitch.tile_max + 1) << 3;
}
u32 Height() const {
return (slice.tile_max + 1) * 64 / Pitch();
}
u64 Address() const {
return u64(base_address) << 8;
}
VAddr CmaskAddress() const {
return VAddr(cmask_base_address) << 8;
}
VAddr FmaskAddress() const {
return VAddr(fmask_base_address) << 8;
}
u32 NumSamples() const {
return 1 << attrib.num_fragments_log2;
}
u32 NumSlices() const {
return view.slice_max + 1;
}
size_t GetColorSliceSize() const {
const auto num_bytes_per_element = NumBits(info.format) / 8u;
const auto slice_size =
num_bytes_per_element * (slice.tile_max + 1) * 64u * NumSamples();
return slice_size;
}
TilingMode GetTilingMode() const {
return info.linear_general ? TilingMode::Display_Linear
: attrib.tile_mode_index.Value();
}
bool IsTiled() const {
return !info.linear_general;
}
NumberFormat NumFormat() const {
// There is a small difference between T# and CB number types, account for it.
return info.number_type == AmdGpu::NumberFormat::SnormNz ? AmdGpu::NumberFormat::Srgb
: info.number_type.Value();
}
};
enum ContextRegs : u32 {
DbZInfo = 0xA010,
CbColor0Base = 0xA318,
CbColor1Base = 0xA327,
CbColor2Base = 0xA336,
CbColor3Base = 0xA345,
CbColor4Base = 0xA354,
CbColor5Base = 0xA363,
CbColor6Base = 0xA372,
CbColor7Base = 0xA381,
CbColor0Cmask = 0xA31F,
CbColor1Cmask = 0xA32E,
CbColor2Cmask = 0xA33D,
CbColor3Cmask = 0xA34C,
CbColor4Cmask = 0xA35B,
CbColor5Cmask = 0xA36A,
CbColor6Cmask = 0xA379,
CbColor7Cmask = 0xA388,
};
struct PolygonOffset {
float depth_bias;
float front_scale;
float front_offset;
float back_scale;
float back_offset;
};
struct Address {
u32 address;
VAddr GetAddress() const {
return u64(address) << 8;
}
};
union DepthRenderControl {
u32 raw;
BitField<0, 1, u32> depth_clear_enable;
BitField<1, 1, u32> stencil_clear_enable;
BitField<2, 1, u32> depth_copy;
BitField<3, 1, u32> stencil_copy;
BitField<4, 1, u32> resummarize_enable;
BitField<5, 1, u32> stencil_compress_disable;
BitField<6, 1, u32> depth_compress_disable;
BitField<7, 1, u32> copy_centroid;
BitField<8, 1, u32> copy_sample;
BitField<9, 1, u32> decompress_enable;
};
union DepthView {
BitField<0, 11, u32> slice_start;
BitField<13, 11, u32> slice_max;
BitField<24, 1, u32> z_read_only;
BitField<25, 1, u32> stencil_read_only;
u32 NumSlices() const {
return slice_max + 1u;
}
};
union AaConfig {
BitField<0, 3, u32> msaa_num_samples;
BitField<4, 1, u32> aa_mask_centroid_dtmn;
BitField<13, 4, u32> max_sample_dst;
BitField<20, 3, u32> msaa_exposed_samples;
BitField<24, 2, u32> detail_to_exposed_mode;
u32 NumSamples() const {
return 1 << msaa_num_samples;
}
};
union ShaderStageEnable {
enum VgtStages : u32 {
Vs = 0u, // always enabled
EsGs = 0xB0u,
};
VgtStages raw;
BitField<0, 2, u32> ls_en;
BitField<2, 1, u32> hs_en;
BitField<3, 2, u32> es_en;
BitField<5, 1, u32> gs_en;
BitField<6, 1, u32> vs_en;
bool IsStageEnabled(u32 stage) const {
switch (stage) {
case 0:
case 1:
return true;
case 2:
return gs_en.Value();
case 3:
return es_en.Value();
case 4:
return hs_en.Value();
case 5:
return ls_en.Value();
default:
UNREACHABLE();
}
}
};
union GsInstances {
u32 raw;
struct {
u32 enable : 2;
u32 count : 6;
};
bool IsEnabled() const {
return enable && count > 0;
}
};
union GsOutPrimitiveType {
u32 raw;
struct {
GsOutputPrimitiveType outprim_type : 6;
GsOutputPrimitiveType outprim_type1 : 6;
GsOutputPrimitiveType outprim_type2 : 6;
GsOutputPrimitiveType outprim_type3 : 6;
u32 reserved : 3;
u32 unique_type_per_stream : 1;
};
GsOutputPrimitiveType GetPrimitiveType(u32 stream) const {
if (unique_type_per_stream == 0) {
return outprim_type;
}
switch (stream) {
case 0:
return outprim_type;
case 1:
return outprim_type1;
case 2:
return outprim_type2;
case 3:
return outprim_type3;
default:
UNREACHABLE();
}
}
};
union GsMode {
u32 raw;
BitField<0, 3, u32> mode;
BitField<3, 2, u32> cut_mode;
BitField<22, 2, u32> onchip;
};
union StreamOutConfig {
u32 raw;
struct {
u32 streamout_0_en : 1;
u32 streamout_1_en : 1;
u32 streamout_2_en : 1;
u32 streamout_3_en : 1;
u32 rast_stream : 3;
u32 : 1;
u32 rast_stream_mask : 4;
u32 : 19;
u32 use_rast_stream_mask : 1;
};
};
union StreamOutBufferConfig {
u32 raw;
struct {
u32 stream_0_buf_en : 4;
u32 stream_1_buf_en : 4;
u32 stream_2_buf_en : 4;
u32 stream_3_buf_en : 4;
};
};
union Eqaa {
u32 raw;
BitField<0, 1, u32> max_anchor_samples;
BitField<4, 3, u32> ps_iter_samples;
BitField<8, 3, u32> mask_export_num_samples;
BitField<12, 3, u32> alpha_to_mask_num_samples;
BitField<16, 1, u32> high_quality_intersections;
BitField<17, 1, u32> incoherent_eqaa_reads;
BitField<18, 1, u32> interpolate_comp_z;
BitField<19, 1, u32> interpolate_src_z;
BitField<20, 1, u32> static_anchor_associations;
BitField<21, 1, u32> alpha_to_mask_eqaa_disable;
BitField<24, 3, u32> overrasterization_amount;
BitField<27, 1, u32> enable_postz_overrasterization;
};
union Regs {
struct {
INSERT_PADDING_WORDS(0x2C08);
ShaderProgram ps_program;
INSERT_PADDING_WORDS(0x2C);
ShaderProgram vs_program;
INSERT_PADDING_WORDS(0x2C);
ShaderProgram gs_program;
INSERT_PADDING_WORDS(0x2C);
ShaderProgram es_program;
INSERT_PADDING_WORDS(0x2C);
ShaderProgram hs_program;
INSERT_PADDING_WORDS(0x2C);
ShaderProgram ls_program;
INSERT_PADDING_WORDS(0xA4);
ComputeProgram cs_program;
INSERT_PADDING_WORDS(0xA008 - 0x2E00 - 80 - 3 - 5);
DepthRenderControl depth_render_control;
INSERT_PADDING_WORDS(1);
DepthView depth_view;
INSERT_PADDING_WORDS(2);
Address depth_htile_data_base;
INSERT_PADDING_WORDS(2);
float depth_bounds_min;
float depth_bounds_max;
u32 stencil_clear;
float depth_clear;
Scissor screen_scissor;
INSERT_PADDING_WORDS(0xA010 - 0xA00C - 2);
DepthBuffer depth_buffer;
INSERT_PADDING_WORDS(0xA080 - 0xA018);
WindowOffset window_offset;
ViewportScissor window_scissor;
INSERT_PADDING_WORDS(0xA08E - 0xA081 - 2);
ColorBufferMask color_target_mask;
ColorBufferMask color_shader_mask;
ViewportScissor generic_scissor;
INSERT_PADDING_WORDS(2);
std::array<ViewportScissor, NumViewports> viewport_scissors;
std::array<ViewportDepth, NumViewports> viewport_depths;
INSERT_PADDING_WORDS(0xA103 - 0xA0D4);
u32 primitive_restart_index;
INSERT_PADDING_WORDS(1);
BlendConstants blend_constants;
INSERT_PADDING_WORDS(0xA10B - 0xA105 - 4);
StencilControl stencil_control;
StencilRefMask stencil_ref_front;
StencilRefMask stencil_ref_back;
INSERT_PADDING_WORDS(1);
std::array<ViewportBounds, NumViewports> viewports;
std::array<ClipUserData, NumClipPlanes> clip_user_data;
INSERT_PADDING_WORDS(0xA191 - 0xA187);
std::array<PsInputControl, 32> ps_inputs;
VsOutputConfig vs_output_config;
INSERT_PADDING_WORDS(4);
BitField<0, 6, u32> num_interp;
INSERT_PADDING_WORDS(0xA1C3 - 0xA1B6 - 1);
ShaderPosFormat shader_pos_format;
ShaderExportFormat z_export_format;
ColorExportFormat color_export_format;
INSERT_PADDING_WORDS(0xA1E0 - 0xA1C3 - 3);
std::array<BlendControl, NumColorBuffers> blend_control;
INSERT_PADDING_WORDS(0xA1F9 - 0xA1E0 - 8);
IndexBufferBase index_base_address;
INSERT_PADDING_WORDS(1);
u32 draw_initiator;
INSERT_PADDING_WORDS(0xA200 - 0xA1F9 - 4);
DepthControl depth_control;
INSERT_PADDING_WORDS(1);
ColorControl color_control;
DepthBufferControl depth_buffer_control;
ClipperControl clipper_control;
PolygonControl polygon_control;
ViewportControl viewport_control;
VsOutputControl vs_output_control;
INSERT_PADDING_WORDS(0xA290 - 0xA207 - 1);
GsMode vgt_gs_mode;
INSERT_PADDING_WORDS(1);
ModeControl mode_control;
INSERT_PADDING_WORDS(8);
GsOutPrimitiveType vgt_gs_out_prim_type;
INSERT_PADDING_WORDS(1);
u32 index_size;
u32 max_index_size;
IndexBufferType index_buffer_type;
INSERT_PADDING_WORDS(0xA2A1 - 0xA29E - 2);
u32 enable_primitive_id;
INSERT_PADDING_WORDS(3);
u32 enable_primitive_restart;
INSERT_PADDING_WORDS(0xA2A8 - 0xA2A5 - 1);
u32 vgt_instance_step_rate_0;
u32 vgt_instance_step_rate_1;
INSERT_PADDING_WORDS(0xA2AB - 0xA2A9 - 1);
u32 vgt_esgs_ring_itemsize;
u32 vgt_gsvs_ring_itemsize;
INSERT_PADDING_WORDS(0xA2CE - 0xA2AC - 1);
BitField<0, 11, u32> vgt_gs_max_vert_out;
INSERT_PADDING_WORDS(0xA2D5 - 0xA2CE - 1);
ShaderStageEnable stage_enable;
INSERT_PADDING_WORDS(1);
u32 vgt_gs_vert_itemsize[4];
INSERT_PADDING_WORDS(4);
PolygonOffset poly_offset;
GsInstances vgt_gs_instance_cnt;
StreamOutConfig vgt_strmout_config;
StreamOutBufferConfig vgt_strmout_buffer_config;
INSERT_PADDING_WORDS(0xA2F8 - 0xA2E6 - 1);
AaConfig aa_config;
INSERT_PADDING_WORDS(0xA318 - 0xA2F8 - 1);
ColorBuffer color_buffers[NumColorBuffers];
INSERT_PADDING_WORDS(0xC242 - 0xA390);
PrimitiveType primitive_type;
INSERT_PADDING_WORDS(0xC24C - 0xC243);
u32 num_indices;
VgtNumInstances num_instances;
};
std::array<u32, NumRegs> reg_array{};
const ShaderProgram* ProgramForStage(u32 index) const {
switch (index) {
case 0:
return &ps_program;
case 1:
return &vs_program;
case 2:
return &gs_program;
case 3:
return &es_program;
case 4:
return &hs_program;
case 5:
return &ls_program;
}
return nullptr;
}
void SetDefaults();
};
Regs regs{};
// See for a comment in context reg parsing code
union CbDbExtent {
struct {
u16 width;
u16 height;
};
u32 raw{0u};
[[nodiscard]] bool Valid() const {
return raw != 0;
}
};
std::array<CbDbExtent, NumColorBuffers> last_cb_extent{};
CbDbExtent last_db_extent{};
public:
Liverpool();
~Liverpool();
void SubmitGfx(std::span<const u32> dcb, std::span<const u32> ccb);
void SubmitAsc(u32 vqid, std::span<const u32> acb);
void SubmitDone() noexcept {
std::scoped_lock lk{submit_mutex};
mapped_queues[GfxQueueId].ccb_buffer_offset = 0;
mapped_queues[GfxQueueId].dcb_buffer_offset = 0;
submit_done = true;
submit_cv.notify_one();
}
void WaitGpuIdle() noexcept {
std::unique_lock lk{submit_mutex};
submit_cv.wait(lk, [this] { return num_submits == 0; });
}
bool IsGpuIdle() const {
return num_submits == 0;
}
void SetVoPort(Libraries::VideoOut::VideoOutPort* port) {
vo_port = port;
}
void BindRasterizer(Vulkan::Rasterizer* rasterizer_) {
rasterizer = rasterizer_;
}
void SendCommand(Common::UniqueFunction<void>&& func) {
std::scoped_lock lk{submit_mutex};
command_queue.emplace(std::move(func));
++num_commands;
submit_cv.notify_one();
}
void reserveCopyBufferSpace() {
GpuQueue& gfx_queue = mapped_queues[GfxQueueId];
std::scoped_lock<std::mutex> lk(gfx_queue.m_access);
constexpr size_t GfxReservedSize = 2_MB >> 2;
gfx_queue.ccb_buffer.reserve(GfxReservedSize);
gfx_queue.dcb_buffer.reserve(GfxReservedSize);
}
private:
struct Task {
struct promise_type {
auto get_return_object() {
Task task{};
task.handle = std::coroutine_handle<promise_type>::from_promise(*this);
return task;
}
static constexpr std::suspend_always initial_suspend() noexcept {
// We want the task to be suspended at start
return {};
}
static constexpr std::suspend_always final_suspend() noexcept {
return {};
}
void unhandled_exception() {
try {
std::rethrow_exception(std::current_exception());
} catch (const std::exception& e) {
UNREACHABLE_MSG("Unhandled exception: {}", e.what());
}
}
void return_void() {}
struct empty {};
std::suspend_always yield_value(empty&&) {
return {};
}
};
using Handle = std::coroutine_handle<promise_type>;
Handle handle;
};
std::pair<std::span<const u32>, std::span<const u32>> CopyCmdBuffers(std::span<const u32> dcb,
std::span<const u32> ccb);
Task ProcessGraphics(std::span<const u32> dcb, std::span<const u32> ccb);
Task ProcessCeUpdate(std::span<const u32> ccb);
Task ProcessCompute(std::span<const u32> acb, int vqid);
void Process(std::stop_token stoken);
struct GpuQueue {
std::mutex m_access{};
std::atomic<u32> dcb_buffer_offset;
std::atomic<u32> ccb_buffer_offset;
std::vector<u32> dcb_buffer;
std::vector<u32> ccb_buffer;
std::queue<Task::Handle> submits{};
ComputeProgram cs_state{};
VAddr indirect_args_addr{};
};
std::array<GpuQueue, NumTotalQueues> mapped_queues{};
struct ConstantEngine {
void Reset() {
ce_count = 0;
de_count = 0;
ce_compare_count = 0;
}
[[nodiscard]] u32 Diff() const {
ASSERT_MSG(ce_count >= de_count, "DE counter is ahead of CE");
return ce_count - de_count;
}
u32 ce_compare_count{};
u32 ce_count{};
u32 de_count{};
static std::array<u8, 48_KB> constants_heap;
} cblock{};
Vulkan::Rasterizer* rasterizer{};
Libraries::VideoOut::VideoOutPort* vo_port{};
std::jthread process_thread{};
std::atomic<u32> num_submits{};
std::atomic<u32> num_commands{};
std::atomic<bool> submit_done{};
std::mutex submit_mutex;
std::condition_variable_any submit_cv;
std::queue<Common::UniqueFunction<void>> command_queue{};
};
static_assert(GFX6_3D_REG_INDEX(ps_program) == 0x2C08);
static_assert(GFX6_3D_REG_INDEX(vs_program) == 0x2C48);
static_assert(GFX6_3D_REG_INDEX(vs_program.user_data) == 0x2C4C);
static_assert(GFX6_3D_REG_INDEX(gs_program) == 0x2C88);
static_assert(GFX6_3D_REG_INDEX(es_program) == 0x2CC8);
static_assert(GFX6_3D_REG_INDEX(hs_program) == 0x2D08);
static_assert(GFX6_3D_REG_INDEX(ls_program) == 0x2D48);
static_assert(GFX6_3D_REG_INDEX(cs_program) == 0x2E00);
static_assert(GFX6_3D_REG_INDEX(cs_program.dim_z) == 0x2E03);
static_assert(GFX6_3D_REG_INDEX(cs_program.address_lo) == 0x2E0C);
static_assert(GFX6_3D_REG_INDEX(cs_program.user_data) == 0x2E40);
static_assert(GFX6_3D_REG_INDEX(depth_render_control) == 0xA000);
static_assert(GFX6_3D_REG_INDEX(depth_view) == 0xA002);
static_assert(GFX6_3D_REG_INDEX(depth_htile_data_base) == 0xA005);
static_assert(GFX6_3D_REG_INDEX(screen_scissor) == 0xA00C);
static_assert(GFX6_3D_REG_INDEX(depth_buffer.z_info) == 0xA010);
static_assert(GFX6_3D_REG_INDEX(depth_buffer.depth_slice) == 0xA017);
static_assert(GFX6_3D_REG_INDEX(window_offset) == 0xA080);
static_assert(GFX6_3D_REG_INDEX(window_scissor) == 0xA081);
static_assert(GFX6_3D_REG_INDEX(color_target_mask) == 0xA08E);
static_assert(GFX6_3D_REG_INDEX(color_shader_mask) == 0xA08F);
static_assert(GFX6_3D_REG_INDEX(generic_scissor) == 0xA090);
static_assert(GFX6_3D_REG_INDEX(viewport_scissors) == 0xA094);
static_assert(GFX6_3D_REG_INDEX(primitive_restart_index) == 0xA103);
static_assert(GFX6_3D_REG_INDEX(stencil_control) == 0xA10B);
static_assert(GFX6_3D_REG_INDEX(viewports) == 0xA10F);
static_assert(GFX6_3D_REG_INDEX(clip_user_data) == 0xA16F);
static_assert(GFX6_3D_REG_INDEX(ps_inputs) == 0xA191);
static_assert(GFX6_3D_REG_INDEX(vs_output_config) == 0xA1B1);
static_assert(GFX6_3D_REG_INDEX(num_interp) == 0xA1B6);
static_assert(GFX6_3D_REG_INDEX(shader_pos_format) == 0xA1C3);
static_assert(GFX6_3D_REG_INDEX(z_export_format) == 0xA1C4);
static_assert(GFX6_3D_REG_INDEX(color_export_format) == 0xA1C5);
static_assert(GFX6_3D_REG_INDEX(blend_control) == 0xA1E0);
static_assert(GFX6_3D_REG_INDEX(index_base_address) == 0xA1F9);
static_assert(GFX6_3D_REG_INDEX(draw_initiator) == 0xA1FC);
static_assert(GFX6_3D_REG_INDEX(depth_control) == 0xA200);
static_assert(GFX6_3D_REG_INDEX(color_control) == 0xA202);
static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
static_assert(GFX6_3D_REG_INDEX(vgt_gs_mode) == 0xA290);
static_assert(GFX6_3D_REG_INDEX(mode_control) == 0xA292);
static_assert(GFX6_3D_REG_INDEX(vgt_gs_out_prim_type) == 0xA29B);
static_assert(GFX6_3D_REG_INDEX(index_size) == 0xA29D);
static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
static_assert(GFX6_3D_REG_INDEX(enable_primitive_restart) == 0xA2A5);
static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_0) == 0xA2A8);
static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_1) == 0xA2A9);
static_assert(GFX6_3D_REG_INDEX(vgt_esgs_ring_itemsize) == 0xA2AB);
static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_itemsize) == 0xA2AC);
static_assert(GFX6_3D_REG_INDEX(vgt_gs_max_vert_out) == 0xA2CE);
static_assert(GFX6_3D_REG_INDEX(stage_enable) == 0xA2D5);
static_assert(GFX6_3D_REG_INDEX(vgt_gs_vert_itemsize[0]) == 0xA2D7);
static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
static_assert(GFX6_3D_REG_INDEX(vgt_gs_instance_cnt) == 0xA2E4);
static_assert(GFX6_3D_REG_INDEX(vgt_strmout_config) == 0xA2E5);
static_assert(GFX6_3D_REG_INDEX(vgt_strmout_buffer_config) == 0xA2E6);
static_assert(GFX6_3D_REG_INDEX(aa_config) == 0xA2F8);
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
static_assert(GFX6_3D_REG_INDEX(color_buffers[7].base_address) == 0xA381);
static_assert(GFX6_3D_REG_INDEX(primitive_type) == 0xC242);
static_assert(GFX6_3D_REG_INDEX(num_instances) == 0xC24D);
#undef GFX6_3D_REG_INDEX
} // namespace AmdGpu
| 45,153
|
C++
|
.h
| 1,248
| 26.78125
| 100
| 0.574818
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,938
|
pixel_format.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/pixel_format.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string_view>
#include <fmt/format.h>
#include "common/types.h"
#include "video_core/amdgpu/types.h"
namespace AmdGpu {
[[nodiscard]] constexpr bool IsInteger(NumberFormat nfmt) {
return nfmt == AmdGpu::NumberFormat::Sint || nfmt == AmdGpu::NumberFormat::Uint;
}
[[nodiscard]] std::string_view NameOf(DataFormat fmt);
[[nodiscard]] std::string_view NameOf(NumberFormat fmt);
int NumComponents(DataFormat format);
int NumBits(DataFormat format);
u32 ComponentBits(DataFormat format, u32 comp);
s32 ComponentOffset(DataFormat format, u32 comp);
} // namespace AmdGpu
template <>
struct fmt::formatter<AmdGpu::DataFormat> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(AmdGpu::DataFormat fmt, format_context& ctx) const {
return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(fmt));
}
};
template <>
struct fmt::formatter<AmdGpu::NumberFormat> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(AmdGpu::NumberFormat fmt, format_context& ctx) const {
return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(fmt));
}
};
| 1,298
|
C++
|
.h
| 36
| 32.916667
| 84
| 0.723863
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,939
|
types.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/types.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace AmdGpu {
enum class FpRoundMode : u32 {
NearestEven = 0,
PlusInf = 1,
MinInf = 2,
ToZero = 3,
};
enum class FpDenormMode : u32 {
InOutFlush = 0,
InAllowOutFlush = 1,
InFlushOutAllow = 2,
InOutAllow = 3,
};
// See `VGT_PRIMITIVE_TYPE` description in [Radeon Sea Islands 3D/Compute Register Reference Guide]
enum class PrimitiveType : u32 {
None = 0,
PointList = 1,
LineList = 2,
LineStrip = 3,
TriangleList = 4,
TriangleFan = 5,
TriangleStrip = 6,
PatchPrimitive = 9,
AdjLineList = 10,
AdjLineStrip = 11,
AdjTriangleList = 12,
AdjTriangleStrip = 13,
RectList = 17,
LineLoop = 18,
QuadList = 19,
QuadStrip = 20,
Polygon = 21,
};
enum class GsOutputPrimitiveType : u32 {
PointList = 0,
LineStrip = 1,
TriangleStrip = 2,
};
// Table 8.13 Data and Image Formats [Sea Islands Series Instruction Set Architecture]
enum class DataFormat : u32 {
FormatInvalid = 0,
Format8 = 1,
Format16 = 2,
Format8_8 = 3,
Format32 = 4,
Format16_16 = 5,
Format10_11_11 = 6,
Format11_11_10 = 7,
Format10_10_10_2 = 8,
Format2_10_10_10 = 9,
Format8_8_8_8 = 10,
Format32_32 = 11,
Format16_16_16_16 = 12,
Format32_32_32 = 13,
Format32_32_32_32 = 14,
Format5_6_5 = 16,
Format1_5_5_5 = 17,
Format5_5_5_1 = 18,
Format4_4_4_4 = 19,
Format8_24 = 20,
Format24_8 = 21,
FormatX24_8_32 = 22,
FormatGB_GR = 32,
FormatBG_RG = 33,
Format5_9_9_9 = 34,
FormatBc1 = 35,
FormatBc2 = 36,
FormatBc3 = 37,
FormatBc4 = 38,
FormatBc5 = 39,
FormatBc6 = 40,
FormatBc7 = 41,
FormatFmask8_1 = 47,
FormatFmask8_2 = 48,
FormatFmask8_4 = 49,
FormatFmask16_1 = 50,
FormatFmask16_2 = 51,
FormatFmask32_2 = 52,
FormatFmask32_4 = 53,
FormatFmask32_8 = 54,
FormatFmask64_4 = 55,
FormatFmask64_8 = 56,
Format4_4 = 57,
Format6_5_5 = 58,
Format1 = 59,
Format1_Reversed = 60,
Format32_As_8 = 61,
Format32_As_8_8 = 62,
Format32_As_32_32_32_32 = 63,
};
enum class NumberFormat : u32 {
Unorm = 0,
Snorm = 1,
Uscaled = 2,
Sscaled = 3,
Uint = 4,
Sint = 5,
SnormNz = 6,
Float = 7,
Srgb = 9,
Ubnorm = 10,
UbnromNz = 11,
Ubint = 12,
Ubscaled = 13,
};
} // namespace AmdGpu
| 2,529
|
C++
|
.h
| 110
| 18.627273
| 99
| 0.619344
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,940
|
pm4_opcodes.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/pm4_opcodes.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace AmdGpu {
enum class PM4ItOpcode : u32 {
Nop = 0x10,
SetBase = 0x11,
ClearState = 0x12,
IndexBufferSize = 0x13,
DispatchDirect = 0x15,
DispatchIndirect = 0x16,
AtomicGds = 0x1D,
Atomic = 0x1E,
OcclusionQuery = 0x1F,
SetPredication = 0x20,
RegRmw = 0x21,
CondExec = 0x22,
PredExec = 0x23,
DrawIndirect = 0x24,
DrawIndexIndirect = 0x25,
IndexBase = 0x26,
DrawIndex2 = 0x27,
ContextControl = 0x28,
IndexType = 0x2A,
DrawIndirectMulti = 0x2C,
DrawIndexAuto = 0x2D,
NumInstances = 0x2F,
DrawIndexMultiAuto = 0x30,
IndirectBufferConst = 0x33,
StrmoutBufferUpdate = 0x34,
DrawIndexOffset2 = 0x35,
WriteData = 0x37,
DrawIndexIndirectMulti = 0x38,
MemSemaphore = 0x39,
WaitRegMem = 0x3c,
IndirectBuffer = 0x3F,
CondIndirectBuffer = 0x3F,
CopyData = 0x40,
CommandProcessorDma = 0x41,
PfpSyncMe = 0x42,
SurfaceSync = 0x43,
CondWrite = 0x45,
EventWrite = 0x46,
EventWriteEop = 0x47,
EventWriteEos = 0x48,
ReleaseMem = 0x49,
PreambleCntl = 0x4A,
DmaData = 0x50,
ContextRegRmw = 0x51,
AcquireMem = 0x58,
Rewind = 0x59,
LoadShReg = 0x5F,
LoadConfigReg = 0x60,
LoadContextReg = 0x61,
SetConfigReg = 0x68,
SetContextReg = 0x69,
SetContextRegIndirect = 0x73,
SetShReg = 0x76,
SetShRegOffset = 0x77,
SetQueueReg = 0x78,
SetUconfigReg = 0x79,
LoadConstRam = 0x80,
WriteConstRam = 0x81,
DumpConstRam = 0x83,
IncrementCeCounter = 0x84,
IncrementDeCounter = 0x85,
WaitOnCeCounter = 0x86,
WaitOnDeCounterDiff = 0x88,
};
} // namespace AmdGpu
| 1,835
|
C++
|
.h
| 71
| 21.225352
| 66
| 0.686754
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,941
|
resource.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/resource.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/alignment.h"
#include "common/assert.h"
#include "common/bit_field.h"
#include "common/types.h"
#include "video_core/amdgpu/pixel_format.h"
namespace AmdGpu {
enum class CompSwizzle : u32 {
Zero = 0,
One = 1,
Red = 4,
Green = 5,
Blue = 6,
Alpha = 7,
};
// Table 8.5 Buffer Resource Descriptor [Sea Islands Series Instruction Set Architecture]
struct Buffer {
u64 base_address : 44;
u64 _padding0 : 4;
u64 stride : 14;
u64 cache_swizzle : 1;
u64 swizzle_enable : 1;
u32 num_records;
u32 dst_sel_x : 3;
u32 dst_sel_y : 3;
u32 dst_sel_z : 3;
u32 dst_sel_w : 3;
u32 num_format : 3;
u32 data_format : 4;
u32 element_size : 2;
u32 index_stride : 2;
u32 add_tid_enable : 1;
u32 _padding1 : 6;
u32 type : 2; // overlaps with T# type, so should be 0 for buffer
bool Valid() const {
return type == 0u;
}
operator bool() const noexcept {
return base_address != 0;
}
bool operator==(const Buffer& other) const noexcept {
return std::memcmp(this, &other, sizeof(Buffer)) == 0;
}
CompSwizzle GetSwizzle(u32 comp) const noexcept {
const std::array select{dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w};
return static_cast<CompSwizzle>(select[comp]);
}
NumberFormat GetNumberFmt() const noexcept {
return static_cast<NumberFormat>(num_format);
}
DataFormat GetDataFmt() const noexcept {
return static_cast<DataFormat>(data_format);
}
u32 GetStride() const noexcept {
return stride;
}
u32 NumDwords() const noexcept {
return Common::AlignUp(GetSize(), sizeof(u32)) >> 2;
}
u32 GetSize() const noexcept {
return stride == 0 ? num_records : (stride * num_records);
}
};
static_assert(sizeof(Buffer) == 16); // 128bits
enum class ImageType : u64 {
Invalid = 0,
Color1D = 8,
Color2D = 9,
Color3D = 10,
Cube = 11,
Color1DArray = 12,
Color2DArray = 13,
Color2DMsaa = 14,
Color2DMsaaArray = 15,
};
constexpr std::string_view NameOf(ImageType type) {
switch (type) {
case ImageType::Invalid:
return "Invalid";
case ImageType::Color1D:
return "Color1D";
case ImageType::Color2D:
return "Color2D";
case ImageType::Color3D:
return "Color3D";
case ImageType::Cube:
return "Cube";
case ImageType::Color1DArray:
return "Color1DArray";
case ImageType::Color2DArray:
return "Color2DArray";
case ImageType::Color2DMsaa:
return "Color2DMsaa";
case ImageType::Color2DMsaaArray:
return "Color2DMsaaArray";
default:
return "Unknown";
}
}
enum class TilingMode : u32 {
Depth_MacroTiled = 0u,
Display_Linear = 0x8u,
Display_MacroTiled = 0xAu,
Texture_MicroTiled = 0xDu,
Texture_MacroTiled = 0xEu,
};
constexpr std::string_view NameOf(TilingMode type) {
switch (type) {
case TilingMode::Depth_MacroTiled:
return "Depth_MacroTiled";
case TilingMode::Display_Linear:
return "Display_Linear";
case TilingMode::Display_MacroTiled:
return "Display_MacroTiled";
case TilingMode::Texture_MicroTiled:
return "Texture_MicroTiled";
case TilingMode::Texture_MacroTiled:
return "Texture_MacroTiled";
default:
return "Unknown";
}
}
struct Image {
u64 base_address : 38;
u64 mtype_l2 : 2;
u64 min_lod : 12;
u64 data_format : 6;
u64 num_format : 4;
u64 mtype : 2;
u64 width : 14;
u64 height : 14;
u64 perf_modulation : 3;
u64 interlaced : 1;
u64 dst_sel_x : 3;
u64 dst_sel_y : 3;
u64 dst_sel_z : 3;
u64 dst_sel_w : 3;
u64 base_level : 4;
u64 last_level : 4;
u64 tiling_index : 5;
u64 pow2pad : 1;
u64 mtype2 : 1;
u64 atc : 1;
u64 type : 4; // overlaps with V# type, so shouldn't be 0 for buffer
u64 depth : 13;
u64 pitch : 14;
u64 : 5;
u64 base_array : 13;
u64 last_array : 13;
u64 : 6;
u64 min_lod_warn : 12;
u64 counter_bank_id : 8;
u64 lod_hw_cnt_en : 1;
u64 : 43;
static constexpr Image Null() {
Image image{};
image.data_format = u64(DataFormat::Format8_8_8_8);
image.dst_sel_x = 4;
image.dst_sel_y = 5;
image.dst_sel_z = 6;
image.dst_sel_w = 7;
image.tiling_index = u64(TilingMode::Texture_MicroTiled);
image.type = u64(ImageType::Color2D);
return image;
}
bool Valid() const {
return (type & 0x8u) != 0;
}
VAddr Address() const {
return base_address << 8;
}
operator bool() const noexcept {
return base_address != 0;
}
u32 DstSelect() const {
return dst_sel_x | (dst_sel_y << 3) | (dst_sel_z << 6) | (dst_sel_w << 9);
}
static char SelectComp(u32 sel) {
switch (sel) {
case 0:
return '0';
case 1:
return '1';
case 4:
return 'R';
case 5:
return 'G';
case 6:
return 'B';
case 7:
return 'A';
default:
UNREACHABLE();
}
}
std::string DstSelectName() const {
std::string result = "[";
u32 dst_sel = DstSelect();
for (u32 i = 0; i < 4; i++) {
result += SelectComp(dst_sel & 7);
dst_sel >>= 3;
}
result += ']';
return result;
}
u32 Pitch() const {
return pitch + 1;
}
u32 NumLayers(bool is_array) const {
u32 slices = GetType() == ImageType::Color3D ? 1 : depth + 1;
if (GetType() == ImageType::Cube) {
if (is_array) {
slices = last_array + 1;
ASSERT(slices % 6 == 0);
} else {
slices = 6;
}
}
if (pow2pad) {
slices = std::bit_ceil(slices);
}
return slices;
}
u32 NumLevels() const {
if (GetType() == ImageType::Color2DMsaa || GetType() == ImageType::Color2DMsaaArray) {
return 1;
}
return last_level + 1;
}
u32 NumSamples() const {
if (GetType() == ImageType::Color2DMsaa || GetType() == ImageType::Color2DMsaaArray) {
return 1u << last_level;
}
return 1;
}
ImageType GetType() const noexcept {
return static_cast<ImageType>(type);
}
DataFormat GetDataFmt() const noexcept {
return static_cast<DataFormat>(data_format);
}
NumberFormat GetNumberFmt() const noexcept {
return static_cast<NumberFormat>(num_format);
}
TilingMode GetTilingMode() const {
if (tiling_index >= 0 && tiling_index <= 7) {
return tiling_index == 5 ? TilingMode::Texture_MicroTiled
: TilingMode::Depth_MacroTiled;
}
if (tiling_index == 0x13) {
return TilingMode::Texture_MicroTiled;
}
return static_cast<TilingMode>(tiling_index);
}
bool IsTiled() const {
return GetTilingMode() != TilingMode::Display_Linear;
}
bool IsFmask() const noexcept {
return GetDataFmt() >= DataFormat::FormatFmask8_1 &&
GetDataFmt() <= DataFormat::FormatFmask64_8;
}
bool IsPartialCubemap() const {
const auto viewed_slice = last_array - base_array + 1;
return GetType() == ImageType::Cube && viewed_slice < 6;
}
};
static_assert(sizeof(Image) == 32); // 256bits
// 8.2.7. Image Sampler [RDNA 2 Instruction Set Architecture]
enum class ClampMode : u64 {
Wrap = 0,
Mirror = 1,
ClampLastTexel = 2,
MirrorOnceLastTexel = 3,
ClampHalfBorder = 4,
MirrorOnceHalfBorder = 5,
ClampBorder = 6,
MirrorOnceBorder = 7,
};
enum class AnisoRatio : u64 {
One,
Two,
Four,
Eight,
Sixteen,
};
enum class DepthCompare : u64 {
Never = 0,
Less = 1,
Equal = 2,
LessEqual = 3,
Greater = 4,
NotEqual = 5,
GreaterEqual = 6,
Always = 7,
};
enum class FilterMode : u64 {
Blend = 0,
Min = 1,
Max = 2,
};
enum class Filter : u64 {
Point = 0,
Bilinear = 1,
AnisoPoint = 2,
AnisoLinear = 3,
};
enum class MipFilter : u64 {
None = 0,
Point = 1,
Linear = 2,
};
enum class BorderColor : u64 {
OpaqueBlack = 0,
TransparentBlack = 1,
White = 2,
Custom = 3,
};
// Table 8.12 Sampler Resource Definition
struct Sampler {
union {
u64 raw0;
BitField<0, 3, ClampMode> clamp_x;
BitField<3, 3, ClampMode> clamp_y;
BitField<6, 3, ClampMode> clamp_z;
BitField<9, 3, AnisoRatio> max_aniso;
BitField<12, 3, DepthCompare> depth_compare_func;
BitField<15, 1, u64> force_unnormalized;
BitField<16, 3, u64> aniso_threshold;
BitField<19, 1, u64> mc_coord_trunc;
BitField<20, 1, u64> force_degamma;
BitField<21, 6, u64> aniso_bias;
BitField<27, 1, u64> trunc_coord;
BitField<28, 1, u64> disable_cube_wrap;
BitField<29, 2, FilterMode> filter_mode;
BitField<32, 12, u64> min_lod;
BitField<44, 12, u64> max_lod;
BitField<56, 4, u64> perf_mip;
BitField<60, 4, u64> perf_z;
};
union {
u64 raw1;
BitField<0, 14, u64> lod_bias;
BitField<14, 6, u64> lod_bias_sec;
BitField<20, 2, Filter> xy_mag_filter;
BitField<22, 2, Filter> xy_min_filter;
BitField<24, 2, u64> z_filter;
BitField<26, 2, MipFilter> mip_filter;
BitField<28, 1, u64> mip_point_preclamp;
BitField<29, 1, u64> disable_lsb_ceil;
BitField<30, 2, u64> unused0;
BitField<32, 12, u64> border_color_ptr;
BitField<42, 18, u64> unused1;
BitField<62, 2, BorderColor> border_color_type;
};
operator bool() const noexcept {
return raw0 != 0 || raw1 != 0;
}
bool operator==(const Sampler& other) const noexcept {
return std::memcmp(this, &other, sizeof(Sampler)) == 0;
}
float LodBias() const noexcept {
return static_cast<float>(static_cast<int16_t>((lod_bias.Value() ^ 0x2000u) - 0x2000u)) /
256.0f;
}
float MinLod() const noexcept {
return static_cast<float>(min_lod);
}
float MaxLod() const noexcept {
return static_cast<float>(max_lod);
}
};
} // namespace AmdGpu
template <>
struct fmt::formatter<AmdGpu::ImageType> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(AmdGpu::ImageType type, format_context& ctx) const {
return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(type));
}
};
| 10,940
|
C++
|
.h
| 383
| 22.109661
| 97
| 0.589927
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,942
|
pm4_cmds.h
|
shadps4-emu_shadPS4/src/video_core/amdgpu/pm4_cmds.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <cstring>
#include "common/bit_field.h"
#include "common/rdtsc.h"
#include "common/types.h"
#include "core/platform.h"
#include "video_core/amdgpu/pm4_opcodes.h"
namespace AmdGpu {
/// This enum defines the Shader types supported in PM4 type 3 header
enum class PM4ShaderType : u32 {
ShaderGraphics = 0, ///< Graphics shader
ShaderCompute = 1 ///< Compute shader
};
/// This enum defines the predicate value supported in PM4 type 3 header
enum class PM4Predicate : u32 {
PredDisable = 0, ///< Predicate disabled
PredEnable = 1 ///< Predicate enabled
};
union PM4Type0Header {
u32 raw;
BitField<0, 16, u32> base; ///< DWORD Memory-mapped address
BitField<16, 14, u32> count; ///< Count of DWORDs in the *information* body (N - 1 for N dwords)
BitField<30, 2, u32> type; ///< Packet identifier. It should be 0 for type 0 packets.
u32 NumWords() const {
return count + 1;
}
};
union PM4Type3Header {
static constexpr u32 TYPE = 3;
constexpr PM4Type3Header(PM4ItOpcode code, u32 num_words_min_one,
PM4ShaderType stype = PM4ShaderType::ShaderGraphics,
PM4Predicate pred = PM4Predicate::PredDisable) {
raw = 0;
predicate.Assign(pred);
shader_type.Assign(stype);
opcode.Assign(code);
count.Assign(num_words_min_one);
type.Assign(3);
}
u32 NumWords() const {
return count + 1;
}
u32 raw;
BitField<0, 1, PM4Predicate> predicate; ///< Predicated version of packet when set
BitField<1, 1, PM4ShaderType> shader_type; ///< 0: Graphics, 1: Compute Shader
BitField<8, 8, PM4ItOpcode> opcode; ///< IT opcode
BitField<16, 14, u32> count; ///< Number of DWORDs - 1 in the information body.
BitField<30, 2, u32> type; ///< Packet identifier. It should be 3 for type 3 packets
};
union PM4Header {
u32 raw;
PM4Type0Header type0;
PM4Type3Header type3;
BitField<30, 2, u32> type;
};
// Write the PM4 header
template <PM4ItOpcode opcode>
constexpr u32* WriteHeader(u32* cmdbuf, u32 size,
PM4ShaderType type = PM4ShaderType::ShaderGraphics,
PM4Predicate predicate = PM4Predicate::PredDisable) {
PM4Type3Header header{opcode, size - 1, type, predicate};
std::memcpy(cmdbuf, &header, sizeof(header));
return ++cmdbuf;
}
// Write arguments
template <typename... Args>
constexpr u32* WriteBody(u32* cmdbuf, Args... data) {
const std::array<u32, sizeof...(Args)> args{data...};
std::memcpy(cmdbuf, args.data(), sizeof(args));
cmdbuf += args.size();
return cmdbuf;
}
template <PM4ItOpcode opcode, typename... Args>
constexpr u32* WritePacket(u32* cmdbuf, PM4ShaderType type, Args... data) {
cmdbuf = WriteHeader<opcode>(cmdbuf, sizeof...(Args), type);
cmdbuf = WriteBody(cmdbuf, data...);
return cmdbuf;
}
union ContextControlEnable {
u32 raw;
BitField<0, 1, u32> enable_single_cntx_config_reg; ///< single context config reg
BitField<1, 1, u32> enable_multi_cntx_render_reg; ///< multi context render state reg
BitField<15, 1, u32> enable_user_config_reg__CI; ///< User Config Reg on CI(reserved for SI)
BitField<16, 1, u32> enable_gfx_sh_reg; ///< Gfx SH Registers
BitField<24, 1, u32> enable_cs_sh_reg; ///< CS SH Registers
BitField<31, 1, u32> enable_dw; ///< DW enable
};
struct PM4CmdContextControl {
PM4Type3Header header;
ContextControlEnable load_control; ///< Enable bits for loading
ContextControlEnable shadow_enable; ///< Enable bits for shadowing
};
union LoadAddressHigh {
u32 raw;
BitField<0, 16, u32>
addr_hi; ///< bits for the block in Memory from where the CP will fetch the state
BitField<31, 1, u32>
wait_idle; ///< if set the CP will wait for the graphics pipe to be idle by writing
///< to the GRBM Wait Until register with "Wait for 3D idle"
};
/**
* PM4CMDLOADDATA can be used with the following opcodes
* - IT_LOAD_CONFIG_REG
* - IT_LOAD_CONTEXT_REG
* - IT_LOAD_SH_REG
*/
struct PM4CmdLoadData {
PM4Type3Header header;
u32 addr_lo; ///< low 32 address bits for the block in memory from where the CP will fetch the
///< state
LoadAddressHigh addr_hi;
u32 reg_offset; ///< offset in DWords from the register base address
u32 num_dwords; ///< number of DWords that the CP will fetch and write into the chip. A value of
///< zero will fetch nothing
};
enum class LoadDataIndex : u32 {
DirectAddress = 0, /// ADDR_LO is direct address
Offset = 1, /// ARRD_LO is ignored and memory offset is in addrOffset
};
enum class LoadDataFormat : u32 {
OffsetAndSize = 0, /// Data is consecutive DWORDs
OffsetAndData = 1, /// Register offset and data is interleaved
};
union LoadAddressLow {
u32 raw;
BitField<0, 1, LoadDataIndex> index;
BitField<2, 30, u32> addr_lo; ///< bits for the block in Memory from where the CP will fetch the
///< state. DWORD aligned
};
/**
* PM4CMDLOADDATAINDEX can be used with the following opcodes (VI+)
* - IT_LOAD_CONTEXT_REG_INDEX
* - IT_LOAD_SH_REG_INDEX
*/
struct PM4CmdLoadDataIndex {
PM4Type3Header header;
LoadAddressLow addr_lo; ///< low 32 address bits for the block in memory from where the CP will
///< fetch the state
u32 addr_offset; ///< addrLo.index = 1 Indexed mode
union {
BitField<0, 16, u32> reg_offset; ///< offset in DWords from the register base address
BitField<31, 1, LoadDataFormat> data_format;
u32 raw;
};
u32 num_dwords; ///< Number of DWords that the CP will fetch and write
///< into the chip. A value of zero will fetch nothing
};
/**
* PM4CMDSETDATA can be used with the following opcodes:
*
* - IT_SET_CONFIG_REG
* - IT_SET_CONTEXT_REG
* - IT_SET_CONTEXT_REG_INDIRECT
* - IT_SET_SH_REG
* - IT_SET_SH_REG_INDEX
* - IT_SET_UCONFIG_REG
*/
struct PM4CmdSetData {
PM4Type3Header header;
union {
u32 raw;
BitField<0, 16, u32> reg_offset; ///< Offset in DWords from the register base address
BitField<28, 4, u32> index; ///< Index for UCONFIG/CONTEXT on CI+
///< Program to zero for other opcodes and on SI
};
u32 data[0];
[[nodiscard]] u32 Size() const {
return header.count << 2u;
}
template <PM4ShaderType type = PM4ShaderType::ShaderGraphics, typename... Args>
static constexpr u32* SetContextReg(u32* cmdbuf, Args... data) {
return WritePacket<PM4ItOpcode::SetContextReg>(cmdbuf, type, data...);
}
template <PM4ShaderType type = PM4ShaderType::ShaderGraphics, typename... Args>
static constexpr u32* SetShReg(u32* cmdbuf, Args... data) {
return WritePacket<PM4ItOpcode::SetShReg>(cmdbuf, type, data...);
}
};
struct PM4CmdNop {
PM4Type3Header header;
u32 data_block[0];
enum PayloadType : u32 {
DebugMarkerPush = 0x68750001u, ///< Begin of GPU event scope
DebugMarkerPop = 0x68750002u, ///< End of GPU event scope
DebugSetMarker = 0x68750003u, ///< Set GPU event marker
SetVsharpInUdata = 0x68750004u, ///< Indicates that V# will be set in the next packet
SetTsharpInUdata = 0x68750005u, ///< Indicates that T# will be set in the next packet
SetSsharpInUdata = 0x68750006u, ///< Indicates that S# will be set in the next packet
DebugColorMarkerPush = 0x6875000eu, ///< Begin of GPU event scope with color
PatchedFlip = 0x68750776u, ///< Patched flip marker
PrepareFlip = 0x68750777u, ///< Flip marker
PrepareFlipLabel = 0x68750778u, ///< Flip marker with label address
PrepareFlipInterrupt = 0x68750780u, ///< Flip marker with interrupt
PrepareFlipInterruptLabel = 0x68750781u, ///< Flip marker with interrupt and label
};
};
struct PM4CmdDrawIndexOffset2 {
PM4Type3Header header;
u32 max_size; ///< Maximum number of indices
u32 index_offset; ///< Zero based starting index number in the index buffer
u32 index_count; ///< number of indices in the Index Buffer
u32 draw_initiator; ///< draw Initiator Register
};
struct PM4CmdDrawIndex2 {
PM4Type3Header header;
u32 max_size; ///< maximum number of indices
u32 index_base_lo; ///< base Address Lo [31:1] of Index Buffer
///< (Word-Aligned). Written to the VGT_DMA_BASE register.
u32 index_base_hi; ///< base Address Hi [39:32] of Index Buffer.
///< Written to the VGT_DMA_BASE_HI register
u32 index_count; ///< number of indices in the Index Buffer.
///< Written to the VGT_NUM_INDICES register.
u32 draw_initiator; ///< written to the VGT_DRAW_INITIATOR register
};
struct PM4CmdDrawIndexType {
PM4Type3Header header;
union {
u32 raw;
BitField<0, 2, u32> index_type; ///< Select 16 Vs 32bit index
BitField<2, 2, u32> swap_mode; ///< DMA swap mode
};
};
struct PM4CmdDrawIndexAuto {
PM4Type3Header header;
u32 index_count;
u32 draw_initiator;
};
enum class DataSelect : u32 {
None = 0,
Data32Low = 1,
Data64 = 2,
GpuClock64 = 3,
PerfCounter = 4,
};
enum class InterruptSelect : u32 {
None = 0,
IrqOnly = 1,
IrqWhenWriteConfirm = 2,
IrqUndocumented = 3,
};
static u64 GetGpuClock64() {
auto now = std::chrono::high_resolution_clock::now();
auto duration = now.time_since_epoch();
auto ticks = std::chrono::duration_cast<std::chrono::nanoseconds>(duration).count();
return static_cast<u64>(ticks);
}
struct PM4CmdEventWriteEop {
PM4Type3Header header;
union {
u32 event_control;
BitField<0, 6, u32> event_type; ///< Event type written to VGT_EVENT_INITIATOR
BitField<8, 4, u32> event_index; ///< Event index
};
u32 address_lo;
union {
u32 data_control;
BitField<0, 16, u32> address_hi; ///< High bits of address
BitField<24, 2, InterruptSelect> int_sel; ///< Selects interrupt action for end-of-pipe
BitField<29, 3, DataSelect> data_sel; ///< Selects source of data
};
u32 data_lo; ///< Value that will be written to memory when event occurs
u32 data_hi; ///< Value that will be written to memory when event occurs
template <typename T>
T* Address() const {
return reinterpret_cast<T*>(address_lo | u64(address_hi) << 32);
}
u32 DataDWord() const {
return data_lo;
}
u64 DataQWord() const {
return data_lo | u64(data_hi) << 32;
}
void SignalFence(auto&& write_mem) const {
u32* address = Address<u32>();
switch (data_sel.Value()) {
case DataSelect::None: {
break;
}
case DataSelect::Data32Low: {
write_mem(address, DataDWord(), sizeof(u32));
break;
}
case DataSelect::Data64: {
write_mem(address, DataQWord(), sizeof(u64));
break;
}
case DataSelect::GpuClock64: {
write_mem(address, GetGpuClock64(), sizeof(u64));
break;
}
case DataSelect::PerfCounter: {
write_mem(address, Common::FencedRDTSC(), sizeof(u64));
break;
}
default: {
UNREACHABLE();
}
}
switch (int_sel.Value()) {
case InterruptSelect::None: {
// No interrupt
break;
}
case InterruptSelect::IrqOnly:
ASSERT(data_sel == DataSelect::None);
[[fallthrough]];
case InterruptSelect::IrqWhenWriteConfirm: {
Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxEop);
break;
}
default: {
UNREACHABLE();
}
}
}
};
struct PM4CmdAcquireMem {
PM4Type3Header header;
u32 cp_coher_cntl;
u32 cp_coher_size_lo;
u32 cp_coher_size_hi;
u32 cp_coher_base_lo;
u32 cp_coher_base_hi;
u32 poll_interval;
};
enum class DmaDataDst : u32 {
Memory = 0,
Gds = 1,
};
enum class DmaDataSrc : u32 {
Memory = 0,
Gds = 1,
Data = 2,
};
struct PM4DmaData {
PM4Type3Header header;
union {
BitField<0, 1, u32> engine;
BitField<12, 1, u32> src_atc;
BitField<13, 2, u32> src_cache_policy;
BitField<15, 1, u32> src_volatile;
BitField<20, 2, DmaDataDst> dst_sel;
BitField<24, 1, u32> dst_atc;
BitField<25, 2, u32> dst_cache_policy;
BitField<27, 1, u32> dst_volatile;
BitField<29, 2, DmaDataSrc> src_sel;
BitField<31, 1, u32> cp_sync;
};
union {
u32 src_addr_lo;
u32 data;
};
u32 src_addr_hi;
u32 dst_addr_lo;
u32 dst_addr_hi;
u32 command;
template <typename T>
T SrcAddress() const {
return std::bit_cast<T>(src_addr_lo | u64(src_addr_hi) << 32);
}
template <typename T>
T DstAddress() const {
return std::bit_cast<T>(dst_addr_lo | u64(dst_addr_hi) << 32);
}
u32 NumBytes() const noexcept {
return command & 0x1fffff;
}
};
struct PM4CmdWaitRegMem {
enum class Engine : u32 { Me = 0u, Pfp = 1u };
enum class MemSpace : u32 { Register = 0u, Memory = 1u };
enum class Function : u32 {
Always = 0u,
LessThan = 1u,
LessThanEqual = 2u,
Equal = 3u,
NotEqual = 4u,
GreaterThanEqual = 5u,
GreaterThan = 6u,
Reserved = 7u
};
PM4Type3Header header;
union {
BitField<0, 3, Function> function;
BitField<4, 1, MemSpace> mem_space;
BitField<8, 1, Engine> engine;
u32 raw;
};
u32 poll_addr_lo;
u32 poll_addr_hi;
u32 ref;
u32 mask;
u32 poll_interval;
template <typename T = u32*>
T Address() const {
return std::bit_cast<T>((uintptr_t(poll_addr_hi) << 32) | poll_addr_lo);
}
bool Test() const {
switch (function.Value()) {
case Function::Always: {
return true;
}
case Function::LessThan: {
return (*Address() & mask) < ref;
}
case Function::LessThanEqual: {
return (*Address() & mask) <= ref;
}
case Function::Equal: {
return (*Address() & mask) == ref;
}
case Function::NotEqual: {
return (*Address() & mask) != ref;
}
case Function::GreaterThanEqual: {
return (*Address() & mask) >= ref;
}
case Function::GreaterThan: {
return (*Address() & mask) > ref;
}
case Function::Reserved:
[[fallthrough]];
default: {
UNREACHABLE();
}
}
}
};
struct PM4CmdWriteData {
PM4Type3Header header;
union {
BitField<8, 11, u32> dst_sel;
BitField<16, 1, u32> wr_one_addr;
BitField<20, 1, u32> wr_confirm;
BitField<30, 1, u32> engine_sel;
u32 raw;
};
union {
struct {
u32 dst_addr_lo;
u32 dst_addr_hi;
};
u64 addr64;
};
u32 data[0];
u32 Size() const {
return (header.count.Value() - 2) * 4;
}
template <typename T>
void Address(T addr) {
addr64 = static_cast<u64>(addr);
}
template <typename T>
T Address() const {
return reinterpret_cast<T>(addr64);
}
};
struct PM4CmdEventWriteEos {
enum class Command : u32 {
GdsStore = 1u,
SignalFence = 2u,
};
PM4Type3Header header;
union {
u32 event_control;
BitField<0, 6, u32> event_type; ///< Event type written to VGT_EVENT_INITIATOR
BitField<8, 4, u32> event_index; ///< Event index
};
u32 address_lo;
union {
u32 cmd_info;
BitField<0, 16, u32> address_hi; ///< High bits of address
BitField<29, 3, Command> command; ///< Command
};
union {
u32 data; ///< Fence value that will be written to memory when event occurs
BitField<0, 16, u32>
gds_index; ///< Indexed offset from the start of the segment within the partition
BitField<16, 16, u32> size; ///< Number of DWs to read from the GDS
};
template <typename T = u32*>
T Address() const {
return reinterpret_cast<T>(address_lo | u64(address_hi) << 32);
}
u32 DataDWord() const {
return this->data;
}
void SignalFence(auto&& write_mem) const {
const auto cmd = command.Value();
switch (cmd) {
case Command::SignalFence: {
write_mem(Address(), DataDWord(), sizeof(u32));
break;
}
case Command::GdsStore: {
break;
}
default: {
UNREACHABLE_MSG("Unknown command {}", u32(cmd));
}
}
}
};
struct PM4WriteConstRam {
PM4Type3Header header;
union {
BitField<0, 16, u32> offset; ///< Starting DW granularity offset into the constant RAM.
///< Thus, bits[1:0] are zero.
u32 dw1;
};
u32 data[0];
[[nodiscard]] u32 Offset() const {
return offset.Value();
}
[[nodiscard]] u32 Size() const {
return header.count << 2u;
}
};
struct PM4DumpConstRam {
PM4Type3Header header;
union {
BitField<0, 16, u32> offset; ///< Starting byte offset into the Constant RAM. The minimum
///< granularity is 4 bytes
u32 dw1;
};
union {
BitField<0, 15, u32>
num_dw; ///< Number of DWs to read from the constant RAM. The minimum granularity is DWs
u32 dw2;
};
u32 addr_lo;
u32 addr_hi;
template <typename T>
T Address() const {
return reinterpret_cast<T>((u64(addr_hi) << 32u) | addr_lo);
}
[[nodiscard]] u32 Offset() const {
return offset.Value();
}
[[nodiscard]] u32 Size() const {
return num_dw.Value() << 2u;
}
};
struct PM4CmdDispatchDirect {
PM4Type3Header header;
u32 dim_x; ///< X dimensions of the array of thread groups to be dispatched
u32 dim_y; ///< Y dimensions of the array of thread groups to be dispatched
u32 dim_z; ///< Z dimensions of the array of thread groups to be dispatched
u32 dispatch_initiator; ///< Dispatch Initiator Register
};
struct PM4CmdDrawNumInstances {
PM4Type3Header header;
u32 num_instances;
};
struct PM4CmdDrawIndexBase {
PM4Type3Header header;
u32 addr_lo;
u32 addr_hi;
};
struct PM4CmdDrawIndexBufferSize {
PM4Type3Header header;
u32 num_indices;
};
struct PM4CmdIndirectBuffer {
PM4Type3Header header;
u32 ibase_lo; ///< Indirect buffer base address, must be 4 byte aligned
union {
BitField<0, 16, u32> ibase_hi; ///< Indirect buffer base address
u32 dw1;
};
union {
BitField<0, 20, u32> ib_size; ///< Indirect buffer size
BitField<20, 1, u32> chain; ///< set to chain to IB allocations
BitField<24, 8, u32> vmid; ///< Virtual memory domain ID for command buffer
u32 dw2;
};
template <typename T>
T* Address() const {
return reinterpret_cast<T*>((u64(ibase_hi) << 32u) | ibase_lo);
}
};
struct PM4CmdReleaseMem {
PM4Type3Header header;
union {
BitField<0, 6, u32> event_type; ///< Event type written to VGT_EVENT_INITIATOR
BitField<8, 4, u32> event_index; ///< Event index
BitField<12, 1, u32> tcl1_vol_action_ena;
BitField<13, 1, u32> tc_vol_action_ena;
BitField<15, 1, u32> tc_wb_action_ena;
BitField<16, 1, u32> tcl1__action_ena;
BitField<17, 1, u32> tc_action_ena;
BitField<25, 2, u32> cache_policy; ///< Cache Policy setting used for writing fences and
///< timestamps to the TCL2
u32 dw1;
};
union {
BitField<16, 2, u32> dst_sel; ///< destination select
BitField<24, 3, InterruptSelect> int_sel; ///< selects interrupt action for end-of-pipe
BitField<29, 3, DataSelect> data_sel; ///< selects source of data
u32 dw2;
};
u32 address_lo; ///< low bits of address
u32 address_hi; ///< high bits of address
union {
struct {
u16 gds_index; ///< Byte offset into GDS to copy from
u16 num_dw; ///< Number of DWORDS of GDS to copy
};
u32 data_lo; ///< value that will be written to memory when event occurs
};
u32 data_hi;
template <typename T>
T* Address() const {
return reinterpret_cast<T*>(address_lo | u64(address_hi) << 32);
}
u32 DataDWord() const {
return data_lo;
}
u64 DataQWord() const {
return data_lo | u64(data_hi) << 32;
}
void SignalFence(Platform::InterruptId irq_id) const {
switch (data_sel.Value()) {
case DataSelect::Data32Low: {
*Address<u32>() = DataDWord();
break;
}
case DataSelect::Data64: {
*Address<u64>() = DataQWord();
break;
}
case DataSelect::GpuClock64: {
*Address<u64>() = GetGpuClock64();
break;
}
case DataSelect::PerfCounter: {
*Address<u64>() = Common::FencedRDTSC();
break;
}
default: {
UNREACHABLE();
}
}
switch (int_sel.Value()) {
case InterruptSelect::None: {
// No interrupt
break;
}
case InterruptSelect::IrqUndocumented:
[[fallthrough]];
case InterruptSelect::IrqWhenWriteConfirm: {
Platform::IrqC::Instance()->Signal(irq_id);
break;
}
default: {
UNREACHABLE();
}
}
}
};
struct PM4CmdSetBase {
enum class BaseIndex : u32 {
DisplayListPatchTable = 0b0000,
DrawIndexIndirPatchTable = 0b0001,
GdsPartition = 0b0010,
CePartition = 0b0011,
};
PM4Type3Header header;
union {
BitField<0, 4, BaseIndex> base_index;
u32 dw1;
};
u32 address0;
u32 address1;
template <typename T>
T Address() const {
ASSERT(base_index == BaseIndex::DisplayListPatchTable ||
base_index == BaseIndex::DrawIndexIndirPatchTable);
return reinterpret_cast<T>(address0 | (u64(address1 & 0xffff) << 32u));
}
};
struct PM4CmdDispatchIndirect {
struct GroupDimensions {
u32 dim_x;
u32 dim_y;
u32 dim_z;
};
PM4Type3Header header;
u32 data_offset; ///< Byte aligned offset where the required data structure starts
u32 dispatch_initiator; ///< Dispatch Initiator Register
};
struct PM4CmdDrawIndirect {
struct DrawInstancedArgs {
u32 vertex_count_per_instance;
u32 instance_count;
u32 start_vertex_location;
u32 start_instance_location;
};
PM4Type3Header header; ///< header
u32 data_offset; ///< Byte aligned offset where the required data structure starts
union {
u32 dw2;
BitField<0, 16, u32> base_vtx_loc; ///< Offset where the CP will write the
///< BaseVertexLocation it fetched from memory
};
union {
u32 dw3;
BitField<0, 16, u32> start_inst_loc; ///< Offset where the CP will write the
///< StartInstanceLocation it fetched from memory
};
u32 draw_initiator; ///< Draw Initiator Register
};
struct PM4CmdDrawIndexIndirect {
struct DrawIndexInstancedArgs {
u32 index_count_per_instance;
u32 instance_count;
u32 start_index_location;
u32 base_vertex_location;
u32 start_instance_location;
};
PM4Type3Header header; ///< header
u32 data_offset; ///< Byte aligned offset where the required data structure starts
union {
u32 dw2;
BitField<0, 16, u32> base_vtx_loc; ///< Offset where the CP will write the
///< BaseVertexLocation it fetched from memory
};
union { // NOTE: this one is undocumented in AMD spec, but Gnm driver writes this field
u32 dw3;
BitField<0, 16, u32> start_inst_loc; ///< Offset where the CP will write the
///< StartInstanceLocation it fetched from memory
};
u32 draw_initiator; ///< Draw Initiator Register
};
} // namespace AmdGpu
| 25,123
|
C++
|
.h
| 737
| 27.02578
| 100
| 0.602634
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,943
|
runtime_info.h
|
shadps4-emu_shadPS4/src/shader_recompiler/runtime_info.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <span>
#include <boost/container/static_vector.hpp>
#include "common/types.h"
#include "video_core/amdgpu/types.h"
namespace Shader {
enum class Stage : u32 {
Fragment,
Vertex,
Geometry,
Export,
Hull,
Local,
Compute,
};
constexpr u32 MaxStageTypes = 6;
[[nodiscard]] constexpr Stage StageFromIndex(size_t index) noexcept {
return static_cast<Stage>(index);
}
struct ExportRuntimeInfo {
u32 vertex_data_size;
auto operator<=>(const ExportRuntimeInfo&) const noexcept = default;
};
enum class VsOutput : u8 {
None,
PointSprite,
EdgeFlag,
KillFlag,
GsCutFlag,
GsMrtIndex,
GsVpIndex,
CullDist0,
CullDist1,
CullDist2,
CullDist3,
CullDist4,
CullDist5,
CullDist6,
CullDist7,
ClipDist0,
ClipDist1,
ClipDist2,
ClipDist3,
ClipDist4,
ClipDist5,
ClipDist6,
ClipDist7,
};
using VsOutputMap = std::array<VsOutput, 4>;
struct VertexRuntimeInfo {
u32 num_outputs;
std::array<VsOutputMap, 3> outputs;
bool emulate_depth_negative_one_to_one{};
bool operator==(const VertexRuntimeInfo& other) const noexcept {
return emulate_depth_negative_one_to_one == other.emulate_depth_negative_one_to_one;
}
};
static constexpr auto GsMaxOutputStreams = 4u;
using GsOutputPrimTypes = std::array<AmdGpu::GsOutputPrimitiveType, GsMaxOutputStreams>;
struct GeometryRuntimeInfo {
u32 num_invocations{};
u32 output_vertices{};
u32 in_vertex_data_size{};
u32 out_vertex_data_size{};
AmdGpu::PrimitiveType in_primitive;
GsOutputPrimTypes out_primitive;
std::span<const u32> vs_copy;
u64 vs_copy_hash;
bool operator==(const GeometryRuntimeInfo& other) const noexcept {
return num_invocations && other.num_invocations &&
output_vertices == other.output_vertices && in_primitive == other.in_primitive &&
std::ranges::equal(out_primitive, other.out_primitive);
}
};
enum class MrtSwizzle : u8 {
Identity = 0,
Alt = 1,
Reverse = 2,
ReverseAlt = 3,
};
static constexpr u32 MaxColorBuffers = 8;
struct FragmentRuntimeInfo {
struct PsInput {
u8 param_index;
bool is_default;
bool is_flat;
u8 default_value;
auto operator<=>(const PsInput&) const noexcept = default;
};
u32 num_inputs;
std::array<PsInput, 32> inputs;
struct PsColorBuffer {
AmdGpu::NumberFormat num_format;
MrtSwizzle mrt_swizzle;
auto operator<=>(const PsColorBuffer&) const noexcept = default;
};
std::array<PsColorBuffer, MaxColorBuffers> color_buffers;
bool operator==(const FragmentRuntimeInfo& other) const noexcept {
return std::ranges::equal(color_buffers, other.color_buffers) &&
num_inputs == other.num_inputs &&
std::ranges::equal(inputs.begin(), inputs.begin() + num_inputs, other.inputs.begin(),
other.inputs.begin() + num_inputs);
}
};
struct ComputeRuntimeInfo {
u32 shared_memory_size;
std::array<u32, 3> workgroup_size;
std::array<bool, 3> tgid_enable;
bool operator==(const ComputeRuntimeInfo& other) const noexcept {
return workgroup_size == other.workgroup_size && tgid_enable == other.tgid_enable;
}
};
/**
* Stores information relevant to shader compilation sourced from liverpool registers.
* It may potentially differ with the same shader module so must be checked.
* It's also possible to store any other custom information that needs to be part of shader key.
*/
struct RuntimeInfo {
Stage stage;
u32 num_user_data;
u32 num_input_vgprs;
u32 num_allocated_vgprs;
AmdGpu::FpDenormMode fp_denorm_mode32;
AmdGpu::FpRoundMode fp_round_mode32;
union {
ExportRuntimeInfo es_info;
VertexRuntimeInfo vs_info;
GeometryRuntimeInfo gs_info;
FragmentRuntimeInfo fs_info;
ComputeRuntimeInfo cs_info;
};
RuntimeInfo(Stage stage_) {
memset(this, 0, sizeof(*this));
stage = stage_;
}
bool operator==(const RuntimeInfo& other) const noexcept {
switch (stage) {
case Stage::Fragment:
return fs_info == other.fs_info;
case Stage::Vertex:
return vs_info == other.vs_info;
case Stage::Compute:
return cs_info == other.cs_info;
case Stage::Export:
return es_info == other.es_info;
case Stage::Geometry:
return gs_info == other.gs_info;
default:
return true;
}
}
};
} // namespace Shader
| 4,787
|
C++
|
.h
| 156
| 25.064103
| 100
| 0.672526
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,944
|
recompiler.h
|
shadps4-emu_shadPS4/src/shader_recompiler/recompiler.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/object_pool.h"
#include "shader_recompiler/ir/basic_block.h"
#include "shader_recompiler/ir/program.h"
namespace Shader {
struct Profile;
struct RuntimeInfo;
struct Pools {
static constexpr u32 InstPoolSize = 8192;
static constexpr u32 BlockPoolSize = 32;
Common::ObjectPool<IR::Inst> inst_pool;
Common::ObjectPool<IR::Block> block_pool;
explicit Pools() : inst_pool{InstPoolSize}, block_pool{BlockPoolSize} {}
void ReleaseContents() {
inst_pool.ReleaseContents();
block_pool.ReleaseContents();
}
};
[[nodiscard]] IR::Program TranslateProgram(std::span<const u32> code, Pools& pools, Info& info,
const RuntimeInfo& runtime_info, const Profile& profile);
} // namespace Shader
| 915
|
C++
|
.h
| 23
| 34.565217
| 100
| 0.714286
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,945
|
info.h
|
shadps4-emu_shadPS4/src/shader_recompiler/info.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <span>
#include <vector>
#include <boost/container/small_vector.hpp>
#include <boost/container/static_vector.hpp>
#include "common/assert.h"
#include "common/types.h"
#include "shader_recompiler/backend/bindings.h"
#include "shader_recompiler/frontend/copy_shader.h"
#include "shader_recompiler/ir/attribute.h"
#include "shader_recompiler/ir/passes/srt.h"
#include "shader_recompiler/ir/reg.h"
#include "shader_recompiler/ir/type.h"
#include "shader_recompiler/params.h"
#include "shader_recompiler/runtime_info.h"
#include "video_core/amdgpu/resource.h"
namespace Shader {
static constexpr size_t NumUserDataRegs = 16;
static constexpr size_t MaxUboSize = 65536;
static constexpr size_t MaxUboDwords = MaxUboSize >> 2;
enum class TextureType : u32 {
Color1D,
ColorArray1D,
Color2D,
ColorArray2D,
Color3D,
ColorCube,
Buffer,
};
constexpr u32 NUM_TEXTURE_TYPES = 7;
struct Info;
struct BufferResource {
u32 sharp_idx;
IR::Type used_types;
AmdGpu::Buffer inline_cbuf;
bool is_gds_buffer{};
bool is_instance_data{};
bool is_written{};
bool IsStorage(AmdGpu::Buffer buffer) const noexcept {
return buffer.GetSize() > MaxUboSize || is_written || is_gds_buffer;
}
constexpr AmdGpu::Buffer GetSharp(const Info& info) const noexcept;
};
using BufferResourceList = boost::container::small_vector<BufferResource, 16>;
struct TextureBufferResource {
u32 sharp_idx;
AmdGpu::NumberFormat nfmt;
bool is_written{};
constexpr AmdGpu::Buffer GetSharp(const Info& info) const noexcept;
};
using TextureBufferResourceList = boost::container::small_vector<TextureBufferResource, 16>;
struct ImageResource {
u32 sharp_idx;
AmdGpu::ImageType type;
AmdGpu::NumberFormat nfmt;
bool is_storage{};
bool is_depth{};
bool is_atomic{};
bool is_array{};
constexpr AmdGpu::Image GetSharp(const Info& info) const noexcept;
};
using ImageResourceList = boost::container::small_vector<ImageResource, 16>;
struct SamplerResource {
u32 sharp_idx;
AmdGpu::Sampler inline_sampler{};
u32 associated_image : 4;
u32 disable_aniso : 1;
constexpr AmdGpu::Sampler GetSharp(const Info& info) const noexcept;
};
using SamplerResourceList = boost::container::small_vector<SamplerResource, 16>;
struct FMaskResource {
u32 sharp_idx;
constexpr AmdGpu::Image GetSharp(const Info& info) const noexcept;
};
using FMaskResourceList = boost::container::small_vector<FMaskResource, 16>;
struct PushData {
static constexpr u32 BufOffsetIndex = 2;
static constexpr u32 UdRegsIndex = 4;
u32 step0;
u32 step1;
std::array<u8, 32> buf_offsets;
std::array<u32, NumUserDataRegs> ud_regs;
void AddOffset(u32 binding, u32 offset) {
ASSERT(offset < 256 && binding < buf_offsets.size());
buf_offsets[binding] = offset;
}
};
static_assert(sizeof(PushData) <= 128,
"PushData size is greater than minimum size guaranteed by Vulkan spec");
/**
* Contains general information generated by the shader recompiler for an input program.
*/
struct Info {
struct VsInput {
enum InstanceIdType : u8 {
None = 0,
OverStepRate0 = 1,
OverStepRate1 = 2,
Plain = 3,
};
AmdGpu::NumberFormat fmt;
u16 binding;
u16 num_components;
u8 sgpr_base;
u8 dword_offset;
InstanceIdType instance_step_rate;
s32 instance_data_buf;
};
boost::container::static_vector<VsInput, 32> vs_inputs{};
struct AttributeFlags {
bool Get(IR::Attribute attrib, u32 comp = 0) const {
return flags[Index(attrib)] & (1 << comp);
}
bool GetAny(IR::Attribute attrib) const {
return flags[Index(attrib)];
}
void Set(IR::Attribute attrib, u32 comp = 0) {
flags[Index(attrib)] |= (1 << comp);
}
u32 NumComponents(IR::Attribute attrib) const {
return 4;
}
static size_t Index(IR::Attribute attrib) {
return static_cast<size_t>(attrib);
}
std::array<u8, IR::NumAttributes> flags;
};
AttributeFlags loads{};
AttributeFlags stores{};
struct UserDataMask {
void Set(IR::ScalarReg reg) noexcept {
mask |= 1 << static_cast<u32>(reg);
}
u32 Index(IR::ScalarReg reg) const noexcept {
const u32 reg_mask = (1 << static_cast<u32>(reg)) - 1;
return std::popcount(mask & reg_mask);
}
u32 NumRegs() const noexcept {
return std::popcount(mask);
}
u32 mask;
};
UserDataMask ud_mask{};
CopyShaderData gs_copy_data;
s8 vertex_offset_sgpr = -1;
s8 instance_offset_sgpr = -1;
BufferResourceList buffers;
TextureBufferResourceList texture_buffers;
ImageResourceList images;
SamplerResourceList samplers;
FMaskResourceList fmasks;
PersistentSrtInfo srt_info;
std::vector<u32> flattened_ud_buf;
std::span<const u32> user_data;
Stage stage;
u64 pgm_hash{};
VAddr pgm_base;
bool has_storage_images{};
bool has_image_buffers{};
bool has_texel_buffers{};
bool has_discard{};
bool has_image_gather{};
bool has_image_query{};
bool uses_lane_id{};
bool uses_group_quad{};
bool uses_group_ballot{};
bool uses_shared{};
bool uses_fp16{};
bool uses_fp64{};
bool uses_step_rates{};
bool translation_failed{}; // indicates that shader has unsupported instructions
bool has_readconst{};
u8 mrt_mask{0u};
explicit Info(Stage stage_, ShaderParams params)
: stage{stage_}, pgm_hash{params.hash}, pgm_base{params.Base()},
user_data{params.user_data} {}
template <typename T>
inline T ReadUdSharp(u32 sharp_idx) const noexcept {
return *reinterpret_cast<const T*>(&flattened_ud_buf[sharp_idx]);
}
template <typename T>
T ReadUdReg(u32 ptr_index, u32 dword_offset) const noexcept {
T data;
const u32* base = user_data.data();
if (ptr_index != IR::NumScalarRegs) {
std::memcpy(&base, &user_data[ptr_index], sizeof(base));
base = reinterpret_cast<const u32*>(VAddr(base) & 0xFFFFFFFFFFFFULL);
}
std::memcpy(&data, base + dword_offset, sizeof(T));
return data;
}
void PushUd(Backend::Bindings& bnd, PushData& push) const {
u32 mask = ud_mask.mask;
while (mask) {
const u32 index = std::countr_zero(mask);
ASSERT(bnd.user_data < NumUserDataRegs && index < NumUserDataRegs);
mask &= ~(1U << index);
push.ud_regs[bnd.user_data++] = user_data[index];
}
}
void AddBindings(Backend::Bindings& bnd) const {
const auto total_buffers =
buffers.size() + texture_buffers.size() + (has_readconst ? 1 : 0);
bnd.buffer += total_buffers;
bnd.unified += total_buffers + images.size() + samplers.size();
bnd.user_data += ud_mask.NumRegs();
}
[[nodiscard]] std::pair<u32, u32> GetDrawOffsets() const {
u32 vertex_offset = 0;
u32 instance_offset = 0;
if (vertex_offset_sgpr != -1) {
vertex_offset = user_data[vertex_offset_sgpr];
}
if (instance_offset_sgpr != -1) {
instance_offset = user_data[instance_offset_sgpr];
}
return {vertex_offset, instance_offset};
}
void RefreshFlatBuf() {
flattened_ud_buf.resize(srt_info.flattened_bufsize_dw);
ASSERT(user_data.size() <= NumUserDataRegs);
std::memcpy(flattened_ud_buf.data(), user_data.data(), user_data.size_bytes());
// Run the JIT program to walk the SRT and write the leaves to a flat buffer
if (srt_info.walker_func) {
srt_info.walker_func(user_data.data(), flattened_ud_buf.data());
}
}
};
constexpr AmdGpu::Buffer BufferResource::GetSharp(const Info& info) const noexcept {
return inline_cbuf ? inline_cbuf : info.ReadUdSharp<AmdGpu::Buffer>(sharp_idx);
}
constexpr AmdGpu::Buffer TextureBufferResource::GetSharp(const Info& info) const noexcept {
return info.ReadUdSharp<AmdGpu::Buffer>(sharp_idx);
}
constexpr AmdGpu::Image ImageResource::GetSharp(const Info& info) const noexcept {
return info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
}
constexpr AmdGpu::Sampler SamplerResource::GetSharp(const Info& info) const noexcept {
return inline_sampler ? inline_sampler : info.ReadUdSharp<AmdGpu::Sampler>(sharp_idx);
}
constexpr AmdGpu::Image FMaskResource::GetSharp(const Info& info) const noexcept {
return info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
}
} // namespace Shader
template <>
struct fmt::formatter<Shader::Stage> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(const Shader::Stage stage, format_context& ctx) const {
constexpr static std::array names = {"fs", "vs", "gs", "es", "hs", "ls", "cs"};
return fmt::format_to(ctx.out(), "{}", names[static_cast<size_t>(stage)]);
}
};
| 9,317
|
C++
|
.h
| 257
| 30.315175
| 92
| 0.664669
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,946
|
profile.h
|
shadps4-emu_shadPS4/src/shader_recompiler/profile.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Shader {
struct Profile {
u32 supported_spirv{0x00010000};
u32 subgroup_size{};
bool unified_descriptor_binding{};
bool support_descriptor_aliasing{};
bool support_int8{};
bool support_int16{};
bool support_int64{};
bool support_vertex_instance_id{};
bool support_float_controls{};
bool support_separate_denorm_behavior{};
bool support_separate_rounding_mode{};
bool support_fp32_denorm_preserve{};
bool support_fp32_denorm_flush{};
bool support_explicit_workgroup_layout{};
bool has_broken_spirv_clamp{};
bool lower_left_origin_mode{};
u64 min_ssbo_alignment{};
};
} // namespace Shader
| 822
|
C++
|
.h
| 25
| 28.96
| 66
| 0.727273
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,947
|
params.h
|
shadps4-emu_shadPS4/src/shader_recompiler/params.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include "common/types.h"
namespace Shader {
/**
* Compilation parameters used to identify and locate a guest shader program.
*/
struct ShaderParams {
static constexpr u32 NumShaderUserData = 16;
std::span<const u32, NumShaderUserData> user_data;
std::span<const u32> code;
u64 hash;
VAddr Base() const noexcept {
return reinterpret_cast<VAddr>(code.data());
}
};
} // namespace Shader
| 568
|
C++
|
.h
| 19
| 26.736842
| 77
| 0.736162
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,948
|
specialization.h
|
shadps4-emu_shadPS4/src/shader_recompiler/specialization.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <bitset>
#include "common/types.h"
#include "shader_recompiler/backend/bindings.h"
#include "shader_recompiler/info.h"
#include "shader_recompiler/ir/passes/srt.h"
namespace Shader {
struct BufferSpecialization {
u16 stride : 14;
u16 is_storage : 1;
auto operator<=>(const BufferSpecialization&) const = default;
};
struct TextureBufferSpecialization {
bool is_integer = false;
auto operator<=>(const TextureBufferSpecialization&) const = default;
};
struct ImageSpecialization {
AmdGpu::ImageType type = AmdGpu::ImageType::Color2D;
bool is_integer = false;
auto operator<=>(const ImageSpecialization&) const = default;
};
struct FMaskSpecialization {
u32 width;
u32 height;
auto operator<=>(const FMaskSpecialization&) const = default;
};
/**
* Alongside runtime information, this structure also checks bound resources
* for compatibility. Can be used as a key for storing shader permutations.
* Is separate from runtime information, because resource layout can only be deduced
* after the first compilation of a module.
*/
struct StageSpecialization {
static constexpr size_t MaxStageResources = 64;
const Shader::Info* info;
RuntimeInfo runtime_info;
std::bitset<MaxStageResources> bitset{};
boost::container::small_vector<BufferSpecialization, 16> buffers;
boost::container::small_vector<TextureBufferSpecialization, 8> tex_buffers;
boost::container::small_vector<ImageSpecialization, 16> images;
boost::container::small_vector<FMaskSpecialization, 8> fmasks;
Backend::Bindings start{};
explicit StageSpecialization(const Shader::Info& info_, RuntimeInfo runtime_info_,
Backend::Bindings start_)
: info{&info_}, runtime_info{runtime_info_}, start{start_} {
u32 binding{};
if (info->has_readconst) {
binding++;
}
ForEachSharp(binding, buffers, info->buffers,
[](auto& spec, const auto& desc, AmdGpu::Buffer sharp) {
spec.stride = sharp.GetStride();
spec.is_storage = desc.IsStorage(sharp);
});
ForEachSharp(binding, tex_buffers, info->texture_buffers,
[](auto& spec, const auto& desc, AmdGpu::Buffer sharp) {
spec.is_integer = AmdGpu::IsInteger(sharp.GetNumberFmt());
});
ForEachSharp(binding, images, info->images,
[](auto& spec, const auto& desc, AmdGpu::Image sharp) {
spec.type = sharp.IsPartialCubemap() ? AmdGpu::ImageType::Color2DArray
: sharp.GetType();
spec.is_integer = AmdGpu::IsInteger(sharp.GetNumberFmt());
});
ForEachSharp(binding, fmasks, info->fmasks,
[](auto& spec, const auto& desc, AmdGpu::Image sharp) {
spec.width = sharp.width;
spec.height = sharp.height;
});
}
void ForEachSharp(u32& binding, auto& spec_list, auto& desc_list, auto&& func) {
for (const auto& desc : desc_list) {
auto& spec = spec_list.emplace_back();
const auto sharp = desc.GetSharp(*info);
if (!sharp) {
binding++;
continue;
}
bitset.set(binding++);
func(spec, desc, sharp);
}
}
bool operator==(const StageSpecialization& other) const {
if (start != other.start) {
return false;
}
if (runtime_info != other.runtime_info) {
return false;
}
u32 binding{};
if (info->has_readconst != other.info->has_readconst) {
return false;
}
if (info->has_readconst) {
binding++;
}
for (u32 i = 0; i < buffers.size(); i++) {
if (other.bitset[binding++] && buffers[i] != other.buffers[i]) {
return false;
}
}
for (u32 i = 0; i < tex_buffers.size(); i++) {
if (other.bitset[binding++] && tex_buffers[i] != other.tex_buffers[i]) {
return false;
}
}
for (u32 i = 0; i < images.size(); i++) {
if (other.bitset[binding++] && images[i] != other.images[i]) {
return false;
}
}
for (u32 i = 0; i < fmasks.size(); i++) {
if (other.bitset[binding++] && fmasks[i] != other.fmasks[i]) {
return false;
}
}
return true;
}
};
} // namespace Shader
| 4,859
|
C++
|
.h
| 122
| 29.704918
| 95
| 0.574486
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,949
|
exception.h
|
shadps4-emu_shadPS4/src/shader_recompiler/exception.h
|
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <exception>
#include <string>
#include <utility>
#include <fmt/format.h>
namespace Shader {
class Exception : public std::exception {
public:
explicit Exception(std::string message) noexcept : err_message{std::move(message)} {}
[[nodiscard]] const char* what() const noexcept override {
return err_message.c_str();
}
void Prepend(std::string_view prepend) {
err_message.insert(0, prepend);
}
void Append(std::string_view append) {
err_message += append;
}
private:
std::string err_message;
};
class LogicError : public Exception {
public:
template <typename... Args>
explicit LogicError(const char* message, Args&&... args)
: Exception{fmt::format(fmt::runtime(message), std::forward<Args>(args)...)} {}
};
class RuntimeError : public Exception {
public:
template <typename... Args>
explicit RuntimeError(const char* message, Args&&... args)
: Exception{fmt::format(fmt::runtime(message), std::forward<Args>(args)...)} {}
};
class NotImplementedException : public Exception {
public:
template <typename... Args>
explicit NotImplementedException(const char* message, Args&&... args)
: Exception{fmt::format(fmt::runtime(message), std::forward<Args>(args)...)} {
Append(" is not implemented");
}
};
class InvalidArgument : public Exception {
public:
template <typename... Args>
explicit InvalidArgument(const char* message, Args&&... args)
: Exception{fmt::format(fmt::runtime(message), std::forward<Args>(args)...)} {}
};
} // namespace Shader
| 1,720
|
C++
|
.h
| 50
| 30.48
| 89
| 0.690821
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,950
|
program.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/program.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string>
#include "shader_recompiler/frontend/instruction.h"
#include "shader_recompiler/info.h"
#include "shader_recompiler/ir/abstract_syntax_list.h"
#include "shader_recompiler/ir/basic_block.h"
namespace Shader::IR {
struct Program {
explicit Program(Info& info_) : info{info_} {}
AbstractSyntaxList syntax_list;
BlockList blocks;
BlockList post_order_blocks;
std::vector<Gcn::GcnInst> ins_list;
Info& info;
};
[[nodiscard]] std::string DumpProgram(const Program& program);
} // namespace Shader::IR
| 669
|
C++
|
.h
| 19
| 32.578947
| 66
| 0.762053
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,951
|
attribute.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/attribute.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <fmt/format.h>
#include "common/assert.h"
#include "common/types.h"
namespace Shader::IR {
enum class Attribute : u64 {
// Export targets
RenderTarget0 = 0,
RenderTarget1 = 1,
RenderTarget2 = 2,
RenderTarget3 = 3,
RenderTarget4 = 4,
RenderTarget5 = 5,
RenderTarget6 = 6,
RenderTarget7 = 7,
Depth = 8,
Null = 9,
Position0 = 12,
Position1 = 13,
Position2 = 14,
Position3 = 15,
Param0 = 32,
Param1 = 33,
Param2 = 34,
Param3 = 35,
Param4 = 36,
Param5 = 37,
Param6 = 38,
Param7 = 39,
Param8 = 40,
Param9 = 41,
Param10 = 42,
Param11 = 43,
Param12 = 44,
Param13 = 45,
Param14 = 46,
Param15 = 47,
Param16 = 48,
Param17 = 49,
Param18 = 50,
Param19 = 51,
Param20 = 52,
Param21 = 53,
Param22 = 54,
Param23 = 55,
Param24 = 56,
Param25 = 57,
Param26 = 58,
Param27 = 59,
Param28 = 60,
Param29 = 61,
Param30 = 62,
Param31 = 63,
// System values
ClipDistance = 64,
CullDistance = 65,
RenderTargetId = 66,
ViewportId = 67,
VertexId = 68,
PrimitiveId = 69,
InstanceId = 70,
IsFrontFace = 71,
SampleIndex = 72,
GlobalInvocationId = 73,
WorkgroupId = 74,
LocalInvocationId = 75,
LocalInvocationIndex = 76,
FragCoord = 77,
InstanceId0 = 78, // step rate 0
InstanceId1 = 79, // step rate 1
Max,
};
constexpr size_t NumAttributes = static_cast<size_t>(Attribute::Max);
constexpr size_t NumRenderTargets = 8;
constexpr size_t NumParams = 32;
constexpr bool IsPosition(Attribute attribute) noexcept {
return attribute >= Attribute::Position0 && attribute <= Attribute::Position3;
}
constexpr bool IsParam(Attribute attribute) noexcept {
return attribute >= Attribute::Param0 && attribute <= Attribute::Param31;
}
constexpr bool IsMrt(Attribute attribute) noexcept {
return attribute >= Attribute::RenderTarget0 && attribute <= Attribute::RenderTarget7;
}
[[nodiscard]] std::string NameOf(Attribute attribute);
[[nodiscard]] constexpr Attribute operator+(Attribute attr, int num) {
const int result{static_cast<int>(attr) + num};
if (result > static_cast<int>(Attribute::Param31)) {
UNREACHABLE_MSG("Overflow on register arithmetic");
}
if (result < static_cast<int>(Attribute::RenderTarget0)) {
UNREACHABLE_MSG("Underflow on register arithmetic");
}
return static_cast<Attribute>(result);
}
} // namespace Shader::IR
template <>
struct fmt::formatter<Shader::IR::Attribute> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(const Shader::IR::Attribute attribute, format_context& ctx) const {
return fmt::format_to(ctx.out(), "{}", Shader::IR::NameOf(attribute));
}
};
| 2,969
|
C++
|
.h
| 107
| 23.420561
| 90
| 0.663509
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,952
|
opcodes.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/opcodes.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <array>
#include <fmt/format.h>
#include "common/types.h"
#include "shader_recompiler/ir/type.h"
namespace Shader::IR {
enum class Opcode {
#define OPCODE(name, ...) name,
#include "opcodes.inc"
#undef OPCODE
};
namespace Detail {
struct OpcodeMeta {
std::string_view name;
Type type;
std::array<Type, 6> arg_types;
};
// using enum Type;
constexpr Type Void{Type::Void};
constexpr Type Opaque{Type::Opaque};
constexpr Type ScalarReg{Type::ScalarReg};
constexpr Type VectorReg{Type::VectorReg};
constexpr Type Attribute{Type::Attribute};
constexpr Type SystemValue{Type::SystemValue};
constexpr Type U1{Type::U1};
constexpr Type U8{Type::U8};
constexpr Type U16{Type::U16};
constexpr Type U32{Type::U32};
constexpr Type U64{Type::U64};
constexpr Type F16{Type::F16};
constexpr Type F32{Type::F32};
constexpr Type F64{Type::F64};
constexpr Type U32x2{Type::U32x2};
constexpr Type U32x3{Type::U32x3};
constexpr Type U32x4{Type::U32x4};
constexpr Type F16x2{Type::F16x2};
constexpr Type F16x3{Type::F16x3};
constexpr Type F16x4{Type::F16x4};
constexpr Type F32x2{Type::F32x2};
constexpr Type F32x3{Type::F32x3};
constexpr Type F32x4{Type::F32x4};
constexpr Type F64x2{Type::F64x2};
constexpr Type F64x3{Type::F64x3};
constexpr Type F64x4{Type::F64x4};
constexpr Type StringLiteral{Type::StringLiteral};
constexpr OpcodeMeta META_TABLE[]{
#define OPCODE(name_token, type_token, ...) \
{ \
.name{#name_token}, \
.type = type_token, \
.arg_types{__VA_ARGS__}, \
},
#include "opcodes.inc"
#undef OPCODE
};
constexpr size_t CalculateNumArgsOf(Opcode op) {
const auto& arg_types{META_TABLE[static_cast<size_t>(op)].arg_types};
return static_cast<size_t>(
std::distance(arg_types.begin(), std::ranges::find(arg_types, Type::Void)));
}
constexpr u8 NUM_ARGS[]{
#define OPCODE(name_token, type_token, ...) static_cast<u8>(CalculateNumArgsOf(Opcode::name_token)),
#include "opcodes.inc"
#undef OPCODE
};
} // namespace Detail
/// Get return type of an opcode
[[nodiscard]] inline Type TypeOf(Opcode op) noexcept {
return Detail::META_TABLE[static_cast<size_t>(op)].type;
}
/// Get the number of arguments an opcode accepts
[[nodiscard]] constexpr inline size_t NumArgsOf(Opcode op) noexcept {
return static_cast<size_t>(Detail::NUM_ARGS[static_cast<size_t>(op)]);
}
/// Get the required type of an argument of an opcode
[[nodiscard]] inline Type ArgTypeOf(Opcode op, size_t arg_index) noexcept {
return Detail::META_TABLE[static_cast<size_t>(op)].arg_types[arg_index];
}
/// Get the name of an opcode
[[nodiscard]] std::string_view NameOf(Opcode op);
} // namespace Shader::IR
template <>
struct fmt::formatter<Shader::IR::Opcode> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
template <typename FormatContext>
auto format(const Shader::IR::Opcode op, FormatContext& ctx) const {
return fmt::format_to(ctx.out(), "{}", Shader::IR::NameOf(op));
}
};
| 3,497
|
C++
|
.h
| 94
| 34.904255
| 100
| 0.655356
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,953
|
value.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/value.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <array>
#include <bit>
#include <cstring>
#include <type_traits>
#include <utility>
#include <boost/container/small_vector.hpp>
#include <boost/intrusive/list.hpp>
#include "common/assert.h"
#include "shader_recompiler/exception.h"
#include "shader_recompiler/ir/attribute.h"
#include "shader_recompiler/ir/opcodes.h"
#include "shader_recompiler/ir/reg.h"
#include "shader_recompiler/ir/type.h"
namespace Shader::IR {
class Block;
class Inst;
struct AssociatedInsts;
class Value {
public:
Value() noexcept = default;
explicit Value(IR::Inst* value) noexcept;
explicit Value(const IR::Inst* value) noexcept;
explicit Value(IR::ScalarReg reg) noexcept;
explicit Value(IR::VectorReg reg) noexcept;
explicit Value(IR::Attribute value) noexcept;
explicit Value(bool value) noexcept;
explicit Value(u8 value) noexcept;
explicit Value(u16 value) noexcept;
explicit Value(u32 value) noexcept;
explicit Value(f32 value) noexcept;
explicit Value(u64 value) noexcept;
explicit Value(f64 value) noexcept;
explicit Value(const char* value) noexcept;
[[nodiscard]] bool IsIdentity() const noexcept;
[[nodiscard]] bool IsPhi() const noexcept;
[[nodiscard]] bool IsEmpty() const noexcept;
[[nodiscard]] bool IsImmediate() const noexcept;
[[nodiscard]] IR::Type Type() const noexcept;
[[nodiscard]] IR::Inst* Inst() const;
[[nodiscard]] IR::Inst* InstRecursive() const;
[[nodiscard]] IR::Inst* TryInstRecursive() const;
[[nodiscard]] IR::Value Resolve() const;
[[nodiscard]] IR::ScalarReg ScalarReg() const;
[[nodiscard]] IR::VectorReg VectorReg() const;
[[nodiscard]] IR::Attribute Attribute() const;
[[nodiscard]] bool U1() const;
[[nodiscard]] u8 U8() const;
[[nodiscard]] u16 U16() const;
[[nodiscard]] u32 U32() const;
[[nodiscard]] f32 F32() const;
[[nodiscard]] u64 U64() const;
[[nodiscard]] f64 F64() const;
[[nodiscard]] const char* StringLiteral() const;
[[nodiscard]] bool operator==(const Value& other) const;
[[nodiscard]] bool operator!=(const Value& other) const;
private:
IR::Type type{};
union {
IR::Inst* inst{};
IR::ScalarReg sreg;
IR::VectorReg vreg;
IR::Attribute attribute;
bool imm_u1;
u8 imm_u8;
u16 imm_u16;
u32 imm_u32;
f32 imm_f32;
u64 imm_u64;
f64 imm_f64;
const char* string_literal;
};
friend class std::hash<Value>;
};
static_assert(static_cast<u32>(IR::Type::Void) == 0, "memset relies on IR::Type being zero");
static_assert(std::is_trivially_copyable_v<Value>);
template <IR::Type type_>
class TypedValue : public Value {
public:
TypedValue() = default;
template <IR::Type other_type>
requires((other_type & type_) != IR::Type::Void)
explicit(false) TypedValue(const TypedValue<other_type>& value) : Value(value) {}
explicit TypedValue(const Value& value) : Value(value) {
if ((value.Type() & type_) == IR::Type::Void) {
throw InvalidArgument("Incompatible types {} and {}", type_, value.Type());
}
}
explicit TypedValue(IR::Inst* inst_) : TypedValue(Value(inst_)) {}
};
class Inst : public boost::intrusive::list_base_hook<> {
public:
explicit Inst(IR::Opcode op_, u32 flags_) noexcept;
explicit Inst(const Inst& base);
~Inst();
Inst& operator=(const Inst&) = delete;
Inst& operator=(Inst&&) = delete;
Inst(Inst&&) = delete;
/// Get the number of uses this instruction has.
[[nodiscard]] int UseCount() const noexcept {
return use_count;
}
/// Determines whether this instruction has uses or not.
[[nodiscard]] bool HasUses() const noexcept {
return use_count > 0;
}
/// Get the opcode this microinstruction represents.
[[nodiscard]] IR::Opcode GetOpcode() const noexcept {
return op;
}
/// Determines whether or not this instruction may have side effects.
[[nodiscard]] bool MayHaveSideEffects() const noexcept;
/// Determines if all arguments of this instruction are immediates.
[[nodiscard]] bool AreAllArgsImmediates() const;
/// Get the type this instruction returns.
[[nodiscard]] IR::Type Type() const;
/// Get the number of arguments this instruction has.
[[nodiscard]] size_t NumArgs() const {
return op == IR::Opcode::Phi ? phi_args.size() : NumArgsOf(op);
}
/// Get the value of a given argument index.
[[nodiscard]] Value Arg(size_t index) const noexcept {
if (op == IR::Opcode::Phi) {
return phi_args[index].second;
} else {
return args[index];
}
}
/// Set the value of a given argument index.
void SetArg(size_t index, Value value);
/// Get a pointer to the block of a phi argument.
[[nodiscard]] Block* PhiBlock(size_t index) const;
/// Add phi operand to a phi instruction.
void AddPhiOperand(Block* predecessor, const Value& value);
void Invalidate();
void ClearArgs();
void ReplaceUsesWith(Value replacement);
void ReplaceOpcode(IR::Opcode opcode);
template <typename FlagsType>
requires(sizeof(FlagsType) <= sizeof(u32) && std::is_trivially_copyable_v<FlagsType>)
[[nodiscard]] FlagsType Flags() const noexcept {
FlagsType ret;
std::memcpy(reinterpret_cast<char*>(&ret), &flags, sizeof(ret));
return ret;
}
template <typename FlagsType>
requires(sizeof(FlagsType) <= sizeof(u32) && std::is_trivially_copyable_v<FlagsType>)
void SetFlags(FlagsType value) noexcept {
std::memcpy(&flags, &value, sizeof(value));
}
/// Intrusively store the host definition of this instruction.
template <typename DefinitionType>
void SetDefinition(DefinitionType def) {
definition = std::bit_cast<u32>(def);
}
/// Return the intrusively stored host definition of this instruction.
template <typename DefinitionType>
[[nodiscard]] DefinitionType Definition() const noexcept {
return std::bit_cast<DefinitionType>(definition);
}
private:
struct NonTriviallyDummy {
NonTriviallyDummy() noexcept {}
};
void Use(const Value& value);
void UndoUse(const Value& value);
IR::Opcode op{};
int use_count{};
u32 flags{};
u32 definition{};
union {
NonTriviallyDummy dummy{};
boost::container::small_vector<std::pair<Block*, Value>, 2> phi_args;
std::array<Value, 6> args;
};
};
static_assert(sizeof(Inst) <= 128, "Inst size unintentionally increased");
using U1 = TypedValue<Type::U1>;
using U8 = TypedValue<Type::U8>;
using U16 = TypedValue<Type::U16>;
using U32 = TypedValue<Type::U32>;
using U64 = TypedValue<Type::U64>;
using F16 = TypedValue<Type::F16>;
using F32 = TypedValue<Type::F32>;
using F64 = TypedValue<Type::F64>;
using U32F32 = TypedValue<Type::U32 | Type::F32>;
using U64F64 = TypedValue<Type::U64 | Type::F64>;
using U32U64 = TypedValue<Type::U32 | Type::U64>;
using U16U32U64 = TypedValue<Type::U16 | Type::U32 | Type::U64>;
using F32F64 = TypedValue<Type::F32 | Type::F64>;
using F16F32F64 = TypedValue<Type::F16 | Type::F32 | Type::F64>;
using UAny = TypedValue<Type::U8 | Type::U16 | Type::U32 | Type::U64>;
inline bool Value::IsIdentity() const noexcept {
return type == Type::Opaque && inst->GetOpcode() == Opcode::Identity;
}
inline bool Value::IsPhi() const noexcept {
return type == Type::Opaque && inst->GetOpcode() == Opcode::Phi;
}
inline bool Value::IsEmpty() const noexcept {
return type == Type::Void;
}
inline bool Value::IsImmediate() const noexcept {
IR::Type current_type{type};
const IR::Inst* current_inst{inst};
while (current_type == Type::Opaque && current_inst->GetOpcode() == Opcode::Identity) {
const Value& arg{current_inst->Arg(0)};
current_type = arg.type;
current_inst = arg.inst;
}
return current_type != Type::Opaque;
}
inline IR::Inst* Value::Inst() const {
DEBUG_ASSERT(type == Type::Opaque);
return inst;
}
inline IR::Inst* Value::InstRecursive() const {
DEBUG_ASSERT(type == Type::Opaque);
if (IsIdentity()) {
return inst->Arg(0).InstRecursive();
}
return inst;
}
inline IR::Inst* Value::TryInstRecursive() const {
if (IsIdentity()) {
return inst->Arg(0).TryInstRecursive();
}
return type == Type::Opaque ? inst : nullptr;
}
inline IR::Value Value::Resolve() const {
if (IsIdentity()) {
return inst->Arg(0).Resolve();
}
return *this;
}
inline IR::ScalarReg Value::ScalarReg() const {
DEBUG_ASSERT(type == Type::ScalarReg);
return sreg;
}
inline IR::VectorReg Value::VectorReg() const {
DEBUG_ASSERT(type == Type::VectorReg);
return vreg;
}
inline IR::Attribute Value::Attribute() const {
DEBUG_ASSERT(type == Type::Attribute);
return attribute;
}
inline bool Value::U1() const {
if (IsIdentity()) {
return inst->Arg(0).U1();
}
DEBUG_ASSERT(type == Type::U1);
return imm_u1;
}
inline u8 Value::U8() const {
if (IsIdentity()) {
return inst->Arg(0).U8();
}
DEBUG_ASSERT(type == Type::U8);
return imm_u8;
}
inline u16 Value::U16() const {
if (IsIdentity()) {
return inst->Arg(0).U16();
}
DEBUG_ASSERT(type == Type::U16);
return imm_u16;
}
inline u32 Value::U32() const {
if (IsIdentity()) {
return inst->Arg(0).U32();
}
DEBUG_ASSERT(type == Type::U32);
return imm_u32;
}
inline f32 Value::F32() const {
if (IsIdentity()) {
return inst->Arg(0).F32();
}
DEBUG_ASSERT(type == Type::F32);
return imm_f32;
}
inline u64 Value::U64() const {
if (IsIdentity()) {
return inst->Arg(0).U64();
}
DEBUG_ASSERT(type == Type::U64);
return imm_u64;
}
inline f64 Value::F64() const {
if (IsIdentity()) {
return inst->Arg(0).F64();
}
DEBUG_ASSERT(type == Type::F64);
return imm_f64;
}
inline const char* Value::StringLiteral() const {
if (IsIdentity()) {
return inst->Arg(0).StringLiteral();
}
DEBUG_ASSERT(type == Type::StringLiteral);
return string_literal;
}
[[nodiscard]] inline bool IsPhi(const Inst& inst) {
return inst.GetOpcode() == Opcode::Phi;
}
} // namespace Shader::IR
namespace std {
template <>
struct hash<Shader::IR::Value> {
std::size_t operator()(const Shader::IR::Value& v) const;
};
} // namespace std
| 10,644
|
C++
|
.h
| 314
| 29.238854
| 93
| 0.661019
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,954
|
ir_emitter.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/ir_emitter.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <cstring>
#include <type_traits>
#include "shader_recompiler/info.h"
#include "shader_recompiler/ir/attribute.h"
#include "shader_recompiler/ir/basic_block.h"
#include "shader_recompiler/ir/condition.h"
#include "shader_recompiler/ir/value.h"
namespace Shader::IR {
class IREmitter {
public:
explicit IREmitter(Block& block_) : block{&block_}, insertion_point{block->end()} {}
explicit IREmitter(Block& block_, Block::iterator insertion_point_)
: block{&block_}, insertion_point{insertion_point_} {}
Block* block;
[[nodiscard]] U1 Imm1(bool value) const;
[[nodiscard]] U8 Imm8(u8 value) const;
[[nodiscard]] U16 Imm16(u16 value) const;
[[nodiscard]] U32 Imm32(u32 value) const;
[[nodiscard]] U32 Imm32(s32 value) const;
[[nodiscard]] F32 Imm32(f32 value) const;
[[nodiscard]] U64 Imm64(u64 value) const;
[[nodiscard]] U64 Imm64(s64 value) const;
[[nodiscard]] F64 Imm64(f64 value) const;
template <typename Dest, typename Source>
[[nodiscard]] Dest BitCast(const Source& value);
U1 ConditionRef(const U1& value);
void Reference(const Value& value);
void PhiMove(IR::Inst& phi, const Value& value);
void Prologue();
void Epilogue();
void Discard();
void Discard(const U1& cond);
void DebugPrint(const char* fmt, boost::container::small_vector<Value, 5> args);
void Barrier();
void WorkgroupMemoryBarrier();
void DeviceMemoryBarrier();
[[nodiscard]] U32 GetUserData(IR::ScalarReg reg);
[[nodiscard]] U1 GetThreadBitScalarReg(IR::ScalarReg reg);
void SetThreadBitScalarReg(IR::ScalarReg reg, const U1& value);
template <typename T = U32>
[[nodiscard]] T GetScalarReg(IR::ScalarReg reg);
template <typename T = U32>
[[nodiscard]] T GetVectorReg(IR::VectorReg reg);
void SetScalarReg(IR::ScalarReg reg, const U32F32& value);
void SetVectorReg(IR::VectorReg reg, const U32F32& value);
[[nodiscard]] U1 GetGotoVariable(u32 id);
void SetGotoVariable(u32 id, const U1& value);
[[nodiscard]] U1 GetScc();
[[nodiscard]] U1 GetExec();
[[nodiscard]] U1 GetVcc();
[[nodiscard]] U32 GetVccLo();
[[nodiscard]] U32 GetVccHi();
[[nodiscard]] U32 GetM0();
void SetScc(const U1& value);
void SetExec(const U1& value);
void SetVcc(const U1& value);
void SetSccLo(const U32& value);
void SetVccLo(const U32& value);
void SetVccHi(const U32& value);
void SetM0(const U32& value);
[[nodiscard]] U1 Condition(IR::Condition cond);
[[nodiscard]] F32 GetAttribute(Attribute attribute, u32 comp = 0, u32 index = 0);
[[nodiscard]] U32 GetAttributeU32(Attribute attribute, u32 comp = 0);
void SetAttribute(Attribute attribute, const F32& value, u32 comp = 0);
[[nodiscard]] Value LoadShared(int bit_size, bool is_signed, const U32& offset);
void WriteShared(int bit_size, const Value& value, const U32& offset);
[[nodiscard]] U32F32 SharedAtomicIAdd(const U32& address, const U32F32& data);
[[nodiscard]] U32 SharedAtomicIMin(const U32& address, const U32& data, bool is_signed);
[[nodiscard]] U32 SharedAtomicIMax(const U32& address, const U32& data, bool is_signed);
[[nodiscard]] U32 ReadConst(const Value& base, const U32& offset);
[[nodiscard]] U32 ReadConstBuffer(const Value& handle, const U32& index);
[[nodiscard]] Value LoadBuffer(int num_dwords, const Value& handle, const Value& address,
BufferInstInfo info);
[[nodiscard]] Value LoadBufferFormat(const Value& handle, const Value& address,
BufferInstInfo info);
void StoreBuffer(int num_dwords, const Value& handle, const Value& address, const Value& data,
BufferInstInfo info);
void StoreBufferFormat(const Value& handle, const Value& address, const Value& data,
BufferInstInfo info);
[[nodiscard]] Value BufferAtomicIAdd(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicIMin(const Value& handle, const Value& address,
const Value& value, bool is_signed, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicIMax(const Value& handle, const Value& address,
const Value& value, bool is_signed, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicInc(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicDec(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicAnd(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicOr(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicXor(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicSwap(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] U32 DataAppend(const U32& counter);
[[nodiscard]] U32 DataConsume(const U32& counter);
[[nodiscard]] U32 LaneId();
[[nodiscard]] U32 WarpId();
[[nodiscard]] U32 QuadShuffle(const U32& value, const U32& index);
[[nodiscard]] U32 ReadFirstLane(const U32& value);
[[nodiscard]] U32 ReadLane(const U32& value, const U32& lane);
[[nodiscard]] U32 WriteLane(const U32& value, const U32& write_value, const U32& lane);
[[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2);
[[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2, const Value& e3);
[[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2, const Value& e3,
const Value& e4);
[[nodiscard]] Value CompositeExtract(const Value& vector, size_t element);
[[nodiscard]] Value CompositeInsert(const Value& vector, const Value& object, size_t element);
[[nodiscard]] Value Select(const U1& condition, const Value& true_value,
const Value& false_value);
[[nodiscard]] U64 PackUint2x32(const Value& vector);
[[nodiscard]] Value UnpackUint2x32(const U64& value);
[[nodiscard]] F64 PackFloat2x32(const Value& vector);
[[nodiscard]] U32 PackFloat2x16(const Value& vector);
[[nodiscard]] Value UnpackFloat2x16(const U32& value);
[[nodiscard]] U32 PackHalf2x16(const Value& vector);
[[nodiscard]] Value UnpackHalf2x16(const U32& value);
[[nodiscard]] F32F64 FPAdd(const F32F64& a, const F32F64& b);
[[nodiscard]] F32F64 FPSub(const F32F64& a, const F32F64& b);
[[nodiscard]] F32F64 FPMul(const F32F64& a, const F32F64& b);
[[nodiscard]] F32F64 FPFma(const F32F64& a, const F32F64& b, const F32F64& c);
[[nodiscard]] F32F64 FPAbs(const F32F64& value);
[[nodiscard]] F32F64 FPNeg(const F32F64& value);
[[nodiscard]] F32F64 FPAbsNeg(const F32F64& value, bool abs, bool neg);
[[nodiscard]] F32 FPCos(const F32& value);
[[nodiscard]] F32 FPSin(const F32& value);
[[nodiscard]] F32 FPExp2(const F32& value);
[[nodiscard]] F32 FPLog2(const F32& value);
[[nodiscard]] F32 FPLdexp(const F32& value, const U32& exp);
[[nodiscard]] F32F64 FPRecip(const F32F64& value);
[[nodiscard]] F32F64 FPRecipSqrt(const F32F64& value);
[[nodiscard]] F32 FPSqrt(const F32& value);
[[nodiscard]] F32F64 FPSaturate(const F32F64& value);
[[nodiscard]] F32F64 FPClamp(const F32F64& value, const F32F64& min_value,
const F32F64& max_value);
[[nodiscard]] F32F64 FPRoundEven(const F32F64& value);
[[nodiscard]] F32F64 FPFloor(const F32F64& value);
[[nodiscard]] F32F64 FPCeil(const F32F64& value);
[[nodiscard]] F32F64 FPTrunc(const F32F64& value);
[[nodiscard]] F32 Fract(const F32& value);
[[nodiscard]] U1 FPEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPNotEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPLessThanEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPGreaterThanEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPLessThan(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPGreaterThan(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPIsNan(const F32F64& value);
[[nodiscard]] U1 FPIsInf(const F32F64& value);
[[nodiscard]] U1 FPCmpClass32(const F32& value, const U32& op);
[[nodiscard]] U1 FPOrdered(const F32F64& lhs, const F32F64& rhs);
[[nodiscard]] U1 FPUnordered(const F32F64& lhs, const F32F64& rhs);
[[nodiscard]] F32F64 FPMax(const F32F64& lhs, const F32F64& rhs, bool is_legacy = false);
[[nodiscard]] F32F64 FPMin(const F32F64& lhs, const F32F64& rhs, bool is_legacy = false);
[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
[[nodiscard]] Value IAddCary(const U32& a, const U32& b);
[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
[[nodiscard]] Value IMulExt(const U32& a, const U32& b, bool is_signed = false);
[[nodiscard]] U32U64 IMul(const U32U64& a, const U32U64& b);
[[nodiscard]] U32 IDiv(const U32& a, const U32& b, bool is_signed = false);
[[nodiscard]] U32 IMod(const U32& a, const U32& b, bool is_signed = false);
[[nodiscard]] U32U64 INeg(const U32U64& value);
[[nodiscard]] U32 IAbs(const U32& value);
[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
[[nodiscard]] U32U64 BitwiseAnd(const U32U64& a, const U32U64& b);
[[nodiscard]] U32U64 BitwiseOr(const U32U64& a, const U32U64& b);
[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
[[nodiscard]] U32 BitFieldInsert(const U32& base, const U32& insert, const U32& offset,
const U32& count);
[[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
bool is_signed = false);
[[nodiscard]] U32 BitReverse(const U32& value);
[[nodiscard]] U32 BitCount(const U32& value);
[[nodiscard]] U32 BitwiseNot(const U32& value);
[[nodiscard]] U32 FindSMsb(const U32& value);
[[nodiscard]] U32 FindUMsb(const U32& value);
[[nodiscard]] U32 FindILsb(const U32& value);
[[nodiscard]] U32 SMin(const U32& a, const U32& b);
[[nodiscard]] U32 UMin(const U32& a, const U32& b);
[[nodiscard]] U32 IMin(const U32& a, const U32& b, bool is_signed);
[[nodiscard]] U32 SMax(const U32& a, const U32& b);
[[nodiscard]] U32 UMax(const U32& a, const U32& b);
[[nodiscard]] U32 IMax(const U32& a, const U32& b, bool is_signed);
[[nodiscard]] U32 SClamp(const U32& value, const U32& min, const U32& max);
[[nodiscard]] U32 UClamp(const U32& value, const U32& min, const U32& max);
[[nodiscard]] U1 ILessThan(const U32U64& lhs, const U32U64& rhs, bool is_signed);
[[nodiscard]] U1 IEqual(const U32U64& lhs, const U32U64& rhs);
[[nodiscard]] U1 ILessThanEqual(const U32& lhs, const U32& rhs, bool is_signed);
[[nodiscard]] U1 IGreaterThan(const U32& lhs, const U32& rhs, bool is_signed);
[[nodiscard]] U1 INotEqual(const U32& lhs, const U32& rhs);
[[nodiscard]] U1 IGreaterThanEqual(const U32& lhs, const U32& rhs, bool is_signed);
[[nodiscard]] U1 LogicalOr(const U1& a, const U1& b);
[[nodiscard]] U1 LogicalAnd(const U1& a, const U1& b);
[[nodiscard]] U1 LogicalXor(const U1& a, const U1& b);
[[nodiscard]] U1 LogicalNot(const U1& value);
[[nodiscard]] U32U64 ConvertFToS(size_t bitsize, const F32F64& value);
[[nodiscard]] U32U64 ConvertFToU(size_t bitsize, const F32F64& value);
[[nodiscard]] U32U64 ConvertFToI(size_t bitsize, bool is_signed, const F32F64& value);
[[nodiscard]] F32F64 ConvertSToF(size_t dest_bitsize, size_t src_bitsize, const Value& value);
[[nodiscard]] F32F64 ConvertUToF(size_t dest_bitsize, size_t src_bitsize, const Value& value);
[[nodiscard]] F32F64 ConvertIToF(size_t dest_bitsize, size_t src_bitsize, bool is_signed,
const Value& value);
[[nodiscard]] U16U32U64 UConvert(size_t result_bitsize, const U16U32U64& value);
[[nodiscard]] F16F32F64 FPConvert(size_t result_bitsize, const F16F32F64& value);
[[nodiscard]] Value ImageAtomicIAdd(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicSMin(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicUMin(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicIMin(const Value& handle, const Value& coords,
const Value& value, bool is_signed, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicSMax(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicUMax(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicIMax(const Value& handle, const Value& coords,
const Value& value, bool is_signed, TextureInstInfo info);
[[nodiscard]] Value ImageAtomicInc(const Value& handle, const Value& coords, const Value& value,
TextureInstInfo info);
[[nodiscard]] Value ImageAtomicDec(const Value& handle, const Value& coords, const Value& value,
TextureInstInfo info);
[[nodiscard]] Value ImageAtomicAnd(const Value& handle, const Value& coords, const Value& value,
TextureInstInfo info);
[[nodiscard]] Value ImageAtomicOr(const Value& handle, const Value& coords, const Value& value,
TextureInstInfo info);
[[nodiscard]] Value ImageAtomicXor(const Value& handle, const Value& coords, const Value& value,
TextureInstInfo info);
[[nodiscard]] Value ImageAtomicExchange(const Value& handle, const Value& coords,
const Value& value, TextureInstInfo info);
[[nodiscard]] Value ImageSampleRaw(const Value& handle, const Value& address1,
const Value& address2, const Value& address3,
const Value& address4, TextureInstInfo info);
[[nodiscard]] Value ImageSampleImplicitLod(const Value& handle, const Value& body,
const F32& bias, const Value& offset,
TextureInstInfo info);
[[nodiscard]] Value ImageSampleExplicitLod(const Value& handle, const Value& body,
const F32& lod, const Value& offset,
TextureInstInfo info);
[[nodiscard]] Value ImageSampleDrefImplicitLod(const Value& handle, const Value& body,
const F32& dref, const F32& bias,
const Value& offset, TextureInstInfo info);
[[nodiscard]] Value ImageSampleDrefExplicitLod(const Value& handle, const Value& body,
const F32& dref, const F32& lod,
const Value& offset, TextureInstInfo info);
[[nodiscard]] Value ImageQueryDimension(const Value& handle, const U32& lod,
const U1& skip_mips);
[[nodiscard]] Value ImageQueryDimension(const Value& handle, const U32& lod,
const U1& skip_mips, TextureInstInfo info);
[[nodiscard]] Value ImageQueryLod(const Value& handle, const Value& coords,
TextureInstInfo info);
[[nodiscard]] Value ImageGather(const Value& handle, const Value& coords, const Value& offset,
TextureInstInfo info);
[[nodiscard]] Value ImageGatherDref(const Value& handle, const Value& coords,
const Value& offset, const F32& dref, TextureInstInfo info);
[[nodiscard]] Value ImageFetch(const Value& handle, const Value& coords, const Value& offset,
const U32& lod, const U32& multisampling, TextureInstInfo info);
[[nodiscard]] Value ImageGradient(const Value& handle, const Value& coords,
const Value& derivatives_dx, const Value& derivatives_dy,
const Value& offset, const F32& lod_clamp,
TextureInstInfo info);
[[nodiscard]] Value ImageRead(const Value& handle, const Value& coords, TextureInstInfo info);
void ImageWrite(const Value& handle, const Value& coords, const Value& color,
TextureInstInfo info);
void EmitVertex();
void EmitPrimitive();
private:
IR::Block::iterator insertion_point;
template <typename T = Value, typename... Args>
T Inst(Opcode op, Args... args) {
auto it{block->PrependNewInst(insertion_point, op, {Value{args}...})};
return T{Value{&*it}};
}
template <typename T>
requires(sizeof(T) <= sizeof(u32) && std::is_trivially_copyable_v<T>)
struct Flags {
Flags() = default;
Flags(T proxy_) : proxy{proxy_} {}
T proxy;
};
template <typename T = Value, typename FlagType, typename... Args>
T Inst(Opcode op, Flags<FlagType> flags, Args... args) {
u32 raw_flags{};
std::memcpy(&raw_flags, &flags.proxy, sizeof(flags.proxy));
auto it{block->PrependNewInst(insertion_point, op, {Value{args}...}, raw_flags)};
return T{Value{&*it}};
}
};
} // namespace Shader::IR
| 19,070
|
C++
|
.h
| 296
| 53.033784
| 100
| 0.638015
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,955
|
abstract_syntax_list.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/abstract_syntax_list.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <vector>
#include "shader_recompiler/ir/value.h"
namespace Shader::IR {
class Block;
struct AbstractSyntaxNode {
enum class Type {
Block,
If,
EndIf,
Loop,
Repeat,
Break,
Return,
Unreachable,
};
union Data {
Block* block;
struct {
U1 cond;
Block* body;
Block* merge;
} if_node;
struct {
Block* merge;
} end_if;
struct {
Block* body;
Block* continue_block;
Block* merge;
} loop;
struct {
U1 cond;
Block* loop_header;
Block* merge;
} repeat;
struct {
U1 cond;
Block* merge;
Block* skip;
} break_node;
};
Data data{};
Type type{};
};
using AbstractSyntaxList = std::vector<AbstractSyntaxNode>;
} // namespace Shader::IR
| 1,089
|
C++
|
.h
| 49
| 14.306122
| 66
| 0.523717
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,956
|
reg.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/reg.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/assert.h"
#include "common/bit_field.h"
#include "common/enum.h"
#include "common/types.h"
namespace Shader::IR {
enum class FloatClassFunc : u32 {
SignalingNan = 1 << 0,
QuietNan = 1 << 1,
NegativeInfinity = 1 << 2,
NegativeNormal = 1 << 3,
NegativeDenorm = 1 << 4,
NegativeZero = 1 << 5,
PositiveZero = 1 << 6,
PositiveDenorm = 1 << 7,
PositiveNormal = 1 << 8,
PositiveInfinity = 1 << 9,
NaN = SignalingNan | QuietNan,
Infinity = PositiveInfinity | NegativeInfinity,
Finite = NegativeNormal | NegativeDenorm | NegativeZero | PositiveNormal | PositiveDenorm |
PositiveZero,
};
DECLARE_ENUM_FLAG_OPERATORS(FloatClassFunc)
union TextureInstInfo {
u32 raw;
BitField<0, 1, u32> is_depth;
BitField<1, 1, u32> has_bias;
BitField<2, 1, u32> has_lod_clamp;
BitField<3, 1, u32> force_level0;
BitField<4, 1, u32> has_lod;
BitField<5, 1, u32> has_offset;
BitField<6, 2, u32> gather_comp;
BitField<8, 1, u32> has_derivatives;
BitField<9, 1, u32> is_array;
BitField<10, 1, u32> is_gather;
};
union BufferInstInfo {
u32 raw;
BitField<0, 1, u32> index_enable;
BitField<1, 1, u32> offset_enable;
BitField<2, 12, u32> inst_offset;
BitField<14, 1, u32> ring_access; // global + system coherency
};
enum class ScalarReg : u32 {
S0,
S1,
S2,
S3,
S4,
S5,
S6,
S7,
S8,
S9,
S10,
S11,
S12,
S13,
S14,
S15,
S16,
S17,
S18,
S19,
S20,
S21,
S22,
S23,
S24,
S25,
S26,
S27,
S28,
S29,
S30,
S31,
S32,
S33,
S34,
S35,
S36,
S37,
S38,
S39,
S40,
S41,
S42,
S43,
S44,
S45,
S46,
S47,
S48,
S49,
S50,
S51,
S52,
S53,
S54,
S55,
S56,
S57,
S58,
S59,
S60,
S61,
S62,
S63,
S64,
S65,
S66,
S67,
S68,
S69,
S70,
S71,
S72,
S73,
S74,
S75,
S76,
S77,
S78,
S79,
S80,
S81,
S82,
S83,
S84,
S85,
S86,
S87,
S88,
S89,
S90,
S91,
S92,
S93,
S94,
S95,
S96,
S97,
S98,
S99,
S100,
S101,
S102,
S103,
Max,
};
static constexpr size_t NumScalarRegs = static_cast<size_t>(ScalarReg::Max);
enum class VectorReg : u32 {
V0,
V1,
V2,
V3,
V4,
V5,
V6,
V7,
V8,
V9,
V10,
V11,
V12,
V13,
V14,
V15,
V16,
V17,
V18,
V19,
V20,
V21,
V22,
V23,
V24,
V25,
V26,
V27,
V28,
V29,
V30,
V31,
V32,
V33,
V34,
V35,
V36,
V37,
V38,
V39,
V40,
V41,
V42,
V43,
V44,
V45,
V46,
V47,
V48,
V49,
V50,
V51,
V52,
V53,
V54,
V55,
V56,
V57,
V58,
V59,
V60,
V61,
V62,
V63,
V64,
V65,
V66,
V67,
V68,
V69,
V70,
V71,
V72,
V73,
V74,
V75,
V76,
V77,
V78,
V79,
V80,
V81,
V82,
V83,
V84,
V85,
V86,
V87,
V88,
V89,
V90,
V91,
V92,
V93,
V94,
V95,
V96,
V97,
V98,
V99,
V100,
V101,
V102,
V103,
V104,
V105,
V106,
V107,
V108,
V109,
V110,
V111,
V112,
V113,
V114,
V115,
V116,
V117,
V118,
V119,
V120,
V121,
V122,
V123,
V124,
V125,
V126,
V127,
V128,
V129,
V130,
V131,
V132,
V133,
V134,
V135,
V136,
V137,
V138,
V139,
V140,
V141,
V142,
V143,
V144,
V145,
V146,
V147,
V148,
V149,
V150,
V151,
V152,
V153,
V154,
V155,
V156,
V157,
V158,
V159,
V160,
V161,
V162,
V163,
V164,
V165,
V166,
V167,
V168,
V169,
V170,
V171,
V172,
V173,
V174,
V175,
V176,
V177,
V178,
V179,
V180,
V181,
V182,
V183,
V184,
V185,
V186,
V187,
V188,
V189,
V190,
V191,
V192,
V193,
V194,
V195,
V196,
V197,
V198,
V199,
V200,
V201,
V202,
V203,
V204,
V205,
V206,
V207,
V208,
V209,
V210,
V211,
V212,
V213,
V214,
V215,
V216,
V217,
V218,
V219,
V220,
V221,
V222,
V223,
V224,
V225,
V226,
V227,
V228,
V229,
V230,
V231,
V232,
V233,
V234,
V235,
V236,
V237,
V238,
V239,
V240,
V241,
V242,
V243,
V244,
V245,
V246,
V247,
V248,
V249,
V250,
V251,
V252,
V253,
V254,
V255,
Max,
};
static constexpr size_t NumVectorRegs = static_cast<size_t>(VectorReg::Max);
template <class T>
concept RegT = std::is_same_v<T, ScalarReg> || std::is_same_v<T, VectorReg>;
template <RegT Reg>
[[nodiscard]] constexpr Reg operator+(Reg reg, int num) {
const int result{static_cast<int>(reg) + num};
if (result >= static_cast<int>(Reg::Max)) {
UNREACHABLE_MSG("Overflow on register arithmetic");
}
if (result < 0) {
UNREACHABLE_MSG("Underflow on register arithmetic");
}
return static_cast<Reg>(result);
}
template <RegT Reg>
[[nodiscard]] constexpr Reg operator-(Reg reg, int num) {
return reg + (-num);
}
template <RegT Reg>
constexpr Reg operator++(Reg& reg) {
reg = reg + 1;
return reg;
}
template <RegT Reg>
constexpr Reg operator++(Reg& reg, int) {
const Reg copy{reg};
reg = reg + 1;
return copy;
}
template <RegT Reg>
[[nodiscard]] constexpr size_t RegIndex(Reg reg) noexcept {
return static_cast<size_t>(reg);
}
} // namespace Shader::IR
template <>
struct fmt::formatter<Shader::IR::ScalarReg> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(Shader::IR::ScalarReg reg, format_context& ctx) const {
return fmt::format_to(ctx.out(), "SGPR{}", static_cast<u32>(reg));
}
};
template <>
struct fmt::formatter<Shader::IR::VectorReg> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(Shader::IR::VectorReg reg, format_context& ctx) const {
return fmt::format_to(ctx.out(), "VGPR{}", static_cast<u32>(reg));
}
};
| 6,627
|
C++
|
.h
| 464
| 9.5625
| 95
| 0.540189
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,957
|
srt_gvn_table.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/srt_gvn_table.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include <unordered_map>
#include <boost/container/set.hpp>
#include <boost/container/small_vector.hpp>
#include "common/assert.h"
#include "common/hash.h"
#include "common/types.h"
#include "shader_recompiler/ir/breadth_first_search.h"
#include "shader_recompiler/ir/opcodes.h"
#include "shader_recompiler/ir/value.h"
namespace Shader::Optimization {
// Does global value numbering on a subset of instructions that are used
// for loads from shader resource tables.
// Inspiration from spirv-opt
class SrtGvnTable {
public:
using ValueNumberTable = std::unordered_map<IR::Value, u32>;
using ValueNum = u32;
SrtGvnTable() : value_numbers(), next_num(0) {}
u32 GetValueNumber(IR::Inst* inst) {
return GetValueNumber(IR::Value{inst});
}
u32 GetValueNumber(IR::Value v) {
v = v.Resolve();
if (auto it = value_numbers.find(v); it != value_numbers.end()) {
return it->second;
}
if (auto inst = v.TryInstRecursive()) {
return ComputeInstValueNumber(inst);
}
return NextValueNumber(v);
}
private:
u32 ComputeInstValueNumber(IR::Inst* inst) {
ASSERT(!value_numbers.contains(
IR::Value(inst))); // Should always be checking before calling this function
if (inst->MayHaveSideEffects()) {
return NextValueNumber(IR::Value(inst));
}
u32 vn;
switch (inst->GetOpcode()) {
case IR::Opcode::Phi: {
// hack to get to parity with main
// Need to fix ssa_rewrite pass to remove certain phis
std::optional<IR::Value> source = TryRemoveTrivialPhi(inst);
if (!source) {
const auto pred = [](IR::Inst* inst) -> std::optional<IR::Inst*> {
if (inst->GetOpcode() == IR::Opcode::GetUserData ||
inst->GetOpcode() == IR::Opcode::CompositeConstructU32x2 ||
inst->GetOpcode() == IR::Opcode::ReadConst) {
return inst;
}
return std::nullopt;
};
source = IR::BreadthFirstSearch(inst, pred).transform([](auto inst) {
return IR::Value{inst};
});
ASSERT(source);
}
vn = GetValueNumber(source.value());
value_numbers[IR::Value(inst)] = vn;
break;
}
case IR::Opcode::GetUserData:
case IR::Opcode::CompositeConstructU32x2:
case IR::Opcode::ReadConst: {
InstVector iv = MakeInstVector(inst);
if (auto it = iv_to_vn.find(iv); it != iv_to_vn.end()) {
vn = it->second;
value_numbers[IR::Value(inst)] = vn;
} else {
vn = NextValueNumber(IR::Value(inst));
iv_to_vn.emplace(std::move(iv), vn);
}
break;
}
default:
vn = NextValueNumber(IR::Value(inst));
break;
}
return vn;
}
u32 NextValueNumber(IR::Value v) {
u32 rv = next_num++;
value_numbers[v] = rv;
return rv;
}
ValueNumberTable value_numbers;
u32 next_num;
using InstVector = boost::container::small_vector<u32, 8>;
InstVector MakeInstVector(IR::Inst* inst) {
ASSERT(inst->GetOpcode() != IR::Opcode::Identity);
InstVector iv;
iv.reserve(2 + inst->NumArgs());
iv.push_back(static_cast<u32>(inst->GetOpcode()));
iv.push_back(inst->Flags<u32>());
for (auto i = 0; i < inst->NumArgs(); i++) {
iv.push_back(GetValueNumber(inst->Arg(i)));
}
return iv;
}
// Temp workaround for something like this:
// [0000555558a5baf8] %297 = Phi [ %24, {Block $1} ], [ %297, {Block $5} ] (uses: 4)
// [0000555558a4e038] %305 = CompositeConstructU32x2 %297, %296 (uses: 4)
// [0000555558a4e0a8] %306 = ReadConst %305, #0 (uses: 2)
// Should probably be fixed in ssa_rewrite
std::optional<IR::Value> TryRemoveTrivialPhi(IR::Inst* phi) {
IR::Value single_source{};
for (auto i = 0; i < phi->NumArgs(); i++) {
IR::Value v = phi->Arg(i).Resolve();
if (v == IR::Value(phi)) {
continue;
}
if (!single_source.IsEmpty() && single_source != v) {
return std::nullopt;
}
single_source = v;
}
ASSERT(!single_source.IsEmpty());
phi->ReplaceUsesWith(single_source);
return single_source;
}
struct HashInstVector {
size_t operator()(const InstVector& iv) const {
u32 h = 0;
for (auto vn : iv) {
h = HashCombine(vn, h);
}
return h;
}
};
std::unordered_map<InstVector, u32, HashInstVector> iv_to_vn;
};
} // namespace Shader::Optimization
| 5,076
|
C++
|
.h
| 135
| 28.088889
| 90
| 0.560163
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,958
|
breadth_first_search.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/breadth_first_search.h
|
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <optional>
#include <type_traits>
#include <boost/container/small_vector.hpp>
#include <queue>
#include "shader_recompiler/ir/value.h"
namespace Shader::IR {
// Use typename Instruction so the function can be used to return either const or mutable
// Insts depending on the context.
template <typename Instruction, typename Pred>
auto BreadthFirstSearch(Instruction* inst, Pred&& pred)
-> std::invoke_result_t<Pred, Instruction*> {
// Most often case the instruction is the desired already.
if (std::optional result = pred(inst)) {
return result;
}
// Breadth-first search visiting the right most arguments first
boost::container::small_vector<Instruction*, 2> visited;
std::queue<Instruction*> queue;
queue.push(inst);
while (!queue.empty()) {
// Pop one instruction from the queue
Instruction* inst{queue.front()};
queue.pop();
if (std::optional result = pred(inst)) {
// This is the instruction we were looking for
return result;
}
// Visit the right most arguments first
for (size_t arg = inst->NumArgs(); arg--;) {
Value arg_value{inst->Arg(arg)};
if (arg_value.IsImmediate()) {
continue;
}
// Queue instruction if it hasn't been visited
Instruction* arg_inst{arg_value.InstRecursive()};
if (std::ranges::find(visited, arg_inst) == visited.end()) {
visited.push_back(arg_inst);
queue.push(arg_inst);
}
}
}
// SSA tree has been traversed and the result hasn't been found
return std::nullopt;
}
template <typename Pred>
auto BreadthFirstSearch(const Value& value, Pred&& pred)
-> std::invoke_result_t<Pred, const Inst*> {
if (value.IsImmediate()) {
// Nothing to do with immediates
return std::nullopt;
}
return BreadthFirstSearch(value.InstRecursive(), pred);
}
template <typename Pred>
auto BreadthFirstSearch(Value value, Pred&& pred) -> std::invoke_result_t<Pred, Inst*> {
if (value.IsImmediate()) {
// Nothing to do with immediates
return std::nullopt;
}
return BreadthFirstSearch(value.InstRecursive(), pred);
}
} // namespace Shader::IR
| 2,497
|
C++
|
.h
| 65
| 30.969231
| 90
| 0.636288
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,959
|
condition.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/condition.h
|
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <fmt/format.h>
#include "common/types.h"
namespace Shader::IR {
enum class Condition : u32 {
False,
True,
Scc0,
Scc1,
Vccz,
Vccnz,
Execz,
Execnz,
};
constexpr std::string_view NameOf(Condition condition) {
switch (condition) {
case Condition::False:
return "False";
case Condition::True:
return "True";
case Condition::Scc0:
return "Scc0";
case Condition::Scc1:
return "Scc1";
case Condition::Vccz:
return "Vccz";
case Condition::Vccnz:
return "Vccnz";
case Condition::Execz:
return "Execz";
case Condition::Execnz:
return "Execnz";
}
}
} // namespace Shader::IR
template <>
struct fmt::formatter<Shader::IR::Condition> : formatter<std::string_view> {
auto format(const Shader::IR::Condition cond, format_context& ctx) const {
return formatter<string_view>::format(NameOf(cond), ctx);
}
};
| 1,080
|
C++
|
.h
| 43
| 20.418605
| 78
| 0.657282
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,960
|
basic_block.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/basic_block.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <initializer_list>
#include <map>
#include <span>
#include <vector>
#include <boost/intrusive/list.hpp>
#include "common/object_pool.h"
#include "common/types.h"
#include "shader_recompiler/ir/reg.h"
#include "shader_recompiler/ir/value.h"
namespace Shader::IR {
class Block {
public:
using InstructionList = boost::intrusive::list<Inst>;
using size_type = InstructionList::size_type;
using iterator = InstructionList::iterator;
using const_iterator = InstructionList::const_iterator;
using reverse_iterator = InstructionList::reverse_iterator;
using const_reverse_iterator = InstructionList::const_reverse_iterator;
explicit Block(Common::ObjectPool<Inst>& inst_pool_);
~Block();
Block(const Block&) = delete;
Block& operator=(const Block&) = delete;
Block(Block&&) = default;
Block& operator=(Block&&) = default;
/// Appends a new instruction to the end of this basic block.
void AppendNewInst(Opcode op, std::initializer_list<Value> args);
/// Prepends a copy of an instruction to this basic block before the insertion point.
iterator PrependNewInst(iterator insertion_point, const Inst& base_inst);
/// Prepends a new instruction to this basic block before the insertion point.
iterator PrependNewInst(iterator insertion_point, Opcode op,
std::initializer_list<Value> args = {}, u32 flags = 0);
/// Adds a new branch to this basic block.
void AddBranch(Block* block);
/// Gets a mutable reference to the instruction list for this basic block.
[[nodiscard]] InstructionList& Instructions() noexcept {
return instructions;
}
/// Gets an immutable reference to the instruction list for this basic block.
[[nodiscard]] const InstructionList& Instructions() const noexcept {
return instructions;
}
/// Gets an immutable span to the immediate predecessors.
[[nodiscard]] std::span<Block* const> ImmPredecessors() const noexcept {
return imm_predecessors;
}
/// Gets an immutable span to the immediate successors.
[[nodiscard]] std::span<Block* const> ImmSuccessors() const noexcept {
return imm_successors;
}
/// Intrusively store the host definition of this instruction.
template <typename T>
void SetDefinition(T def) {
definition = std::bit_cast<u32>(def);
}
/// Return the intrusively stored host definition of this instruction.
template <typename T>
[[nodiscard]] T Definition() const noexcept {
return std::bit_cast<T>(definition);
}
void SsaSeal() noexcept {
is_ssa_sealed = true;
}
[[nodiscard]] bool IsSsaSealed() const noexcept {
return is_ssa_sealed;
}
[[nodiscard]] bool empty() const {
return instructions.empty();
}
[[nodiscard]] size_type size() const {
return instructions.size();
}
[[nodiscard]] Inst& front() {
return instructions.front();
}
[[nodiscard]] const Inst& front() const {
return instructions.front();
}
[[nodiscard]] Inst& back() {
return instructions.back();
}
[[nodiscard]] const Inst& back() const {
return instructions.back();
}
[[nodiscard]] iterator begin() {
return instructions.begin();
}
[[nodiscard]] const_iterator begin() const {
return instructions.cbegin();
}
[[nodiscard]] iterator end() {
return instructions.end();
}
[[nodiscard]] const_iterator end() const {
return instructions.cend();
}
[[nodiscard]] reverse_iterator rbegin() {
return instructions.rbegin();
}
[[nodiscard]] const_reverse_iterator rbegin() const {
return instructions.rbegin();
}
[[nodiscard]] reverse_iterator rend() {
return instructions.rend();
}
[[nodiscard]] const_reverse_iterator rend() const {
return instructions.rend();
}
[[nodiscard]] const_iterator cbegin() const {
return instructions.cbegin();
}
[[nodiscard]] const_iterator cend() const {
return instructions.cend();
}
[[nodiscard]] const_reverse_iterator crbegin() const {
return instructions.crbegin();
}
[[nodiscard]] const_reverse_iterator crend() const {
return instructions.crend();
}
/// Intrusively store the value of a register in the block.
std::array<Value, NumScalarRegs> ssa_sreg_values;
std::array<Value, NumScalarRegs> ssa_sbit_values;
std::array<Value, NumVectorRegs> ssa_vreg_values;
bool has_multiple_predecessors{false};
private:
/// Memory pool for instruction list
Common::ObjectPool<Inst>* inst_pool;
/// List of instructions in this block
InstructionList instructions;
/// Block immediate predecessors
std::vector<Block*> imm_predecessors;
/// Block immediate successors
std::vector<Block*> imm_successors;
/// Intrusively store if the block is sealed in the SSA pass.
bool is_ssa_sealed{false};
/// Intrusively stored host definition of this block.
u32 definition{};
};
using BlockList = std::vector<Block*>;
[[nodiscard]] std::string DumpBlock(const Block& block);
[[nodiscard]] std::string DumpBlock(const Block& block,
const std::map<const Block*, size_t>& block_to_index,
std::map<const Inst*, size_t>& inst_to_index,
size_t& inst_index);
} // namespace Shader::IR
| 5,674
|
C++
|
.h
| 148
| 32.155405
| 89
| 0.667456
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,961
|
debug_print.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/debug_print.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include "common/bit_field.h"
#include "shader_recompiler/ir/opcodes.h"
#include "src/common/types.h"
#pragma once
namespace Shader::IR {
constexpr size_t DEBUGPRINT_NUM_FORMAT_ARGS = NumArgsOf(IR::Opcode::DebugPrint) - 1;
union DebugPrintFlags {
u32 raw;
// For now, only flag is the number of variadic format args actually used
// So bitfield not really needed
BitField<0, 32, u32> num_args;
};
} // namespace Shader::IR
| 556
|
C++
|
.h
| 15
| 34.666667
| 84
| 0.753731
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,962
|
type.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/type.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <string>
#include <fmt/format.h>
#include "common/enum.h"
namespace Shader::IR {
enum class Type {
Void = 0,
Opaque = 1 << 0,
ScalarReg = 1 << 1,
VectorReg = 1 << 2,
Attribute = 1 << 3,
SystemValue = 1 << 4,
U1 = 1 << 5,
U8 = 1 << 6,
U16 = 1 << 7,
U32 = 1 << 8,
U64 = 1 << 9,
F16 = 1 << 10,
F32 = 1 << 11,
F64 = 1 << 12,
U32x2 = 1 << 13,
U32x3 = 1 << 14,
U32x4 = 1 << 15,
F16x2 = 1 << 16,
F16x3 = 1 << 17,
F16x4 = 1 << 18,
F32x2 = 1 << 19,
F32x3 = 1 << 20,
F32x4 = 1 << 21,
F64x2 = 1 << 22,
F64x3 = 1 << 23,
F64x4 = 1 << 24,
StringLiteral = 1 << 25,
};
DECLARE_ENUM_FLAG_OPERATORS(Type)
[[nodiscard]] std::string NameOf(Type type);
[[nodiscard]] bool AreTypesCompatible(Type lhs, Type rhs) noexcept;
} // namespace Shader::IR
template <>
struct fmt::formatter<Shader::IR::Type> {
constexpr auto parse(format_parse_context& ctx) {
return ctx.begin();
}
auto format(Shader::IR::Type type, format_context& ctx) const {
return fmt::format_to(ctx.out(), "{}", Shader::IR::NameOf(type));
}
};
| 1,269
|
C++
|
.h
| 49
| 21.877551
| 73
| 0.575908
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,963
|
post_order.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/post_order.h
|
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/ir/abstract_syntax_list.h"
#include "shader_recompiler/ir/basic_block.h"
namespace Shader::IR {
BlockList PostOrder(const AbstractSyntaxNode& root);
} // namespace Shader::IR
| 330
|
C++
|
.h
| 8
| 39.625
| 63
| 0.804416
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,964
|
srt.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/passes/srt.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <boost/container/set.hpp>
#include <boost/container/small_vector.hpp>
#include "common/types.h"
namespace Shader {
using PFN_SrtWalker = void PS4_SYSV_ABI (*)(const u32* /*user_data*/, u32* /*flat_dst*/);
struct PersistentSrtInfo {
// Special case when fetch shader uses step rates.
struct SrtSharpReservation {
u32 sgpr_base;
u32 dword_offset;
u32 num_dwords;
};
PFN_SrtWalker walker_func{};
boost::container::small_vector<SrtSharpReservation, 2> srt_reservations;
u32 flattened_bufsize_dw = 16; // NumUserDataRegs
// Special case for fetch shaders because we don't generate IR to read from step rate buffers,
// so we won't see usage with GetUserData/ReadConst.
// Reserve space in the flattened buffer for a sharp ahead of time
u32 ReserveSharp(u32 sgpr_base, u32 dword_offset, u32 num_dwords) {
u32 rv = flattened_bufsize_dw;
srt_reservations.emplace_back(sgpr_base, dword_offset, num_dwords);
flattened_bufsize_dw += num_dwords;
return rv;
}
};
} // namespace Shader
| 1,213
|
C++
|
.h
| 29
| 37.137931
| 98
| 0.714528
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,965
|
ir_passes.h
|
shadps4-emu_shadPS4/src/shader_recompiler/ir/passes/ir_passes.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/ir/basic_block.h"
#include "shader_recompiler/ir/program.h"
namespace Shader::Optimization {
void SsaRewritePass(IR::BlockList& program);
void IdentityRemovalPass(IR::BlockList& program);
void DeadCodeEliminationPass(IR::Program& program);
void ConstantPropagationPass(IR::BlockList& program);
void FlattenExtendedUserdataPass(IR::Program& program);
void ResourceTrackingPass(IR::Program& program);
void CollectShaderInfoPass(IR::Program& program);
void LowerSharedMemToRegisters(IR::Program& program);
void RingAccessElimination(const IR::Program& program, const RuntimeInfo& runtime_info,
Stage stage);
} // namespace Shader::Optimization
| 826
|
C++
|
.h
| 17
| 45.705882
| 87
| 0.799751
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,966
|
copy_shader.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/copy_shader.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include <unordered_map>
#include "common/types.h"
#include "shader_recompiler/ir/attribute.h"
namespace Shader {
struct CopyShaderData {
std::unordered_map<u32, std::pair<Shader::IR::Attribute, u32>> attr_map;
u32 num_attrs{0};
};
CopyShaderData ParseCopyShader(std::span<const u32> code);
} // namespace Shader
| 469
|
C++
|
.h
| 14
| 31.428571
| 76
| 0.770089
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,967
|
structured_control_flow.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/structured_control_flow.h
|
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/frontend/control_flow_graph.h"
#include "shader_recompiler/ir/abstract_syntax_list.h"
#include "shader_recompiler/ir/basic_block.h"
#include "shader_recompiler/ir/value.h"
namespace Shader {
struct Info;
struct Profile;
struct RuntimeInfo;
} // namespace Shader
namespace Shader::Gcn {
[[nodiscard]] IR::AbstractSyntaxList BuildASL(Common::ObjectPool<IR::Inst>& inst_pool,
Common::ObjectPool<IR::Block>& block_pool, CFG& cfg,
Info& info, const RuntimeInfo& runtime_info,
const Profile& profile);
} // namespace Shader::Gcn
| 817
|
C++
|
.h
| 18
| 36.388889
| 98
| 0.655738
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,968
|
opcodes.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/opcodes.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/enum.h"
#include "common/types.h"
namespace Shader::Gcn {
enum class OpcodeSOP2 : u32 {
S_ADD_U32 = 0,
S_SUB_U32 = 1,
S_ADD_I32 = 2,
S_SUB_I32 = 3,
S_ADDC_U32 = 4,
S_SUBB_U32 = 5,
S_MIN_I32 = 6,
S_MIN_U32 = 7,
S_MAX_I32 = 8,
S_MAX_U32 = 9,
S_CSELECT_B32 = 10,
S_CSELECT_B64 = 11,
S_AND_B32 = 14,
S_AND_B64 = 15,
S_OR_B32 = 16,
S_OR_B64 = 17,
S_XOR_B32 = 18,
S_XOR_B64 = 19,
S_ANDN2_B32 = 20,
S_ANDN2_B64 = 21,
S_ORN2_B32 = 22,
S_ORN2_B64 = 23,
S_NAND_B32 = 24,
S_NAND_B64 = 25,
S_NOR_B32 = 26,
S_NOR_B64 = 27,
S_XNOR_B32 = 28,
S_XNOR_B64 = 29,
S_LSHL_B32 = 30,
S_LSHL_B64 = 31,
S_LSHR_B32 = 32,
S_LSHR_B64 = 33,
S_ASHR_I32 = 34,
S_ASHR_I64 = 35,
S_BFM_B32 = 36,
S_BFM_B64 = 37,
S_MUL_I32 = 38,
S_BFE_U32 = 39,
S_BFE_I32 = 40,
S_BFE_U64 = 41,
S_BFE_I64 = 42,
S_CBRANCH_G_FORK = 43,
S_ABSDIFF_I32 = 44,
OP_RANGE_SOP2 = S_ABSDIFF_I32 + 1,
};
enum class OpcodeSOPK : u32 {
S_MOVK_I32 = 0,
S_CMOVK_I32 = 2,
S_CMPK_EQ_I32 = 3,
S_CMPK_LG_I32 = 4,
S_CMPK_GT_I32 = 5,
S_CMPK_GE_I32 = 6,
S_CMPK_LT_I32 = 7,
S_CMPK_LE_I32 = 8,
S_CMPK_EQ_U32 = 9,
S_CMPK_LG_U32 = 10,
S_CMPK_GT_U32 = 11,
S_CMPK_GE_U32 = 12,
S_CMPK_LT_U32 = 13,
S_CMPK_LE_U32 = 14,
S_ADDK_I32 = 15,
S_MULK_I32 = 16,
S_CBRANCH_I_FORK = 17,
S_GETREG_B32 = 18,
S_SETREG_B32 = 19,
S_GETREG_REGRD_B32 = 20,
S_SETREG_IMM32_B32 = 21,
OP_RANGE_SOPK = S_SETREG_IMM32_B32 + 1,
};
enum class OpcodeSOP1 : u32 {
S_MOV_B32 = 3,
S_MOV_B64 = 4,
S_CMOV_B32 = 5,
S_CMOV_B64 = 6,
S_NOT_B32 = 7,
S_NOT_B64 = 8,
S_WQM_B32 = 9,
S_WQM_B64 = 10,
S_BREV_B32 = 11,
S_BREV_B64 = 12,
S_BCNT0_I32_B32 = 13,
S_BCNT0_I32_B64 = 14,
S_BCNT1_I32_B32 = 15,
S_BCNT1_I32_B64 = 16,
S_FF0_I32_B32 = 17,
S_FF0_I32_B64 = 18,
S_FF1_I32_B32 = 19,
S_FF1_I32_B64 = 20,
S_FLBIT_I32_B32 = 21,
S_FLBIT_I32_B64 = 22,
S_FLBIT_I32 = 23,
S_FLBIT_I32_I64 = 24,
S_SEXT_I32_I8 = 25,
S_SEXT_I32_I16 = 26,
S_BITSET0_B32 = 27,
S_BITSET0_B64 = 28,
S_BITSET1_B32 = 29,
S_BITSET1_B64 = 30,
S_GETPC_B64 = 31,
S_SETPC_B64 = 32,
S_SWAPPC_B64 = 33,
S_RFE_B64 = 34,
S_AND_SAVEEXEC_B64 = 36,
S_OR_SAVEEXEC_B64 = 37,
S_XOR_SAVEEXEC_B64 = 38,
S_ANDN2_SAVEEXEC_B64 = 39,
S_ORN2_SAVEEXEC_B64 = 40,
S_NAND_SAVEEXEC_B64 = 41,
S_NOR_SAVEEXEC_B64 = 42,
S_XNOR_SAVEEXEC_B64 = 43,
S_QUADMASK_B32 = 44,
S_QUADMASK_B64 = 45,
S_MOVRELS_B32 = 46,
S_MOVRELS_B64 = 47,
S_MOVRELD_B32 = 48,
S_MOVRELD_B64 = 49,
S_CBRANCH_JOIN = 50,
S_MOV_REGRD_B32 = 51,
S_ABS_I32 = 52,
S_MOV_FED_B32 = 53,
OP_RANGE_SOP1 = S_MOV_FED_B32 + 1,
};
enum class OpcodeSOPC : u32 {
S_CMP_EQ_I32 = 0,
S_CMP_LG_I32 = 1,
S_CMP_GT_I32 = 2,
S_CMP_GE_I32 = 3,
S_CMP_LT_I32 = 4,
S_CMP_LE_I32 = 5,
S_CMP_EQ_U32 = 6,
S_CMP_LG_U32 = 7,
S_CMP_GT_U32 = 8,
S_CMP_GE_U32 = 9,
S_CMP_LT_U32 = 10,
S_CMP_LE_U32 = 11,
S_BITCMP0_B32 = 12,
S_BITCMP1_B32 = 13,
S_BITCMP0_B64 = 14,
S_BITCMP1_B64 = 15,
S_SETVSKIP = 16,
OP_RANGE_SOPC = S_SETVSKIP + 1,
};
enum class OpcodeSOPP : u32 {
S_NOP = 0,
S_ENDPGM = 1,
S_BRANCH = 2,
S_CBRANCH_SCC0 = 4,
S_CBRANCH_SCC1 = 5,
S_CBRANCH_VCCZ = 6,
S_CBRANCH_VCCNZ = 7,
S_CBRANCH_EXECZ = 8,
S_CBRANCH_EXECNZ = 9,
S_BARRIER = 10,
S_SETKILL = 11,
S_WAITCNT = 12,
S_SETHALT = 13,
S_SLEEP = 14,
S_SETPRIO = 15,
S_SENDMSG = 16,
S_SENDMSGHALT = 17,
S_TRAP = 18,
S_ICACHE_INV = 19,
S_INCPERFLEVEL = 20,
S_DECPERFLEVEL = 21,
S_TTRACEDATA = 22,
S_CBRANCH_CDBGSYS = 23,
S_CBRANCH_CDBGUSER = 24,
S_CBRANCH_CDBGSYS_OR_USER = 25,
S_CBRANCH_CDBGSYS_AND_USER = 26,
OP_RANGE_SOPP = S_CBRANCH_CDBGSYS_AND_USER + 1,
};
enum class OpcodeSMRD : u32 {
S_LOAD_DWORD = 0,
S_LOAD_DWORDX2 = 1,
S_LOAD_DWORDX4 = 2,
S_LOAD_DWORDX8 = 3,
S_LOAD_DWORDX16 = 4,
S_BUFFER_LOAD_DWORD = 8,
S_BUFFER_LOAD_DWORDX2 = 9,
S_BUFFER_LOAD_DWORDX4 = 10,
S_BUFFER_LOAD_DWORDX8 = 11,
S_BUFFER_LOAD_DWORDX16 = 12,
S_DCACHE_INV_VOL = 29,
S_MEMTIME = 30,
S_DCACHE_INV = 31,
OP_RANGE_SMRD = S_DCACHE_INV + 1,
};
enum class OpcodeVOP2 : u32 {
V_CNDMASK_B32 = 0,
V_READLANE_B32 = 1,
V_WRITELANE_B32 = 2,
V_ADD_F32 = 3,
V_SUB_F32 = 4,
V_SUBREV_F32 = 5,
V_MAC_LEGACY_F32 = 6,
V_MUL_LEGACY_F32 = 7,
V_MUL_F32 = 8,
V_MUL_I32_I24 = 9,
V_MUL_HI_I32_I24 = 10,
V_MUL_U32_U24 = 11,
V_MUL_HI_U32_U24 = 12,
V_MIN_LEGACY_F32 = 13,
V_MAX_LEGACY_F32 = 14,
V_MIN_F32 = 15,
V_MAX_F32 = 16,
V_MIN_I32 = 17,
V_MAX_I32 = 18,
V_MIN_U32 = 19,
V_MAX_U32 = 20,
V_LSHR_B32 = 21,
V_LSHRREV_B32 = 22,
V_ASHR_I32 = 23,
V_ASHRREV_I32 = 24,
V_LSHL_B32 = 25,
V_LSHLREV_B32 = 26,
V_AND_B32 = 27,
V_OR_B32 = 28,
V_XOR_B32 = 29,
V_BFM_B32 = 30,
V_MAC_F32 = 31,
V_MADMK_F32 = 32,
V_MADAK_F32 = 33,
V_BCNT_U32_B32 = 34,
V_MBCNT_LO_U32_B32 = 35,
V_MBCNT_HI_U32_B32 = 36,
V_ADD_I32 = 37,
V_SUB_I32 = 38,
V_SUBREV_I32 = 39,
V_ADDC_U32 = 40,
V_SUBB_U32 = 41,
V_SUBBREV_U32 = 42,
V_LDEXP_F32 = 43,
V_CVT_PKACCUM_U8_F32 = 44,
V_CVT_PKNORM_I16_F32 = 45,
V_CVT_PKNORM_U16_F32 = 46,
V_CVT_PKRTZ_F16_F32 = 47,
V_CVT_PK_U16_U32 = 48,
V_CVT_PK_I16_I32 = 49,
OP_RANGE_VOP2 = V_CVT_PK_I16_I32 + 1,
};
enum class OpcodeVOP3 : u32 {
V_CMP_F_F32 = 0,
V_CMP_LT_F32 = 1,
V_CMP_EQ_F32 = 2,
V_CMP_LE_F32 = 3,
V_CMP_GT_F32 = 4,
V_CMP_LG_F32 = 5,
V_CMP_GE_F32 = 6,
V_CMP_O_F32 = 7,
V_CMP_U_F32 = 8,
V_CMP_NGE_F32 = 9,
V_CMP_NLG_F32 = 10,
V_CMP_NGT_F32 = 11,
V_CMP_NLE_F32 = 12,
V_CMP_NEQ_F32 = 13,
V_CMP_NLT_F32 = 14,
V_CMP_TRU_F32 = 15,
V_CMP_T_F32 = 15,
V_CMPX_F_F32 = 16,
V_CMPX_LT_F32 = 17,
V_CMPX_EQ_F32 = 18,
V_CMPX_LE_F32 = 19,
V_CMPX_GT_F32 = 20,
V_CMPX_LG_F32 = 21,
V_CMPX_GE_F32 = 22,
V_CMPX_O_F32 = 23,
V_CMPX_U_F32 = 24,
V_CMPX_NGE_F32 = 25,
V_CMPX_NLG_F32 = 26,
V_CMPX_NGT_F32 = 27,
V_CMPX_NLE_F32 = 28,
V_CMPX_NEQ_F32 = 29,
V_CMPX_NLT_F32 = 30,
V_CMPX_TRU_F32 = 31,
V_CMPX_T_F32 = 31,
V_CMP_F_F64 = 32,
V_CMP_LT_F64 = 33,
V_CMP_EQ_F64 = 34,
V_CMP_LE_F64 = 35,
V_CMP_GT_F64 = 36,
V_CMP_LG_F64 = 37,
V_CMP_GE_F64 = 38,
V_CMP_O_F64 = 39,
V_CMP_U_F64 = 40,
V_CMP_NGE_F64 = 41,
V_CMP_NLG_F64 = 42,
V_CMP_NGT_F64 = 43,
V_CMP_NLE_F64 = 44,
V_CMP_NEQ_F64 = 45,
V_CMP_NLT_F64 = 46,
V_CMP_TRU_F64 = 47,
V_CMP_T_F64 = 47,
V_CMPX_F_F64 = 48,
V_CMPX_LT_F64 = 49,
V_CMPX_EQ_F64 = 50,
V_CMPX_LE_F64 = 51,
V_CMPX_GT_F64 = 52,
V_CMPX_LG_F64 = 53,
V_CMPX_GE_F64 = 54,
V_CMPX_O_F64 = 55,
V_CMPX_U_F64 = 56,
V_CMPX_NGE_F64 = 57,
V_CMPX_NLG_F64 = 58,
V_CMPX_NGT_F64 = 59,
V_CMPX_NLE_F64 = 60,
V_CMPX_NEQ_F64 = 61,
V_CMPX_NLT_F64 = 62,
V_CMPX_TRU_F64 = 63,
V_CMPX_T_F64 = 63,
V_CMPS_F_F32 = 64,
V_CMPS_LT_F32 = 65,
V_CMPS_EQ_F32 = 66,
V_CMPS_LE_F32 = 67,
V_CMPS_GT_F32 = 68,
V_CMPS_LG_F32 = 69,
V_CMPS_GE_F32 = 70,
V_CMPS_O_F32 = 71,
V_CMPS_U_F32 = 72,
V_CMPS_NGE_F32 = 73,
V_CMPS_NLG_F32 = 74,
V_CMPS_NGT_F32 = 75,
V_CMPS_NLE_F32 = 76,
V_CMPS_NEQ_F32 = 77,
V_CMPS_NLT_F32 = 78,
V_CMPS_TRU_F32 = 79,
V_CMPS_T_F32 = 79,
V_CMPSX_F_F32 = 80,
V_CMPSX_LT_F32 = 81,
V_CMPSX_EQ_F32 = 82,
V_CMPSX_LE_F32 = 83,
V_CMPSX_GT_F32 = 84,
V_CMPSX_LG_F32 = 85,
V_CMPSX_GE_F32 = 86,
V_CMPSX_O_F32 = 87,
V_CMPSX_U_F32 = 88,
V_CMPSX_NGE_F32 = 89,
V_CMPSX_NLG_F32 = 90,
V_CMPSX_NGT_F32 = 91,
V_CMPSX_NLE_F32 = 92,
V_CMPSX_NEQ_F32 = 93,
V_CMPSX_NLT_F32 = 94,
V_CMPSX_TRU_F32 = 95,
V_CMPSX_T_F32 = 95,
V_CMPS_F_F64 = 96,
V_CMPS_LT_F64 = 97,
V_CMPS_EQ_F64 = 98,
V_CMPS_LE_F64 = 99,
V_CMPS_GT_F64 = 100,
V_CMPS_LG_F64 = 101,
V_CMPS_GE_F64 = 102,
V_CMPS_O_F64 = 103,
V_CMPS_U_F64 = 104,
V_CMPS_NGE_F64 = 105,
V_CMPS_NLG_F64 = 106,
V_CMPS_NGT_F64 = 107,
V_CMPS_NLE_F64 = 108,
V_CMPS_NEQ_F64 = 109,
V_CMPS_NLT_F64 = 110,
V_CMPS_TRU_F64 = 111,
V_CMPS_T_F64 = 111,
V_CMPSX_F_F64 = 112,
V_CMPSX_LT_F64 = 113,
V_CMPSX_EQ_F64 = 114,
V_CMPSX_LE_F64 = 115,
V_CMPSX_GT_F64 = 116,
V_CMPSX_LG_F64 = 117,
V_CMPSX_GE_F64 = 118,
V_CMPSX_O_F64 = 119,
V_CMPSX_U_F64 = 120,
V_CMPSX_NGE_F64 = 121,
V_CMPSX_NLG_F64 = 122,
V_CMPSX_NGT_F64 = 123,
V_CMPSX_NLE_F64 = 124,
V_CMPSX_NEQ_F64 = 125,
V_CMPSX_NLT_F64 = 126,
V_CMPSX_TRU_F64 = 127,
V_CMPSX_T_F64 = 127,
V_CMP_F_I32 = 128,
V_CMP_LT_I32 = 129,
V_CMP_EQ_I32 = 130,
V_CMP_LE_I32 = 131,
V_CMP_GT_I32 = 132,
V_CMP_LG_I32 = 133,
V_CMP_NE_I32 = 133,
V_CMP_GE_I32 = 134,
V_CMP_TRU_I32 = 135,
V_CMP_T_I32 = 135,
V_CMP_CLASS_F32 = 136,
V_CMPX_F_I32 = 144,
V_CMPX_LT_I32 = 145,
V_CMPX_EQ_I32 = 146,
V_CMPX_LE_I32 = 147,
V_CMPX_GT_I32 = 148,
V_CMPX_LG_I32 = 149,
V_CMPX_NE_I32 = 149,
V_CMPX_GE_I32 = 150,
V_CMPX_TRU_I32 = 151,
V_CMPX_T_I32 = 151,
V_CMPX_CLASS_F32 = 152,
V_CMP_F_I64 = 160,
V_CMP_LT_I64 = 161,
V_CMP_EQ_I64 = 162,
V_CMP_LE_I64 = 163,
V_CMP_GT_I64 = 164,
V_CMP_LG_I64 = 165,
V_CMP_NE_I64 = 165,
V_CMP_GE_I64 = 166,
V_CMP_TRU_I64 = 167,
V_CMP_T_I64 = 167,
V_CMP_CLASS_F64 = 168,
V_CMPX_F_I64 = 176,
V_CMPX_LT_I64 = 177,
V_CMPX_EQ_I64 = 178,
V_CMPX_LE_I64 = 179,
V_CMPX_GT_I64 = 180,
V_CMPX_LG_I64 = 181,
V_CMPX_NE_I64 = 181,
V_CMPX_GE_I64 = 182,
V_CMPX_TRU_I64 = 183,
V_CMPX_T_I64 = 183,
V_CMPX_CLASS_F64 = 184,
V_CMP_F_U32 = 192,
V_CMP_LT_U32 = 193,
V_CMP_EQ_U32 = 194,
V_CMP_LE_U32 = 195,
V_CMP_GT_U32 = 196,
V_CMP_LG_U32 = 197,
V_CMP_NE_U32 = 197,
V_CMP_GE_U32 = 198,
V_CMP_TRU_U32 = 199,
V_CMP_T_U32 = 199,
V_CMPX_F_U32 = 208,
V_CMPX_LT_U32 = 209,
V_CMPX_EQ_U32 = 210,
V_CMPX_LE_U32 = 211,
V_CMPX_GT_U32 = 212,
V_CMPX_LG_U32 = 213,
V_CMPX_NE_U32 = 213,
V_CMPX_GE_U32 = 214,
V_CMPX_TRU_U32 = 215,
V_CMPX_T_U32 = 215,
V_CMP_F_U64 = 224,
V_CMP_LT_U64 = 225,
V_CMP_EQ_U64 = 226,
V_CMP_LE_U64 = 227,
V_CMP_GT_U64 = 228,
V_CMP_LG_U64 = 229,
V_CMP_NE_U64 = 229,
V_CMP_GE_U64 = 230,
V_CMP_TRU_U64 = 231,
V_CMP_T_U64 = 231,
V_CMPX_F_U64 = 240,
V_CMPX_LT_U64 = 241,
V_CMPX_EQ_U64 = 242,
V_CMPX_LE_U64 = 243,
V_CMPX_GT_U64 = 244,
V_CMPX_LG_U64 = 245,
V_CMPX_NE_U64 = 245,
V_CMPX_GE_U64 = 246,
V_CMPX_TRU_U64 = 247,
V_CMPX_T_U64 = 247,
V_CNDMASK_B32 = 256,
V_READLANE_B32 = 257,
V_WRITELANE_B32 = 258,
V_ADD_F32 = 259,
V_SUB_F32 = 260,
V_SUBREV_F32 = 261,
V_MAC_LEGACY_F32 = 262,
V_MUL_LEGACY_F32 = 263,
V_MUL_F32 = 264,
V_MUL_I32_I24 = 265,
V_MUL_HI_I32_I24 = 266,
V_MUL_U32_U24 = 267,
V_MUL_HI_U32_U24 = 268,
V_MIN_LEGACY_F32 = 269,
V_MAX_LEGACY_F32 = 270,
V_MIN_F32 = 271,
V_MAX_F32 = 272,
V_MIN_I32 = 273,
V_MAX_I32 = 274,
V_MIN_U32 = 275,
V_MAX_U32 = 276,
V_LSHR_B32 = 277,
V_LSHRREV_B32 = 278,
V_ASHR_I32 = 279,
V_ASHRREV_I32 = 280,
V_LSHL_B32 = 281,
V_LSHLREV_B32 = 282,
V_AND_B32 = 283,
V_OR_B32 = 284,
V_XOR_B32 = 285,
V_BFM_B32 = 286,
V_MAC_F32 = 287,
V_MADMK_F32 = 288,
V_MADAK_F32 = 289,
V_BCNT_U32_B32 = 290,
V_MBCNT_LO_U32_B32 = 291,
V_MBCNT_HI_U32_B32 = 292,
V_ADD_I32 = 293,
V_SUB_I32 = 294,
V_SUBREV_I32 = 295,
V_ADDC_U32 = 296,
V_SUBB_U32 = 297,
V_SUBBREV_U32 = 298,
V_LDEXP_F32 = 299,
V_CVT_PKACCUM_U8_F32 = 300,
V_CVT_PKNORM_I16_F32 = 301,
V_CVT_PKNORM_U16_F32 = 302,
V_CVT_PKRTZ_F16_F32 = 303,
V_CVT_PK_U16_U32 = 304,
V_CVT_PK_I16_I32 = 305,
V_MAD_LEGACY_F32 = 320,
V_MAD_F32 = 321,
V_MAD_I32_I24 = 322,
V_MAD_U32_U24 = 323,
V_CUBEID_F32 = 324,
V_CUBESC_F32 = 325,
V_CUBETC_F32 = 326,
V_CUBEMA_F32 = 327,
V_BFE_U32 = 328,
V_BFE_I32 = 329,
V_BFI_B32 = 330,
V_FMA_F32 = 331,
V_FMA_F64 = 332,
V_LERP_U8 = 333,
V_ALIGNBIT_B32 = 334,
V_ALIGNBYTE_B32 = 335,
V_MULLIT_F32 = 336,
V_MIN3_F32 = 337,
V_MIN3_I32 = 338,
V_MIN3_U32 = 339,
V_MAX3_F32 = 340,
V_MAX3_I32 = 341,
V_MAX3_U32 = 342,
V_MED3_F32 = 343,
V_MED3_I32 = 344,
V_MED3_U32 = 345,
V_SAD_U8 = 346,
V_SAD_HI_U8 = 347,
V_SAD_U16 = 348,
V_SAD_U32 = 349,
V_CVT_PK_U8_F32 = 350,
V_DIV_FIXUP_F32 = 351,
V_DIV_FIXUP_F64 = 352,
V_LSHL_B64 = 353,
V_LSHR_B64 = 354,
V_ASHR_I64 = 355,
V_ADD_F64 = 356,
V_MUL_F64 = 357,
V_MIN_F64 = 358,
V_MAX_F64 = 359,
V_LDEXP_F64 = 360,
V_MUL_LO_U32 = 361,
V_MUL_HI_U32 = 362,
V_MUL_LO_I32 = 363,
V_MUL_HI_I32 = 364,
V_DIV_SCALE_F32 = 365,
V_DIV_SCALE_F64 = 366,
V_DIV_FMAS_F32 = 367,
V_DIV_FMAS_F64 = 368,
V_MSAD_U8 = 369,
V_QSAD_U8 = 370,
V_QSAD_PK_U16_U8 = 370,
V_MQSAD_U8 = 371,
V_MQSAD_PK_U16_U8 = 371,
V_TRIG_PREOP_F64 = 372,
V_MQSAD_U32_U8 = 373,
V_MAD_U64_U32 = 374,
V_MAD_I64_I32 = 375,
V_NOP = 384,
V_MOV_B32 = 385,
V_READFIRSTLANE_B32 = 386,
V_CVT_I32_F64 = 387,
V_CVT_F64_I32 = 388,
V_CVT_F32_I32 = 389,
V_CVT_F32_U32 = 390,
V_CVT_U32_F32 = 391,
V_CVT_I32_F32 = 392,
V_MOV_FED_B32 = 393,
V_CVT_F16_F32 = 394,
V_CVT_F32_F16 = 395,
V_CVT_RPI_I32_F32 = 396,
V_CVT_FLR_I32_F32 = 397,
V_CVT_OFF_F32_I4 = 398,
V_CVT_F32_F64 = 399,
V_CVT_F64_F32 = 400,
V_CVT_F32_UBYTE0 = 401,
V_CVT_F32_UBYTE1 = 402,
V_CVT_F32_UBYTE2 = 403,
V_CVT_F32_UBYTE3 = 404,
V_CVT_U32_F64 = 405,
V_CVT_F64_U32 = 406,
V_TRUNC_F64 = 407,
V_CEIL_F64 = 408,
V_RNDNE_F64 = 409,
V_FLOOR_F64 = 410,
V_FRACT_F32 = 416,
V_TRUNC_F32 = 417,
V_CEIL_F32 = 418,
V_RNDNE_F32 = 419,
V_FLOOR_F32 = 420,
V_EXP_F32 = 421,
V_LOG_CLAMP_F32 = 422,
V_LOG_F32 = 423,
V_RCP_CLAMP_F32 = 424,
V_RCP_LEGACY_F32 = 425,
V_RCP_F32 = 426,
V_RCP_IFLAG_F32 = 427,
V_RSQ_CLAMP_F32 = 428,
V_RSQ_LEGACY_F32 = 429,
V_RSQ_F32 = 430,
V_RCP_F64 = 431,
V_RCP_CLAMP_F64 = 432,
V_RSQ_F64 = 433,
V_RSQ_CLAMP_F64 = 434,
V_SQRT_F32 = 435,
V_SQRT_F64 = 436,
V_SIN_F32 = 437,
V_COS_F32 = 438,
V_NOT_B32 = 439,
V_BFREV_B32 = 440,
V_FFBH_U32 = 441,
V_FFBL_B32 = 442,
V_FFBH_I32 = 443,
V_FREXP_EXP_I32_F64 = 444,
V_FREXP_MANT_F64 = 445,
V_FRACT_F64 = 446,
V_FREXP_EXP_I32_F32 = 447,
V_FREXP_MANT_F32 = 448,
V_CLREXCP = 449,
V_MOVRELD_B32 = 450,
V_MOVRELS_B32 = 451,
V_MOVRELSD_B32 = 452,
V_LOG_LEGACY_F32 = 453,
V_EXP_LEGACY_F32 = 454,
OP_RANGE_VOP3 = V_EXP_LEGACY_F32 + 1,
};
enum class OpcodeVOP1 : u32 {
V_NOP = 0,
V_MOV_B32 = 1,
V_READFIRSTLANE_B32 = 2,
V_CVT_I32_F64 = 3,
V_CVT_F64_I32 = 4,
V_CVT_F32_I32 = 5,
V_CVT_F32_U32 = 6,
V_CVT_U32_F32 = 7,
V_CVT_I32_F32 = 8,
V_MOV_FED_B32 = 9,
V_CVT_F16_F32 = 10,
V_CVT_F32_F16 = 11,
V_CVT_RPI_I32_F32 = 12,
V_CVT_FLR_I32_F32 = 13,
V_CVT_OFF_F32_I4 = 14,
V_CVT_F32_F64 = 15,
V_CVT_F64_F32 = 16,
V_CVT_F32_UBYTE0 = 17,
V_CVT_F32_UBYTE1 = 18,
V_CVT_F32_UBYTE2 = 19,
V_CVT_F32_UBYTE3 = 20,
V_CVT_U32_F64 = 21,
V_CVT_F64_U32 = 22,
V_TRUNC_F64 = 23,
V_CEIL_F64 = 24,
V_RNDNE_F64 = 25,
V_FLOOR_F64 = 26,
V_FRACT_F32 = 32,
V_TRUNC_F32 = 33,
V_CEIL_F32 = 34,
V_RNDNE_F32 = 35,
V_FLOOR_F32 = 36,
V_EXP_F32 = 37,
V_LOG_CLAMP_F32 = 38,
V_LOG_F32 = 39,
V_RCP_CLAMP_F32 = 40,
V_RCP_LEGACY_F32 = 41,
V_RCP_F32 = 42,
V_RCP_IFLAG_F32 = 43,
V_RSQ_CLAMP_F32 = 44,
V_RSQ_LEGACY_F32 = 45,
V_RSQ_F32 = 46,
V_RCP_F64 = 47,
V_RCP_CLAMP_F64 = 48,
V_RSQ_F64 = 49,
V_RSQ_CLAMP_F64 = 50,
V_SQRT_F32 = 51,
V_SQRT_F64 = 52,
V_SIN_F32 = 53,
V_COS_F32 = 54,
V_NOT_B32 = 55,
V_BFREV_B32 = 56,
V_FFBH_U32 = 57,
V_FFBL_B32 = 58,
V_FFBH_I32 = 59,
V_FREXP_EXP_I32_F64 = 60,
V_FREXP_MANT_F64 = 61,
V_FRACT_F64 = 62,
V_FREXP_EXP_I32_F32 = 63,
V_FREXP_MANT_F32 = 64,
V_CLREXCP = 65,
V_MOVRELD_B32 = 66,
V_MOVRELS_B32 = 67,
V_MOVRELSD_B32 = 68,
V_LOG_LEGACY_F32 = 69,
V_EXP_LEGACY_F32 = 70,
OP_RANGE_VOP1 = V_EXP_LEGACY_F32 + 1,
};
enum class OpcodeVOPC : u32 {
V_CMP_F_F32 = 0,
V_CMP_LT_F32 = 1,
V_CMP_EQ_F32 = 2,
V_CMP_LE_F32 = 3,
V_CMP_GT_F32 = 4,
V_CMP_LG_F32 = 5,
V_CMP_GE_F32 = 6,
V_CMP_O_F32 = 7,
V_CMP_U_F32 = 8,
V_CMP_NGE_F32 = 9,
V_CMP_NLG_F32 = 10,
V_CMP_NGT_F32 = 11,
V_CMP_NLE_F32 = 12,
V_CMP_NEQ_F32 = 13,
V_CMP_NLT_F32 = 14,
V_CMP_TRU_F32 = 15,
V_CMP_T_F32 = 15,
V_CMPX_F_F32 = 16,
V_CMPX_LT_F32 = 17,
V_CMPX_EQ_F32 = 18,
V_CMPX_LE_F32 = 19,
V_CMPX_GT_F32 = 20,
V_CMPX_LG_F32 = 21,
V_CMPX_GE_F32 = 22,
V_CMPX_O_F32 = 23,
V_CMPX_U_F32 = 24,
V_CMPX_NGE_F32 = 25,
V_CMPX_NLG_F32 = 26,
V_CMPX_NGT_F32 = 27,
V_CMPX_NLE_F32 = 28,
V_CMPX_NEQ_F32 = 29,
V_CMPX_NLT_F32 = 30,
V_CMPX_TRU_F32 = 31,
V_CMPX_T_F32 = 31,
V_CMP_F_F64 = 32,
V_CMP_LT_F64 = 33,
V_CMP_EQ_F64 = 34,
V_CMP_LE_F64 = 35,
V_CMP_GT_F64 = 36,
V_CMP_LG_F64 = 37,
V_CMP_GE_F64 = 38,
V_CMP_O_F64 = 39,
V_CMP_U_F64 = 40,
V_CMP_NGE_F64 = 41,
V_CMP_NLG_F64 = 42,
V_CMP_NGT_F64 = 43,
V_CMP_NLE_F64 = 44,
V_CMP_NEQ_F64 = 45,
V_CMP_NLT_F64 = 46,
V_CMP_TRU_F64 = 47,
V_CMP_T_F64 = 47,
V_CMPX_F_F64 = 48,
V_CMPX_LT_F64 = 49,
V_CMPX_EQ_F64 = 50,
V_CMPX_LE_F64 = 51,
V_CMPX_GT_F64 = 52,
V_CMPX_LG_F64 = 53,
V_CMPX_GE_F64 = 54,
V_CMPX_O_F64 = 55,
V_CMPX_U_F64 = 56,
V_CMPX_NGE_F64 = 57,
V_CMPX_NLG_F64 = 58,
V_CMPX_NGT_F64 = 59,
V_CMPX_NLE_F64 = 60,
V_CMPX_NEQ_F64 = 61,
V_CMPX_NLT_F64 = 62,
V_CMPX_TRU_F64 = 63,
V_CMPX_T_F64 = 63,
V_CMPS_F_F32 = 64,
V_CMPS_LT_F32 = 65,
V_CMPS_EQ_F32 = 66,
V_CMPS_LE_F32 = 67,
V_CMPS_GT_F32 = 68,
V_CMPS_LG_F32 = 69,
V_CMPS_GE_F32 = 70,
V_CMPS_O_F32 = 71,
V_CMPS_U_F32 = 72,
V_CMPS_NGE_F32 = 73,
V_CMPS_NLG_F32 = 74,
V_CMPS_NGT_F32 = 75,
V_CMPS_NLE_F32 = 76,
V_CMPS_NEQ_F32 = 77,
V_CMPS_NLT_F32 = 78,
V_CMPS_TRU_F32 = 79,
V_CMPS_T_F32 = 79,
V_CMPSX_F_F32 = 80,
V_CMPSX_LT_F32 = 81,
V_CMPSX_EQ_F32 = 82,
V_CMPSX_LE_F32 = 83,
V_CMPSX_GT_F32 = 84,
V_CMPSX_LG_F32 = 85,
V_CMPSX_GE_F32 = 86,
V_CMPSX_O_F32 = 87,
V_CMPSX_U_F32 = 88,
V_CMPSX_NGE_F32 = 89,
V_CMPSX_NLG_F32 = 90,
V_CMPSX_NGT_F32 = 91,
V_CMPSX_NLE_F32 = 92,
V_CMPSX_NEQ_F32 = 93,
V_CMPSX_NLT_F32 = 94,
V_CMPSX_TRU_F32 = 95,
V_CMPSX_T_F32 = 95,
V_CMPS_F_F64 = 96,
V_CMPS_LT_F64 = 97,
V_CMPS_EQ_F64 = 98,
V_CMPS_LE_F64 = 99,
V_CMPS_GT_F64 = 100,
V_CMPS_LG_F64 = 101,
V_CMPS_GE_F64 = 102,
V_CMPS_O_F64 = 103,
V_CMPS_U_F64 = 104,
V_CMPS_NGE_F64 = 105,
V_CMPS_NLG_F64 = 106,
V_CMPS_NGT_F64 = 107,
V_CMPS_NLE_F64 = 108,
V_CMPS_NEQ_F64 = 109,
V_CMPS_NLT_F64 = 110,
V_CMPS_TRU_F64 = 111,
V_CMPS_T_F64 = 111,
V_CMPSX_F_F64 = 112,
V_CMPSX_LT_F64 = 113,
V_CMPSX_EQ_F64 = 114,
V_CMPSX_LE_F64 = 115,
V_CMPSX_GT_F64 = 116,
V_CMPSX_LG_F64 = 117,
V_CMPSX_GE_F64 = 118,
V_CMPSX_O_F64 = 119,
V_CMPSX_U_F64 = 120,
V_CMPSX_NGE_F64 = 121,
V_CMPSX_NLG_F64 = 122,
V_CMPSX_NGT_F64 = 123,
V_CMPSX_NLE_F64 = 124,
V_CMPSX_NEQ_F64 = 125,
V_CMPSX_NLT_F64 = 126,
V_CMPSX_TRU_F64 = 127,
V_CMPSX_T_F64 = 127,
V_CMP_F_I32 = 128,
V_CMP_LT_I32 = 129,
V_CMP_EQ_I32 = 130,
V_CMP_LE_I32 = 131,
V_CMP_GT_I32 = 132,
V_CMP_LG_I32 = 133,
V_CMP_NE_I32 = 133,
V_CMP_GE_I32 = 134,
V_CMP_TRU_I32 = 135,
V_CMP_T_I32 = 135,
V_CMP_CLASS_F32 = 136,
V_CMPX_F_I32 = 144,
V_CMPX_LT_I32 = 145,
V_CMPX_EQ_I32 = 146,
V_CMPX_LE_I32 = 147,
V_CMPX_GT_I32 = 148,
V_CMPX_LG_I32 = 149,
V_CMPX_NE_I32 = 149,
V_CMPX_GE_I32 = 150,
V_CMPX_TRU_I32 = 151,
V_CMPX_T_I32 = 151,
V_CMPX_CLASS_F32 = 152,
V_CMP_F_I64 = 160,
V_CMP_LT_I64 = 161,
V_CMP_EQ_I64 = 162,
V_CMP_LE_I64 = 163,
V_CMP_GT_I64 = 164,
V_CMP_LG_I64 = 165,
V_CMP_NE_I64 = 165,
V_CMP_GE_I64 = 166,
V_CMP_TRU_I64 = 167,
V_CMP_T_I64 = 167,
V_CMP_CLASS_F64 = 168,
V_CMPX_F_I64 = 176,
V_CMPX_LT_I64 = 177,
V_CMPX_EQ_I64 = 178,
V_CMPX_LE_I64 = 179,
V_CMPX_GT_I64 = 180,
V_CMPX_LG_I64 = 181,
V_CMPX_NE_I64 = 181,
V_CMPX_GE_I64 = 182,
V_CMPX_TRU_I64 = 183,
V_CMPX_T_I64 = 183,
V_CMPX_CLASS_F64 = 184,
V_CMP_F_U32 = 192,
V_CMP_LT_U32 = 193,
V_CMP_EQ_U32 = 194,
V_CMP_LE_U32 = 195,
V_CMP_GT_U32 = 196,
V_CMP_LG_U32 = 197,
V_CMP_NE_U32 = 197,
V_CMP_GE_U32 = 198,
V_CMP_TRU_U32 = 199,
V_CMP_T_U32 = 199,
V_CMPX_F_U32 = 208,
V_CMPX_LT_U32 = 209,
V_CMPX_EQ_U32 = 210,
V_CMPX_LE_U32 = 211,
V_CMPX_GT_U32 = 212,
V_CMPX_LG_U32 = 213,
V_CMPX_NE_U32 = 213,
V_CMPX_GE_U32 = 214,
V_CMPX_TRU_U32 = 215,
V_CMPX_T_U32 = 215,
V_CMP_F_U64 = 224,
V_CMP_LT_U64 = 225,
V_CMP_EQ_U64 = 226,
V_CMP_LE_U64 = 227,
V_CMP_GT_U64 = 228,
V_CMP_LG_U64 = 229,
V_CMP_NE_U64 = 229,
V_CMP_GE_U64 = 230,
V_CMP_TRU_U64 = 231,
V_CMP_T_U64 = 231,
V_CMPX_F_U64 = 240,
V_CMPX_LT_U64 = 241,
V_CMPX_EQ_U64 = 242,
V_CMPX_LE_U64 = 243,
V_CMPX_GT_U64 = 244,
V_CMPX_LG_U64 = 245,
V_CMPX_NE_U64 = 245,
V_CMPX_GE_U64 = 246,
V_CMPX_TRU_U64 = 247,
V_CMPX_T_U64 = 247,
OP_RANGE_VOPC = V_CMPX_T_U64 + 1,
};
enum class OpcodeVINTRP : u32 {
V_INTERP_P1_F32 = 0,
V_INTERP_P2_F32 = 1,
V_INTERP_MOV_F32 = 2,
OP_RANGE_VINTRP = V_INTERP_MOV_F32 + 1,
};
enum class OpcodeDS : u32 {
DS_ADD_U32 = 0,
DS_SUB_U32 = 1,
DS_RSUB_U32 = 2,
DS_INC_U32 = 3,
DS_DEC_U32 = 4,
DS_MIN_I32 = 5,
DS_MAX_I32 = 6,
DS_MIN_U32 = 7,
DS_MAX_U32 = 8,
DS_AND_B32 = 9,
DS_OR_B32 = 10,
DS_XOR_B32 = 11,
DS_MSKOR_B32 = 12,
DS_WRITE_B32 = 13,
DS_WRITE2_B32 = 14,
DS_WRITE2ST64_B32 = 15,
DS_CMPST_B32 = 16,
DS_CMPST_F32 = 17,
DS_MIN_F32 = 18,
DS_MAX_F32 = 19,
DS_NOP = 20,
DS_GWS_SEMA_RELEASE_ALL = 24,
DS_GWS_INIT = 25,
DS_GWS_SEMA_V = 26,
DS_GWS_SEMA_BR = 27,
DS_GWS_SEMA_P = 28,
DS_GWS_BARRIER = 29,
DS_WRITE_B8 = 30,
DS_WRITE_B16 = 31,
DS_ADD_RTN_U32 = 32,
DS_SUB_RTN_U32 = 33,
DS_RSUB_RTN_U32 = 34,
DS_INC_RTN_U32 = 35,
DS_DEC_RTN_U32 = 36,
DS_MIN_RTN_I32 = 37,
DS_MAX_RTN_I32 = 38,
DS_MIN_RTN_U32 = 39,
DS_MAX_RTN_U32 = 40,
DS_AND_RTN_B32 = 41,
DS_OR_RTN_B32 = 42,
DS_XOR_RTN_B32 = 43,
DS_MSKOR_RTN_B32 = 44,
DS_WRXCHG_RTN_B32 = 45,
DS_WRXCHG2_RTN_B32 = 46,
DS_WRXCHG2ST64_RTN_B32 = 47,
DS_CMPST_RTN_B32 = 48,
DS_CMPST_RTN_F32 = 49,
DS_MIN_RTN_F32 = 50,
DS_MAX_RTN_F32 = 51,
DS_WRAP_RTN_B32 = 52,
DS_SWIZZLE_B32 = 53,
DS_READ_B32 = 54,
DS_READ2_B32 = 55,
DS_READ2ST64_B32 = 56,
DS_READ_I8 = 57,
DS_READ_U8 = 58,
DS_READ_I16 = 59,
DS_READ_U16 = 60,
DS_CONSUME = 61,
DS_APPEND = 62,
DS_ORDERED_COUNT = 63,
DS_ADD_U64 = 64,
DS_SUB_U64 = 65,
DS_RSUB_U64 = 66,
DS_INC_U64 = 67,
DS_DEC_U64 = 68,
DS_MIN_I64 = 69,
DS_MAX_I64 = 70,
DS_MIN_U64 = 71,
DS_MAX_U64 = 72,
DS_AND_B64 = 73,
DS_OR_B64 = 74,
DS_XOR_B64 = 75,
DS_MSKOR_B64 = 76,
DS_WRITE_B64 = 77,
DS_WRITE2_B64 = 78,
DS_WRITE2ST64_B64 = 79,
DS_CMPST_B64 = 80,
DS_CMPST_F64 = 81,
DS_MIN_F64 = 82,
DS_MAX_F64 = 83,
DS_ADD_RTN_U64 = 96,
DS_SUB_RTN_U64 = 97,
DS_RSUB_RTN_U64 = 98,
DS_INC_RTN_U64 = 99,
DS_DEC_RTN_U64 = 100,
DS_MIN_RTN_I64 = 101,
DS_MAX_RTN_I64 = 102,
DS_MIN_RTN_U64 = 103,
DS_MAX_RTN_U64 = 104,
DS_AND_RTN_B64 = 105,
DS_OR_RTN_B64 = 106,
DS_XOR_RTN_B64 = 107,
DS_MSKOR_RTN_B64 = 108,
DS_WRXCHG_RTN_B64 = 109,
DS_WRXCHG2_RTN_B64 = 110,
DS_WRXCHG2ST64_RTN_B64 = 111,
DS_CMPST_RTN_B64 = 112,
DS_CMPST_RTN_F64 = 113,
DS_MIN_RTN_F64 = 114,
DS_MAX_RTN_F64 = 115,
DS_READ_B64 = 118,
DS_READ2_B64 = 119,
DS_READ2ST64_B64 = 120,
DS_CONDXCHG32_RTN_B64 = 126,
DS_ADD_SRC2_U32 = 128,
DS_SUB_SRC2_U32 = 129,
DS_RSUB_SRC2_U32 = 130,
DS_INC_SRC2_U32 = 131,
DS_DEC_SRC2_U32 = 132,
DS_MIN_SRC2_I32 = 133,
DS_MAX_SRC2_I32 = 134,
DS_MIN_SRC2_U32 = 135,
DS_MAX_SRC2_U32 = 136,
DS_AND_SRC2_B32 = 137,
DS_OR_SRC2_B32 = 138,
DS_XOR_SRC2_B32 = 139,
DS_WRITE_SRC2_B32 = 141,
DS_MIN_SRC2_F32 = 146,
DS_MAX_SRC2_F32 = 147,
DS_ADD_SRC2_U64 = 192,
DS_SUB_SRC2_U64 = 193,
DS_RSUB_SRC2_U64 = 194,
DS_INC_SRC2_U64 = 195,
DS_DEC_SRC2_U64 = 196,
DS_MIN_SRC2_I64 = 197,
DS_MAX_SRC2_I64 = 198,
DS_MIN_SRC2_U64 = 199,
DS_MAX_SRC2_U64 = 200,
DS_AND_SRC2_B64 = 201,
DS_OR_SRC2_B64 = 202,
DS_XOR_SRC2_B64 = 203,
DS_WRITE_SRC2_B64 = 205,
DS_MIN_SRC2_F64 = 210,
DS_MAX_SRC2_F64 = 211,
DS_WRITE_B96 = 222,
DS_WRITE_B128 = 223,
DS_CONDXCHG32_RTN_B128 = 253,
DS_READ_B96 = 254,
DS_READ_B128 = 255,
OP_RANGE_DS = DS_READ_B128 + 1,
};
enum class OpcodeMUBUF : u32 {
BUFFER_LOAD_FORMAT_X = 0,
BUFFER_LOAD_FORMAT_XY = 1,
BUFFER_LOAD_FORMAT_XYZ = 2,
BUFFER_LOAD_FORMAT_XYZW = 3,
BUFFER_STORE_FORMAT_X = 4,
BUFFER_STORE_FORMAT_XY = 5,
BUFFER_STORE_FORMAT_XYZ = 6,
BUFFER_STORE_FORMAT_XYZW = 7,
BUFFER_LOAD_UBYTE = 8,
BUFFER_LOAD_SBYTE = 9,
BUFFER_LOAD_USHORT = 10,
BUFFER_LOAD_SSHORT = 11,
BUFFER_LOAD_DWORD = 12,
BUFFER_LOAD_DWORDX2 = 13,
BUFFER_LOAD_DWORDX4 = 14,
BUFFER_LOAD_DWORDX3 = 15,
BUFFER_STORE_BYTE = 24,
BUFFER_STORE_SHORT = 26,
BUFFER_STORE_DWORD = 28,
BUFFER_STORE_DWORDX2 = 29,
BUFFER_STORE_DWORDX4 = 30,
BUFFER_STORE_DWORDX3 = 31,
BUFFER_ATOMIC_SWAP = 48,
BUFFER_ATOMIC_CMPSWAP = 49,
BUFFER_ATOMIC_ADD = 50,
BUFFER_ATOMIC_SUB = 51,
BUFFER_ATOMIC_SMIN = 53,
BUFFER_ATOMIC_UMIN = 54,
BUFFER_ATOMIC_SMAX = 55,
BUFFER_ATOMIC_UMAX = 56,
BUFFER_ATOMIC_AND = 57,
BUFFER_ATOMIC_OR = 58,
BUFFER_ATOMIC_XOR = 59,
BUFFER_ATOMIC_INC = 60,
BUFFER_ATOMIC_DEC = 61,
BUFFER_ATOMIC_FCMPSWAP = 62,
BUFFER_ATOMIC_FMIN = 63,
BUFFER_ATOMIC_FMAX = 64,
BUFFER_ATOMIC_SWAP_X2 = 80,
BUFFER_ATOMIC_CMPSWAP_X2 = 81,
BUFFER_ATOMIC_ADD_X2 = 82,
BUFFER_ATOMIC_SUB_X2 = 83,
BUFFER_ATOMIC_SMIN_X2 = 85,
BUFFER_ATOMIC_UMIN_X2 = 86,
BUFFER_ATOMIC_SMAX_X2 = 87,
BUFFER_ATOMIC_UMAX_X2 = 88,
BUFFER_ATOMIC_AND_X2 = 89,
BUFFER_ATOMIC_OR_X2 = 90,
BUFFER_ATOMIC_XOR_X2 = 91,
BUFFER_ATOMIC_INC_X2 = 92,
BUFFER_ATOMIC_DEC_X2 = 93,
BUFFER_ATOMIC_FCMPSWAP_X2 = 94,
BUFFER_ATOMIC_FMIN_X2 = 95,
BUFFER_ATOMIC_FMAX_X2 = 96,
BUFFER_WBINVL1_SC = 112,
BUFFER_WBINVL1 = 113,
OP_RANGE_MUBUF = BUFFER_WBINVL1 + 1,
};
enum class OpcodeMTBUF : u32 {
TBUFFER_LOAD_FORMAT_X = 0,
TBUFFER_LOAD_FORMAT_XY = 1,
TBUFFER_LOAD_FORMAT_XYZ = 2,
TBUFFER_LOAD_FORMAT_XYZW = 3,
TBUFFER_STORE_FORMAT_X = 4,
TBUFFER_STORE_FORMAT_XY = 5,
TBUFFER_STORE_FORMAT_XYZ = 6,
TBUFFER_STORE_FORMAT_XYZW = 7,
OP_RANGE_MTBUF = TBUFFER_STORE_FORMAT_XYZW + 1,
};
enum class OpcodeMIMG : u32 {
IMAGE_LOAD = 0,
IMAGE_LOAD_MIP = 1,
IMAGE_LOAD_PCK = 2,
IMAGE_LOAD_PCK_SGN = 3,
IMAGE_LOAD_MIP_PCK = 4,
IMAGE_LOAD_MIP_PCK_SGN = 5,
IMAGE_STORE = 8,
IMAGE_STORE_MIP = 9,
IMAGE_STORE_PCK = 10,
IMAGE_STORE_MIP_PCK = 11,
IMAGE_GET_RESINFO = 14,
IMAGE_ATOMIC_SWAP = 15,
IMAGE_ATOMIC_CMPSWAP = 16,
IMAGE_ATOMIC_ADD = 17,
IMAGE_ATOMIC_SUB = 18,
IMAGE_ATOMIC_SMIN = 20,
IMAGE_ATOMIC_UMIN = 21,
IMAGE_ATOMIC_SMAX = 22,
IMAGE_ATOMIC_UMAX = 23,
IMAGE_ATOMIC_AND = 24,
IMAGE_ATOMIC_OR = 25,
IMAGE_ATOMIC_XOR = 26,
IMAGE_ATOMIC_INC = 27,
IMAGE_ATOMIC_DEC = 28,
IMAGE_ATOMIC_FCMPSWAP = 29,
IMAGE_ATOMIC_FMIN = 30,
IMAGE_ATOMIC_FMAX = 31,
IMAGE_SAMPLE = 32,
IMAGE_SAMPLE_CL = 33,
IMAGE_SAMPLE_D = 34,
IMAGE_SAMPLE_D_CL = 35,
IMAGE_SAMPLE_L = 36,
IMAGE_SAMPLE_B = 37,
IMAGE_SAMPLE_B_CL = 38,
IMAGE_SAMPLE_LZ = 39,
IMAGE_SAMPLE_C = 40,
IMAGE_SAMPLE_C_CL = 41,
IMAGE_SAMPLE_C_D = 42,
IMAGE_SAMPLE_C_D_CL = 43,
IMAGE_SAMPLE_C_L = 44,
IMAGE_SAMPLE_C_B = 45,
IMAGE_SAMPLE_C_B_CL = 46,
IMAGE_SAMPLE_C_LZ = 47,
IMAGE_SAMPLE_O = 48,
IMAGE_SAMPLE_CL_O = 49,
IMAGE_SAMPLE_D_O = 50,
IMAGE_SAMPLE_D_CL_O = 51,
IMAGE_SAMPLE_L_O = 52,
IMAGE_SAMPLE_B_O = 53,
IMAGE_SAMPLE_B_CL_O = 54,
IMAGE_SAMPLE_LZ_O = 55,
IMAGE_SAMPLE_C_O = 56,
IMAGE_SAMPLE_C_CL_O = 57,
IMAGE_SAMPLE_C_D_O = 58,
IMAGE_SAMPLE_C_D_CL_O = 59,
IMAGE_SAMPLE_C_L_O = 60,
IMAGE_SAMPLE_C_B_O = 61,
IMAGE_SAMPLE_C_B_CL_O = 62,
IMAGE_SAMPLE_C_LZ_O = 63,
IMAGE_GATHER4 = 64,
IMAGE_GATHER4_CL = 65,
IMAGE_GATHER4_L = 68,
IMAGE_GATHER4_B = 69,
IMAGE_GATHER4_B_CL = 70,
IMAGE_GATHER4_LZ = 71,
IMAGE_GATHER4_C = 72,
IMAGE_GATHER4_C_CL = 73,
IMAGE_GATHER4_C_L = 76,
IMAGE_GATHER4_C_B = 77,
IMAGE_GATHER4_C_B_CL = 78,
IMAGE_GATHER4_C_LZ = 79,
IMAGE_GATHER4_O = 80,
IMAGE_GATHER4_CL_O = 81,
IMAGE_GATHER4_L_O = 84,
IMAGE_GATHER4_B_O = 85,
IMAGE_GATHER4_B_CL_O = 86,
IMAGE_GATHER4_LZ_O = 87,
IMAGE_GATHER4_C_O = 88,
IMAGE_GATHER4_C_CL_O = 89,
IMAGE_GATHER4_C_L_O = 92,
IMAGE_GATHER4_C_B_O = 93,
IMAGE_GATHER4_C_B_CL_O = 94,
IMAGE_GATHER4_C_LZ_O = 95,
IMAGE_GET_LOD = 96,
IMAGE_SAMPLE_CD = 104,
IMAGE_SAMPLE_CD_CL = 105,
IMAGE_SAMPLE_C_CD = 106,
IMAGE_SAMPLE_C_CD_CL = 107,
IMAGE_SAMPLE_CD_O = 108,
IMAGE_SAMPLE_CD_CL_O = 109,
IMAGE_SAMPLE_C_CD_O = 110,
IMAGE_SAMPLE_C_CD_CL_O = 111,
OP_RANGE_MIMG = IMAGE_SAMPLE_C_CD_CL_O + 1,
};
enum class OpcodeEXP : u32 {
EXP = 0,
OP_RANGE_EXP = EXP + 1,
};
// Use to map VOP3 opcodes into VOP1, VOP2, VOPC
enum class OpMapVOP3VOPX : u32 {
VOP3_TO_VOPC = 0,
VOP3_TO_VOP2 = 256,
VOP3_TO_VOP1 = 384,
};
// Use to map all opcodes into a single enum
enum class OpcodeMap : u32 {
OP_MAP_SOP2 = 0,
OP_MAP_SOPK = OP_MAP_SOP2 + (u32)OpcodeSOP2::OP_RANGE_SOP2,
OP_MAP_SOP1 = OP_MAP_SOPK + (u32)OpcodeSOPK::OP_RANGE_SOPK,
OP_MAP_SOPC = OP_MAP_SOP1 + (u32)OpcodeSOP1::OP_RANGE_SOP1,
OP_MAP_SOPP = OP_MAP_SOPC + (u32)OpcodeSOPC::OP_RANGE_SOPC,
OP_MAP_VOPC = OP_MAP_SOPP + (u32)OpcodeSOPP::OP_RANGE_SOPP,
OP_MAP_VOP2 = OP_MAP_VOPC + (u32)OpcodeVOPC::OP_RANGE_VOPC,
OP_MAP_VOP1 = OP_MAP_VOP2 + (u32)OpcodeVOP2::OP_RANGE_VOP2,
OP_MAP_VOP3 = OP_MAP_VOP1 + (u32)OpcodeVOP1::OP_RANGE_VOP1,
OP_MAP_VINTRP = OP_MAP_VOP3 + (u32)OpcodeVOP3::OP_RANGE_VOP3,
OP_MAP_SMRD = OP_MAP_VINTRP + (u32)OpcodeVINTRP::OP_RANGE_VINTRP,
OP_MAP_DS = OP_MAP_SMRD + (u32)OpcodeSMRD::OP_RANGE_SMRD,
OP_MAP_MUBUF = OP_MAP_DS + (u32)OpcodeDS::OP_RANGE_DS,
OP_MAP_MTBUF = OP_MAP_MUBUF + (u32)OpcodeMUBUF::OP_RANGE_MUBUF,
OP_MAP_MIMG = OP_MAP_MTBUF + (u32)OpcodeMTBUF::OP_RANGE_MTBUF,
OP_MAP_EXP = OP_MAP_MIMG + (u32)OpcodeMIMG::OP_RANGE_MIMG,
};
enum class Opcode : u32 {
// SOP2
S_ADD_U32 = 0 + (u32)OpcodeMap::OP_MAP_SOP2,
S_SUB_U32 = 1 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ADD_I32 = 2 + (u32)OpcodeMap::OP_MAP_SOP2,
S_SUB_I32 = 3 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ADDC_U32 = 4 + (u32)OpcodeMap::OP_MAP_SOP2,
S_SUBB_U32 = 5 + (u32)OpcodeMap::OP_MAP_SOP2,
S_MIN_I32 = 6 + (u32)OpcodeMap::OP_MAP_SOP2,
S_MIN_U32 = 7 + (u32)OpcodeMap::OP_MAP_SOP2,
S_MAX_I32 = 8 + (u32)OpcodeMap::OP_MAP_SOP2,
S_MAX_U32 = 9 + (u32)OpcodeMap::OP_MAP_SOP2,
S_CSELECT_B32 = 10 + (u32)OpcodeMap::OP_MAP_SOP2,
S_CSELECT_B64 = 11 + (u32)OpcodeMap::OP_MAP_SOP2,
S_AND_B32 = 14 + (u32)OpcodeMap::OP_MAP_SOP2,
S_AND_B64 = 15 + (u32)OpcodeMap::OP_MAP_SOP2,
S_OR_B32 = 16 + (u32)OpcodeMap::OP_MAP_SOP2,
S_OR_B64 = 17 + (u32)OpcodeMap::OP_MAP_SOP2,
S_XOR_B32 = 18 + (u32)OpcodeMap::OP_MAP_SOP2,
S_XOR_B64 = 19 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ANDN2_B32 = 20 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ANDN2_B64 = 21 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ORN2_B32 = 22 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ORN2_B64 = 23 + (u32)OpcodeMap::OP_MAP_SOP2,
S_NAND_B32 = 24 + (u32)OpcodeMap::OP_MAP_SOP2,
S_NAND_B64 = 25 + (u32)OpcodeMap::OP_MAP_SOP2,
S_NOR_B32 = 26 + (u32)OpcodeMap::OP_MAP_SOP2,
S_NOR_B64 = 27 + (u32)OpcodeMap::OP_MAP_SOP2,
S_XNOR_B32 = 28 + (u32)OpcodeMap::OP_MAP_SOP2,
S_XNOR_B64 = 29 + (u32)OpcodeMap::OP_MAP_SOP2,
S_LSHL_B32 = 30 + (u32)OpcodeMap::OP_MAP_SOP2,
S_LSHL_B64 = 31 + (u32)OpcodeMap::OP_MAP_SOP2,
S_LSHR_B32 = 32 + (u32)OpcodeMap::OP_MAP_SOP2,
S_LSHR_B64 = 33 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ASHR_I32 = 34 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ASHR_I64 = 35 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFM_B32 = 36 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFM_B64 = 37 + (u32)OpcodeMap::OP_MAP_SOP2,
S_MUL_I32 = 38 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFE_U32 = 39 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFE_I32 = 40 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFE_U64 = 41 + (u32)OpcodeMap::OP_MAP_SOP2,
S_BFE_I64 = 42 + (u32)OpcodeMap::OP_MAP_SOP2,
S_CBRANCH_G_FORK = 43 + (u32)OpcodeMap::OP_MAP_SOP2,
S_ABSDIFF_I32 = 44 + (u32)OpcodeMap::OP_MAP_SOP2,
// SOPK
S_MOVK_I32 = 0 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMOVK_I32 = 2 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_EQ_I32 = 3 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LG_I32 = 4 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_GT_I32 = 5 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_GE_I32 = 6 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LT_I32 = 7 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LE_I32 = 8 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_EQ_U32 = 9 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LG_U32 = 10 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_GT_U32 = 11 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_GE_U32 = 12 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LT_U32 = 13 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CMPK_LE_U32 = 14 + (u32)OpcodeMap::OP_MAP_SOPK,
S_ADDK_I32 = 15 + (u32)OpcodeMap::OP_MAP_SOPK,
S_MULK_I32 = 16 + (u32)OpcodeMap::OP_MAP_SOPK,
S_CBRANCH_I_FORK = 17 + (u32)OpcodeMap::OP_MAP_SOPK,
S_GETREG_B32 = 18 + (u32)OpcodeMap::OP_MAP_SOPK,
S_SETREG_B32 = 19 + (u32)OpcodeMap::OP_MAP_SOPK,
S_GETREG_REGRD_B32 = 20 + (u32)OpcodeMap::OP_MAP_SOPK,
S_SETREG_IMM32_B32 = 21 + (u32)OpcodeMap::OP_MAP_SOPK,
// SOP1
S_MOV_B32 = 3 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOV_B64 = 4 + (u32)OpcodeMap::OP_MAP_SOP1,
S_CMOV_B32 = 5 + (u32)OpcodeMap::OP_MAP_SOP1,
S_CMOV_B64 = 6 + (u32)OpcodeMap::OP_MAP_SOP1,
S_NOT_B32 = 7 + (u32)OpcodeMap::OP_MAP_SOP1,
S_NOT_B64 = 8 + (u32)OpcodeMap::OP_MAP_SOP1,
S_WQM_B32 = 9 + (u32)OpcodeMap::OP_MAP_SOP1,
S_WQM_B64 = 10 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BREV_B32 = 11 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BREV_B64 = 12 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BCNT0_I32_B32 = 13 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BCNT0_I32_B64 = 14 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BCNT1_I32_B32 = 15 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BCNT1_I32_B64 = 16 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FF0_I32_B32 = 17 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FF0_I32_B64 = 18 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FF1_I32_B32 = 19 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FF1_I32_B64 = 20 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FLBIT_I32_B32 = 21 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FLBIT_I32_B64 = 22 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FLBIT_I32 = 23 + (u32)OpcodeMap::OP_MAP_SOP1,
S_FLBIT_I32_I64 = 24 + (u32)OpcodeMap::OP_MAP_SOP1,
S_SEXT_I32_I8 = 25 + (u32)OpcodeMap::OP_MAP_SOP1,
S_SEXT_I32_I16 = 26 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BITSET0_B32 = 27 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BITSET0_B64 = 28 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BITSET1_B32 = 29 + (u32)OpcodeMap::OP_MAP_SOP1,
S_BITSET1_B64 = 30 + (u32)OpcodeMap::OP_MAP_SOP1,
S_GETPC_B64 = 31 + (u32)OpcodeMap::OP_MAP_SOP1,
S_SETPC_B64 = 32 + (u32)OpcodeMap::OP_MAP_SOP1,
S_SWAPPC_B64 = 33 + (u32)OpcodeMap::OP_MAP_SOP1,
S_RFE_B64 = 34 + (u32)OpcodeMap::OP_MAP_SOP1,
S_AND_SAVEEXEC_B64 = 36 + (u32)OpcodeMap::OP_MAP_SOP1,
S_OR_SAVEEXEC_B64 = 37 + (u32)OpcodeMap::OP_MAP_SOP1,
S_XOR_SAVEEXEC_B64 = 38 + (u32)OpcodeMap::OP_MAP_SOP1,
S_ANDN2_SAVEEXEC_B64 = 39 + (u32)OpcodeMap::OP_MAP_SOP1,
S_ORN2_SAVEEXEC_B64 = 40 + (u32)OpcodeMap::OP_MAP_SOP1,
S_NAND_SAVEEXEC_B64 = 41 + (u32)OpcodeMap::OP_MAP_SOP1,
S_NOR_SAVEEXEC_B64 = 42 + (u32)OpcodeMap::OP_MAP_SOP1,
S_XNOR_SAVEEXEC_B64 = 43 + (u32)OpcodeMap::OP_MAP_SOP1,
S_QUADMASK_B32 = 44 + (u32)OpcodeMap::OP_MAP_SOP1,
S_QUADMASK_B64 = 45 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOVRELS_B32 = 46 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOVRELS_B64 = 47 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOVRELD_B32 = 48 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOVRELD_B64 = 49 + (u32)OpcodeMap::OP_MAP_SOP1,
S_CBRANCH_JOIN = 50 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOV_REGRD_B32 = 51 + (u32)OpcodeMap::OP_MAP_SOP1,
S_ABS_I32 = 52 + (u32)OpcodeMap::OP_MAP_SOP1,
S_MOV_FED_B32 = 53 + (u32)OpcodeMap::OP_MAP_SOP1,
// SOPC
S_CMP_EQ_I32 = 0 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LG_I32 = 1 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_GT_I32 = 2 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_GE_I32 = 3 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LT_I32 = 4 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LE_I32 = 5 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_EQ_U32 = 6 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LG_U32 = 7 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_GT_U32 = 8 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_GE_U32 = 9 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LT_U32 = 10 + (u32)OpcodeMap::OP_MAP_SOPC,
S_CMP_LE_U32 = 11 + (u32)OpcodeMap::OP_MAP_SOPC,
S_BITCMP0_B32 = 12 + (u32)OpcodeMap::OP_MAP_SOPC,
S_BITCMP1_B32 = 13 + (u32)OpcodeMap::OP_MAP_SOPC,
S_BITCMP0_B64 = 14 + (u32)OpcodeMap::OP_MAP_SOPC,
S_BITCMP1_B64 = 15 + (u32)OpcodeMap::OP_MAP_SOPC,
S_SETVSKIP = 16 + (u32)OpcodeMap::OP_MAP_SOPC,
// SOPP
S_NOP = 0 + (u32)OpcodeMap::OP_MAP_SOPP,
S_ENDPGM = 1 + (u32)OpcodeMap::OP_MAP_SOPP,
S_BRANCH = 2 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_SCC0 = 4 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_SCC1 = 5 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_VCCZ = 6 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_VCCNZ = 7 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_EXECZ = 8 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_EXECNZ = 9 + (u32)OpcodeMap::OP_MAP_SOPP,
S_BARRIER = 10 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SETKILL = 11 + (u32)OpcodeMap::OP_MAP_SOPP,
S_WAITCNT = 12 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SETHALT = 13 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SLEEP = 14 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SETPRIO = 15 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SENDMSG = 16 + (u32)OpcodeMap::OP_MAP_SOPP,
S_SENDMSGHALT = 17 + (u32)OpcodeMap::OP_MAP_SOPP,
S_TRAP = 18 + (u32)OpcodeMap::OP_MAP_SOPP,
S_ICACHE_INV = 19 + (u32)OpcodeMap::OP_MAP_SOPP,
S_INCPERFLEVEL = 20 + (u32)OpcodeMap::OP_MAP_SOPP,
S_DECPERFLEVEL = 21 + (u32)OpcodeMap::OP_MAP_SOPP,
S_TTRACEDATA = 22 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_CDBGSYS = 23 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_CDBGUSER = 24 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_CDBGSYS_OR_USER = 25 + (u32)OpcodeMap::OP_MAP_SOPP,
S_CBRANCH_CDBGSYS_AND_USER = 26 + (u32)OpcodeMap::OP_MAP_SOPP,
// VOPC
V_CMP_F_F32 = 0 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_F32 = 1 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_F32 = 2 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_F32 = 3 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_F32 = 4 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LG_F32 = 5 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_F32 = 6 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_O_F32 = 7 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_U_F32 = 8 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NGE_F32 = 9 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLG_F32 = 10 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NGT_F32 = 11 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLE_F32 = 12 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NEQ_F32 = 13 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLT_F32 = 14 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_F32 = 15 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_F32 = 15 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_F32 = 16 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_F32 = 17 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_F32 = 18 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_F32 = 19 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_F32 = 20 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LG_F32 = 21 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_F32 = 22 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_O_F32 = 23 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_U_F32 = 24 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NGE_F32 = 25 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLG_F32 = 26 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NGT_F32 = 27 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLE_F32 = 28 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NEQ_F32 = 29 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLT_F32 = 30 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_F32 = 31 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_F32 = 31 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_F_F64 = 32 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_F64 = 33 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_F64 = 34 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_F64 = 35 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_F64 = 36 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LG_F64 = 37 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_F64 = 38 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_O_F64 = 39 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_U_F64 = 40 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NGE_F64 = 41 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLG_F64 = 42 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NGT_F64 = 43 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLE_F64 = 44 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NEQ_F64 = 45 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NLT_F64 = 46 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_F64 = 47 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_F64 = 47 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_F64 = 48 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_F64 = 49 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_F64 = 50 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_F64 = 51 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_F64 = 52 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LG_F64 = 53 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_F64 = 54 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_O_F64 = 55 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_U_F64 = 56 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NGE_F64 = 57 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLG_F64 = 58 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NGT_F64 = 59 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLE_F64 = 60 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NEQ_F64 = 61 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NLT_F64 = 62 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_F64 = 63 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_F64 = 63 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_F_F32 = 64 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LT_F32 = 65 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_EQ_F32 = 66 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LE_F32 = 67 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_GT_F32 = 68 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LG_F32 = 69 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_GE_F32 = 70 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_O_F32 = 71 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_U_F32 = 72 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NGE_F32 = 73 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLG_F32 = 74 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NGT_F32 = 75 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLE_F32 = 76 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NEQ_F32 = 77 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLT_F32 = 78 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_TRU_F32 = 79 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_T_F32 = 79 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_F_F32 = 80 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LT_F32 = 81 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_EQ_F32 = 82 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LE_F32 = 83 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_GT_F32 = 84 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LG_F32 = 85 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_GE_F32 = 86 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_O_F32 = 87 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_U_F32 = 88 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NGE_F32 = 89 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLG_F32 = 90 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NGT_F32 = 91 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLE_F32 = 92 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NEQ_F32 = 93 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLT_F32 = 94 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_TRU_F32 = 95 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_T_F32 = 95 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_F_F64 = 96 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LT_F64 = 97 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_EQ_F64 = 98 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LE_F64 = 99 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_GT_F64 = 100 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_LG_F64 = 101 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_GE_F64 = 102 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_O_F64 = 103 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_U_F64 = 104 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NGE_F64 = 105 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLG_F64 = 106 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NGT_F64 = 107 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLE_F64 = 108 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NEQ_F64 = 109 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_NLT_F64 = 110 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_TRU_F64 = 111 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPS_T_F64 = 111 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_F_F64 = 112 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LT_F64 = 113 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_EQ_F64 = 114 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LE_F64 = 115 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_GT_F64 = 116 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_LG_F64 = 117 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_GE_F64 = 118 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_O_F64 = 119 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_U_F64 = 120 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NGE_F64 = 121 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLG_F64 = 122 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NGT_F64 = 123 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLE_F64 = 124 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NEQ_F64 = 125 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_NLT_F64 = 126 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_TRU_F64 = 127 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPSX_T_F64 = 127 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_F_I32 = 128 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_I32 = 129 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_I32 = 130 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_I32 = 131 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_I32 = 132 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NE_I32 = 133 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_I32 = 134 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_I32 = 135 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_I32 = 135 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_CLASS_F32 = 136 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_I32 = 144 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_I32 = 145 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_I32 = 146 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_I32 = 147 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_I32 = 148 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LG_I32 = 149 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NE_I32 = 149 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_I32 = 150 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_I32 = 151 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_I32 = 151 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_CLASS_F32 = 152 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_F_I64 = 160 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_I64 = 161 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_I64 = 162 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_I64 = 163 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_I64 = 164 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LG_I64 = 165 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NE_I64 = 165 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_I64 = 166 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_I64 = 167 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_I64 = 167 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_CLASS_F64 = 168 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_I64 = 176 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_I64 = 177 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_I64 = 178 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_I64 = 179 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_I64 = 180 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LG_I64 = 181 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NE_I64 = 181 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_I64 = 182 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_I64 = 183 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_I64 = 183 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_CLASS_F64 = 184 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_F_U32 = 192 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_U32 = 193 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_U32 = 194 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_U32 = 195 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_U32 = 196 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NE_U32 = 197 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_U32 = 198 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_U32 = 199 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_U32 = 199 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_U32 = 208 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_U32 = 209 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_U32 = 210 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_U32 = 211 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_U32 = 212 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NE_U32 = 213 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_U32 = 214 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_U32 = 215 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_U32 = 215 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_F_U64 = 224 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LT_U64 = 225 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_EQ_U64 = 226 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LE_U64 = 227 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GT_U64 = 228 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_LG_U64 = 229 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_NE_U64 = 229 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_GE_U64 = 230 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_TRU_U64 = 231 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMP_T_U64 = 231 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_F_U64 = 240 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LT_U64 = 241 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_EQ_U64 = 242 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LE_U64 = 243 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GT_U64 = 244 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_LG_U64 = 245 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_NE_U64 = 245 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_GE_U64 = 246 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_TRU_U64 = 247 + (u32)OpcodeMap::OP_MAP_VOPC,
V_CMPX_T_U64 = 247 + (u32)OpcodeMap::OP_MAP_VOPC,
// VOP2
V_CNDMASK_B32 = 0 + (u32)OpcodeMap::OP_MAP_VOP2,
V_READLANE_B32 = 1 + (u32)OpcodeMap::OP_MAP_VOP2,
V_WRITELANE_B32 = 2 + (u32)OpcodeMap::OP_MAP_VOP2,
V_ADD_F32 = 3 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUB_F32 = 4 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUBREV_F32 = 5 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAC_LEGACY_F32 = 6 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_LEGACY_F32 = 7 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_F32 = 8 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_I32_I24 = 9 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_HI_I32_I24 = 10 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_U32_U24 = 11 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MUL_HI_U32_U24 = 12 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MIN_LEGACY_F32 = 13 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAX_LEGACY_F32 = 14 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MIN_F32 = 15 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAX_F32 = 16 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MIN_I32 = 17 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAX_I32 = 18 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MIN_U32 = 19 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAX_U32 = 20 + (u32)OpcodeMap::OP_MAP_VOP2,
V_LSHR_B32 = 21 + (u32)OpcodeMap::OP_MAP_VOP2,
V_LSHRREV_B32 = 22 + (u32)OpcodeMap::OP_MAP_VOP2,
V_ASHR_I32 = 23 + (u32)OpcodeMap::OP_MAP_VOP2,
V_ASHRREV_I32 = 24 + (u32)OpcodeMap::OP_MAP_VOP2,
V_LSHL_B32 = 25 + (u32)OpcodeMap::OP_MAP_VOP2,
V_LSHLREV_B32 = 26 + (u32)OpcodeMap::OP_MAP_VOP2,
V_AND_B32 = 27 + (u32)OpcodeMap::OP_MAP_VOP2,
V_OR_B32 = 28 + (u32)OpcodeMap::OP_MAP_VOP2,
V_XOR_B32 = 29 + (u32)OpcodeMap::OP_MAP_VOP2,
V_BFM_B32 = 30 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MAC_F32 = 31 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MADMK_F32 = 32 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MADAK_F32 = 33 + (u32)OpcodeMap::OP_MAP_VOP2,
V_BCNT_U32_B32 = 34 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MBCNT_LO_U32_B32 = 35 + (u32)OpcodeMap::OP_MAP_VOP2,
V_MBCNT_HI_U32_B32 = 36 + (u32)OpcodeMap::OP_MAP_VOP2,
V_ADD_I32 = 37 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUB_I32 = 38 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUBREV_I32 = 39 + (u32)OpcodeMap::OP_MAP_VOP2,
V_ADDC_U32 = 40 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUBB_U32 = 41 + (u32)OpcodeMap::OP_MAP_VOP2,
V_SUBBREV_U32 = 42 + (u32)OpcodeMap::OP_MAP_VOP2,
V_LDEXP_F32 = 43 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PKACCUM_U8_F32 = 44 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PKNORM_I16_F32 = 45 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PKNORM_U16_F32 = 46 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PKRTZ_F16_F32 = 47 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PK_U16_U32 = 48 + (u32)OpcodeMap::OP_MAP_VOP2,
V_CVT_PK_I16_I32 = 49 + (u32)OpcodeMap::OP_MAP_VOP2,
// VOP1
V_NOP = 0 + (u32)OpcodeMap::OP_MAP_VOP1,
V_MOV_B32 = 1 + (u32)OpcodeMap::OP_MAP_VOP1,
V_READFIRSTLANE_B32 = 2 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_I32_F64 = 3 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F64_I32 = 4 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_I32 = 5 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_U32 = 6 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_U32_F32 = 7 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_I32_F32 = 8 + (u32)OpcodeMap::OP_MAP_VOP1,
V_MOV_FED_B32 = 9 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F16_F32 = 10 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_F16 = 11 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_RPI_I32_F32 = 12 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_FLR_I32_F32 = 13 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_OFF_F32_I4 = 14 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_F64 = 15 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F64_F32 = 16 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_UBYTE0 = 17 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_UBYTE1 = 18 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_UBYTE2 = 19 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F32_UBYTE3 = 20 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_U32_F64 = 21 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CVT_F64_U32 = 22 + (u32)OpcodeMap::OP_MAP_VOP1,
V_TRUNC_F64 = 23 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CEIL_F64 = 24 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RNDNE_F64 = 25 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FLOOR_F64 = 26 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FRACT_F32 = 32 + (u32)OpcodeMap::OP_MAP_VOP1,
V_TRUNC_F32 = 33 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CEIL_F32 = 34 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RNDNE_F32 = 35 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FLOOR_F32 = 36 + (u32)OpcodeMap::OP_MAP_VOP1,
V_EXP_F32 = 37 + (u32)OpcodeMap::OP_MAP_VOP1,
V_LOG_CLAMP_F32 = 38 + (u32)OpcodeMap::OP_MAP_VOP1,
V_LOG_F32 = 39 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_CLAMP_F32 = 40 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_LEGACY_F32 = 41 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_F32 = 42 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_IFLAG_F32 = 43 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RSQ_CLAMP_F32 = 44 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RSQ_LEGACY_F32 = 45 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RSQ_F32 = 46 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_F64 = 47 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RCP_CLAMP_F64 = 48 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RSQ_F64 = 49 + (u32)OpcodeMap::OP_MAP_VOP1,
V_RSQ_CLAMP_F64 = 50 + (u32)OpcodeMap::OP_MAP_VOP1,
V_SQRT_F32 = 51 + (u32)OpcodeMap::OP_MAP_VOP1,
V_SQRT_F64 = 52 + (u32)OpcodeMap::OP_MAP_VOP1,
V_SIN_F32 = 53 + (u32)OpcodeMap::OP_MAP_VOP1,
V_COS_F32 = 54 + (u32)OpcodeMap::OP_MAP_VOP1,
V_NOT_B32 = 55 + (u32)OpcodeMap::OP_MAP_VOP1,
V_BFREV_B32 = 56 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FFBH_U32 = 57 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FFBL_B32 = 58 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FFBH_I32 = 59 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FREXP_EXP_I32_F64 = 60 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FREXP_MANT_F64 = 61 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FRACT_F64 = 62 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FREXP_EXP_I32_F32 = 63 + (u32)OpcodeMap::OP_MAP_VOP1,
V_FREXP_MANT_F32 = 64 + (u32)OpcodeMap::OP_MAP_VOP1,
V_CLREXCP = 65 + (u32)OpcodeMap::OP_MAP_VOP1,
V_MOVRELD_B32 = 66 + (u32)OpcodeMap::OP_MAP_VOP1,
V_MOVRELS_B32 = 67 + (u32)OpcodeMap::OP_MAP_VOP1,
V_MOVRELSD_B32 = 68 + (u32)OpcodeMap::OP_MAP_VOP1,
V_LOG_LEGACY_F32 = 69 + (u32)OpcodeMap::OP_MAP_VOP1,
V_EXP_LEGACY_F32 = 70 + (u32)OpcodeMap::OP_MAP_VOP1,
// VOP3
V_MAD_LEGACY_F32 = 320 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAD_F32 = 321 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAD_I32_I24 = 322 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAD_U32_U24 = 323 + (u32)OpcodeMap::OP_MAP_VOP3,
V_CUBEID_F32 = 324 + (u32)OpcodeMap::OP_MAP_VOP3,
V_CUBESC_F32 = 325 + (u32)OpcodeMap::OP_MAP_VOP3,
V_CUBETC_F32 = 326 + (u32)OpcodeMap::OP_MAP_VOP3,
V_CUBEMA_F32 = 327 + (u32)OpcodeMap::OP_MAP_VOP3,
V_BFE_U32 = 328 + (u32)OpcodeMap::OP_MAP_VOP3,
V_BFE_I32 = 329 + (u32)OpcodeMap::OP_MAP_VOP3,
V_BFI_B32 = 330 + (u32)OpcodeMap::OP_MAP_VOP3,
V_FMA_F32 = 331 + (u32)OpcodeMap::OP_MAP_VOP3,
V_FMA_F64 = 332 + (u32)OpcodeMap::OP_MAP_VOP3,
V_LERP_U8 = 333 + (u32)OpcodeMap::OP_MAP_VOP3,
V_ALIGNBIT_B32 = 334 + (u32)OpcodeMap::OP_MAP_VOP3,
V_ALIGNBYTE_B32 = 335 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MULLIT_F32 = 336 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MIN3_F32 = 337 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MIN3_I32 = 338 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MIN3_U32 = 339 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAX3_F32 = 340 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAX3_I32 = 341 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAX3_U32 = 342 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MED3_F32 = 343 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MED3_I32 = 344 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MED3_U32 = 345 + (u32)OpcodeMap::OP_MAP_VOP3,
V_SAD_U8 = 346 + (u32)OpcodeMap::OP_MAP_VOP3,
V_SAD_HI_U8 = 347 + (u32)OpcodeMap::OP_MAP_VOP3,
V_SAD_U16 = 348 + (u32)OpcodeMap::OP_MAP_VOP3,
V_SAD_U32 = 349 + (u32)OpcodeMap::OP_MAP_VOP3,
V_CVT_PK_U8_F32 = 350 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_FIXUP_F32 = 351 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_FIXUP_F64 = 352 + (u32)OpcodeMap::OP_MAP_VOP3,
V_LSHL_B64 = 353 + (u32)OpcodeMap::OP_MAP_VOP3,
V_LSHR_B64 = 354 + (u32)OpcodeMap::OP_MAP_VOP3,
V_ASHR_I64 = 355 + (u32)OpcodeMap::OP_MAP_VOP3,
V_ADD_F64 = 356 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MUL_F64 = 357 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MIN_F64 = 358 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAX_F64 = 359 + (u32)OpcodeMap::OP_MAP_VOP3,
V_LDEXP_F64 = 360 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MUL_LO_U32 = 361 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MUL_HI_U32 = 362 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MUL_LO_I32 = 363 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MUL_HI_I32 = 364 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_SCALE_F32 = 365 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_SCALE_F64 = 366 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_FMAS_F32 = 367 + (u32)OpcodeMap::OP_MAP_VOP3,
V_DIV_FMAS_F64 = 368 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MSAD_U8 = 369 + (u32)OpcodeMap::OP_MAP_VOP3,
V_QSAD_U8 = 370 + (u32)OpcodeMap::OP_MAP_VOP3,
V_QSAD_PK_U16_U8 = 370 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MQSAD_U8 = 371 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MQSAD_PK_U16_U8 = 371 + (u32)OpcodeMap::OP_MAP_VOP3,
V_TRIG_PREOP_F64 = 372 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MQSAD_U32_U8 = 373 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAD_U64_U32 = 374 + (u32)OpcodeMap::OP_MAP_VOP3,
V_MAD_I64_I32 = 375 + (u32)OpcodeMap::OP_MAP_VOP3,
// VINTRP
V_INTERP_P1_F32 = 0 + (u32)OpcodeMap::OP_MAP_VINTRP,
V_INTERP_P2_F32 = 1 + (u32)OpcodeMap::OP_MAP_VINTRP,
V_INTERP_MOV_F32 = 2 + (u32)OpcodeMap::OP_MAP_VINTRP,
// SMRD
S_LOAD_DWORD = 0 + (u32)OpcodeMap::OP_MAP_SMRD,
S_LOAD_DWORDX2 = 1 + (u32)OpcodeMap::OP_MAP_SMRD,
S_LOAD_DWORDX4 = 2 + (u32)OpcodeMap::OP_MAP_SMRD,
S_LOAD_DWORDX8 = 3 + (u32)OpcodeMap::OP_MAP_SMRD,
S_LOAD_DWORDX16 = 4 + (u32)OpcodeMap::OP_MAP_SMRD,
S_BUFFER_LOAD_DWORD = 8 + (u32)OpcodeMap::OP_MAP_SMRD,
S_BUFFER_LOAD_DWORDX2 = 9 + (u32)OpcodeMap::OP_MAP_SMRD,
S_BUFFER_LOAD_DWORDX4 = 10 + (u32)OpcodeMap::OP_MAP_SMRD,
S_BUFFER_LOAD_DWORDX8 = 11 + (u32)OpcodeMap::OP_MAP_SMRD,
S_BUFFER_LOAD_DWORDX16 = 12 + (u32)OpcodeMap::OP_MAP_SMRD,
S_MEMTIME = 30 + (u32)OpcodeMap::OP_MAP_SMRD,
S_DCACHE_INV = 31 + (u32)OpcodeMap::OP_MAP_SMRD,
// DS
DS_ADD_U32 = 0 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_U32 = 1 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_U32 = 2 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_U32 = 3 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_U32 = 4 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_I32 = 5 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_I32 = 6 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_U32 = 7 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_U32 = 8 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_B32 = 9 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_B32 = 10 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_B32 = 11 + (u32)OpcodeMap::OP_MAP_DS,
DS_MSKOR_B32 = 12 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B32 = 13 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE2_B32 = 14 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE2ST64_B32 = 15 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_B32 = 16 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_F32 = 17 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_F32 = 18 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_F32 = 19 + (u32)OpcodeMap::OP_MAP_DS,
DS_NOP = 20 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_SEMA_RELEASE_ALL = 24 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_INIT = 25 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_SEMA_V = 26 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_SEMA_BR = 27 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_SEMA_P = 28 + (u32)OpcodeMap::OP_MAP_DS,
DS_GWS_BARRIER = 29 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B8 = 30 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B16 = 31 + (u32)OpcodeMap::OP_MAP_DS,
DS_ADD_RTN_U32 = 32 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_RTN_U32 = 33 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_RTN_U32 = 34 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_RTN_U32 = 35 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_RTN_U32 = 36 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_I32 = 37 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_I32 = 38 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_U32 = 39 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_U32 = 40 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_RTN_B32 = 41 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_RTN_B32 = 42 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_RTN_B32 = 43 + (u32)OpcodeMap::OP_MAP_DS,
DS_MSKOR_RTN_B32 = 44 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG_RTN_B32 = 45 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG2_RTN_B32 = 46 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG2ST64_RTN_B32 = 47 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_RTN_B32 = 48 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_RTN_F32 = 49 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_F32 = 50 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_F32 = 51 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRAP_RTN_B32 = 52 + (u32)OpcodeMap::OP_MAP_DS,
DS_SWIZZLE_B32 = 53 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_B32 = 54 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ2_B32 = 55 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ2ST64_B32 = 56 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_I8 = 57 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_U8 = 58 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_I16 = 59 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_U16 = 60 + (u32)OpcodeMap::OP_MAP_DS,
DS_CONSUME = 61 + (u32)OpcodeMap::OP_MAP_DS,
DS_APPEND = 62 + (u32)OpcodeMap::OP_MAP_DS,
DS_ORDERED_COUNT = 63 + (u32)OpcodeMap::OP_MAP_DS,
DS_ADD_U64 = 64 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_U64 = 65 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_U64 = 66 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_U64 = 67 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_U64 = 68 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_I64 = 69 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_I64 = 70 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_U64 = 71 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_U64 = 72 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_B64 = 73 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_B64 = 74 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_B64 = 75 + (u32)OpcodeMap::OP_MAP_DS,
DS_MSKOR_B64 = 76 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B64 = 77 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE2_B64 = 78 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE2ST64_B64 = 79 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_B64 = 80 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_F64 = 81 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_F64 = 82 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_F64 = 83 + (u32)OpcodeMap::OP_MAP_DS,
DS_ADD_RTN_U64 = 96 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_RTN_U64 = 97 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_RTN_U64 = 98 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_RTN_U64 = 99 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_RTN_U64 = 100 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_I64 = 101 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_I64 = 102 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_U64 = 103 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_U64 = 104 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_RTN_B64 = 105 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_RTN_B64 = 106 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_RTN_B64 = 107 + (u32)OpcodeMap::OP_MAP_DS,
DS_MSKOR_RTN_B64 = 108 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG_RTN_B64 = 109 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG2_RTN_B64 = 110 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRXCHG2ST64_RTN_B64 = 111 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_RTN_B64 = 112 + (u32)OpcodeMap::OP_MAP_DS,
DS_CMPST_RTN_F64 = 113 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_RTN_F64 = 114 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_RTN_F64 = 115 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_B64 = 118 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ2_B64 = 119 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ2ST64_B64 = 120 + (u32)OpcodeMap::OP_MAP_DS,
DS_CONDXCHG32_RTN_B64 = 126 + (u32)OpcodeMap::OP_MAP_DS,
DS_ADD_SRC2_U32 = 128 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_SRC2_U32 = 129 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_SRC2_U32 = 130 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_SRC2_U32 = 131 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_SRC2_U32 = 132 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_I32 = 133 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_I32 = 134 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_U32 = 135 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_U32 = 136 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_SRC2_B32 = 137 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_SRC2_B32 = 138 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_SRC2_B32 = 139 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_SRC2_B32 = 141 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_F32 = 146 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_F32 = 147 + (u32)OpcodeMap::OP_MAP_DS,
DS_ADD_SRC2_U64 = 192 + (u32)OpcodeMap::OP_MAP_DS,
DS_SUB_SRC2_U64 = 193 + (u32)OpcodeMap::OP_MAP_DS,
DS_RSUB_SRC2_U64 = 194 + (u32)OpcodeMap::OP_MAP_DS,
DS_INC_SRC2_U64 = 195 + (u32)OpcodeMap::OP_MAP_DS,
DS_DEC_SRC2_U64 = 196 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_I64 = 197 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_I64 = 198 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_U64 = 199 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_U64 = 200 + (u32)OpcodeMap::OP_MAP_DS,
DS_AND_SRC2_B64 = 201 + (u32)OpcodeMap::OP_MAP_DS,
DS_OR_SRC2_B64 = 202 + (u32)OpcodeMap::OP_MAP_DS,
DS_XOR_SRC2_B64 = 203 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_SRC2_B64 = 205 + (u32)OpcodeMap::OP_MAP_DS,
DS_MIN_SRC2_F64 = 210 + (u32)OpcodeMap::OP_MAP_DS,
DS_MAX_SRC2_F64 = 211 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B96 = 222 + (u32)OpcodeMap::OP_MAP_DS,
DS_WRITE_B128 = 223 + (u32)OpcodeMap::OP_MAP_DS,
DS_CONDXCHG32_RTN_B128 = 253 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_B96 = 254 + (u32)OpcodeMap::OP_MAP_DS,
DS_READ_B128 = 255 + (u32)OpcodeMap::OP_MAP_DS,
// MUBUF
BUFFER_LOAD_FORMAT_X = 0 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_FORMAT_XY = 1 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_FORMAT_XYZ = 2 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_FORMAT_XYZW = 3 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_FORMAT_X = 4 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_FORMAT_XY = 5 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_FORMAT_XYZ = 6 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_FORMAT_XYZW = 7 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_UBYTE = 8 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_SBYTE = 9 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_USHORT = 10 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_SSHORT = 11 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_DWORD = 12 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_DWORDX2 = 13 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_DWORDX4 = 14 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_LOAD_DWORDX3 = 15 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_BYTE = 24 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_SHORT = 26 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_DWORD = 28 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_DWORDX2 = 29 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_DWORDX4 = 30 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_STORE_DWORDX3 = 31 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SWAP = 48 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_CMPSWAP = 49 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_ADD = 50 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SUB = 51 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SMIN = 53 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_UMIN = 54 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SMAX = 55 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_UMAX = 56 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_AND = 57 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_OR = 58 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_XOR = 59 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_INC = 60 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_DEC = 61 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FCMPSWAP = 62 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FMIN = 63 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FMAX = 64 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SWAP_X2 = 80 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_CMPSWAP_X2 = 81 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_ADD_X2 = 82 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SUB_X2 = 83 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SMIN_X2 = 85 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_UMIN_X2 = 86 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_SMAX_X2 = 87 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_UMAX_X2 = 88 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_AND_X2 = 89 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_OR_X2 = 90 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_XOR_X2 = 91 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_INC_X2 = 92 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_DEC_X2 = 93 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FCMPSWAP_X2 = 94 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FMIN_X2 = 95 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_ATOMIC_FMAX_X2 = 96 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_WBINVL1_SC = 112 + (u32)OpcodeMap::OP_MAP_MUBUF,
BUFFER_WBINVL1 = 113 + (u32)OpcodeMap::OP_MAP_MUBUF,
// MTBUF
TBUFFER_LOAD_FORMAT_X = 0 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_LOAD_FORMAT_XY = 1 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_LOAD_FORMAT_XYZ = 2 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_LOAD_FORMAT_XYZW = 3 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_STORE_FORMAT_X = 4 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_STORE_FORMAT_XY = 5 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_STORE_FORMAT_XYZ = 6 + (u32)OpcodeMap::OP_MAP_MTBUF,
TBUFFER_STORE_FORMAT_XYZW = 7 + (u32)OpcodeMap::OP_MAP_MTBUF,
// MIMG
IMAGE_LOAD = 0 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_LOAD_MIP = 1 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_LOAD_PCK = 2 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_LOAD_PCK_SGN = 3 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_LOAD_MIP_PCK = 4 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_LOAD_MIP_PCK_SGN = 5 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_STORE = 8 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_STORE_MIP = 9 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_STORE_PCK = 10 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_STORE_MIP_PCK = 11 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GET_RESINFO = 14 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_SWAP = 15 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_CMPSWAP = 16 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_ADD = 17 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_SUB = 18 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_SMIN = 20 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_UMIN = 21 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_SMAX = 22 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_UMAX = 23 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_AND = 24 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_OR = 25 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_XOR = 26 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_INC = 27 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_DEC = 28 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_FCMPSWAP = 29 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_FMIN = 30 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_ATOMIC_FMAX = 31 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE = 32 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CL = 33 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_D = 34 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_D_CL = 35 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_L = 36 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_B = 37 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_B_CL = 38 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_LZ = 39 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C = 40 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CL = 41 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_D = 42 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_D_CL = 43 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_L = 44 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_B = 45 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_B_CL = 46 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_LZ = 47 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_O = 48 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CL_O = 49 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_D_O = 50 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_D_CL_O = 51 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_L_O = 52 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_B_O = 53 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_B_CL_O = 54 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_LZ_O = 55 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_O = 56 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CL_O = 57 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_D_O = 58 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_D_CL_O = 59 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_L_O = 60 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_B_O = 61 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_B_CL_O = 62 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_LZ_O = 63 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4 = 64 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_CL = 65 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_L = 68 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_B = 69 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_B_CL = 70 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_LZ = 71 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C = 72 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_CL = 73 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_L = 76 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_B = 77 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_B_CL = 78 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_LZ = 79 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_O = 80 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_CL_O = 81 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_L_O = 84 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_B_O = 85 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_B_CL_O = 86 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_LZ_O = 87 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_O = 88 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_CL_O = 89 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_L_O = 92 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_B_O = 93 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_B_CL_O = 94 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GATHER4_C_LZ_O = 95 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_GET_LOD = 96 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CD = 104 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CD_CL = 105 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CD = 106 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CD_CL = 107 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CD_O = 108 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_CD_CL_O = 109 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CD_O = 110 + (u32)OpcodeMap::OP_MAP_MIMG,
IMAGE_SAMPLE_C_CD_CL_O = 111 + (u32)OpcodeMap::OP_MAP_MIMG,
// EXP
EXP = 0 + (u32)OpcodeMap::OP_MAP_EXP,
};
enum class EncodingMask : u32 {
MASK_9bit = 0x000001FFULL << 23,
MASK_7bit = 0x0000007FULL << 25,
MASK_6bit = 0x0000003FULL << 26,
MASK_5bit = 0x0000001FULL << 27,
MASK_4bit = 0x0000000FULL << 28,
MASK_2bit = 0x00000003ULL << 30,
MASK_1bit = 0x00000001ULL << 31
};
enum class InstEncoding : u32 {
/// InstructionEncodingMask_9bit
/// bits [31:23] - (1 0 1 1 1 1 1 0 1)
SOP1 = 0x0000017Du << 23,
/// bits [31:23] - (1 0 1 1 1 1 1 1 1)
SOPP = 0x0000017Fu << 23,
/// bits [31:23] - (1 0 1 1 1 1 1 1 0)
SOPC = 0x0000017Eu << 23,
/// InstructionEncodingMask_7bit
/// bits [31:25] - (0 1 1 1 1 1 1)
VOP1 = 0x0000003Fu << 25,
/// bits [31:25] - (0 1 1 1 1 1 0)
VOPC = 0x0000003Eu << 25,
/// InstructionEncodingMask_6bit
/// bits [31:26] - (1 1 0 1 0 0)
VOP3 = 0x00000034u << 26,
/// bits [31:26] - (1 1 1 1 1 0)
EXP = 0x0000003Eu << 26,
/// bits [31:26] - (1 1 0 0 1 0)
VINTRP = 0x00000032u << 26,
/// bits [31:26] - (1 1 0 1 1 0)
DS = 0x00000036u << 26,
/// bits [31:26] - (1 1 1 0 0 0)
MUBUF = 0x00000038u << 26,
/// bits [31:26] - (1 1 1 0 1 0)
MTBUF = 0x0000003Au << 26,
/// bits [31:26] - (1 1 1 1 0 0)
MIMG = 0x0000003Cu << 26,
/// InstructionEncodingMask_5bit
/// bits [31:27] - (1 1 0 0 0)
SMRD = 0x00000018u << 27,
/// InstructionEncodingMask_4bit
/// bits [31:28] - (1 0 1 1)
SOPK = 0x0000000Bu << 28,
/// InstructionEncodingMask_2bit
/// bits [31:30] - (1 0)
SOP2 = 0x00000002u << 30,
/// InstructionEncodingMask_1bit
/// bits [31:31] - (0)
VOP2 = 0x00000000u << 31,
ILLEGAL
};
enum class InstClass : u32 {
Undefined,
ScalarArith,
ScalarAbs,
ScalarMov,
ScalarMovRel,
ScalarCmp,
ScalarSelect,
ScalarBitLogic,
ScalarBitManip,
ScalarBitField,
ScalarConv,
ScalarExecMask,
ScalarQuadMask,
VectorRegMov,
VectorMovRel,
VectorLane,
VectorBitLogic,
VectorBitField32,
VectorThreadMask,
VectorBitField64,
VectorFpArith32,
VectorFpRound32,
VectorFpField32,
VectorFpTran32,
VectorFpCmp32,
VectorFpArith64,
VectorFpRound64,
VectorFpField64,
VectorFpTran64,
VectorFpCmp64,
VectorIntArith32,
VectorIntArith64,
VectorIntCmp32,
VectorIntCmp64,
VectorConv,
VectorFpGraph32,
VectorIntGraph,
VectorMisc,
ScalarProgFlow,
ScalarSync,
ScalarWait,
ScalarCache,
ScalarPrior,
ScalarRegAccess,
ScalarMsg,
ScalarMemRd,
ScalarMemUt,
VectorMemBufNoFmt,
VectorMemBufFmt,
VectorMemBufAtomic,
VectorMemImgNoSmp,
VectorMemImgSmp,
VectorMemImgUt,
VectorMemL1Cache,
DsIdxRd,
DsIdxWr,
DsIdxWrXchg,
DsIdxCondXchg,
DsIdxWrap,
DsAtomicArith32,
DsAtomicArith64,
DsAtomicMinMax32,
DsAtomicMinMax64,
DsAtomicCmpSt32,
DsAtomicCmpSt64,
DsAtomicLogic32,
DsAtomicLogic64,
DsAppendCon,
DsDataShareUt,
DsDataShareMisc,
GdsSync,
GdsOrdCnt,
VectorInterpFpCache,
Exp,
DbgProf
};
enum class InstCategory : u32 {
Undefined,
/// Scalar ALU Operation
ScalarALU,
/// Scalar Instruction Memory
ScalarMemory,
/// Vector ALU Operation
VectorALU,
/// Vector Instruction Memory Read
VectorMemory,
/// Scalar Program Flow Control and Special Operations
FlowControl,
/// LDS and GDS
DataShare,
/// Vector Interpolation Operations
VectorInterpolation,
/// Export
Export,
/// Debug and Profiling Operations
DebugProfile,
};
enum class ScalarType : u32 {
Undefined,
Any,
Uint32,
Uint64,
Sint32,
Sint64,
Float16,
Float32,
Float64,
Bool,
};
/// Instruction's action when GPU thread is not active.
enum class DivergentAction : u32 { Nop, ZeroScalar, Execute };
enum class OperandField : u32 {
ScalarGPR = 0,
VccLo = 106,
VccHi,
M0 = 124,
ExecLo = 126,
ExecHi,
ConstZero,
SignedConstIntPos = 129,
SignedConstIntNeg = 193,
ConstFloatPos_0_5 = 240,
ConstFloatNeg_0_5,
ConstFloatPos_1_0,
ConstFloatNeg_1_0,
ConstFloatPos_2_0,
ConstFloatNeg_2_0,
ConstFloatPos_4_0,
ConstFloatNeg_4_0,
VccZ = 251,
ExecZ = 252,
Scc = 253,
LdsDirect = 254,
LiteralConst = 255,
VectorGPR,
Undefined = 0xFFFFFFFF,
};
enum class SystemValue : u32 {
None = 0,
Position = 1,
ClipDistance = 2,
CullDistance = 3,
RenderTargetId = 4,
ViewportId = 5,
VertexId = 6,
PrimitiveId = 7,
InstanceId = 8,
IsFrontFace = 9,
SampleIndex = 10,
FinalQuadUeq0EdgeTessFactor = 11,
FinalQuadVeq0EdgeTessFactor = 12,
FinalQuadUeq1EdgeTessFactor = 13,
FinalQuadVeq1EdgeTessFactor = 14,
FinalQuadUInsideTessFactor = 15,
FinalQuadVInsideTessFactor = 16,
FinalTriUeq0EdgeTessFactor = 17,
FinalTriVeq0EdgeTessFactor = 18,
FinalTriWeq0EdgeTessFactor = 19,
FinalTriInsideTessFactor = 20,
FinalLineDetailTessFactor = 21,
FinalLineDensityTessFactor = 22,
GlobalInvocationId = 23,
WorkgroupId = 24,
LocalInvocationId = 25,
LocalInvocationIndex = 26,
Target = 64,
Depth = 65,
Coverage = 66,
DepthGe = 67,
DepthLe = 68,
NumSubgroups = 70,
SubgroupID = 71,
SubgroupSize = 72,
SubgroupInvocationID = 73,
SubgroupEqMask = 74,
SubgroupGeMask = 75,
SubgroupGtMask = 76,
SubgroupLeMask = 77,
SubgroupLtMask = 78,
};
enum class InterpolationMode : u32 {
Undefined = 0,
Constant = 1,
Linear = 2,
LinearCentroid = 3,
LinearNoPerspective = 4,
LinearNoPerspectiveCentroid = 5,
LinearSample = 6,
LinearNoPerspectiveSample = 7,
};
enum class MimgModifier : u32 {
Lod, /// LOD is used instead of TA computed LOD.
LodBias, /// Add this BIAS to the LOD TA computes.
LodClamp, /// Clamp the LOD to be no larger than this value.
Derivative, /// Send dx/dv, dx/dy, etc. slopes to TA for it to used in LOD computation.
CoarseDerivative, /// Send dx/dv, dx/dy, etc. slopes to TA for it to used in LOD computation.
Level0, /// Force use of MIP level 0.
Pcf, /// Percentage closer filtering.
Offset /// Send X, Y, Z integer offsets (packed into 1 Dword) to offset XYZ address.
};
using MimgModifierFlags = Common::Flags<MimgModifier>;
enum class ImageResComponent : u32 { Width, Height, Depth, MipCount };
using ImageResFlags = Common::Flags<ImageResComponent>;
enum class ImageAddrComponent : u32 {
Offsets,
Bias,
Zpcf,
DxDh,
DyDh,
DzDh,
DxDv,
DyDv,
DzDv,
X,
Y,
Z,
Slice,
FaceId,
FragId,
Lod,
Clamp,
};
struct SendMsgSimm {
enum class Message : u32 {
Interrupt = 1,
Gs = 2,
GsDone = 3,
System = 15,
};
enum class GsOp : u32 {
Nop = 0,
Cut = 1,
Emit = 2,
EmitCut = 3,
};
Message msg : 4;
GsOp op : 2;
};
} // namespace Shader::Gcn
| 86,671
|
C++
|
.h
| 2,448
| 30.486111
| 99
| 0.606526
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,969
|
decode.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/decode.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "shader_recompiler/frontend/instruction.h"
namespace Shader::Gcn {
struct InstFormat {
InstClass inst_class = InstClass::Undefined;
InstCategory inst_category = InstCategory::Undefined;
u32 src_count = 0;
u32 dst_count = 0;
ScalarType src_type = ScalarType::Undefined;
ScalarType dst_type = ScalarType::Undefined;
};
InstEncoding GetInstructionEncoding(u32 token);
u32 GetEncodingLength(InstEncoding encoding);
InstFormat InstructionFormat(InstEncoding encoding, u32 opcode);
Opcode DecodeOpcode(u32 token);
class GcnCodeSlice {
public:
GcnCodeSlice(const u32* ptr, const u32* end) : m_ptr(ptr), m_end(end) {}
GcnCodeSlice(const GcnCodeSlice& other) = default;
~GcnCodeSlice() = default;
u32 at(u32 id) const {
return m_ptr[id];
}
u32 readu32() {
return *(m_ptr++);
}
u64 readu64() {
const u64 value = *(u64*)m_ptr;
m_ptr += 2;
return value;
}
bool atEnd() const {
return m_ptr == m_end;
}
private:
const u32* m_ptr{};
const u32* m_end{};
};
class GcnDecodeContext {
public:
GcnInst decodeInstruction(GcnCodeSlice& code);
private:
uint32_t getEncodingLength(InstEncoding encoding);
uint32_t getOpMapOffset(InstEncoding encoding);
uint32_t mapEncodingOp(InstEncoding encoding, Opcode opcode);
void updateInstructionMeta(InstEncoding encoding);
uint32_t getMimgModifier(Opcode opcode);
void repairOperandType();
OperandField getOperandField(uint32_t code);
void decodeInstruction32(InstEncoding encoding, GcnCodeSlice& code);
void decodeInstruction64(InstEncoding encoding, GcnCodeSlice& code);
void decodeLiteralConstant(InstEncoding encoding, GcnCodeSlice& code);
// 32 bits encodings
void decodeInstructionSOP1(uint32_t hexInstruction);
void decodeInstructionSOPP(uint32_t hexInstruction);
void decodeInstructionSOPC(uint32_t hexInstruction);
void decodeInstructionSOPK(uint32_t hexInstruction);
void decodeInstructionSOP2(uint32_t hexInstruction);
void decodeInstructionVOP1(uint32_t hexInstruction);
void decodeInstructionVOPC(uint32_t hexInstruction);
void decodeInstructionVOP2(uint32_t hexInstruction);
void decodeInstructionSMRD(uint32_t hexInstruction);
void decodeInstructionVINTRP(uint32_t hexInstruction);
// 64 bits encodings
void decodeInstructionVOP3(uint64_t hexInstruction);
void decodeInstructionMUBUF(uint64_t hexInstruction);
void decodeInstructionMTBUF(uint64_t hexInstruction);
void decodeInstructionMIMG(uint64_t hexInstruction);
void decodeInstructionDS(uint64_t hexInstruction);
void decodeInstructionEXP(uint64_t hexInstruction);
private:
GcnInst m_instruction;
};
} // namespace Shader::Gcn
| 2,916
|
C++
|
.h
| 76
| 33.881579
| 76
| 0.75878
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,970
|
control_flow_graph.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/control_flow_graph.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <algorithm>
#include <span>
#include <string>
#include <boost/container/small_vector.hpp>
#include <boost/intrusive/set.hpp>
#include "common/assert.h"
#include "common/object_pool.h"
#include "common/types.h"
#include "shader_recompiler/frontend/instruction.h"
#include "shader_recompiler/ir/condition.h"
namespace Shader::Gcn {
using Hook =
boost::intrusive::set_base_hook<boost::intrusive::link_mode<boost::intrusive::normal_link>>;
enum class EndClass {
Branch, ///< Block ends with a (un)conditional branch.
Exit, ///< Block ends with an exit instruction.
Kill, ///< Block ends with a discard instruction.
};
/// A block represents a linear range of instructions.
struct Block : Hook {
[[nodiscard]] bool Contains(u32 pc) const noexcept;
bool operator<(const Block& rhs) const noexcept {
return begin < rhs.begin;
}
u32 begin;
u32 end;
u32 begin_index;
u32 end_index;
u32 num_predecessors{};
IR::Condition cond{};
GcnInst end_inst{};
EndClass end_class{};
Block* branch_true{};
Block* branch_false{};
bool is_dummy{};
};
class CFG {
using Label = u32;
public:
explicit CFG(Common::ObjectPool<Block>& block_pool, std::span<const GcnInst> inst_list);
[[nodiscard]] std::string Dot() const;
private:
void EmitLabels();
void EmitDivergenceLabels();
void EmitBlocks();
void LinkBlocks();
void AddLabel(Label address) {
const auto it = std::ranges::find(labels, address);
if (it == labels.end()) {
labels.push_back(address);
}
};
size_t GetIndex(Label label) {
if (label == 0) {
return 0ULL;
}
const auto it_index = std::ranges::lower_bound(index_to_pc, label);
ASSERT(it_index != index_to_pc.end() || label > index_to_pc.back());
return std::distance(index_to_pc.begin(), it_index);
};
public:
Common::ObjectPool<Block>& block_pool;
std::span<const GcnInst> inst_list;
std::vector<u32> index_to_pc;
boost::container::small_vector<Label, 16> labels;
boost::intrusive::set<Block> blocks;
};
} // namespace Shader::Gcn
| 2,303
|
C++
|
.h
| 71
| 27.929577
| 96
| 0.672686
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,971
|
fetch_shader.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/fetch_shader.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <vector>
#include "common/types.h"
namespace Shader::Gcn {
struct VertexAttribute {
u8 semantic; ///< Semantic index of the attribute
u8 dest_vgpr; ///< Destination VGPR to load first component.
u8 num_elements; ///< Number of components to load
u8 sgpr_base; ///< SGPR that contains the pointer to the list of vertex V#
u8 dword_offset; ///< The dword offset of the V# that describes this attribute.
u8 instance_data; ///< Indicates that the buffer will be accessed in instance rate
};
struct FetchShaderData {
std::vector<VertexAttribute> attributes;
s8 vertex_offset_sgpr = -1; ///< SGPR of vertex offset from VADDR
s8 instance_offset_sgpr = -1; ///< SGPR of instance offset from VADDR
};
FetchShaderData ParseFetchShader(const u32* code, u32* out_size);
} // namespace Shader::Gcn
| 979
|
C++
|
.h
| 21
| 43.571429
| 86
| 0.723449
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,972
|
instruction.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/instruction.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <limits>
#include "common/bit_field.h"
#include "shader_recompiler/frontend/opcodes.h"
namespace Shader::Gcn {
constexpr u32 GcnMaxSrcCount = 4;
constexpr u32 GcnMaxDstCount = 2;
enum OperandFieldRange {
ScalarGPRMin = 0,
ScalarGPRMax = 103,
SignedConstIntPosMin = 129,
SignedConstIntPosMax = 192,
SignedConstIntNegMin = 193,
SignedConstIntNegMax = 208,
ConstFloatMin = 240,
VectorGPRMin = 256,
VectorGPRMax = 511
};
/// These are applied after loading an operand register.
struct InputModifiers {
bool neg = false;
bool abs = false;
};
/// These are applied before storing an operand register.
struct OutputModifiers {
bool clamp = false;
float multiplier = 0.f;
};
struct InstOperand {
OperandField field = OperandField::Undefined;
ScalarType type = ScalarType::Undefined;
InputModifiers input_modifier = {};
OutputModifiers output_modifier = {};
u32 code = 0xFFFFFFFF;
};
struct Operand {
OperandField field = OperandField::Undefined;
ScalarType type = ScalarType::Undefined;
union {
InputModifiers input_modifier = {};
OutputModifiers output_modifier;
};
u32 code = 0xFFFFFFFF;
};
struct InstSOPK {
u16 simm;
};
struct InstSOPP {
u16 simm;
};
struct InstVOP3 {
Operand vdst;
Operand src0;
Operand src1;
Operand src2;
};
struct SMRD {
u8 offset;
bool imm;
u8 sbase;
};
struct InstControlSOPK {
s16 simm;
};
struct InstControlSOPP {
s16 simm;
};
struct InstControlVOP3 {
u64 : 8;
u64 abs : 3;
u64 clmp : 1;
u64 : 47;
u64 omod : 2;
u64 neg : 3;
};
struct InstControlSMRD {
u32 offset : 8;
u32 imm : 1;
u32 count : 5;
u32 : 18;
};
struct InstControlMUBUF {
u64 offset : 12;
u64 offen : 1;
u64 idxen : 1;
u64 glc : 1;
u64 : 1;
u64 lds : 1;
u64 : 37;
u64 slc : 1;
u64 tfe : 1;
u64 count : 3;
u64 size : 5;
};
struct InstControlMTBUF {
u64 offset : 12;
u64 offen : 1;
u64 idxen : 1;
u64 glc : 1;
u64 : 4;
u64 dfmt : 4;
u64 nfmt : 3;
u64 : 28;
u64 slc : 1;
u64 tfe : 1;
u64 count : 3;
u64 size : 5;
};
struct InstControlMIMG {
u64 : 8;
u64 dmask : 4;
u64 unrm : 1;
u64 glc : 1;
u64 da : 1;
u64 r128 : 1;
u64 tfe : 1;
u64 lwe : 1;
u64 : 7;
u64 slc : 1;
u64 mod : 32;
u64 : 6;
};
struct InstControlDS {
u64 offset0 : 8;
u64 offset1 : 8;
u64 : 1;
u64 gds : 1;
u64 dual : 1;
u64 sign : 1;
u64 relative : 1;
u64 stride : 1;
u64 size : 4;
u64 : 38;
};
struct InstControlVINTRP {
u32 : 8;
u32 chan : 2;
u32 attr : 6;
u32 : 16;
};
struct InstControlEXP {
u64 en : 4;
u64 target : 6;
u64 compr : 1;
u64 done : 1;
u64 vm : 1;
u64 reserved : 51;
};
union InstControl {
InstControlSOPK sopk;
InstControlSOPP sopp;
InstControlVOP3 vop3;
InstControlSMRD smrd;
InstControlMUBUF mubuf;
InstControlMTBUF mtbuf;
InstControlMIMG mimg;
InstControlDS ds;
InstControlVINTRP vintrp;
InstControlEXP exp;
};
struct GcnInst {
Opcode opcode;
InstEncoding encoding;
InstClass inst_class;
InstCategory category;
InstControl control;
u32 length;
u32 src_count;
u32 dst_count;
std::array<InstOperand, GcnMaxSrcCount> src;
std::array<InstOperand, GcnMaxDstCount> dst;
u32 BranchTarget(u32 pc) const;
bool IsTerminateInstruction() const;
bool IsUnconditionalBranch() const;
bool IsConditionalBranch() const;
bool IsFork() const;
bool IsCmpx() const;
};
} // namespace Shader::Gcn
| 3,821
|
C++
|
.h
| 181
| 17.104972
| 66
| 0.65227
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,973
|
translate.h
|
shadps4-emu_shadPS4/src/shader_recompiler/frontend/translate/translate.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <span>
#include "shader_recompiler/frontend/instruction.h"
#include "shader_recompiler/info.h"
#include "shader_recompiler/ir/basic_block.h"
#include "shader_recompiler/ir/ir_emitter.h"
namespace Shader {
struct Info;
struct Profile;
} // namespace Shader
namespace Shader::Gcn {
enum class ConditionOp : u32 {
F,
EQ,
LG,
GT,
GE,
LT,
LE,
TRU,
U,
};
enum class AtomicOp : u32 {
Swap,
CmpSwap,
Add,
Sub,
Smin,
Umin,
Smax,
Umax,
And,
Or,
Xor,
Inc,
Dec,
FCmpSwap,
Fmin,
Fmax,
};
enum class NegateMode : u32 {
None,
Src1,
Result,
};
class Translator {
public:
explicit Translator(IR::Block* block_, Info& info, const RuntimeInfo& runtime_info,
const Profile& profile);
// Instruction categories
void EmitPrologue();
void EmitFetch(const GcnInst& inst);
void EmitExport(const GcnInst& inst);
void EmitFlowControl(u32 pc, const GcnInst& inst);
void EmitScalarAlu(const GcnInst& inst);
void EmitScalarMemory(const GcnInst& inst);
void EmitVectorAlu(const GcnInst& inst);
void EmitVectorInterpolation(const GcnInst& inst);
void EmitDataShare(const GcnInst& inst);
void EmitVectorMemory(const GcnInst& inst);
// Instruction encodings
void EmitSOPC(const GcnInst& inst);
void EmitSOPK(const GcnInst& inst);
// Scalar ALU
// SOP2
void S_ADD_U32(const GcnInst& inst);
void S_SUB_U32(const GcnInst& inst);
void S_ADD_I32(const GcnInst& inst);
void S_ADDC_U32(const GcnInst& inst);
void S_MIN_U32(bool is_signed, const GcnInst& inst);
void S_MAX_U32(bool is_signed, const GcnInst& inst);
void S_CSELECT_B32(const GcnInst& inst);
void S_CSELECT_B64(const GcnInst& inst);
void S_AND_B32(NegateMode negate, const GcnInst& inst);
void S_AND_B64(NegateMode negate, const GcnInst& inst);
void S_OR_B32(const GcnInst& inst);
void S_OR_B64(NegateMode negate, bool is_xor, const GcnInst& inst);
void S_XOR_B32(const GcnInst& inst);
void S_LSHL_B32(const GcnInst& inst);
void S_LSHR_B32(const GcnInst& inst);
void S_ASHR_I32(const GcnInst& inst);
void S_BFM_B32(const GcnInst& inst);
void S_MUL_I32(const GcnInst& inst);
void S_BFE_U32(const GcnInst& inst);
void S_ABSDIFF_I32(const GcnInst& inst);
// SOPK
void S_MOVK(const GcnInst& inst);
void S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst);
void S_ADDK_I32(const GcnInst& inst);
void S_MULK_I32(const GcnInst& inst);
// SOP1
void S_MOV(const GcnInst& inst);
void S_MOV_B64(const GcnInst& inst);
void S_NOT_B64(const GcnInst& inst);
void S_BREV_B32(const GcnInst& inst);
void S_BCNT1_I32_B64(const GcnInst& inst);
void S_GETPC_B64(u32 pc, const GcnInst& inst);
void S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst);
// SOPC
void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
// SOPP
void S_BARRIER();
void S_SENDMSG(const GcnInst& inst);
// Scalar Memory
// SMRD
void S_LOAD_DWORD(int num_dwords, const GcnInst& inst);
void S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst);
// Vector ALU
// VOP2
void V_CNDMASK_B32(const GcnInst& inst);
void V_READLANE_B32(const GcnInst& inst);
void V_WRITELANE_B32(const GcnInst& inst);
void V_ADD_F32(const GcnInst& inst);
void V_SUB_F32(const GcnInst& inst);
void V_SUBREV_F32(const GcnInst& inst);
void V_MUL_F32(const GcnInst& inst);
void V_MUL_I32_I24(const GcnInst& inst);
void V_MIN_F32(const GcnInst& inst, bool is_legacy = false);
void V_MAX_F32(const GcnInst& inst, bool is_legacy = false);
void V_MIN_I32(const GcnInst& inst);
void V_MIN_U32(const GcnInst& inst);
void V_MAX_U32(bool is_signed, const GcnInst& inst);
void V_LSHR_B32(const GcnInst& inst);
void V_LSHRREV_B32(const GcnInst& inst);
void V_ASHR_I32(const GcnInst& inst);
void V_ASHRREV_I32(const GcnInst& inst);
void V_LSHL_B32(const GcnInst& inst);
void V_LSHLREV_B32(const GcnInst& inst);
void V_AND_B32(const GcnInst& inst);
void V_OR_B32(bool is_xor, const GcnInst& inst);
void V_BFM_B32(const GcnInst& inst);
void V_MAC_F32(const GcnInst& inst);
void V_MADMK_F32(const GcnInst& inst);
void V_BCNT_U32_B32(const GcnInst& inst);
void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
void V_ADD_I32(const GcnInst& inst);
void V_SUB_I32(const GcnInst& inst);
void V_SUBREV_I32(const GcnInst& inst);
void V_ADDC_U32(const GcnInst& inst);
void V_SUBB_U32(const GcnInst& inst);
void V_SUBBREV_U32(const GcnInst& inst);
void V_LDEXP_F32(const GcnInst& inst);
void V_CVT_PKNORM_U16_F32(const GcnInst& inst);
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
// VOP1
void V_MOV(const GcnInst& inst);
void V_READFIRSTLANE_B32(const GcnInst& inst);
void V_CVT_I32_F64(const GcnInst& inst);
void V_CVT_F64_I32(const GcnInst& inst);
void V_CVT_F32_I32(const GcnInst& inst);
void V_CVT_F32_U32(const GcnInst& inst);
void V_CVT_U32_F32(const GcnInst& inst);
void V_CVT_I32_F32(const GcnInst& inst);
void V_CVT_F16_F32(const GcnInst& inst);
void V_CVT_F32_F16(const GcnInst& inst);
void V_CVT_RPI_I32_F32(const GcnInst& inst);
void V_CVT_FLR_I32_F32(const GcnInst& inst);
void V_CVT_OFF_F32_I4(const GcnInst& inst);
void V_CVT_F32_F64(const GcnInst& inst);
void V_CVT_F64_F32(const GcnInst& inst);
void V_CVT_F32_UBYTE(u32 index, const GcnInst& inst);
void V_FRACT_F32(const GcnInst& inst);
void V_TRUNC_F32(const GcnInst& inst);
void V_CEIL_F32(const GcnInst& inst);
void V_RNDNE_F32(const GcnInst& inst);
void V_FLOOR_F32(const GcnInst& inst);
void V_EXP_F32(const GcnInst& inst);
void V_LOG_F32(const GcnInst& inst);
void V_RCP_F32(const GcnInst& inst);
void V_RCP_F64(const GcnInst& inst);
void V_RSQ_F32(const GcnInst& inst);
void V_SQRT_F32(const GcnInst& inst);
void V_SIN_F32(const GcnInst& inst);
void V_COS_F32(const GcnInst& inst);
void V_NOT_B32(const GcnInst& inst);
void V_BFREV_B32(const GcnInst& inst);
void V_FFBH_U32(const GcnInst& inst);
void V_FFBL_B32(const GcnInst& inst);
void V_MOVRELD_B32(const GcnInst& inst);
void V_MOVRELS_B32(const GcnInst& inst);
void V_MOVRELSD_B32(const GcnInst& inst);
// VOPC
void V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst);
void V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst);
void V_CMP_NE_U64(const GcnInst& inst);
void V_CMP_CLASS_F32(const GcnInst& inst);
// VOP3a
void V_MAD_F32(const GcnInst& inst);
void V_MAD_I32_I24(const GcnInst& inst, bool is_signed = false);
void V_MAD_U32_U24(const GcnInst& inst);
void V_CUBEID_F32(const GcnInst& inst);
void V_CUBESC_F32(const GcnInst& inst);
void V_CUBETC_F32(const GcnInst& inst);
void V_CUBEMA_F32(const GcnInst& inst);
void V_BFE_U32(bool is_signed, const GcnInst& inst);
void V_BFI_B32(const GcnInst& inst);
void V_FMA_F32(const GcnInst& inst);
void V_FMA_F64(const GcnInst& inst);
void V_MIN3_F32(const GcnInst& inst);
void V_MIN3_I32(const GcnInst& inst);
void V_MAX3_F32(const GcnInst& inst);
void V_MAX3_U32(bool is_signed, const GcnInst& inst);
void V_MED3_F32(const GcnInst& inst);
void V_MED3_I32(const GcnInst& inst);
void V_SAD(const GcnInst& inst);
void V_SAD_U32(const GcnInst& inst);
void V_CVT_PK_U16_U32(const GcnInst& inst);
void V_CVT_PK_U8_F32(const GcnInst& inst);
void V_LSHL_B64(const GcnInst& inst);
void V_MUL_F64(const GcnInst& inst);
void V_MAX_F64(const GcnInst& inst);
void V_MUL_LO_U32(const GcnInst& inst);
void V_MUL_HI_U32(bool is_signed, const GcnInst& inst);
void V_MAD_U64_U32(const GcnInst& inst);
// Vector interpolation
// VINTRP
void V_INTERP_P2_F32(const GcnInst& inst);
void V_INTERP_MOV_F32(const GcnInst& inst);
// Data share
// DS
void DS_ADD_U32(const GcnInst& inst, bool rtn);
void DS_MIN_U32(const GcnInst& inst, bool is_signed, bool rtn);
void DS_MAX_U32(const GcnInst& inst, bool is_signed, bool rtn);
void DS_WRITE(int bit_size, bool is_signed, bool is_pair, bool stride64, const GcnInst& inst);
void DS_SWIZZLE_B32(const GcnInst& inst);
void DS_READ(int bit_size, bool is_signed, bool is_pair, bool stride64, const GcnInst& inst);
void DS_APPEND(const GcnInst& inst);
void DS_CONSUME(const GcnInst& inst);
// Buffer Memory
// MUBUF / MTBUF
void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
void BUFFER_LOAD_FORMAT(u32 num_dwords, const GcnInst& inst);
void BUFFER_STORE(u32 num_dwords, bool is_typed, const GcnInst& inst);
void BUFFER_STORE_FORMAT(u32 num_dwords, const GcnInst& inst);
void BUFFER_ATOMIC(AtomicOp op, const GcnInst& inst);
// Image Memory
// MIMG
void IMAGE_LOAD(bool has_mip, const GcnInst& inst);
void IMAGE_STORE(const GcnInst& inst);
void IMAGE_GET_RESINFO(const GcnInst& inst);
void IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst);
void IMAGE_SAMPLE(const GcnInst& inst);
void IMAGE_GATHER(const GcnInst& inst);
void IMAGE_GET_LOD(const GcnInst& inst);
private:
template <typename T = IR::U32>
[[nodiscard]] T GetSrc(const InstOperand& operand);
template <typename T = IR::U64>
[[nodiscard]] T GetSrc64(const InstOperand& operand);
void SetDst(const InstOperand& operand, const IR::U32F32& value);
void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
// Vector ALU Helpers
IR::U32 GetCarryIn(const GcnInst& inst);
void SetCarryOut(const GcnInst& inst, const IR::U1& carry);
IR::U32 VMovRelSHelper(u32 src_vgprno, const IR::U32 m0);
void VMovRelDHelper(u32 dst_vgprno, const IR::U32 src_val, const IR::U32 m0);
void LogMissingOpcode(const GcnInst& inst);
private:
IR::IREmitter ir;
Info& info;
const RuntimeInfo& runtime_info;
const Profile& profile;
bool opcode_missing = false;
};
void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list, Info& info,
const RuntimeInfo& runtime_info, const Profile& profile);
} // namespace Shader::Gcn
| 10,576
|
C++
|
.h
| 269
| 34.475836
| 98
| 0.689404
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,974
|
bindings.h
|
shadps4-emu_shadPS4/src/shader_recompiler/backend/bindings.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include "common/types.h"
namespace Shader::Backend {
struct Bindings {
u32 unified{};
u32 buffer{};
u32 user_data{};
auto operator<=>(const Bindings&) const = default;
};
} // namespace Shader::Backend
| 350
|
C++
|
.h
| 12
| 26.333333
| 66
| 0.731928
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,975
|
spirv_emit_context.h
|
shadps4-emu_shadPS4/src/shader_recompiler/backend/spirv/spirv_emit_context.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <array>
#include <sirit/sirit.h>
#include "shader_recompiler/backend/bindings.h"
#include "shader_recompiler/info.h"
#include "shader_recompiler/ir/program.h"
#include "shader_recompiler/profile.h"
namespace Shader::Backend::SPIRV {
using Sirit::Id;
struct VectorIds {
[[nodiscard]] Id& operator[](u32 index) {
return ids[index - 1];
}
[[nodiscard]] const Id& operator[](u32 index) const {
return ids[index - 1];
}
[[nodiscard]] Id& Get(u32 index) {
return ids[index - 1];
}
[[nodiscard]] const Id& Get(u32 index) const {
return ids[index - 1];
}
std::array<Id, 4> ids;
};
class EmitContext final : public Sirit::Module {
public:
explicit EmitContext(const Profile& profile, const RuntimeInfo& runtime_info, const Info& info,
Bindings& binding);
~EmitContext();
Id Def(const IR::Value& value);
void DefineBufferOffsets();
[[nodiscard]] Id DefineInput(Id type, u32 location) {
const Id input_id{DefineVar(type, spv::StorageClass::Input)};
Decorate(input_id, spv::Decoration::Location, location);
return input_id;
}
[[nodiscard]] Id DefineOutput(Id type, std::optional<u32> location = std::nullopt) {
const Id output_id{DefineVar(type, spv::StorageClass::Output)};
if (location) {
Decorate(output_id, spv::Decoration::Location, *location);
}
return output_id;
}
[[nodiscard]] Id DefineUniformConst(Id type, u32 set, u32 binding, bool readonly = false) {
const Id uniform_id{DefineVar(type, spv::StorageClass::UniformConstant)};
Decorate(uniform_id, spv::Decoration::DescriptorSet, set);
Decorate(uniform_id, spv::Decoration::Binding, binding);
if (readonly) {
Decorate(uniform_id, spv::Decoration::NonWritable);
}
return uniform_id;
}
template <bool global = true>
[[nodiscard]] Id DefineVar(Id type, spv::StorageClass storage_class,
std::optional<Id> initializer = std::nullopt) {
const Id pointer_type_id{TypePointer(storage_class, type)};
return global ? AddGlobalVariable(pointer_type_id, storage_class, initializer)
: AddLocalVariable(pointer_type_id, storage_class, initializer);
}
[[nodiscard]] Id DefineVariable(Id type, std::optional<spv::BuiltIn> builtin,
spv::StorageClass storage_class,
std::optional<Id> initializer = std::nullopt) {
const Id id{DefineVar(type, storage_class, initializer)};
if (builtin) {
Decorate(id, spv::Decoration::BuiltIn, *builtin);
}
interfaces.push_back(id);
return id;
}
[[nodiscard]] Id ConstU32(u32 value) {
return Constant(U32[1], value);
}
template <typename... Args>
[[nodiscard]] Id ConstU32(Args&&... values) {
constexpr u32 size = static_cast<u32>(sizeof...(values));
static_assert(size >= 2);
const std::array constituents{Constant(U32[1], values)...};
const Id type = size <= 4 ? U32[size] : TypeArray(U32[1], ConstU32(size));
return ConstantComposite(type, constituents);
}
[[nodiscard]] Id ConstS32(s32 value) {
return Constant(S32[1], value);
}
template <typename... Args>
[[nodiscard]] Id ConstS32(Args&&... values) {
constexpr u32 size = static_cast<u32>(sizeof...(values));
static_assert(size >= 2);
const std::array constituents{Constant(S32[1], values)...};
const Id type = size <= 4 ? S32[size] : TypeArray(S32[1], ConstU32(size));
return ConstantComposite(type, constituents);
}
[[nodiscard]] Id ConstF32(f32 value) {
return Constant(F32[1], value);
}
template <typename... Args>
[[nodiscard]] Id ConstF32(Args... values) {
constexpr u32 size = static_cast<u32>(sizeof...(values));
static_assert(size >= 2);
const std::array constituents{Constant(F32[1], values)...};
const Id type = size <= 4 ? F32[size] : TypeArray(F32[1], ConstU32(size));
return ConstantComposite(type, constituents);
}
const Info& info;
const RuntimeInfo& runtime_info;
const Profile& profile;
Stage stage{};
Id void_id{};
Id U8{};
Id S8{};
Id U16{};
Id S16{};
Id U64{};
VectorIds F16{};
VectorIds F32{};
VectorIds F64{};
VectorIds S32{};
VectorIds U32{};
VectorIds U1{};
Id full_result_i32x2;
Id full_result_u32x2;
Id pi_x2;
Id true_value{};
Id false_value{};
Id u32_one_value{};
Id u32_zero_value{};
Id f32_zero_value{};
Id shared_u8{};
Id shared_u16{};
Id shared_u32{};
Id shared_u32x2{};
Id shared_u32x4{};
Id input_u32{};
Id input_f32{};
Id input_s32{};
Id output_u32{};
Id output_f32{};
Id output_s32{};
Id gl_in{};
boost::container::small_vector<Id, 16> interfaces;
Id output_position{};
Id primitive_id{};
Id vertex_index{};
Id instance_id{};
Id push_data_block{};
Id base_vertex{};
Id frag_coord{};
Id front_facing{};
Id frag_depth{};
Id clip_distances{};
Id cull_distances{};
Id workgroup_id{};
Id local_invocation_id{};
Id subgroup_local_invocation_id{};
Id image_u32{};
Id shared_memory_u8{};
Id shared_memory_u16{};
Id shared_memory_u32{};
Id shared_memory_u32x2{};
Id shared_memory_u32x4{};
Id shared_memory_u32_type{};
struct TextureDefinition {
const VectorIds* data_types;
Id id;
Id sampled_type;
Id pointer_type;
Id image_type;
bool is_integer = false;
bool is_storage = false;
};
struct BufferDefinition {
Id id;
Id offset;
Id offset_dwords;
u32 binding;
const VectorIds* data_types;
Id pointer_type;
};
struct TextureBufferDefinition {
Id id;
Id coord_offset;
u32 binding;
Id image_type;
Id result_type;
bool is_integer = false;
bool is_storage = false;
};
Bindings& binding;
boost::container::small_vector<BufferDefinition, 16> buffers;
boost::container::small_vector<TextureBufferDefinition, 8> texture_buffers;
BufferDefinition srt_flatbuf;
boost::container::small_vector<TextureDefinition, 8> images;
boost::container::small_vector<Id, 4> samplers;
Id sampler_type{};
Id sampler_pointer_type{};
struct SpirvAttribute {
Id id;
Id pointer_type;
Id component_type;
u32 num_components;
bool is_integer{};
bool is_default{};
s32 buffer_handle{-1};
};
std::array<SpirvAttribute, IR::NumParams> input_params{};
std::array<SpirvAttribute, IR::NumParams> output_params{};
std::array<SpirvAttribute, IR::NumRenderTargets> frag_outputs{};
private:
void DefineArithmeticTypes();
void DefineInterfaces();
void DefineInputs();
void DefineOutputs();
void DefinePushDataBlock();
void DefineBuffers();
void DefineTextureBuffers();
void DefineImagesAndSamplers();
void DefineSharedMemory();
SpirvAttribute GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id, u32 num_components,
bool output);
};
} // namespace Shader::Backend::SPIRV
| 7,623
|
C++
|
.h
| 222
| 27.382883
| 99
| 0.625527
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,976
|
emit_spirv_instructions.h
|
shadps4-emu_shadPS4/src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <sirit/sirit.h>
#include "common/types.h"
namespace Shader::IR {
enum class Attribute : u64;
enum class ScalarReg : u32;
class Inst;
class Value;
} // namespace Shader::IR
namespace Shader::Backend::SPIRV {
using Sirit::Id;
class EmitContext;
// Microinstruction emitters
Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
void EmitVoid(EmitContext& ctx);
Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
Id EmitConditionRef(EmitContext& ctx, const IR::Value& value);
void EmitReference(EmitContext&);
void EmitPhiMove(EmitContext&);
void EmitJoin(EmitContext& ctx);
void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
void EmitDeviceMemoryBarrier(EmitContext& ctx);
void EmitGetScc(EmitContext& ctx);
void EmitGetExec(EmitContext& ctx);
void EmitGetVcc(EmitContext& ctx);
void EmitGetSccLo(EmitContext& ctx);
void EmitGetVccLo(EmitContext& ctx);
void EmitGetVccHi(EmitContext& ctx);
void EmitGetM0(EmitContext& ctx);
void EmitSetScc(EmitContext& ctx);
void EmitSetExec(EmitContext& ctx);
void EmitSetVcc(EmitContext& ctx);
void EmitSetSccLo(EmitContext& ctx);
void EmitSetVccLo(EmitContext& ctx);
void EmitSetVccHi(EmitContext& ctx);
void EmitSetM0(EmitContext& ctx);
void EmitFPCmpClass32(EmitContext& ctx);
void EmitPrologue(EmitContext& ctx);
void EmitEpilogue(EmitContext& ctx);
void EmitDiscard(EmitContext& ctx);
void EmitDiscardCond(EmitContext& ctx, Id condition);
void EmitDebugPrint(EmitContext& ctx, IR::Inst* inst, Id arg0, Id arg1, Id arg2, Id arg3, Id arg4);
void EmitBarrier(EmitContext& ctx);
void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
void EmitDeviceMemoryBarrier(EmitContext& ctx);
Id EmitGetUserData(EmitContext& ctx, IR::ScalarReg reg);
void EmitGetThreadBitScalarReg(EmitContext& ctx);
void EmitSetThreadBitScalarReg(EmitContext& ctx);
void EmitGetScalarRegister(EmitContext& ctx);
void EmitSetScalarRegister(EmitContext& ctx);
void EmitGetVectorRegister(EmitContext& ctx);
void EmitSetVectorRegister(EmitContext& ctx);
void EmitSetGotoVariable(EmitContext& ctx);
void EmitGetGotoVariable(EmitContext& ctx);
void EmitSetScc(EmitContext& ctx);
Id EmitReadConst(EmitContext& ctx, IR::Inst* inst);
Id EmitReadConstBuffer(EmitContext& ctx, u32 handle, Id index);
Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
Id EmitLoadBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
Id EmitLoadBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
Id EmitLoadBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
Id EmitLoadBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
void EmitStoreBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
void EmitStoreBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
void EmitStoreBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
void EmitStoreBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
void EmitStoreBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicInc32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp, u32 index);
Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp);
void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 comp);
void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value);
void EmitSetSampleMask(EmitContext& ctx, Id value);
void EmitSetFragDepth(EmitContext& ctx, Id value);
Id EmitWorkgroupId(EmitContext& ctx);
Id EmitLocalInvocationId(EmitContext& ctx);
Id EmitInvocationId(EmitContext& ctx);
Id EmitInvocationInfo(EmitContext& ctx);
Id EmitSampleId(EmitContext& ctx);
Id EmitUndefU1(EmitContext& ctx);
Id EmitUndefU8(EmitContext& ctx);
Id EmitUndefU16(EmitContext& ctx);
Id EmitUndefU32(EmitContext& ctx);
Id EmitUndefU64(EmitContext& ctx);
Id EmitLoadSharedU32(EmitContext& ctx, Id offset);
Id EmitLoadSharedU64(EmitContext& ctx, Id offset);
Id EmitLoadSharedU128(EmitContext& ctx, Id offset);
void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU128(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicSMax32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicUMin32(EmitContext& ctx, Id offset, Id value);
Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value);
Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2);
Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeInsertU32x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertU32x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeConstructF16x2(EmitContext& ctx, Id e1, Id e2);
Id EmitCompositeConstructF16x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructF16x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeConstructF32x2(EmitContext& ctx, Id e1, Id e2);
Id EmitCompositeConstructF32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructF32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeInsertF32x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF32x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index);
void EmitCompositeConstructF64x2(EmitContext& ctx);
void EmitCompositeConstructF64x3(EmitContext& ctx);
void EmitCompositeConstructF64x4(EmitContext& ctx);
void EmitCompositeExtractF64x2(EmitContext& ctx);
void EmitCompositeExtractF64x3(EmitContext& ctx);
void EmitCompositeExtractF64x4(EmitContext& ctx);
Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitBitCastU16F16(EmitContext& ctx, Id value);
Id EmitBitCastU32F32(EmitContext& ctx, Id value);
Id EmitBitCastU64F64(EmitContext& ctx, Id value);
Id EmitBitCastF16U16(EmitContext& ctx, Id value);
Id EmitBitCastF32U32(EmitContext& ctx, Id value);
void EmitBitCastF64U64(EmitContext& ctx);
Id EmitPackUint2x32(EmitContext& ctx, Id value);
Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
Id EmitPackFloat2x32(EmitContext& ctx, Id value);
Id EmitPackFloat2x16(EmitContext& ctx, Id value);
Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
Id EmitPackHalf2x16(EmitContext& ctx, Id value);
Id EmitUnpackHalf2x16(EmitContext& ctx, Id value);
Id EmitFPAbs16(EmitContext& ctx, Id value);
Id EmitFPAbs32(EmitContext& ctx, Id value);
Id EmitFPAbs64(EmitContext& ctx, Id value);
Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPSub32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPMax32(EmitContext& ctx, Id a, Id b, bool is_legacy = false);
Id EmitFPMax64(EmitContext& ctx, Id a, Id b);
Id EmitFPMin32(EmitContext& ctx, Id a, Id b, bool is_legacy = false);
Id EmitFPMin64(EmitContext& ctx, Id a, Id b);
Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPNeg16(EmitContext& ctx, Id value);
Id EmitFPNeg32(EmitContext& ctx, Id value);
Id EmitFPNeg64(EmitContext& ctx, Id value);
Id EmitFPSin(EmitContext& ctx, Id value);
Id EmitFPCos(EmitContext& ctx, Id value);
Id EmitFPExp2(EmitContext& ctx, Id value);
Id EmitFPLdexp(EmitContext& ctx, Id value, Id exp);
Id EmitFPLog2(EmitContext& ctx, Id value);
Id EmitFPRecip32(EmitContext& ctx, Id value);
Id EmitFPRecip64(EmitContext& ctx, Id value);
Id EmitFPRecipSqrt32(EmitContext& ctx, Id value);
Id EmitFPRecipSqrt64(EmitContext& ctx, Id value);
Id EmitFPSqrt(EmitContext& ctx, Id value);
Id EmitFPSaturate16(EmitContext& ctx, Id value);
Id EmitFPSaturate32(EmitContext& ctx, Id value);
Id EmitFPSaturate64(EmitContext& ctx, Id value);
Id EmitFPClamp16(EmitContext& ctx, Id value, Id min_value, Id max_value);
Id EmitFPClamp32(EmitContext& ctx, Id value, Id min_value, Id max_value);
Id EmitFPClamp64(EmitContext& ctx, Id value, Id min_value, Id max_value);
Id EmitFPRoundEven16(EmitContext& ctx, Id value);
Id EmitFPRoundEven32(EmitContext& ctx, Id value);
Id EmitFPRoundEven64(EmitContext& ctx, Id value);
Id EmitFPFloor16(EmitContext& ctx, Id value);
Id EmitFPFloor32(EmitContext& ctx, Id value);
Id EmitFPFloor64(EmitContext& ctx, Id value);
Id EmitFPCeil16(EmitContext& ctx, Id value);
Id EmitFPCeil32(EmitContext& ctx, Id value);
Id EmitFPCeil64(EmitContext& ctx, Id value);
Id EmitFPTrunc16(EmitContext& ctx, Id value);
Id EmitFPTrunc32(EmitContext& ctx, Id value);
Id EmitFPTrunc64(EmitContext& ctx, Id value);
Id EmitFPFract(EmitContext& ctx, Id value);
Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPIsNan16(EmitContext& ctx, Id value);
Id EmitFPIsNan32(EmitContext& ctx, Id value);
Id EmitFPIsNan64(EmitContext& ctx, Id value);
Id EmitFPIsInf32(EmitContext& ctx, Id value);
Id EmitFPIsInf64(EmitContext& ctx, Id value);
Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitIAdd64(EmitContext& ctx, Id a, Id b);
Id EmitIAddCary32(EmitContext& ctx, Id a, Id b);
Id EmitISub32(EmitContext& ctx, Id a, Id b);
Id EmitISub64(EmitContext& ctx, Id a, Id b);
Id EmitSMulExt(EmitContext& ctx, Id a, Id b);
Id EmitUMulExt(EmitContext& ctx, Id a, Id b);
Id EmitIMul32(EmitContext& ctx, Id a, Id b);
Id EmitIMul64(EmitContext& ctx, Id a, Id b);
Id EmitSDiv32(EmitContext& ctx, Id a, Id b);
Id EmitUDiv32(EmitContext& ctx, Id a, Id b);
Id EmitSMod32(EmitContext& ctx, Id a, Id b);
Id EmitUMod32(EmitContext& ctx, Id a, Id b);
Id EmitINeg32(EmitContext& ctx, Id value);
Id EmitINeg64(EmitContext& ctx, Id value);
Id EmitIAbs32(EmitContext& ctx, Id value);
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseAnd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseOr64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
Id EmitBitReverse32(EmitContext& ctx, Id value);
Id EmitBitCount32(EmitContext& ctx, Id value);
Id EmitBitwiseNot32(EmitContext& ctx, Id value);
Id EmitFindSMsb32(EmitContext& ctx, Id value);
Id EmitFindUMsb32(EmitContext& ctx, Id value);
Id EmitFindILsb32(EmitContext& ctx, Id value);
Id EmitSMin32(EmitContext& ctx, Id a, Id b);
Id EmitUMin32(EmitContext& ctx, Id a, Id b);
Id EmitSMax32(EmitContext& ctx, Id a, Id b);
Id EmitUMax32(EmitContext& ctx, Id a, Id b);
Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
Id EmitSLessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSLessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitULessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitULessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitLogicalOr(EmitContext& ctx, Id a, Id b);
Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b);
Id EmitLogicalXor(EmitContext& ctx, Id a, Id b);
Id EmitLogicalNot(EmitContext& ctx, Id value);
Id EmitConvertS16F16(EmitContext& ctx, Id value);
Id EmitConvertS16F32(EmitContext& ctx, Id value);
Id EmitConvertS16F64(EmitContext& ctx, Id value);
Id EmitConvertS32F16(EmitContext& ctx, Id value);
Id EmitConvertS32F32(EmitContext& ctx, Id value);
Id EmitConvertS32F64(EmitContext& ctx, Id value);
Id EmitConvertS64F16(EmitContext& ctx, Id value);
Id EmitConvertS64F32(EmitContext& ctx, Id value);
Id EmitConvertS64F64(EmitContext& ctx, Id value);
Id EmitConvertU16F16(EmitContext& ctx, Id value);
Id EmitConvertU16F32(EmitContext& ctx, Id value);
Id EmitConvertU16F64(EmitContext& ctx, Id value);
Id EmitConvertU32F16(EmitContext& ctx, Id value);
Id EmitConvertU32F32(EmitContext& ctx, Id value);
Id EmitConvertU32F64(EmitContext& ctx, Id value);
Id EmitConvertU64F16(EmitContext& ctx, Id value);
Id EmitConvertU64F32(EmitContext& ctx, Id value);
Id EmitConvertU64F64(EmitContext& ctx, Id value);
Id EmitConvertU64U32(EmitContext& ctx, Id value);
Id EmitConvertU32U64(EmitContext& ctx, Id value);
Id EmitConvertF16F32(EmitContext& ctx, Id value);
Id EmitConvertF32F16(EmitContext& ctx, Id value);
Id EmitConvertF32F64(EmitContext& ctx, Id value);
Id EmitConvertF64F32(EmitContext& ctx, Id value);
Id EmitConvertF16S8(EmitContext& ctx, Id value);
Id EmitConvertF16S16(EmitContext& ctx, Id value);
Id EmitConvertF16S32(EmitContext& ctx, Id value);
Id EmitConvertF16S64(EmitContext& ctx, Id value);
Id EmitConvertF16U8(EmitContext& ctx, Id value);
Id EmitConvertF16U16(EmitContext& ctx, Id value);
Id EmitConvertF16U32(EmitContext& ctx, Id value);
Id EmitConvertF16U64(EmitContext& ctx, Id value);
Id EmitConvertF32S8(EmitContext& ctx, Id value);
Id EmitConvertF32S16(EmitContext& ctx, Id value);
Id EmitConvertF32S32(EmitContext& ctx, Id value);
Id EmitConvertF32S64(EmitContext& ctx, Id value);
Id EmitConvertF32U8(EmitContext& ctx, Id value);
Id EmitConvertF32U16(EmitContext& ctx, Id value);
Id EmitConvertF32U32(EmitContext& ctx, Id value);
Id EmitConvertF32U64(EmitContext& ctx, Id value);
Id EmitConvertF64S8(EmitContext& ctx, Id value);
Id EmitConvertF64S16(EmitContext& ctx, Id value);
Id EmitConvertF64S32(EmitContext& ctx, Id value);
Id EmitConvertF64S64(EmitContext& ctx, Id value);
Id EmitConvertF64U8(EmitContext& ctx, Id value);
Id EmitConvertF64U16(EmitContext& ctx, Id value);
Id EmitConvertF64U32(EmitContext& ctx, Id value);
Id EmitConvertF64U64(EmitContext& ctx, Id value);
Id EmitConvertU16U32(EmitContext& ctx, Id value);
Id EmitConvertU32U16(EmitContext& ctx, Id value);
Id EmitImageSampleRaw(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address1, Id address2,
Id address3, Id address4);
Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias,
const IR::Value& offset);
Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod,
const IR::Value& offset);
Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
Id bias, const IR::Value& offset);
Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
Id lod, const IR::Value& offset);
Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
const IR::Value& offset);
Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
const IR::Value& offset, Id dref);
Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, const IR::Value& offset,
Id lod, Id ms);
Id EmitImageQueryDimensions(EmitContext& ctx, IR::Inst* inst, u32 handle, Id lod, bool skip_mips);
Id EmitImageQueryLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords);
Id EmitImageGradient(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id derivatives_dx,
Id derivatives_dy, const IR::Value& offset, const IR::Value& lod_clamp);
Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords);
void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id color);
Id EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicInc32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value);
Id EmitLaneId(EmitContext& ctx);
Id EmitWarpId(EmitContext& ctx);
Id EmitQuadShuffle(EmitContext& ctx, Id value, Id index);
Id EmitReadFirstLane(EmitContext& ctx, Id value);
Id EmitReadLane(EmitContext& ctx, Id value, u32 lane);
Id EmitWriteLane(EmitContext& ctx, Id value, Id write_value, u32 lane);
Id EmitDataAppend(EmitContext& ctx, u32 gds_addr, u32 binding);
Id EmitDataConsume(EmitContext& ctx, u32 gds_addr, u32 binding);
void EmitEmitVertex(EmitContext& ctx);
void EmitEmitPrimitive(EmitContext& ctx);
} // namespace Shader::Backend::SPIRV
| 23,552
|
C++
|
.h
| 406
| 56.413793
| 99
| 0.784655
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,977
|
emit_spirv.h
|
shadps4-emu_shadPS4/src/shader_recompiler/backend/spirv/emit_spirv.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <vector>
#include "shader_recompiler/backend/bindings.h"
#include "shader_recompiler/ir/program.h"
#include "shader_recompiler/profile.h"
namespace Shader::Backend::SPIRV {
[[nodiscard]] std::vector<u32> EmitSPIRV(const Profile& profile, const RuntimeInfo& runtime_info,
const IR::Program& program, Bindings& binding);
} // namespace Shader::Backend::SPIRV
| 537
|
C++
|
.h
| 11
| 43.636364
| 97
| 0.731286
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
15,978
|
main_window_themes.h
|
shadps4-emu_shadPS4/src/qt_gui/main_window_themes.h
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#include <QApplication>
#include <QLineEdit>
#include <QWidget>
enum class Theme : int {
Dark,
Light,
Green,
Blue,
Violet,
};
class WindowThemes : public QObject {
Q_OBJECT
public Q_SLOTS:
void SetWindowTheme(Theme theme, QLineEdit* mw_searchbar);
};
| 408
|
C++
|
.h
| 18
| 19.888889
| 66
| 0.740933
|
shadps4-emu/shadPS4
| 9,253
| 501
| 185
|
GPL-2.0
|
9/20/2024, 9:26:25 PM (Europe/Amsterdam)
| false
| false
| false
| false
| false
| false
| false
| false
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.