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3,101 | In a master/slave multiprocessor system, the master CPU is in control of the computer and the slave CPU performs assigned tasks. The CPUs can be completely different in terms of speed and architecture. Some of the CPUs can share a common bus, each can also have a private bus , or they may be isolated except for a co... |
3,102 | Two early examples of a mainframe master/slave multiprocessor are the Bull Gamma 60 and the Burroughs B5000. |
3,103 | An early example of a master/slave multiprocessor system of microprocessors is the Tandy/Radio Shack TRS-80 Model 16 desktop computer which came out in February 1982 and ran the multi-user/multi-tasking Xenix operating system, Microsoft's version of UNIX . The Model 16 has two microprocessors: an 8-bit Zilog Z80 CPU r... |
3,104 | The earlier TRS-80 Model II, which was released in 1979, could also be considered a multiprocessor system as it had both a Z-80 CPU and an Intel 8021 microcontroller in the keyboard. The 8021 made the Model II the first desktop computer system with a separate detachable lightweight keyboard connected with by a single ... |
3,105 | In multiprocessing, the processors can be used to execute a single sequence of instructions in multiple contexts , multiple sequences of instructions in a single context , or multiple sequences of instructions in multiple contexts . |
3,106 | Tightly coupled multiprocessor systems contain multiple CPUs that are connected at the bus level. These CPUs may have access to a central shared memory , or may participate in a memory hierarchy with both local and shared memory . The IBM p690 Regatta is an example of a high end SMP system. Intel Xeon processors domin... |
3,107 | Chip multiprocessors, also known as multi-core computing, involves more than one processor placed on a single chip and can be thought of the most extreme form of tightly coupled multiprocessing. Mainframe systems with multiple processors are often tightly coupled. |
3,108 | Loosely coupled multiprocessor systems are based on multiple standalone relatively low processor count commodity computers interconnected via a high speed communication system . A Linux Beowulf cluster is an example of a loosely coupled system. |
3,109 | Tightly coupled systems perform better and are physically smaller than loosely coupled systems, but have historically required greater initial investments and may depreciate rapidly; nodes in a loosely coupled system are usually inexpensive commodity computers and can be recycled as independent machines upon retirement... |
3,110 | Power consumption is also a consideration. Tightly coupled systems tend to be much more energy-efficient than clusters. This is because a considerable reduction in power consumption can be realized by designing components to work together from the beginning in tightly coupled systems, whereas loosely coupled systems us... |
3,111 | Loosely coupled systems have the ability to run different operating systems or OS versions on different systems. |
3,112 | The user can be the source of an event. The user may interact with the software through the computer's peripherals - for example, by typing on a akeyboard or clicking with a mouse. Another source is a hardware device such as a timer. Software can also trigger its own set of events into the event loop, e.g. to communica... |
3,113 | Event driven systems are typically used when there is some asynchronous external activity that needs to be handled by a program; for example, a user who presses a button on their mouse. An event driven system typically runs an event loop, that keeps waiting for such activities, e.g. input from devices or internal alarm... |
3,114 | A program can choose to ignore events, and there may be libraries to dispatch an event to multiple handlers that may be programmed to listen for a particular event. The data associated with an event at a minimum specifies what type of event it is, but may include other information such as when it occurred, who or what ... |
3,115 | Events are typically used in user interfaces, where actions in the outside world are handled by the program as a series of events. Programs written for many windowing environments consist predominantly of event handlers. |
3,116 | Events can also be used at instruction set level, where they complement interrupts. Compared to interrupts, events are normally implemented synchronously: the program explicitly waits for an event to be generated and handled , whereas an interrupt can demand immediate service. |
3,117 | There are a large number of situations or events that a program or system may generate or respond to. Some common user generated events include: |
3,118 | A pointing device can generate a number of software recognisable pointing device gestures. A mouse can generate a number of mouse events, such as mouse move , mouse left/right button up/down and mouse wheel motion, or a combination of these gestures. For example, double-clicks commonly select words and characters withi... |
3,119 | Pressing a key on a keyboard or a combination of keys generates a keyboard event, enabling the program currently running to respond to the introduced data such as which key/s the user pressed. |
3,120 | Moving a joystick generates an X-Y analogue signal. They often have multiple buttons to trigger events. Some gamepads for popular game boxes use joysticks. |
3,121 | The events generated using a touchscreen are commonly referred to as touch events or gestures. |
3,122 | Device events include action by or to a device, such as a shake, tilt, rotation, move etc. |
3,123 | A common variant in object-oriented programming is the delegate event model, which is provided by some graphic user interfaces. This model is based on three entities: |
3,124 | Furthermore, the model requires that: |
3,125 | C# uses events as special delegates that can only be fired by the class that declares it. This allows for better abstraction, for example: |
3,126 | In computer programming, an event handler may be implemented using a callback subroutine that handles inputs received in a program . Each event is a piece of application-level information from the underlying framework, typically the GUI toolkit. GUI events include key presses, mouse movement, action selections, and tim... |
3,127 | The events are created by the framework based on interpreting lower-level inputs, which may be lower-level events themselves. For example, mouse movements and clicks are interpreted as menu selections. The events initially originate from actions on the operating system level, such as interrupts generated by hardware de... |
3,128 | Created events are first processed by an event dispatcher within the framework. It typically manages the associations between events and event handlers, and may queue event handlers or events for later processing. Event dispatchers may call event handlers directly, or wait for events to be dequeued with information abo... |
3,129 | Event notification is a term used in conjunction with communications software for linking applications that generate small messages to applications that monitor the associated conditions and may take actions triggered by events. |
3,130 | Event notification is an important feature in modern database systems , modern operating systems , and modern distributed systems, where the producer of an event might be on a different machine than the consumer, or consumers. Event notification platforms are normally designed so that the application producing events d... |
3,131 | It is sometimes used as a synonym for publish-subscribe, a term that relates to one class of products supporting event notification in networked settings. The virtual synchrony model is sometimes used to endow event notification systems, and publish-subscribe systems, with stronger fault-tolerance and consistency guara... |
3,132 | Interrupts are commonly used by hardware devices to indicate electronic or physical state changes that require time-sensitive attention. Interrupts are also commonly used to implement computer multitasking and system calls, especially in real-time computing. Systems that use interrupts in these ways are said to be inte... |
3,133 | Hardware interrupts were introduced as an optimization, eliminating unproductive waiting time in polling loops, waiting for external events. The first system to use this approach was the DYSEAC, completed in 1954, although earlier systems provided error trap functions. |
3,134 | The UNIVAC 1103A computer is generally credited with the earliest use of interrupts in 1953. Earlier, on the UNIVAC I "Arithmetic overflow either triggered the execution of a two-instruction fix-up routine at address 0, or, at the programmer's option, caused the computer to stop." The IBM 650 incorporated the first o... |
3,135 | Interrupt signals may be issued in response to hardware or software events. These are classified as hardware interrupts or software interrupts, respectively. For any particular processor, the number of interrupt types is limited by the architecture. |
3,136 | A hardware interrupt is a condition related to the state of the hardware that may be signaled by an external hardware device, e.g., an interrupt request line on a PC, or detected by devices embedded in processor logic , to communicate that the device needs attention from the operating system or, if there is no OS, fr... |
3,137 | Hardware interrupts can arrive asynchronously with respect to the processor clock, and at any time during instruction execution. Consequently, all incoming hardware interrupt signals are conditioned by synchronizing them to the processor clock, and acted upon only at instruction execution boundaries. |
3,138 | In many systems, each device is associated with a particular IRQ signal. This makes it possible to quickly determine which hardware device is requesting service, and to expedite servicing of that device. |
3,139 | On some older systems, such as the 1964 CDC 3600, all interrupts went to the same location, and the OS used a specialized instruction to determine the highest-priority outstanding unmasked interrupt. On contemporary systems, there is generally a distinct interrupt routine for each type of interrupt , often implemented ... |
3,140 | To mask an interrupt is to disable it, so it is deferred or ignored by the processor, while to unmask an interrupt is to enable it. |
3,141 | Processors typically have an internal interrupt mask register, which allows selective enabling of hardware interrupts. Each interrupt signal is associated with a bit in the mask register. On some systems, the interrupt is enabled when the bit is set, and disabled when the bit is clear. On others, the reverse is true, ... |
3,142 | Some interrupt signals are not affected by the interrupt mask and therefore cannot be disabled; these are called non-maskable interrupts . These indicate high-priority events which cannot be ignored under any circumstances, such as the timeout signal from a watchdog timer. With regard to SPARC, the Non-Maskable Interru... |
3,143 | One failure mode is when the hardware does not generate the expected interrupt for a change in state, causing the operating system to wait indefinitely. Depending on the details, the failure might affect only a single process or might have global impact. Some operating systems have code specifically to deal with this. |
3,144 | As an example, IBM Operating System/360 relies on a not-ready to ready device-end interrupt when a tape has been mounted on a tape drive, and will not read the tape label until that interrupt occurs or is simulated. IBM added code in OS/360 so that the VARY ONLINE command will simulate a device end interrupt on the ta... |
3,145 | A spurious interrupt is a hardware interrupt for which no source can be found. The term "phantom interrupt" or "ghost interrupt" may also be used to describe this phenomenon. Spurious interrupts tend to be a problem with a wired-OR interrupt circuit attached to a level-sensitive processor input. Such interrupts may ... |
3,146 | In a wired-OR circuit, parasitic capacitance charging/discharging through the interrupt line's bias resistor will cause a small delay before the processor recognizes that the interrupt source has been cleared. If the interrupting device is cleared too late in the interrupt service routine , there will not be enough ti... |
3,147 | A spurious interrupt may also be the result of electrical anomalies due to faulty circuit design, high noise levels, crosstalk, timing issues, or more rarely, device errata. |
3,148 | A spurious interrupt may result in system deadlock or other undefined operation if the ISR does not account for the possibility of such an interrupt occurring. As spurious interrupts are mostly a problem with wired-OR interrupt circuits, good programming practice in such systems is for the ISR to check all interrupt s... |
3,149 | A software interrupt is requested by the processor itself upon executing particular instructions or when certain conditions are met. Every software interrupt signal is associated with a particular interrupt handler. |
3,150 | A software interrupt may be intentionally caused by executing a special instruction which, by design, invokes an interrupt when executed. Such instructions function similarly to subroutine calls and are used for a variety of purposes, such as requesting operating system services and interacting with device drivers . So... |
3,151 | Typically, the operating system kernel will catch and handle such interrupts. Some interrupts are handled transparently to the program - for example, the normal resolution of a page fault is to make the required page accessible in physical memory. But in other cases such as a segmentation fault the operating system exe... |
3,152 | In a kernel process, it is often the case that some types of software interrupts are not supposed to happen. If they occur nonetheless, an operating system crash may result. |
3,153 | The terms interrupt, trap, exception, fault, and abort are used to distinguish types of interrupts, although "there is no clear consensus as to the exact meaning of these terms". The term trap may refer to any interrupt, to any software interrupt, to any synchronous software interrupt, or only to interrupts caused by i... |
3,154 | x86 divides interrupts into interrupts and software exceptions, and identifies three types of exceptions: faults, traps, and aborts. interrupts are interrupts triggered asynchronously by an I/O device, and allow the program to be restarted with no loss of continuity. A fault is restartable as well but is tied to the ... |
3,155 | Arm uses the term exception to refer to all types of interrupts, and divides exceptions into interrupts, aborts, reset, and exception-generating instructions. Aborts correspond to x86 exceptions and may be prefetch aborts or data aborts , and may be synchronous or asynchronous. Asynchronous aborts may be precise or i... |
3,156 | RISC-V uses interrupt as the overall term as well as for the external subset; internal interrupts are called exceptions. |
3,157 | Each interrupt signal input is designed to be triggered by either a logic signal level or a particular signal edge . Level-sensitive inputs continuously request processor service so long as a particular logic level is applied to the input. Edge-sensitive inputs react to signal edges: a particular edge will cause a se... |
3,158 | A level-triggered interrupt is requested by holding the interrupt signal at its particular active logic level. A device invokes a level-triggered interrupt by driving the signal to and holding it at the active level. It negates the signal when the processor commands it to do so, typically after the device has been ser... |
3,159 | The processor samples the interrupt input signal during each instruction cycle. The processor will recognize the interrupt request if the signal is asserted when sampling occurs. |
3,160 | Level-triggered inputs allow multiple devices to share a common interrupt signal via wired-OR connections. The processor polls to determine which devices are requesting service. After servicing a device, the processor may again poll and, if necessary, service other devices before exiting the ISR. |
3,161 | An edge-triggered interrupt is an interrupt signaled by a level transition on the interrupt line, either a falling edge or a rising edge . A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its inactive state. If the pulse is too short to be detected by polled I/O then s... |
3,162 | Computers with edge-triggered interrupts may include an interrupt register that retains the status of pending interrupts. Systems with interrupt registers generally have interrupt mask registers as well. |
3,163 | The processor samples the interrupt trigger signals or interrupt register during each instruction cycle, and will process the highest priority enabled interrupt found.
Regardless of the triggering method, the processor will begin interrupt processing at the next instruction boundary following a detected trigger, thus e... |
3,164 | There are several different architectures for handling interrupts. In some, there is a single interrupt handler that must scan for the highest priority enabled interrupt. In others, there are separate interrupt handlers for separate interrupt types, separate I/O channels or devices, or both. Several interrupt causes m... |
3,165 | Interrupts may be fully handled in hardware by the CPU, or may be handled by both the CPU and another component such as a programmable interrupt controller or a southbridge. |
3,166 | If an additional component is used, that component would be connected between the interrupting device and the processor's interrupt pin to multiplex several sources of interrupt onto the one or two CPU lines typically available. If implemented as part of the memory controller, interrupts are mapped into the system's me... |
3,167 | In systems on a chip implementations, interrupts come from different blocks of the chip and are usually aggregated in an interrupt controller attached to one or several processors . |
3,168 | Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to its inactive state, which is the default state of it. Devices signal an interrupt by briefly driving the line to its non-defau... |
3,169 | Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, while interrupts from high-priority devices continue to be received and get serviced. If there is a device that the CPU does not know how to service, wh... |
3,170 | The elderly Industry Standard Architecture bus uses edge-triggered interrupts, without mandating that devices be able to share IRQ lines, but all mainstream ISA motherboards include pull-up resistors on their IRQ lines, so well-behaved ISA devices sharing IRQ lines should just work fine. The parallel port also uses ed... |
3,171 | There are 3 ways multiple devices "sharing the same line" can be raised. First is by exclusive conduction or exclusive connection . Next is by bus : cards on a bus must know when they are to talk and not talk . Talking can be triggered in two ways: by accumulation latch or by logic gates. Logic gates expect a cont... |
3,172 | Triggering for software interrupts must be built into the software . A 'C' app has a trigger table in its header, which both the app and OS know of and use appropriately that is not related to hardware. However do not confuse this with hardware interrupts which signal the CPU . |
3,173 | Multiple devices sharing an interrupt line all act as spurious interrupt sources with respect to each other. With many devices on one line, the workload in servicing interrupts grows in proportion to the square of the number of devices. It is therefore preferred to spread devices evenly across the available interrup... |
3,174 | Some devices with a poorly designed programming interface provide no way to determine whether they have requested service. They may lock up or otherwise misbehave if serviced when they do not want it. Such devices cannot tolerate spurious interrupts, and so also cannot tolerate sharing an interrupt line. ISA cards, du... |
3,175 | Some systems use a hybrid of level-triggered and edge-triggered signaling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time. |
3,176 | A common use of a hybrid interrupt is for the NMI input. Because NMIs generally signal major – or even catastrophic – system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false i... |
3,177 | A message-signaled interrupt does not use a physical interrupt line. Instead, a device signals its request for service by sending a short message over some communications medium, typically a computer bus. The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory ... |
3,178 | Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition. Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signaled interrupts with the same message are allowed to... |
3,179 | Message-signalled interrupt vectors can be shared, to the extent that the underlying communication medium can be shared. No additional effort is required. |
3,180 | Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled. This reduces the need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any additional lines. |
3,181 | PCI Express, a serial computer bus, uses message-signaled interrupts exclusively. |
3,182 | In a push button analogy applied to computer systems, the term doorbell or doorbell interrupt is often used to describe a mechanism whereby a software system can signal or notify a computer hardware device that there is some work to be done. Typically, the software system will place data in some well-known and mutuall... |
3,183 | The term doorbell interrupt is usually a misnomer. It is similar to an interrupt, because it causes some work to be done by the device; however, the doorbell region is sometimes implemented as a polled region, sometimes the doorbell region writes through to physical device registers, and sometimes the doorbell region ... |
3,184 | Doorbell interrupts can be compared to Message Signaled Interrupts, as they have some similarities. |
3,185 | In multiprocessor systems, a processor may send an interrupt request to another processor via inter-processor interrupts . |
3,186 | Interrupts provide low overhead and good latency at low load, but degrade significantly at high interrupt rate unless care is taken to prevent several pathologies. The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an inte... |
3,187 | There are various forms of livelocks, when the system spends all of its time processing interrupts to the exclusion of other required tasks.
Under extreme conditions, a large number of interrupts may completely stall the system. To avoid such problems, an operating system must schedule network interrupt handling as ca... |
3,188 | With multi-core processors, additional performance improvements in interrupt handling can be achieved through receive-side scaling when multiqueue NICs are used. Such NICs provide multiple receive queues associated to separate interrupts; by routing each of those interrupts to different cores, processing of the inter... |
3,189 | A purely software-based implementation of the receiving traffic distribution, known as receive packet steering , distributes received traffic among cores later in the data path, as part of the interrupt handler functionality. Advantages of RPS over RSS include no requirements for specific hardware, more advanced traff... |
3,190 | Interrupts are commonly used to service hardware timers, transfer data to and from storage and communication interfaces , handle keyboard and mouse events, and to respond to any other time-sensitive events as required by the application system. Non-maskable interrupts are typically used to respond to high-priority req... |
3,191 | Hardware timers are often used to generate periodic interrupts. In some applications, such interrupts are counted by the interrupt handler to keep track of absolute or elapsed time, or used by the OS task scheduler to manage execution of running processes, or both. Periodic interrupts are also commonly used to invoke s... |
3,192 | A disk interrupt signals the completion of a data transfer from or to the disk peripheral; this may cause a process to run which is waiting to read or write. A power-off interrupt predicts imminent loss of power, allowing the computer to perform an orderly shut-down while there still remains enough power to do so. Keyb... |
3,193 | Interrupts are sometimes used to emulate instructions which are unimplemented on some computers in a product family. For example floating point instructions may be implemented in hardware on some systems and emulated on lower-cost systems. In the latter case, execution of an unimplemented floating point instruction wil... |
3,194 | Interrupts are similar to signals, the difference being that signals are used for inter-process communication , mediated by the kernel and handled by processes, while interrupts are mediated by the processor and handled by the kernel. The kernel may pass an interrupt as a signal to the process that caused it . |
3,195 | Multitasking does not require parallel execution of multiple tasks at exactly the same time; instead, it allows more than one task to advance over a given period of time. Even on multiprocessor computers, multitasking allows many more tasks to be run than there are CPUs. |
3,196 | Multitasking is a common feature of computer operating systems since at least the 1960s. It allows more efficient use of the computer hardware; when a program is waiting for some external event such as a user input or an input/output transfer with a peripheral to complete, the central processor can still be used with ... |
3,197 | Often multitasking operating systems include measures to change the priority of individual tasks, so that important jobs receive more processor time than those considered less significant. Depending on the operating system, a task might be as large as an entire application program, or might be made up of smaller thread... |
3,198 | A processor intended for use with multitasking operating systems may include special hardware to securely support multiple tasks, such as memory protection, and protection rings that ensure the supervisory software cannot be damaged or subverted by user-mode program errors. |
3,199 | The term "multitasking" has become an international term, as the same word is used in many other languages such as German, Italian, Dutch, Romanian, Czech, Danish and Norwegian. |
3,200 | In the early days of computing, CPU time was expensive, and peripherals were very slow. When the computer ran a program that needed access to a peripheral, the central processing unit would have to stop executing program instructions while the peripheral processed the data. This was usually very inefficient. Multiprog... |
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