KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

content stringlengths 0 376M
<reponame>martinda/hdlConvertor<filename>.travis.yml sudo: required dist: xenial language: python git: depth: 1 cache: - apt: true - pip : true matrix: include: - name: "Python 2.7 gcc-8" python: 2.7 env: CC=gcc-8 CXX=g++-8 addons: apt: sources: ...
<gh_stars>100-1000 # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: tcdm_interface authors: - <NAME> <<EMAIL>> dependencies: reqrsp_interface: {path: ../reqrsp_interface} export_includ...
<filename>env/azure_pipeline.yaml # Triggers are currently handled by branch policy for build validation in azure devops trigger: none # trigger: # batch: true # branches: # include: # - master stages: - stage: 'all' jobs: - job: 'CI_no_license' pool: name: CI_no_license ste...
<filename>.github/workflows/test.yml<gh_stars>10-100 name: Test on: push: pull_request: jobs: action: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Run VUnit tests uses: ./ with: cmd: test/run.py container-job: runs-on: ubuntu-latest contain...
version: 1 formatters: colored: format: '[%(asctime)s] (%(color)s%(slvl)s%(crst)s) %(name)-6s %(msgcolor)s%(message)s%(crst)s' nocolor: format: '[%(asctime)s] (%(slvl)s) %(name)-6s %(message)s' handlers: console: class: logging.StreamHandler level: INFO formatter:...
<gh_stars>0 identifier: fwrisc_test name: fwrisc SoC type: mcu arch: riscv32 toolchain: - zephyr ram: 32 testing: ignore_tags: - net - bluetooth
<reponame>usmnzain/serv on: [push, pull_request] jobs: lint: runs-on: ubuntu-latest name: Linter steps: - name: Checkout uses: actions/checkout@v1 - name: Lint Verilog source files with Verilator uses: librecores/ci-fusesoc-action@main with: command: 'run' ...
name: ci on: [push] jobs: ################ # Verible Lint # ################ verilog: name: Verilog Sources # This job runs on Linux (fixed ubuntu version) runs-on: ubuntu-18.04 env: VERIBLE_VERSION: 0.0-807-g10e7c71 steps: - uses: actions/checkout@v2 - name: Install Verible ...
# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # rtl: path: .. tech_cells_generic: path: ../../tech_cells_generic
<filename>external/opensocdebug/software/shippable.yml<gh_stars>10-100 language: c compiler: - gcc env: global: # Codecov upload token: CODECOV_TOKEN=xxx # To decrypt/replace go to the Shippable UI into the project settings - secure: <KEY> matrix: # Configure options (resulting in one build job ...
# action.yml name: 'Hawkeye CLI Scanner' description: Runs the Hawkeye CLI scanner runs: using: 'docker' image: 'Dockerfile'
<reponame>mfkiwl/garnet<gh_stars>0 name: gen_sram_macro commands: - bash gen_srams.sh inputs: - adk outputs: - sram.v - sram-pwr.v - sram.lef - sram_tt.lib - sram_ff.lib - sram_tt.db # Need this back for power on ptpx - sram.gds - sram.spi parameters: num_words: 2048 word_size: 64 mux_siz...
package: name: apb_fll_if dependencies: apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.1.0 } sources: - src/fll_intf.sv - src/apb_fll_if.sv - src/apb_to_fll.sv - target: test files: - test/apb_fll_tb.sv
<reponame>DanielTRYTRYLOOK/RDF-2020 name: usbf_top clock_port: clk_i verilog: - usbf_crc16.v - usbf_crc5.v - usbf_defines.v - usbf_ep_rf.v - usbf_ep_rf_dummy.v - usbf_idma.v - usbf_mem_arb.v - usbf_pa.v - usbf_pd.v - usbf_pe.v - usbf_pl.v - usbf_rf.v - usbf_top.v ...
<filename>.landscape.yaml max-line-length: 300 ignore-paths: - pybar/utils - pybar/scans/deprecated ignore-patterns: - analyze_test_beam
hw-mac-engine: incdirs : [ rtl ] files : [ rtl/mac_package.sv, rtl/mac_fsm.sv, rtl/mac_ctrl.sv, rtl/mac_streamer.sv, rtl/mac_engine.sv, rtl/mac_top.sv, rtl/aes_1cc.v, rtl/AddRoundKey.v, rtl/KeyExpansion.v, rtl/MixColumns.v, rtl/ShiftRows.v, rtl/SubBytes.v, r...
<reponame>mfkiwl/garnet name: e2e_testbench commands: - bash gen_testbench.sh # Script extract noteworthy tiles outputs: - testbench.sv - input.raw - tiles_Tile_MemCore.list - tiles_Tile_PE.list - cmd.tcl parameters: array_width: 12 array_height: 12 pipeline_config_interval: 8 interconnect_only...
name: Manylinux on: push: tags: - 'v..*' jobs: deploy: strategy: matrix: os: [ubuntu-latest] python-version: [3.7, 3.8] rust-version: [stable] runs-on: ${{ matrix.os }} steps: - name: Checkout uses: actions/checkout@v2 - name: Set up Python ${{...
<filename>tests/config/delta_mark_classification.yml<gh_stars>0 # supported task types are 'classification', 'object_detection' and 'semantic_segmentation'. task_type: classification network_name: LmnetV1Quantize dataset: format: DeLTA-Mark for Classification train_path: ./lmnet/tests/fixtures/datasets/custom_del...
<filename>examples/afe/source.yaml verilog_sources: sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" ams_models: files: - "build/channel/channel.sv" - "build/ctle1/ctle1.sv" - "build/ctle2/ctle2.sv" - "build/ctle3/ctle3.sv" - "build/nonlin/nonlin.sv" - "build/unfm/unfm.s...
name: sasc_top clock_port: clk verilog: - sasc_brg.v - sasc_fifo4.v - sasc_top.v - timescale.v
version: 1.0.{build} image: Visual Studio 2017 shallow_clone: true configuration: Release platform: x64 install: - cmd: echo "Downloading conan..." - cmd: set PATH=%PATH%;%PYTHON%/Scripts/ - cmd: pip.exe install conan - cmd: conan user # Create the conan data directory - cmd: conan --version - cmd: mkdir...
# Human readable task name name: Comlink # Long form description. description: \|+ We have captured a spy. They were carrying this device with them. See the README for more details. # The flag flag: CTF{HAVE_YOU_EVER_SEEN_A_Z80_CPU_WITH_AN_AES_PERIPHERAL} # Task category. (one of hardware, crypto, pwn, reversing, web,...
run_sim_udp:vivado2019.2:questasim2019.2: extends: .template_base image: ${IPBUS_DOCKER_REGISTRY}/ipbus-fw-dev-centos7:2021-06-21__ipbbdev-2021i_uhal2.8.0 tags: - docker - docker-cap-net-admin - docker-device-net-tun - xilinx-tools stage: quick_checks only: - /^pull-requests.[0-9]+$/ - ma...
<filename>libs/EXTERNAL/libargparse/.travis.yml language: cpp dist: trusty #Ubuntu 14.04 by default sudo: false #Use container based infrastructure matrix: include: #Extensive testing for base compiler - env: MATRIX_EVAL="CC=gcc-5 CXX=g++-5" addons: { apt: { packages: ["cmake", "g++-5"], ...
<reponame>b1f6c1c4/fpnew # Copyright 2019 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: FPnew authors: ["<NAME> <<EMAIL>>"] dependencies: common_cells: {git: "https://github.com/pulp-platform/common_ce...
<reponame>diorga/snitch package: name: lowrisc_rv_plic description: "lowRISC RISC-V Platform Level Interrupt Controller" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: - rtl/rv_plic_gateway.sv - rtl/rv_plic_target.sv
udma_core: files: [ rtl/core/udma_ch_addrgen.sv, rtl/core/udma_filter_au.sv, rtl/core/udma_filter_bincu.sv, rtl/core/udma_filter_rx_dataout.sv, rtl/core/udma_filter.sv, rtl/core/udma_filter_tx_datafetch.sv, rtl/core/udma_arbiter.sv, rtl/core/udma_core.sv, rtl/core/udma_rx_channels....
<reponame>gokhankici/iodine name: iodine version: 0.1.0.0 github: "gokhankici/iodine" license: MIT author: "<NAME>" maintainer: "<EMAIL>" copyright: "2018 <NAME>" extra-source-files: - README.md - ChangeLog.md synopsis: Gen...
<reponame>mikey/microwatt<filename>.travis.yml # global options dist: xenial os: linux language: shell services: docker before_install: docker pull ghdl/vunit:llvm env: matrix: - TASK="tests_unit" - TASK="tests_console" - TASK="; apt update && apt install -y python3-pexpect && make -j$(nproc) test_micr...
<reponame>StanfordVLSI/dragonphy2 # Adapted from Garnet and ButterPHY name: termination commands: - \| mkdir -p outputs tar -xvf /home/sjkim85/dragonphy_tarballs/termination-latest.tar.gz -C outputs mv outputs/termination-0.1.0/* outputs/ outputs: - termination.lef - termination.gds - termination.s...
common_cells_all: files: [ generic_fifo.sv, generic_LFSR_8bit.sv, onehot_to_bin.sv, rstgen.sv, edge_propagator_tx.sv, edge_propagator_rx.sv, edge_propagator.sv, pulp_sync_wedge.sv, pulp_sync.sv, clock_divider.sv, clock_divider_counter.sv, ]
<gh_stars>0 name: "sy_experiment_1" data: src: "de" trg: "en" train: "postediting/data/multi30k/train.lc.norm.tok" dev: "postediting/data/multi30k/dev_2017_flickr.lc.norm.tok" random_train_subset: 10000 level: "word" lowercase: False max_sent_length: 50 src_voc_min_freq: ...
<filename>ultra96/ROOT_FS/app/fad/data/OdometryCalculator/PatternMatchingVOCalculator/PatternMatcher/AKAZEPatternMatcher/param.yaml %YAML 1.2 --- AKAZE: # https://docs.opencv.org/3.4.2/d8/d30/classcv_1_1AKAZE.html descriptor_type: 5 # 2:DESCRIPTOR_KAZE_UPRIGHT, 3:DESCRIPTOR_KAZE, 4:DESCRIPTOR_...
<gh_stars>100-1000 pip_test: - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3 dst_wire: SLICE_X11Y69.SLICEL/D3 pip_chain_test: - wires: - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE - $CONSTANTS_X0Y0/$GND_NODE - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0 ...
<filename>.github/workflows/documentation.yml<gh_stars>0 name: Documentation on: push: branches: - develop pull_request: jobs: markdown-link-check: name: 'Check Markdown links' runs-on: ubuntu-latest steps: - uses: actions/checkout@master - uses: gaurav-nelson/github-action-markd...
<filename>ultra96/ROOT_FS/app/fad/data/OdometryCalculator/PatternMatchingVOCalculator/param.yaml %YAML 1.2 --- param: match_method: "TM" # "AKAZE", "TM" line_area_thr: 0.040 # 白線領域として許容する面積のしきい値(m^2) cutting_size_of_ref_map: 1.70 # マッチング処理において参照地図を切...
<reponame>AltisourceLabs/ecloudmanager<gh_stars>0 controllerPackage: org.ecloudmanager.rest modelPackage: org.ecloudmanager.node.model swaggerUrl: swagger.yaml environment: development entityProcessors: - json - xml - yaml
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
before_script: - export CXX=g++-7 CC=gcc-7 # paths to local or network installations (the riscv toolchain and # verilator are not built in the ci job as in travis) - export QUESTASIM_HOME= - export QUESTASIM_VERSION= - export QUESTASIM_FLAGS= - export RISCV=/scratch/$USER/projects/riscv_install - expor...
<reponame>icgrp/doblink # @package _global_ do_blink: backend: vivado figure: fig1 sub_figure: b device: 19eg part: xczu19eg-ffvb1517-2-e num_luts: 2400 bft: bft8 use_abs: True
name: Regression on: push: pull_request: schedule: - cron: 0 11 * * ? jobs: linux: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - name: Set up Python 3.7 uses: actions/setup-python@v1 with: python-version: 3.7 - name: Update pip ...
<filename>Bender.yml package: name: "ntx" version: "1.0.0" authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> sources: - src/ntx_tools_pkg.vhd - src/ntx_lzc.vhd - src/ntx_fifo_asic.vhd - src/ntx_fifo_asic_oregs.vhd - src/ntx_fifo_d1.vhd - src/ntx_fifo_d2.vhd - src/ntx_fifo.vhd - src/fp32_pkg....
dist: xenial language: minimal services: - docker before_install: - docker pull tilk/riscv-gnu-toolchain - docker run --name rv -t -d tilk/riscv-gnu-toolchain /bin/bash - docker exec rv apt-get update - docker exec rv apt-get install -y verilator g++ - docker cp . rv:/root/rv script: - do...
--- input_file : ../akane/02_word_package.akd output_file : 02_word_package.md image_url : "Fig.1 ワードの構成" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/35e6911d-d654-1426-bd0a-ba5bb52b2642.jpeg" "Fig.2 BITS Field" : "https://qiita-image-store.s3.ap...
name: Implementation on: push: pull_request: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: all-in-one: runs-on: ubuntu-latest name: '🛳️ All-in-one' steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '⚙️ Generate bitstream' uses: docker...
#this is a example of how ENC ip is used in our yaml PWM_CAPTURE: IP: __PWM_CAPTURE CMD: CAP pwm_input: PIN: A34 DIRECTION: in rs232_tx: PIN: A35 DIRECTION: OUT
on: [workflow_dispatch, push] name: 'Documentation' jobs: docs_test_job: timeout-minutes: 10 runs-on: ubuntu-latest name: 'Test documentation build' steps: - uses: actions/checkout@v2 - name: Install Dependencies run: \| sudo apt-get update sudo apt-get install...
- Global: Print : true - Library: Name : merge_sorter Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../../src/main/vhdl"] - Library: Name : pipework Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../....
# if trusty is not used compilation is killed (out or mem) sudo: required dist: trusty language: python git: depth: 1 cache: apt: true # clang is required because there is not enought ram for gcc compiler: gcc python: - "3.5" addons: apt: sources: - ubuntu-toolchain-r-test #- llvm-...
# To use: # # pre-commit run -a # # Or: # # pre-commit install # (runs every time you commit in git) # # To update this file: # # pre-commit autoupdate # # See https://github.com/pre-commit/pre-commit repos: # Standard hooks - repo: https://github.com/pre-commit/pre-commit-hooks rev: v3.2.0 hooks: -...
hosts: # All fields in a host object are optional! # Interfaces can be defined by connections from switches # The following is the simplest host: h1 : {} # Hosts can optionally define interfaces h2 : interfaces: - ip: 10.0.0.11/24 # _MUST_ put mac address in qu...
docs_list_title: documents docs: - title: User Manual url: ./pdf/RFSoC_2x2_UG.pdf - title: Board schematics url: ./pdf/HTG-ZRF2-XUP_REV_11_Schematic_20Jan21.pdf
dist: bionic language: C compiler: gcc git: depth: 1 before_install: - export INSTALL_DIR=~/symbiflow - SRC=https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/releases/download/v1.2.0/Symbiflow_v1.2.0.gz.run - RUNFILE=$(basename $SRC) - echo "retrive new file" - wget $SRC - echo 'y' \| bash $RU...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
dist: xenial language: cpp env: global: # versions - ARROW_VERSION=0.13.0 - AWS_FPGA_VERSION=1.4.8 - CAPI_SNAP_VERSION=1.5.1 - CAPI_PSLSE_VERSION=4.1 - PSLVER=8 - MDBOOK_VERSION=0.2.1 # fletcher - FLETCHER_CPP=0 - FLETCHER_ECHO=0 - FLETCHER_AWS=0 - FLETCHER_SNAP=0 ...
<gh_stars>0 language: c cache: apt: true os: - linux dist: trusty addons: apt: sources: - sourceline: ppa:saltmakrell/ppa packages: - make - iverilog - yosys env: - SYNTH_KW= - SYNTH_KW=synth_ before_script: - make --no-print-directory ${SYNTH_KW}build script: - make...
<filename>stack.yaml resolver: lts-6.18 packages: - '.' extra-deps: - netlist-0.3.1 - netlist-to-vhdl-0.3.2 - sized-types-0.5.1 flags: {} extra-package-dbs: []
package: name: scm sources: - src/latch_register_file_1r_1w.sv - src/latch_register_file_1r_1w_all.sv - src/latch_register_file_1r_1w_test_wrap.sv - src/latch_register_file_1r_1w_all_test_wrap.sv - src/ff_register_file_1r_1w.sv - src/ff_register_file_1r_1w_all.sv - src/ff_register_file_1r_1w_test_wrap....
public_folder: ./content upload_folder: ./content/uploads database_type: postgresql database_user: launchsip database_password: <PASSWORD> database_host: localhost database_path: launchsip
# Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: swerv description: Full swerv core test top_module: tb_top tags: swerv path: third...
<filename>src_files.yml riscv_regfile_rtl: targets: [ rtl, tsmc55, gf22, ] incdirs: [ ./rtl/include, ] files: [ ./rtl/register_file_test_wrap.sv, ./rtl/riscv_register_file.sv, ] riscv: vlog_opts: [ -L fpnew_lib, ] incdirs: [ ./rtl/include, ../../rtl/includes, ] ...
<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...
<filename>Verilog Source Code/FoldedRule90/SEFUAM_SRAM_Channel_Count_Experiment/hdc_sensor_fusion_sim.yml sim.inputs.top_module: "hdc_sensor_fusion" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "hdc_sensor_fusion_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/SEFUAM_SRAM_Channel_Count_Expe...
name: EggNetExtension on: [push] jobs: build: runs-on: ${{ matrix.os }} strategy: matrix: os: [ubuntu-latest, windows-latest, macOS-latest] # os: [ubuntu-latest, macOS-latest] python-version: [3.6, 3.7, 3.8] steps: - uses: actions/checkout@v1 - name: Set up Py...
udma_filter: files: [ rtl/udma_filter_au.sv, rtl/udma_filter_bincu.sv, rtl/udma_filter_rx_dataout.sv, rtl/udma_filter_tx_datafetch.sv, rtl/udma_filter_reg_if.sv, rtl/udma_filter.sv, ]
# # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # # Examples: # # or10n: # commit: tags/PULP3_final # domain: [cluster] # udma: # commit: 62b10440 # domain: [soc] # axi_slice: # commit: master # domain: [soc,cluster] # If a tag or commit is referenced, the ...
# Run the RISC-V compliance framework port to check current NEORV32 version name: 'RISC-V Compliance' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest name: '🐧 Ubuntu-Latest' steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '🔧 Setup Environ...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
name: "wmt_ende_best" data: src: "en" trg: "de" train: "test/data/en-de/train.tok.bpe" dev: "test/data/en-de/dev.tok.bpe" test: "test/data/en-de/test.tok.bpe" level: "bpe" lowercase: False max_sent_length: 100 src_voc_min_freq: 0 src_voc_limit: 100000 trg_voc_mi...
package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.1.1 } sources: - target: any(all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_sram), not(tech_c...
<reponame>teratide/tydi-json<filename>.github/workflows/test.yml name: Test on: push: branches: - master pull_request: jobs: vhdl: name: VHDL runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: true - uses: ghdl/setup-ghdl-ci@maste...
register_interface: vlog_opts: - -L common_cells_lib - -L axi_lib incdirs: - include - ../pulp_platform_axi/include - ../pulp_platform_common_cells/include files: # Level 0 - src/reg_intf.sv # Level 1 - src/apb_to_reg.sv - src/axi_to_reg.sv - src/periph_to_reg.sv -...
<filename>Bender.yml package: name: apb_fll_if dependencies: apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.1 } ## fll_behav: { git: "<EMAIL>:alsaqr-synthesis/fll_behav.git", version: 0.0.0 } sources: - src/fll_intf.sv - src/apb_to_fll.sv - target: test files: - test/apb_fll...
module_name: oscillator description: Interface for a generic oscillator. Note that there is an optional input, actl, which is a control input to adjust the output frequency of an oscillator. If this input exists, in either current or voltage domain, the test and the generated model will be checking Kvco, gain compress...
<reponame>honorpeter/fletcher image: docker:latest services: - docker:dind stages: - check - test - examples .env: &env GHDL_IMAGE: ghdl/ghdl GHDL_TAG: ubuntu18-llvm-5.0 variables: <<: *env .ghdl-check-job: &ghdl-check-job stage: check image: $GHDL_IMAGE:$GHDL_TAG script: - find hardware/vh...
<reponame>siracusa-soc/hwpe-ctrl<gh_stars>1-10 package: name: hwpe-ctrl authors: - "<NAME> <<EMAIL>>" dependencies: tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 } sources: - include_dirs: - rtl files: # Source files grouped in levels...
<filename>public/cloc-1.82/tests/outputs/issues/114/T1.yaml --- # github.com/AlDanial/cloc header : cloc_url : github.com/AlDanial/cloc cloc_version : 1.70 elapsed_seconds : 0.0196640491485596 n_files : 3 n_lines : 3 files_per_second : 152.56267807995 lines_per_...
<filename>.github/workflows/generate-riscv.yml name: Generate Riscv using VexRiscv, archive on: workflow_dispatch: push: branches: [ trunk ] # Publish semver tags as releases. tags: [ 'v..*' ] jobs: generate-riscv: name: Generate Riscv runs-on: ubuntu-latest container: image: ghcr...
steps: - command: \| # tool setup source /cad/modules/tcl/init/bash module load base vcs xcelium/19.03.003 hspice spectre/18.10.314 verdi # create virtual environment python3.7 -m venv venv source venv/bin/activate # install python dependencies for testing pip install ...
package: name: udma_uart authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: udma_core: { git: "<EMAIL>:Alsaqr-platform/udma_core.git", version: 2.0.0 } common_cells: { git: "<EMAIL>:pulp-platform/common_cells.git"...
<filename>hw/vendor/pulp_platform_tech_cells_generic/Bender.yml package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.1.1 } sources: - target: any(all(rtl, simulatio...
apiVersion: grafana.f110.dev/v1alpha1 kind: GrafanaUser metadata: name: hoge namespace: grafana labels: instance: prod spec: email: <EMAIL> admin: true
# OpTiMSoC requires Ubuntu 16.04 # Travis supports this OS only in a docker environment # See Dockerfile for the full build instructions sudo: required language: cpp services: - docker script: - docker build .
<reponame>pan185/UnarySim<gh_stars>1-10 # This file defines single architecture set for tlut systolic array performance projection - proj_16_16_bank8_block16 - proj_32_32_bank8_block16 - proj_64_64_bank8_block16 - proj_128_128_bank8_block16
<gh_stars>100-1000 package: name: axi_node description: "An efficient AXI4 interconnect" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.10.0 } axi: { git: "https://github.com/pulp-platform/axi.git", rev: 3330f59b8668d8913e9835ba6b58d09536d2f209 } sources: ...
<gh_stars>1-10 # Copyright 2022 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed t...
--- title: Understanding the Instruction Set author: - Felix "xq" Queißner date: April 28, 2020 abstract: \| The SPU Mark II uses quite unique instruction set following a highly orthogonal programming style. In contrast to most cpus on the market, the SPU Mark II is a stack machine. This means that all operations ...
language: c matrix: include: - os: linux compiler: gcc cache: apt dist: xenial - os: osx compiler: clang osx_image: xcode10.2 # workaround for https://travis-ci.community/t/xcode-8-3-homebrew-outdated-error/3798 env: global: - SHORT_COMMIT_HASH=`git rev-parse --sho...
<reponame>bluetiger9/Vitis-AI name: vitis-ai-optimizer_caffe channels: - conda-forge - defaults dependencies: - python=3.7 - vai_optimizer_caffe_gpu
<reponame>jvanstraten/vhdmmio metadata: name: basic fields: - address: 0 name: ctrl behavior: control - address: 4 name: stat behavior: status - address: 0x1--- name: slv_a behavior: axi
# This is a sample build configuration for Python. # Check our guides at https://confluence.atlassian.com/x/x4UWN for more examples. # Only use spaces to indent your .yml configuration. # ----- # You can specify a custom docker image from Docker Hub as your build environment. image: sagemath/sagemath pipelines: defa...
before_install: - sudo add-apt-repository ppa:saltmakrell/ppa -y - sudo apt-get update - sudo apt-get install -y yosys language: node_js node_js: - "8"
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
label-alias: bug: 'Type: Bug' feature_request: 'Type: Feature Request' question: 'Type: Question'
dist: xenial language: python python: - "3.6" sudo: required cache: directories: - ${TRAVIS_BUILD_DIR}/pycoreir - ${TRAVIS_BUILD_DIR}/pysmt - ${TRAVIS_BUILD_DIR}/coreir - /home/travis/.smt_solvers/python-bindings-3.6 addons: apt: update: true sources: - ubuntu-toolchain-r-test packages:...
language: ruby bundler_args: --without development rvm: - 1.9.3 - 2.0.0 gemfile: - tests/Gemfile branches: only: - master - 2.x script: cd tests; bundle exec rake
<gh_stars>100-1000 axi_slice: files: [ src/axi_single_slice.sv, src/axi_ar_buffer.sv, src/axi_aw_buffer.sv, src/axi_b_buffer.sv, src/axi_r_buffer.sv, src/axi_slice.sv, src/axi_w_buffer.sv, src/axi_slice_wrap.sv, ]
<gh_stars>100-1000 # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agre...
<filename>.github/workflows/unittest.yml # ************************************************************************ # @author: <NAME> # @copyright: Copyright 2021 # @credits: AKAE # # @license: BSDv3 # @maintainer: <NAME> # @email: <EMAIL> # # @file: unittest.yml # @date: 2021-08-25 ...

<reponame>martinda/hdlConvertor<filename>.travis.yml sudo: required dist: xenial language: python git: depth: 1 cache: - apt: true - pip : true matrix: include: - name: "Python 2.7 gcc-8" python: 2.7 env: CC=gcc-8 CXX=g++-8 addons: apt: sources: ...

<gh_stars>100-1000 # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: tcdm_interface authors: - <NAME> <<EMAIL>> dependencies: reqrsp_interface: {path: ../reqrsp_interface} export_includ...

<filename>env/azure_pipeline.yaml # Triggers are currently handled by branch policy for build validation in azure devops trigger: none # trigger: # batch: true # branches: # include: # - master stages: - stage: 'all' jobs: - job: 'CI_no_license' pool: name: CI_no_license ste...

<filename>.github/workflows/test.yml<gh_stars>10-100 name: Test on: push: pull_request: jobs: action: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Run VUnit tests uses: ./ with: cmd: test/run.py container-job: runs-on: ubuntu-latest contain...

version: 1 formatters: colored: format: '[%(asctime)s] (%(color)s%(slvl)s%(crst)s) %(name)-6s %(msgcolor)s%(message)s%(crst)s' nocolor: format: '[%(asctime)s] (%(slvl)s) %(name)-6s %(message)s' handlers: console: class: logging.StreamHandler level: INFO formatter:...

<gh_stars>0 identifier: fwrisc_test name: fwrisc SoC type: mcu arch: riscv32 toolchain: - zephyr ram: 32 testing: ignore_tags: - net - bluetooth

<reponame>usmnzain/serv on: [push, pull_request] jobs: lint: runs-on: ubuntu-latest name: Linter steps: - name: Checkout uses: actions/checkout@v1 - name: Lint Verilog source files with Verilator uses: librecores/ci-fusesoc-action@main with: command: 'run' ...

name: ci on: [push] jobs: ################ # Verible Lint # ################ verilog: name: Verilog Sources # This job runs on Linux (fixed ubuntu version) runs-on: ubuntu-18.04 env: VERIBLE_VERSION: 0.0-807-g10e7c71 steps: - uses: actions/checkout@v2 - name: Install Verible ...

# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # rtl: path: .. tech_cells_generic: path: ../../tech_cells_generic

<filename>external/opensocdebug/software/shippable.yml<gh_stars>10-100 language: c compiler: - gcc env: global: # Codecov upload token: CODECOV_TOKEN=xxx # To decrypt/replace go to the Shippable UI into the project settings - secure: <KEY> matrix: # Configure options (resulting in one build job ...

# action.yml name: 'Hawkeye CLI Scanner' description: Runs the Hawkeye CLI scanner runs: using: 'docker' image: 'Dockerfile'

<reponame>mfkiwl/garnet<gh_stars>0 name: gen_sram_macro commands: - bash gen_srams.sh inputs: - adk outputs: - sram.v - sram-pwr.v - sram.lef - sram_tt.lib - sram_ff.lib - sram_tt.db # Need this back for power on ptpx - sram.gds - sram.spi parameters: num_words: 2048 word_size: 64 mux_siz...

package: name: apb_fll_if dependencies: apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.1.0 } sources: - src/fll_intf.sv - src/apb_fll_if.sv - src/apb_to_fll.sv - target: test files: - test/apb_fll_tb.sv

<reponame>DanielTRYTRYLOOK/RDF-2020 name: usbf_top clock_port: clk_i verilog: - usbf_crc16.v - usbf_crc5.v - usbf_defines.v - usbf_ep_rf.v - usbf_ep_rf_dummy.v - usbf_idma.v - usbf_mem_arb.v - usbf_pa.v - usbf_pd.v - usbf_pe.v - usbf_pl.v - usbf_rf.v - usbf_top.v ...

<filename>.landscape.yaml max-line-length: 300 ignore-paths: - pybar/utils - pybar/scans/deprecated ignore-patterns: - analyze_test_beam

hw-mac-engine: incdirs : [ rtl ] files : [ rtl/mac_package.sv, rtl/mac_fsm.sv, rtl/mac_ctrl.sv, rtl/mac_streamer.sv, rtl/mac_engine.sv, rtl/mac_top.sv, rtl/aes_1cc.v, rtl/AddRoundKey.v, rtl/KeyExpansion.v, rtl/MixColumns.v, rtl/ShiftRows.v, rtl/SubBytes.v, r...

<reponame>mfkiwl/garnet name: e2e_testbench commands: - bash gen_testbench.sh # Script extract noteworthy tiles outputs: - testbench.sv - input.raw - tiles_Tile_MemCore.list - tiles_Tile_PE.list - cmd.tcl parameters: array_width: 12 array_height: 12 pipeline_config_interval: 8 interconnect_only...

name: Manylinux on: push: tags: - 'v*.*.*' jobs: deploy: strategy: matrix: os: [ubuntu-latest] python-version: [3.7, 3.8] rust-version: [stable] runs-on: ${{ matrix.os }} steps: - name: Checkout uses: actions/checkout@v2 - name: Set up Python ${{...

<filename>tests/config/delta_mark_classification.yml<gh_stars>0 # supported task types are 'classification', 'object_detection' and 'semantic_segmentation'. task_type: classification network_name: LmnetV1Quantize dataset: format: DeLTA-Mark for Classification train_path: ./lmnet/tests/fixtures/datasets/custom_del...

<filename>examples/afe/source.yaml verilog_sources: sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" ams_models: files: - "build/channel/channel.sv" - "build/ctle1/ctle1.sv" - "build/ctle2/ctle2.sv" - "build/ctle3/ctle3.sv" - "build/nonlin/nonlin.sv" - "build/unfm/unfm.s...

name: sasc_top clock_port: clk verilog: - sasc_brg.v - sasc_fifo4.v - sasc_top.v - timescale.v

version: 1.0.{build} image: Visual Studio 2017 shallow_clone: true configuration: Release platform: x64 install: - cmd: echo "Downloading conan..." - cmd: set PATH=%PATH%;%PYTHON%/Scripts/ - cmd: pip.exe install conan - cmd: conan user # Create the conan data directory - cmd: conan --version - cmd: mkdir...

# Human readable task name name: Comlink # Long form description. description: |+ We have captured a spy. They were carrying this device with them. See the README for more details. # The flag flag: CTF{HAVE_YOU_EVER_SEEN_A_Z80_CPU_WITH_AN_AES_PERIPHERAL} # Task category. (one of hardware, crypto, pwn, reversing, web,...

run_sim_udp:vivado2019.2:questasim2019.2: extends: .template_base image: ${IPBUS_DOCKER_REGISTRY}/ipbus-fw-dev-centos7:2021-06-21__ipbbdev-2021i_uhal2.8.0 tags: - docker - docker-cap-net-admin - docker-device-net-tun - xilinx-tools stage: quick_checks only: - /^pull-requests.[0-9]+$/ - ma...

<filename>libs/EXTERNAL/libargparse/.travis.yml language: cpp dist: trusty #Ubuntu 14.04 by default sudo: false #Use container based infrastructure matrix: include: #Extensive testing for base compiler - env: MATRIX_EVAL="CC=gcc-5 CXX=g++-5" addons: { apt: { packages: ["cmake", "g++-5"], ...

<reponame>b1f6c1c4/fpnew # Copyright 2019 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: FPnew authors: ["<NAME> <<EMAIL>>"] dependencies: common_cells: {git: "https://github.com/pulp-platform/common_ce...

<reponame>diorga/snitch package: name: lowrisc_rv_plic description: "lowRISC RISC-V Platform Level Interrupt Controller" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: - rtl/rv_plic_gateway.sv - rtl/rv_plic_target.sv

udma_core: files: [ rtl/core/udma_ch_addrgen.sv, rtl/core/udma_filter_au.sv, rtl/core/udma_filter_bincu.sv, rtl/core/udma_filter_rx_dataout.sv, rtl/core/udma_filter.sv, rtl/core/udma_filter_tx_datafetch.sv, rtl/core/udma_arbiter.sv, rtl/core/udma_core.sv, rtl/core/udma_rx_channels....

<reponame>gokhankici/iodine name: iodine version: 0.1.0.0 github: "gokhankici/iodine" license: MIT author: "<NAME>" maintainer: "<EMAIL>" copyright: "2018 <NAME>" extra-source-files: - README.md - ChangeLog.md synopsis: Gen...

<reponame>mikey/microwatt<filename>.travis.yml # global options dist: xenial os: linux language: shell services: docker before_install: docker pull ghdl/vunit:llvm env: matrix: - TASK="tests_unit" - TASK="tests_console" - TASK="; apt update && apt install -y python3-pexpect && make -j$(nproc) test_micr...

<reponame>StanfordVLSI/dragonphy2 # Adapted from Garnet and ButterPHY name: termination commands: - | mkdir -p outputs tar -xvf /home/sjkim85/dragonphy_tarballs/termination-latest.tar.gz -C outputs mv outputs/termination-0.1.0/* outputs/ outputs: - termination.lef - termination.gds - termination.s...

common_cells_all: files: [ generic_fifo.sv, generic_LFSR_8bit.sv, onehot_to_bin.sv, rstgen.sv, edge_propagator_tx.sv, edge_propagator_rx.sv, edge_propagator.sv, pulp_sync_wedge.sv, pulp_sync.sv, clock_divider.sv, clock_divider_counter.sv, ]

<gh_stars>0 name: "sy_experiment_1" data: src: "de" trg: "en" train: "postediting/data/multi30k/train.lc.norm.tok" dev: "postediting/data/multi30k/dev_2017_flickr.lc.norm.tok" random_train_subset: 10000 level: "word" lowercase: False max_sent_length: 50 src_voc_min_freq: ...

<filename>ultra96/ROOT_FS/app/fad/data/OdometryCalculator/PatternMatchingVOCalculator/PatternMatcher/AKAZEPatternMatcher/param.yaml %YAML 1.2 --- AKAZE: # https://docs.opencv.org/3.4.2/d8/d30/classcv_1_1AKAZE.html descriptor_type: 5 # 2:DESCRIPTOR_KAZE_UPRIGHT, 3:DESCRIPTOR_KAZE, 4:DESCRIPTOR_...

<gh_stars>100-1000 pip_test: - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3 dst_wire: SLICE_X11Y69.SLICEL/D3 pip_chain_test: - wires: - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE - $CONSTANTS_X0Y0/$GND_NODE - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0 ...

<filename>.github/workflows/documentation.yml<gh_stars>0 name: Documentation on: push: branches: - develop pull_request: jobs: markdown-link-check: name: 'Check Markdown links' runs-on: ubuntu-latest steps: - uses: actions/checkout@master - uses: gaurav-nelson/github-action-markd...

<filename>ultra96/ROOT_FS/app/fad/data/OdometryCalculator/PatternMatchingVOCalculator/param.yaml %YAML 1.2 --- param: match_method: "TM" # "AKAZE", "TM" line_area_thr: 0.040 # 白線領域として許容する面積のしきい値(m^2) cutting_size_of_ref_map: 1.70 # マッチング処理において参照地図を切...

<reponame>AltisourceLabs/ecloudmanager<gh_stars>0 controllerPackage: org.ecloudmanager.rest modelPackage: org.ecloudmanager.node.model swaggerUrl: swagger.yaml environment: development entityProcessors: - json - xml - yaml

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

before_script: - export CXX=g++-7 CC=gcc-7 # paths to local or network installations (the riscv toolchain and # verilator are not built in the ci job as in travis) - export QUESTASIM_HOME= - export QUESTASIM_VERSION= - export QUESTASIM_FLAGS= - export RISCV=/scratch/$USER/projects/riscv_install - expor...

<reponame>icgrp/doblink # @package _global_ do_blink: backend: vivado figure: fig1 sub_figure: b device: 19eg part: xczu19eg-ffvb1517-2-e num_luts: 2400 bft: bft8 use_abs: True

name: Regression on: push: pull_request: schedule: - cron: 0 11 * * ? jobs: linux: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - name: Set up Python 3.7 uses: actions/setup-python@v1 with: python-version: 3.7 - name: Update pip ...

<filename>Bender.yml package: name: "ntx" version: "1.0.0" authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> sources: - src/ntx_tools_pkg.vhd - src/ntx_lzc.vhd - src/ntx_fifo_asic.vhd - src/ntx_fifo_asic_oregs.vhd - src/ntx_fifo_d1.vhd - src/ntx_fifo_d2.vhd - src/ntx_fifo.vhd - src/fp32_pkg....

dist: xenial language: minimal services: - docker before_install: - docker pull tilk/riscv-gnu-toolchain - docker run --name rv -t -d tilk/riscv-gnu-toolchain /bin/bash - docker exec rv apt-get update - docker exec rv apt-get install -y verilator g++ - docker cp . rv:/root/rv script: - do...

--- input_file : ../akane/02_word_package.akd output_file : 02_word_package.md image_url : "Fig.1 ワードの構成" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/35e6911d-d654-1426-bd0a-ba5bb52b2642.jpeg" "Fig.2 BITS Field" : "https://qiita-image-store.s3.ap...

name: Implementation on: push: pull_request: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: all-in-one: runs-on: ubuntu-latest name: '🛳️ All-in-one' steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '⚙️ Generate bitstream' uses: docker...

#this is a example of how ENC ip is used in our yaml PWM_CAPTURE: IP: __PWM_CAPTURE CMD: CAP pwm_input: PIN: A34 DIRECTION: in rs232_tx: PIN: A35 DIRECTION: OUT

on: [workflow_dispatch, push] name: 'Documentation' jobs: docs_test_job: timeout-minutes: 10 runs-on: ubuntu-latest name: 'Test documentation build' steps: - uses: actions/checkout@v2 - name: Install Dependencies run: | sudo apt-get update sudo apt-get install...

- Global: Print : true - Library: Name : merge_sorter Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../../src/main/vhdl"] - Library: Name : pipework Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../....

# if trusty is not used compilation is killed (out or mem) sudo: required dist: trusty language: python git: depth: 1 cache: apt: true # clang is required because there is not enought ram for gcc compiler: gcc python: - "3.5" addons: apt: sources: - ubuntu-toolchain-r-test #- llvm-...

# To use: # # pre-commit run -a # # Or: # # pre-commit install # (runs every time you commit in git) # # To update this file: # # pre-commit autoupdate # # See https://github.com/pre-commit/pre-commit repos: # Standard hooks - repo: https://github.com/pre-commit/pre-commit-hooks rev: v3.2.0 hooks: -...

hosts: # All fields in a host object are optional! # Interfaces can be defined by connections from switches # The following is the simplest host: h1 : {} # Hosts can optionally define interfaces h2 : interfaces: - ip: 10.0.0.11/24 # _MUST_ put mac address in qu...

docs_list_title: documents docs: - title: User Manual url: ./pdf/RFSoC_2x2_UG.pdf - title: Board schematics url: ./pdf/HTG-ZRF2-XUP_REV_11_Schematic_20Jan21.pdf

dist: bionic language: C compiler: gcc git: depth: 1 before_install: - export INSTALL_DIR=~/symbiflow - SRC=https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/releases/download/v1.2.0/Symbiflow_v1.2.0.gz.run - RUNFILE=$(basename $SRC) - echo "retrive new file" - wget $SRC - echo 'y' | bash $RU...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

dist: xenial language: cpp env: global: # versions - ARROW_VERSION=0.13.0 - AWS_FPGA_VERSION=1.4.8 - CAPI_SNAP_VERSION=1.5.1 - CAPI_PSLSE_VERSION=4.1 - PSLVER=8 - MDBOOK_VERSION=0.2.1 # fletcher - FLETCHER_CPP=0 - FLETCHER_ECHO=0 - FLETCHER_AWS=0 - FLETCHER_SNAP=0 ...

<gh_stars>0 language: c cache: apt: true os: - linux dist: trusty addons: apt: sources: - sourceline: ppa:saltmakrell/ppa packages: - make - iverilog - yosys env: - SYNTH_KW= - SYNTH_KW=synth_ before_script: - make --no-print-directory ${SYNTH_KW}build script: - make...

<filename>stack.yaml resolver: lts-6.18 packages: - '.' extra-deps: - netlist-0.3.1 - netlist-to-vhdl-0.3.2 - sized-types-0.5.1 flags: {} extra-package-dbs: []

package: name: scm sources: - src/latch_register_file_1r_1w.sv - src/latch_register_file_1r_1w_all.sv - src/latch_register_file_1r_1w_test_wrap.sv - src/latch_register_file_1r_1w_all_test_wrap.sv - src/ff_register_file_1r_1w.sv - src/ff_register_file_1r_1w_all.sv - src/ff_register_file_1r_1w_test_wrap....

public_folder: ./content upload_folder: ./content/uploads database_type: postgresql database_user: launchsip database_password: <PASSWORD> database_host: localhost database_path: launchsip

# Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: swerv description: Full swerv core test top_module: tb_top tags: swerv path: third...

<filename>src_files.yml riscv_regfile_rtl: targets: [ rtl, tsmc55, gf22, ] incdirs: [ ./rtl/include, ] files: [ ./rtl/register_file_test_wrap.sv, ./rtl/riscv_register_file.sv, ] riscv: vlog_opts: [ -L fpnew_lib, ] incdirs: [ ./rtl/include, ../../rtl/includes, ] ...

<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...

<filename>Verilog Source Code/FoldedRule90/SEFUAM_SRAM_Channel_Count_Experiment/hdc_sensor_fusion_sim.yml sim.inputs.top_module: "hdc_sensor_fusion" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "hdc_sensor_fusion_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/SEFUAM_SRAM_Channel_Count_Expe...

name: EggNetExtension on: [push] jobs: build: runs-on: ${{ matrix.os }} strategy: matrix: os: [ubuntu-latest, windows-latest, macOS-latest] # os: [ubuntu-latest, macOS-latest] python-version: [3.6, 3.7, 3.8] steps: - uses: actions/checkout@v1 - name: Set up Py...

udma_filter: files: [ rtl/udma_filter_au.sv, rtl/udma_filter_bincu.sv, rtl/udma_filter_rx_dataout.sv, rtl/udma_filter_tx_datafetch.sv, rtl/udma_filter_reg_if.sv, rtl/udma_filter.sv, ]

# # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # # Examples: # # or10n: # commit: tags/PULP3_final # domain: [cluster] # udma: # commit: 62b10440 # domain: [soc] # axi_slice: # commit: master # domain: [soc,cluster] # If a *tag* or *commit* is referenced, the ...

# Run the RISC-V compliance framework port to check current NEORV32 version name: 'RISC-V Compliance' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest name: '🐧 Ubuntu-Latest' steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '🔧 Setup Environ...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

name: "wmt_ende_best" data: src: "en" trg: "de" train: "test/data/en-de/train.tok.bpe" dev: "test/data/en-de/dev.tok.bpe" test: "test/data/en-de/test.tok.bpe" level: "bpe" lowercase: False max_sent_length: 100 src_voc_min_freq: 0 src_voc_limit: 100000 trg_voc_mi...

package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.1.1 } sources: - target: any(all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_sram), not(tech_c...

<reponame>teratide/tydi-json<filename>.github/workflows/test.yml name: Test on: push: branches: - master pull_request: jobs: vhdl: name: VHDL runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: true - uses: ghdl/setup-ghdl-ci@maste...

register_interface: vlog_opts: - -L common_cells_lib - -L axi_lib incdirs: - include - ../pulp_platform_axi/include - ../pulp_platform_common_cells/include files: # Level 0 - src/reg_intf.sv # Level 1 - src/apb_to_reg.sv - src/axi_to_reg.sv - src/periph_to_reg.sv -...

<filename>Bender.yml package: name: apb_fll_if dependencies: apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.1 } ## fll_behav: { git: "<EMAIL>:alsaqr-synthesis/fll_behav.git", version: 0.0.0 } sources: - src/fll_intf.sv - src/apb_to_fll.sv - target: test files: - test/apb_fll...

module_name: oscillator description: Interface for a generic oscillator. Note that there is an optional input, actl, which is a control input to adjust the output frequency of an oscillator. If this input exists, in either current or voltage domain, the test and the generated model will be checking Kvco, gain compress...

<reponame>honorpeter/fletcher image: docker:latest services: - docker:dind stages: - check - test - examples .env: &env GHDL_IMAGE: ghdl/ghdl GHDL_TAG: ubuntu18-llvm-5.0 variables: <<: *env .ghdl-check-job: &ghdl-check-job stage: check image: $GHDL_IMAGE:$GHDL_TAG script: - find hardware/vh...

<reponame>siracusa-soc/hwpe-ctrl<gh_stars>1-10 package: name: hwpe-ctrl authors: - "<NAME> <<EMAIL>>" dependencies: tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 } sources: - include_dirs: - rtl files: # Source files grouped in levels...

<filename>public/cloc-1.82/tests/outputs/issues/114/T1.yaml --- # github.com/AlDanial/cloc header : cloc_url : github.com/AlDanial/cloc cloc_version : 1.70 elapsed_seconds : 0.0196640491485596 n_files : 3 n_lines : 3 files_per_second : 152.56267807995 lines_per_...

<filename>.github/workflows/generate-riscv.yml name: Generate Riscv using VexRiscv, archive on: workflow_dispatch: push: branches: [ trunk ] # Publish semver tags as releases. tags: [ 'v*.*.*' ] jobs: generate-riscv: name: Generate Riscv runs-on: ubuntu-latest container: image: ghcr...

steps: - command: | # tool setup source /cad/modules/tcl/init/bash module load base vcs xcelium/19.03.003 hspice spectre/18.10.314 verdi # create virtual environment python3.7 -m venv venv source venv/bin/activate # install python dependencies for testing pip install ...

package: name: udma_uart authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: udma_core: { git: "<EMAIL>:Alsaqr-platform/udma_core.git", version: 2.0.0 } common_cells: { git: "<EMAIL>:pulp-platform/common_cells.git"...

<filename>hw/vendor/pulp_platform_tech_cells_generic/Bender.yml package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.1.1 } sources: - target: any(all(rtl, simulatio...

apiVersion: grafana.f110.dev/v1alpha1 kind: GrafanaUser metadata: name: hoge namespace: grafana labels: instance: prod spec: email: <EMAIL> admin: true

# OpTiMSoC requires Ubuntu 16.04 # Travis supports this OS only in a docker environment # See Dockerfile for the full build instructions sudo: required language: cpp services: - docker script: - docker build .

<reponame>pan185/UnarySim<gh_stars>1-10 # This file defines single architecture set for tlut systolic array performance projection - proj_16_16_bank8_block16 - proj_32_32_bank8_block16 - proj_64_64_bank8_block16 - proj_128_128_bank8_block16

<gh_stars>100-1000 package: name: axi_node description: "An efficient AXI4 interconnect" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.10.0 } axi: { git: "https://github.com/pulp-platform/axi.git", rev: 3330f59b8668d8913e9835ba6b58d09536d2f209 } sources: ...

<gh_stars>1-10 # Copyright 2022 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed t...

--- title: Understanding the Instruction Set author: - Felix "xq" Queißner date: April 28, 2020 abstract: | The SPU Mark II uses quite unique instruction set following a highly orthogonal programming style. In contrast to most cpus on the market, the SPU Mark II is a stack machine. This means that all operations ...

language: c matrix: include: - os: linux compiler: gcc cache: apt dist: xenial - os: osx compiler: clang osx_image: xcode10.2 # workaround for https://travis-ci.community/t/xcode-8-3-homebrew-outdated-error/3798 env: global: - SHORT_COMMIT_HASH=`git rev-parse --sho...

<reponame>bluetiger9/Vitis-AI name: vitis-ai-optimizer_caffe channels: - conda-forge - defaults dependencies: - python=3.7 - vai_optimizer_caffe_gpu

<reponame>jvanstraten/vhdmmio metadata: name: basic fields: - address: 0 name: ctrl behavior: control - address: 4 name: stat behavior: status - address: 0x1--- name: slv_a behavior: axi

# This is a sample build configuration for Python. # Check our guides at https://confluence.atlassian.com/x/x4UWN for more examples. # Only use spaces to indent your .yml configuration. # ----- # You can specify a custom docker image from Docker Hub as your build environment. image: sagemath/sagemath pipelines: defa...

before_install: - sudo add-apt-repository ppa:saltmakrell/ppa -y - sudo apt-get update - sudo apt-get install -y yosys language: node_js node_js: - "8"

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

label-alias: bug: 'Type: Bug' feature_request: 'Type: Feature Request' question: 'Type: Question'

dist: xenial language: python python: - "3.6" sudo: required cache: directories: - ${TRAVIS_BUILD_DIR}/pycoreir - ${TRAVIS_BUILD_DIR}/pysmt - ${TRAVIS_BUILD_DIR}/coreir - /home/travis/.smt_solvers/python-bindings-3.6 addons: apt: update: true sources: - ubuntu-toolchain-r-test packages:...

language: ruby bundler_args: --without development rvm: - 1.9.3 - 2.0.0 gemfile: - tests/Gemfile branches: only: - master - 2.x script: cd tests; bundle exec rake

<gh_stars>100-1000 axi_slice: files: [ src/axi_single_slice.sv, src/axi_ar_buffer.sv, src/axi_aw_buffer.sv, src/axi_b_buffer.sv, src/axi_r_buffer.sv, src/axi_slice.sv, src/axi_w_buffer.sv, src/axi_slice_wrap.sv, ]

<gh_stars>100-1000 # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agre...

<filename>.github/workflows/unittest.yml # ************************************************************************ # @author: <NAME> # @copyright: Copyright 2021 # @credits: AKAE # # @license: BSDv3 # @maintainer: <NAME> # @email: <EMAIL> # # @file: unittest.yml # @date: 2021-08-25 ...