KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

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sudo: required language: python python: - "3.6" addons: apt: update: true before_install: - pip install git+https://github.com/m-labs/nmigen - pip install codecov script: - coverage run -m unittest discover - codecov notifications: email: on_failure: never on_success: never
<filename>books/centaur/quicklisp/bundle/software/babel-20141217-git/.travis.yml language: lisp env: matrix: - LISP=abcl - LISP=allegro - LISP=sbcl - LISP=sbcl32 - LISP=ccl - LISP=ccl32 - LISP=clisp - LISP=clisp32 - LISP=cmucl - LISP=ecl matrix: allow_failures: - env: L...
<filename>.circleci/config.yml version: 2 jobs: build: docker: - image: jeffbush001/nyuzi-build steps: - checkout - run: name: Compile and Test command: scripts/run_ci_tests.sh
sudo: false language: scala scala: - 2.12.4 jdk: - oraclejdk8 branches: only: - master cache: directories: - $HOME/.ivy2 addons: postgresql: '9.5' addons: apt: packages: - language-pack-en - language-pack-sv addons: chrome: stable install: - wget -N http://chromedriver.stora...
# See https://pre-commit.com for more information # See https://pre-commit.com/hooks.html for more hooks default_install_hook_types: [pre-commit, commit-msg] repos: - repo: https://github.com/pre-commit/pre-commit-hooks rev: v3.2.0 hooks: - id: trailing-whitespace stages: [commit, manual ] -...
<reponame>cmarqu/pyVHDLParser language: python matrix: include: # Python 3.5 - env: CONFIG="Python3.5" os: linux sudo: false python: "3.5" install: - pip3 install -r .Travis-CI/requirements.txt before_script: - ./.PyPI/PyPI.setup.sh script: - python3 ./TestSuite.py deploy: skip_clean...
--- - name: Hello World hosts: localhost tasks: - name: Echo 'Hello World' debug: # Default msg parameter is 'Hello World!'
file_list: - impl1/source/top.vhd - ../../common/utility/source/blink.vhd - ../../common/utility/source/clk_div_n.vhd - ../../common/utility/source/edge_detect.vhd - ../../common/utility/source/pwm.vhd - ../../common/utility/source/sdm.vhd - ../../common/utility/source/quad_decoder.vhd - ../../common/utility/so...
<reponame>zld012739/zldrepository<gh_stars>0 #Descriptions: #CMD: cpld command #A: Assitant Board #T: Target Board #FUNC0: the function of this pin connection #DIRECTION: A2T T2A T2T #FRDM A-B-C-D DEFINITION #\| NAME \| SIZE \| CPLD_SCH \| FRDM_SCH #\| A \| (102) \| JJ_2 \| ? #\| B \| (82) \| JJ_1 \| ? #\| C...
resources: repositories: - repository: abs-tudelft type: github endpoint: github name: abs-tudelft/azure-pipelines-templates variables: arrowVersion: 0.16.0 ocaccelVersion: master ocseVersion: master jobs: - job: runtime pool: vmImage: ubuntu-latest steps: - checkout: self submodu...
python-targets: - 3 test-warnings: no strictness: medium max-line-length: 180 pylint: disable: - too-many-arguments pep8: disable: - E704 options: max-line-length: 180 mccabe: options: max-complexity: 20 ignore-paths: - docs - vhdl
<reponame>popas90/vhdl-parser<gh_stars>1-10 sudo: false language: python python: - "3.5" ##Install dependencies install: - pip install -r requirements.txt ##Run tests script: - ./setup.sh --local && ./build.sh --local && ./validate.sh notifications: email: on_success: never on_failure: never
--- category: - Recursion - Memoization - Classic CS problems and programs - Arithmetic - Simple note: Arithmetic operations
<reponame>parzival3/Surelog variables: VSIM: vsim-10.6b -64 VLIB: vlib-10.6b VLOG: vlog-10.6b -64 SYNOPSYS_DC: synopsys-2016.03 dc_shell -64bit before_script: - export PATH=~fschuiki/.cargo/bin:$PATH - mkdir -p build modelsim: script: - bender vsim - cd build - ../scripts/compile_vsim.sh ...
<reponame>Ameln93/cv32e40p<filename>src_files.yml cv32e40p_regfile_rtl: targets: [ rtl, tsmc55, gf22, ] incdirs: [ ./rtl/include, ] files: [ ./rtl/cv32e40p_register_file_test_wrap.sv, ./rtl/cv32e40p_register_file_latch.sv, ] riscv: vlog_opts: [ -L fpnew_lib, ] incdirs: [ ...
<reponame>Cloud-V/Fault<filename>.github/workflows/ci.yml on: push: tags: - "*" name: CI jobs: build_image: name: "Build" runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: fetch-depth: 0 - name: Get Tag if: ${{ github.event_name == 'push' && startsWi...
# Details: https://github.com/actions/labeler/blob/master/README.md host_net: - host/net/* host: - host/* monitor: - monitor/* board_fpga: - board/fpga/* board_soc: - board/soc/*
<reponame>Purdue-SoCET/RISCVBusiness # ISA Configurations isa_params: xlen : 32 # Microarchitectural Configurations microarch_params: # Branch/Jump Configurations br_predictor_type : "not_taken" # Cache configurations cache_config : "separate" dcache_type : "pass_through" icache_type : "pass_th...
#sudo: required language: bash git: depth: false quiet: true branches: only: - master services: - docker # maybe add a stage with a trivial test env: matrix: - BUILD_MODE=opt DOCKER=mascucsc/archlinux-masc DOCKER_LGRAPH_SRC=/root/livehd LGRAPH_COMPILER=g++ - BUILD_MODE=dbg DOCK...
machine: pre: - wget -O ghdl.deb https://github.com/tgingold/ghdl/releases/download/v0.33/ghdl_0.33-1ubuntu1_amd64.deb - sudo dpkg -i ghdl.deb \|\| true - sudo apt-get install -f test: override: - ghdl -i --work=LFSR src/LFSR/.vhd - ghdl -i --work=JUNIT_TB test/JUNIT_TB/....
on: [push, pull_request] name: CI jobs: lints: name: Lints runs-on: ubuntu-latest steps: - name: Checkout sources uses: actions/checkout@v2 - name: Install Rust toolchain uses: actions-rs/toolchain@v1 with: profile: minimal toolchain: stable ...
<filename>.github/workflows/python-app.yml<gh_stars>10-100 # This workflow will install Python dependencies, run tests and lint with a single version of Python # For more information see: https://help.github.com/actions/language-and-framework-guides/using-python-with-github-actions name: avr (single test) on: workf...
<reponame>slaclab/lcls-timing-core ############################################################################## ## This file is part of 'LCLS Timing Core'. ## It is subject to the license terms in the LICENSE.txt file found in the ## top-level directory of this distribution and at: ## https://confluence.slac.stanf...
# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: future dependencies: axi: {path: ../../vendor/pulp_platform_axi} common_cells: {path: ../../vendor/pulp_platform_common_cells} sources: #...
name: 'examples' on: push: jobs: examples: name: 'Running examples' runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: true fetch-depth: 0 - name: Pull container images run: \| docker pull hdlc/sim:osvb docker pull hdlc/ghdl:y...
name: coverage on: push: branches: - master jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Set up Python uses: actions/setup-python@v2 - name: Generate coverage report run: \| pip install pytest pip install cov...
module: test_fifo_singleclock_standard sources: - ../verilog/fifo_singleclock_standard.sv toplevel: fifo_singleclock_standard simulators: - vcs parameters: WIDTH: 16 DEPTH: 32
extends: default page: margin: [0.8in, 0.67in, 0.75in, 0.67in] link: font-color: #edac00 image: align: center caption: align: center running-content: start-at: toc header: height: 0.65in vertical-align: bottom image-vertical-align: bottom font-size: 11 border-color: #000000 border-width: 1 recto...
--- input_file : ../akane/04_sorting_network.akd output_file : 04_sorting_network.md image_url : "Fig.1 コンパレーター (昇順)" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/55ce3859-6d0e-7fa8-979b-d0a9a9d75e76.jpeg" "Fig.2 コンパレーター (降順)" : "htt...
<filename>fpga/style_rules.yaml rule: global: indentSize: 4 case: 'lower' library_003: disable: true # Allow doxygen comment before LIBRARY library_004: case: 'upper' # Upper-case LIBRARY keyword library_005: case: 'upper' # Upper-case USE keyword library_008: indentSize: 0 # ...
<gh_stars>1-10 # Ignore coverage for http.go and resolver.go which don't have tests. ignore: - "http.go" - "resolver.go"
<filename>.github/workflows/gh-pages.yml # Generate doxygen-based documentation and deploy it to neorv32 github-pages name: 'Deploy SW Framework Documentation to GitHub-Pages' on: push: branches: - master paths: - 'sw/' pull_request: branches: - master paths: - 'sw/' workflow...
<gh_stars>0 format_version: v1.0 type: UniqueComponent attributes: {id: spi1} children: - type: Symbols children: - type: Integer attributes: {id: SPI_BRG_VALUE} children: - type: Values children: - type: Dynamic attributes: {id: spi1, value: '23'} - type: KeyValueSet attribute...
module: test_noc_buffer sources: - ../verilog/noc_buffer.sv toplevel: noc_buffer simulators: - vcs parameters: FLIT_WIDTH: [8,32] DEPTH: [2,4,16] parameter_includes: - FLIT_WIDTH: 32 DEPTH: 8 # Test case to test the FULLPACKET feature. The test is hardcoded and only # works with these paramet...
language: c install: wget https://raw.githubusercontent.com/ocaml/ocaml-travisci-skeleton/master/.travis-opam.sh script: bash -ex .travis-opam.sh env: - PACKAGE="tls" OCAML_VERSION=4.01 EXTRA_REMOTES=https://github.com/mirage/mirage-dev.git PINS="nocrypto asn1-combinators x509" - PACKAGE="tls" OCAML_VERSION=latest ...
package: name: lowrisc_i2c description: "lowRISC I2C" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: - rtl/i2c_reg_pkg.sv - rtl/i2c_reg_top.sv - rtl/i2c_fsm.sv - rtl/i2c_core.sv - rtl/i2c.sv
--- name: loopback board: boards/alpha250 version: 0.2.0 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/edge_detector_v1_0 - fpga/cores/comparator_v1_0 - fpga/cores/unrandomizer_v1_0 - boards/alpha250/cores/precision_dac_v1_0 - boa...
title: R. Sameni Homepage author: Copyright 2020, <NAME> description: > # this means to ignore newlines until "show_excerpts:" www.sameni.info show_excerpts: false # set to true to show excerpts on the homepage # Minima date format # refer to https://shopify.github.io/liquid/filters/date/ if you want to customize t...
<filename>models/AI-Model-Zoo/model-list/cf_reid_market1501_160_80_0.95G_1.4/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache...
<reponame>scale-lab/PVTsensors # # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # # Examples: # # or10n: # commit: tags/PULP3_final # domain: [cluster] # udma: # commit: 62b10440 # domain: [soc] # axi_slice: # commit: master # domain: [soc,cluster]...
# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: system-occamy authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: # axi_riscv_atomics: {path: ../../vendor/pulp_platform_axi_...
module: test_scm sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../common/osd_scm.sv toplevel: osd_scm simulators: - vcs parameters: SYSTEM_VENDOR_ID: 1 SYSTEM_DEVICE_ID: 1 NUM_MOD: 1 MAX_PKT_LEN: 12
<filename>models/AI-Model-Zoo/model-list/pt_FairMOT_mixed_640_480_0.5_36G_2.0/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apach...
<gh_stars>1-10 hwpe-ctrl: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/hwpe_ctrl_package.sv, rtl/hwpe_ctrl_interfaces.sv, rtl/hwpe_ctrl_regfile.sv, rtl/hwpe_ctrl_regfile_latch.sv, rtl/hwpe_ctrl_regfile_latch_test_wrap.sv, rtl/hwpe_ctrl_slave.sv, rtl/hwpe_ctrl...
--- algorithm: class: ParetoGPSimplified population_size: 600 archive_size: 200 generations_per_cascade: 10 mutation_probability: 0.00 shorten_individual: true tournament_size: 10 init: method: ramped # grow or full or ramped sensible_depth: 7 termination: max_steps: 1000 on_i...
axi_slice_dc: files: [ src/axi_slice_dc_master.sv, src/axi_slice_dc_slave.sv, src/dc_data_buffer.sv, src/dc_full_detector.v, src/dc_synchronizer.v, src/dc_token_ring_fifo_din.v, src/dc_token_ring_fifo_dout.v, src/dc_token_ring.v, src/axi_slice_dc_master_wrap.sv, src/axi_slice_d...
<filename>firmware/releases.yaml GitBase: .. TopRoguePackage: lcls2_epix_hr_pcie RoguePackages: - submodules/axi-pcie-core/python - submodules/clink-gateway-fw-lib/python - submodules/l2si-core/python - submodules/lcls2-pgp-fw-lib/python - submodules/lcls-timing-core/python - submodules/surf/python - p...
<reponame>zephyr-cosim/zephyr-cosim {% set filename = "{{name}}_64.yaml" %} identifier: {{name}}_64 name: Native 64-bit POSIX port type: native arch: posix ram: 65536 flash: 65536 toolchain: - host - llvm supported: - eeprom - netif:eth - usb_device - adc
package: name: riscv dependencies: fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.4 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 } sou...
<filename>infrastructure/kctf/base/k8s/deployment/autoscaling.yaml apiVersion: "autoscaling/v1" kind: "HorizontalPodAutoscaler" metadata: name: "chal" spec: scaleTargetRef: kind: "Deployment" name: "chal" apiVersion: "apps/v1beta1" minReplicas: 1 maxReplicas: 1 targetCPUUtilizationPercentage: 50
<reponame>f110/wing apiVersion: harbor.f110.dev/v1alpha1 kind: HarborProject metadata: name: test spec: public: true
<reponame>SubjeBilisim/anasymod<gh_stars>10-100 analog_probes: v_in_probe: abspath: 'tb_i.v_in' range: 10.0 v_out_probe: abspath: 'tb_i.v_out' range: 10.0 analog_ctrl_inputs: v_in: abspath: 'tb_i.v_in' range: 10 init_value: 0.0 analog_ctrl_outputs: v_out: abspath:...
<filename>documentation/metadata/vchip.yaml --- title: Unnamed DMA Chip author: - Felix "xq" Queißner date: May 07, 2020 abstract: \| <p>The RAM Blitter is a DMA unit that is developed for general purpose DMA transfers, as well as framebuffer modifications. It supports basic linear memory transfers as well as rectan...
<gh_stars>10-100 # Device description for the Keithley 6517A Electrometer. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are implemented here. identifier : KEITHLEY INSTRUMENTS INC.,MODEL 6517A remote_enable : REN on : OUTP ON off : OUTP OFF #get_current : MEAS:CU...
<reponame>diorga/snitch<filename>hw/vendor/pulp_platform_common_cells/.travis.yml language: cpp cache: apt: true directories: $VERILATOR_ROOT timeout: 1000 env: global: - VERILATOR_ROOT="/home/travis/verilator-4.014/" # required packages to install addons: apt: sources: - ubuntu-toolch...
top: cover_percentage: 40.28 coverage: 29 size: 72 type: <class 'cocotb_coverage.coverage.CoverItem'> top.covercross: cover_percentage: 30.0 coverage: 3 size: 10 type: <class 'cocotb_coverage.coverage.CoverItem'> top.covercross.cr0: at_least: 1 bins:_hits: ((0, 5), 0): 1 ((0, 5), 1): 1 (...
# Private CI trigger. Used to run tooling that can't currently be shared # publicly. trigger: batch: true branches: include: - '' tags: include: - "" pr: branches: include: - '*' # The runner used for private CI enforces the use of the template below. All # build steps need to be pl...
site_name: Croyde RISC-V theme: readthedocs nav: - Home: index.md - Project Organisation: project-organisation.md - Requirements: functional-requirements.md - Instruction Listing: instruction-listing.md - Pipeline: pipeline.md - Core Complex: ccx.md - Memory Interfaces: memory-interface.md - Flow - Synt...
name: Bump version on: workflow_dispatch: schedule: - cron: '0 0 * * *' jobs: bump-version: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 with: fetch-depth: 0 - name: Take last commit id: log run: echo "::set-output nam...
<reponame>ChipFlow/mpw4<gh_stars>1-10 name: Flow CI test on: [push, pull_request] jobs: Build-yosys: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: recursive - name: Install run: \| sudo apt-get update sudo apt-get install git make cm...
<reponame>slaclab/epix-hr-10k-2m ePixHr10kT: enable: True ForceWrite: False InitAfterConfig: False EpixHR: enable: True TriggerRegisters: enable: True RunTriggerEnable: False RunTriggerDelay: 0 DaqTriggerEnable: False DaqTriggerDelay: 0 AutoRunEn: True AutoDaqEn...
<filename>.github/workflows/docker-rpm.yml name: Docker Build and Review RPM on: push: branches-ignore: - '**' paths: - opae.spec - scripts/docker_rpm.sh - .github/workflows/docker-rpm.yml jobs: build_docker_image: runs-on: ubuntu-latest steps: - uses: actions/checkout...
<filename>hw/vendor/pulp_platform_axi_riscv_atomics/src_files.yml axi_riscv_atomics: files: [ src/axi_res_tbl.sv, src/axi_riscv_amos_alu.sv, src/axi_riscv_amos.sv, src/axi_riscv_amos_wrap.sv, src/axi_riscv_lrsc.sv, src/axi_riscv_lrsc_wrap.sv, src/axi_riscv_atomics.sv, src/axi_riscv_ato...
<gh_stars>1-10 --- project: description: "RISC-V SoC." foundry: "SkyWater" git_url: "https://github.com/kasirgalabs/kasirga-k0.git" organization: "Kasirga Labs" organization_url: "http://www.kasirgalabs.com/" owner: "<NAME>" process: "SKY130" project_name: "Kasirga K0" project_id: "00000000" tags: ...
<gh_stars>10-100 site_name: Mill repo_url: https://github.com/CircuitCoder/mill repo_name: CircuitCoder/mill edit_uri: edit/master/doc/docs/ copyright: Copyright © Mill developers, released under CC BY-NC-SA 4.0 plugins: - search: - git-revision-date-localized: type: iso_datetime fallback_to_build_dat...
<filename>site/docs/cloudbuild-deploy-docs.yaml # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 steps: - name: 'gcr.io/active-premise-257318/builder' args: ['./util/build_docs.py'] - name: 'gcr.io/cloud-builders/gsutil...
<reponame>IanBoyanZhang/kratos name: Google Test on: [push] jobs: build: runs-on: ubuntu-latest if: "!contains(github.event.head_commit.message, 'skip ci')" steps: - uses: actions/checkout@v2 - name: Checkout submodules shell: bash run: \| auth_header="$(git config --local -...
<filename>modules/dem_uart/test/test_dem_uart_wb.manifest.yaml module: test_dem_uart_wb sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../../../blocks/regaccess/common/osd_regaccess_demux.sv - ../../../blocks/regaccess/common/osd_regaccess_layer.sv ...
<gh_stars>10-100 description: >- Final version of data and analysis scripts for sigcomm submission. Formatting and analysis differences in analysis.ipynb. Telemetry has also been disabled in the experiment as a whole. experiment: e2e repositories: P4Boosters: 317c7f28 TofinoP4Boosters: 1d83cb15853...
# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_ssr authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_cells} ...
<gh_stars>10-100 image: Visual Studio 2019 clone_depth: 1 platform: - Win32 configuration: - Release environment: matrix: - PYTHON: "36" - PYTHON: "37" - PYTHON: "38" - PYTHON: "39" # scripts that are called at very beginning, before repo cloning init: # if it's not tagged, only run py39 ...
defaults: - <EMAIL>: - "1600" - "3200" - "6400" - "12800" - <EMAIL>: - "7010" - "7020" - "at200" - <EMAIL>: - "data_1_4_1" - "data_1_4_2" - "data_in_redir" - "dotProduct_1" - "dotProduct_2" - "Sigmoid_axi" - <EMAIL>: - "update_knn1" - "update_knn2" ...
<filename>ci/vivado-checks.yml<gh_stars>0 quick_check:enclustra_ax3_pm3_a35__2018.3: extends: .template_vivado_quick_check variables: VIVADO_VERSION: "2018.3" PROJ: enclustra_ax3_pm3_a35 quick_check:enclustra_ax3_pm3_a35__2019.2: extends: .template_vivado_quick_check variables: VIVADO_VERSION: "201...
package: name: lowrisc_gpio description: "lowRISC GPIO" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: # Level 0 - rtl/gpio_reg_pkg.sv # Level 1 - rtl/gpio_reg_top.sv - rtl/gpio.sv
language: rust # cache: cargo rust: - stable - beta - nightly # minimum supported version - "1.43.0" jobs: allow_failures: - rust: nightly fast_finish: true before_script: - rustup component add rustfmt script: - "[ $TRAVIS_RUST_VERSION != stable ] \|\| cargo fmt -- --check" - cargo build - ca...
<reponame>SubjeBilisim/anasymod PROJECT: dt: 0.1e-6 board_name: PYNQ_Z1 plugins: ['msdsl'] emu_clk_freq: 10e6 FPGA_TARGET: fpga: tstop: 10e-6
# TODO: Extend this to add job(s) for simulations, can be run in parallel with risc-v formal. dist: focal sudo: false language: generic cache: directories: - /home/travis/build/$TRAVIS_PULL_REQUEST_SLUG/formal/env - /home/travis/build/$TRAVIS_REPO_SLUG/formal/env before_install: install: # If env is no...
apiVersion: kctf.dev/v1 kind: Challenge metadata: name: xss-bot spec: deployed: true powDifficultySeconds: 0 network: public: false healthcheck: # TIP: disable the healthcheck during development enabled: true # You can allow the bot to connect to other challenges internally. # This can be usef...
<reponame>e7p/hal pull_request_rules: - name: automatic merge on CI success and review conditions: - status-success=ci/gitlab/gitlab.com - "#approved-reviews-by>=1" - base=master - label!="work in progress" actions: merge: method: merge - name: Delete branch after merge...
name: aes clock_port: clk verilog: - aes.v - byte_mixcolum.v - keysched.v - mixcolum.v - sbox.v - subbytes.v - timescale.v - word_mixcolum.v
<reponame>inmcm/Simon_Speck_Ciphers language: python python: - "2.6" - "2.7" - "3.5" - "3.6" - "3.7-dev" branches: only: - master - inmcm/python_packaging before_install: - cd Python/simonspeckciphers/ - pip install setuptools_scm # required for py2.6 install: - python setup.py install scri...
<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...
name: CI/VHDLTest on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: act...
site_name: PsPIN repo_url: https://github.com/spcl/pspin theme: name: material nav: - Home: 'index.md' - Getting started: - Docker image: 'docker.md' - Manual installation: 'compile.md' - Running examples: 'examples.md' - Testing your own handlers: - Minimal handler: ...
<reponame>hito0512/Vitis-AI # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable ...
<filename>modules/wb_leds/data/wb_leds_csr.yml memory-map: bus: wb-32-be name: wb_leds_csr description: LEDs Register Bank children: - reg: name: leds width: 32 access: rw type: unsigned
# Technology Setup is done in hammer-tstech28-plugin/bwrc.yml. vlsi.core.max_threads: 24 # File inputs synthesis.inputs: input_files: [ "src/HDC_Sensor_Fusion_FoldedRule90/hdc_sensor_fusion.sv", "src/HDC_Sensor_Fusion_FoldedRule90/associative_memory.sv", "src/HDC_Senso...
<reponame>mfkiwl/neorv32 # Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version name: 'riscv-arch-test' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest strategy: fail-fast: false matrix: suite: - I - C - M - pr...
"top": arch: "artix7_200t" device_family: "xc7a200t" device_name: "doblink-6-overlay" device_speed: "sbg484-1" device: "xc7a200t-doblink-6-overlay-virt" board: "nexys_video" use_roi: "FALSE" timeout: 1600
# -- yaml -- modulename: path/off/SRC_BASE_DIR/modulev1.sv # Empty assignment means leave module out of project bad_mod: # Include other yaml files include: - chip/a10_substitutions.yml - chip/s10_substitutions.yml
name: sv-test-env channels: - LiteX-Hub - pkgw-forge - conda-forge dependencies: # - LiteX-Hub::iverilog # - LiteX-Hub::moore # - LiteX-Hub::odin_ii # - LiteX-Hub::slang # - LiteX-Hub::surelog # - LiteX-Hub::sv-parser # - LiteX-Hub::tree-sitter-verilog # - LiteX-Hub::uhdm-integration-verilator # - LiteX-...
name: vitis-ai-optimizer_darknet channels: - conda-forge - defaults dependencies: - python=3.6 - vai_optimizer_darknet_gpu
<reponame>Laegluin/mikrorechner<filename>.travis.yml language: rust matrix: include: - os: windows rust: stable env: - DEPLOY=1 - os: windows rust: beta - os: windows rust: nightly - os: linux rust: stable env: - DEPLOY=1 - os: linux r...
<reponame>mfkiwl/snitch axi/axi: commit: v0.29.1 domain: [cluster, soc] common_cells: commit: v1.21.0 domain: [cluster, soc]
name: "Direct Push Warning" on: push: branches: - master - release-** jobs: build: runs-on: ubuntu-latest if: github.repository_owner == 'NixOS' env: GITHUB_SHA: ${{ github.sha }} GITHUB_REPOSITORY: ${{ github.repository }} steps: - name: Check if commit is a merge comm...
<filename>src_files.yml udma_external_per: files: [ rtl/udma_external_per_reg_if.sv, rtl/udma_traffic_gen_rx.sv, rtl/udma_traffic_gen_tx.sv, rtl/udma_external_per_top.sv, rtl/udma_external_per_wrapper.sv, ]
# Copyright 2021 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 cache_root_dir: /usr/scratch2/dolent1/gitlabci/buildcache/mempool artifacts: tc-riscv-gcc: inputs: - Makefile - toolchain/riscv-gnu-...
<filename>rtl/vendor/pulp_platform_register_interface/.github/workflows/lint.yml # Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run all lint checks name: lint on: [push, pull_request] jobs: ##...
apiVersion: "v1" kind: "Service" metadata: name: "xss-bot" namespace: "default" labels: app: "xss-bot" spec: type: "LoadBalancer" selector: app: "xss-bot" ports: - protocol: "TCP" port: 1 targetPort: 1337
<filename>.devcontainer/docker-compose.yml version: '3.7' services: metalfs-dev: image: metalfs/sdk-base:webpack init: true command: tail -f /dev/null working_dir: /workspace environment: - DISPLAY=$DISPLAY volumes: - /tmp/.X11-unix:/tmp/.X11-unix - ..:/workspace devices...

sudo: required language: python python: - "3.6" addons: apt: update: true before_install: - pip install git+https://github.com/m-labs/nmigen - pip install codecov script: - coverage run -m unittest discover - codecov notifications: email: on_failure: never on_success: never

<filename>books/centaur/quicklisp/bundle/software/babel-20141217-git/.travis.yml language: lisp env: matrix: - LISP=abcl - LISP=allegro - LISP=sbcl - LISP=sbcl32 - LISP=ccl - LISP=ccl32 - LISP=clisp - LISP=clisp32 - LISP=cmucl - LISP=ecl matrix: allow_failures: - env: L...

<filename>.circleci/config.yml version: 2 jobs: build: docker: - image: jeffbush001/nyuzi-build steps: - checkout - run: name: Compile and Test command: scripts/run_ci_tests.sh

sudo: false language: scala scala: - 2.12.4 jdk: - oraclejdk8 branches: only: - master cache: directories: - $HOME/.ivy2 addons: postgresql: '9.5' addons: apt: packages: - language-pack-en - language-pack-sv addons: chrome: stable install: - wget -N http://chromedriver.stora...

# See https://pre-commit.com for more information # See https://pre-commit.com/hooks.html for more hooks default_install_hook_types: [pre-commit, commit-msg] repos: - repo: https://github.com/pre-commit/pre-commit-hooks rev: v3.2.0 hooks: - id: trailing-whitespace stages: [commit, manual ] -...

<reponame>cmarqu/pyVHDLParser language: python matrix: include: # Python 3.5 - env: CONFIG="Python3.5" os: linux sudo: false python: "3.5" install: - pip3 install -r .Travis-CI/requirements.txt before_script: - ./.PyPI/PyPI.setup.sh script: - python3 ./TestSuite.py deploy: skip_clean...

--- - name: Hello World hosts: localhost tasks: - name: Echo 'Hello World' debug: # Default msg parameter is 'Hello World!'

file_list: - impl1/source/top.vhd - ../../common/utility/source/blink.vhd - ../../common/utility/source/clk_div_n.vhd - ../../common/utility/source/edge_detect.vhd - ../../common/utility/source/pwm.vhd - ../../common/utility/source/sdm.vhd - ../../common/utility/source/quad_decoder.vhd - ../../common/utility/so...

<reponame>zld012739/zldrepository<gh_stars>0 #Descriptions: #CMD: cpld command #A: Assitant Board #T: Target Board #FUNC0: the function of this pin connection #DIRECTION: A2T T2A T2T #FRDM A-B-C-D DEFINITION #| NAME | SIZE | CPLD_SCH | FRDM_SCH #| A | (10*2) | JJ_2 | ? #| B | (8*2) | JJ_1 | ? #| C...

resources: repositories: - repository: abs-tudelft type: github endpoint: github name: abs-tudelft/azure-pipelines-templates variables: arrowVersion: 0.16.0 ocaccelVersion: master ocseVersion: master jobs: - job: runtime pool: vmImage: ubuntu-latest steps: - checkout: self submodu...

python-targets: - 3 test-warnings: no strictness: medium max-line-length: 180 pylint: disable: - too-many-arguments pep8: disable: - E704 options: max-line-length: 180 mccabe: options: max-complexity: 20 ignore-paths: - docs - vhdl

<reponame>popas90/vhdl-parser<gh_stars>1-10 sudo: false language: python python: - "3.5" ##Install dependencies install: - pip install -r requirements.txt ##Run tests script: - ./setup.sh --local && ./build.sh --local && ./validate.sh notifications: email: on_success: never on_failure: never

--- category: - Recursion - Memoization - Classic CS problems and programs - Arithmetic - Simple note: Arithmetic operations

<reponame>parzival3/Surelog variables: VSIM: vsim-10.6b -64 VLIB: vlib-10.6b VLOG: vlog-10.6b -64 SYNOPSYS_DC: synopsys-2016.03 dc_shell -64bit before_script: - export PATH=~fschuiki/.cargo/bin:$PATH - mkdir -p build modelsim: script: - bender vsim - cd build - ../scripts/compile_vsim.sh ...

<reponame>Ameln93/cv32e40p<filename>src_files.yml cv32e40p_regfile_rtl: targets: [ rtl, tsmc55, gf22, ] incdirs: [ ./rtl/include, ] files: [ ./rtl/cv32e40p_register_file_test_wrap.sv, ./rtl/cv32e40p_register_file_latch.sv, ] riscv: vlog_opts: [ -L fpnew_lib, ] incdirs: [ ...

<reponame>Cloud-V/Fault<filename>.github/workflows/ci.yml on: push: tags: - "*" name: CI jobs: build_image: name: "Build" runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: fetch-depth: 0 - name: Get Tag if: ${{ github.event_name == 'push' && startsWi...

# Details: https://github.com/actions/labeler/blob/master/README.md host_net: - host/net/* host: - host/* monitor: - monitor/* board_fpga: - board/fpga/* board_soc: - board/soc/*

<reponame>Purdue-SoCET/RISCVBusiness # ISA Configurations isa_params: xlen : 32 # Microarchitectural Configurations microarch_params: # Branch/Jump Configurations br_predictor_type : "not_taken" # Cache configurations cache_config : "separate" dcache_type : "pass_through" icache_type : "pass_th...

#sudo: required language: bash git: depth: false quiet: true branches: only: - master services: - docker # maybe add a stage with a trivial test env: matrix: - BUILD_MODE=opt DOCKER=mascucsc/archlinux-masc DOCKER_LGRAPH_SRC=/root/livehd LGRAPH_COMPILER=g++ - BUILD_MODE=dbg DOCK...

machine: pre: - wget -O ghdl.deb https://github.com/tgingold/ghdl/releases/download/v0.33/ghdl_0.33-1ubuntu1_amd64.deb - sudo dpkg -i ghdl.deb || true - sudo apt-get install -f test: override: - ghdl -i --work=LFSR src/LFSR/*.vhd - ghdl -i --work=JUNIT_TB test/JUNIT_TB/*....

on: [push, pull_request] name: CI jobs: lints: name: Lints runs-on: ubuntu-latest steps: - name: Checkout sources uses: actions/checkout@v2 - name: Install Rust toolchain uses: actions-rs/toolchain@v1 with: profile: minimal toolchain: stable ...

<filename>.github/workflows/python-app.yml<gh_stars>10-100 # This workflow will install Python dependencies, run tests and lint with a single version of Python # For more information see: https://help.github.com/actions/language-and-framework-guides/using-python-with-github-actions name: avr (single test) on: workf...

<reponame>slaclab/lcls-timing-core ############################################################################## ## This file is part of 'LCLS Timing Core'. ## It is subject to the license terms in the LICENSE.txt file found in the ## top-level directory of this distribution and at: ## https://confluence.slac.stanf...

# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: future dependencies: axi: {path: ../../vendor/pulp_platform_axi} common_cells: {path: ../../vendor/pulp_platform_common_cells} sources: #...

name: 'examples' on: push: jobs: examples: name: 'Running examples' runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: true fetch-depth: 0 - name: Pull container images run: | docker pull hdlc/sim:osvb docker pull hdlc/ghdl:y...

name: coverage on: push: branches: - master jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Set up Python uses: actions/setup-python@v2 - name: Generate coverage report run: | pip install pytest pip install cov...

module: test_fifo_singleclock_standard sources: - ../verilog/fifo_singleclock_standard.sv toplevel: fifo_singleclock_standard simulators: - vcs parameters: WIDTH: 16 DEPTH: 32

extends: default page: margin: [0.8in, 0.67in, 0.75in, 0.67in] link: font-color: #edac00 image: align: center caption: align: center running-content: start-at: toc header: height: 0.65in vertical-align: bottom image-vertical-align: bottom font-size: 11 border-color: #000000 border-width: 1 recto...

--- input_file : ../akane/04_sorting_network.akd output_file : 04_sorting_network.md image_url : "Fig.1 コンパレーター (昇順)" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/55ce3859-6d0e-7fa8-979b-d0a9a9d75e76.jpeg" "Fig.2 コンパレーター (降順)" : "htt...

<filename>fpga/style_rules.yaml rule: global: indentSize: 4 case: 'lower' library_003: disable: true # Allow doxygen comment before LIBRARY library_004: case: 'upper' # Upper-case LIBRARY keyword library_005: case: 'upper' # Upper-case USE keyword library_008: indentSize: 0 # ...

<gh_stars>1-10 # Ignore coverage for http.go and resolver.go which don't have tests. ignore: - "http.go" - "resolver.go"

<filename>.github/workflows/gh-pages.yml # Generate doxygen-based documentation and deploy it to neorv32 github-pages name: 'Deploy SW Framework Documentation to GitHub-Pages' on: push: branches: - master paths: - 'sw/**' pull_request: branches: - master paths: - 'sw/**' workflow...

<gh_stars>0 format_version: v1.0 type: UniqueComponent attributes: {id: spi1} children: - type: Symbols children: - type: Integer attributes: {id: SPI_BRG_VALUE} children: - type: Values children: - type: Dynamic attributes: {id: spi1, value: '23'} - type: KeyValueSet attribute...

module: test_noc_buffer sources: - ../verilog/noc_buffer.sv toplevel: noc_buffer simulators: - vcs parameters: FLIT_WIDTH: [8,32] DEPTH: [2,4,16] parameter_includes: - FLIT_WIDTH: 32 DEPTH: 8 # Test case to test the FULLPACKET feature. The test is hardcoded and only # works with these paramet...

language: c install: wget https://raw.githubusercontent.com/ocaml/ocaml-travisci-skeleton/master/.travis-opam.sh script: bash -ex .travis-opam.sh env: - PACKAGE="tls" OCAML_VERSION=4.01 EXTRA_REMOTES=https://github.com/mirage/mirage-dev.git PINS="nocrypto asn1-combinators x509" - PACKAGE="tls" OCAML_VERSION=latest ...

package: name: lowrisc_i2c description: "lowRISC I2C" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: - rtl/i2c_reg_pkg.sv - rtl/i2c_reg_top.sv - rtl/i2c_fsm.sv - rtl/i2c_core.sv - rtl/i2c.sv

--- name: loopback board: boards/alpha250 version: 0.2.0 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/edge_detector_v1_0 - fpga/cores/comparator_v1_0 - fpga/cores/unrandomizer_v1_0 - boards/alpha250/cores/precision_dac_v1_0 - boa...

title: R. Sameni Homepage author: Copyright 2020, <NAME> description: > # this means to ignore newlines until "show_excerpts:" www.sameni.info show_excerpts: false # set to true to show excerpts on the homepage # Minima date format # refer to https://shopify.github.io/liquid/filters/date/ if you want to customize t...

<filename>models/AI-Model-Zoo/model-list/cf_reid_market1501_160_80_0.95G_1.4/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache...

<reponame>scale-lab/PVTsensors # # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # # Examples: # # or10n: # commit: tags/PULP3_final # domain: [cluster] # udma: # commit: 62b10440 # domain: [soc] # axi_slice: # commit: master # domain: [soc,cluster]...

# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: system-occamy authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: # axi_riscv_atomics: {path: ../../vendor/pulp_platform_axi_...

module: test_scm sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../common/osd_scm.sv toplevel: osd_scm simulators: - vcs parameters: SYSTEM_VENDOR_ID: 1 SYSTEM_DEVICE_ID: 1 NUM_MOD: 1 MAX_PKT_LEN: 12

<filename>models/AI-Model-Zoo/model-list/pt_FairMOT_mixed_640_480_0.5_36G_2.0/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apach...

<gh_stars>1-10 hwpe-ctrl: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/hwpe_ctrl_package.sv, rtl/hwpe_ctrl_interfaces.sv, rtl/hwpe_ctrl_regfile.sv, rtl/hwpe_ctrl_regfile_latch.sv, rtl/hwpe_ctrl_regfile_latch_test_wrap.sv, rtl/hwpe_ctrl_slave.sv, rtl/hwpe_ctrl...

--- algorithm: class: ParetoGPSimplified population_size: 600 archive_size: 200 generations_per_cascade: 10 mutation_probability: 0.00 shorten_individual: true tournament_size: 10 init: method: ramped # grow or full or ramped sensible_depth: 7 termination: max_steps: 1000 on_i...

axi_slice_dc: files: [ src/axi_slice_dc_master.sv, src/axi_slice_dc_slave.sv, src/dc_data_buffer.sv, src/dc_full_detector.v, src/dc_synchronizer.v, src/dc_token_ring_fifo_din.v, src/dc_token_ring_fifo_dout.v, src/dc_token_ring.v, src/axi_slice_dc_master_wrap.sv, src/axi_slice_d...

<filename>firmware/releases.yaml GitBase: .. TopRoguePackage: lcls2_epix_hr_pcie RoguePackages: - submodules/axi-pcie-core/python - submodules/clink-gateway-fw-lib/python - submodules/l2si-core/python - submodules/lcls2-pgp-fw-lib/python - submodules/lcls-timing-core/python - submodules/surf/python - p...

<reponame>zephyr-cosim/zephyr-cosim {% set filename = "{{name}}_64.yaml" %} identifier: {{name}}_64 name: Native 64-bit POSIX port type: native arch: posix ram: 65536 flash: 65536 toolchain: - host - llvm supported: - eeprom - netif:eth - usb_device - adc

package: name: riscv dependencies: fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.4 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 } sou...

<filename>infrastructure/kctf/base/k8s/deployment/autoscaling.yaml apiVersion: "autoscaling/v1" kind: "HorizontalPodAutoscaler" metadata: name: "chal" spec: scaleTargetRef: kind: "Deployment" name: "chal" apiVersion: "apps/v1beta1" minReplicas: 1 maxReplicas: 1 targetCPUUtilizationPercentage: 50

<reponame>f110/wing apiVersion: harbor.f110.dev/v1alpha1 kind: HarborProject metadata: name: test spec: public: true

<reponame>SubjeBilisim/anasymod<gh_stars>10-100 analog_probes: v_in_probe: abspath: 'tb_i.v_in' range: 10.0 v_out_probe: abspath: 'tb_i.v_out' range: 10.0 analog_ctrl_inputs: v_in: abspath: 'tb_i.v_in' range: 10 init_value: 0.0 analog_ctrl_outputs: v_out: abspath:...

<filename>documentation/metadata/vchip.yaml --- title: Unnamed DMA Chip author: - Felix "xq" Queißner date: May 07, 2020 abstract: | <p>The RAM Blitter is a DMA unit that is developed for general purpose DMA transfers, as well as framebuffer modifications. It supports basic linear memory transfers as well as rectan...

<gh_stars>10-100 # Device description for the Keithley 6517A Electrometer. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are implemented here. identifier : KEITHLEY INSTRUMENTS INC.,MODEL 6517A remote_enable : REN on : OUTP ON off : OUTP OFF #get_current : MEAS:CU...

<reponame>diorga/snitch<filename>hw/vendor/pulp_platform_common_cells/.travis.yml language: cpp cache: apt: true directories: $VERILATOR_ROOT timeout: 1000 env: global: - VERILATOR_ROOT="/home/travis/verilator-4.014/" # required packages to install addons: apt: sources: - ubuntu-toolch...

top: cover_percentage: 40.28 coverage: 29 size: 72 type: <class 'cocotb_coverage.coverage.CoverItem'> top.covercross: cover_percentage: 30.0 coverage: 3 size: 10 type: <class 'cocotb_coverage.coverage.CoverItem'> top.covercross.cr0: at_least: 1 bins:_hits: ((0, 5), 0): 1 ((0, 5), 1): 1 (...

# Private CI trigger. Used to run tooling that can't currently be shared # publicly. trigger: batch: true branches: include: - '*' tags: include: - "*" pr: branches: include: - '*' # The runner used for private CI enforces the use of the template below. All # build steps need to be pl...

site_name: Croyde RISC-V theme: readthedocs nav: - Home: index.md - Project Organisation: project-organisation.md - Requirements: functional-requirements.md - Instruction Listing: instruction-listing.md - Pipeline: pipeline.md - Core Complex: ccx.md - Memory Interfaces: memory-interface.md - Flow - Synt...

name: Bump version on: workflow_dispatch: schedule: - cron: '0 0 * * *' jobs: bump-version: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 with: fetch-depth: 0 - name: Take last commit id: log run: echo "::set-output nam...

<reponame>ChipFlow/mpw4<gh_stars>1-10 name: Flow CI test on: [push, pull_request] jobs: Build-yosys: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 with: submodules: recursive - name: Install run: | sudo apt-get update sudo apt-get install git make cm...

<reponame>slaclab/epix-hr-10k-2m ePixHr10kT: enable: True ForceWrite: False InitAfterConfig: False EpixHR: enable: True TriggerRegisters: enable: True RunTriggerEnable: False RunTriggerDelay: 0 DaqTriggerEnable: False DaqTriggerDelay: 0 AutoRunEn: True AutoDaqEn...

<filename>.github/workflows/docker-rpm.yml name: Docker Build and Review RPM on: push: branches-ignore: - '**' paths: - opae.spec - scripts/docker_rpm.sh - .github/workflows/docker-rpm.yml jobs: build_docker_image: runs-on: ubuntu-latest steps: - uses: actions/checkout...

<filename>hw/vendor/pulp_platform_axi_riscv_atomics/src_files.yml axi_riscv_atomics: files: [ src/axi_res_tbl.sv, src/axi_riscv_amos_alu.sv, src/axi_riscv_amos.sv, src/axi_riscv_amos_wrap.sv, src/axi_riscv_lrsc.sv, src/axi_riscv_lrsc_wrap.sv, src/axi_riscv_atomics.sv, src/axi_riscv_ato...

<gh_stars>1-10 --- project: description: "RISC-V SoC." foundry: "SkyWater" git_url: "https://github.com/kasirgalabs/kasirga-k0.git" organization: "Kasirga Labs" organization_url: "http://www.kasirgalabs.com/" owner: "<NAME>" process: "SKY130" project_name: "Kasirga K0" project_id: "00000000" tags: ...

<gh_stars>10-100 site_name: Mill repo_url: https://github.com/CircuitCoder/mill repo_name: CircuitCoder/mill edit_uri: edit/master/doc/docs/ copyright: Copyright © Mill developers, released under CC BY-NC-SA 4.0 plugins: - search: - git-revision-date-localized: type: iso_datetime fallback_to_build_dat...

<filename>site/docs/cloudbuild-deploy-docs.yaml # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 steps: - name: 'gcr.io/active-premise-257318/builder' args: ['./util/build_docs.py'] - name: 'gcr.io/cloud-builders/gsutil...

<reponame>IanBoyanZhang/kratos name: Google Test on: [push] jobs: build: runs-on: ubuntu-latest if: "!contains(github.event.head_commit.message, 'skip ci')" steps: - uses: actions/checkout@v2 - name: Checkout submodules shell: bash run: | auth_header="$(git config --local -...

<filename>modules/dem_uart/test/test_dem_uart_wb.manifest.yaml module: test_dem_uart_wb sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../../../blocks/regaccess/common/osd_regaccess_demux.sv - ../../../blocks/regaccess/common/osd_regaccess_layer.sv ...

<gh_stars>10-100 description: >- Final version of data and analysis scripts for sigcomm submission. Formatting and analysis differences in analysis.ipynb. Telemetry has also been disabled in the experiment as a whole. experiment: e2e repositories: P4Boosters: 317c7f28 TofinoP4Boosters: 1d83cb15853...

# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_ssr authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_cells} ...

<gh_stars>10-100 image: Visual Studio 2019 clone_depth: 1 platform: - Win32 configuration: - Release environment: matrix: - PYTHON: "36" - PYTHON: "37" - PYTHON: "38" - PYTHON: "39" # scripts that are called at very beginning, before repo cloning init: # if it's not tagged, only run py39 ...

defaults: - <EMAIL>: - "1600" - "3200" - "6400" - "12800" - <EMAIL>: - "7010" - "7020" - "at200" - <EMAIL>: - "data_1_4_1" - "data_1_4_2" - "data_in_redir" - "dotProduct_1" - "dotProduct_2" - "Sigmoid_axi" - <EMAIL>: - "update_knn1" - "update_knn2" ...

<filename>ci/vivado-checks.yml<gh_stars>0 quick_check:enclustra_ax3_pm3_a35__2018.3: extends: .template_vivado_quick_check variables: VIVADO_VERSION: "2018.3" PROJ: enclustra_ax3_pm3_a35 quick_check:enclustra_ax3_pm3_a35__2019.2: extends: .template_vivado_quick_check variables: VIVADO_VERSION: "201...

package: name: lowrisc_gpio description: "lowRISC GPIO" authors: ["lowRISC Contributors"] dependencies: lowrisc_prim: {path: ../prim} sources: # Level 0 - rtl/gpio_reg_pkg.sv # Level 1 - rtl/gpio_reg_top.sv - rtl/gpio.sv

language: rust # cache: cargo rust: - stable - beta - nightly # minimum supported version - "1.43.0" jobs: allow_failures: - rust: nightly fast_finish: true before_script: - rustup component add rustfmt script: - "[ $TRAVIS_RUST_VERSION != stable ] || cargo fmt -- --check" - cargo build - ca...

<reponame>SubjeBilisim/anasymod PROJECT: dt: 0.1e-6 board_name: PYNQ_Z1 plugins: ['msdsl'] emu_clk_freq: 10e6 FPGA_TARGET: fpga: tstop: 10e-6

# TODO: Extend this to add job(s) for simulations, can be run in parallel with risc-v formal. dist: focal sudo: false language: generic cache: directories: - /home/travis/build/$TRAVIS_PULL_REQUEST_SLUG/formal/env - /home/travis/build/$TRAVIS_REPO_SLUG/formal/env before_install: install: # If env is no...

apiVersion: kctf.dev/v1 kind: Challenge metadata: name: xss-bot spec: deployed: true powDifficultySeconds: 0 network: public: false healthcheck: # TIP: disable the healthcheck during development enabled: true # You can allow the bot to connect to other challenges internally. # This can be usef...

<reponame>e7p/hal pull_request_rules: - name: automatic merge on CI success and review conditions: - status-success=ci/gitlab/gitlab.com - "#approved-reviews-by>=1" - base=master - label!="work in progress" actions: merge: method: merge - name: Delete branch after merge...

name: aes clock_port: clk verilog: - aes.v - byte_mixcolum.v - keysched.v - mixcolum.v - sbox.v - subbytes.v - timescale.v - word_mixcolum.v

<reponame>inmcm/Simon_Speck_Ciphers language: python python: - "2.6" - "2.7" - "3.5" - "3.6" - "3.7-dev" branches: only: - master - inmcm/python_packaging before_install: - cd Python/simonspeckciphers/ - pip install setuptools_scm # required for py2.6 install: - python setup.py install scri...

<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...

name: CI/VHDLTest on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: act...

site_name: PsPIN repo_url: https://github.com/spcl/pspin theme: name: material nav: - Home: 'index.md' - Getting started: - Docker image: 'docker.md' - Manual installation: 'compile.md' - Running examples: 'examples.md' - Testing your own handlers: - Minimal handler: ...

<reponame>hito0512/Vitis-AI # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable ...

<filename>modules/wb_leds/data/wb_leds_csr.yml memory-map: bus: wb-32-be name: wb_leds_csr description: LEDs Register Bank children: - reg: name: leds width: 32 access: rw type: unsigned

# Technology Setup is done in hammer-tstech28-plugin/bwrc.yml. vlsi.core.max_threads: 24 # File inputs synthesis.inputs: input_files: [ "src/HDC_Sensor_Fusion_FoldedRule90/hdc_sensor_fusion.sv", "src/HDC_Sensor_Fusion_FoldedRule90/associative_memory.sv", "src/HDC_Senso...

<reponame>mfkiwl/neorv32 # Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version name: 'riscv-arch-test' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest strategy: fail-fast: false matrix: suite: - I - C - M - pr...

"top": arch: "artix7_200t" device_family: "xc7a200t" device_name: "doblink-6-overlay" device_speed: "sbg484-1" device: "xc7a200t-doblink-6-overlay-virt" board: "nexys_video" use_roi: "FALSE" timeout: 1600

# -*- yaml -*- modulename: path/off/SRC_BASE_DIR/modulev1.sv # Empty assignment means leave module out of project bad_mod: # Include other yaml files include: - chip/a10_substitutions.yml - chip/s10_substitutions.yml

name: sv-test-env channels: - LiteX-Hub - pkgw-forge - conda-forge dependencies: # - LiteX-Hub::iverilog # - LiteX-Hub::moore # - LiteX-Hub::odin_ii # - LiteX-Hub::slang # - LiteX-Hub::surelog # - LiteX-Hub::sv-parser # - LiteX-Hub::tree-sitter-verilog # - LiteX-Hub::uhdm-integration-verilator # - LiteX-...

name: vitis-ai-optimizer_darknet channels: - conda-forge - defaults dependencies: - python=3.6 - vai_optimizer_darknet_gpu

<reponame>Laegluin/mikrorechner<filename>.travis.yml language: rust matrix: include: - os: windows rust: stable env: - DEPLOY=1 - os: windows rust: beta - os: windows rust: nightly - os: linux rust: stable env: - DEPLOY=1 - os: linux r...

<reponame>mfkiwl/snitch axi/axi: commit: v0.29.1 domain: [cluster, soc] common_cells: commit: v1.21.0 domain: [cluster, soc]

name: "Direct Push Warning" on: push: branches: - master - release-** jobs: build: runs-on: ubuntu-latest if: github.repository_owner == 'NixOS' env: GITHUB_SHA: ${{ github.sha }} GITHUB_REPOSITORY: ${{ github.repository }} steps: - name: Check if commit is a merge comm...

<filename>src_files.yml udma_external_per: files: [ rtl/udma_external_per_reg_if.sv, rtl/udma_traffic_gen_rx.sv, rtl/udma_traffic_gen_tx.sv, rtl/udma_external_per_top.sv, rtl/udma_external_per_wrapper.sv, ]

# Copyright 2021 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 cache_root_dir: /usr/scratch2/dolent1/gitlabci/buildcache/mempool artifacts: tc-riscv-gcc: inputs: - Makefile - toolchain/riscv-gnu-...

<filename>rtl/vendor/pulp_platform_register_interface/.github/workflows/lint.yml # Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run all lint checks name: lint on: [push, pull_request] jobs: ##...

apiVersion: "v1" kind: "Service" metadata: name: "xss-bot" namespace: "default" labels: app: "xss-bot" spec: type: "LoadBalancer" selector: app: "xss-bot" ports: - protocol: "TCP" port: 1 targetPort: 1337

<filename>.devcontainer/docker-compose.yml version: '3.7' services: metalfs-dev: image: metalfs/sdk-base:webpack init: true command: tail -f /dev/null working_dir: /workspace environment: - DISPLAY=$DISPLAY volumes: - /tmp/.X11-unix:/tmp/.X11-unix - ..:/workspace devices...