Search is not available for this dataset
content stringlengths 0 376M |
|---|
<reponame>ess-dmsc/dmg-build-scripts<gh_stars>0
---
- hosts: data-generators
gather_facts: False
tasks:
- name: start loki data
command: "{{daemonize_cmd}} {{script_path}}/datagen_loki.bash"
tags:
- loki
|
<reponame>ejangelico/cryo-on-epix-hr-dev<gh_stars>1-10
cryoAsicGen1:
enable: True
ForceWrite: False
InitAfterConfig: False
PollEn: True
dataWriter:
enable: True
DataFile: ''
IsOpen: False
BufferSize: 0
MaxFileSize: 0
EpixHRGen1Cryo:
enable: True
MMCMSerdesRegisters:
enable:... |
<reponame>Malcolmnixon/FpgaDemo<filename>.github/workflows/vunit.yml
name: CI/VUnit
on:
push:
branches: [ master ]
pull_request:
branches: [ master ]
jobs:
build:
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v2
- uses: ghdl/setup-ghdl-ci@nightly
with... |
<reponame>icgrp/doblink
"7010":
arch: "zynq7"
device_family: "xc7z010"
device_name: "fig1"
device_speed: "clg400-1"
device: "xc7z010-fig1-roi-virt"
board: "zybo"
timeout: 200 |
GitBase: ..
TopRoguePackage: cameralink_gateway
RoguePackages:
- submodules/axi-pcie-core/python
- submodules/clink-gateway-fw-lib/python
- submodules/l2si-core/python
- submodules/lcls2-pgp-fw-lib/python
- submodules/lcls-timing-core/python
- submodules/surf/python
- python
RogueConfig:
- ../s... |
<filename>.gitlab-ci.yml
firmware:
image:
name: docker.i74.de:5000/gcvideo-build-system
stage: build
before_script:
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- export PATH=$PATH:/root/zpugcc/toolchain/install/bin
script:
- HDL/gcvideo_dvi/build-all.sh
artifacts:
p... |
# Human readable task name
name: Atheris
# Long form description.
description: |+
https://pypi.org/project/atheris/
# The flag
flag: CTF{atheris-hispida-is-the-closest-thing-that-exists-to-a-fuzzy-python}
# Task category. (one of hw, crypto, pwn, rev, web, net, misc)
category: pwn
# === the fields below will be fill... |
%YAML 1.2
---
ratio: 0.00473758865248 # 実空間における地図画像1pixあたりの大きさ(メートル)
file_path_information: # 各種環境情報
edge_map: "/data/RoutePlanner/edge.png"
line_map: "/data/RoutePlanner/line.png"
paths: "/data/RoutePlanner/paths.yaml"
path_connection: "/data/RoutePlanner/path_connection.yaml"
route: "/data/RoutePlanne... |
<filename>ci/vivado-builds.yml
build:enclustra_ax3_pm3_a35__2018.3:
extends: .template_vivado_build
variables:
VIVADO_VERSION: "2018.3"
dependencies:
- quick_check:enclustra_ax3_pm3_a35__2018.3
build:enclustra_ax3_pm3_a35__2019.2:
extends: .template_vivado_build
variables:
VIVADO_VERSION: "2019.2... |
image: python:3.7-alpine
run:
script:
- python3 setup.py bdist_wheel
artifacts:
paths:
- dist/*.whl
pages:
stage: deploy
script:
- pip install -U sphinx
- pip install -U sphinx-rtd-theme
- pip install dist/*.whl
- sphinx-build -b html doc/source/ public
artifacts:
paths:
... |
<reponame>Datum-Technology-Corporation/core-v-mcu
name: Retrieve CI result from GitLab
on:
push:
branches-ignore:
- gh-pages # deployment target branch (this workflow should not exist on that branch anyway)
- v** # such branch names conflict with tags
pull_request:
branches-ignore:
... |
<reponame>StanfordVLSI/dragonphy2
# Adapted from Garnet
name: constraints
commands:
- python gen_constraints.py
outputs:
- constraints.tcl
parameters:
# Name of the design
design_name: undefined
# Name of the ADK
adk_name: tsmc16
# Period of the main clock in nanoseconds
# (will be scaled by cons... |
<reponame>UNO-NULLify/eCTF20
exclude:
- /getting_started.md
- /package-lock.json
- /Vagrantfile
- /devserver.md
- /LICENSE
- /package.json
- /README.md
- /boot-image/.*
- /sample-audio/.*
- /node_modules/.*
- /vivado-boards/.*
- /docs/.*
- /vagrant/.*
- /pl/.*
- /mb/Cora-Z7-07S/.*
- /mb/drm_audio_fw_bsp/.*
- /mb/README... |
# File auto-generated by Padrick 0.1.0.post0.dev40+g68903cf
package:
name: axi_tlb
authors:
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
dependencies:
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
common_cells: { git: "https://github.... |
udma_i2c:
files: [
rtl/udma_i2c_reg_if.sv,
rtl/udma_i2c_bus_ctrl.sv,
rtl/udma_i2c_control.sv,
rtl/udma_i2c_top.sv,
]
|
<gh_stars>100-1000
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: test
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
axi: {path: ../../vendor/pulp_platform_axi}
req... |
name: Verible formatter
on:
pull_request:
jobs:
format:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@master
- uses: chipsalliance/verible-formatter-action@main
with:
parameters:
--indentation_spaces 4
--module_net_variable_alignment=preserve
--ca... |
name: build
on: push
jobs:
build:
runs-on: ubuntu-latest
strategy:
matrix:
python-version: [3.7, 3.8, 3.9]
steps:
- name: Checkout
uses: actions/checkout@v2.3.4
with:
fetch-depth: 0
- name: Set up Python ${{ matrix.python-version }}
uses: actions/setup-p... |
<gh_stars>10-100
# Huh this worked
env:
AFAR: boo
# agents: { queue: "papers" }
agents: { queue: "hours" }
steps:
- label: label1
# agents: { queue: "papers" }
commands:
- set -x
- echo hye
- export AFOO=bar
- ABOO=har
- echo AFOO=$$AFOO ABOO=$$ABOO AFAR=$$AFAR
- printenv | sort | head
- wait: { co... |
<filename>info.yaml<gh_stars>0
---
project:
description: "A simple RISC-V core+peripherals subsystem for the Google-sponsored Open MPW shuttles for SKY130."
foundry: "SkyWater"
git_url: "https://github.com/mballance/caravel_fwpayload.git"
organization: "<NAME>"
organization_url: "http://github.com/mballance... |
# For Windows based CI
environment:
matrix:
# For Python versions available on Appveyor, see
# http://www.appveyor.com/docs/installed-software#python
# The list here is complete (excluding Python 2.6, which
# isn't covered by this document) at the time of writing.
- BUILD_NAME: py27-unit
... |
---
- hosts: data-generators
gather_facts: False
tasks:
- name: check if we can ping the other servers with correct MTU
command: "~/deployment/event-formation-unit/util/hwcheck/pingcheck.bash 9000"
|
<reponame>f110/wing
language: go
sudo: false
go:
- 1.10.x
- 1.11.x
- 1.12.x
- 1.13.x
- 1.14.x
- 1.15.x
cache:
directories:
- $HOME/.cache/go-build
- $HOME/gopath/pkg/mod
env:
global:
- GO111MODULE=on
before_install:
- go get github.com/mattn/goveralls
- go get golang.org/x/tools/cm... |
<reponame>icgrp/doblink
# @package _global_
defaults:
- override /do_blink/fig1a@do_blink.fig.fig1a: ["7010", "7020", "at200"]
- override /do_blink/fig2a@do_blink.fig.fig2a: []
- override /do_blink/spam_filter@do_blink.fig.spam_filter: []
- override /do_blink/digit_recognition@do_blink.fig.digit_recognition: []... |
name: RAIDers of corruption
# Long form description.
description: |+
Picked up these at a yardsale, there doesn't seem to be anything useful in there though!
# The flag
flag: CTF{I_g0t_Str1p3s}
# Task category. (one of hw, crypto, pwn, rev, web, net, misc)
category: misc
# === the fields below will be filled by SRE ... |
PytorchModel: example-models/2LayerModel.plk
PytorchDict: example-models/2LayerDict.plk
OutputDir: my-hls-dir-test
ProjectName: myproject
XilinxPart: xc7vx690tffg1927-2
ClockPeriod: 5
IOType: io_parallel # options: io_serial/io_parallel
ReuseFactor: 1
DefaultPrecision: ap_fixed<18,8>
|
<reponame>BearerPipelineTest/google-ctf
apiVersion: kctf.dev/v1
kind: Challenge
metadata:
name: pwn
spec:
deployed: true
powDifficultySeconds: 0
network:
public: false
healthcheck:
# TIP: disable the healthcheck during development
enabled: true
horizontalPodAutoscalerSpec:
maxReplicas: 10
... |
name: vitis-ai-neptune
channels:
- file:///scratch/conda-channel
- pytorch
- defaults
- conda-forge/label/gcc7
- conda-forge
dependencies:
- python=3.6
- xip
- dpuv1-rt-neptune
|
name: dragonphy
outputs:
- dragonphy_top_tt.lib
- dragonphy_top_tt.db
- dragonphy_top.lef
- dragonphy_top.gds
- dragonphy_top.spi
- dragonphy_RDL.gds
- dragonphy_RDL.lef
commands:
- bash fixup.sh
|
<reponame>semify-eda/waveform-generator<gh_stars>1-10
name: Continuous Integration
on: [push]
jobs:
unit-tests:
runs-on: ubuntu-latest
timeout-minutes: 10
steps:
- uses: actions/checkout@main
- name: Compile and install iverilog
run: |
sudo apt install -y gperf
... |
<gh_stars>0
language: cpp
sudo: required
services:
- docker
matrix:
include:
- env: BUILD_TYPE=gcc CONFIG_FLAGS="-DCMAKE_CXX_COMPILER=g++-8"
- env: BUILD_TYPE=clang CONFIG_FLAGS="-DCMAKE_CXX_COMPILER=clang++-6.0 -DSLANG_COVERAGE=ON -DSLANG_SANITIZERS=undefined,address"
before_install:
- docker pull mpo... |
<filename>.travis.yml
dist: xenial
language: python
python:
- "3.4"
- "3.5"
- "3.6"
- "3.7"
# - "pypy3"
install: pip -q install tox codacy-coverage codecov
script:
- tox -e cover
after_success:
- python-codacy-coverage -r coverage.xml
- codecov
|
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
name: lint-editorconfig
on: [push, pull_request]
jobs:
editorconfig:
name: Editorconfig
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
with:
python-version: 3.x
- name: Install requirements
run: pip install editorconfig-checker
... |
<filename>ikondemo/actions/datagen_stop_multiblade.yml
---
- hosts: data-generators
gather_facts: False
tasks:
- name: stop data generators
command: "killall datagen_multiblade.bash udpgen_pcap"
ignore_errors: True
tags:
- multiblade
|
ebpc_encoder:
files: [
src/ebpc_pkg.sv,
src/fifo_slice.sv,
src/encoder/bpc_buffer.sv,
src/encoder/bpc_encoder.sv,
src/encoder/dbx_compressor.sv,
src/encoder/ebpc_encoder.sv,
src/encoder/seq_coder.sv,
src/encoder/shift_streamer.sv,
src/encoder/zrle.sv,
src/encoder/dbp_dbx_enc.sv,
]
ebpc_decoder:... |
apiVersion: apps/v1
kind: DaemonSet
metadata:
name: ctf-daemon
namespace: kube-system
labels:
k8s-app: ctf-daemon
spec:
selector:
matchLabels:
name: ctf-daemon
template:
metadata:
labels:
name: ctf-daemon
spec:
tolerations:
- key: node-role.kubernetes.io/master
... |
title: ASIC Design
description: Introduction To ASIC Design
google_analytics: UA-93559920-1
gems:
- jekyll-sitemap
- jekyll-seo-tag
|
# Human readable task name
name: PCIVault 2
# Long form description.
description: |+
See PCIVault 1 for the description and the challenge.
Enter the second flag here.
# The flag
flag: CTF{B3h1nD_S3vEn_D4v1C3s}
# Task category. (one of hardware, crypto, pwn, reversing, web, net, misc)
category: hardware
# === the f... |
<filename>software/yml/cryo_config_SCOPE.yml
cryoAsicGen1:
enable: True
ForceWrite: False
EpixHRGen1Cryo:
enable: True
Oscilloscope:
enable: True
ArmReg: False
TrigReg: False
ScopeEnable: False
TriggerEdge: Falling
TriggerChannel: AcqStart
TriggerMode: Always
... |
event_unit_flex:
incdirs: [
./rtl,
]
files: [
./rtl/event_unit_core.sv,
./rtl/hw_barrier_unit.sv,
./rtl/hw_dispatch.sv,
./rtl/hw_mutex_unit.sv,
./rtl/interc_sw_evt_trig.sv,
./rtl/periph_FIFO_id.sv,
./rtl/soc_periph_fifo.sv,
./rtl/event_unit_interface_mux.sv,
./rtl/event_uni... |
<reponame>benreynwar/axilent<filename>.travis.yml<gh_stars>1-10
language: python
python:
- "3.7"
os: linux
sudo: required
dist: bionic
before_install:
- sudo apt-get update -qq
- sudo apt-get install -y gnat zlib1g-dev
before_script:
- pip install fusesoc
- pip install -e .
- git clone --depth 1 https:/... |
<gh_stars>1-10
# USBpix board
USB:
bit_file : "firmware/mio.bit" # Selecting FPGA firmware
board_id : # Selecting USBpix board by ID
avoid_download : True # Avoiding download of FPGA firmware if already initialized
SINGLE_CHIP_ADAPTER_CARD:
no_calibration : False
#QUAD_MODULE_ADAPTER_CAR... |
name: oxide_ci
on: [push, pull_request]
jobs:
install-use-oxide-conda:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
with:
python-version: '3.7'
- run: bash scripts/setup -ci
- run: which pip3 && which python3 && which pip
... |
language: c
cache: ccache
sudo: true
dist: trusty
services:
- docker
before_install:
- docker pull librecores/librecores-ci-openrisc
- docker images
script:
- docker run --rm -v $(pwd):/src -e "JOB=$JOB" -e "SIM=$SIM" -e "PIPELINE=$PIPELINE" -e "EXPECTED_FAILURES=$EXPECTED_FAILURES" -e "EXTRA_CORE_ARGS=$EX... |
# you describe your data using the YAML notation here
# and then load them using Fixtures.load("data.yml")
# User(bob):
# email: <EMAIL>
# password: <PASSWORD>
# fullname: Bob
User(joel):
email: <EMAIL>
password: <PASSWORD>
fullname: Joel |
<gh_stars>1-10
- Global:
Print : true
- Library:
Name : zynqmp_acp_adapter_library
Format : "add_vhdl_file sources_1 #{library_name} #{file_name}"
PathList :
- "../../../src/main/vhdl/"
- "../../../PipeWork/src/components/reducer.vhd"
- "../../../PipeWork/src/comp... |
<gh_stars>10-100
apb_adv_timer:
incdirs: [
.,
]
files: [
adv_timer_apb_if.sv,
comparator.sv,
lut_4x4.sv,
out_filter.sv,
up_down_counter.sv,
input_stage.sv,
prescaler.sv,
apb_adv_timer.sv,
timer_cntrl.sv,
timer_module.sv,
]
|
<filename>.buildkite/pipelines/mem_tile_only.yml
agents: { jobsize: "hours" }
env:
GOLD: /build/mem_tile_only.${BUILDKITE_BUILD_NUMBER}
OVERRIDE_MFLOWGEN_BRANCH: silent_fail
steps:
##############################################################################
# INDIVIDUAL TILE RUNS - Mem tile only
- label: 'set... |
axi_mem_if_DP:
files: [
axi_mem_if_MP_Hybrid_multi_bank.sv,
axi_mem_if_multi_bank.sv,
axi_mem_if_DP_hybr.sv,
axi_mem_if_DP.sv,
axi_mem_if_SP.sv,
axi_read_only_ctrl.sv,
axi_write_only_ctrl.sv,
]
|
<reponame>ManuelG28/pulpino<filename>ips/adv_dbg_if/src_files.yml
adv_dbg_if:
incdirs: [
rtl,
]
files: [
rtl/adbg_axi_biu.sv,
rtl/adbg_axi_module.sv,
rtl/adbg_lint_biu.sv,
rtl/adbg_lint_module.sv,
rtl/adbg_crc32.v,
rtl/adbg_or1k_biu.sv,
rtl/adbg_or1k_module.sv,
rtl/adbg_or1k_st... |
package:
name: udma_external_per
authors:
- "<NAME> <<EMAIL>>"
dependencies:
udma_core: { git: "<EMAIL>:pulp-platform/udma_core.git", version: 1.0.1 }
sources:
# Source files grouped in levels. Files in level 0 have no dependencies on files in this
# package. Files in level 1 only depend on files ... |
<filename>src_files.yml<gh_stars>1-10
apb_uart_sv:
files: [
apb_uart_sv.sv,
uart_rx.sv,
uart_tx.sv,
io_generic_fifo.sv,
uart_interrupt.sv,
]
|
<reponame>nguyenhuydong1998/osd-hw
module: test_regaccess
sources:
- ../../../interfaces/common/dii_channel.sv
- ../common/osd_regaccess.sv
toplevel: osd_regaccess
simulators:
- vcs
parameters:
MOD_VENDOR: 1
MOD_TYPE: 2
MOD_VERSION: 3
MOD_EVENT_DEST_DEFAULT: 4
CAN_STALL: 1
MAX_REG_SIZE... |
---
# Firmware folder relative to repository root
firmwareFolder: firmware/fox_hoplite_multicast
hdlFolder: hdl/fox_hoplite_multicast
|
<gh_stars>1-10
linters-settings:
golint:
min-confidence: 0.3
gocyclo:
min-complexity: 28
goimports:
local-prefixes: github.com
linters:
enable:
- deadcode
- dupl
- errcheck
- gocritic
- gocyclo
- goimports
- golint
- gosimple
- govet
- ineffassign
- megac... |
name: lint-sv
on: [push, pull_request]
env:
VERIBLE_VERSION: 0.0-1051-gd4cd328
jobs:
system_verilog:
name: System Verilog Sources
runs-on: ubuntu-20.04
steps:
- uses: actions/checkout@v2
- name: Install Verible
run: |
set -e
mkdir -p build/verible
cd build/verible
... |
# Copyright 2021 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, s... |
name: build website
on:
push:
branches:
- main
jobs:
deploy:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Set up Node
uses: actions/setup-node@v2
with:
node-version: "12"
- name: Build
run: |
cd website
ya... |
udma_i2s:
files: [
rtl/i2s_clk_gen.sv,
rtl/i2s_rx_channel.sv,
rtl/i2s_ws_gen.sv,
rtl/cic_top.sv,
rtl/cic_integrator.sv,
rtl/cic_comb.sv,
rtl/udma_i2s_multich.sv,
rtl/udma_i2s_2ch.sv,
rtl/udma_i2s_reg_if.sv,
]
|
- import_playbook: integration_test_env_check.yml
- import_playbook: integration_test_start_up.yml
- import_playbook: integration_test_commands.yml
- import_playbook: integration_test_end.yml
- import_playbook: integration_test_checks.yml
|
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: mem_interface
authors:
- <NAME> <<EMAIL>>
dependencies:
reqrsp_interface: {path: ../reqrsp_interface}
export_include_dirs:
- include
s... |
name: ci
on: [push, pull_request]
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: YosysHQ/setup-oss-cad-suite@v1
- name: Run checks
run: tabbypip install xmlschema && make ci
|
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
options:
sim_args:
usage:
simulation args pass to simulator
with_value_action:
sim_option:
- $sim_args
compile_args:
usage:
compiling args pass to simulator
with_value_action:
compile_option:
- $compile_args |
<filename>app/Tlut/configs/arch/arch_tlut_systolic_projection_bank8_block32.yml
# This file defines single architecture set for tlut systolic array performance projection
- proj_16_16_bank8_block32
- proj_32_32_bank8_block32
- proj_64_64_bank8_block32
- proj_128_128_bank8_block32
|
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
<gh_stars>100-1000
apb_uart:
files: [
src/apb_uart.vhd,
src/slib_clock_div.vhd,
src/slib_counter.vhd,
src/slib_edge_detect.vhd,
src/slib_fifo.vhd,
src/slib_input_filter.vhd,
src/slib_input_sync.vhd,
src/slib_mv_filter.vhd,
src/uart_baudgen.vhd,
src/uart_interrupt.vhd,
src/u... |
# Build configure for https://www.tea-ci.org (fork of Drone CI with Msys2 support)
# 32-bit until release including https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=commitdiff;h=0aa738220bb9dea2ad479e484560767b36701947
build:
image: teaci/msys32
shell: mingw32
pull: true
branches:
-master
envir... |
# Copyright 2020 by the project contributors
# SPDX-License-Identifier: GPL-3.0-only
#
# Author(s): <NAME> <<EMAIL>>
version: v1.0
name: Ubuntu18 Based Pipeline
agent:
machine:
type: e1-standard-2 # Linux machine type with 2 vCPUs, 4 GB of RAM
os_image: ubuntu1804 # The Ubuntu 18.04 OS image.
fail_fas... |
<gh_stars>0
language: c
before_install:
- sudo apt-get install -yy qemu-system-mips
- curl -sc /tmp/gcokie 'https://drive.google.com/uc?export=download&id=1Mo5hGcCg1zm8Ca0KQB-G5PNI3fXfAAmR'
- getcode="$(awk '/_warning_/ {print $NF}' /tmp/gcokie)"
- curl -s -C - -LOJb /tmp/gcokie "https://drive.google.com/uc?exp... |
#
# List of RTL sources. Contrarily to IPs, these reside in
# the current Git repository.
# Uses the YAML syntax.
# 'domain' refers to the two soc,cluster domains for FPGA
# emulator synthesis
#
tb:
path: tb
domain: [soc]
vip:
path: vip
domain: [soc]
pulpemu:
path: pulpemu
domain: [soc]
pulp:
path: pulp
... |
<gh_stars>1-10
axi:
files:
- src/axi_pkg.sv
- src/axi_intf.sv
- src/axi_atop_filter.sv
- src/axi_cut.sv
- src/axi_delayer.sv
- src/axi_join.sv
- src/axi_lite_join.sv
- src/axi_lite_to_axi.sv
- src/axi_modify_address.sv
- src/axi_to_axi_lite.sv
axi_sim:
files:
- src/axi... |
<reponame>iicarus-bit/google-ctf
#
# Copyright 2019 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by ap... |
version: '3'
services:
db:
image: mysql:latest
ports:
- "3306:3306"
volumes:
- ./var/mysql:/var/lib/mysql
environment:
- MYSQL_DATABASE=db
- MYSQL_USER=admin
- MYSQL_PASSWORD=password
- MYSQL_ROOT_PASSWORD=password
web:
# image: eboraas/apache-php
image: tutum/apache-php
ports:
... |
name: Sync + Release
on:
repository_dispatch:
types: [sync_release]
workflow_dispatch:
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Sync with upstream + Release
run: ./.github/sync_release.sh <EMAIL> <EMAIL>
env:
NOTIFICATION_API_KEY: $... |
<reponame>Malcolmnixon/VhdlTest<filename>example/test.yaml
files:
- full_adder.vhd
- full_adder_pass_tb.vhd
- full_adder_fail_tb.vhd
- half_adder.vhd
- half_adder_pass_tb.vhd
- half_adder_fail_tb.vhd
tests:
- full_adder_pass_tb
- full_adder_fail_tb
- half_adder_pass_tb
- half_adder_fail_tb
|
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
# Device description for the Hewlett Packard Pulse-/ Pattern Generator.
# Only GPIB shows working communication with this device!
identifier : HEWLETT-PACKARD,HP81104A
channel 1:
on : OUTP1:NORM:STAT ON
off : OUTP1:NORM:STAT OFF
channel 2:
on : OUTP2:NORM:STAT ON
off : OUTP2:NORM:STAT OFF
... |
---
algorithm:
class: Nsga2
population_size: 200
probabilities:
crossover: 0.5
mutation: 0.01
injection: 0.9
shorten_individual: true
init:
method: ramped # grow or full or ramped
sensible_depth: 7
inject:
method: grow # grow or full or random
sensible_depth: 7
ter... |
# Copyright 2021 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
package:
name: mempool
dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.27.1 }
... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: snitch_const_cache
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
axi: {path: ../../vendor/pulp_axi}
snitch_icache: {p... |
<reponame>SHirsch78/XSharpDev<gh_stars>10-100
name: 'nightly artifacts cleanup'
on:
schedule:
- cron: '0 1 * * *' # every night at 1 am UTC
workflow_dispatch:
jobs:
delete-artifacts:
runs-on: windows-2019
steps:
- uses: kolpav/purge-artifacts-action@v1
with:
token: ${{ secrets... |
<reponame>FPGA-Research-Manchester/FABulous
name: fabulous-doc
channels:
- conda-forge
- defaults
dependencies:
- python>=3.8
- pip
- pip:
- -r ./requirements.txt
- graphviz
|
FPGA Core dts01 Temperature:
- id: 8
FPGA Core dts11 Temperature:
- id: 9
FPGA Core dts12 Temperature:
- id: 13
FPGA Core dts21 Temperature:
- id: 10
FPGA Core dts22 Temperature:
- id: 14
FPGA Core dts31 Temperature:
- id: 11
FPGA Core dts32 Temperature:
- id: 15
FPGA Core dts41 Temperature:
- id: 12
FPGA Core dts42 Te... |
variables:
VSIM: vsim-10.7b -64
VLIB: vlib-10.7b
VLOG: vlog-10.7b -64
SYNOPSYS_DC: synopsys-2019.12 dc_shell -64bit
before_script:
- export PATH=~/.cargo/bin:$PATH
- mkdir -p build
vsim:
stage: build
script:
- >
if ! memora lookup vsim; then
cd build && ../scripts/compile_vsim.sh
... |
<gh_stars>1-10
resources:
- grafana.f110.dev_grafanas.yaml
- grafana.f110.dev_grafanausers.yaml
- harbor.f110.dev_harborrobotaccounts.yaml
- harbor.f110.dev_harborprojects.yaml
- minio.f110.dev_miniobuckets.yaml
- minio.f110.dev_miniousers.yaml
- consul.f110.dev_consulbackups.yaml |
# Human readable task name
name: H1
# Long form description.
description: |+
Crypto is not real hacking, they say.
# The flag
flag: CTF{But_in_real_life_devs_would_never_use_such_a_buggy_RNG_right?}
# Task category. (one of hw, crypto, pwn, rev, web, net, misc)
category: crypto
# === the fields below will be filled... |
<gh_stars>10-100
name: symbiyosys-tests
on: [push, pull_request]
jobs:
build:
runs-on: ubuntu-18.04
steps:
- uses: actions/checkout@v2
with:
lfs: true
- name: Install SymbiYosys
run: |
wget https://github.com/open-tool-forge/fpga-toolchain/releases/download/... |
name: cgra_rtl_sim_compile
commands:
- bash compile_rtl_testbench.sh
inputs:
- design.v
outputs:
- xcelium.d
- xrun.log
- libcgra.so
parameters:
array_width: 12
array_height: 12
axi_addr_width: 13
axi_data_width: 32
glb_tile_mem_size: 256
clock_period: 1.2
top_name: top
postconditions:
- ... |
# Use full-chip agents so as not to hamper per-check-in jobs
agents: { queue: "papers" }
env:
GOLD: /build/glb${BUILDKITE_BUILD_NUMBER}/full_chip
# OVERRIDE_MFLOWGEN_BRANCH: placementCheck
steps:
# Build mflowgen framework for full-chip
- label: 'setup'
commands:
- 'source mflowgen/bin/setup-buildkite.sh --d... |
name: mc-gen-sram
commands:
- bash gen_srams.sh
outputs:
- sram.v
- sram_pwr.v
- sram.lef
- sram_tt.lib
- sram_tt.db
- sram.gds
- sram.spi
parameters:
sram_word_size: 144
sram_num_words: 1024
sram_mux_size: 4
sram_corner: "tt0p8v25c"
sram_partial_write: True
|
<filename>mflowgen/glb_top/sim/configure.yml
name: sim
commands:
- bash run_sim.sh
inputs:
- design.v
- glb_tile.v
outputs:
- sim.log
postconditions:
- assert File( 'outputs/sim.log' ) # must exist
# Basic error checking
- assert '*E,' not in File( 'outputs/sim.log' )
|
variables:
VSIM: vsim-10.6b -64
VLIB: vlib-10.6b
VMAP: vmap-10.6b
VCOM: vcom-10.6b -64
VLOG: vlog-10.6b -64
VOPT: vopt-10.6b -64
before_script:
- export PATH="~fschuiki/.cargo/bin/":$PATH
- |
echo 'plugins:' > Bender.local
echo ' bender-vsim: { git: "<EMAIL>:fschuiki/bender-vsim.git", rev: mas... |
sim.inputs.top_module: "SVM"
sim.inputs.tb_dut: "dut"
sim.inputs.tb_name: "SVM_tb"
sim.inputs.input_files_meta: "append"
sim.inputs.input_files:
- "src/SVM/SVM.sv"
- "src/SVM/SVM_tb.sv"
- "src/SVM/multiply_quantize.sv"
sim.inputs:
timescale: "1ns/1ps"
options:
- "-notice"
- "-line"
- "-debug_... |
<reponame>mgielda/hwt<filename>.travis.yml
dist: trusty
language: python
git:
depth: 1
cache:
apt: true
python:
- '3.6'
install:
- export PYTHON_VERSION=$(python -c "import sys;v = sys.version_info;print('%d.%d.%d' % (v[0], v[1], v[2]))")
- export PYTHON_VERSION_SHORT=$(python -c "import sys;v = sys.version... |
PROJECT:
dt: 0.1e-6
board_name: ZC706
plugins: ['msdsl']
emu_clk_freq: 10e6
flatten_hierarchy': 'none'
vivado_stack: 2000
ila_depth: 4096
# cpu_debug_mode: 1
# cpu_debug_hierarchies: [[0, "top"]]
|
<filename>uloop-example/code.yml
#
# code.yml
# <NAME> <<EMAIL>>
#
# Copyright (C) 2017-2019 ETH Zurich, University of Bologna
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# See LICENSE.sw.txt for details.
# You may obtain a copy of... |
<reponame>ess-dmsc/dmg-build-scripts
---
- hosts: data-generators
gather_facts: False
tasks:
- name: start multigrid data
command: "{{daemonize_cmd}} {{script_path}}/datagen_multiblade.bash"
tags:
- multiblade
|
<reponame>pan185/UnarySim<gh_stars>1-10
# This file defines single architecture set for tlut systolic array performance projection
- proj_16_16_bank4_block16
- proj_32_32_bank4_block16
- proj_64_64_bank4_block16
- proj_128_128_bank4_block16
|
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