Search is not available for this dataset
content stringlengths 0 376M |
|---|
ssh:
user: iped
key: '~/.ssh/id_rsa_tofino'
port: 22
params:
rate: '{0.args.rate}'
pktgen_template: ./pktgen_template.lua
n_set_pkts: 5000
n_get_pkts: 45000
n_total_pkts: 50000
key_space: 10000
zipf_coef: 1.00
dirs:
home: /home/{0.ssh.user}
P4Boosters: '{0.dirs.home}/dc... |
name: Test and Publish
on:
push:
branches:
- main
jobs:
checks:
uses: ./.github/workflows/checks.yml
# the jobs below are taken from the actions in https://github.com/relekang/python-semantic-release under MIT License
beautify:
name: Beautify
runs-on: ubuntu-latest
concurrency: push
... |
trigger:
branches:
include:
- '*'
tags:
include:
- '*'
resources:
repositories:
- repository: abs-tudelft
type: github
endpoint: github
name: abs-tudelft/azure-pipelines-templates
jobs:
- job:
pool:
vmImage: ubuntu-latest
container: abstudelft/ghdl-gcc-python:latest
step... |
<filename>src_files.yml
axi2mem:
files: [
axi2mem_busy_unit.sv,
axi2mem_rd_channel.sv,
axi2mem.sv,
axi2mem_tcdm_rd_if.sv,
axi2mem_tcdm_synch.sv,
axi2mem_tcdm_unit.sv,
axi2mem_tcdm_wr_if.sv,
axi2mem_trans_unit.sv,
axi2mem_wr_channel.sv,
]
|
<gh_stars>0
name: Chisel-test
on: [push]
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Cache SBT
uses: actions/cache@v2
with:
path: |
~/.ivy2/cache
~/.sbt
key: ${{ runner.os }}-sbt-${{ hashFiles('**/bu... |
axi_node:
incdirs: [
.,
]
files: [
apb_regs_top.sv,
axi_address_decoder_AR.sv,
axi_address_decoder_AW.sv,
axi_address_decoder_BR.sv,
axi_address_decoder_BW.sv,
axi_address_decoder_DW.sv,
axi_AR_allocator.sv,
axi_ArbitrationTree.sv,
axi_AW_allocator.sv,
axi_BR_allocator.... |
<gh_stars>10-100
---
title: VGA Chip
author:
- Felix "xq" Queißner
date: May 07, 2020
abstract: The VGA Chip provides a framebuffer with 256×128 pixels output. |
config:
- xlen : 64
- supportISA : [System,ZiCsr,RV64I,RV64M,RV64F,RV64D,RV64Q,RV64Zfh,RV64A]
- supportMode : [M,S] |
<gh_stars>1-10
GitBase: ..
TopRoguePackage: ucsc_hn
RoguePackages:
- python
RogueScripts:
- ../software/scripts/renaGui
CondaDependencies:
- surf
- rce_gen3_fw_lib
RogueConfig:
Targets:
MultiRena:
ImageDir: targets/MultiRena/images
Extensions:
- bit
SlaveRena:
ImageDir: ... |
components:
incdirs: [
../includes,
]
files: [
apb_clkdiv.sv,
apb_timer_unit.sv,
apb_soc_ctrl.sv,
counter.sv,
memory_models.sv,
pulp_interfaces.sv,
axi_slice_dc_master_wrap.sv,
axi_slice_dc_slave_wrap.sv,
glitch_free_clk_mux.sv,
scm_2048x32.sv,
scm_512x32.sv,
]
c... |
<filename>tests/vivado_backend_tests/projects/2/hls4ml_config.yml<gh_stars>1-10
Backend: Vivado
ClockPeriod: 5
HLSConfig:
LayerName:
layer1:
Precision:
bias: ap_fixed<7,1>
weight: ap_fixed<7,1>
ReuseFactor: 1
layer1_input:
Precision:
result: ap_fixed<22,2>
layer2:... |
<reponame>anmeza/platform_ml_models
AcceleratorConfig:
Driver: python
Interface: axi_stream
Precision:
Input: float
Output: float
Backend: VivadoAccelerator
Board: pynq-z2
ClockPeriod: 10
HLSConfig:
LayerName:
flatten:
StreamDepth: 10000
in_local:
StreamDepth: 10000
input_1:
... |
<gh_stars>1-10
# Copyright 2018-2021 The University of Birmingham
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless req... |
<reponame>pulp-platform/hypnos
hypnos:
incdirs:
- rtl/spi_module
files:
- src/common/pkg_common.sv
- src/hd_accelerator/hd_encoder/mixer/pkg_mixer_permutate.sv
- src/hd_accelerator/hd_encoder/mixer/mixer.sv
- src/hd_accelerator/hd_encoder/man_module/unary_encoder/unary_encoder.sv
- src/hd_accelerator/... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
cv32e40p_regfile_rtl:
targets: [
rtl,
tsmc55,
gf22,
]
incdirs: [
./rtl/include,
]
files: [
./rtl/cv32e40p_register_file_test_wrap.sv,
./rtl/cv32e40p_register_file_latch.sv,
]
cv32e40p:
vlog_opts: [
-L fpnew_lib,
]
incdirs: [
./rtl/include,
../../rtl/includes,
]
... |
<filename>vsg_files.yaml
file_list:
- common/source/clk_div_n.vhd
- common/sim/clk_div_n_long_code_tb.vhd
- common/sim/clk_div_n_stimulus_array_tb.vhd
- common/sim/clk_div_n_stimulus_file_tb.vhd
- common/sim/clk_div_n_vunit_tb.vhd
- demo/impl1/source/fpga_demo.vhd
|
name: 'test'
on:
push:
pull_request:
schedule:
- cron: '0 0 * * 5'
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- run: docker pull ghdl/vunit:llvm
- run: docker run -t -v $PWD:/build -w /build ghdl/vunit:llvm bash -c "make GNATMAKE='gnatmake -j'$(nproc)"
p... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
before_script:
- export SNPSLMD_LICENSE_FILE="1711@sac-lic-31:1711@sc-lic-32:1711@lic-34:1711@sc-lic-33:1711@sc-lic-14"
stages:
- test
regress:
stage: test
script:
- make USE_VM_ENV=1
- /home/bin/ci_sanity -tot `pwd`
|
name: Test
on:
push:
branches:
- master
pull_request:
branches:
- master
jobs:
test:
name: Test
runs-on: ubuntu-latest
steps:
- name: Wit Init
uses: sifive/wit/actions/init@v0.14.0
with:
additional_packages: git@github.com:sifive/environment-blockci-sifive.gi... |
---
project:
description: "A SoC with two crypto-supported RISC-V cores"
foundry: "SkyWater"
git_url: "https://github.com/phthinh/soric_project.git"
organization: ""
organization_url: ""
owner: "<NAME> - <NAME> - <NAME>"
process: "SKY130A"
project_name: "SORIC"
project_id: "321"
tags:
- "Open MP... |
<reponame>hprice99/ENGG4811_code
---
networkRows: 3
networkCols: 2
foxNetworkStages: 2
foxNodeFifos:
peToNetwork: 8
networkToPe: 1024
resultNodeCoord:
x: 0
y: 0
resultNodeFifos:
peToNetwork: 8
networkToPe: 1024
romNodeCoord:
x: 0
y: 2
resultUartFifoDepth: 1024
packetFormat:
multicastGroupBits: ... |
<gh_stars>10-100
#=========================================================================
# Synopsys PrimePower -- Gate-Level Power Estimation
#=========================================================================
# This step runs gate-level average power analysis with Synopsys PrimeTime PX
# or PrimePower, the s... |
<reponame>niwis/snitch
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: spm_interface
authors:
- <NAME> <<EMAIL>>
dependencies:
common_cells: {path: ../../vendor/pulp_platform_common_ce... |
<gh_stars>0
afe_readout_subsystem:
vlog_opts: [
"-L vivopulp_lib"
]
files: [
rtl/afe_reg_if.sv,
rtl/afe_ro_arbiter.sv,
rtl/afe_ro_conf_if.sv,
rtl/afe_sync_if.sv,
rtl/afe_buff_addrgen.sv,
rtl/afe_l2_addrgen.sv,
rtl/afe_top.sv,
rtl/afe_ro_udma_if.sv,
rtl/afe_ro_sram_buffer.sv... |
<gh_stars>0
### YamlMime:ManagedReference
items:
- uid: alps_.net_api.abstracPass
commentId: T:alps_.net_api.abstracPass
id: abstracPass
parent: alps_.net_api
children: []
langs:
- csharp
- vb
name: abstracPass
nameWithType: abstracPass
fullName: alps_.net_api.abstracPass
type: Interface
source:... |
<gh_stars>1000+
# Copyright 2021 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed... |
GitBase: ..
Targets:
SmurfKcu1500RssiOffload10GbE:
ImageDir: targets/SmurfKcu1500RssiOffload10GbE/images
Extensions:
- mcs
Kcu105TenGigE:
ImageDir: targets/Kcu105TenGigE/images
Extensions:
- bit
Releases:
all:
Primary: True
Targets:
- SmurfKcu1500RssiOffload10GbE
... |
<reponame>ultrazohm/ultrazohm_sw
image:
file: .devcontainer/Dockerfile
# List the ports you want to expose and what to do when they are served. See https://www.gitpod.io/docs/config-ports/
ports:
- port: 3000
onOpen: open-preview
# List the start up tasks. You can start them in parallel in multiple terminals... |
#Descriptions:
#CMD: cpld command
#A: Assitant Board
#T: Target Board
#FUNC0: the function of this pin connection
#DIRECTION: A2T T2A T2T
#FRDM A-B-C-D DEFINITION
#| NAME | SIZE | CPLD_SCH | FRDM_SCH
#| A | (10*2) | JJ_2 | ?
#| B | (8*2) | JJ_1 | ?
#| C | (5*2) | JJ_3 | ?
#| D | (8*2) |... |
<filename>ikondemo/actions/datagen_start_NMX_overlap.yml<gh_stars>0
---
- hosts: data-generators
gather_facts: False
tasks:
- name: start gem data
command: "{{daemonize_cmd}} {{script_path}}/datagen_NMX_overlap.bash 1000"
tags:
- gdgem
|
# Technology Setup is done in hammer-tstech28-plugin/bwrc.yml.
vlsi.core.max_threads: 24
# File inputs
synthesis.inputs:
input_files: [
"src/SVM_SRAM/SVM.sv",
"src/SVM_SRAM/multiply_quantize.sv",
"src/SVM_SRAM/SVM_memories_214.sv"
]
top_module: "SVM"
... |
package:
name: hypnos
authors:
- "<NAME> <<EMAIL>>"
dependencies:
tech_cells_generic: {git: "<EMAIL>:pulp-platform/tech_cells_generic.git", version: 0.2.3}
common_cells: { git: "<EMAIL>:pulp-platform/common_cells.git", version: 1.13.1 }
udma_core: { git: "https://github.com/pulp-platform/udm... |
<filename>fpga/modules/address/config.yml
---
name: address
board: boards/red-pitaya
cores:
- fpga/cores/comparator_v1_0
- fpga/cores/averager_counter_v1_0
- fpga/cores/address_generator_v1_0
- fpga/cores/edge_detector_v1_0
control_registers:
- addr # reset[0:0], trig_acq[1:1], delay_tvalid[6:2]
- d... |
<reponame>Calculasians/HDC-Sensor-Fusion-Research
power.inputs.waveforms_meta: "append"
power.inputs.waveforms:
- "/tools/B/daniels/hammer-tsmc28/build/sim-par-rundir/hdc_sensor_fusion.vcd"
power.inputs.database: "/tools/B/daniels/hammer-tsmc28/build/par-rundir/latest"
power.inputs.tb_name: "hdc_sensor_fusion_tb"
... |
<reponame>usmnzain/serv
name: build-openlane-sky130
on: [push]
jobs:
build-openlane:
runs-on: ubuntu-latest
steps:
- name: Checkout subservient
uses: actions/checkout@v2
- name: Build with Openlane
uses: librecores/ci-fusesoc-action@migrate-dockerized
with:
core: ... |
title: RFSoC 2x2
logo: /assets/img/logo.png
description: RFSoC 2x2 development board
show_downloads: true
google_analytics: UA-190351354-1
theme: jekyll-theme-dinky
|
image:
file: .gitpod.Dockerfile
tasks:
- before: >
sudo apt update ;
sudo apt install iverilog ;
pip3 install cocotb ;
export COCOTB_REDUCED_LOG_FMT=1 ;
git submodule update --init ;
cargo install rstbrun
init: >
cd /workspace/rstb_examples/test_axis_fifo &&
carg... |
<filename>appveyor.yml
build: false # Tell appveyor to not use msbuild
environment:
matrix:
- PYTHON: 2.7
platform:
- x86
- x64
init:
- "ECHO %PYTHON%"
- ps: Start-FileDownload 'http://download.microsoft.com/download/7/9/6/796EF2E4-801B-4FC4-AB28-B59FBF6D907B/VCForPython27.msi' C:\VCForPython27.msi; e... |
sudo: required
language: ruby
services:
- docker
before_install:
- echo "Testing Docker Hub credentials"
- docker login -e=$DOCKER_EMAIL -u=$DOCKER_USERNAME -p=$DOCKER_PASSWORD
- echo "Docker Hub credentials are working"
- docker build -t build-springxd-base .
script:
- docker ps -a
after_success:
- ... |
<filename>infrastructure/kctf/base/challenge-skeleton/healthcheck/secrets/kustomization.yaml<gh_stars>0
secretGenerator:
- name: challenge-skeleton-healthcheck-secrets
files:
generatorOptions:
disableNameSuffixHash: true
labels:
type: generated
annotations:
note: generated
|
---
name: adc-dac
board: boards/red-pitaya
cores:
- fpga/cores/axi_ctl_register_v1_0
- fpga/cores/axi_sts_register_v1_0
- fpga/cores/dna_reader_v1_0
- fpga/cores/redp_adc_v1_0
- fpga/cores/redp_dac_v1_0
memory:
- name: control
offset: '0x60000000'
range: 4K
- name: status
offset: '0x50000000... |
<filename>Bender.yml
package:
name: redundancy_cells
authors:
- "<NAME> <<EMAIL>>"
dependencies:
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 }
hci: ... |
<reponame>StanfordAHA/garnet
name: Tile_PE
commands:
- bash get_Tile_PE_outputs.sh
inputs:
- design.v
outputs:
- Tile_PE_tt.lib
- Tile_PE_tt.db
- Tile_PE.lef
- Tile_PE.gds
- Tile_PE.vcs.v
- Tile_PE.vcs.pg.v
- Tile_PE.pt.sdc
- Tile_PE.spef.gz
- Tile_PE.lvs.v
- Tile_PE.sdf
postconditions:
- ... |
# .readthedocs.yml
# Read the Docs configuration file
# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
version: 2
# Use conda because default Python is not compiled with --enable-shared
conda:
environment: documentation/conda.yml
python:
install:
- method: pip
path: .
e... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
package:
name: snitch_ipu
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
common_cells: {path: ../../vendor/pulp_platform_common... |
<reponame>sgherbst/svreal
steps:
- command: |
# set up environment
source /cad/modules/tcl/init/bash
module load base xcelium/19.03.003 vcs
/usr/local/miniconda/bin/python3.7 -m venv venv
source venv/bin/activate
printenv
# upgrade pip
python -m pip install --upgrade p... |
apiVersion: v1
kind: Service
metadata:
name: sourcerer-app
labels:
app: sourcerer-app
spec:
type: ClusterIP
ports:
- port: 80
targetPort: 80
selector:
app: sourcerer-app
---
apiVersion: apps/v1beta1
kind: Deployment
metadata:
name: sourcerer-app
spec:
replicas: $REPLICAS
template:
meta... |
<reponame>een5afr-public/ariane<filename>docs/_data/docs.yml
- title: Introduction
docs:
- home
- documentation
- title: Architecture
docs:
- pcgen_stage
- if_stage
- id_stage
- issue_stage
- ex_stage
- commit_stage
|
variables:
VSIM: vsim-10.7e
VLOG: vlog-10.7e
before_script:
- export PATH="~balasr/.local/bin":$PATH
stages:
- build
- test
build:
stage: build
script:
- cd testbench
- make build
test_pulp_tap:
stage: test
script:
- cd testbench
- make build run
|
variables:
build_num: $(Build.BuildNumber)
jobs:
- job: PyPi_Linux
pool:
vmImage: 'ubuntu-18.04'
steps:
- bash: echo "##vso[task.prependpath]$CONDA/bin"
displayName: Add conda to PATH
- script: |
sudo apt-get install zlib1g-dev
echo "Which Conda: `which conda`"
conda create --... |
<reponame>dosadih/svut<gh_stars>10-100
name: macOS
on: [push]
jobs:
lint-code:
runs-on: macos-latest
steps:
- uses: actions/checkout@v2
- run: brew install pylint
- run: cd test; ./lint.sh
ci-tests:
runs-on: macos-latest
steps:
- uses: actions/checkout@v2
- run: brew in... |
pull_request_rules:
- name: remove outdated reviews
conditions:
- base=master
actions:
dismiss_reviews:
pull_request_rules:
- name: automatic squash-and-merge on CI success and review
conditions:
- status-success=continuous-integration/travis-ci/pr
- "#approved-reviews-by>=1"
... |
<reponame>rits-drsl/ZybotR2-96-fpt19
%YAML 1.2
---
conn00:
dst_path_index: 9
dst_path_number: 1
src_path_index: 40
src_path_number: 2
conn01:
dst_path_index: 100
dst_path_number: 3
src_path_index: 67
src_path_number: 1
conn02:
dst_path_index: 94
dst_path_number: 4
src_path_index: 40
src_path_num... |
# Adapted from Garnet and ButterPHY
name: prelvs_fix
commands:
- |
mkdir -p outputs
python fix_adbg_intf_i.py inputs/design.lvs.v
python fix_term_vss.py inputs/design_alt.lvs.v
mv inputs/design_alt_alt.lvs.v outputs/design.lvs.v
inputs:
- design.lvs.v
outputs:
- design.lvs.v
|
package:
name: tech_cells_generic
description: "Technology-agnostic building blocks."
sources:
- target: all(fpga, xilinx)
files:
- src/deprecated/cluster_clk_cells_xilinx.sv
- src/fpga/tc_clk_xilinx.sv
- target: not(all(fpga, xilinx))
files:
- src/deprecated/cluster_clk_cells.sv
... |
<gh_stars>0
name: Assets
on:
release:
types:
- created
pull_request:
env:
CMAKE_VERSION: '3.20.0'
jobs:
archive:
name: Linux
runs-on: ubuntu-latest
container: centos:7
strategy:
matrix:
sim:
- ON
- OFF
steps:
- name: Install dependencies
run... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: snitch_icache
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
common_cells: {path: ../../vendor/pulp_platform_common_cell... |
<filename>.travis.yml
language: python
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- verilator
- verilog
- g++-4.9
python:
- "3.6"
install:
# Convenience script for installing coreir on travis
- wget https://raw.githubusercontent.com/phanrahan/magma/master/.travis/in... |
<filename>vlsi/example-design.yml
# General Hammer Inputs Related to the Design and Build System
# Generate Make include to aid in flow
vlsi.core.build_system: make
vlsi.core.max_threads: 12
# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.... |
language: cpp
# run on new infrastructure
dist: xenial
sudo: false
cache:
apt: true
directories:
$RISCV
$VERILATOR_ROOT
timeout: 1000
# required packages to install
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- gcc-7
- g++-7
- gperf
- autoconf
-... |
<gh_stars>1-10
---
mapper:
class: MyMapper
initialize: file.abnf
selector:
class: MySelector
require: test/data/external_class.rb
attribute1: 3
attr2: toto
|
<reponame>DanielTRYTRYLOOK/RDF-2020
name: pci_bridge32
clock_port: wb_clk_i
verilog:
- bus_commands.v
- pci_async_reset_flop.v
- pci_bridge32.v
- pci_cbe_en_crit.v
- pci_conf_cyc_addr_dec.v
- pci_conf_space.v
- pci_constants.v
- pci_cur_out_reg.v
- pci_delayed_sync.v
- pci_delay... |
description: Featherweight IP programmable interrupt controller
compatible: "fw_pic"
include: [interrupt-controller.yaml, base.yaml]
properties:
reg:
required: true
"#interrupt-cells":
const: 1
num-irqs:
type: int
required: true
description: Number o... |
name: C/C++ CI Build and Test (dummy)
on:
workflow_dispatch:
push:
jobs:
build:
runs-on: ubuntu-latest
strategy:
matrix:
build-type: [Debug, Release, RelWithDebInfo]
steps:
- run: exit 0
test:
runs-on: ubuntu-latest
steps:
- run: exit 0
|
<filename>models/AI-Model-Zoo/model-list/cf_inceptionv3_imagenet_299_299_11.4G_2.0/model.yaml
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.... |
---
algorithm:
class: SteadyState
population_size: 800
probabilities:
crossover: 0.9
mutation: 0.1
injection: 0.1
termination:
max_steps: 2000
on_individual: :stopping_condition
init:
method: ramped # grow or full or random or ramped
random_length: 8
sensible_depth: 5
... |
<gh_stars>1-10
# RUN: not lld -flavor darwin -arch x86_64 -macosx_version_min 10.9 -flat_namespace -undefined error %s -o %t %p/Inputs/libSystem.yaml 2>&1 | FileCheck %s
--- !native
defined-atoms:
- name: _main
scope: global
content: [ E9, 00, 00, 00, 00 ]
alignment: 16... |
name: 'Documentation'
on:
push:
pull_request:
workflow_dispatch:
jobs:
doxygen:
runs-on: ubuntu-latest
name: 'SW Framework'
steps:
- name: '🧰 Repository Checkout'
uses: actions/checkout@v2
- name: '🛠️ Modifying Doxyfile'
run: |
ls -al ./docs
sed -i 's/$(P... |
<filename>integration_files/SweRV_EH1/riscv_dv_extension/testlist.yaml<gh_stars>0
- test: cmark
c_tests: directed_tests/c/cmark.c
gcc_opts: -g -O3 -funroll-all-loops
iterations: 1
rtl_test: core_base_test_benchmark
- test: cmark_iccm
c_tests: directed_tests/c/cmark_iccm.c
gcc_opts: -g -O3 -funroll-all-loop... |
<reponame>codepainters/edalize<filename>.github/workflows/ci.yml
name: CI
on:
push:
pull_request:
# Run CI once a week even without code changes to ensure tests pass with
# updated dependencies.
schedule:
- cron: '0 0 * * 5'
# Allow triggering a CI run from the web UI.
workflow_dispatch:
jobs:
Fo... |
<filename>app/Tlut/configs/arch/arch_tlut_systolic_projection_bank16_block32.yml
# This file defines single architecture set for tlut systolic array performance projection
- proj_16_16_bank16_block32
- proj_32_32_bank16_block32
- proj_64_64_bank16_block32
- proj_128_128_bank16_block32
|
<reponame>SamuelRiedel/snitch
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: system-snitch-cluster
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
... |
%YAML 1.2
---
Basis:
feature_pt_min_num_feat: 2000 # cv::calcOpticalFlowPyrLKで追跡された特徴点の数が
# この値より少なければFAST特徴点抽出による再計算を行う
vo_queue_depth: 5
vo_dtheta_valid_norm_threshold: 0.001 # 移動量がこの値以下であれば⊿θ = 0とする
Fast:
use_nms: 1 # 1: use, 0: not use
threshold: 20
Opt... |
<reponame>BearerPipelineTest/google-ctf<filename>2021/quals/rev-adspam/metadata.yaml
# Copyright 2021 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org... |
<reponame>drhodes/jade2hdl
flags: {}
extra-package-dbs: []
packages:
- .
- ../rawr
extra-deps:
- hashids-1.0.2.3
- parsec3-numbers-0.1.0
- rawr-0.1.0
resolver: lts-9.4
|
<gh_stars>1-10
apb_i2c:
incdirs: [
.,
]
files: [
apb_i2c.sv,
i2c_master_bit_ctrl.sv,
i2c_master_byte_ctrl.sv,
i2c_master_defines.sv,
]
|
marble_sim:
stage: test
script:
- cd projects/test_marble_family && make all net_slave_check
.bitgen:
stage: synthesis
before_script:
- cd projects/test_marble_family && ls /non-free
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
expire_in: 2 days
marble_mini_synth:
extends: .bitgen
... |
<filename>third_party/tests/ariane/tb/common_verification/Bender.yml
package:
name: common_verification
authors:
- "<NAME> <<EMAIL>>"
sources:
# Files in this package are meant for simulation only.
- target: simulation
files:
# Source files grouped in levels. Files in level 0 have no dependencies o... |
dist: bionic
language: cpp
compiler:
- gcc
addons:
apt:
packages:
- g++-8
before_install:
- wget https://github.com/bazelbuild/bazel/releases/download/1.1.0/bazel_1.1.0-linux-x86_64.deb
- sudo dpkg -i bazel_1.1.0-linux-x86_64.deb
- git clone https://github.com/google/verible.git verible
- cd v... |
package:
name: cluster_peripherals
dependencies:
hci: { git: "https://github.com/pulp-platform/hci.git", version: "1.0" }
sources:
- cluster_control_unit/cluster_control_unit.sv
- include_dirs:
- event_unit/include
files:
# Level 0
- event_unit/HW_barrier_logic.sv
- event_unit/eve... |
<filename>.github/workflows/android.yml
name: Android CI
on:
push:
branches:
- master
- tree/*MAINT
pull_request:
branches:
- master
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- name: set up JDK 11
uses: actions/setup-java@v1
with:
... |
<reponame>hzeller/Surelog
name: 'regression_on_demand'
on:
workflow_dispatch:
jobs:
linux-gcc:
runs-on: ubuntu-latest
defaults:
run:
shell: bash
steps:
- name: Install dependencies
run: |
sudo apt-get update -qq
sudo apt install -y \
g++-7 \
... |
<filename>.travis.yml
sudo: enabled
language: cpp
env:
global:
- secure: "<KEY>
before_script:
- echo -n | openssl s_client -connect scan.coverity.com:443 | sed -ne '/-BEGIN CERTIFICATE-/,/-END CERTIFICATE-/p' | sudo tee -a /etc/ssl/certs/ca-
- ./src/runtime_src/tools/scripts/xrtdeps.sh
- cd build
before_... |
register_maps:
- ./test_map_1.yaml
- ./test_map_2.yaml
output_generators:
- vhdl_package
- c_header
output_paths:
default: ./default_outputs
c_header: ./c_outputs/
|
<filename>examples/heart/main.yaml
name: heart
system:
outputs:
SA_v: REAL
RA_v: REAL
OS_v: REAL
Fast_v: REAL
AV_v: REAL
His_v: REAL
RBB_v: REAL
RVA_v: REAL
RV_v: REAL
definitions:
Cell: !include cell.yaml
Path: !include path.yaml
instances:
!include cells.yaml
... |
variables:
build_num: $(Build.BuildNumber)
jobs:
- job: PyPi_Linux
pool:
vmImage: 'ubuntu-18.04'
steps:
- script: |
python -m pip install wheel twine
displayName: 'Install wheel+twine'
- script: |
docker pull quay.io/pypa/manylinux2010_x86_64
docker build -t pybfms .
displayNa... |
# Copyright 2021 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
---
address:
# Snitch: cl_peripherals + 0x40
barrier_reg: 0x120040
cluster_base_hartid: 0x40000040
cluster_id: 0x40000050
cluster_num: 0x4000... |
# .goreleaser.yml
# Build customization
builds:
- main: ./cmd/riscv-as/main.go
binary: riscv-as
goos:
- windows
- darwin
- linux
- main: ./cmd/riscv-tb/main.go
binary: riscv-tb
goos:
- windows
- darwin
- linux
archive:
files:
- examples/*
|
---
name: template
board: boards/cora07s
version: 0.1.1
cores:
- fpga/cores/axi_ctl_register_v1_0
- fpga/cores/dna_reader_v1_0
- fpga/cores/axi_sts_register_v1_0
memory:
- name: control
offset: '0x60000000'
range: 4K
- name: status
offset: '0x50000000'
range: 4K
- name: led0
offset: '... |
hwpe-ctrl:
commit: ec068eb
hwpe-stream:
group: bigcola317
commit: mac-single-tcdm
tech_cells_generic:
commit: b35652608124b7ea813818b14a00ca76edd7599d
|
<filename>Gathered CTF writeups/2017-06-17-googlectf/a7_gee_cue_elle/app.yaml
service: anon2-lmuwucba5we9gi5a
runtime: python27
api_version: 1
threadsafe: true
handlers:
- url: /login
script: main.app
- url: /
static_files: index.html
upload: index.html
- url: /(.+)
static_files: \1
upload: .*[.](?!py$).*
... |
theme: jekyll-theme-dinky
title: RV12 RISC-V CPU Core
description: Single-issue, single-core RV32I, RV64I compliant RISC-V CPU
show_downloads: true
show_license: true
license: Non-Commercial License
|
%YAML 1.2
---
Motor:
one_rotation_pulse: 630 # 1回転あたりのロータリーエンコーダのパルス数
one_rotation_dist: 0.233 # 1回転で進む距離(m)
tire_tread: 0.17 # タイヤ間の距離(m)
|
<reponame>mfkiwl/snitch
package:
name: lowrisc_prim
description: "lowRISC RTL primitives"
authors: ["lowRISC Contributors"]
# Used for implementation of primitive cells
dependencies:
common_cells: {path: ../../pulp_platform_common_cells}
sources:
# Patched in
- prim_pulp_platform/prim_flop_2sync.sv
# Level 0
... |
# Run in container-based environment
sudo: required
dist: trusty
group: edge # Add this
git:
submodules: false
# Using the precompiled toolchain from docker
services:
- docker
# define test
env:
global:
- DOCKER_TOP=/opt/lowrisc
- DOCKER_TAG=rocket-v1.0
matrix:
- CONFIG=LoRCDefaultConfig TEST... |
<gh_stars>100-1000
package:
name: axi_slice
dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.7.4 }
sources:
- src/axi_single_slice.sv
- src/axi_ar_buffer.sv
- src/axi_aw_buffer.sv
- src/axi_b_buffer.sv
- src/axi_r_buffer.sv
- src/axi_slice.sv
- src/a... |
<filename>src_files.yml<gh_stars>1-10
apb_event_unit:
incdirs: [
./include/,
]
files: [
apb_event_unit.sv,
generic_service_unit.sv,
sleep_unit.sv,
]
|
language: python
install:
- pip install tox
script:
- tox -e $BUILD_NAME
matrix:
include:
- env: BUILD_NAME=py27-unit
python: '2.7'
- env: BUILD_NAME=py33-unit
python: '3.3'
- env: BUILD_NAME=py34-unit
python: '3.4'
- env: BUILD_NAME=py35-unit
python: '3.5'
- env: BUILD_NAME=py36-unit
... |
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