KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

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<reponame>ikwzm/merge_sorter --- input_file : 03_word_compare.akd output_file : ../03_word_compare.md image_url : "Fig.1 Word Compare" : "image/03_word_compare_1.jpg" link_list : - id : "「はじめに」" title: "「VHDL で書くマージソーター(はじめに)」" url : "./01_introduction.md" - id : "「ワードの定義」" title: "「VHDL で書くマ...
<reponame>accuminium/axi name: Build and deploy documentation on: push: branches-ignore: - gh-pages # deployment target branch (this workflow should not exist on that branch anyway) - v # such branch names conflict with tags tags: - v pull_request: branches-ignore: - g...
<filename>testing/snort/execution/cfgs/snort_cfg.yml<gh_stars>10-100 ssh: user: ncshy key: '~/.ssh/id_rsa_tofino' port: 22 params: rate: '{0.args.rate}' pktgen_template: ./pktgen_template.lua n_set_pkts: 5000 n_get_pkts: 45000 n_total_pkts: 10000 key_space: 10000 zipf_coef: 1.00...
<filename>scripts/fox_hoplite_multicast/FirmwareConfig.yaml --- foxFirmware: name: firmware_fox_hoplite_multicast memory_size: 3072 resultFirmware: name: firmware_fox_hoplite_multicast_result memory_size: 4096
<gh_stars>1-10 name: PoC Default on: push: paths: - '.github/workflows/poc_default.yml' - 'poc/**' - '!poc/README.md' defaults: run: working-directory: poc jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Use Node.js 12.x uses: actions/s...
# Human readable task name name: Cpp # Long form description. description: \|+ We have this program's source code, but it uses a strange DRM solution. Can you crack it? # The flag flag: CTF{pr3pr0cess0r_pr0fe5sor} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: reversing # === the fields bel...
package: name: apb authors: - "<NAME> <<EMAIL>>" # current maintainer - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.2 } export_include_dirs: - include sources: # Source files grouped in levels. Fil...
<gh_stars>10-100 # Copyright 2021 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 package: name: tcdm_adapter dependencies: common_cells: { path: "../../deps/common_cells" } axi: { path: "../../deps/a...
name: Update Specification on: [push] jobs: latex-job: runs-on: ubuntu-latest name: Specification Document Compilation steps: - uses: actions/checkout@v1 - name: Compilation uses: vinay0410/tectonic-action@master env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} ...
<filename>documentation/metadata/ashet.yaml --- title: Ashet Hardware Architecture author: - Felix "xq" Queißner date: Jan 19, 2021 abstract: The document describes the system architecture of the Ashet Home Computer.
<reponame>mfkiwl/snitch package: name: apb_timer authors: ["<NAME> <<EMAIL>>"] sources: # Level 0 - src/timer.sv # Level 1 - src/apb_timer.sv
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
--- # Copyright 2021 Datum Technology Corporation # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ######################################################################################################################## # Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file e...
comms_top: before_script: - cd projects/comms_top && ls /non-free stage: synthesis script: - PATH=$XILINX_VIVADO/bin:$PATH make comms_top.bit artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME" expire_in: 1 week paths: - projects/comms_top/comms_top.bit comms_top_run: stage: program...
<gh_stars>0 language: python python: - 2.7 - 3.7 sudo: required dist: xenial notifications: slack: silab-bonn:nU3pnaHN3RJ6WRFrfjec9vPM email: - <EMAIL> - <EMAIL> - <EMAIL> before_install: # Install cocotb and iverilog for interface test # - git clone https://github.com/potentialventures/cocotb...
<filename>hw/ip/snitch_cluster/Bender.yml # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_cluster authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: axi: {path: ../....
datamover: vlog_opts: [ +nowarnSVCHK, -suppress 2275, -L hwpe_stream_lib, -L hwpe_ctrl_lib, -L hci_lib, ] files: [ rtl/datamover_package.sv, rtl/datamover_streamer.sv, rtl/datamover_engine.sv, rtl/datamover_top.sv, ]
<gh_stars>10-100 --- # Wait a few clk cycles for core to go idle - {opcode: wait, addr: 0, data: 0} - {opcode: wait, addr: 0, data: 0} # Enable all interrupts - {opcode: write, addr: 0x00000004, data: 0x00000007} # Enable kmac mode, cSHAKE, 128-bit kstrength, no endian swap - {opcode: write, addr: 0x00000010, data: 0...
<filename>third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/Bender.yml package: name: fpu_div_sqrt_mvp dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.13.1 } sources: # Level 0 - hdl/defs_div_sqrt_mvp.sv - hdl/iteration_div_sqrt_mvp.sv # Level 1 - h...
language: scala scala: 2.11.7 notifications: slack: rooms: - plasticine-arch:kRp0KfrygHiq2wCMrcgMogBW#regression email: recipients: <EMAIL> on_success: change # default: change on_failure: always # default: always # branches: # only: # - fpga # - master install: - wget https://www.ver...
name: RTL-CI on: push: branches: [main] pull_request: branches: [main] schedule: [cron: "0 /24 * *"] jobs: build-and-simulate: name: Build and Simulate runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: olafurpg/setup-scala@v10 with: java-vers...
language: scala scala: - 2.11 sudo: false cache: directories: $HOME/.ivy2 $INSTALL_DIR git: depth: 10 sbt_args: -Dsbt.log.noformat=true env: global: INSTALL_DIR=$TRAVIS_BUILD_DIR/install VERILATOR_ROOT=$INSTALL_DIR PATH=$PATH:$VERILATOR_ROOT/bin:$TRAVIS_BUILD_DIR/utils/bin install: # ...
name: fw-ci on: push: branches: - develop jobs: fw-release: runs-on: ubuntu-latest steps: - name: Git Checkout uses: actions/checkout@v2 - name: Build fw/all run: \| cmake -GNinja -Bbuild cmake --build build --target fw/all container: nupole/hdl-t...
<gh_stars>0 --- - hosts: packet-generator gather_facts: False tasks: - name: stop carbon metrics collection command: "killall pktgen_carbon.bash" ignore_errors: True tags: - generator
version: '3.3' services: controller: image: ${CONTROL_TAG} volumes: - ./configs:/configs - ./logs:/ping_controller/logs user: "${UID}:${GUID}" network_mode: "host" stdin_open: true # -i flag tty: true # -t flag server: image: ${SERVER_TAG} user: "${UID}:${GUID}" ...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
<reponame>RasooulFaraji/Simple-10GbE-RUDP-KCU105-Example # ---------------------------------------------------------------------------- # This file is part of the `Simple-10GbE-RUDP-KCU105-Example`. It is subject to # the license terms in the LICENSE.txt file found in the top-level directory # of this distribution and ...
%YAML 1.2 --- Pedestrian: pedestrian_haar_like_cascade_file_path: "/data/ConstraintGenerator/PedestrianDetector/HaarLike/pedestrian_cascade.xml" y_of_top_of_detection_area: 40 # 歩行者認識の対象とする画像領域のy方向の下限 y_of_bottom_of_detection_area: 220 # 歩行者認識の対象とする画像領域のy方向の上限 x_of_left_of_detection_area: 200 # ...
<filename>rtl/tb/src_files.yml<gh_stars>1-10 tb: targets: [ rtl ] files: [ riscv_pkg.sv, jtag_pkg.sv, pulp_tap_pkg.sv, tb_clk_gen.sv, tb_fs_handler.sv, dpi_models/dpi_models.sv, tb_driver/tb_driver.sv, tb_pulp.sv, SimJTAG.sv, SimDTM.sv, ] vlog_opts : [ -L riscv_...
<reponame>StanfordVLSI/dragonphy2<gh_stars>10-100 # Adapted from Garnet and ButterPHY name: mdll_r1 commands: - \| mkdir -p outputs tar -xzvf /home/sjkim85/dragonphy_tarballs/mdll_r1_top-latest.tar.gz -C outputs mv outputs// outputs/ python comment_fill_bound_tap.py outputs/mdll_r1_top.lvs.v mv...
# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: clint description: RISC-V Core-local Interrupt Controller authors: [<NAME> <<EMAIL>>] dependencies: register_interface: {path: ../../ven...
<gh_stars>0 - Global: Print : true - Library: Name : pipework Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../qconv-strip-vhdl/PipeWork/src/"] Use : ["SDPRAM(XILINX_ULTRASCALE_AUTO_SELECT)"] - Library: Name : qconv Format : "ad...
# Copyright 2019 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 fpnew: incdirs: [ ../common_cells/include, ] files: [ src/fpnew_pkg.sv, src/fpnew_cast_multi.sv, src/fpnew_classifier.sv, src/fpnew_di...
<reponame>Datum-Technology-Corporation/core-v-mcu<gh_stars>10-100 core-v-mcu-soc: incdirs: [ ../includes, include, ../vendor/pulp_platform_axi/include ] files: [ soc/pkg_soc_interconnect.sv, soc/axi64_2_lint32_wrap.sv, soc/lint_2_axi_wrap.sv, soc/contiguous_crossbar.sv, soc/interle...
"at200": arch: "artix7_200t" device_family: "xc7a200t" device_name: "fig1" device_speed: "ffg1156-1" device: "xc7a200t-fig1-roi-virt" board: "nexys_video" timeout: 200
<reponame>DeepFlyingSky/circt name: "Request review from code owner" on: pull_request_target: branches: [ main ] jobs: # Automatically request reviews from the code owner identified in a set of # JSON files in codeowners/. request_reviewer: name: "Request review from code owner" runs-on: ubuntu-18....
before_script: - echo start testing $CI_PROJECT_NAME. build_on_host: tags: - aisw script: - source /opt/rh/devtoolset-9/enable - ./cmake.sh --clean build_for_microblaze: tags: - aisw script: - source /var/lib/docker/scratch/gitlab-runner/build/mb_sdk/environment-setup...
--- name: led-blinker board: boards/zedboard version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers: - l...
steps: - label: "test" command: \| # set up environment source /cad/modules/tcl/init/bash module load base xcelium/19.03.003 export ANASYMOD_TARGET=sim_xcelium printenv # set up Python environment /usr/local/miniconda/bin/python3.7 -m venv venv source venv/bin/activ...
--- version: 2.1 jobs: build-and-test: machine: image: ubuntu-2004:202101-01 resource_class: arm.medium environment: RELEASE: https://github.com/modula3/cm3/releases/download/d5.11.4/cm3-boot-AMD64_LINUX-d5.11.4.tar.xz CM3_TARGET: ARM64_LINUX steps: - run: name: Instal...
<reponame>mfkiwl/Bedrock # Defs are made available as Verilog defines # Params are made available as Verilog localparams and included in ROM metadata marble_mini: defs: MARBLE_MINI: 1 USE_I2CBRIDGE: 1 MMC_CTRACE: 1 USE_GTPCLK: 1 params: carrier: "Marble Mini" car...
metadata: name: axil_addrdec fields: - address: 0x0---- name: M_00 behavior: axi flatten: record - address: 0x1---- name: M_01 behavior: axi flatten: record - address: 0x2---- name: M_02 behavior: axi flatten: record - address: 0x3---- name: M_03 behavior: axi ...
<reponame>justin371/rules_verilog<gh_stars>0 name: Run Bazel Tests on: [push] jobs: bazel-tests: name: Bazel Tests runs-on: ubuntu-latest steps: - name: checkout uses: actions/checkout@main - name: install-bazelisk uses: vsco/bazelisk-action@master with: ...
<reponame>letrend/neopixel_fpga sudo: required dist: trusty language: generic notifications: email: on_success: always on_failure: always env: - ROS_DISTRO=indigo before_script: - export CI_SOURCE_PATH=$(pwd) - export REPOSITORY_NAME=${PWD##*/} - if [ ! "$ROS_PARALLEL_JOBS" ]; then export ROS_PARALLEL...
<filename>.github/workflows/riscv-arch-test.yml # Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version name: 'riscv-arch-test' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest strategy: fail-fast: false matrix: suite: - I - C ...
<reponame>Calculasians/HDC-Sensor-Fusion-Research power.inputs.waveforms_meta: "append" power.inputs.waveforms: - "/tools/B/daniels/hammer-tsmc28/build/sim-par-rundir/svm.vcd" power.inputs.database: "/tools/B/daniels/hammer-tsmc28/build/par-rundir/latest" power.inputs.tb_name: "SVM_tb" power.inputs.saifs_meta: "ap...
--- name: mars_zx3_template board: boards/mars_zx3 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers:...
<reponame>thirono/basil # Device description for the Agilent Technologies E3644A Power Supply. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are imlemented here. identifier: Agilent Technologies,E3644A get_voltage: MEAS:VOLT:DC? get_current: MEAS:CURR:DC? set_enab...
identifier: rudolv name: RudolV RISC-V Soft-CPU type: mcu arch: riscv32 toolchain: - zephyr testing: ignore_tags: - net - bluetooth
hwpe-stream: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/hwpe_stream_package.sv, rtl/hwpe_stream_interfaces.sv, rtl/hwpe_stream_addressgen.sv, rtl/hwpe_stream_fifo_earlystall_sidech.sv, rtl/hwpe_stream_fifo_earlystall.sv, rtl/hwpe_stream_fifo_scm.sv, rtl/hwp...
name: Coverage # Skip this step for now since the upload action seems to be broken: # https://github.com/codecov/codecov-action/issues/37 on: push: branches-ignore: - '**' jobs: test: runs-on: ubuntu-latest container: image: xd009642/tarpaulin options: --security-opt seccomp=un...
<reponame>NicoBaumann454/alsp.net.api ### YamlMime:ManagedReference items: - uid: alps_.net_api.SimplePASSElement commentId: T:alps_.net_api.SimplePASSElement id: SimplePASSElement parent: alps_.net_api children: [] langs: - csharp - vb name: SimplePASSElement nameWithType: SimplePASSElement fullNam...
# Builds glb_tile but not from scratch, uses pre-cached gold collateral agents: { jobsize: "hours" } ############################################################################## # Use this to test a specific branch/commit: # Add to env: # NOV11: ee214ef77b827f969e4b5f056f5d866cf391be7a # Add to commands: # - pwd;...
package: name: fwperiph-dma version: None deps: - name: fwprotocol-defs url: http://github.com/Featherweight-IP/fwprotocol-defs.git type: raw dev-deps: - name: fwprotocol-defs url: http://github.com/Featherweight-IP/fwprotocol-defs.git type: raw ...
--- input_file : 11_merge_sort_core_2.akd output_file : ../11_merge_sort_core_2.md image_url : "Fig.1 マージソートコアの構成" : "image/11_merge_sort_core_2_1.jpg" "Fig.2 4-way マージソートツリーによる16ワードデータのソート例" : "image/11_merge_sort_core_2_2.jpg" "Fig.3 最初のパスのDMA転送(ストリーム入力無し)" ...
<reponame>nicolasruscher/Artemis version: '2' services: artemis-app: image: artemis environment: - _JAVA_OPTIONS=-Xmx512m -Xms256m - SPRING_PROFILES_ACTIVE=prod,swagger - MANAGEMENT_METRICS_EXPORT_PROMETHEUS_ENABLED=true - SPRING_DATASOURCE_URL=jdbc:my...
description: >- NSID 2020 final version of failover data and plotting scripts. Bitstreams are the same as the corresponding e2e experiments experiment: failover repositories: P4Boosters: 5ac827ee files: documentation.md: failover_readme.md raw_data: failover_output_6/ power_data.pickle: analy...
<reponame>SigmaX-ai/bolson<gh_stars>1-10 name: Documentation on: push: branches: - master pull_request: paths: - 'doc/' - 'src/' - 'Doxyfile' - 'README.md' jobs: book: name: Book runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Install mdbook ...
verilog_sources: sim_ctrl: files: './sim_ctrl.*v' functional_models: filter: files: './my_filter.py'
<reponame>Malcolmnixon/MotionFpga<filename>fpga/common/vhdltest.yaml files: # Source files - utility/source/blink.vhd - utility/source/clk_div_n.vhd - utility/source/edge_detect.vhd - utility/source/pwm.vhd - utility/source/sdm.vhd - utility/source/quad_decoder.vhd - utility/source/delay_line.vhd - utility/sou...
# Check NEORV32 software framework and test processor name: Processor on: push: branches: - main paths: - 'rtl/' - 'sw/' - 'sim/' pull_request: branches: - main paths: - 'rtl/' - 'sw/' - 'sim/' workflow_dispatch: jobs: Linux: runs-on: ubuntu-l...
# Copyright 2021 OpenHW Group # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run functional regression checks name: ci on: [push, pull_request] jobs: ####### # ISA # ####### base-isa: name: Base ISA Tests runs-on: ubuntu-latest en...
format_version: v1.0 type: UniqueComponent attributes: {id: FreeRTOS} children: - type: Symbols children: - type: Integer attributes: {id: FREERTOS_CPU_CLOCK_HZ} children: - type: Values children: - type: Dynamic attributes: {id: FreeRTOS, value: '48000000'} - type: Boolean att...
# Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Azure template for installing dependencies from various package managers, # necessary for building, testing, and packaging OpenTitan. # # This template executes: # - apt-...
<reponame>hito0512/Vitis-AI # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable ...
<filename>circle.yml machine: services: - docker dependencies: pre: - docker pull dhiru/fedora - docker run --name fedora -v /home/ubuntu:/base -i -t dhiru/fedora /base/JohnTheRipper/src/CircleCI-MinGW.sh general: artifacts: - /home/ubuntu/builds
- src: docker.io/calico/node dst: asia.gcr.io/fighting-falcon/calico/node tags: ["v3.12.0"] - src: docker.io/mvance/unbound dst: registry.f110.dev/mirror/unbound tags: ["1.9.5"] - src: docker.io/goharbor/harbor-db dst: asia.gcr.io/fighting-falcon/goharbor/harbor-db tags: ["v1.10.0", "v2.1.1"] - src: ghcr.io...
steps: - label: "test" command: \| # set up environment source /etc/environment export FPGA_BOARD=xilinx.com:zc702:part0:1.4 export FPGA_PART=xc7z020clg484-1 export TAP_CORE_LOC=/tools/synopsys/syn/L-2016.03-SP5-5/dw/syn_ver/tap_core.edf printenv # create virtual environm...
configMapGenerator: - name: xss-bot-healthcheck-config files: - env generatorOptions: disableNameSuffixHash: true labels: type: generated annotations: note: generated
<filename>rtl/apb_gpio/Bender.yml package: name: apb_gpio authors: [ "<NAME> <<EMAIL>>" ] sources: - rtl/apb_gpio.sv
<reponame>fabianschuiki/sv-tests name: sv-test-env channels: - symbiflow - pkgw-forge - conda-forge dependencies: # - iverilog # - moore # - odin_ii # - slang # - surelog # - sv-parser # - tree-sitter-verilog # - verible # - verilator # - yosys # - zachjs-sv2v - python=3.7 - pip - pip: ...
name: Windows on: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: Matrix: runs-on: ubuntu-latest outputs: matrix: ${{ steps.generate.outputs.matrix }} steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '🔧 Generate examples matrix' id:...
working_dir : # Module data will be written to this path. If not given, use path of this file. Default: not given / empty dut : dut_mio.yaml # DUT hardware configuration (.yaml). Change to dut_mio_gpac.yaml for GPAC support. dut_configuration : dut_configuration_mio.yaml # DUT init configuration (.yaml). Change ...
# For Windows based CI environment: matrix: # For Python versions available on Appveyor, see # https://www.appveyor.com/docs/windows-images-software/#python - BUILD_NAME: py38-unit PYTHON: "C:\\Python38" - BUILD_NAME: py38-lint PYTHON: "C:\\Python38" - BUILD_NAME: py38-docs ...
name: Implementation on: push: paths: - 'setups/' - 'rtl/' pull_request: paths: - 'setups/' - 'rtl/' schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: Matrix: runs-on: ubuntu-latest outputs: matrix: ${{ steps.generate.outputs.matrix }} steps: ...
<filename>.github/workflows/fixed_point_default.yml name: Fixed Point Default on: push: paths: - 'fixed_point/**' - '!fixed_point/README.md' - '.github/workflows/fixed_point_default.yml' defaults: run: working-directory: fixed_point shell: bash jobs: cppcheck: runs-on: ubuntu-20.04 ...
name: sim-gl-compile parameters: sdf: False PWR_AWARE: False tool: "XCELIUM" num_glb_tiles: 16 commands: - bash run_sim.sh inputs: - adk - design.vcs.v - design.vcs.pg.v - header - design.sdf - glb_tile.vcs.v - glb_tile.vcs.pg.v - glb_tile.sdf - glb_tile_sram.v - glb_tile_sram_pwr.v ou...
<filename>documentation/metadata/an001.yaml --- title: The SPU Assembly Language author: - Felix "xq" Queißner date: April 28, 2020 abstract: \| The highly flexible nature of the instruction set of the SPU Mark II makes it different to put all possible instructions into useful mnemonics. So the assembly langua...
<filename>examples/mercury_pe1_zx1/dma_example/config.yml --- name: PE1_XZ1_7030_DMA board: boards/mercury_zx1_pe1 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/tlast_gen_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000...
<filename>vlog_netlist/fll/fll_design/rtl/configure.yml name: rtl commands: - \| mkdir -p outputs cp -r $VLOG_HOME/mux_4t1 ./outputs cat "./outputs/mux_4t1/qr_4t1_mux_top.sv" "./outputs/mux_4t1/qr_mux_fixed.sv" "./outputs/mux_4t1/ff_c.sv" "./outputs/mux_4t1/tx_inv.sv" > "./outputs/design.v" python gen...
--- name: phase-noise-analyzer board: boards/alpha250 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/axis_constant_v1_0 - fpga/cores/latched_mux_v1_0 - fpga/cores/edge_detector_v1_0 - fpga/cores/comparator_v1_0 - fpg...
## Copyright lowRISC contributors. ## Licensed under the Apache License, Version 2.0, see LICENSE for details. ## SPDX-License-Identifier: Apache-2.0 Device: rv32imc Vendor: opentitan ISA: RV32IMC misa: implemented: True MXL: range: rangelist: [[1]] mode: Unchanged Extensions: bitmask: ...
<reponame>recogni/cluster_interconnect package: name: cluster_interconnect dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v1.13.0 } sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only d...
udma_i2s: files: [ rtl/i2s_clk_gen.sv, rtl/i2s_rx_channel.sv, rtl/i2s_tx_channel.sv, rtl/i2s_ws_gen.sv, rtl/i2s_clkws_gen.sv, rtl/i2s_txrx.sv, rtl/cic_top.sv, rtl/cic_integrator.sv, rtl/cic_comb.sv, rtl/pdm_top.sv, rtl/udma_i2s_reg_if.sv, rtl/udma_i2s_top.sv, ]
<gh_stars>1-10 builds: build1: test_discoverer: type: uvm_test attr: test_dir: $JVS_PRJ_HOME/build1_testcases build2:
name: CI/Console on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: acti...
on: - push name: Linux CI jobs: build: name: Build (Ubuntu) runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 with: submodules: true - name: Get LLVM and Bison run: \| sudo apt-get install llvm-11-dev bison echo "LLVM_CONFIG=llvm-config-...
<gh_stars>1-10 KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN50x50.json KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN50x50_weights.h5 InputData: /media/data/projects/landsat_soil_classifier/data/Landsat_x_test.dat OutputPredictions: /media/data/projects/landsat_soil_classifier/d...
<filename>mie-workflows/vod_translate_workflow.yaml AWSTemplateFormatVersion: '2010-09-09' Description: "Media Insights Engine - Workflow to run VOD transcribe and translate application" Parameters: WorkflowCustomResourceArn: Type: String Description: "ARN of the Media Insights custom resource that handles ...
<reponame>lrsb/digitallogicdesign-vhdl-2019<gh_stars>0 language: python addons: apt: update: true install: - sudo apt-get install -y gnat - git clone https://github.com/ghdl/ghdl.git - mkdir $TRAVIS_BUILD_DIR/ghdl/build - cd $TRAVIS_BUILD_DIR/ghdl/build - $TRAVIS_BUILD_DIR/ghdl/configure --prefix=$TRA...
#this is a example of how ENC ip is used in our yaml IR_RECIEVE: IP: __IR_RECIEVE CMD: IRR ir_sda: PIN: A34 DIRECTION: in ir_recieve_status: PIN: A35 DIRECTION: out
<filename>Bender.yml package: name: per2axi dependencies: axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.3 } sources: - src/per2axi_busy_unit.sv - src/per2axi_req_channel.sv - src/per2axi_res_channel.sv - src/per2axi.sv
name: tiny-mlperf-fifo-env-take-2 channels: - conda-forge dependencies: - python=3.7 - pip - pip: - jupyter - pydot - graphviz - git+https://github.com/nicologhielmetti/hls4ml.git@fifo_depth_opt#egg=hls4ml[profiling] - matplotlib - numpy - PyYAML - scikit-learn - tensorflow ...
<filename>Bender.yml package: name: fpu_interco authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.4 } riscv: { git: "<EMAIL>:AlSaqr-platform/riscv_nn.git", rev: "9...
<filename>.github/workflows/atomsim-atombones.yml name: atomsim-atombones on: push: branches: [ main ] pull_request: branches: [ main ] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: build: name: atomsim-atombones runs-on: ubuntu-20.04 steps: ...
<reponame>SubjeBilisim/anasymod analog_ctrl_inputs: in_: abspath: 'tb_i.in_' range: 10 init_value: 0.0 analog_ctrl_outputs: out: abspath: 'tb_i.out' range: 10
<filename>hw/vendor/pulp_platform_apb_uart/Bender.yml package: name: apb_uart authors: [ "<NAME>", "<NAME>" ] sources: - src/slib_clock_div.sv - src/slib_counter.sv - src/slib_edge_detect.sv - src/slib_fifo.sv - src/slib_input_filter.sv - src/slib_input_sync.sv - src/slib_mv_filter.sv...
name: ICan'tBelieveIt'sNotCrypto # Long form description. description: \|+ Every journey starts with a single step Guest challenge by TethysSvensson # The flag flag: CTF{5t3p_by_st3p_I_m4k3_my_w4y} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: misc # === the fields below will be filled b...
<reponame>bver/GERET<gh_stars>1-10 --- algorithm: class: ParetoGPSimplified population_size: 800 archive_size: 200 generations_per_cascade: 10 mutation_probability: 0.00 shorten_individual: true tournament_size: 10 init: method: ramped # grow or full or ramped sensible_depth: 7 termina...
<gh_stars>0 package: name: fw-wishbone-interconnect version: None deps: - name: fwprotocol-defs url: https://github.com/featherweight-ip/fwprotocol-defs.git dev-deps: - name: fwprotocol-defs url: https://github.com/featherweight-ip/fwprotocol-defs.git - name: ...

<reponame>ikwzm/merge_sorter --- input_file : 03_word_compare.akd output_file : ../03_word_compare.md image_url : "Fig.1 Word Compare" : "image/03_word_compare_1.jpg" link_list : - id : "「はじめに」" title: "「VHDL で書くマージソーター(はじめに)」" url : "./01_introduction.md" - id : "「ワードの定義」" title: "「VHDL で書くマ...

<reponame>accuminium/axi name: Build and deploy documentation on: push: branches-ignore: - gh-pages # deployment target branch (this workflow should not exist on that branch anyway) - v** # such branch names conflict with tags tags: - v** pull_request: branches-ignore: - g...

<filename>testing/snort/execution/cfgs/snort_cfg.yml<gh_stars>10-100 ssh: user: ncshy key: '~/.ssh/id_rsa_tofino' port: 22 params: rate: '{0.args.rate}' pktgen_template: ./pktgen_template.lua n_set_pkts: 5000 n_get_pkts: 45000 n_total_pkts: 10000 key_space: 10000 zipf_coef: 1.00...

<filename>scripts/fox_hoplite_multicast/FirmwareConfig.yaml --- foxFirmware: name: firmware_fox_hoplite_multicast memory_size: 3072 resultFirmware: name: firmware_fox_hoplite_multicast_result memory_size: 4096

<gh_stars>1-10 name: PoC Default on: push: paths: - '.github/workflows/poc_default.yml' - 'poc/**' - '!poc/README.md' defaults: run: working-directory: poc jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Use Node.js 12.x uses: actions/s...

# Human readable task name name: Cpp # Long form description. description: |+ We have this program's source code, but it uses a strange DRM solution. Can you crack it? # The flag flag: CTF{pr3pr0cess0r_pr0fe5sor} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: reversing # === the fields bel...

package: name: apb authors: - "<NAME> <<EMAIL>>" # current maintainer - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.2 } export_include_dirs: - include sources: # Source files grouped in levels. Fil...

<gh_stars>10-100 # Copyright 2021 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 package: name: tcdm_adapter dependencies: common_cells: { path: "../../deps/common_cells" } axi: { path: "../../deps/a...

name: Update Specification on: [push] jobs: latex-job: runs-on: ubuntu-latest name: Specification Document Compilation steps: - uses: actions/checkout@v1 - name: Compilation uses: vinay0410/tectonic-action@master env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} ...

<filename>documentation/metadata/ashet.yaml --- title: Ashet Hardware Architecture author: - Felix "xq" Queißner date: Jan 19, 2021 abstract: The document describes the system architecture of the Ashet Home Computer.

<reponame>mfkiwl/snitch package: name: apb_timer authors: ["<NAME> <<EMAIL>>"] sources: # Level 0 - src/timer.sv # Level 1 - src/apb_timer.sv

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

--- # Copyright 2021 Datum Technology Corporation # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ######################################################################################################################## # Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file e...

comms_top: before_script: - cd projects/comms_top && ls /non-free stage: synthesis script: - PATH=$XILINX_VIVADO/bin:$PATH make comms_top.bit artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME" expire_in: 1 week paths: - projects/comms_top/comms_top.bit comms_top_run: stage: program...

<gh_stars>0 language: python python: - 2.7 - 3.7 sudo: required dist: xenial notifications: slack: silab-bonn:nU3pnaHN3RJ6WRFrfjec9vPM email: - <EMAIL> - <EMAIL> - <EMAIL> before_install: # Install cocotb and iverilog for interface test # - git clone https://github.com/potentialventures/cocotb...

<filename>hw/ip/snitch_cluster/Bender.yml # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_cluster authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: axi: {path: ../....

datamover: vlog_opts: [ +nowarnSVCHK, -suppress 2275, -L hwpe_stream_lib, -L hwpe_ctrl_lib, -L hci_lib, ] files: [ rtl/datamover_package.sv, rtl/datamover_streamer.sv, rtl/datamover_engine.sv, rtl/datamover_top.sv, ]

<gh_stars>10-100 --- # Wait a few clk cycles for core to go idle - {opcode: wait, addr: 0, data: 0} - {opcode: wait, addr: 0, data: 0} # Enable all interrupts - {opcode: write, addr: 0x00000004, data: 0x00000007} # Enable kmac mode, cSHAKE, 128-bit kstrength, no endian swap - {opcode: write, addr: 0x00000010, data: 0...

<filename>third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/Bender.yml package: name: fpu_div_sqrt_mvp dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.13.1 } sources: # Level 0 - hdl/defs_div_sqrt_mvp.sv - hdl/iteration_div_sqrt_mvp.sv # Level 1 - h...

language: scala scala: 2.11.7 notifications: slack: rooms: - plasticine-arch:kRp0KfrygHiq2wCMrcgMogBW#regression email: recipients: <EMAIL> on_success: change # default: change on_failure: always # default: always # branches: # only: # - fpga # - master install: - wget https://www.ver...

name: RTL-CI on: push: branches: [main] pull_request: branches: [main] schedule: [cron: "0 */24 * * *"] jobs: build-and-simulate: name: Build and Simulate runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: olafurpg/setup-scala@v10 with: java-vers...

language: scala scala: - 2.11 sudo: false cache: directories: $HOME/.ivy2 $INSTALL_DIR git: depth: 10 sbt_args: -Dsbt.log.noformat=true env: global: INSTALL_DIR=$TRAVIS_BUILD_DIR/install VERILATOR_ROOT=$INSTALL_DIR PATH=$PATH:$VERILATOR_ROOT/bin:$TRAVIS_BUILD_DIR/utils/bin install: # ...

name: fw-ci on: push: branches: - develop jobs: fw-release: runs-on: ubuntu-latest steps: - name: Git Checkout uses: actions/checkout@v2 - name: Build fw/all run: | cmake -GNinja -Bbuild cmake --build build --target fw/all container: nupole/hdl-t...

<gh_stars>0 --- - hosts: packet-generator gather_facts: False tasks: - name: stop carbon metrics collection command: "killall pktgen_carbon.bash" ignore_errors: True tags: - generator

version: '3.3' services: controller: image: ${CONTROL_TAG} volumes: - ./configs:/configs - ./logs:/ping_controller/logs user: "${UID}:${GUID}" network_mode: "host" stdin_open: true # -i flag tty: true # -t flag server: image: ${SERVER_TAG} user: "${UID}:${GUID}" ...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

<reponame>RasooulFaraji/Simple-10GbE-RUDP-KCU105-Example # ---------------------------------------------------------------------------- # This file is part of the `Simple-10GbE-RUDP-KCU105-Example`. It is subject to # the license terms in the LICENSE.txt file found in the top-level directory # of this distribution and ...

%YAML 1.2 --- Pedestrian: pedestrian_haar_like_cascade_file_path: "/data/ConstraintGenerator/PedestrianDetector/HaarLike/pedestrian_cascade.xml" y_of_top_of_detection_area: 40 # 歩行者認識の対象とする画像領域のy方向の下限 y_of_bottom_of_detection_area: 220 # 歩行者認識の対象とする画像領域のy方向の上限 x_of_left_of_detection_area: 200 # ...

<filename>rtl/tb/src_files.yml<gh_stars>1-10 tb: targets: [ rtl ] files: [ riscv_pkg.sv, jtag_pkg.sv, pulp_tap_pkg.sv, tb_clk_gen.sv, tb_fs_handler.sv, dpi_models/dpi_models.sv, tb_driver/tb_driver.sv, tb_pulp.sv, SimJTAG.sv, SimDTM.sv, ] vlog_opts : [ -L riscv_...

<reponame>StanfordVLSI/dragonphy2<gh_stars>10-100 # Adapted from Garnet and ButterPHY name: mdll_r1 commands: - | mkdir -p outputs tar -xzvf /home/sjkim85/dragonphy_tarballs/mdll_r1_top-latest.tar.gz -C outputs mv outputs/*/* outputs/ python comment_fill_bound_tap.py outputs/mdll_r1_top.lvs.v mv...

# Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: clint description: RISC-V Core-local Interrupt Controller authors: [<NAME> <<EMAIL>>] dependencies: register_interface: {path: ../../ven...

<gh_stars>0 - Global: Print : true - Library: Name : pipework Format : "add_vhdl_file sources_1 #{library_name} #{file_name}" PathList : ["../../qconv-strip-vhdl/PipeWork/src/"] Use : ["SDPRAM(XILINX_ULTRASCALE_AUTO_SELECT)"] - Library: Name : qconv Format : "ad...

# Copyright 2019 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 fpnew: incdirs: [ ../common_cells/include, ] files: [ src/fpnew_pkg.sv, src/fpnew_cast_multi.sv, src/fpnew_classifier.sv, src/fpnew_di...

<reponame>Datum-Technology-Corporation/core-v-mcu<gh_stars>10-100 core-v-mcu-soc: incdirs: [ ../includes, include, ../vendor/pulp_platform_axi/include ] files: [ soc/pkg_soc_interconnect.sv, soc/axi64_2_lint32_wrap.sv, soc/lint_2_axi_wrap.sv, soc/contiguous_crossbar.sv, soc/interle...

"at200": arch: "artix7_200t" device_family: "xc7a200t" device_name: "fig1" device_speed: "ffg1156-1" device: "xc7a200t-fig1-roi-virt" board: "nexys_video" timeout: 200

<reponame>DeepFlyingSky/circt name: "Request review from code owner" on: pull_request_target: branches: [ main ] jobs: # Automatically request reviews from the code owner identified in a set of # JSON files in codeowners/. request_reviewer: name: "Request review from code owner" runs-on: ubuntu-18....

before_script: - echo start testing $CI_PROJECT_NAME. build_on_host: tags: - aisw script: - source /opt/rh/devtoolset-9/enable - ./cmake.sh --clean build_for_microblaze: tags: - aisw script: - source /var/lib/docker/scratch/gitlab-runner/build/mb_sdk/environment-setup...

--- name: led-blinker board: boards/zedboard version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers: - l...

steps: - label: "test" command: | # set up environment source /cad/modules/tcl/init/bash module load base xcelium/19.03.003 export ANASYMOD_TARGET=sim_xcelium printenv # set up Python environment /usr/local/miniconda/bin/python3.7 -m venv venv source venv/bin/activ...

--- version: 2.1 jobs: build-and-test: machine: image: ubuntu-2004:202101-01 resource_class: arm.medium environment: RELEASE: https://github.com/modula3/cm3/releases/download/d5.11.4/cm3-boot-AMD64_LINUX-d5.11.4.tar.xz CM3_TARGET: ARM64_LINUX steps: - run: name: Instal...

<reponame>mfkiwl/Bedrock # Defs are made available as Verilog defines # Params are made available as Verilog localparams and included in ROM metadata marble_mini: defs: MARBLE_MINI: 1 USE_I2CBRIDGE: 1 MMC_CTRACE: 1 USE_GTPCLK: 1 params: carrier: "Marble Mini" car...

metadata: name: axil_addrdec fields: - address: 0x0---- name: M_00 behavior: axi flatten: record - address: 0x1---- name: M_01 behavior: axi flatten: record - address: 0x2---- name: M_02 behavior: axi flatten: record - address: 0x3---- name: M_03 behavior: axi ...

<reponame>justin371/rules_verilog<gh_stars>0 name: Run Bazel Tests on: [push] jobs: bazel-tests: name: Bazel Tests runs-on: ubuntu-latest steps: - name: checkout uses: actions/checkout@main - name: install-bazelisk uses: vsco/bazelisk-action@master with: ...

<reponame>letrend/neopixel_fpga sudo: required dist: trusty language: generic notifications: email: on_success: always on_failure: always env: - ROS_DISTRO=indigo before_script: - export CI_SOURCE_PATH=$(pwd) - export REPOSITORY_NAME=${PWD##*/} - if [ ! "$ROS_PARALLEL_JOBS" ]; then export ROS_PARALLEL...

<filename>.github/workflows/riscv-arch-test.yml # Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version name: 'riscv-arch-test' on: workflow_dispatch: jobs: build: runs-on: ubuntu-latest strategy: fail-fast: false matrix: suite: - I - C ...

<reponame>Calculasians/HDC-Sensor-Fusion-Research power.inputs.waveforms_meta: "append" power.inputs.waveforms: - "/tools/B/daniels/hammer-tsmc28/build/sim-par-rundir/svm.vcd" power.inputs.database: "/tools/B/daniels/hammer-tsmc28/build/par-rundir/latest" power.inputs.tb_name: "SVM_tb" power.inputs.saifs_meta: "ap...

--- name: mars_zx3_template board: boards/mars_zx3 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers:...

<reponame>thirono/basil # Device description for the Agilent Technologies E3644A Power Supply. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are imlemented here. identifier: Agilent Technologies,E3644A get_voltage: MEAS:VOLT:DC? get_current: MEAS:CURR:DC? set_enab...

identifier: rudolv name: RudolV RISC-V Soft-CPU type: mcu arch: riscv32 toolchain: - zephyr testing: ignore_tags: - net - bluetooth

hwpe-stream: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/hwpe_stream_package.sv, rtl/hwpe_stream_interfaces.sv, rtl/hwpe_stream_addressgen.sv, rtl/hwpe_stream_fifo_earlystall_sidech.sv, rtl/hwpe_stream_fifo_earlystall.sv, rtl/hwpe_stream_fifo_scm.sv, rtl/hwp...

name: Coverage # Skip this step for now since the upload action seems to be broken: # https://github.com/codecov/codecov-action/issues/37 on: push: branches-ignore: - '**' jobs: test: runs-on: ubuntu-latest container: image: xd009642/tarpaulin options: --security-opt seccomp=un...

<reponame>NicoBaumann454/alsp.net.api ### YamlMime:ManagedReference items: - uid: alps_.net_api.SimplePASSElement commentId: T:alps_.net_api.SimplePASSElement id: SimplePASSElement parent: alps_.net_api children: [] langs: - csharp - vb name: SimplePASSElement nameWithType: SimplePASSElement fullNam...

# Builds glb_tile but not from scratch, uses pre-cached gold collateral agents: { jobsize: "hours" } ############################################################################## # Use this to test a specific branch/commit: # Add to env: # NOV11: ee214ef77b827f969e4b5f056f5d866cf391be7a # Add to commands: # - pwd;...

package: name: fwperiph-dma version: None deps: - name: fwprotocol-defs url: http://github.com/Featherweight-IP/fwprotocol-defs.git type: raw dev-deps: - name: fwprotocol-defs url: http://github.com/Featherweight-IP/fwprotocol-defs.git type: raw ...

--- input_file : 11_merge_sort_core_2.akd output_file : ../11_merge_sort_core_2.md image_url : "Fig.1 マージソートコアの構成" : "image/11_merge_sort_core_2_1.jpg" "Fig.2 4-way マージソートツリーによる16ワードデータのソート例" : "image/11_merge_sort_core_2_2.jpg" "Fig.3 最初のパスのDMA転送(ストリーム入力無し)" ...

<reponame>nicolasruscher/Artemis version: '2' services: artemis-app: image: artemis environment: - _JAVA_OPTIONS=-Xmx512m -Xms256m - SPRING_PROFILES_ACTIVE=prod,swagger - MANAGEMENT_METRICS_EXPORT_PROMETHEUS_ENABLED=true - SPRING_DATASOURCE_URL=jdbc:my...

description: >- NSID 2020 final version of failover data and plotting scripts. Bitstreams are the same as the corresponding e2e experiments experiment: failover repositories: P4Boosters: 5ac827ee files: documentation.md: failover_readme.md raw_data: failover_output_6/ power_data.pickle: analy...

<reponame>SigmaX-ai/bolson<gh_stars>1-10 name: Documentation on: push: branches: - master pull_request: paths: - 'doc/**' - 'src/**' - 'Doxyfile' - 'README.md' jobs: book: name: Book runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Install mdbook ...

verilog_sources: sim_ctrl: files: './sim_ctrl.*v' functional_models: filter: files: './my_filter.py'

<reponame>Malcolmnixon/MotionFpga<filename>fpga/common/vhdltest.yaml files: # Source files - utility/source/blink.vhd - utility/source/clk_div_n.vhd - utility/source/edge_detect.vhd - utility/source/pwm.vhd - utility/source/sdm.vhd - utility/source/quad_decoder.vhd - utility/source/delay_line.vhd - utility/sou...

# Check NEORV32 software framework and test processor name: Processor on: push: branches: - main paths: - 'rtl/**' - 'sw/**' - 'sim/**' pull_request: branches: - main paths: - 'rtl/**' - 'sw/**' - 'sim/**' workflow_dispatch: jobs: Linux: runs-on: ubuntu-l...

# Copyright 2021 OpenHW Group # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run functional regression checks name: ci on: [push, pull_request] jobs: ####### # ISA # ####### base-isa: name: Base ISA Tests runs-on: ubuntu-latest en...

format_version: v1.0 type: UniqueComponent attributes: {id: FreeRTOS} children: - type: Symbols children: - type: Integer attributes: {id: FREERTOS_CPU_CLOCK_HZ} children: - type: Values children: - type: Dynamic attributes: {id: FreeRTOS, value: '48000000'} - type: Boolean att...

# Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Azure template for installing dependencies from various package managers, # necessary for building, testing, and packaging OpenTitan. # # This template executes: # - apt-...

<reponame>hito0512/Vitis-AI # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable ...

<filename>circle.yml machine: services: - docker dependencies: pre: - docker pull dhiru/fedora - docker run --name fedora -v /home/ubuntu:/base -i -t dhiru/fedora /base/JohnTheRipper/src/CircleCI-MinGW.sh general: artifacts: - /home/ubuntu/builds

- src: docker.io/calico/node dst: asia.gcr.io/fighting-falcon/calico/node tags: ["v3.12.0"] - src: docker.io/mvance/unbound dst: registry.f110.dev/mirror/unbound tags: ["1.9.5"] - src: docker.io/goharbor/harbor-db dst: asia.gcr.io/fighting-falcon/goharbor/harbor-db tags: ["v1.10.0", "v2.1.1"] - src: ghcr.io...

steps: - label: "test" command: | # set up environment source /etc/environment export FPGA_BOARD=xilinx.com:zc702:part0:1.4 export FPGA_PART=xc7z020clg484-1 export TAP_CORE_LOC=/tools/synopsys/syn/L-2016.03-SP5-5/dw/syn_ver/tap_core.edf printenv # create virtual environm...

configMapGenerator: - name: xss-bot-healthcheck-config files: - env generatorOptions: disableNameSuffixHash: true labels: type: generated annotations: note: generated

<filename>rtl/apb_gpio/Bender.yml package: name: apb_gpio authors: [ "<NAME> <<EMAIL>>" ] sources: - rtl/apb_gpio.sv

<reponame>fabianschuiki/sv-tests name: sv-test-env channels: - symbiflow - pkgw-forge - conda-forge dependencies: # - iverilog # - moore # - odin_ii # - slang # - surelog # - sv-parser # - tree-sitter-verilog # - verible # - verilator # - yosys # - zachjs-sv2v - python=3.7 - pip - pip: ...

name: Windows on: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: Matrix: runs-on: ubuntu-latest outputs: matrix: ${{ steps.generate.outputs.matrix }} steps: - name: '🧰 Repository Checkout' uses: actions/checkout@v2 - name: '🔧 Generate examples matrix' id:...

working_dir : # Module data will be written to this path. If not given, use path of this file. Default: not given / empty dut : dut_mio.yaml # DUT hardware configuration (.yaml). Change to dut_mio_gpac.yaml for GPAC support. dut_configuration : dut_configuration_mio.yaml # DUT init configuration (.yaml). Change ...

# For Windows based CI environment: matrix: # For Python versions available on Appveyor, see # https://www.appveyor.com/docs/windows-images-software/#python - BUILD_NAME: py38-unit PYTHON: "C:\\Python38" - BUILD_NAME: py38-lint PYTHON: "C:\\Python38" - BUILD_NAME: py38-docs ...

name: Implementation on: push: paths: - 'setups/**' - 'rtl/**' pull_request: paths: - 'setups/**' - 'rtl/**' schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: Matrix: runs-on: ubuntu-latest outputs: matrix: ${{ steps.generate.outputs.matrix }} steps: ...

<filename>.github/workflows/fixed_point_default.yml name: Fixed Point Default on: push: paths: - 'fixed_point/**' - '!fixed_point/README.md' - '.github/workflows/fixed_point_default.yml' defaults: run: working-directory: fixed_point shell: bash jobs: cppcheck: runs-on: ubuntu-20.04 ...

name: sim-gl-compile parameters: sdf: False PWR_AWARE: False tool: "XCELIUM" num_glb_tiles: 16 commands: - bash run_sim.sh inputs: - adk - design.vcs.v - design.vcs.pg.v - header - design.sdf - glb_tile.vcs.v - glb_tile.vcs.pg.v - glb_tile.sdf - glb_tile_sram.v - glb_tile_sram_pwr.v ou...

<filename>documentation/metadata/an001.yaml --- title: The SPU Assembly Language author: - Felix "xq" Queißner date: April 28, 2020 abstract: | The highly flexible nature of the instruction set of the *SPU Mark II* makes it different to put all possible instructions into useful mnemonics. So the assembly langua...

<filename>examples/mercury_pe1_zx1/dma_example/config.yml --- name: PE1_XZ1_7030_DMA board: boards/mercury_zx1_pe1 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/tlast_gen_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000...

<filename>vlog_netlist/fll/fll_design/rtl/configure.yml name: rtl commands: - | mkdir -p outputs cp -r $VLOG_HOME/mux_4t1 ./outputs cat "./outputs/mux_4t1/qr_4t1_mux_top.sv" "./outputs/mux_4t1/qr_mux_fixed.sv" "./outputs/mux_4t1/ff_c.sv" "./outputs/mux_4t1/tx_inv.sv" > "./outputs/design.v" python gen...

--- name: phase-noise-analyzer board: boards/alpha250 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/axis_constant_v1_0 - fpga/cores/latched_mux_v1_0 - fpga/cores/edge_detector_v1_0 - fpga/cores/comparator_v1_0 - fpg...

## Copyright lowRISC contributors. ## Licensed under the Apache License, Version 2.0, see LICENSE for details. ## SPDX-License-Identifier: Apache-2.0 Device: rv32imc Vendor: opentitan ISA: RV32IMC misa: implemented: True MXL: range: rangelist: [[1]] mode: Unchanged Extensions: bitmask: ...

<reponame>recogni/cluster_interconnect package: name: cluster_interconnect dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v1.13.0 } sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only d...

udma_i2s: files: [ rtl/i2s_clk_gen.sv, rtl/i2s_rx_channel.sv, rtl/i2s_tx_channel.sv, rtl/i2s_ws_gen.sv, rtl/i2s_clkws_gen.sv, rtl/i2s_txrx.sv, rtl/cic_top.sv, rtl/cic_integrator.sv, rtl/cic_comb.sv, rtl/pdm_top.sv, rtl/udma_i2s_reg_if.sv, rtl/udma_i2s_top.sv, ]

<gh_stars>1-10 builds: build1: test_discoverer: type: uvm_test attr: test_dir: $JVS_PRJ_HOME/build1_testcases build2:

name: CI/Console on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: acti...

on: - push name: Linux CI jobs: build: name: Build (Ubuntu) runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 with: submodules: true - name: Get LLVM and Bison run: | sudo apt-get install llvm-11-dev bison echo "LLVM_CONFIG=llvm-config-...

<gh_stars>1-10 KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN50x50.json KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN50x50_weights.h5 InputData: /media/data/projects/landsat_soil_classifier/data/Landsat_x_test.dat OutputPredictions: /media/data/projects/landsat_soil_classifier/d...

<filename>mie-workflows/vod_translate_workflow.yaml AWSTemplateFormatVersion: '2010-09-09' Description: "Media Insights Engine - Workflow to run VOD transcribe and translate application" Parameters: WorkflowCustomResourceArn: Type: String Description: "ARN of the Media Insights custom resource that handles ...

<reponame>lrsb/digitallogicdesign-vhdl-2019<gh_stars>0 language: python addons: apt: update: true install: - sudo apt-get install -y gnat - git clone https://github.com/ghdl/ghdl.git - mkdir $TRAVIS_BUILD_DIR/ghdl/build - cd $TRAVIS_BUILD_DIR/ghdl/build - $TRAVIS_BUILD_DIR/ghdl/configure --prefix=$TRA...

#this is a example of how ENC ip is used in our yaml IR_RECIEVE: IP: __IR_RECIEVE CMD: IRR ir_sda: PIN: A34 DIRECTION: in ir_recieve_status: PIN: A35 DIRECTION: out

<filename>Bender.yml package: name: per2axi dependencies: axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.3 } sources: - src/per2axi_busy_unit.sv - src/per2axi_req_channel.sv - src/per2axi_res_channel.sv - src/per2axi.sv

name: tiny-mlperf-fifo-env-take-2 channels: - conda-forge dependencies: - python=3.7 - pip - pip: - jupyter - pydot - graphviz - git+https://github.com/nicologhielmetti/hls4ml.git@fifo_depth_opt#egg=hls4ml[profiling] - matplotlib - numpy - PyYAML - scikit-learn - tensorflow ...

<filename>Bender.yml package: name: fpu_interco authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.4 } riscv: { git: "<EMAIL>:AlSaqr-platform/riscv_nn.git", rev: "9...

<filename>.github/workflows/atomsim-atombones.yml name: atomsim-atombones on: push: branches: [ main ] pull_request: branches: [ main ] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: build: name: atomsim-atombones runs-on: ubuntu-20.04 steps: ...

<reponame>SubjeBilisim/anasymod analog_ctrl_inputs: in_: abspath: 'tb_i.in_' range: 10 init_value: 0.0 analog_ctrl_outputs: out: abspath: 'tb_i.out' range: 10

<filename>hw/vendor/pulp_platform_apb_uart/Bender.yml package: name: apb_uart authors: [ "<NAME>", "<NAME>" ] sources: - src/slib_clock_div.sv - src/slib_counter.sv - src/slib_edge_detect.sv - src/slib_fifo.sv - src/slib_input_filter.sv - src/slib_input_sync.sv - src/slib_mv_filter.sv...

name: ICan'tBelieveIt'sNotCrypto # Long form description. description: |+ Every journey starts with a single step Guest challenge by TethysSvensson # The flag flag: CTF{5t3p_by_st3p_I_m4k3_my_w4y} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: misc # === the fields below will be filled b...

<reponame>bver/GERET<gh_stars>1-10 --- algorithm: class: ParetoGPSimplified population_size: 800 archive_size: 200 generations_per_cascade: 10 mutation_probability: 0.00 shorten_individual: true tournament_size: 10 init: method: ramped # grow or full or ramped sensible_depth: 7 termina...

<gh_stars>0 package: name: fw-wishbone-interconnect version: None deps: - name: fwprotocol-defs url: https://github.com/featherweight-ip/fwprotocol-defs.git dev-deps: - name: fwprotocol-defs url: https://github.com/featherweight-ip/fwprotocol-defs.git - name: ...