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#include <bits/stdc++.h> using namespace std; const int MaxN = 110; const double EPS = 1E-10; struct TTriangle { double x[3], y[3]; } a[MaxN]; struct TSeg { double x[2], y[2]; } Seg[MaxN * 3]; int n, Total; double Ans; pair<double, int> s[MaxN * 3 * 2]; inline double Cross(const double x1, const double y1, const double x2, const double y2) { return x1 * y2 - x2 * y1; } inline bool Equal(const TTriangle &a, const TTriangle &b) { return a.x[0] == b.x[0] && a.y[0] == b.y[0] && a.x[1] == b.x[1] && a.y[1] == b.y[1] && a.x[2] == b.x[2] && a.y[2] == b.y[2] || a.x[0] == b.x[1] && a.y[0] == b.y[1] && a.x[1] == b.x[2] && a.y[1] == b.y[2] && a.x[2] == b.x[0] && a.y[2] == b.y[0] || a.x[0] == b.x[2] && a.y[0] == b.y[2] && a.x[1] == b.x[0] && a.y[1] == b.y[0] && a.x[2] == b.x[1] && a.y[2] == b.y[1]; } void Init() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %lf%lf%lf%lf%lf%lf , &a[i].x[0], &a[i].y[0], &a[i].x[1], &a[i].y[1], &a[i].x[2], &a[i].y[2]); if (Cross(a[i].x[1] - a[i].x[0], a[i].y[1] - a[i].y[0], a[i].x[2] - a[i].x[0], a[i].y[2] - a[i].y[0]) < -EPS) { swap(a[i].x[1], a[i].x[2]); swap(a[i].y[1], a[i].y[2]); } for (int j = 1; j < i; ++j) if (Equal(a[i], a[j])) { --i, --n; break; } } for (int i = 1; i <= n; ++i) { Seg[i * 3 - 2].x[0] = a[i].x[0], Seg[i * 3 - 2].y[0] = a[i].y[0], Seg[i * 3 - 2].x[1] = a[i].x[1], Seg[i * 3 - 2].y[1] = a[i].y[1]; Seg[i * 3 - 1].x[0] = a[i].x[1], Seg[i * 3 - 1].y[0] = a[i].y[1], Seg[i * 3 - 1].x[1] = a[i].x[2], Seg[i * 3 - 1].y[1] = a[i].y[2]; Seg[i * 3].x[0] = a[i].x[2], Seg[i * 3].y[0] = a[i].y[2], Seg[i * 3].x[1] = a[i].x[0], Seg[i * 3].y[1] = a[i].y[0]; } } inline bool Check(const TSeg &a, const TSeg &b) { return Cross(b.x[0] - a.x[0], b.y[0] - a.y[0], b.x[1] - a.x[0], b.y[1] - a.y[0]) * Cross(b.x[0] - a.x[1], b.y[0] - a.y[1], b.x[1] - a.x[1], b.y[1] - a.y[1]) < EPS; } inline double GetRatio(const TSeg &a, const TSeg &b) { const double u = Cross(a.x[1] - a.x[0], a.y[1] - a.y[0], b.x[0] - a.x[0], b.y[0] - a.y[0]), v = u + Cross(b.x[1] - a.x[0], b.y[1] - a.y[0], a.x[1] - a.x[0], a.y[1] - a.y[0]); return u / v; } inline void Calc(const TSeg &a, const TSeg &b, const TSeg &c) { if (Check(a, c) && Check(b, c)) { double l = GetRatio(a, c), r = GetRatio(b, c); if (l > r) swap(l, r); l = (l > (double)0 ? l : (double)0); l = (l < (double)1 ? l : (double)1); r = (r > (double)0 ? r : (double)0); r = (r < (double)1 ? r : (double)1); if (fabs(l - r) < EPS) return; s[++Total] = make_pair(l, -1); s[++Total] = make_pair(r, 1); } } inline pair<double, double> RatioToVertex(const TSeg &a, const double &k) { return make_pair(a.x[0] + (a.x[1] - a.x[0]) * k, a.y[0] + (a.y[1] - a.y[0]) * k); } int main() { Init(); double l; pair<double, double> p1, p2; for (int i = 1, j, k; i <= n * 3; ++i) { for (j = 1, Total = 0; j <= n; ++j) if ((i - 1) / 3 + 1 != j) { Calc(Seg[j * 3 - 2], Seg[j * 3 - 1], Seg[i]); Calc(Seg[j * 3 - 1], Seg[j * 3], Seg[i]); Calc(Seg[j * 3], Seg[j * 3 - 2], Seg[i]); } sort(s + 1, s + Total + 1); s[++Total] = make_pair((double)1, 0); for (j = 1, k = 0; j <= Total; ++j) { if (!k) { p1 = RatioToVertex(Seg[i], s[j - 1].first); p2 = RatioToVertex(Seg[i], s[j].first); Ans += sqrt(((p1.first - p2.first) * (p1.first - p2.first)) + ((p1.second - p2.second) * (p1.second - p2.second))); } k -= s[j].second; } } cout << setprecision(10) << fixed << Ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_8_V
`define SKY130_FD_SC_LP__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_8_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_register
*/
module test_axis_register;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter REG_TYPE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_register.lxt");
$dumpvars(0, test_axis_register);
end
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(REG_TYPE)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
module automatic_events();
reg [5:1] any;
integer k;
initial begin
any = 5'b00000;
#200;
for (k = 1; k <= 5; k = k + 1) begin
#10 any[k] = 1;
#10 any[k] = 0;
end
end
task automatic report_events;
input integer n;
begin:task_body
reg [5:1] pos;
reg [5:1] neg;
#n;
pos = 5'b00000;
neg = 5'b00000;
fork:task_threads
integer i;
integer j;
for (i = 1; i <= 5; i = i + 1) begin
#10 neg[i] = 1;
#10 pos[i] = 1;
#10 neg[i] = 0;
#10 pos[i] = 0;
end
for (j = 1; j <= 20; j = j + 1) begin
@( any[1] or posedge pos[1] or negedge neg[1]
or any[2] or posedge pos[2] or negedge neg[2]
or any[3] or posedge pos[3] or negedge neg[3]
or any[4] or posedge pos[4] or negedge neg[4]
or any[5] or posedge pos[5] or negedge neg[5] );
#n $display("task %0d triggered: %b %b %b %4d", n, any, pos, neg, $time);
end
join
end
endtask
initial begin
fork
report_events(1);
report_events(2);
join
$finish(0);
end
endmodule
|
module reg_128x32b_3r_2w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr1_addr, wr0_en,
wr1_en, wr0_data, wr1_data
,clk_double
);
input clk;
input clk_double;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [6:0] rd0_addr;
input [6:0] rd1_addr;
input [6:0] rd2_addr;
input [6:0] wr0_addr;
input [6:0] wr1_addr;
input wr0_en;
input wr1_en;
input [31:0] wr0_data;
input [31:0] wr1_data;
reg [31:0] converted_port_a_address;
reg [31:0] converted_port_b_address;
reg [31:0] converted_port_c_address;
wire [31:0] converted_port_d_address;
reg [3:0] wr_en_a;
reg [3:0] wr_en_b;
wire [31:0] block_out_a;
wire [31:0] block_out_b;
wire [31:0] block_out_c;
assign converted_port_d_address = {wr1_addr, 2'b0};
always @(*) begin
if(wr0_en) begin
converted_port_a_address <= {wr0_addr, 2'b0};
converted_port_c_address <= {wr0_addr, 2'b0};
wr_en_a <= {4{wr0_en}};
end
else begin
converted_port_a_address <= {rd0_addr, 2'b0};
converted_port_c_address <= {rd2_addr, 2'b0};
wr_en_a <= 4'd0;
end
if(wr1_en) begin
converted_port_b_address <= {wr1_addr, 2'b0};
wr_en_b <= {4{wr1_en}};
end
else begin
converted_port_b_address <= {rd1_addr, 2'b0};
wr_en_b <= 4'd0;
end
end
assign rd0_data = block_out_a;
assign rd1_data = block_out_b;
assign rd2_data = block_out_c;
block_ram bank0(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(wr_en_a), // input [3 : 0] wea
.addra(converted_port_a_address), // input [31 : 0] addra
.dina(wr0_data), // input [31 : 0] dina
.douta(block_out_a), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(wr_en_b), // input [3 : 0] web
.addrb(converted_port_b_address), // input [31 : 0] addrb
.dinb(wr1_data), // input [31 : 0] dinb
.doutb(block_out_b) // output [31 : 0] doutb
);
block_ram bank1(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(wr_en_a), // input [3 : 0] wea
.addra(converted_port_c_address), // input [31 : 0] addra
.dina(wr0_data), // input [31 : 0] dina
.douta(block_out_c), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(wr_en_b), // input [3 : 0] web
.addrb(converted_port_d_address), // input [31 : 0] addrb
.dinb(wr1_data), // input [31 : 0] dinb
.doutb() // output [31 : 0] doutb
);
endmodule
|
module top(...);
input [3:0] a;
output o1_1 = 4'b0000 > a;
output o1_2 = 4'b0000 <= a;
output o1_3 = 4'b1111 < a;
output o1_4 = 4'b1111 >= a;
output o1_5 = a < 4'b0000;
output o1_6 = a >= 4'b0000;
output o1_7 = a > 4'b1111;
output o1_8 = a <= 4'b1111;
output o2_1 = 4'sb0000 > $signed(a);
output o2_2 = 4'sb0000 <= $signed(a);
output o2_3 = $signed(a) < 4'sb0000;
output o2_4 = $signed(a) >= 4'sb0000;
output o3_1 = 4'b0100 > a;
output o3_2 = 4'b0100 <= a;
output o3_3 = a < 4'b0100;
output o3_4 = a >= 4'b0100;
output o4_1 = 5'b10000 > a;
output o4_2 = 5'b10000 >= a;
output o4_3 = 5'b10000 < a;
output o4_4 = 5'b10000 <= a;
output o4_5 = a < 5'b10000;
output o4_6 = a <= 5'b10000;
output o4_7 = a > 5'b10000;
output o4_8 = a >= 5'b10000;
output o5_1 = 5'b10100 > a;
output o5_2 = 5'b10100 >= a;
output o5_3 = 5'b10100 < a;
output o5_4 = 5'b10100 <= a;
output o5_5 = a < 5'b10100;
output o5_6 = a <= 5'b10100;
output o5_7 = a > 5'b10100;
output o5_8 = a >= 5'b10100;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O32AI_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 755, M = 10000005; char s[M]; bool e[N][N]; int n; struct ACAutomaton { int trie[M][2], id[M], idx, pos[M], fa[M]; void ins(char *s, int t) { int cur = 0, l = strlen(s + 1); for (int i = 1; i <= l; i++) { if (!trie[cur][s[i] - a ]) trie[cur][s[i] - a ] = ++idx, fa[idx] = cur; cur = trie[cur][s[i] - a ]; } id[cur] = t; pos[t] = cur; } int fail[M]; void build_fail() { queue<int> q; for (int i = 0; i < 2; i++) if (trie[0][i]) q.push(trie[0][i]); while (!q.empty()) { int nd = q.front(); q.pop(); for (int i = 0; i < 2; i++) if (trie[nd][i]) fail[trie[nd][i]] = trie[fail[nd]][i], q.push(trie[nd][i]); else trie[nd][i] = trie[fail[nd]][i]; } } int f[M]; int getf(int v) { return f[v] == v ? v : f[v] = getf(f[v]); } void build_tr() { for (int i = 1; i <= idx; i++) f[i] = id[i] ? i : fail[i]; for (int i = 1; i <= n; i++) { int p = pos[i]; if (id[getf(fail[p])]) e[i][id[getf(fail[p])]] = 1; p = fa[pos[i]]; while (p) { if (id[p]) { e[i][id[p]] = 1; break; } if (id[getf(p)]) e[i][id[getf(p)]] = 1; p = fa[p]; } } } } t; int mat[N], mat2[N]; bool vis[N]; int find(int pos) { if (vis[pos]) return 0; vis[pos] = 1; for (int i = 1; i <= n; i++) if (e[pos][i] && (!mat[i] || find(mat[i]))) { mat[i] = pos; return 1; } return 0; } bool vis1[N], vis2[N]; void dfs(int pos) { if (vis1[pos]) return; vis1[pos] = 1; for (int i = 1; i <= n; i++) if (e[pos][i] && mat2[pos] != i && !vis2[i]) { vis2[i] = 1; if (mat[i]) dfs(mat[i]); } } int ans[N], idx; int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) cin >> (s + 1), t.ins(s, i); t.build_fail(); t.build_tr(); for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) e[i][j] |= e[i][k] & e[k][j]; for (int i = 1; i <= n; i++) memset(vis, 0, sizeof(vis)), find(i); for (int i = 1; i <= n; i++) if (mat[i]) mat2[mat[i]] = i; for (int i = 1; i <= n; i++) if (!mat2[i]) dfs(i); for (int i = 1; i <= n; i++) if (vis1[i] && !vis2[i]) ans[++idx] = i; cout << idx << endl; for (int i = 1; i <= idx; i++) cout << ans[i] << ; return 0; }
|
module hdUnit(
d_raddr1, d_raddr2, d_addrselector, d_jr_or_exec, d_immonly, d_opcode, e_isLoad, e_wreg,
//nop_alu_stall, nop_lw_stall, nop_sw_stall, // this doesn't seem to be required for this
pc_stall, ifid_stall, idex_stall, inst_stall,
write_done
);
// d_addrselector is lhb_llb_regcon, it gives addr fof [11:8] in raddr2 when 1 OR [7:4] in raddr2 when 0
// jal or exec is jal || exec
// ! (jal || exec) will indicate sw instruction
// d_immonly is 1 for instructions which only use immediates or offsets and don't need to be stalled
input [3:0] d_raddr1;
input [3:0] d_raddr2;
input d_addrselector;
input d_jr_or_exec;
input d_immonly;
input [3:0] d_opcode;
input e_isLoad;
input [3:0] e_wreg;
input write_done;
output pc_stall;
output ifid_stall;
output idex_stall;
output inst_stall;
//reg [1:0] stallCount;
/*always @ (*)
begin
stallCount = (e_isLoad===1'b1 && d_immonly!==1'b1 && (
(d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg))
)) ? 2'b111 : stallCount;
if(stallCount>3'b00) begin
pc_stall_temp = 1'b1;
ifid_stall_temp = 1'b1;
stallCount = stallCount-1'b1;
end
else begin
pc_stall_temp = 1'b0;
ifid_stall_temp = 1'b0;
end
end*/
/*wire temp_r1_w;
assign temp_r1_w = (d_raddr1===e_wreg);
assign pc_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;
assign ifid_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;
assign idex_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;*/
assign pc_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign ifid_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign idex_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign inst_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
/// NOP also has to sent through the whole pipeline 3 times
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_31x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_31x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [30:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [30:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire [30:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [6:0] usedw = sub_wire1[6:0];
wire empty = sub_wire2;
wire [30:0] q = sub_wire3[30:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 31,
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_widthu = 7,
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.almost_full_value = 3,
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "31"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "31"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 31 0 INPUT NODEFVAL data[30..0]
// Retrieval info: USED_PORT: q 0 0 31 0 OUTPUT NODEFVAL q[30..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 31 0 data 0 0 31 0
// Retrieval info: CONNECT: q 0 0 31 0 @q 0 0 31 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin >> n >> m; if (n == 1) { cout << 1; exit(0); } cout << fixed << setprecision(12) << 1.0 / n + (1.0 * (n - 1)) / n * (1.0 * (m - 1)) / (m * n - 1); }
|
//
// tmr.v -- programmable timer
//
module tmr(clk, reset,
en, wr, addr,
data_in, data_out,
wt, irq);
input clk;
input reset;
input en;
input wr;
input [3:2] addr;
input [31:0] data_in;
output reg [31:0] data_out;
output wt;
output irq;
reg [31:0] counter;
reg [31:0] divisor;
reg divisor_loaded;
reg expired;
reg alarm;
reg ien;
always @(posedge clk) begin
if (divisor_loaded == 1) begin
counter <= divisor;
expired <= 0;
end else begin
if (counter == 32'h00000001) begin
counter <= divisor;
expired <= 1;
end else begin
counter <= counter - 1;
expired <= 0;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
divisor <= 32'hFFFFFFFF;
divisor_loaded <= 1;
alarm <= 0;
ien <= 0;
end else begin
if (expired == 1) begin
alarm <= 1;
end else begin
if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
alarm <= data_in[0];
ien <= data_in[1];
end
if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
divisor <= data_in;
divisor_loaded <= 1;
end else begin
divisor_loaded <= 0;
end
end
end
end
always @(*) begin
case (addr[3:2])
2'b00:
// ctrl
data_out = { 28'h0000000, 2'b00, ien, alarm };
2'b01:
// divisor
data_out = divisor;
2'b10:
// counter
data_out = counter;
2'b11:
// not used
data_out = 32'hxxxxxxxx;
default:
data_out = 32'hxxxxxxxx;
endcase
end
assign wt = 0;
assign irq = ien & alarm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A211O_BEHAVIORAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a211o (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_20_V
`define SKY130_FD_SC_LP__BUSDRIVER_20_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog wrapper for busdriver with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdriver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver_20 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdriver base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver_20 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdriver base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_20_V
|
module core (
ir_next,
ir_be,
// ir0, ir1,
// ir11, ir10, ir01, ir00,
// ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000,
// ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000,
of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001,
// offset,
// pc_next,
// pc_en,
// pc,
// len,
// imm,
// imm_en
// , cur_len
clk, reset_n
);
input clk, reset_n;
input [63:0] ir_next;
input [1:0] ir_be;
// input [3:0] pc_next;
// input pc_en;
// input imm_en;
// output [31:0] ir1, ir0;
// output [15:0] ir11, ir10, ir01, ir00;
// output [7:0] ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000;
// output [3:0] ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000;
output [3:0] of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001;
// output [3:0] offset;
// output [3:0] len;
// output [2:0] cur_len;
// output [3:0] pc;
// output [31:0] imm;
reg [63:0] ir;
reg [31:0] ir0, ir1;
// reg [15:0] ir11, ir10, ir01, ir00;
// reg [7:0] ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000;
// reg [3:0] ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000;
reg [3:0] of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001;
wire [3:0]
// of1111, of1110,
of1101, of1100, of1011, of1010, of1001, of1000,
of0111, of0110, of0101, of0100, of0011, of0010, of0001;
//, of0000;
// wire [3:0] offset;
// wire [2:0] cur_len;
// wire [31:0] imm_next;
// reg [3:0] len;
// reg [3:0] pc;
// reg [31:0] imm;
always @(posedge clk or negedge reset_n) if (~reset_n) ir0 <= 32'b0; else if (ir_be[0]) ir0 <= ir_next[31:0];
always @(posedge clk or negedge reset_n) if (~reset_n) ir1 <= 32'b0; else if (ir_be[1]) ir1 <= ir_next[63:32];
// always @(posedge clk or negedge reset_n) if (~reset_n) pc <= 4'b0; else if (pc_en) pc <= pc_next;
always @ (ir0, ir1) begin
// {ir11, ir10} = ir1;
// {ir01, ir00} = ir0;
//
// {ir111, ir110, ir101, ir100} = ir1;
// {ir011, ir010, ir001, ir000} = ir0;
//
// {ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000} = ir1;
// {ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000} = ir0;
// len = ir0000;
ir = {ir1, ir0};
end
tail_offset u_tail_offset (
.ir(ir), /* .pc(pc), .offset(offset), */
.of1101(of1101),
.of1100(of1100),
.of1011(of1011),
.of1010(of1010),
.of1001(of1001),
.of1000(of1000),
.of0111(of0111),
.of0110(of0110),
.of0101(of0101),
.of0100(of0100),
.of0011(of0011),
.of0010(of0010),
.of0001(of0001)
// , .len(cur_len)
// , .imm(imm_next)
);
// always @(posedge clk) if (imm_en) imm <= imm_next;
always @(posedge clk) of_r1101 <= of1101;
always @(posedge clk) of_r1100 <= of1100;
always @(posedge clk) of_r1011 <= of1011;
always @(posedge clk) of_r1010 <= of1010;
always @(posedge clk) of_r1001 <= of1001;
always @(posedge clk) of_r1000 <= of1000;
always @(posedge clk) of_r0111 <= of0111;
always @(posedge clk) of_r0110 <= of0110;
always @(posedge clk) of_r0101 <= of0101;
always @(posedge clk) of_r0100 <= of0100;
always @(posedge clk) of_r0011 <= of0011;
always @(posedge clk) of_r0010 <= of0010;
always @(posedge clk) of_r0001 <= of0001;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register
*/
module axis_srl_register #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
module Microphone(
output spi_clk, // SPI clock to ADC
output spi_mosi, // Data to ADC
output reg spi_cs, // Chip select for ADC
input spi_miso, // Data from ADC
input clk,
input rst,
input start_sample, // Set to 1 to sample the ADC
output reg sample_done, // Latest sample is ready to be read
output reg [9:0] sample
);
// The 10-bit ADC sample
reg sample_done_d;
reg [9:0] sample_d;
// SPI module
reg spi_start, spi_start_d;
reg spi_cs_d;
reg [7:0] spi_mosi_byte, spi_mosi_byte_d;
wire [7:0] spi_miso_byte;
wire spi_done;
SPI #(6) spi(clk, rst, spi_miso, spi_mosi, spi_clk, spi_start, spi_mosi_byte, spi_miso_byte, , spi_done);
// parameter 6 = divide 100 Mhz clock by 2^6, which ends up being 1.5625 MHz
// States
reg [3:0] state, state_d; // State of the module
reg [3:0] state_after, state_after_d; // State to go to after waiting for spi to be done
localparam SPI_START = 4'd0,
SPI_WAIT = 4'd1,
IDLE = 4'd2,
CS_LOW = 4'd3,
SEND_START = 4'd4,
SEND_CHANNEL = 4'd5,
RECV_2BITS = 4'd6,
SEND_ZEROS = 4'd7,
RECV_8BITS = 4'd8,
CS_HIGH = 4'd9;
// Sequential logic
always @ (posedge clk) begin
if(rst) begin
sample <= 10'b0;
sample_done <= 1'b0;
spi_start <= 1'b0;
spi_cs <= 1'b1;
spi_mosi_byte <= 8'b0;
state <= IDLE;
state_after <= IDLE;
end else begin
sample <= sample_d;
sample_done <= sample_done_d;
spi_start <= spi_start_d;
spi_cs <= spi_cs_d;
spi_mosi_byte <= spi_mosi_byte_d;
state <= state_d;
state_after <= state_after_d;
end
end
// Combinational logic
always @ (*) begin
sample_d = sample;
sample_done_d = 1'b0;
spi_start_d = 1'b0;
spi_cs_d = spi_cs;
spi_mosi_byte_d = spi_mosi_byte;
state_d = state;
state_after_d = state_after;
case(state)
IDLE: begin
if(start_sample == 1'b1) begin
spi_cs_d = 1'b0; // chip select low
state_d = SEND_START;
end
end
SEND_START: begin
spi_mosi_byte_d = 8'h01;
state_d = SPI_START;
state_after_d = SEND_CHANNEL;
end
SEND_CHANNEL: begin
spi_mosi_byte_d = 8'h00; // Read from ADC channel 0
state_d = SPI_START;
state_after_d = RECV_2BITS;
end
RECV_2BITS: begin
sample_d[9:8] = spi_miso_byte[1:0];
state_d = SEND_ZEROS;
end
SEND_ZEROS: begin
spi_mosi_byte_d = 8'h00; // Send zeros so we can read the last 8 bits
state_d = SPI_START;
state_after_d = RECV_8BITS;
end
RECV_8BITS: begin
sample_d[7:0] = spi_miso_byte;
state_d = IDLE;
sample_done_d = 1'b1;
spi_cs_d = 1'b1; // chip select high
end
SPI_START: begin
spi_start_d = 1'b1;
state_d = SPI_WAIT;
end
SPI_WAIT: begin
if(spi_done)
state_d = state_after; // go to state we were waiting to go to
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 205; const int mod = 10007; void add(int &x, int y) { x += y; if (x >= mod) x -= mod; } int mul(int x, int y) { return x * y % mod; } int pw(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = mul(ret, x); x = mul(x, x); y >>= 1; } return ret; } namespace berlekamp_massey { vector<int> bm(vector<int> x) { vector<int> rel, cur; int lf, ld; for (int i = 0; i < x.size(); ++i) { int sum = 0; for (int j = 0; j < cur.size(); ++j) add(sum, mul(x[i - j - 1], cur[j])); if (sum == x[i]) continue; if (!cur.size()) { cur.resize(i + 1); lf = i; ld = sum - x[i]; add(ld, mod); continue; } int coef = mul(sum - x[i] + mod, pw(ld, mod - 2)); vector<int> new_cur(i - lf - 1); new_cur.push_back(coef); for (int j = 0; j < rel.size(); ++j) { new_cur.push_back(mul(mod - rel[j], coef)); } if (new_cur.size() < cur.size()) new_cur.resize(cur.size()); for (int j = 0; j < cur.size(); ++j) add(new_cur[j], cur[j]); if (i - lf + rel.size() >= cur.size()) { rel = cur, lf = i, ld = sum - x[i]; add(ld, mod); } cur = new_cur; } return cur; } int sz; int a[5005], rel[5005], tmp[5005]; int ff[5005], gg[5005]; void mulmod(int *p, int *q) { for (int i = 0; i < sz + sz; ++i) tmp[i] = 0; for (int i = 0; i < sz; ++i) if (p[i]) { for (int j = 0; j < sz; ++j) { add(tmp[i + j], mul(p[i], q[j])); } } for (int i = sz + sz - 1; i >= sz; --i) if (tmp[i]) { for (int j = sz - 1; j >= 0; --j) { add(tmp[i - j - 1], mul(tmp[i], rel[j])); } } for (int i = 0; i < sz; ++i) p[i] = tmp[i]; } int solve(vector<int> x, int n) { if (n < x.size()) return x[n]; vector<int> cur = bm(x); sz = cur.size(); for (int i = 0; i < sz; ++i) rel[i] = cur[i], a[i] = x[i]; for (int i = 0; i < sz; ++i) ff[i] = gg[i] = 0; ff[0] = 1; if (sz > 1) gg[1] = 1; else gg[0] = rel[0]; while (n) { if (n & 1) mulmod(ff, gg); mulmod(gg, gg); n >>= 1; } int ret = 0; for (int i = 0; i < sz; ++i) add(ret, mul(ff[i], a[i])); return ret; } } // namespace berlekamp_massey using namespace berlekamp_massey; int n, m; string s; int f[805][N][N], ans[1405]; vector<int> g; int main() { ios_base::sync_with_stdio(false); cin >> s >> n; m = s.size(); s = ~ + s; f[0][0][0] = 1; int len = m + 1400 >> 1; for (int i = 1; i <= len; ++i) { for (int j = 0; j <= m; ++j) { for (int k = 0; k <= m; ++k) { if (f[i - 1][j][k] == 0) continue; if (j == m && k == m) add(f[i][j][k], mul(26, f[i - 1][j][k])); else if (j == m) { add(f[i][j][k], mul(25, f[i - 1][j][k])); add(f[i][j][k + 1], f[i - 1][j][k]); } else if (k == m) { add(f[i][j][k], mul(25, f[i - 1][j][k])); add(f[i][j + 1][k], f[i - 1][j][k]); } else { if (s[j + 1] == s[m + 1 - k - 1]) { add(f[i][j + 1][k + 1], f[i - 1][j][k]); add(f[i][j][k], mul(25, f[i - 1][j][k])); } else { add(f[i][j + 1][k], f[i - 1][j][k]); add(f[i][j][k + 1], f[i - 1][j][k]); add(f[i][j][k], mul(24, f[i - 1][j][k])); } } } } } for (int i = 0; i < 1400; ++i) { int l = m + i >> 1; for (int j = 0; j <= m; ++j) { for (int k = 0; k <= m; ++k) { if (j + k >= m) { if (m + i & 1) add(ans[i], mul(26, f[l][j][k])); else add(ans[i], f[l][j][k]); } if (j + k == m - 1) { if (m + i & 1) add(ans[i], f[l][j][k]); } } } } for (int i = 0; i < 1400; ++i) g.push_back(ans[i]); cout << solve(g, n) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k, d; cin >> k >> d; if (k > 1 && d == 0) cout << No solution ; else { cout << d; for (int i = 0; i < k - 1; i++) cout << 0 ; } return 0; }
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "fifo.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd231;
// Push 8...
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd230;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd201;
// Pop 8...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
// Try push and pull
/*
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd18;
*/
// Push 3 in
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd18;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
/*
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd74;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd138;
// Pop 3 out
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
*/
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_TB_V
`define SKY130_FD_SC_HDLL__O21AI_TB_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hdll__o21ai dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_1_V
`define SKY130_FD_SC_HVL__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_1_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; void _IOS() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin.sync_with_stdio(0); } long long a[500009], b[500009]; long long n, m, k; map<long long, bool> pg; long long dp[100009][3]; int main() { _IOS(); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int i = n - 2; while (i >= 0 && k--) { a[n - 1] += a[i]; a[i] = 0; i--; } long long mn = (long long)1e10, mx = 0; for (int i = 0; i < n; i++) { mn = min(a[i], mn); mx = max(a[i], mx); } cout << abs(mx - mn) << endl; } }
|
#include <bits/stdc++.h> using namespace std; struct node { int v; long long w; node(){}; node(int v, long long w) : v(v), w(w) {} }; vector<vector<node> > G; int b[102550]; long long solve(int s) { long long ans = 10000000000000000; int len = G[s].size(); for (int i = 0; i < len; i++) { node p = G[s][i]; if (b[p.v]) { ans = min(ans, p.w); } } if (ans == 10000000000000000) ans = -1; return ans; } int main() { int n, m, k, num; scanf( %d %d %d , &n, &m, &k); G.clear(); G.resize(n + 5); memset(b, 0, sizeof(b)); for (int i = 1; i <= m; i++) { int u, v; long long w; scanf( %d %d %I64d , &u, &v, &w); G[u].push_back(node(v, w)); G[v].push_back(node(u, w)); } for (int i = 1; i <= k; i++) { scanf( %d , &num); b[num] = 1; } long long ans = 10000000000000000; for (int i = 1; i <= n; i++) { if (b[i] == 1) continue; long long num = solve(i); if (num != -1) ans = min(ans, num); } if (ans == 10000000000000000) ans = -1; printf( %I64d n , ans); return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int qtable[9][9]; int x_min[9]; int x_max[9]; int y_min[9]; int y_max[9]; int solve_problem() { int n, m, k, s; if (scanf( %d %d %d %d , &n, &m, &k, &s) != 4) return 1; fill(x_min, x_min + k, numeric_limits<int>::max()); fill(x_max, x_max + k, numeric_limits<int>::min()); fill(y_min, y_min + k, numeric_limits<int>::max()); fill(y_max, y_max + k, numeric_limits<int>::min()); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int t; scanf( %d , &t); --t; int x = i + j; int y = i - j; if (x < x_min[t]) x_min[t] = x; if (x > x_max[t]) x_max[t] = x; if (y < y_min[t]) y_min[t] = y; if (y > y_max[t]) y_max[t] = y; } int prev_q = -1; for (int i = 0; i < s; i++) { int q; scanf( %d , &q); --q; if (i > 0) qtable[min(prev_q, q)][max(prev_q, q)] = 1; prev_q = q; } int result = 0; for (int i = 0; i < k; i++) for (int j = i; j < k; j++) if (qtable[i][j]) { int cand = abs(x_min[i] - x_max[j]); if (cand > result) result = cand; cand = abs(x_max[i] - x_min[j]); if (cand > result) result = cand; cand = abs(y_min[i] - y_max[j]); if (cand > result) result = cand; cand = abs(y_max[i] - y_min[j]); if (cand > result) result = cand; } printf( %d n , result); return 0; } int main() { solve_problem(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a1, a2, b1, b2, c1, c2, s; cin >> n; cin >> a1 >> a2 >> b1 >> b2 >> c1 >> c2; s = a1 + b1 + c1; n = n - s; if (n == 0) { cout << a1 << << b1 << << c1 << endl; return 0; } else { a2 = a2 - a1; b2 = b2 - b1; c2 = c2 - c1; if (n <= a2) a1 += n; else { a1 += a2; n = n - a2; if (n == 0) { cout << a1 << << b1 << << c1 << endl; return 0; } if (n <= b2) b1 += n; else { b1 += b2; n = n - b2; if (n == 0) { cout << a1 << << b1 << << c1 << endl; return 0; } if (n <= c2) { c1 += n; } else { c1 += c2; } } } } cout << a1 << << b1 << << c1 << endl; return 0; }
|
#include <bits/stdc++.h> void sort(int *a, int n) { int isSorted = 0; int i; int tmp; while (isSorted == 0) { isSorted = 1; for (i = 0; i < n - 1; i++) { if (a[i] > a[i + 1]) { tmp = a[i]; a[i] = a[i + 1]; a[i + 1] = tmp; isSorted = 0; } } } } int main() { int n, m; int p[101]; int i; int numeven, numodd; scanf( %d , &n); m = n / 2; for (i = 0; i < m; i++) scanf( %d , p + i); sort(p, m); numeven = 0; numodd = 0; for (i = 0; i < m; i++) { numeven += ((n - i * 2) - p[m - 1 - i]) > 0 ? ((n - i * 2) - p[m - 1 - i]) : -((n - i * 2) - p[m - 1 - i]); } for (i = 0; i < m; i++) { numodd += (((i * 2 + 1) - p[i])) > 0 ? (((i * 2 + 1) - p[i])) : -(((i * 2 + 1) - p[i])); } if (numeven > numodd) printf( %d n , numodd); else printf( %d n , numeven); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > v[1000007]; vector<int> rv[1000007]; int comp[1000007]; vector<pair<int, int> > g[1000007]; long long sm[1000007]; int used[1000007]; int stver; stack<int> s; vector<int> srt; bool val[100000002]; long long hval[1000007]; long long dp[1000007]; map<int, int> ZX; void dfs(int vertex) { used[vertex] = 1; int i; int sz = v[vertex].size(); for (i = 0; i < sz; i++) { if (used[v[vertex][i].first] == 0) { dfs(v[vertex][i].first); } } s.push(vertex); } void revdfs(int vertex, int id) { comp[vertex] = id; int i; int sz = rv[vertex].size(); for (i = 0; i < sz; i++) { if (comp[rv[vertex][i]] == 0) { revdfs(rv[vertex][i], id); } } } void precalc() { int i; long long cur = 0; int br = 1; if (val[0] == true) { hval[0] = 1; } for (i = 1; i < 100000002; i++) { cur = cur + br; if (i >= (br * (br + 1) / 2)) { br++; } if (val[i] == true) { hval[ZX[i]] = cur; } } } void calc_dp(int vertex) { used[vertex] = 1; int i; int sz = g[vertex].size(); for (i = 0; i < sz; i++) { if (used[g[vertex][i].first] == 0) { calc_dp(g[vertex][i].first); } if (dp[vertex] < dp[g[vertex][i].first] + g[vertex][i].second) { dp[vertex] = dp[g[vertex][i].first] + g[vertex][i].second; } } dp[vertex] += sm[vertex]; } void input() { scanf( %d%d , &n, &m); int i; for (i = 1; i <= m; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); v[x].push_back(make_pair(y, z)); rv[y].push_back(x); srt.push_back(z); val[z] = true; } if (srt.size() != 0) { sort(srt.begin(), srt.end()); ZX[srt[0]] = 1; for (i = 1; i < m; i++) { if (srt[i] == srt[i - 1]) { continue; } ZX[srt[i]] = ZX[srt[i - 1]] + 1; } } scanf( %d , &stver); precalc(); } void solve() { int i, j; for (i = 1; i <= n; i++) { if (used[i] == 0) { dfs(i); } } int tp = 1; while (s.empty() == false) { int u = s.top(); s.pop(); if (comp[u] != 0) { continue; } revdfs(u, tp); tp++; } for (i = 1; i <= n; i++) { int sz = v[i].size(); for (j = 0; j < sz; j++) { if (comp[v[i][j].first] == comp[i]) { sm[comp[i]] += hval[ZX[v[i][j].second]]; } else { g[comp[i]].push_back(make_pair(comp[v[i][j].first], v[i][j].second)); } } } for (i = 1; i <= n; i++) { used[i] = 0; } stver = comp[stver]; calc_dp(stver); printf( %I64d n , dp[stver]); } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); input(); solve(); return 0; }
|
#include <bits/stdc++.h> int main() { int n, x; std::cin >> n >> x; std::vector<int> data; int counter = 0; for (int i = 0; i != n; i++) { int temp; std::cin >> temp; data.push_back(temp); } std::sort(data.begin(), data.end()); if (std::find(data.begin(), data.end(), x) != data.end()) { auto it = std::find(data.begin(), data.end(), x); counter++; data.erase(it); } for (int i = 0; i < x; i++) { if (std::find(data.begin(), data.end(), i) == data.end()) { data.push_back(i); counter++; } } std::cout << counter << std::endl; return 0; }
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Interval timer mode. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer dco_clk_cnt;
always @(negedge dco_clk)
dco_clk_cnt <= dco_clk_cnt+1;
integer mclk_cnt;
always @(negedge mclk)
mclk_cnt <= mclk_cnt+1;
integer smclk_cnt;
always @(negedge smclk)
smclk_cnt <= smclk_cnt+1;
integer aclk_cnt;
`ifdef ASIC_CLOCKING
always @(negedge aclk)
aclk_cnt <= aclk_cnt+1;
`else
always @(negedge lfxt_clk)
aclk_cnt <= aclk_cnt+1;
`endif
integer inst_cnt;
always @(inst_number)
inst_cnt <= inst_cnt+1;
reg watchdog_clock;
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`else
`ifdef WATCHDOG_NOMUX_ACLK
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`else
always @(posedge dco_clk or negedge dco_clk) watchdog_clock <= dco_clk;
`endif
`endif
`else
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`endif
integer watchdog_clock_cnt;
always @(posedge watchdog_clock)
watchdog_clock_cnt <= watchdog_clock_cnt+1;
always @(posedge dut.wdt_irq)
watchdog_clock_cnt = 1'b0;
integer ii;
integer jj;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
ii = 0;
jj = 0;
`ifdef WATCHDOG
// WATCHDOG TEST: INTERVAL MODE /64
//--------------------------------------------------------
@(r15==16'h1000);
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
`ifdef ACLK_DIVIDER
repeat(5) @(posedge watchdog_clock);
`else
repeat(4) @(posedge watchdog_clock);
`endif
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef ACLK_DIVIDER
repeat(6) @(posedge watchdog_clock);
`else
repeat(5) @(posedge watchdog_clock);
`endif
`else
repeat(21) @(posedge watchdog_clock);
`endif
`endif
`endif
for ( ii=0; ii < 9; ii=ii+1)
begin
repeat(1) @(posedge watchdog_clock);
jj = 1;
dco_clk_cnt = 0;
mclk_cnt = 0;
smclk_cnt = 0;
aclk_cnt = 0;
inst_cnt = 0;
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 1) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 1) =====");
if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 1) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 1) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 1) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 1) =====");
`else
`ifdef WATCHDOG_NOMUX_ACLK
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 2) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 2) =====");
if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 2) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 2) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 2) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 2) =====");
`else
repeat(39) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 39) tb_error("====== DCO_CLK is not running (CONFIG 3) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 3) =====");
if (smclk_cnt !== 39) tb_error("====== SMCLK is not running (CONFIG 3) =====");
if (aclk_cnt === 0) tb_error("====== ACLK is not running (CONFIG 3) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 3) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");
repeat(24) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 3) =====");
`endif
`endif
`else
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt < 1800) tb_error("====== DCO_CLK is not running (CONFIG 4) =====");
if (mclk_cnt < 1800) tb_error("====== MCLK is not running (CONFIG 4) =====");
if (smclk_cnt < 1800) tb_error("====== SMCLK is not running (CONFIG 4) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 4) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 4) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 4) =====");
`endif
end
// WATCHDOG TEST: RESET MODE /64
//--------------------------------------------------------
@(r15==16'h5000);
if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");
`else
tb_skip_finish("| (the Watchdog is not included) |");
`endif
stimulus_done = 1;
end
|
//=========================================================
// Integrated Instruction/Data memory (seperate ports)
//=========================================================
`define EOF 32'hFFFF_FFFF
`define NULL 0
`timescale 1ns/100ps
module Memory(
inst_addr,
instr,
data_addr,
data_in,
mem_read,
mem_write,
data_out
);
// Interface
input [4*8:1] inst_addr;
output [31:0] instr;
input [4*8:1] data_addr;
input [31:0] data_in;
input mem_read;
input mem_write;
output [31:0] data_out;
// Memory is byte-addressable, instructions are word-aligned
// Memory with 2k 8-bit
// Data address range: 0x0000 ~ 0x2FFC
// Instruction address range: 0x3000 ~ 0x3FFC
parameter MEM_SIZE=32'h00004000;
integer i;
integer file, r;
reg [7:0] memory [0:MEM_SIZE-1];
reg [31:0] data_addr_reg, inst_addr_reg;
reg [12*8:1] rest;
initial
begin : file_block
// for(i=0; i<2048; i=i+1) begin
// memory[i] = 8'b0;
// end
file = $fopen("MinMax.hexdump","r");
if (file == `NULL)
disable file_block;
for (i = 0; i < 3 ; i=i+1)
begin
r = $fscanf(file, "%h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h\n", data_addr_reg, memory[data_addr_reg], memory[data_addr_reg+1], memory[data_addr_reg+2], memory[data_addr_reg+3], memory[data_addr_reg+4], memory[data_addr_reg+5], memory[data_addr_reg+6], memory[data_addr_reg+7], memory[data_addr_reg+8], memory[data_addr_reg+9], memory[data_addr_reg+10], memory[data_addr_reg+11], memory[data_addr_reg+12], memory[data_addr_reg+13], memory[data_addr_reg+14], memory[data_addr_reg+15]);
end // for first loop
r = $fscanf(file, "%s\n", rest);
for (i = 0; i < 8 ; i=i+1)
begin
r = $fscanf(file, "%h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h\n", inst_addr_reg, memory[inst_addr_reg], memory[inst_addr_reg+1], memory[inst_addr_reg+2], memory[inst_addr_reg+3], memory[inst_addr_reg+4], memory[inst_addr_reg+5], memory[inst_addr_reg+6], memory[inst_addr_reg+7], memory[inst_addr_reg+8], memory[inst_addr_reg+9], memory[inst_addr_reg+10], memory[inst_addr_reg+11], memory[inst_addr_reg+12], memory[inst_addr_reg+13], memory[inst_addr_reg+14], memory[inst_addr_reg+15]);
end // for second loop
$fclose(file);
end // initial
// Read data
assign data_out = (mem_read) ? {memory[data_addr+3], memory[data_addr+2], memory[data_addr+1], memory[data_addr]} : 32'b0;
//write data
always @ (posedge mem_write or data_addr or data_in)
begin
if (mem_write ==1) begin
memory[data_addr+3] <= data_in[31:24];
memory[data_addr+2] <= data_in[23:16];
memory[data_addr+1] <= data_in[15:8];
memory[data_addr] <= data_in[7:0];
end
end
// Read instruction
assign instr = {memory[inst_addr+3], memory[inst_addr+2], memory[inst_addr+1], memory[inst_addr]} ;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T sqr(const T &a) { return a * a; } template <typename T> inline int nread(vector<T> &a) { int n; cin >> n; a.clear(); a.resize(n); for (int i = 0; i < n; i++) cin >> a[i]; return n; } template <typename T> inline void nwread(int n, vector<T> &a) { a.clear(); a.resize(n); for (int i = 0; i < n; i++) cin >> a[i]; } const int N = 3001; int gr[N][N], cg[N]; int res[N * N]; pair<int, int> que[N * N]; int main() { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) cg[i] = 0; for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; gr[x][cg[x]++] = y; gr[y][cg[y]++] = x; } set<pair<pair<int, int>, int> > zapr; for (int i = 0; i < k; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); x--; y--; z--; zapr.insert(make_pair(make_pair(x, y), z)); } map<pair<int, int>, int> path; int qi = 0, qj = 1; que[0] = make_pair(-1, 0); while (qi < qj) { pair<int, int> tek = que[qi++]; int pv = tek.first, tv = tek.second; vector<int> nreb; for (int i = 0; i < cg[tv];) { int fv = gr[tv][i]; if (zapr.count(make_pair(tek, fv))) i++; else { que[qj++] = make_pair(tv, fv); path[make_pair(tv, fv)] = pv; if (fv == n - 1) { int lr = 2; res[0] = fv; res[1] = tv; while (tv != 0) { pv = path[make_pair(tv, fv)]; res[lr++] = pv; fv = tv; tv = pv; } reverse(res, res + lr); cout << lr - 1 << endl; for (int i = 0; i < lr; i++) printf( %d , res[i] + 1); return 0; } if (cg[tv]) gr[tv][i] = gr[tv][cg[tv] - 1]; cg[tv]--; } } } cout << -1; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_7x16_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_7x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [6:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [6:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [6:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [6:0] q = sub_wire3[6:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 7,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "7"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "7"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL "data[6..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL "q[6..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V
|
/*
Copyright (C) 2016
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : Clock Domain Crossing Buffer
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module LTZ_CDCB #(
parameter WIDTH = 1,
parameter [WIDTH -1:0] INITVAL = {WIDTH{1'b0}}
) (
input rst_n ,
input clk ,
input [WIDTH -1:0] din ,
output reg [WIDTH -1:0] dout
);
reg [WIDTH -1:0] buff;
always @(posedge clk or negedge rst_n)
if (!rst_n)
{dout, buff} <= {INITVAL, INITVAL};
else
{dout, buff} <= {buff, din};
//
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 12; int rows, cols, k, n; char mat[MAXN][MAXN]; int sol = 0; int Calc(int a, int b, int c, int d) { int ret = 0; for (int i = a; i <= c; i++) { for (int j = b; j <= d; j++) ret += (mat[i][j] == # ); } return ret; } int main() { scanf( %d %d %d %d , &rows, &cols, &n, &k); for (int i = 0; i <= rows; i++) for (int j = 0; j <= cols; j++) mat[i][j] = . ; for (int i = 0; i < n; i++) { int x, y; scanf( %d %d , &x, &y); mat[x][y] = # ; } for (int i = 1; i <= rows; i++) { for (int j = 1; j <= cols; j++) { for (int ii = i; ii <= rows; ii++) { for (int jj = j; jj <= cols; jj++) { int sum = Calc(i, j, ii, jj); sol += (sum >= k); } } } } printf( %d n , sol); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); int n; cin >> n; int pass = 0, ans = 0; while (n) { ans += n; ans += (pass * (n - 1)); pass++; --n; } cout << ans; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:26:40 08/18/2012
// Design Name: timing_synch_fsm
// Module Name: /home/glenn/Documents/Firmware/FONT5_base/ISE10/FONT5_base/timing_sync_fsm_tb.v
// Project Name: FONT5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timing_synch_fsm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timing_sync_fsm_tb;
// Inputs
reg fastClk;
reg slowClk;
reg rst;
reg trigSyncExt;
reg trigSyncExt_edge_sel;
reg trig;
reg [11:0] trig_delay;
reg [6:0] sample_hold_off;
reg [9:0] num_smpls;
reg [7:0] trigSync_size_b;
reg use_trigSyncExt_b;
// Outputs
wire store_strb;
wire adc_powerup;
wire adc_align_en;
wire trig_led_strb;
wire clk2_16_led_strb;
wire [3:0] state;
// Instantiate the Unit Under Test (UUT)
timing_synch_fsm uut (
.fastClk(fastClk),
.slowClk(slowClk),
.rst(rst),
.trigSyncExt(trigSyncExt),
.trigSyncExt_edge_sel(trigSyncExt_edge_sel),
.trig(trig),
.trig_delay(trig_delay),
.sample_hold_off(sample_hold_off),
.num_smpls(num_smpls),
.trigSync_size_b(trigSync_size_b),
.use_trigSyncExt_b(use_trigSyncExt_b),
.store_strb(store_strb),
.adc_powerup(adc_powerup),
.adc_align_en(adc_align_en),
.trig_led_strb(trig_led_strb),
.clk2_16_led_strb(clk2_16_led_strb),
.state(state)
);
initial begin
// Initialize Inputs
fastClk = 0;
slowClk = 0;
rst = 0;
trigSyncExt = 0;
trigSyncExt_edge_sel = 0;
trig = 0;
trig_delay = 0;
sample_hold_off = 0;
num_smpls = 165;
trigSync_size_b = 0;
use_trigSyncExt_b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
trig_delay = 10;
sample_hold_off = 50;
#150 trig =1;
#200 trig =0;
end
always # 1.4 fastClk = ~fastClk; //357 MHz clock
//always # 2.5 fastClk = ~fastClk; //200 MHz clock
always # 12.5 slowClk = ~slowClk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n, sum = 0, maxi, mini, start, end; ; cin >> a >> b >> n; mini = min(a, b); maxi = max(a, b); if (n <= min(a, b)) { cout << n + 1; } else { if (mini + maxi >= n) { int k = n - maxi; if (k < 0) { k = 0; } sum = mini - k + 1; } cout << sum; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 100010; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long n, m, p, a[N], b[N], q[N], yue[N], miu[N], f[N], tot; long long ans; long long power(long long a, long long b, long long m) { long long re = 1; while (b) { if (b & 1) re = (long long)re * a % m; a = (long long)a * a % m; b >>= 1; } return re; } long long calc(long long x) { long long i, j, k, l; for (i = 1; i <= tot; i++) if (power(x, yue[i], p) == 1) return yue[i]; } int main() { long long i, j, k; scanf( %I64d%I64d%I64d , &n, &m, &p); for (i = 1; i * i <= p - 1; i++) { if ((p - 1) % i == 0) { yue[++tot] = i; if (i * i < p - 1) yue[++tot] = (p - 1) / i; } } sort(yue + 1, yue + tot + 1); for (i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (i = 1, k = 0; i <= m; i++) { scanf( %I64d , &j); k = gcd(k, j); } k = gcd(k, p - 1); for (i = 1; i <= n; i++) { q[i] = calc(a[i]); a[i] = (p - 1) * gcd(q[i], k) / q[i]; } for (i = 1; i <= tot; i++) for (j = 1; j <= n; j++) if (yue[i] % a[j] == 0) { f[i] = 1; break; } for (i = 1; i <= tot; i++) { ans += (f[i] - miu[i]) * ((p - 1) / yue[i]); for (j = i + 1; j <= tot; j++) if (yue[j] % yue[i] == 0) miu[j] += (f[i] - miu[i]); miu[i] += (f[i] - miu[i]); } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_TB_V
`define SKY130_FD_SC_LP__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 40500; int h, lgn, n, t, r, x, y, a[N], dis[N], lp[N], dp[N][17]; vector<pair<int, int> > e1, e2; vector<int> g[N]; bool mark[N]; int lg(int xx) { int l = 0; while (xx > 1) { xx /= 2; ++l; } return l; } void bfs(int d, vector<int> &v) { vector<int> w; for (int i = 0; i < v.size(); i++) { for (int j = 0; j < g[v[i]].size(); j++) { if (dis[g[v[i]][j]] == INT32_MAX) { dis[g[v[i]][j]] = d + 1; w.push_back(g[v[i]][j]); } } } if (!w.empty()) bfs(d + 1, w); } void dfs(int v) { mark[v] = true; for (int i = 0; i < g[v].size(); i++) { if (!mark[g[v][i]]) { dis[g[v][i]] = dis[v] + 1; dp[g[v][i]][0] = v; for (int j = 1; j <= lgn; j++) dp[g[v][i]][j] = dp[dp[g[v][i]][j - 1]][j - 1]; dfs(g[v][i]); } } } int par(int v, int p) { while (p > 0) { int pp = p & (-p); v = dp[v][lg(pp)]; p -= pp; } return v; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> h >> t >> r >> x; int hh, tt; for (int i = 0; i < x; i++) { cin >> hh >> tt; e1.push_back({hh, tt}); } cin >> y; for (int i = 0; i < y; i++) { cin >> hh >> tt; e2.push_back({hh, tt}); } for (int i = r; i >= 0; i--) { for (int j = r - i; j >= 0; j--) { for (int k = 0; k < min(x, i); k++) { if ((i - k - 1 + e1[k].first + j + e1[k].second) <= r) g[(r + 1) * i + j].push_back((i - k - 1 + e1[k].first) * (r + 1) + j + e1[k].second); } for (int k = 0; k < min(y, j); k++) { if ((i + e2[k].first + j - k - 1 + e2[k].second) <= r) g[(r + 1) * i + j].push_back((i + e2[k].first) * (r + 1) + j - k - 1 + e2[k].second); } } } n = (r + 1) * (r + 1); lgn = lg(n); int s = h * (r + 1) + t; fill(dis, dis + n, INT32_MAX); vector<int> v; v.push_back(s); dis[s] = 0; bfs(0, v); if (dis[0] != INT32_MAX) { cout << Ivan n << dis[0]; return 0; } for (int i = 0; i < n; i++) fill(dp[i], dp[i] + 17, s); dfs(s); for (int i = 0; i < n; i++) { if (dis[i] != INT32_MAX) { for (int j = 0; j < g[i].size(); j++) { if (dis[g[i][j]] <= dis[i] && g[i][j] == par(i, dis[i] - dis[g[i][j]])) { cout << Draw ; return 0; } } } } for (int i = 0; i < n; i++) { if (dis[i] != INT32_MAX) { for (int j = 0; j < g[i].size(); j++) ++a[g[i][j]]; } } vector<int> w; w.push_back(s); while (!w.empty()) { int u = w[w.size() - 1]; w.pop_back(); for (int i = 0; i < g[u].size(); i++) { --a[g[u][i]]; lp[g[u][i]] = max(lp[g[u][i]], lp[u] + 1); if (a[g[u][i]] == 0) w.push_back(g[u][i]); } } int ans = 0; for (int i = 0; i < n; i++) ans = max(ans, lp[i]); cout << Zmey n << ans + 1; }
|
#include <bits/stdc++.h> using namespace std; int n, m; long long int arr[100050]; vector<vector<long long int>> v(100050); int main() { cin >> n >> m; for (int i = 1; i <= m; i++) cin >> arr[i]; for (int i = 1; i <= m; i++) { if (i > 1 && arr[i - 1] != arr[i]) v[arr[i]].push_back(arr[i - 1]); if (i < m && arr[i] != arr[i + 1]) v[arr[i]].push_back(arr[i + 1]); } long long int sum = 0, ans; for (int i = 1; i < m; i++) sum += abs(arr[i] - arr[i + 1]); ans = sum; for (int i = 1; i <= n; i++) { if (v[i].size() == 0) continue; sort(v[i].begin(), v[i].end()); long long int y = v[i][v[i].size() / 2]; long long int before = 0, after = 0; for (int x : v[i]) { before += abs(x - i); after += abs(y - x); } ans = min(ans, sum - before + after); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int m; int count; int sum; while (scanf( %d%d , &n, &m) != EOF) { count = 0; sum = 0; if (n == m) { printf( 0 ); printf( n ); continue; } while (n < m) { n = n * 2; count++; } int k = n - m; sum += count; while (count != -1 && k != 0) { while (k >= (1 << count)) { sum += k / (1 << count); k = k - (k / (1 << count)) * (1 << count); } count--; } printf( %d n , sum); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000100; const int INF = (1 << 29); const double EPS = 0.000000001; const double Pi = acos(-1.0); int n; long long x[maxn]; int main() { while (cin >> n) { for (int i = 1; i <= n; i++) scanf( %I64d , &x[i]); sort(x + 1, x + n + 1); long long ans = 1e12; for (int i = 1; i + n / 2 <= n; i++) { long long a = x[i], b = x[i + n / 2]; ans = min(ans, b - a); } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> int getmin(int a, int b) { if (a == -1) return b; else if (b == -1) return a; else return a < b ? a : b; } int solve(int a, int b) { int tot = 0; while (a != 1 || b != 1) { tot++; if (!a || !b) return -1; if (a > b) a -= b; else b -= a; } return tot; } int main() { int n, ans = -1; scanf( %d , &n); for (int a = 1; a < n; a++) ans = getmin(ans, solve(a, n)); if (ans == -1) ans++; printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int compare(const void* a, const void* b) { return ((*(pair<long long, long long>*)a).first - (*(pair<long long, long long>*)b).first); } string alfabet = abcdefghijklmnopqrstuvwxyz ; int main() { long long n, x1, x2, k, b; cin >> n; cin >> x1 >> x2; vector<pair<double, double> > lines; pair<double, double> line; for (int i = 0; i < n; ++i) { cin >> k >> b; line.first = k * x1 + b; line.second = k * x2 + b; lines.push_back(line); } sort(lines.begin(), lines.end()); for (int i = 0; i < n - 1; ++i) { if (lines[i].second > lines[i + 1].second && lines[i].first != lines[i + 1].first) { cout << YES ; return 0; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[110], b[110], n; int main() { int t; cin >> t; while (t--) { cin >> n; for (register int i = 1; i <= n; i++) cin >> a[i]; for (register int i = 1; i <= n; i++) cin >> b[i]; sort(a + 1, a + n + 1); sort(b + 1, b + n + 1); for (register int i = 1; i <= n; i++) cout << a[i] << ; puts( ); for (register int i = 1; i <= n; i++) cout << b[i] << ; puts( ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; for (int i = s.size() - 1; i >= 0; i--) { int x = s[i] - 0 ; if (x >= 5) printf( -O| ); else printf( O-| ); x = x % 5; if (x == 0) printf( -OOOO n ); else if (x == 1) printf( O-OOO n ); else if (x == 2) printf( OO-OO n ); else if (x == 3) printf( OOO-O n ); else printf( OOOO- n ); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6; long long int x[maxn]; long long int sum, ans; map<long long int, long long int> table[27]; string s; int main() { for (int i = 1; i <= 26; i++) cin >> x[i]; cin >> s; for (int i = 0; i < s.size(); i++) { ans += table[s[i] - a + 1][sum]; sum += x[s[i] - a + 1]; table[s[i] - a + 1][sum]++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int power(int num1, int num2) { int ans = 1; for (int i = 0; i < num2; i++) { ans *= num1; } return ans; } int main() { string str; int num1, help = 0; cin >> num1 >> str; for (int i = 0; i < str.size(); i++) { help += power(10, i) * (str[i] - 0 ); } cout << help + num1; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 200100; struct node { int x, y, z; } a[mx]; struct nod { int id, x; } b[mx]; int fa[mx]; long long num[mx]; long long ans[mx]; int n, m; bool cmp(node x, node y) { return x.z < y.z; } bool cmp1(nod x, nod y) { return x.x < y.x; } int find(int x) { if (x != fa[x]) { return fa[x] = find(fa[x]); } return fa[x]; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) fa[i] = i, num[i] = 1; for (int i = 1; i < n; i++) { cin >> a[i].x >> a[i].y >> a[i].z; } for (int i = 1; i <= m; i++) { cin >> b[i].x; b[i].id = i; } sort(a + 1, a + n, cmp); sort(b + 1, b + m + 1, cmp1); int l = 1; long long sum = 0; for (int i = 1; i < n; i++) { while (l <= m && a[i].z > b[l].x) { ans[b[l].id] = sum; l++; } int x = find(a[i].x); int y = find(a[i].y); sum += num[y] * num[x]; fa[x] = y; num[y] += num[x]; } while (l <= m) { if (a[n - 1].z <= b[l].x) { ans[b[l].id] = sum; } l++; } for (int i = 1; i <= m; i++) cout << ans[i] << n [i == m]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t = 1; while (t--) { int n; cin >> n; map<int, vector<int>> m; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; m[v[i]].push_back(i); } vector<pair<int, int>> res; for (auto p : m) { vector<int> tmp = p.second; if (tmp.size() == 1) { res.push_back(make_pair(p.first, 0)); continue; } int d = tmp[1] - tmp[0]; int flag = 0; for (int i = 1; i < tmp.size() - 1; i++) { int curr = tmp[i + 1] - tmp[i]; if (curr != d) { flag = 1; break; } } if (flag == 1) { continue; } res.push_back(make_pair(p.first, d)); } sort((res).begin(), (res).end()); cout << res.size() << endl; for (auto p : res) { cout << p.first << << p.second << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HD__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_SYMBOL_V
|
// avm.v
//
// AVM in Verilog
//
// This is an implementation of AVM in C for experimenation purposes.
// It is both an AVM interpretr and an assembler for the instruction set.
//
// (C) 2016 David J. Goehrig
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE.
//
`include "avm.vh"
module avm (
// io
input clock_in, // clock
input reset_in, // reset
input [`PINS-1:0] io_in, // hardware input
input [`BITS-1:0] data_in, // ram data out
input [`BITS-1:0] ip_in, // rom data in
output read_out, // read active
output write_out, // write active
output [`BITS-1:0] src_addr_out, // source ram addr
output [`BITS-1:0] dst_addr_out, // dest ram addr
output [`BITS-1:0] ip_addr_out, // rom address
output [`BITS-1:0] data_out, // dst data out
output [`PINS-1:0] io_out); // hardware output
// instruction
wire instre; // instr read enable
wire [`BITS-1:0] instr; // instruction
wire [`BITS-1:0] imm = { 1'b0, instr[`BITS-2:0] }; // immediate value
reg [`BITS-1:0] ip; // instruction pointer
reg [`BITS-1:0] flags; // flags register
// stacks
stack rs();
stack ds();
// memory access
reg [`BITS-1:0] dst; // destination address
reg [`BITS-1:0] src; // source address
wire dste; // write enable
wire srce; // read enable
`include "rom.v"
`include "ram.v"
// clock events
// TODO fetch instruction from ROM
// TODO update data stack
// TODO update return stack
// TODO RAM reads
// TODO IO reads
// TODO ALU instructions
// TODO RAM writes
// TODO IO writes
// TODO update data stack pointers
// TODO update return stack pointers
// TODO update instruction pointer
endmodule;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_4_V
`define SKY130_FD_SC_MS__OR4BB_4_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_4 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_4 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_4_V
|
#include <bits/stdc++.h> template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } using namespace std; int main() { cin.tie(NULL), ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { int a, b; cin >> a >> b; if (a > b) { if ((b - a) % 2 == 0) cout << 1 << n ; else cout << 2 << n ; } else if (a == b) cout << 0 << n ; else { if ((b - a) % 2 != 0) cout << 1 << n ; else cout << 2 << n ; } } }
|
// See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output logic [7:0] count,
input logic clk,
input logic reset,
input logic start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output logic clk,
output logic reset,
output logic start,
input logic [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] count; // From submod0 of autoinst_interface_sub.v
// End of automatics
my_svi my_svi_noport_upper_decl ();
autoinst_interface_sub submod0 (/*AUTOINST*/
// Interfaces
.my_svi_port (my_svi_port.master),
.my_svi_noport (my_svi_noport),
.my_svi_noport_upper_decl(my_svi_noport_upper_decl),
// Outputs
.count (count[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.start (start));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
`include "bsg_defines.v"
module bsg_wormhole_router_output_control
#(parameter `BSG_INV_PARAM(input_dirs_p))
(input clk_i
, input reset_i
// this input channel has a header packet at the head of the FIFO for this output
, input [input_dirs_p-1:0] reqs_i
// the input channel finished a packet on the previous cycle
// note: it is up to this module to verify that the input channel was allocated to this output channel
, input [input_dirs_p-1:0] release_i
// from input fifos
, input [input_dirs_p-1:0] valid_i
, output [input_dirs_p-1:0] yumi_o
// channel outputs
, input ready_i
, output valid_o
, output [input_dirs_p-1:0] data_sel_o
);
wire [input_dirs_p-1:0] scheduled_r, scheduled_with_release, scheduled_n, grants_lo;
bsg_dff_reset #(.width_p(input_dirs_p)) scheduled_reg (.clk_i, .reset_i, .data_i(scheduled_n), .data_o(scheduled_r));
assign scheduled_with_release = scheduled_r & ~release_i;
wire free_to_schedule = !scheduled_with_release;
bsg_round_robin_arb
#(.inputs_p(input_dirs_p)) brr
(.clk_i
,.reset_i
,.grants_en_i (free_to_schedule) // ports are all free
,.reqs_i (reqs_i) // requests from input ports
,.grants_o (grants_lo) // output grants, takes into account grants_en_i
,.sel_one_hot_o() // output grants, does not take into account grants_en_i
,.v_o () // some reqs_i was set
,.tag_o ()
// make sure to only allocate the port if we succeeded in transmitting the header
// otherwise the input will try to allocate again on the next cycle
,.yumi_i (free_to_schedule & ready_i & valid_o) // update round_robin
);
assign scheduled_n = grants_lo | scheduled_with_release;
assign data_sel_o = scheduled_n;
assign valid_o = (|(scheduled_n & valid_i));
assign yumi_o = ready_i ? (scheduled_n & valid_i) : '0;
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_router_output_control)
|
#include <bits/stdc++.h> using namespace std; char a[514][514]; int n, m; int ID[514][514]; int RID[20005]; int idt[20005]; int g[20005]; int FIND(int x) { return g[x] == x ? x : (g[x] = FIND(g[x])); } void UNION(int x, int y) { x = FIND(x); y = FIND(y); g[x] = y; } int edge(int x, int y) { if (FIND(x) == FIND(y)) return 1; UNION(x, y); return 0; } long long P[2][514][514]; int MOD = 1e9 + 7; int nid = 0, Pid[2] = {}; void bridge(int x, int y) { x = FIND(x); y = FIND(y); if (x == y) return; P[idt[x]][RID[x]][RID[x]]++; P[idt[x]][RID[x]][RID[y]]--; P[idt[x]][RID[y]][RID[x]]--; P[idt[x]][RID[y]][RID[y]]++; } long long inv(long long x, long long y, long long p, long long q, long long r, long long s) { if (y == 0) return (p % MOD + MOD) % MOD; return inv(y, x % y, r, s, p - r * (x / y), q - s * (x / y)); } long long det(long long F[514][514], int D) { long long ans = 1; for (int i = 0; i < D; i++) { int r = i; while (r < D && F[r][i] == 0) ++r; if (r >= D) return 0; if (r != i) ans = ans * (MOD - 1) % MOD; for (int j = i; j < D; j++) swap(F[r][j], F[i][j]); ans = ans * F[i][i] % MOD; long long t = inv(F[i][i], MOD, 1, 0, 0, 1); for (int j = i; j < D; j++) F[i][j] = (F[i][j] * t) % MOD; for (int r = i + 1; r < D; r++) if (F[r][i] != 0) { long long s = F[r][i]; for (int j = i; j < D; j++) { F[r][j] = (F[r][j] - s * F[i][j]) % MOD; if (F[r][j] < 0) F[r][j] += MOD; } } } return ans; } int main(void) { scanf( %d%d%d , &n, &m, &MOD); assert(1 <= n && n <= 100); assert(1 <= m && m <= 100); for (int i = 0; i < n; i++) scanf( %s , a[i]); for (int i = 0; i < n; i++) assert(strlen(a[i]) == m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) assert(a[i][j] == / || a[i][j] == || a[i][j] == * ); for (int i = 0; i <= n; i++) for (int j = 0; j <= m; j++) { ID[i][j] = ++nid; g[nid] = nid; idt[nid] = (i % 2) ^ (j % 2); } int fail = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (a[i][j] == / ) { fail |= edge(ID[i + 1][j], ID[i][j + 1]); } else if (a[i][j] == ) { fail |= edge(ID[i][j], ID[i + 1][j + 1]); } } if (fail) { puts( 0 ); return 0; } for (int i = 0; i <= n; i++) for (int j = 0; j <= m; j++) if (FIND(ID[i][j]) == ID[i][j]) { RID[ID[i][j]] = Pid[idt[ID[i][j]]]++; } int cnt = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == * ) { bridge(ID[i][j], ID[i + 1][j + 1]); bridge(ID[i + 1][j], ID[i][j + 1]); ++cnt; } } } assert(cnt <= 200); for (int z = 0; z < 2; z++) for (int i = 0; i < Pid[z]; i++) for (int j = 0; j < Pid[z]; j++) P[z][i][j] = (P[z][i][j] + MOD) % MOD; long long ans = det(P[0], Pid[0] - 1) + det(P[1], Pid[1] - 1); printf( %d n , (int)(ans % MOD)); return 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v1_9_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
module Pipeline_tb ();
reg clk, rst_n, rx;
reg [7:0] switch;
wire tx;
wire [7:0] led;
wire [6:0] digi[3:0];
CPU cpu(
.clk(clk), .rst_n(rst_n),
.switch(switch),
.led(led),
.rx(rx), .tx(tx),
.digi_out1(digi[0]),
.digi_out2(digi[1]),
.digi_out3(digi[2]),
.digi_out4(digi[3])
);
initial begin
clk = 1'b1;
rst_n = 1'b1;
rx = 1'b1;
switch = 8'h69;
#1 rst_n = 1'b0;
#1 rst_n = 1'b1;
#1 rx = 1'b0; // start
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b1;// end
#104166 rx = 1'b0;// start
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b1;// end
end
initial
forever #18.5 clk <= ~clk;
endmodule
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output [width_p-1:0] data_o
);
wire unused = reset_i;
// we use a 2 port RF because the 1 port RF
// does not support bit-level masking for 80-bit width
// alternatively we could instantiate 2 40-bit 1rw RF's
`bsg_mem_1rf_sync_macro_bit(256,4,8,4) else
`bsg_mem_1rf_sync_macro_bit(256,30,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,32,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,34,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,36,8,2) else
`bsg_mem_1rw_sync_macro_bit(64,80,6,1) else
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
// synopsys translate_off
always_ff @(posedge clk_i)
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// DMA Request Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_dma_req.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_dma_req.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack);
input clk, rst;
input [7:0] cfg;
input [1:0] status;
input full_empty;
output dma_req;
input dma_ack;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg dma_req_d;
reg dma_req_r1;
reg dma_req;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(cfg or status or full_empty)
case(cfg[5:4]) // synopsys parallel_case full_case
// REQ = Ch_EN & DMA_EN & Status
// 1/4 full/empty
2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0));
// 1/2 full/empty
2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3));
2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty;
endcase
always @(posedge clk)
dma_req_r1 <= #1 dma_req_d & !dma_ack;
always @(posedge clk or negedge rst)
if(!rst) dma_req <= #1 1'b0;
else
if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1;
else
if(dma_ack) dma_req <= #1 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; cin.get(); vector<string> v(n); for (int i = 0; i < n; i++) getline(cin, v[i]); vector<int> p(k); for (int i = 0; i < k; i++) p[i] = i; int minDiff = INT_MAX; do { int minNum, maxNum; minNum = INT_MAX; maxNum = INT_MIN; for (int i = 0; i < n; i++) { int num = 0; for (int j = 0; j < k; j++) num = num * 10 + v[i][p[j]] - 0 ; if (num < minNum) minNum = num; if (num > maxNum) maxNum = num; } minDiff = min(minDiff, maxNum - minNum); } while (next_permutation(p.begin(), p.end())); cout << minDiff; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x; bool X[26]; int mat[6][6]; int niz[26]; int sum; bool check() { sum = 0; for (int i = 0; i < n; i++) sum += mat[i][0]; for (int j = 1; j < n; j++) { int st = 0; for (int i = 0; i < n; i++) st += mat[i][j]; if (st != sum) return false; } for (int i = 0; i < n; i++) { int st = 0; for (int j = 0; j < n; j++) st += mat[i][j]; if (st != sum) return false; } int sz = 0; for (int i = 0; i < n; i++) { sz += mat[i][i]; } if (sz != sum) return false; sz = 0; for (int i = 0; i < n; i++) { sz += mat[i][n - i - 1]; } if (sz != sum) return false; return true; } vector<pair<int, int> > pos; vector<int> vals; int empty_cnt = 0; int main() { scanf( %d , &n); for (int i = 0; i < n * n; i++) { scanf( %d , &niz[i]); vals.push_back(i); pos.push_back(make_pair(i / n, i % n)); } do { for (int i = 0; i < pos.size(); i++) { mat[pos[i].first][pos[i].second] = niz[vals[i]]; } if (check()) { break; } } while (next_permutation(vals.begin(), vals.end())); printf( %d n , sum); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { printf( %d , mat[i][j]); } printf( n ); } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// Filename: afi_mux.v
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// During calibration, mux_sel = 1, sequencer AFI signals are selected
// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module afi_mux_ddrx (
clk,
mux_sel,
afi_addr,
afi_ba,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dm,
afi_wlat,
afi_rlat,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_cal_success,
afi_cal_fail,
seq_mux_addr,
seq_mux_ba,
seq_mux_cs_n,
seq_mux_cke,
seq_mux_odt,
seq_mux_ras_n,
seq_mux_cas_n,
seq_mux_we_n,
seq_mux_dm,
seq_mux_dqs_burst,
seq_mux_wdata,
seq_mux_wdata_valid,
seq_mux_rdata_en,
seq_mux_rdata_en_full,
seq_mux_rdata,
seq_mux_rdata_valid,
phy_mux_addr,
phy_mux_ba,
phy_mux_cs_n,
phy_mux_cke,
phy_mux_odt,
phy_mux_ras_n,
phy_mux_cas_n,
phy_mux_we_n,
phy_mux_dm,
phy_mux_wlat,
phy_mux_rlat,
phy_mux_dqs_burst,
phy_mux_wdata,
phy_mux_wdata_valid,
phy_mux_rdata_en,
phy_mux_rdata_en_full,
phy_mux_rdata,
phy_mux_rdata_valid,
phy_mux_cal_success,
phy_mux_cal_fail
);
parameter AFI_ADDR_WIDTH = 0;
parameter AFI_BANKADDR_WIDTH = 0;
parameter AFI_CS_WIDTH = 0;
parameter AFI_CLK_EN_WIDTH = 0;
parameter AFI_ODT_WIDTH = 0;
parameter AFI_WLAT_WIDTH = 0;
parameter AFI_RLAT_WIDTH = 0;
parameter AFI_DM_WIDTH = 0;
parameter AFI_CONTROL_WIDTH = 0;
parameter AFI_DQ_WIDTH = 0;
parameter AFI_WRITE_DQS_WIDTH = 0;
parameter AFI_RATE_RATIO = 0;
parameter MRS_MIRROR_PING_PONG_ATSO = 0;
input clk;
input mux_sel;
// AFI inputs from the controller
input [AFI_ADDR_WIDTH-1:0] afi_addr;
input [AFI_BANKADDR_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CS_WIDTH-1:0] afi_cs_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_DM_WIDTH-1:0] afi_dm;
output [AFI_WLAT_WIDTH-1:0] afi_wlat;
output [AFI_RLAT_WIDTH-1:0] afi_rlat;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DQ_WIDTH-1:0] afi_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_RATE_RATIO-1:0] afi_rdata_en;
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] afi_rdata;
output [AFI_RATE_RATIO-1:0] afi_rdata_valid;
output afi_cal_success;
output afi_cal_fail;
// AFI inputs from the sequencer
input [AFI_ADDR_WIDTH-1:0] seq_mux_addr;
input [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba;
input [AFI_CS_WIDTH-1:0] seq_mux_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke;
input [AFI_ODT_WIDTH-1:0] seq_mux_odt;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n;
input [AFI_DM_WIDTH-1:0] seq_mux_dm;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_dqs_burst;
input [AFI_DQ_WIDTH-1:0] seq_mux_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_wdata_valid;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] seq_mux_rdata;
output [AFI_RATE_RATIO-1:0] seq_mux_rdata_valid;
// Mux output to the rest of the PHY logic
output [AFI_ADDR_WIDTH-1:0] phy_mux_addr;
output [AFI_BANKADDR_WIDTH-1:0] phy_mux_ba;
output [AFI_CS_WIDTH-1:0] phy_mux_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_mux_cke;
output [AFI_ODT_WIDTH-1:0] phy_mux_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_we_n;
output [AFI_DM_WIDTH-1:0] phy_mux_dm;
input [AFI_WLAT_WIDTH-1:0] phy_mux_wlat;
input [AFI_RLAT_WIDTH-1:0] phy_mux_rlat;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_dqs_burst;
output [AFI_DQ_WIDTH-1:0] phy_mux_wdata;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_wdata_valid;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en_full;
input [AFI_DQ_WIDTH-1:0] phy_mux_rdata;
input [AFI_RATE_RATIO-1:0] phy_mux_rdata_valid;
input phy_mux_cal_success;
input phy_mux_cal_fail;
reg [AFI_ADDR_WIDTH-1:0] afi_addr_r;
reg [AFI_BANKADDR_WIDTH-1:0] afi_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
reg [AFI_CS_WIDTH-1:0] afi_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
reg [AFI_ADDR_WIDTH-1:0] seq_mux_addr_r;
reg [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke_r;
reg [AFI_CS_WIDTH-1:0] seq_mux_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] seq_mux_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n_r;
always @(posedge clk)
begin
afi_addr_r <= afi_addr;
afi_ba_r <= afi_ba;
afi_cs_n_r <= afi_cs_n;
afi_cke_r <= afi_cke;
afi_odt_r <= afi_odt;
afi_ras_n_r <= afi_ras_n;
afi_cas_n_r <= afi_cas_n;
afi_we_n_r <= afi_we_n;
seq_mux_addr_r <= seq_mux_addr;
seq_mux_ba_r <= seq_mux_ba;
seq_mux_cs_n_r <= seq_mux_cs_n;
seq_mux_cke_r <= seq_mux_cke;
seq_mux_odt_r <= seq_mux_odt;
seq_mux_ras_n_r <= seq_mux_ras_n;
seq_mux_cas_n_r <= seq_mux_cas_n;
seq_mux_we_n_r <= seq_mux_we_n;
end
wire [AFI_DQ_WIDTH-1:0] afi_wdata_int;
assign afi_rdata = phy_mux_rdata;
assign afi_wdata_int = afi_wdata;
assign afi_rdata_valid = mux_sel ? {AFI_RATE_RATIO{1'b0}} : phy_mux_rdata_valid;
assign seq_mux_rdata = phy_mux_rdata;
assign seq_mux_rdata_valid = phy_mux_rdata_valid;
assign phy_mux_addr = mux_sel ? seq_mux_addr_r : afi_addr_r;
assign phy_mux_ba = mux_sel ? seq_mux_ba_r : afi_ba_r;
assign phy_mux_cs_n = mux_sel ? seq_mux_cs_n_r : afi_cs_n_r;
assign phy_mux_cke = mux_sel ? seq_mux_cke_r : afi_cke_r;
assign phy_mux_odt = mux_sel ? seq_mux_odt_r : afi_odt_r;
assign phy_mux_ras_n = mux_sel ? seq_mux_ras_n_r : afi_ras_n_r;
assign phy_mux_cas_n = mux_sel ? seq_mux_cas_n_r : afi_cas_n_r;
assign phy_mux_we_n = mux_sel ? seq_mux_we_n_r : afi_we_n_r;
assign phy_mux_dm = mux_sel ? seq_mux_dm : afi_dm;
assign afi_wlat = phy_mux_wlat;
assign afi_rlat = phy_mux_rlat;
assign phy_mux_dqs_burst = mux_sel ? seq_mux_dqs_burst : afi_dqs_burst;
assign phy_mux_wdata = mux_sel ? seq_mux_wdata : afi_wdata_int;
assign phy_mux_wdata_valid = mux_sel ? seq_mux_wdata_valid : afi_wdata_valid;
assign phy_mux_rdata_en = mux_sel ? seq_mux_rdata_en : afi_rdata_en;
assign phy_mux_rdata_en_full = mux_sel ? seq_mux_rdata_en_full : afi_rdata_en_full;
assign afi_cal_success = phy_mux_cal_success;
assign afi_cal_fail = phy_mux_cal_fail;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_33x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_33x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [32:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [32:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [32:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [32:0] q = sub_wire2[32:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 33,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "33"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "33"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "33"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 33 0 INPUT NODEFVAL data[32..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 33 0 OUTPUT NODEFVAL q[32..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 33 0 data 0 0 33 0
// Retrieval info: CONNECT: q 0 0 33 0 @q 0 0 33 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_33x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_16_V
`define SKY130_FD_SC_LS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_16_V
|
#include <bits/stdc++.h> using namespace std; const int N = 605; int n; vector<int> g[N]; map<vector<int>, int> memo; int ask(vector<int> &vs) { if (int((vs).size()) <= 1) return 0; sort((vs).begin(), (vs).end()); if (memo.count(vs)) return memo[vs]; cout << ? << int((vs).size()) << endl; for (int x = (0), qwerty = (int((vs).size())); x < qwerty; x++) { if (x) cout << ; cout << vs[x]; } cout << endl; int v; cin >> v; return memo[vs] = v; } pair<int, int> f(vector<int> vs1, vector<int> vs2, bool b) { if (int((vs1).size()) == 1 && int((vs2).size()) == 1) { if (!b) { vector<int> vs = {vs1[0], vs2[0]}; int v = ask(vs); if (!v) return {-1, -1}; } return {vs1[0], vs2[0]}; } vector<int> vs = vs1; for (int v : vs2) vs.push_back(v); int A, B, AB, abo; if (!b) A = ask(vs1), B = ask(vs2), AB = ask(vs), abo = AB - A - B; else abo = 1; if (!abo) return {-1, -1}; bool rev = 0; if (int((vs2).size()) == 1) swap(vs1, vs2), rev = 1; vector<int> vs2_0, vs2_1; for (int x = (0), qwerty = (int((vs2).size()) / 2); x < qwerty; x++) vs2_0.push_back(vs2[x]); for (int x = (int((vs2).size()) / 2), qwerty = (int((vs2).size())); x < qwerty; x++) vs2_1.push_back(vs2[x]); pair<int, int> tmp = f(vs1, vs2_0, 0); if (tmp.first == -1) tmp = f(vs1, vs2_1, 1); if (rev) swap(tmp.first, tmp.second); return tmp; } vector<int> cs[2]; int dep[N], par[N]; void dfs(int u, int p, int c) { cs[c].push_back(u); for (int v : g[u]) if (v != p) par[v] = u, dep[v] = dep[u] + 1, dfs(v, u, !c); } pair<int, int> solve(vector<int> vs) { vector<int> vs1, vs2; for (int x = (0), qwerty = (int((vs).size()) / 2); x < qwerty; x++) vs1.push_back(vs[x]); for (int x = (int((vs).size()) / 2), qwerty = (int((vs).size())); x < qwerty; x++) vs2.push_back(vs[x]); int A = ask(vs1), B = ask(vs2), AB = ask(vs), ABo = AB - A - B; if (A) return solve(vs1); if (B) return solve(vs2); assert(ABo > 0); return f(vs1, vs2, 0); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; vector<int> nused, used; for (int x = (1), qwerty = (n + 1); x < qwerty; x++) nused.push_back(x); random_shuffle((nused).begin(), (nused).end()); used.push_back(nused.back()); nused.pop_back(); for (int x = (1), qwerty = (n); x < qwerty; x++) { pair<int, int> tmp = f(used, nused, 0); int idx = -1; for (int i = (0), qwerty = (int((nused).size())); i < qwerty; i++) if (nused[i] == tmp.second) idx = i; assert(idx != -1); swap(nused.back(), nused[idx]); nused.pop_back(); used.push_back(tmp.second); sort((used).begin(), (used).end()); g[tmp.first].push_back(tmp.second); g[tmp.second].push_back(tmp.first); } dfs(1, 0, 0); if (ask(cs[0]) == 0 && ask(cs[1]) == 0) { cout << Y << int((cs[0]).size()) << endl; for (int x = (0), qwerty = (int((cs[0]).size())); x < qwerty; x++) { if (x) cout << ; cout << cs[0][x]; } cout << endl; } else { if (ask(cs[0]) == 0) swap(cs[0], cs[1]); pair<int, int> tmp = solve(cs[0]); assert(tmp.first != -1); vector<int> vs1, vs2; int u = tmp.first, v = tmp.second; while (u != v) { if (dep[u] < dep[v]) { vs2.push_back(v); v = par[v]; } else { vs1.push_back(u); u = par[u]; } } vs1.push_back(u); reverse((vs1).begin(), (vs1).end()); for (int v : vs2) vs1.push_back(v); cout << N << int((vs1).size()) << endl; for (int x = (0), qwerty = (int((vs1).size())); x < qwerty; x++) { if (x) cout << ; cout << vs1[x]; } cout << endl; } }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:dragster_configurator:1.0
// IP Revision: 1
(* X_CORE_INFO = "dragster_configurator,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_dragster_configurator_0_0,dragster_configurator,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_dragster_configurator_0_0,dragster_configurator,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=dragster_configurator,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_dragster_configurator_0_0 (
clk,
reset_n,
miso,
mosi,
sclk,
ss_n
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_n RST" *)
input wire reset_n;
input wire miso;
output wire mosi;
output wire sclk;
output wire [1 : 0] ss_n;
dragster_configurator inst (
.clk(clk),
.reset_n(reset_n),
.miso(miso),
.mosi(mosi),
.sclk(sclk),
.ss_n(ss_n)
);
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : MIG
// / / Filename : glbl.v
// /___/ /\ Date Last Modified : $Date: 2010/03/18 06:49:35 $
// \ \ / \ Date Created : Wed Aug 16 2006
// \___\/\___\
//
// Device : Virtex-5
// Design Name : DDR2
// Purpose : Used for intializing the simulation environment.
// Reference:
// Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; const long long N = 1000 + 5, L = 12, inf = LLONG_MAX; long long n, m, k; long long a[N][N], par[N * N], sz[N * N], res[N][N], hh, cnt; bool mark[N][N], vis[N][N]; long long mp[N * N]; vector<pair<long long, long long> > vec, all; set<long long> s; long long H[] = {0, 0, -1, 1}; long long G[] = {1, -1, 0, 0}; inline void er(long long x) { mp[x]--; if (mp[x] == 0) { s.erase(-x); } return; } inline void ad(long long x) { mp[x]++; if (mp[x] == 1) { s.insert(-x); } return; } long long find(long long a) { if (par[a] == a) return a; return par[a] = find(par[a]); } inline void _union(long long a, long long b) { a = find(a); b = find(b); if (a == b) return; if (sz[a] < sz[b]) swap(a, b); er(sz[a]); er(sz[b]); par[b] = a; sz[a] += sz[b]; ad(sz[a]); return; } void dfs(long long x, long long y) { vis[x][y] = 1; all.push_back({x, y}); for (long long k = 0; k < 4; k++) { long long i = x + H[k], j = y + G[k]; if (i >= 0 && j >= 0 && i < n && j < m) { if (!vis[i][j] && a[i][j] >= hh) { dfs(i, j); } } } return; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); ; cin >> n >> m >> k; for (long long i = 0; i < n * m; i++) par[i] = i, sz[i] = 1; s.insert(-1); mp[1] = n * m; for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) { cin >> a[i][j]; vec.push_back({a[i][j], i * m + j}); } sort(vec.begin(), vec.end(), greater<pair<long long, long long> >()); long long ans = -1, xx = -1, yy = -1; for (auto p : vec) { long long x = p.second / m, y = p.second % m, h = p.first; mark[x][y] = 1; for (long long k = 0; k < 4; k++) { long long i = x + H[k], j = y + G[k]; if (i >= 0 && j >= 0 && i < n && j < m && mark[i][j]) { _union(i * m + j, p.second); } } if (k % h == 0) { long long mx = sz[find(p.second)]; if (mx >= k / h) { ans = mx; hh = h; xx = x; yy = y; break; } } } if (ans == -1) return cout << NO n , 0; dfs(xx, yy); cout << YES n ; long long sum = 0; for (auto p : all) { res[p.first][p.second] = hh; sum += hh; if (sum == k) break; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) cout << res[i][j] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long int n, m, a; cin >> n >> m >> a; long int colNum = ceil((double)a / (double)(2 * m)); a -= (colNum - 1) * m * 2; long int rowNum = ceil((double)a / 2); a -= rowNum * 2; if (a == 0) cout << colNum << << rowNum << R ; else cout << colNum << << rowNum << L ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, K = 0; int ans[1005]; int main() { scanf( %d , &N); int i, j, tmp = 0; for (i = 1; i * 2 < N; i++) { ++K; ans[K] = i; N -= i; } printf( %d n , K + 1); for (i = 1; i <= K; i++) printf( %d , ans[i]); printf( %d n , N); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, c = 0, j, x = 0, n; cin >> n; string s; vector<string> ar; for (i = 0; i < n; i++) { cin >> s; ar.push_back(s); } for (i = 0; i < ar[0].length(); i++) { for (j = 0; j < n - 1; j++) { if (ar[j][i] != ar[j + 1][i]) { x = 1; break; } } if (x == 0) c++; else break; } cout << c; return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
module cls_spi(
input wire clock,
input wire reset,
input wire [15:0] A,
input wire [7:0] Di,
input wire [7:0] Do,
input wire [15:0] PC,
input wire [15:0] SP,
input wire [15:0] AF,
input wire [15:0] BC,
input wire [15:0] DE,
input wire [15:0] HL,
input wire [15:0] joypad_state,
input wire [1:0] mode,
output wire ss,
output reg mosi,
input wire miso,
output wire sclk
);
parameter WAIT = 1;
parameter SEND = 2;
parameter SEND_2 = 3;
parameter SEND_3 = 4;
parameter SEND_4 = 5;
parameter SEND_5 = 6;
parameter SENDHEX = 7;
parameter SENDJOYPAD = 8;
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter LOOP_1 = 20;
parameter LOOP_2 = 21;
parameter LOOP_3 = 22;
parameter LOOP_4 = 23;
parameter LOOP_5 = 24;
parameter LOOP_6 = 25;
parameter LOOP_7 = 26;
parameter LOOP_8 = 27;
parameter LOOP_9 = 28;
parameter LOOP_10 = 29;
parameter LOOP_11 = 30;
parameter LOOP_7b = 31;
parameter LOOP_8b = 32;
reg [63:0] send_buf; // send buffer (8 bytes)
reg [2:0] send_idx; // current bit (0h-7h)
reg [2:0] send_ctr; // current byte (0h-7h)
reg [2:0] send_max; // total bytes (0h-7h)
reg [31:0] wait_ctr; // current cycle
reg [31:0] wait_max; // total cycles
reg [2:0] hex_idx; // current word
reg [3:0] btn_idx; // current joypad button
reg [1:0] mode_latch; // 0-PCSP, 1-AFBC, 2-DEHL
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
reg [7:0] next_state_hex;
reg [7:0] next_state_btn;
reg ss_enable;
reg sclk_enable;
reg [7:0] glyph_rom [15:0];
reg [31:0] data;
reg [1:0] data_idx;
initial begin
$readmemh("data/hexascii.hex", glyph_rom, 0, 15);
end
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 64'b0;
send_idx <= 3'b0;
send_ctr <= 3'b0;
send_max <= 3'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 8'b0;
next_state_hex <= 8'b0;
next_state_btn <= 8'b0;
mode_latch <= 2'b0;
hex_idx <= 3'b0;
btn_idx <= 4'b0;
data <= 32'b0;
data_idx <= 2'b0;
ss_enable <= 0;
sclk_enable <= 0;
mosi <= 1'b0;
end
// STATES
else begin
// SEND - send up to eight serial bytes
if (state == SEND) begin
ss_enable <= 1;
state <= SEND_2;
end
else if (state == SEND_2) begin
state <= SEND_3;
end
else if (state == SEND_3) begin
mosi <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7) begin
send_idx <= 0;
state <= SEND_4;
end else begin
sclk_enable <= 1;
send_idx <= send_idx + 1;
end
end
else if (state == SEND_4) begin
mosi <= 0;
state <= SEND_5;
end
else if (state == SEND_5) begin
sclk_enable <= 0;
ss_enable <= 0;
if (send_ctr == send_max) begin
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else begin
send_ctr <= send_ctr + 1;
state <= SEND;
end
end
// SENDHEX - send a glyph corresponding to a hex value
else if (state == SENDHEX) begin
send_buf <= glyph_rom[(data >> ({hex_idx, 2'b00})) & 4'hF];
send_max <= 0;
if (hex_idx == 0) begin
next_state <= next_state_hex;
end else begin
next_state <= SENDHEX;
hex_idx <= hex_idx - 1;
end
state <= SEND;
end
// SENDJOYPAD - send a glyph corresponding to a joypad button
else if (state == SENDJOYPAD) begin
case (btn_idx)
0: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h42; // B
1: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h59; // Y
2: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h73; // Select
3: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h53; // Start
4: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h5E; // Up
5: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h64; // Down
6: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3C; // Left
7: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3E; // Right
8: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h41; // A
9: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h58; // X
10: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h4C; // L
11: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h52; // R
default: send_buf <= 8'h20;
endcase
send_max <= 0;
if (btn_idx == 15) begin
btn_idx <= 4'b0;
next_state <= next_state_btn;
end else begin
next_state <= SENDJOYPAD;
btn_idx <= btn_idx + 1;
end
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- send display on, backlight on cmd
else if (state == STARTUP_1) begin
send_buf <= 32'h65335B1B; // ESC BRACKET '3' 'e'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_2;
end
// STARTUP_2 -- clear the display
else if (state == STARTUP_2) begin
send_buf <= 32'h6A305B1B; // ESC BRACKET '0' 'j'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- set the cursor mode
else if (state == STARTUP_3) begin
send_buf <= 32'h63305B1B; // ESC BRACKET '0' 'c'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set the display mode
else if (state == STARTUP_4) begin
send_buf <= 32'h68305B1B; // ESC BRACKET '0' 'h'
send_max <= 3;
state <= SEND;
next_state <= LOOP_1;
end
// LOOP_1 -- set cursor to 0,0
else if (state == LOOP_1) begin
send_buf <= 48'h48303B305B1B; // ESC BRACKET '0' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= LOOP_2;
mode_latch <= mode;
end
else if (state == LOOP_2) begin
send_buf <= 24'h3A4120; // A:
send_max <= 2;
state <= SEND;
next_state <= LOOP_3;
end
else if (state == LOOP_3) begin
data <= A;
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_4;
end
else if (state == LOOP_4) begin
send_buf <= 32'h3A4f4920; // IO:
send_max <= 3;
state <= SEND;
next_state <= LOOP_5;
end
else if (state == LOOP_5) begin
data <= { Di, Do };
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_6;
end
else if (state == LOOP_6) begin
send_buf <= 48'h48303B315B1B; // ESC BRACKET '1' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= mode_latch == 2'b11 ? LOOP_7b : LOOP_7;
end
else if (state == LOOP_7) begin
case (mode_latch)
2'b00: send_buf <= 24'h3A4350; // PC:
2'b01: send_buf <= 24'h3A4641; // AF:
2'b10: send_buf <= 24'h3A4544; // DE:
endcase
send_max <= 2;
state <= SEND;
next_state <= LOOP_8;
end
else if (state == LOOP_8) begin
case (mode_latch)
2'b00: data <= PC;
2'b01: data <= AF;
2'b10: data <= DE;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_9;
end
else if (state == LOOP_9) begin
case (mode_latch)
2'b00: send_buf <= 32'h3A505320; // SP:
2'b01: send_buf <= 32'h3A434220; // BC:
2'b10: send_buf <= 32'h3A4C4820; // HL:
endcase
send_max <= 3;
state <= SEND;
next_state <= LOOP_10;
end
else if (state == LOOP_10) begin
case (mode_latch)
2'b00: data <= SP;
2'b01: data <= BC;
2'b10: data <= HL;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_11;
end
else if (state == LOOP_7b) begin
send_buf <= 16'h2020;
send_max <= 1;
state <= SEND;
next_state <= LOOP_8b;
end
else if (state == LOOP_8b) begin
state <= SENDJOYPAD;
next_state_btn <= LOOP_11;
end
else if (state == LOOP_11) begin
wait_max <= 10;
state <= WAIT;
next_state <= LOOP_1;
end
end
end
assign ss = (ss_enable) ? 1'b0 : 1'b1;
assign sclk = (sclk_enable) ? !clock : 1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_SYMBOL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_SYMBOL_V
|
module inputconditioner(clk, noisysignal, conditioned, positiveedge, negativeedge);
output reg conditioned = 0;
output reg positiveedge = 0;
output reg negativeedge = 0;
input clk, noisysignal;
// variables
parameter counterwidth = 5;
parameter waittime = 10;
reg[counterwidth-1:0] counter = 0;
reg sync0 = 0;
reg sync1 = 0;
always @(posedge clk) begin
// if last bit of buffer is the same as conditioned,
// no need to wait to see if change is consistent
if (conditioned == sync1) begin
counter <= 0;
positiveedge <= 0;
negativeedge <= 0;
// otherwise we check the counter
end else begin
// if the counter is at the end point, we approve this input
if (counter == waittime) begin
counter <= 0;
conditioned <= sync1;
// we know this is an edge--check if rising or falling
if (sync1 == 1) begin
positiveedge <= 1;
end else begin
negativeedge <= 1;
end
// otherwise we increment
end else begin
counter <= counter + 1;
end
end
sync1 = sync0;
sync0 = noisysignal;
end
endmodule
module testConditioner;
wire conditioned;
wire rising;
wire falling;
reg pin, clk;
reg ri;
always @(posedge clk) ri=rising;
inputconditioner dut(clk, pin, conditioned, rising, falling);
initial clk=0;
always #10 clk=!clk; // 50MHz Clock
initial begin
// Your Test Code
// Be sure to test each of the three things the conditioner does:
// Synchronize, Clean, Preprocess (edge finding)
$display("Test Edge Finding");
pin=0; #1010
$display("pin=0; #1010 | expect 0 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
pin=1; #20
$display("pin=1; #20 | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#240
$display("wait #240 | expect 1 1 1 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#100
pin=0;
$display("wait #100 pin=0; | expect 0 1 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#250
$display("wait #250 | expect 0 0 0 1");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
$display("----------------------------------------------------------");
$display("Test Cleaning");
#250
pin=1;
$display("wait #250 pin=1; | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#200
$display("wait #200 | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
pin=0; #250
$display("pin=0; #250 | expect 0 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:56:33 05/24/2015
// Design Name:
// Module Name: subroutine_stack
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module subroutine_stack(
input clock,
input subroutine_call,
input subroutine_return,
input [11:0] PC,
output reg [11:0] RTS_adr
);
reg [11:0] stack [7:0];
reg [2:0] stack_pointer;
integer i;
initial begin
for (i = 0; i < 8 ; i = i + 1) begin
stack[i] = 12'h00;
end
stack_pointer = 3'h0;
RTS_adr = 12'h00;
end
always @(posedge clock) begin
if (subroutine_call == 1) begin
stack_pointer <= stack_pointer + 1;
end
else if (subroutine_return == 1) begin
stack_pointer <= stack_pointer - 1;
end
if (subroutine_call == 1) begin
stack[stack_pointer] <= PC;
end
if (stack_pointer == 0)
RTS_adr <= stack[7];
else
RTS_adr <= stack[stack_pointer - 1];
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:34:12 11/19/2013
// Design Name: top_module
// Module Name: C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/top_module_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_module_test;
// Inputs
reg clock;
reg reset;
// Outputs
wire lrck;
wire mclk;
wire sdin;
wire sclk;
wire [15:0] left_data_o;
wire [15:0] right_data_o;
// Instantiate the Unit Under Test (UUT)
top_module uut (
.clock(clock),
.reset(reset),
.lrck(lrck),
.mclk(mclk),
.sdin(sdin),
.left_data_o(left_data_o),
.right_data_o(right_data_o)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// Library - static, Cell - th44w22, View - schematic
// LAST TIME SAVED: May 23 17:59:39 2014
// NETLIST TIME: May 23 17:59:46 2014
`timescale 1ns / 1ns
module th44w22 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w22";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N12 ( .d(net046), .g(a), .s(net040), .b(cds_globals.gnd_));
nfet_b N11 ( .d(net040), .g(d), .s(net32), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net040), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net046), .g(b), .s(net040), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net32), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net46), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net046), .g(c), .s(net035), .b(cds_globals.gnd_));
nfet_b N15 ( .d(net046), .g(d), .s(net035), .b(cds_globals.gnd_));
nfet_b N13 ( .d(net035), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N0 ( .d(net046), .g(a), .s(net46), .b(cds_globals.gnd_));
pfet_b P12 ( .b(cds_globals.vdd_), .g(y), .s(net034), .d(net046));
pfet_b P8 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net047));
pfet_b P7 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net047));
pfet_b P6 ( .b(cds_globals.vdd_), .g(y), .s(net34), .d(net046));
pfet_b P10 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net034));
pfet_b P11 ( .b(cds_globals.vdd_), .g(d), .s(net047), .d(net034));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net046));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net046);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_2_V
`define SKY130_FD_SC_MS__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, cntx = 0, cntX = 0, c = 0; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == x ) cntx++; else cntX++; } int i = 0; if (cntx > cntX) { while (cntx != cntX) { if (s[i] == x ) { s[i] = X ; cntx--; c++; cntX++; } i++; } } else { while (cntx != cntX) { if (s[i] == X ) { s[i] = x ; cntX--; cntx++; c++; } i++; } } cout << c << endl << s << endl; return 0; }
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Content Addressable Memory (block RAM based)
*/
module cam_bram #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// width of data bus slices
parameter SLICE_WIDTH = 9
)
(
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ADDR_WIDTH-1:0] match_addr,
output wire match
);
// total number of slices (enough to cover DATA_WIDTH with address inputs)
localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
// depth of RAMs
localparam RAM_DEPTH = 2**ADDR_WIDTH;
localparam [2:0]
STATE_INIT = 3'd0,
STATE_IDLE = 3'd1,
STATE_DELETE_1 = 3'd2,
STATE_DELETE_2 = 3'd3,
STATE_WRITE_1 = 3'd4,
STATE_WRITE_2 = 3'd5;
reg [2:0] state_reg = STATE_INIT, state_next;
wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, compare_data};
wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, write_data};
reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
reg [SLICE_COUNT*SLICE_WIDTH-1:0] ram_addr = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
reg [RAM_DEPTH-1:0] set_bit;
reg [RAM_DEPTH-1:0] clear_bit;
reg wr_en;
reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_data_padded_next;
reg write_delete_reg = 1'b0, write_delete_next;
reg write_busy_reg = 1'b1;
assign write_busy = write_busy_reg;
reg [RAM_DEPTH-1:0] match_raw_out[SLICE_COUNT-1:0];
reg [RAM_DEPTH-1:0] match_many_raw;
assign match_many = match_many_raw;
reg [DATA_WIDTH-1:0] erase_ram [RAM_DEPTH-1:0];
reg [DATA_WIDTH-1:0] erase_data = {DATA_WIDTH{1'b0}};
reg erase_ram_wr_en;
integer i;
initial begin
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
erase_ram[i] = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
end
end
integer k;
always @* begin
match_many_raw = {RAM_DEPTH{1'b1}};
for (k = 0; k < SLICE_COUNT; k = k + 1) begin
match_many_raw = match_many_raw & match_raw_out[k];
end
end
priority_encoder #(
.WIDTH(RAM_DEPTH),
.LSB_PRIORITY("HIGH")
)
priority_encoder_inst (
.input_unencoded(match_many_raw),
.output_valid(match),
.output_encoded(match_addr),
.output_unencoded(match_single)
);
// BRAMs
genvar slice_ind;
generate
for (slice_ind = 0; slice_ind < SLICE_COUNT; slice_ind = slice_ind + 1) begin : slice
localparam W = slice_ind == SLICE_COUNT-1 ? DATA_WIDTH-SLICE_WIDTH*slice_ind : SLICE_WIDTH;
wire [RAM_DEPTH-1:0] match_data;
wire [RAM_DEPTH-1:0] ram_data;
ram_dp #(
.DATA_WIDTH(RAM_DEPTH),
.ADDR_WIDTH(W)
)
ram_inst
(
.a_clk(clk),
.a_we(1'b0),
.a_addr(compare_data[SLICE_WIDTH * slice_ind +: W]),
.a_din({RAM_DEPTH{1'b0}}),
.a_dout(match_data),
.b_clk(clk),
.b_we(wr_en),
.b_addr(ram_addr[SLICE_WIDTH * slice_ind +: W]),
.b_din((ram_data & ~clear_bit) | set_bit),
.b_dout(ram_data)
);
always @* begin
match_raw_out[slice_ind] <= match_data;
end
end
endgenerate
// erase
always @(posedge clk) begin
erase_data <= erase_ram[write_addr_next];
if (erase_ram_wr_en) begin
erase_data <= write_data_padded_reg;
erase_ram[write_addr_next] <= write_data_padded_reg;
end
end
// write
always @* begin
state_next = STATE_IDLE;
count_next = count_reg;
ram_addr = erase_data;
set_bit = {RAM_DEPTH{1'b0}};
clear_bit = {RAM_DEPTH{1'b0}};
wr_en = 1'b0;
erase_ram_wr_en = 1'b0;
write_addr_next = write_addr_reg;
write_data_padded_next = write_data_padded_reg;
write_delete_next = write_delete_reg;
case (state_reg)
STATE_INIT: begin
// zero out RAMs
ram_addr = {SLICE_COUNT{count_reg}} & {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}}};
set_bit = {RAM_DEPTH{1'b0}};
clear_bit = {RAM_DEPTH{1'b1}};
wr_en = 1'b1;
if (count_reg == 0) begin
state_next = STATE_IDLE;
end else begin
count_next = count_reg - 1;
state_next = STATE_INIT;
end
end
STATE_IDLE: begin
// idle state
write_addr_next = write_addr;
write_data_padded_next = write_data_padded;
write_delete_next = write_delete;
if (write_enable) begin
// wait for read from erase_ram
state_next = STATE_DELETE_1;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DELETE_1: begin
// wait for read
state_next = STATE_DELETE_2;
end
STATE_DELETE_2: begin
// clear bit and write back
clear_bit = 1'b1 << write_addr;
wr_en = 1'b1;
if (write_delete_reg) begin
state_next = STATE_IDLE;
end else begin
erase_ram_wr_en = 1'b1;
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_1: begin
// wait for read
state_next = STATE_WRITE_2;
end
STATE_WRITE_2: begin
// set bit and write back
set_bit = 1'b1 << write_addr;
wr_en = 1'b1;
state_next = STATE_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_INIT;
count_reg <= {SLICE_WIDTH{1'b1}};
write_busy_reg <= 1'b1;
end else begin
state_reg <= state_next;
count_reg <= count_next;
write_busy_reg <= state_next != STATE_IDLE;
end
write_addr_reg <= write_addr_next;
write_data_padded_reg <= write_data_padded_next;
write_delete_reg <= write_delete_next;
end
endmodule
|
module fifo(in_data, in_d_rdy, clk, out_data, out_d_rdy, rdy2rcv);
parameter WIDTH=8;
parameter BUFF_LEN=16;
parameter BUFF_LENm=BUFF_LEN - 1;
parameter BUFF_LEN_WIDTH_bits = (BUFF_LENm[7:7]==1'b1) ? 8 :
(BUFF_LENm[6:6]==1'b1) ? 7 :
(BUFF_LENm[5:5]==1'b1) ? 6 :
(BUFF_LENm[4:4]==1'b1) ? 5 :
(BUFF_LENm[3:3]==1'b1) ? 4 :
(BUFF_LENm[2:2]==1'b1) ? 3 :
(BUFF_LENm[1:1]==1'b1) ? 2 :
(BUFF_LENm[0:0]==1'b1) ? 1 : 0;
input wire [(WIDTH-1):0] in_data;
input wire in_d_rdy, clk, rdy2rcv;
output wire [(WIDTH-1):0] out_data;
output wire out_d_rdy;
//fifo
reg [(BUFF_LEN_WIDTH_bits-1):0] fifo_buff_wptr;
initial fifo_buff_wptr <= {BUFF_LEN_WIDTH_bits {1'b0}};
reg [(BUFF_LEN_WIDTH_bits-1):0] fifo_buff_sptr;
initial fifo_buff_sptr <= {BUFF_LEN_WIDTH_bits {1'b0}};
reg [(BUFF_LEN_WIDTH_bits-1):0] fifo_buff_cnt;
initial fifo_buff_cnt <= {BUFF_LEN_WIDTH_bits {1'b0}};
reg [(WIDTH-1):0] fifo_buff [0:(BUFF_LEN-1)];
integer i;
initial begin
for(i=0;i<BUFF_LEN;i=i+1) begin
fifo_buff[i] <= {WIDTH {1'b0}};
end
end
assign out_d_rdy = (fifo_buff_cnt>0)&&rdy2rcv;
assign out_data = (out_d_rdy) ? fifo_buff[fifo_buff_sptr] : {WIDTH {1'b0}};
//assign out_data = fifo_buff[fifo_buff_sptr];
always @ (posedge clk) begin
if (in_d_rdy==1'b1) begin //in_d_rdy - store
fifo_buff[fifo_buff_wptr] <= in_data;
fifo_buff_wptr <= fifo_buff_wptr + 1'b1;
if ((fifo_buff_cnt!={BUFF_LEN_WIDTH_bits {1'b0}})&&(rdy2rcv==1'b1)) begin
fifo_buff_sptr <= fifo_buff_sptr + 1'b1;
fifo_buff_cnt <= fifo_buff_cnt;
end else begin
fifo_buff_cnt <= fifo_buff_cnt + 1'b1;
end
end else begin // restore data only when not write data
if ((fifo_buff_cnt!={BUFF_LEN_WIDTH_bits {1'b0}})&&(rdy2rcv==1'b1)) begin
fifo_buff_sptr <= fifo_buff_sptr + 1'b1;
fifo_buff_cnt <= fifo_buff_cnt - 1'b1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:47:13 03/17/2015
// Design Name:
// Module Name: or_gate
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//-----------------------------------------------
module or_gate
(
input [9:0] i,
output o
);
//-----------------------------------------------
wire [4095:0]data=4096'hf5ffe6ecf6c7fd7c7577ec5e5f46e55ef474ee66444ff77d756475fde5d76f6fd7ced54c7f67476cdf5fed477ff4644fdf4eee4e476f776665e4fefd7ee5f4f5def75ce5fe4d75ffcc7f47ffcfcffde657cd5475dfc566f66d7cdc675cd655cdf46fd476f7cdddd7fe4dd7e4f545d4c467ee457c5f654664cc6f4567fc6e77fcc6e7cfff4ee6f74eedfdf7e54dee5c7e77fcdeecf6545d44dce676f4cf4fd7ed647f544edeedecdde46ec44d7ed77dfeddc564d657dece675ddf565f7fde7d4dc6c47ec5544f75fdfd5de7f57c466f67e6f5cc5cfd4647777676c46d5fed6d67574f6fecee75dee7d54eee6dce74eedcff6dd5cfd4674ffc4447d6cc5fccee4666f46df547e7e6d67e6f5f457e45ed45ddce565c5656754c5e546e5464d664fddfe5f5efecdf5eee45447f7f4fdcf5e4dd677cd4fef7ce6ce6c6ff4f5f4544ed575feffc675cc6edecee47dc64776d4e5e57644dd75ef4eefc47e5d6465c5cecdf4c4d74cf4ddf6f5d6465cfdc56c4c1cc7f7ec46c5dfd596ec57755e4de6ee9dc5d46df4ff67f54c77de546445f4f7d7de7c746e7c7d677775dde6e457c7e6dd4f6e7ef67ccf6e55e454f45fdf7ef686d4e4d4657d54f79ed5f5e5d7c6e6743efcdc5ceecc7ed7d577d6fd4f74ecd6ef6de5e67e4df4cfc447d56ded46c75f7cdff74f746476de544de74cfedee6550f45e56ec7f75dcda4f647defdf6ee4d9;
//-----------------------------------------------
assign o = data[4*i+2];
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufkapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; map<string, int> fr; int main() { ios_base::sync_with_stdio(false); string s; cin >> s; for (int k = 0; k <= 9; k++) { string a; cin >> a; fr[a] = k; } int id = 0; string act = ; for (int k = 0; k < 80; k++) { act += s[k]; id++; if (id == 10) { cout << fr[act]; id = 0; act = ; } } return 0; }
|
module tx_frontend
#(parameter BASE=0,
parameter WIDTH_OUT=16,
parameter IQCOMP_EN=1)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [23:0] tx_i, input [23:0] tx_q, input run,
output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b
);
// IQ balance --> DC offset --> rounding --> mux
wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
wire [WIDTH_OUT-1:0] i_final, q_final;
wire [7:0] mux_ctrl;
wire [35:0] corr_i, corr_q;
wire [23:0] i_bal, q_bal;
wire [17:0] mag_corr, phase_corr;
setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(i_dco),.changed());
setting_reg #(.my_addr(BASE+1), .width(24)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(q_dco),.changed());
setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(mag_corr),.changed());
setting_reg #(.my_addr(BASE+3),.width(18)) sr_3
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_corr),.changed());
setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(mux_ctrl),.changed());
generate
if(IQCOMP_EN==1)
begin
// IQ Balance
MULT18X18S mult_mag_corr
(.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) );
MULT18X18S mult_phase_corr
(.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
add2_and_clip_reg #(.WIDTH(24)) add_clip_i
(.clk(clk), .rst(rst),
.in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1),
.sum(i_bal), .strobe_out());
add2_and_clip_reg #(.WIDTH(24)) add_clip_q
(.clk(clk), .rst(rst),
.in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1),
.sum(q_bal), .strobe_out());
// DC Offset
add2_and_clip_reg #(.WIDTH(24)) add_dco_i
(.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
add2_and_clip_reg #(.WIDTH(24)) add_dco_q
(.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
end // if (IQCOMP_EN==1)
else
begin
// DC Offset
add2_and_clip_reg #(.WIDTH(24)) add_dco_i
(.clk(clk), .rst(rst), .in1(i_dco), .in2(tx_i), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
add2_and_clip_reg #(.WIDTH(24)) add_dco_q
(.clk(clk), .rst(rst), .in1(q_dco), .in2(tx_q), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
end // else: !if(IQCOMP_EN==1)
endgenerate
// Rounding
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i
(.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
(.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
// Mux
always @(posedge clk)
case(mux_ctrl[3:0])
0 : dac_a <= i_final;
1 : dac_a <= q_final;
default : dac_a <= 0;
endcase // case (mux_ctrl[3:0])
always @(posedge clk)
case(mux_ctrl[7:4])
0 : dac_b <= i_final;
1 : dac_b <= q_final;
default : dac_b <= 0;
endcase // case (mux_ctrl[7:4])
endmodule // tx_frontend
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
wire valid_start_state;
wire valid_next_state;
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_start_state = ~((^start_state)^(^start_state));
assign valid_next_state = ~((^next_state)^(^next_state));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_start_state, r_next_state;
reg assert_state;
`ifdef OVL_SYNTHESIS
`else
initial begin
assert_state = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_start_state == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_state contains X or Z");
end
if (valid_next_state == 1'b1)
begin
// Do nothing
end
else
begin
if (start_state != test_expr)
begin
// Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"next_state contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (assert_state == 1'b0) begin // INIT_STATE
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
end
else begin // CHECK_STATE
if (test_expr == r_next_state) begin
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0; // done ok.
end
else if (test_expr != r_start_state) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Test expression transitioned from value start_state to a value other than next_state"); // test_expr moves to unexpected state
`endif // OVL_ASSERT_ON
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0; // done error.
end
end
end
else begin
assert_state <= 1'b0;
r_start_state <= {width{1'b0}};
r_next_state <= {width{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; struct node { int x, y, id; void scan() { scanf( %d%d , &x, &y); if (x > y) swap(x, y); } } e[N * 5], q[N], tmp[N]; struct opt { int x, y, sz, f; long long ans; } op[N * 5]; int T; int ext; int cnt, now, tot, n, m, qu, bs, l, r, top, pos; int ed[N], in[N], sz[N], father[N]; vector<node> v[N], g[N]; long long ret[N], ans; bool cmpx(const node &a, const node &b) { return a.x < b.x; } bool cmpy(const node &a, const node &b) { return a.y < b.y; } int calc(int x) { int l = 1, r = m; if (e[1].x >= x) return 1; if (e[m].x < x) return m + 1; while (l + 1 < r) { int mid = (l + r) >> 1; if (e[mid].x >= x) r = mid; else l = mid + 1; } if (e[l].x >= x) return l; else return r; } int getfather(int x) { return father[x] == x ? x : getfather(father[x]); } void solve(int x, int y) { int fx = getfather(x), fy = getfather(y); if (fx == fy) return; if (sz[fx] < sz[fy]) swap(fx, fy); ++top; op[top].x = fx; op[top].y = fy; op[top].sz = sz[fx]; op[top].f = father[fy]; op[top].ans = ans; father[fy] = fx; ans++; sz[fx] += sz[fy]; } void undo() { for (int i(top); i >= (1); --i) { int fx = op[i].x, fy = op[i].y; father[fy] = op[i].f; ans = op[i].ans; sz[fx] = op[i].sz; } } int main() { scanf( %d%d , &n, &ext); scanf( %d , &m); for (int i(1); i <= (m); ++i) e[i].scan(); scanf( %d , &qu); for (int i(1); i <= (qu); ++i) q[i].scan(), q[i].id = i; sort(e + 1, e + m + 1, cmpx); memset(in, 0, sizeof in); for (int i(1); i <= (m); ++i) ++in[e[i].x]; bs = (int)floor(sqrt((double)(2 * m) * (double)(log(n) / 0.4))); tot = 0; now = 0; memset(ed, 0, sizeof ed); for (int i(1); i <= (n); ++i) { now += in[i]; if (now >= bs) { ++tot; ed[tot] = i; now = 0; } } if (ed[tot] != n) { ++tot; ed[tot] = n; } for (int i(1); i <= (tot); ++i) { l = ed[i - 1] + 1, r = ed[i]; v[i].clear(); g[i].clear(); for (int j(1); j <= (m); ++j) if (e[j].x >= l && e[j].x <= r) v[i].push_back(e[j]); for (int j(1); j <= (qu); ++j) if (q[j].x >= l && q[j].y <= r) g[i].push_back(q[j]); } for (int et(1); et <= (tot); ++et) { l = ed[et - 1] + 1, r = ed[et]; cnt = 0; for (int i(1); i <= (qu); ++i) if (q[i].x >= l && q[i].x <= r && q[i].y > r) { tmp[++cnt] = q[i]; } sort(tmp + 1, tmp + cnt + 1, cmpy); sort(e + 1, e + m + 1, cmpx); pos = calc(r + 1); sort(e + pos, e + m + 1, cmpy); for (int i(1); i <= (n); ++i) father[i] = i, sz[i] = 1; ans = 0; for (int j = pos, k = 1; k <= cnt; ++k) { while (e[j].y <= tmp[k].y && j <= m) { solve(e[j].x, e[j].y); ++j; } top = 0; for (auto edge : v[et]) { if (tmp[k].x <= edge.x && edge.y <= tmp[k].y) { solve(edge.x, edge.y); } } ret[tmp[k].id] = tmp[k].y - tmp[k].x + 1 - ans; undo(); } for (int i(1); i <= (n); ++i) father[i] = i, sz[i] = 1; ans = 0; for (auto query : g[et]) { top = 0; for (auto edge : v[et]) { if (query.x <= edge.x && edge.y <= query.y) { solve(edge.x, edge.y); } } ret[query.id] = query.y - query.x + 1 - ans; undo(); } } for (int i(1); i <= (qu); ++i) printf( %lld n , ret[i]); return 0; }
|
module test();
localparam [7:0] dly1 = 1;
wire [7:0] dly2 = 2;
reg [7:0] dly3 = 3;
reg en;
wire i = 1;
wire [6:1] o;
tranif1 #(dly1, dly2) buf1(o[1], i, en);
tranif1 #(dly2, dly1) buf2(o[2], i, en);
tranif1 #(dly1, dly3) buf3(o[3], i, en);
tranif1 #(dly3, dly1) buf4(o[4], i, en);
tranif1 #(dly2, dly3+1) buf5(o[5], i, en);
tranif1 #(4, 2) buf6(o[6], i, en);
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
en = 1'b1;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
en = 1'b0;
#0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b1, 1'bz, 1'b1, 1'bz, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'b1, 1'bz, 1'b1, 1'bz)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'b1, 1'bz)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 110; const int INF = 1 << 28; const double EPS = 1e-9; const double PI = 3.14159265358979; int n, d; int a[MAX_N]; int x[MAX_N], y[MAX_N]; int g[MAX_N][MAX_N]; int main() { cin >> n >> d; for (int i = (1); i < (n - 1); i++) cin >> a[i]; for (int i = (0); i < (n); i++) cin >> x[i] >> y[i]; for (int i = (0); i < (n); i++) for (int j = (0); j < (n); j++) { g[i][j] = d * (abs(x[i] - x[j]) + abs(y[i] - y[j])); if (i != j) g[i][j] -= a[j]; } for (int k = (0); k < (n); k++) for (int i = (0); i < (n); i++) for (int j = (0); j < (n); j++) g[i][j] = min(g[i][j], g[i][k] + g[k][j]); cout << g[0][n - 1] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; char arr[105]; scanf( %d%*c , &t); while (t--) { gets(arr); int len = strlen(arr); char temp[20] = {arr[len - 5], arr[len - 4], arr[len - 3], arr[len - 2], arr[len - 1]}; char tem[20] = {arr[0], arr[1], arr[2], arr[3], arr[4]}; if (strcmp(temp, lala. ) == 0 && strcmp(tem, miao. ) == 0) printf( OMG>.< I don t know! n ); else if (strcmp(temp, lala. ) == 0) printf( Freda s n ); else if (strcmp(tem, miao. ) == 0) printf( Rainbow s n ); else printf( OMG>.< I don t know! n ); } return 0; }
|
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