text stringlengths 59 71.4k |
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module vga_bw
(
CLOCK_PIXEL,
RESET,
PIXEL,
PIXEL_H,
PIXEL_V,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
input PIXEL; // black (0) or white (1)
output [10:0] PIXEL_H;
output [10:0] PIXEL_V;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg [10:0] hor_pixel; // the next pixel
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg [10:0] ver_pixel; // the next pixel
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// visible pixel counter
//reg [15:0] visible_pixel;
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max) begin
ver_reg <= 0;
end else begin
ver_reg <= ver_reg + 1;
end
end else begin
hor_reg <= hor_reg + 1;
end
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
hor_pixel <= 0;
ver_pixel <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) begin // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
end else if (hor_reg == 928) begin // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
end
/* Generating the vertical sync signal */
if (ver_reg == 493) begin // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
end else if (ver_reg == 496) begin // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
end
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
if (ver_reg > 480) begin
ver_pixel <= 0;
end
if (hor_reg > 800) begin
hor_pixel <= 0;
end
end
else begin
hor_pixel <= hor_reg;
ver_pixel <= ver_reg;
// Draw the pixel.
if (PIXEL) begin
// white
red <= 1;
green <= 1;
blue <= 1;
end
else begin
// black
red <= 0;
green <= 0;
blue <= 0;
end
end
end
end
// Send the sync signals to the output.
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
assign PIXEL_H = hor_pixel;
assign PIXEL_V = ver_pixel;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : sonic_single_port.sv
// Description : basic PHY with gearbox and blocksync
// Author : Han Wang
// Created On : Fri Apr 25 21:17:48 2014
// Last Modified By: Han Wang
// Last Modified On: Fri Apr 25 21:17:48 2014
// Update Count : 0
// Status : initial design for OSDI
module sonic_single_port (/*AUTOARG*/
// Outputs
xcvr_tx_dataout,
cntr_local_state,
xgmii_rx_data,
log_data,
log_valid,
log_delay,
// Inputs
xcvr_rx_datain,
xcvr_tx_clkout,
xcvr_rx_clkout,
xcvr_tx_ready,
xcvr_rx_ready,
ctrl_bypass_clksync,
ctrl_disable_clksync,
ctrl_clear_local_state,
ctrl_mode,
ctrl_disable_ecc,
ctrl_error_bound,
cntr_global_state,
xgmii_tx_data,
clk_in,
rst_in,
lpbk_endec,
timeout_init,
timeout_sync
);
// lower layer xcvr interface
output wire [39:0] xcvr_tx_dataout;
input wire [39:0] xcvr_rx_datain;
input wire xcvr_tx_clkout;
input wire xcvr_rx_clkout;
input wire xcvr_tx_ready;
input wire xcvr_rx_ready;
input wire ctrl_bypass_clksync; //ctrl_bypass clocksync
input wire ctrl_disable_clksync; //disable clocksync
input wire ctrl_clear_local_state; //ctrl_clear_local_state c_local counters
input wire ctrl_mode; //0 for NIC mode, 1 for switch mode
input wire ctrl_disable_ecc;
input wire [31:0] ctrl_error_bound;
input wire [52:0] cntr_global_state;
output wire [52:0] cntr_local_state;
// upper layer xgmii interface
input wire [71:0] xgmii_tx_data;
output wire [71:0] xgmii_rx_data;
input wire clk_in;
output wire [511:0] log_data;
output wire log_valid;
output wire [15:0] log_delay;
// system interface
input wire rst_in;
input wire lpbk_endec;
input wire [31:0] timeout_init;
input wire [31:0] timeout_sync;
wire [63:0] xgmii_txd;
wire [7:0] xgmii_txc;
wire [63:0] xgmii_rxd;
wire [7:0] xgmii_rxc;
wire lock;
wire [65:0] encoded_datain, decoded_dataout, clksync_dataout, loopback_dataout;
parameter INIT_TYPE=2'b01, ACK_TYPE=2'b10, BEACON_TYPE=2'b11;
// xgmii data conversion
assign xgmii_txc[7] = xgmii_tx_data[71];
assign xgmii_txc[6] = xgmii_tx_data[62];
assign xgmii_txc[5] = xgmii_tx_data[53];
assign xgmii_txc[4] = xgmii_tx_data[44];
assign xgmii_txc[3] = xgmii_tx_data[35];
assign xgmii_txc[2] = xgmii_tx_data[26];
assign xgmii_txc[1] = xgmii_tx_data[17];
assign xgmii_txc[0] = xgmii_tx_data[8];
assign xgmii_txd[63:56] = xgmii_tx_data[70:63];
assign xgmii_txd[55:48] = xgmii_tx_data[61:54];
assign xgmii_txd[47:40] = xgmii_tx_data[52:45];
assign xgmii_txd[39:32] = xgmii_tx_data[43:36];
assign xgmii_txd[31:24] = xgmii_tx_data[34:27];
assign xgmii_txd[23:16] = xgmii_tx_data[25:18];
assign xgmii_txd[15:8] = xgmii_tx_data[16:9];
assign xgmii_txd[7:0] = xgmii_tx_data[7:0];
assign xgmii_rx_data = {xgmii_rxc[7], xgmii_rxd[63:56],
xgmii_rxc[6], xgmii_rxd[55:48],
xgmii_rxc[5], xgmii_rxd[47:40],
xgmii_rxc[4], xgmii_rxd[39:32],
xgmii_rxc[3], xgmii_rxd[31:24],
xgmii_rxc[2], xgmii_rxd[23:16],
xgmii_rxc[1], xgmii_rxd[15:8],
xgmii_rxc[0], xgmii_rxd[7:0]};
// Clock synchronisation layer
// Use the link_fault_status, 00=No link fault, 01=Local Fault, 10=Remote Fault
// if transceiver ready, assume link ok.
// NOTE: this is not entirely safe, because we also need to make sure data in
// phy is valid (fifos, gearbox, etc). For testing purpose, we ignore the
// corner cases.
clocksync_sm clocksync_sm (
.reset(rst_in || ctrl_disable_clksync),
.clear(ctrl_clear_local_state),
.mode(ctrl_mode),
.disable_filter(ctrl_disable_ecc),
.thres(ctrl_error_bound),
.clock(clk_in),
.link_ok(xcvr_rx_ready && lock),
// axillary data saved to DDR3 ram
.export_data(log_data),
.export_valid(log_valid),
.export_delay(log_delay),
.c_global(cntr_global_state),
.c_local_o(cntr_local_state),
.encoded_datain(encoded_datain), // data from encoder
.clksync_dataout(clksync_dataout), // data from clksync to txchan
.decoded_dataout(decoded_dataout), // data from decoder
.init_timeout(timeout_init),
.sync_timeout(timeout_sync)
);
wire [65:0] bypass_dataout;
xgmii_mux mux_bypass (
.data0x(clksync_dataout),
.data1x(encoded_datain),
.data2x(),
.data3x(),
.sel({1'b0, ctrl_bypass_clksync}),
.clock(clk_in),
.result(bypass_dataout)
);
// XGMII encoder
encoder encoder_block (
.clk(clk_in),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.data_out(encoded_datain),
.t_type(),
.init(rst_in),
.enable(xcvr_tx_ready)
);
// TX channel
sonic_tx_chan_66 tx_chan (
.data_in(bypass_dataout),
.wr_clock(clk_in),
.data_out(xcvr_tx_dataout),
.rd_clock(xcvr_tx_clkout),
.reset(rst_in),
.xcvr_tx_ready(xcvr_tx_ready)
);
// XGMII decoder
decoder decoder_block (
.clk(clk_in),
.data_in(loopback_dataout),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.r_type(),
.sync_lock(lock),
.init(rst_in),
.idle_bus()
);
// RX channel
sonic_rx_chan_66 rx_chan (
.data_in(xcvr_rx_datain),
.wr_clock(xcvr_rx_clkout),
.data_out(decoded_dataout),
.rd_clock(clk_in),
.reset(rst_in),
.lock(lock),
.xcvr_rx_ready(xcvr_rx_ready)
);
// encoder to decoder loopback
xgmii_loopback lpbk (
.data0x(decoded_dataout),
.data1x(bypass_dataout),
.sel(lpbk_endec),
.result(loopback_dataout)
);
endmodule // sonic_single_port
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.3
// \ \ Application : xaw2verilog
// / / Filename : clk_blk.v
// /___/ /\ Timestamp : 04/07/2011 11:02:43
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle X:/DSD/pipelined_cpu/clk_blk/clk_blk.xaw -st clk_blk.v
//Design Name: clk_blk
//Device: xc3s500e-4fg320
//
// Module clk_blk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module clk_blk(CLKIN_IN,
RST_IN,
CLK0_OUT,
CLK180_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLK0_OUT;
output CLK180_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK180_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLK0_OUT = CLKFB_IN;
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
.O(CLK180_OUT));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(CLK180_BUF),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int maxN = 110; int n, k, a[maxN]; void solve() { vector<vector<double> > d[2]; int u = 0, v = 1; d[u].assign(maxN, vector<double>(maxN, 0.0)); for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { if (a[i] < a[j]) { d[u][i][j] = 1.0; } else { d[u][j][i] = 1.0; } } } double p = 2.0 / (double)(n * (n + 1)); for (int steps = 0; steps < k; ++steps, swap(u, v)) { d[v].assign(maxN, vector<double>(maxN, 0.0)); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (i == j) { continue; } for (int a = 1; a <= n; ++a) { for (int b = a; b <= n; ++b) { int ni = i; if (a <= i && i <= b) { ni = a + b - i; } int nj = j; if (a <= j && j <= b) { nj = a + b - j; } d[v][ni][nj] += p * d[u][i][j]; } } } } } double res = 0.0; for (int i = 1; i <= n; ++i) { for (int j = 1; j < i; ++j) { res += d[u][i][j]; } } printf( %.10lf n , res); } int main() { cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> a[i]; } solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int b[101]; int main() { int n, x; cin >> n >> x; int a[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; b[a[i]]++; } int t = 0; for (int i = 0; i < x; i++) { if (b[i] == 0) { t++; } } if (b[x] == 1) t++; cout << t; } |
#include <bits/stdc++.h> using namespace std; using s64 = long long; const int M = 1000000007; int add(int a, const int &b) { a += b; return a >= M ? a - M : a; } int sub(int a, const int &b) { a -= b; return a < 0 ? a + M : a; } int mul(const int &a, const int &b) { return (s64)a * b % M; } int main() { int n, k; cin >> n >> k; vector<int> fac(n), ifac(n); fac[0] = fac[1] = ifac[0] = ifac[1] = 1; for (int i = 2; i < n; ++i) { fac[i] = mul(fac[i - 1], i); ifac[i] = mul(M - M / i, ifac[M % i]); } for (int i = 2; i < n; ++i) { ifac[i] = mul(ifac[i], ifac[i - 1]); } vector<int> f(n + 1), sum(n + 1); for (int i = k + 1; i <= n; ++i) { f[i] = mul(add(i - k - 1, sub(sum[i - 1], sum[i - k - 1])), fac[i - 2]); sum[i] = mul(f[i], ifac[i - 1]); sum[i] = add(sum[i], sum[i - 1]); } int answer = 0; for (int i = 1; i <= n; ++i) { answer = add(answer, mul(f[i], mul(fac[n - 1], ifac[i - 1]))); } cout << answer << endl; return 0; } |
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
// CREATED "Wed Nov 06 13:54:26 2013"
module HalfAdder(
A,
Cin,
Cout,
Sum
);
input wire A;
input wire Cin;
output wire Cout;
output wire Sum;
assign Cout = A & Cin;
assign Sum = A ^ Cin;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool arr[1001][1001]; struct node { int ct; int lastind; }; struct node1 { int ct; int lastind; }; node row[1001]; node1 col[1001]; int main() { vector<int> a; int n, i, x, y, j, temp; scanf( %d , &n); for (i = 0; i < n - 1; i++) { scanf( %d%d , &x, &y); arr[x][y] = 1; } for (i = 1; i <= n; i++) { row[i].ct = 0; row[i].lastind = 0; for (j = 1; j <= n; j++) { if (arr[i][j]) { row[i].ct++; row[i].lastind = j; } } } for (i = 1; i <= n; i++) { temp = i; for (j = i + 1; j <= n; j++) { if (row[temp].ct > row[j].ct) { temp = j; } else if (row[temp].ct == row[j].ct && row[temp].lastind > row[j].lastind) temp = j; } if (temp != i) { a.push_back(1); a.push_back(i); a.push_back(temp); swap(row[i], row[temp]); for (j = 1; j <= n; j++) { swap(arr[i][j], arr[temp][j]); } } } for (i = 1; i <= n; i++) { col[i].ct = 0; col[i].lastind = n; for (j = 1; j <= n; j++) { if (arr[j][i]) { col[i].ct++; col[i].lastind = min(col[i].lastind, j); } } } for (i = 1; i <= n; i++) { temp = i; for (j = i + 1; j <= n; j++) { if (col[temp].ct < col[j].ct) { temp = j; } else if (col[temp].ct == col[j].ct && col[temp].lastind > col[j].lastind) temp = j; } if (temp != i) { a.push_back(2); a.push_back(i); a.push_back(temp); swap(col[i], col[temp]); } } printf( %d n , a.size() / 3); for (i = 0; i < a.size(); i += 3) { printf( %d %d %d n , a[i], a[i + 1], a[i + 2]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 13; int n, m; set<int> e[N]; set<pair<int, int> > q; int p[N]; int tin[N], cnt, w[N], ans; int gcd(int a, int b) { return (!a ? b : gcd(b % a, a)); } void init() { for (int i = 0; i < N; ++i) p[i] = i; } int find(int u) { if (p[u] == u) return u; return p[u] = find(p[u]); } void uni(int a, int b) { a = find(a); b = find(b); if (a == b) return; if (e[a].size() < e[b].size()) swap(a, b); for (int to : e[b]) e[a].insert(find(to)); p[b] = a; e[b].clear(); } void print(int ans) { printf( %d n , ans); exit(0); } pair<int, int> getMax() { auto it = q.end(); --it; pair<int, int> res = (*it); return res; } void merge(int id) { if (id != find(id)) return; vector<int> ver; for (int v : e[id]) ver.push_back(find(v)); e[id].clear(); for (int i = 0; i < ver.size(); ++i) { int pi = find(ver[i]); q.erase(make_pair(e[pi].size(), pi)); } for (int i = 1; i < ver.size(); ++i) uni(ver[i], ver[i - 1]); int lv = find(ver[0]); id = find(id); e[id].insert(lv); q.insert(make_pair(e[lv].size(), lv)); q.insert(make_pair(e[id].size(), id)); if (e[id].find(id) != e[id].end()) print(1); } void compress() { for (int i = 0; i < n; ++i) { q.insert(make_pair(e[i].size(), find(i))); } while (true) { pair<int, int> cur = getMax(); if (cur.first < 2) return; q.erase(cur); merge(cur.second); } } void dfs(int u) { w[u] = 1; tin[u] = cnt; ++cnt; for (int to : e[u]) { int vt = find(to); if (!w[vt]) dfs(vt); else if (w[vt] == 1) { ans = gcd(ans, tin[u] - tin[vt] + 1); } } w[u] = 2; --cnt; } void solve() { init(); scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { int u, v; scanf( %d %d , &u, &v); --u; --v; if (u == v) print(1); e[u].insert(find(v)); } compress(); for (int i = 0; i < n; ++i) if (!w[find(i)]) dfs(find(i)); if (ans == 0) ans = n; printf( %d n , ans); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using PII = pair<ll, ll>; using piii = pair<pii, pii>; using Pi = pair<int, pii>; using Graph = vector<vector<int>>; const int dx[4] = {0, -1, 1, 0}; const int dy[4] = {-1, 0, 0, 1}; bool check(int x, int y) { if (0 <= x && x < 55 && 0 <= y && y < 55) return true; else return false; } const ll INF = 1e+7; int gcd(int x, int y) { if (x < y) swap(x, y); if (y == 0) return x; return gcd(y, x % y); } void mul(ll a, ll b) { a = a * b % INF; } using Graph = vector<vector<int>>; long long modinv(long long a, long long m) { long long b = m, u = 1, v = 0; while (b) { long long t = a / b; a -= t * b; swap(a, b); u -= t * v; swap(u, v); } u %= m; if (u < 0) u += m; return u; } const double PI = 3.14159265358979323846; const int MAX = 510000; ll fac[MAX], finv[MAX], inv[MAX]; void COMinit() { fac[0] = fac[1] = 1; finv[0] = finv[1] = 1; inv[1] = 1; for (int i = 2; i < MAX; ++i) { fac[i] = fac[i - 1] * i % INF; inv[i] = INF - inv[INF % i] * (INF / i) % INF; finv[i] = finv[i - 1] * inv[i] % INF; } } ll COM(int n, int k) { if (n < k) return 0; if (n < 0 || k < 0) return 0; return fac[n] * (finv[k] * finv[n - k] % INF) % INF; } double Euclidean_distance(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } int prime[1001000]; bool is_prime[1001010]; int sieve(int n) { int p = 0; for (int i = 0; i <= n; ++i) { is_prime[i] = true; } is_prime[0] = false; is_prime[1] = false; for (int i = 2; i <= n; ++i) { if (is_prime[i]) { prime[p] = i; p++; for (int j = 2 * i; j <= n; j += i) { is_prime[j] = false; } } } return p; } map<int, int> prime_factor(int n) { map<int, int> res; for (int i = 2; i * i <= n; ++i) { while (n % i == 0) { ++res[i]; n /= i; } } if (n != 1) res[n] = 1; return res; } ll powmod(ll a, ll k, ll mod) { ll ap = a, ans = 1; while (k) { if (k & 1) { ans *= ap; ans %= mod; } ap = ap * ap; ap %= mod; k >>= 1; } return ans; } ll invi(ll a, ll mod) { return powmod(a, mod - 2, mod); } int main() { int t; cin >> t; while (t--) { ll n, m; cin >> n >> m; if (n == 1 || m == 1) { cout << YES << endl; } else if (n == 2 && m == 2) { cout << YES << endl; } else { cout << NO << endl; } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_PP_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg_s/sky130_fd_sc_hdll__udp_pwrgood_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; if (n <= 2) cout << -1; else while (n--) cout << n + 1 << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long temp = 0; string s; cin >> s; for (int i = 0; i < s.length(); i++) { temp = temp * 16; if (s[i] == > ) temp += 8; else if (s[i] == < ) temp += 9; else if (s[i] == + ) temp += 10; else if (s[i] == - ) temp += 11; else if (s[i] == . ) temp += 12; else if (s[i] == , ) temp += 13; else if (s[i] == [ ) temp += 14; else if (s[i] == ] ) temp += 15; temp = temp % 1000003; } cout << temp << endl; } |
// psi2c_readback.v
`timescale 1 ps / 1 ps
module psi2c_readback
(
input clk,
input sync,
input reset,
input go,
input rda,
input sync2,
input i2c_send,
output [31:0]d
);
reg rdaff;
always @(posedge clk or posedge reset) rdaff <= reset ? 0 : rda;
wire nto; // not timeout
wire last;
wire running;
wire toflag; // time out flag
srff_timeout ffto
(
.clk(clk),
.sync(sync),
.reset(reset),
.s(go),
.r(running),
.to_disable(i2c_send),
.q(nto),
.to(toflag)
);
rda_bitcounter bitcounter
(
.aclr(reset),
.clk_en(sync),
.clock(clk),
.cnt_en(running),
.sset(sync && !rda && rdaff && nto),
.cout(last),
.q()
);
assign running = !last;
// shift register
reg [28:0]shiftreg;
always @(posedge clk or posedge reset)
begin
if (reset) shiftreg <= 0;
else if (running && sync) shiftreg <= {shiftreg[27:0], rdaff};
end
// rda data mapper
wire [4:0]ha = shiftreg[7:3];
wire [2:0]pa = shiftreg[2:0];
wire [7:0]ra = {shiftreg[28:25], shiftreg[23:20]};
wire [7:0]rd = {shiftreg[18:15], shiftreg[13:10]};
wire start = shiftreg[8];
wire _s3 = shiftreg[24];
wire _rw = shiftreg[19];
wire _d4 = shiftreg[14];
wire _d0 = shiftreg[9];
assign d = {running || nto, toflag, 1'b0, _s3, _rw, _d4, _d0, start, ha, pa, ra, rd};
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_2d_transfer (
input req_aclk,
input req_aresetn,
input req_valid,
output reg req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_x_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_y_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_dest_stride,
input [C_DMA_LENGTH_WIDTH-1:0] req_src_stride,
input req_sync_transfer_start,
output reg req_eot,
output reg out_req_valid,
input out_req_ready,
output [31:C_BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:C_BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [C_DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
);
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_BYTES_PER_BEAT_WIDTH_SRC = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = 3;
reg [31:C_BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [C_DMA_LENGTH_WIDTH-1:0] x_length;
reg [C_DMA_LENGTH_WIDTH-1:0] y_length;
reg [C_DMA_LENGTH_WIDTH-1:0] dest_stride;
reg [C_DMA_LENGTH_WIDTH-1:0] src_stride;
reg [1:0] req_id;
reg [1:0] eot_id;
reg [3:0] last_req;
assign out_req_dest_address = dest_address;
assign out_req_src_address = src_address;
assign out_req_length = x_length;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
req_id <= 2'b0;
eot_id <= 2'b0;
req_eot <= 1'b0;
end else begin
if (out_req_valid && out_req_ready) begin
req_id <= req_id + 1'b1;
last_req[req_id] <= y_length == 0;
end
req_eot <= 1'b0;
if (out_eot) begin
eot_id <= eot_id + 1'b1;
req_eot <= last_req[eot_id];
end
end
end
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
dest_address <= 'h00;
src_address <= 'h00;
x_length <= 'h00;
y_length <= 'h00;
dest_stride <= 'h00;
src_stride <= 'h00;
req_ready <= 1'b1;
out_req_valid <= 1'b0;
out_req_sync_transfer_start <= 1'b0;
end else begin
if (req_ready) begin
if (req_valid) begin
dest_address <= req_dest_address;
src_address <= req_src_address;
x_length <= req_x_length;
y_length <= req_y_length;
dest_stride <= req_dest_stride;
src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start;
req_ready <= 1'b0;
out_req_valid <= 1'b1;
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin
out_req_valid <= 1'b0;
req_ready <= 1'b1;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int countbit(int n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } int lowbit(int n) { return (n ^ (n - 1)) & n; } const double pi = acos(-1.0); const double eps = 1e-11; template <class T> T sqr(T x) { return x * x; } int n, m, k; int c[101], clen; bool Nim(int k) { for (int i = 0; i < 8; ++i) { int sum = 0; for (int j = 0; j < clen; ++j) sum += (c[j] >> i) & 1; if (sum % (k + 1)) return true; } return false; } int main() { scanf( %d%d%d , &n, &m, &k); int aw = 0, bw = 0; for (int i = 0; i < n; ++i) { char str[101]; char *pos, *pos1, *pos2; scanf( %s , str); pos = strchr(str, - ); pos2 = strchr(str, R ); pos1 = strchr(str, G ); if (pos && !pos1 && pos2) bw = 1; if (pos && !pos2 && pos1) aw = 1; if (pos1 && pos2) c[clen++] = abs(pos1 - pos2) - 1; } if (aw && bw) { printf( Draw n ); return 0; } else if (aw) { printf( First n ); return 0; } else if (bw) { printf( Second n ); return 0; } if (Nim(k)) printf( First n ); else printf( Second n ); return 0; } |
`timescale 1ns / 1ps
module Controlador_Menu_Editor(
clk,
reset,
boton_arriba_in,
boton_abajo_in,
boton_izq_in,
boton_der_in,
boton_elige_in,
//boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige,
text_red,
text_green,
text_blue,
char_scale,
es_mayuscula,
text_red_temp,
text_green_temp,
text_blue_temp,
char_scale_temp,
es_mayuscula_temp,
nuevo,
guardar,
cerrar,
where_fila,
where_columna
);
input clk, reset;
input boton_arriba_in, boton_abajo_in, boton_izq_in, boton_der_in, boton_elige_in;
wire boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige;
Navegador_PushButtons nav_pb(
.clk_100Mhz (clk),
.boton_arriba_in (boton_arriba_in),
.boton_abajo_in (boton_abajo_in),
.boton_izq_in (boton_izq_in),
.boton_der_in (boton_der_in),
.boton_elige_in (boton_elige_in),
.boton_arriba_out (boton_arriba),
.boton_abajo_out (boton_abajo),
.boton_izq_out (boton_izq),
.boton_der_out (boton_der),
.boton_elige_out (boton_elige)
);
output reg [2:0] where_fila;
output reg [2:0] where_columna;
output reg [9:0] char_scale;
output wire [9:0] char_scale_temp;
output reg text_red, text_green, text_blue, es_mayuscula;
output wire text_red_temp, text_green_temp, text_blue_temp, es_mayuscula_temp;
output reg nuevo, guardar, cerrar;
assign text_red_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 0 :
(where_fila == 5 && where_columna == 4)? 1 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_green_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 1 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 0 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_blue_temp = (where_fila == 5 && where_columna == 1)? 1 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 0 : 1;
assign es_mayuscula_temp = (where_fila == 4 && where_columna == 2)? 0 : 1;
assign char_scale_temp = (where_fila == 6 && where_columna == 1)? 10'd1 :
(where_fila == 6 && where_columna == 2)? 10'd2 :
(where_fila == 6 && where_columna == 3)? 10'd3 :
10'd2;
initial begin
where_fila <= 1;
where_columna <= 1;
char_scale <= 10'd2;
text_red <= 1'b0;
text_green <= 1'b0;
text_blue <= 1'b1;
es_mayuscula <= 1'b1;
nuevo <= 1'b0;
guardar <= 1'b0;
cerrar <= 1'b0;
end
wire temp_clk;
assign temp_clk = (boton_abajo || boton_izq || boton_arriba || boton_der || boton_elige);
reg [2:0] estado, sigEstado;
parameter inicio = 0;
parameter aumenta_fila = 1;
parameter disminuye_fila = 2;
parameter aumenta_columna = 3;
parameter disminuye_columna = 4;
parameter elige = 5;
always @(posedge clk or posedge reset) begin
if (reset)
estado <= inicio;
else
estado <= sigEstado;
end
always @(posedge temp_clk) begin
case (estado)
inicio:
begin
if (boton_arriba)
sigEstado = disminuye_columna;
else if (boton_abajo)
sigEstado = aumenta_columna;
else if (boton_izq)
sigEstado = disminuye_fila;
else if (boton_der)
sigEstado = aumenta_fila;
else if (boton_elige)
sigEstado = elige;
else
sigEstado = inicio;
end
aumenta_fila:
begin
nuevo = 0;
where_columna = 1;
where_fila = (where_fila < 6)? where_fila + 1 : where_fila;
sigEstado = inicio;
end
disminuye_fila:
begin
where_columna = 1;
where_fila = (where_fila > 1)? where_fila - 1 : where_fila;
sigEstado = inicio;
end
aumenta_columna:
begin
case (where_fila)
4:
where_columna = (where_columna < 2)? where_columna + 1: where_columna;
5:
where_columna = (where_columna < 6)? where_columna + 1: where_columna;
6:
where_columna = (where_columna < 3)? where_columna + 1: where_columna;
endcase
sigEstado = inicio;
end
disminuye_columna:
begin
where_columna = (where_columna > 1)? where_columna - 1 : where_columna;
sigEstado = inicio;
end
elige:
begin
case (where_fila)
1:
nuevo = 1;
2:
guardar = 1;
3:
cerrar = 1;
4:
begin
case (where_columna)
1:
es_mayuscula = 1;
2:
es_mayuscula = 0;
endcase
end
5:
begin
case (where_columna)
1:
begin
text_red = 0;
text_green = 0;
text_blue = 1;
end
2:
begin
text_red = 0;
text_green = 1;
text_blue = 0;
end
3:
begin
text_red = 0;
text_green = 1;
text_blue = 1;
end
4:
begin
text_red = 1;
text_green = 0;
text_blue = 0;
end
5:
begin
text_red = 1;
text_green = 0;
text_blue = 1;
end
6:
begin
text_red = 1;
text_green = 1;
text_blue = 0;
end
endcase
end
6:
begin
case (where_columna)
1:
char_scale = 10'd1;
2:
char_scale = 10'd2;
3:
char_scale = 10'd3;
endcase
end
endcase
sigEstado = inicio;
end
default: sigEstado = inicio;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MXN = 80 + 10; const long long MX5 = 4e5 + 10; const long long MX6 = 1e6 + 10; const long long LOG = 20; const long long INF = 8e18; const double eps = 1e-9; const long long MOD = 1e9 + 7; long long power(long long a, long long b, long long md) { return (!b ? 1 : (b & 1 ? a * power(a * a % md, b / 2, md) % md : power(a * a % md, b / 2, md) % md)); } long long bmm(long long a, long long b) { return (a % b == 0 ? b : bmm(b, a % b)); } string base2(long long n) { string a = ; while (n >= 2) { a += (char)(n % 2 + 0 ); n /= 2; } a += (char)(n + 0 ); reverse((a).begin(), (a).end()); return a; } long long n; long long PS[MX5], Ans[MX5], ex[MX5]; vector<long long> second, T; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { long long x; cin >> x; second.push_back(x); } for (int i = 0; i < n; i++) { long long x; cin >> x; T.push_back(x); } PS[0] = T[0]; for (int i = 1; i < n; i++) PS[i] = PS[i - 1] + T[i]; PS[n] = INF; for (int i = 0; i < n; i++) { long long men = (i - 1 < 0 ? 0 : PS[i - 1]); if (second[i] <= T[i]) { ex[i] += second[i]; continue; } long long l = i, r = n; while (r - l > 1) { long long mid = (l + r) / 2; if (PS[mid] - men <= second[i]) { l = mid; } else { r = mid; } } Ans[l + 1]--, Ans[i]++; if (PS[l] - men < second[i]) { ex[l + 1] += second[i] - PS[l] + men; } } for (int i = 1; i < n; i++) Ans[i] += Ans[i - 1]; for (int i = 0; i < n; i++) { cout << Ans[i] * T[i] + ex[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5; long long pref1[N + 5]; long long pref2[N + 5]; long long ans; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, type, l, r; cin >> n; n++; int arr[n]; for (int i = 1; i < n; i++) { cin >> arr[i]; pref1[i] = pref1[i - 1] + arr[i]; } sort(arr + 1, arr + n); for (int i = 1; i < n; i++) pref2[i] = pref2[i - 1] + arr[i]; cin >> m; while (m--) { cin >> type >> l >> r; if (type == 1) ans = pref1[r] - pref1[l - 1]; else ans = pref2[r] - pref2[l - 1]; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10; int mod = 1e9 + 7; int qpow(int a, int b) { int ans = 1; for (; b >= 1; b >>= 1, a = (long long)a * a % mod) if (b & 1) ans = (long long)ans * a % mod; return ans; } long long ans[32]; int main() { int t; scanf( %d , &t); while (t--) { int d, m, c; scanf( %d%d , &d, &mod); fill(ans, ans + 30, 0); for (c = 0; (1 << (c + 1)) <= d; c++) ; for (int i = 0; i < c; i++) ans[i] = (1ll << i) % mod; ans[c] = (d - (1ll << c) + 1) % mod; long long res = 1; for (int i = 0; i <= c; i++) res = res * (ans[i] + 1ll) % mod; res = (res + mod - 1) % mod; printf( %lld n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; string s[70010]; map<pair<int, int>, int> m; pair<int, int> ans[70010]; int main() { int k = 64, p = 5; int n, i, j, l; cin >> n; for (i = 1; i <= n; i++) cin >> s[i]; for (i = 1; i <= n; i++) for (j = 0; j < 9; j++) { int x = 0; for (l = j; l < 9; l++) { x = x * 10 + s[i][l] - 0 ; if (m.find(pair<int, int>(x, l - j + 1)) != m.end() && m[pair<int, int>(x, l - j + 1)] != i) m[pair<int, int>(x, l - j + 1)] = -1; else m[pair<int, int>(x, l - j + 1)] = i; } } for (auto it = m.begin(); it != m.end(); it++) { if (it->second == -1) continue; if (ans[it->second].second == 0 || ans[it->second].second > it->first.second) ans[it->second] = pair<int, int>(it->first.first, it->first.second); } for (i = 1; i <= n; i++) { char s[10]; sprintf(s, %%0%dd n , ans[i].second); printf(s, ans[i].first); } return 0; } |
`define ADDER_WIDTH 014
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; char s[200010]; int n, k; int sa[200010]; int ra[200010], tr[200010]; int lcp[200010]; int l[200010], r[200010]; stack<int> ls, rs; set<long long> ss; bool CmpSa(int a, int b) { if (ra[a] != ra[b]) return ra[a] < ra[b]; int aa = a + k < n ? ra[a + k] : -1; int bb = b + k < n ? ra[b + k] : -1; return aa < bb; } void GaoSa() { for (int i = 0; i <= n; ++i) { sa[i] = i; ra[i] = i < n ? s[i] : -1; } for (k = 1; k <= n; k <<= 1) { sort(sa, sa + n + 1, CmpSa); tr[sa[0]] = 0; for (int i = 1; i <= n; ++i) { tr[sa[i]] = tr[sa[i - 1]] + CmpSa(sa[i - 1], sa[i]); } memcpy(ra, tr, sizeof(int) * (n + 1)); } } void GaoLcp() { int tmp = 0; for (int i = 0; i < n; ++i) { int rk = ra[i]; int j = sa[rk - 1]; if (tmp > 0) --tmp; while (i + tmp < n && j + tmp < n && s[i + tmp] == s[j + tmp]) { ++tmp; } lcp[rk - 1] = tmp; } } inline long long Hash(int b, int c) { return b * 1000000ll + c; } int main() { scanf( %s , s); n = strlen(s); s[n] = | ; memcpy(s + n + 1, s, sizeof(char) * n); n = 2 * n + 1; GaoSa(); GaoLcp(); for (int i = 0; i <= n; ++i) { while (!rs.empty() && lcp[rs.top()] > lcp[i]) { r[rs.top()] = i; rs.pop(); } rs.push(i); } for (int i = n; i >= 0; --i) { while (!ls.empty() && lcp[ls.top()] > lcp[i]) { l[ls.top()] = i; ls.pop(); } ls.push(i); } long long ans = 0; for (int i = 1; i < n - 1; ++i) { if (lcp[i]) { if (ss.find(Hash(lcp[i], l[i])) != ss.end()) continue; long long tmp = (r[i] - l[i]) / 2; tmp = tmp * (tmp + 1) / 2; ans += tmp * (lcp[i] - max(lcp[l[i]], lcp[r[i]])); ss.insert(Hash(lcp[i], l[i])); } } cout << ans << endl; return 0; } |
module bram1 #(
parameter ABITS = 8, DBITS = 8, TRANSP = 0
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
initial begin
memory[INIT_ADDR_0] <= INIT_DATA_0;
memory[INIT_ADDR_1] <= INIT_DATA_1;
memory[INIT_ADDR_2] <= INIT_DATA_2;
memory[INIT_ADDR_3] <= INIT_DATA_3;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;
RD_DATA_BUF <= memory[RD_ADDR];
end
assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_SYMBOL_V
`define SKY130_FD_SC_MS__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_SYMBOL_V
`define SKY130_FD_SC_HD__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long h, w, n; pair<long long, long long> a[2005]; long long fact[200005]; long long ifact[200005]; long long dp[2005]; long long exp(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a; if (b % 2 == 0) { long long r = exp(a, b / 2); return (r * r) % 1000000007; } long long r = exp(a, b - 1); return (r * a) % 1000000007; } long long C(long long n, long long k) { return (((fact[n] * ifact[k]) % 1000000007) * ifact[n - k]) % 1000000007; } int main() { scanf( %lld %lld %lld , &h, &w, &n); for (long long i = 0; i < n; i++) { scanf( %lld %lld , &a[i].first, &a[i].second); a[i].first--; a[i].second--; } sort(a, a + n); a[n++] = make_pair(h - 1, w - 1); fact[0] = 1; ifact[0] = 1; for (long long i = 1; i <= max(w, h) * 2; i++) { fact[i] = (fact[i - 1] * i) % 1000000007; ifact[i] = exp(fact[i], 1000000007 - 2); } for (long long i = 0; i < n; i++) { long long num = C(a[i].first + a[i].second, a[i].first); for (long long j = 0; j < i; j++) { if (a[j].first <= a[i].first && a[j].second <= a[i].second) { int sub = (dp[j] * C((a[i].first - a[j].first) + (a[i].second - a[j].second), a[i].first - a[j].first)) % 1000000007; num = (num - sub + 1000000007) % 1000000007; } } dp[i] = num; } cout << dp[n - 1] << endl; } |
#include <bits/stdc++.h> using namespace std; struct node { long long s, mn, mx; }; node T[303030]; node operator+(node l, node r) { node x; x.s = l.s + r.s; x.mn = min(l.mn, l.s + r.mn); x.mx = max(l.mx, l.s + r.mx); return x; } int A[100009]; void init(int idx, int s, int e) { if (s == e) { T[idx] = {A[s], min(A[s], 0), max(A[s], 0)}; return; } int m = s + e >> 1; init(idx * 2, s, m); init(idx * 2 + 1, m + 1, e); T[idx] = T[idx * 2] + T[idx * 2 + 1]; } node get(int idx, int s, int e, int l, int r) { if (r < s || e < l) return (node){0, 0, 0}; if (l <= s && e <= r) return T[idx]; int m = s + e >> 1; return get(idx * 2, s, m, l, r) + get(idx * 2 + 1, m + 1, e, l, r); } int main() { int N, Q; scanf( %d%d , &N, &Q); for (int i = 1; i <= N; i++) scanf( %d , &A[i]); for (int i = 1; i <= N; i++) { int x; scanf( %d , &x); A[i] = x - A[i]; } init(1, 1, N); while (Q--) { int l, r; scanf( %d%d , &l, &r); node x = get(1, 1, N, l, r); if (x.mn < 0 || x.s != 0) puts( -1 ); else printf( %lld n , x.mx); } return 0; } |
`timescale 1ns / 1ps
module Print(
input clk, // ʱÖÓÐźÅ
input [15:0] num, // ÒªÏÔʾµÄ4λÊý
input [3:0] flash, // 4λ, ÊÇ·ñÉÁ˸, 1 => true, 0 => false
output reg [7:0] display, // Êä³ö, 8λ¶ÎÑ¡¶Ë(CA, CB, CC, CD, CE, CF, CG, DP)
output reg [3:0] an // Êä³ö, 4λλѡ¶Ë
);
reg flash_state; // µ±Ç°ÉÁ˸״̬, 1 => ´¦ÓÚÉÁ˸״̬
reg [3:0] tmp;
reg [15:0] counter;
reg [31:0] flash_counter;
reg [3:0] an_tmp;
parameter [15:0] MAX_COUNTER = 16'D5_0000;
parameter [31:0] MAX_FLASH_COUNTER = 32'D5000_0000;
initial begin
an_tmp = 4'B0111;
counter = 0;
flash_counter = 0;
flash_state = 0;
end
always@(an_tmp) begin
case(an_tmp)
4'B0111: tmp = num[15:12];
4'B1011: tmp = num[11:8];
4'B1101: tmp = num[7:4];
4'B1110: tmp = num[3:0];
endcase
case(tmp)
4'H0: display = 8'B0000_0011;
4'H1: display = 8'B1001_1111;
4'H2: display = 8'B0010_0101;
4'H3: display = 8'B0000_1101;
4'H4: display = 8'B1001_1001;
4'H5: display = 8'B0100_1001;
4'H6: display = 8'B0100_0001;
4'H7: display = 8'B0001_1111;
4'H8: display = 8'B0000_0001;
4'H9: display = 8'B0000_1001;
endcase
end
always@(posedge clk) begin
// ÏÔʾɨÃè
counter = counter + 1;
if(counter == MAX_COUNTER) begin
an_tmp = (an_tmp >> 1) + 4'B1000;
counter = 0;
end
if(an_tmp == 4'B1111) begin
an_tmp = 4'B0111;
end
// ÉÁ˸ɨÃè
flash_counter = flash_counter + 1;
if(flash_counter == MAX_FLASH_COUNTER) begin
flash_counter = 0;
flash_state = ~flash_state;
end
// »ñµÃ×îÖÕanÖµ
if(flash_state) an = an_tmp | flash;
else an = an_tmp;
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:24:21 12/06/2016
// Design Name:
// Module Name: vga_sync
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_sync(
input wire clk, clr,
output reg hsync, vsync,
output wire video_on,
output wire [9:0] pixel_x, pixel_y
);
parameter hpixels = 800;
parameter vlines = 525;
parameter hbp = 144;
parameter hfp = 784;
parameter vbp = 35;
parameter vfp = 515;
reg [9:0] hc, vc;
assign pixel_x = hc - hbp - 1;
assign pixel_y = vc - vbp - 1;
always @ (posedge clk or posedge clr)
begin
if (clr == 1)
hc <= 0;
else
begin
if (hc == hpixels - 1)
begin
hc <= 0;
end
else
begin
hc <= hc + 1;
end
end
end
always @*
begin
if(hc >= 96)
hsync = 1;
else
hsync = 0;
end
always @(posedge clk or posedge clr)
begin
if (clr == 1)
begin
vc <= 0;
end
else
begin
if (hc == hpixels - 1)
begin
if (vc == vlines - 1)
begin
vc <= 0;
end
else
begin
vc <= vc + 1;
end
end
end
end
always @*
begin
if(vc >= 2)
vsync = 1;
else
vsync = 0;
end
assign video_on = (hc < hfp) && (hc > hbp) && (vc < vfp) && (vc > vbp);
endmodule
|
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: one_wire_io.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// Rev: Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module one_wire_io (
CLK, DDIR, DOUT, DQ_CONTROL, MR, DIN, DQ_IN, DATA_IN, DATA_OUT,
DQ0_T, DQ1_T, DQ2_T, DQ3_T, DQ4_T, DQ5_T, DQ6_T, DQ7_T,
DQ0_O, DQ1_O, DQ2_O, DQ3_O, DQ4_O, DQ5_O, DQ6_O, DQ7_O,
DQ0_I, DQ1_I, DQ2_I, DQ3_I, DQ4_I, DQ5_I, DQ6_I, DQ7_I, DQ_SEL);
input CLK;
input DDIR;
input [7:0] DOUT;
input DQ_CONTROL;
input MR;
output [7:0] DIN;
output DQ_IN;
input [7:0] DATA_IN;
output [7:0] DATA_OUT;
output DQ0_T;
output DQ1_T;
output DQ2_T;
output DQ3_T;
output DQ4_T;
output DQ5_T;
output DQ6_T;
output DQ7_T;
output DQ0_O;
output DQ1_O;
output DQ2_O;
output DQ3_O;
output DQ4_O;
output DQ5_O;
output DQ6_O;
output DQ7_O;
input DQ0_I;
input DQ1_I;
input DQ2_I;
input DQ3_I;
input DQ4_I;
input DQ5_I;
input DQ6_I;
input DQ7_I;
input [2:0] DQ_SEL;
reg DQ_IN;
assign DATA_OUT = DOUT;
assign DIN = DATA_IN;
//assign DQ =DQ_CONTROL==1?1'bz:1'b0;
wire DQ_INTERNAL;
// IOBUF xIOBUF(
// .T (DQ_CONTROL ),
// .I (1'b0 ),
// .O (DQ_INTERNAL),
// .IO (DQ )
// );
// assign DQ_T = DQ_CONTROL;
// assign DQ_O = 1'b0;
// assign DQ_INTERNAL = DQ_I;
assign DQ0_T = (DQ_SEL [2:0] == 0) ? DQ_CONTROL : 1'b1;
assign DQ1_T = (DQ_SEL [2:0] == 1) ? DQ_CONTROL : 1'b1;
assign DQ2_T = (DQ_SEL [2:0] == 2) ? DQ_CONTROL : 1'b1;
assign DQ3_T = (DQ_SEL [2:0] == 3) ? DQ_CONTROL : 1'b1;
assign DQ4_T = (DQ_SEL [2:0] == 4) ? DQ_CONTROL : 1'b1;
assign DQ5_T = (DQ_SEL [2:0] == 5) ? DQ_CONTROL : 1'b1;
assign DQ6_T = (DQ_SEL [2:0] == 6) ? DQ_CONTROL : 1'b1;
assign DQ7_T = (DQ_SEL [2:0] == 7) ? DQ_CONTROL : 1'b1;
assign DQ0_O = 1'b0;
assign DQ1_O = 1'b0;
assign DQ2_O = 1'b0;
assign DQ3_O = 1'b0;
assign DQ4_O = 1'b0;
assign DQ5_O = 1'b0;
assign DQ6_O = 1'b0;
assign DQ7_O = 1'b0;
assign DQ_INTERNAL = (DQ_SEL [2:0] == 0) & DQ0_I
| (DQ_SEL [2:0] == 1) & DQ1_I
| (DQ_SEL [2:0] == 2) & DQ2_I
| (DQ_SEL [2:0] == 3) & DQ3_I
| (DQ_SEL [2:0] == 4) & DQ4_I
| (DQ_SEL [2:0] == 5) & DQ5_I
| (DQ_SEL [2:0] == 6) & DQ6_I
| (DQ_SEL [2:0] == 7) & DQ7_I;
//
// Synchronize DQ_IN
//
always @(posedge MR or negedge CLK)
if (MR)
DQ_IN <= 1'b1;
else
DQ_IN <= DQ_INTERNAL;
endmodule // one_wire_io |
module top;
reg passed;
reg signed[95:0] m_one, m_two, zero, one, two;
// Both argument positive.
reg signed[95:0] rem;
wire signed[95:0] wrem = two / one;
// First argument negative.
reg signed[95:0] rem1n;
wire signed[95:0] wrem1n = m_two / one;
// Second argument negative.
reg signed[95:0] rem2n;
wire signed[95:0] wrem2n = two / m_one;
// Both arguments negative.
reg signed[95:0] rembn;
wire signed[95:0] wrembn = m_two / m_one;
// Divide by zero.
reg signed[95:0] remd0;
wire signed[95:0] wremd0 = one / zero;
initial begin
passed = 1'b1;
m_one = 96'hffffffffffffffffffffffff;
m_two = 96'hfffffffffffffffffffffffe;
zero = 96'h000000000000000000000000;
one = 96'h000000000000000000000001;
two = 96'h000000000000000000000002;
#1;
// Both positive.
if (wrem !== 96'h000000000000000000000002) begin
$display("Failed: CA divide, expected 96'h00...02, got %h",
wrem);
passed = 1'b0;
end
rem = two / one;
if (rem !== 96'h000000000000000000000002) begin
$display("Failed: divide, expected 96'h00...02, got %h",
rem);
passed = 1'b0;
end
// First negative.
if (wrem1n !== 96'hfffffffffffffffffffffffe) begin
$display("Failed: CA divide (1n), expected 96'hff...fe, got %h",
wrem1n);
passed = 1'b0;
end
rem1n = m_two / one;
if (rem1n !== 96'hfffffffffffffffffffffffe) begin
$display("Failed: divide (1n), expected 96'hff...fe, got %h",
rem1n);
passed = 1'b0;
end
// Second negative.
if (wrem2n !== 96'hfffffffffffffffffffffffe) begin
$display("Failed: CA divide (2n), expected 96'hff...fe, got %h",
wrem2n);
passed = 1'b0;
end
rem2n = two / m_one;
if (rem2n !== 96'hfffffffffffffffffffffffe) begin
$display("Failed: divide (2n), expected 96'hff...fe, got %h",
rem2n);
passed = 1'b0;
end
// Both negative.
if (wrembn !== 96'h000000000000000000000002) begin
$display("Failed: CA divide (bn), expected 96'h00...02, got %h",
wrembn);
passed = 1'b0;
end
rembn = m_two / m_one;
if (rembn !== 96'h000000000000000000000002) begin
$display("Failed: divide (bn), expected 96'h00...02, got %h",
rembn);
passed = 1'b0;
end
// Divide by zero.
if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: CA divide (d0), expected 96'hxx...xx, got %h",
wremd0);
passed = 1'b0;
end
remd0 = one / zero;
if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: divide (d0), expected 96'hxx...xx, got %h",
remd0);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t-- > 0) { int n; cin >> n; int a; int f[51] = {0}; for (int i = 0; i < 2 * n; i++) { cin >> a; if (f[a] == 0) { f[a]++; cout << a << ; } } std::cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, m, k; int h; while (scanf( %d%d%d , &n, &m, &h) != EOF) { int sum1, sum2; sum1 = sum2 = 0; for (i = 1; i <= m; i++) { scanf( %d , &k); if (i == h) sum1 = k; else sum2 += k; } k = n - 1; if (sum1 + sum2 < n) puts( -1 ); else if (sum2 < k - 1) puts( 1 ); else { k = n - 1; h = sum2; double ans = 1; for (i = 1; i <= k; i++) { ans *= h; h--; } h = sum2 + sum1 - 1; for (i = 1; i <= k; i++) { ans /= h; h--; } printf( %.7lf n , 1 - ans); } } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] in = crc[3:0];
wire clken = crc[4];
wire rstn = !(cyc < 20 || (crc[11:8]==0));
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ff_out; // From test of Test.v
wire [3:0] fg_out; // From test of Test.v
wire [3:0] fh_out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_out (ff_out[3:0]),
.fg_out (fg_out[3:0]),
.fh_out (fh_out[3:0]),
// Inputs
.clk (clk),
.clken (clken),
.rstn (rstn),
.in (in[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, ff_out, fg_out, fh_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(/*AUTOARG*/
// Outputs
ff_out, fg_out, fh_out,
// Inputs
clk, clken, rstn, in
);
input clk;
input clken;
input rstn;
input [3:0] in;
output reg [3:0] ff_out;
reg [3:0] ff_10;
reg [3:0] ff_11;
reg [3:0] ff_12;
reg [3:0] ff_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
ff_10 <= 0;
ff_11 <= 0;
ff_12 <= 0;
ff_13 <= 0;
end
else begin
ff_10 <= in;
ff_11 <= ff_10;
ff_12 <= ff_11;
ff_13 <= ff_12;
ff_out <= ff_13;
end
end
output reg [3:0] fg_out;
reg [3:0] fg_10;
reg [3:0] fg_11;
reg [3:0] fg_12;
reg [3:0] fg_13;
always @(posedge clk) begin
if (clken) begin
if ((rstn == 0)) begin
fg_10 <= 0;
fg_11 <= 0;
fg_12 <= 0;
fg_13 <= 0;
end
else begin
fg_10 <= in;
fg_11 <= fg_10;
fg_12 <= fg_11;
fg_13 <= fg_12;
fg_out <= fg_13;
end
end
end
output reg [3:0] fh_out;
reg [3:0] fh_10;
reg [3:0] fh_11;
reg [3:0] fh_12;
reg [3:0] fh_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
fh_10 <= 0;
fh_11 <= 0;
fh_12 <= 0;
fh_13 <= 0;
end
else begin
if (clken) begin
fh_10 <= in;
fh_11 <= fh_10;
fh_12 <= fh_11;
fh_13[3:1] <= fh_12[3:1];
fh_13[0] <= fh_12[0];
fh_out <= fh_13;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = int(1e9); const double EPS = 1e-5; const long long mod = ((long long)1e18) - 131; int n, m, ans = 0; set<string> h; string s; int main() { cin >> s; for (int i = 0; i < s.length(); i++) for (int j = i; j < s.length(); j++) { if (h.count(s.substr(i, j - i + 1))) ans = max(ans, j - i + 1); else h.insert(s.substr(i, j - i + 1)); } printf( %d , ans); return 0; } |
// Lab 4
// Created by David Tran
// Last Modified 02-05-2014
// extras
`timescale 1 ms /1 us
`include "four_bit_adder.v"
// Testbench Module
module four_bit_adder_tb (A0, A1, A2, A3, B0, B1, B2, B3,
output A0, A1, A2, A3, B0, B1, B2, B3, C0;
reg A0, A1, A2, A3, B0, B1, B2, B3, C0;
wire D0, D1, D2, D3, D4;
reg t_A0 [5000:0];
reg t_A1 [5000:0];
reg t_A2 [5000:0];
reg t_A3 [5000:0];
reg t_B0 [5000:0];
reg t_B1 [5000:0];
reg t_B2 [5000:0];
reg t_B3 [5000:0];
reg t_C0 [5000:0];
reg t_clock;
reg [31:0] vectornum; //Values from 0 -> 2^31
integer fp;
four_bit_adder I1 (A0, A1, A2, A3, B0, B1, B2, B3, C0, D0, D1, D2, D3, D4);
//initial #1000 $finish;
initial
begin
t_clock=0;
forever #5 t_clock=~t_clock;
end
initial
begin
$readmemb("./bit_str_a_0.txt",t_A0);
$readmemb("./bit_str_a_1.txt",t_A1);
$readmemb("./bit_str_a_2.txt",t_A2);
$readmemb("./bit_str_a_3.txt",t_A3);
$readmemb("./bit_str_b_0.txt",t_B0);
$readmemb("./bit_str_b_1.txt",t_B1);
$readmemb("./bit_str_b_2.txt",t_B2);
$readmemb("./bit_str_b_3.txt",t_B3);
$readmemb("./bit_str_c_0.txt",t_C0);
vectornum=0; // Set test vector 0
end
always @(posedge t_clock)
begin
A0<=t_A0[vectornum];
A1<=t_A1[vectornum];
A2<=t_A2[vectornum];
A3<=t_A3[vectornum];
B0<=t_B0[vectornum];
B1<=t_B1[vectornum];
B2<=t_B2[vectornum];
B3<=t_B3[vectornum];
C0<=t_C0[vectornum];
vectornum<=vectornum+1;
end
initial
begin
//fp=$fopen("four_bit_adder_tb.out");
//$fmonitor(fp, "time=%0d", $time,, "A=%b B=%b D=%b S=%b C=%b", A, B, D, S, C);
$monitor("time=%03d", $time,,
//"A0=%b, A1=%b, A2=%b, A3=%b, B0=%b, B1=%b, B2=%b, B3=%b, C0=%b | D0=%b, D1=%b, D2=%b, D3=%b, D4=%b",
//"A=%b%b%b%b B=%b%b%b%b, C0=%b | D0=%b, D1=%b, D2=%b, D3=%b, D4=%b",
"A=%b%b%b%b B=%b%b%b%b, C=%b | D=%b%b%b%b%b",
A3, A2, A1, A0,
B3, B2, B1, B0,
C0,
D4, D3, D2, D1, D0,
);
$dumpfile("fulladder.vcd");
$dumpvars;
#1000
//$fclose(fp);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void prepare() {} void solve() { string s; cin >> s; set<int> ss[26]; for (int i = 0; i < s.size(); ++i) ss[s[i] - a ].insert(i); int i = 25; int cur = -1; while (i != -1) { if (ss[i].empty()) { --i; continue; } while (!ss[i].empty() && *ss[i].begin() < cur) ss[i].erase(ss[i].begin()); if (ss[i].empty()) { --i; continue; } for (int j = 0; j < ss[i].size(); ++j) printf( %c , i + a ); cur = *(--ss[i].end()); --i; } } int main() { prepare(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int num : a) { m -= num; } if (m != 0) cout << NO << endl; else cout << YES << endl; } } |
/*
# ZUMA Open FPGA Overlay
# Alex Brant
# Email:
# 2012
# LUTRAM wrapper
*/
`include "def_generated.v"
module elut_custom #(
parameter used = 0,
parameter [0:2**6-1] LUT_MASK={2**6{1'b0}}
) (
a,
d,
dpra,
clk,
we,
dpo,
qdpo_clk,
qdpo_rst,
qdpo);
input [5 : 0] a;
input [0 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
input qdpo_clk;
input qdpo_rst;
output dpo;
output qdpo;
wire lut_output;
wire lut_registered_output;
//no plattform. just for a verificational build.
generate
if( used == 1)
begin
//we generate a lut and a latch
LUT_K #(
.K(6),
.LUT_MASK(LUT_MASK)
) verification_lut2 (
.in(dpra),
.out(lut_output)
);
DFF #(
.INITIAL_VALUE(1'b0)
) verification_latch (
.D(lut_output),
.Q(lut_registered_output),
.clock(qdpo_clk)
);
end
else
begin
assign lut_output = 1'b0;
assign lut_registered_output = 1'b0;
end
endgenerate
assign dpo = lut_output;
assign qdpo = lut_registered_output;
endmodule
|
module top;
/***********
* Check parameters.
***********/
// Check parameter/parameter name issues.
parameter name_pp = 1;
parameter name_pp = 0;
parameter name_pl = 1;
localparam name_pl = 0;
localparam name_lp = 0;
parameter name_lp = 1;
localparam name_ll = 1;
localparam name_ll = 0;
/***********
* Check genvars.
***********/
// Check genvar/genvar name issues.
genvar name_vv;
genvar name_vv;
/***********
* Check tasks.
***********/
// Check task/task name issues.
task name_tt;
$display("FAILED in task name_tt(a)");
endtask
task name_tt;
$display("FAILED in task name_tt(b)");
endtask
// Check that task/task checks work in a generate block.
generate
begin: task_blk
task name_tt;
$display("FAILED in task name_tt(a)");
endtask
task name_tt;
$display("FAILED in task name_tt(b)");
endtask
end
endgenerate
/***********
* Check functions.
***********/
// Check function/function name issues.
function name_ff;
input in;
name_ff = in;
endfunction
function name_ff;
input in;
name_ff = 2*in;
endfunction
// Check that function/function checks work in a generate block.
generate
begin: task_blk
function name_ff;
input in;
name_ff = in;
endfunction
function name_ff;
input in;
name_ff = 2*in;
endfunction
end
endgenerate
/***********
* Check named events
***********/
// Check named event/named event name issues.
event name_ee;
event name_ee;
initial name_tt;
specify
specparam name_ss = 1;
specparam name_ss = 0;
endspecify
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_enable,
src_adc_valid,
src_adc_data,
dst_adc_enable,
dst_adc_valid,
dst_adc_data
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_enable;
input src_adc_valid;
input [15:0] src_adc_data;
output dst_adc_enable;
output dst_adc_valid;
output [15:0] dst_adc_data;
reg dst_adc_enable;
reg dst_adc_valid;
reg [15:0] dst_adc_data;
reg [31:0] status = 0;
reg [15:0] adc_pn_data = 0;
reg [ 3:0] mode;
reg [ 3:0] channel_sel;
wire adc_dvalid;
wire [15:0] adc_pn_data_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
assign adc_dvalid = src_adc_enable & src_adc_valid;
always @(posedge clk) begin
channel_sel <= control[3:0];
mode <= control[7:4];
end
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
end
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(32)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in(src_adc_ddata),
.adc_data_pn(adc_pn_data),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// rx path are passed through on test mode
always @(posedge clk) begin
dst_adc_enable <= src_adc_enable;
dst_adc_data <= src_adc_data;
dst_adc_valid <= src_adc_valid;
end
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2012, Jahanzeb Ahmad
/// All rights reserved.
///
/// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
/*!
HDMI rom for storing edid structure. This structure has one extenstion block contains the HDMI resolutions.
*/
module hdmirom(clk,adr,data);
input clk;
input [7:0] adr;
output [7:0] data;
reg [7:0] data ;
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
initial $readmemh("..//hdl//edid//hdmirom.hex", mem);
always @ (posedge clk)
begin
data <= mem[adr];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Team { string name; int fi, se, th; } t[60]; int cmp(Team a, Team b) { if (a.fi != b.fi) return a.fi > b.fi; else if (a.se != b.se) return a.se > b.se; else return a.th > b.th; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> t[i].name; t[i].fi = t[i].se = t[i].th = 0; } for (int i = 0; i < n * (n - 1) / 2; i++) { string te, t1, t2; int a, b; char ch; cin >> te >> a >> ch >> b; t1 = te.substr(0, te.find( - )); t2 = te.substr(te.find( - ) + 1); for (int j = 0; j < n; j++) { if (t[j].name == t1) { if (a > b) t[j].fi += 3; else if (a == b) t[j].fi += 1; t[j].se += a - b; t[j].th += a; } if (t[j].name == t2) { if (a < b) t[j].fi += 3; else if (a == b) t[j].fi += 1; t[j].se += b - a; t[j].th += b; } } } string ans[30]; sort(t, t + n, cmp); for (int i = 0; i < n / 2; i++) ans[i] = t[i].name; sort(ans, ans + n / 2); for (int i = 0; i < n / 2; i++) cout << ans[i] << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Florian Beyer
//
// Create Date: 17:38:52 02/23/2017
// Design Name:
// Module Name: tb_SpongentHash
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_SpongentHash;
wire [87:0] hash;
reg [87:0] reference_hash;
reg clk;
reg rst;
reg en;
wire rdy;
SpongentHash uut (
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy),
.hash_out(hash)
);
initial begin
clk = 0;
rst = 1;
en = 0;
// Set reference Hash value, to test if the result is right.
// Hash for "Hello WorldHello World ZY"
// reference_hash = 88'ha9b5344ec2f458323a1acc;
// Hash for "Spongent is a lightweight Hashfunction"
reference_hash = 88'h06846ff7186c0cfa5dfd32;
#100;
rst = 0;
en = 1;
end
always begin
#5; clk = !clk;
end
always @ rdy begin
if (rdy == 1) begin
$display("hash %h", hash);
if (hash === reference_hash) begin
$display("SUCCESS");
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int A[101]; int B[101]; int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> A[i]; int t = n / k; for (int i = 0; i < k; i++) { int max1 = 0; int max2 = 0; for (int j = 0; j < t; j++) if (A[i + j * k] == 1) max1++; else max2++; if (max2 > max1) B[i] = 2; else B[i] = 1; } int d = 0; for (int i = 0; i < t; i++) { for (int j = 0; j < k; j++) if (A[i * k + j] != B[j]) d++; } cout << d; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; int a[11], b[11]; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , a + i); } for (int i = 0; i < m; i++) { scanf( %d , b + i); } sort(a, a + n); sort(b, b + m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i] == b[j]) { printf( %d n , a[i]); return 0; } } } if (a[0] > b[0]) printf( %d%d n , b[0], a[0]); else printf( %d%d n , a[0], b[0]); return 0; } |
#include <bits/stdc++.h> using namespace std; void CP() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); return; } int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; int a[n + 1]; a[1] = 1; for (int i = 2; i <= n; i++) { a[i] = a[i - 1] + i; } for (int i = 1; i <= n; i++) { cerr << a[i] << ; } cerr << endl; if (m == 1) { m -= 1; } else { if (m > a[n]) { m %= a[n]; cerr << m << endl; } int i; for (i = n - 1; i > 1; i--) { if (m >= a[i]) { m %= a[i]; break; } } if (i == 1 && m != 0) { m -= 1; } } cout << m << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * flag; } int n; int s[109]; int main() { n = read(); for (int i = (1), i_end_ = (n); i <= i_end_; ++i) { char c = getchar(); if (c == U ) s[i] = 1; if (c == R ) s[i] = 2; } int ans = 0, i = 1; while (i <= n) { if (s[i] == 1) if (s[i + 1] == 2) ++ans, i = i + 2; else i++; else if (s[i] == 2) if (s[i + 1] == 1) ++ans, i = i + 2; else i++; } printf( %d n , n - ans); return 0; } |
`timescale 1 ns / 1 ps
module elink2_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire [1:0] done;
wire [1:0] error;
// Create an instance of the example tb
elink_testbench dut
(.aclk (aclk),
.aresetn (aresetn),
.csysreq (csysreq),
.done0 (done[0]),
.done1 (done[1]),
.error0 (error[0]),
.error1 (error[1]),
.start (start));
// Reset Generator
initial begin
aresetn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge aclk);
aresetn = 1'b1;
end
// Clock Generator
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Drive the BFM
initial begin
start = 1'b0;
// Wait for end of reset
wait(aresetn === 0) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
#500 start = 1'b1;
$display("=== TB Started");
wait( done == 2'b11);
$display("=== TEST_FINISHED");
if ( error != 2'b00 ) begin
$display("===_TEST: FAILED!");
end else begin
$display("=== TEST: PASSED!");
end
end
always @ (posedge error[0])
if( error[0] == 1'b1 )
$display("=== ERROR FLAG 0 @ %t", $time);
always @ (posedge error[1])
if( error[1] == 1'b1 )
$display("=== ERROR FLAG 1 @ %T", $time);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4bb (
VPWR,
VGND,
X ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nor0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> const size_t max_vertices = 1 << 16; int degree[max_vertices], xor_sum[max_vertices]; std::queue<int> queue; std::vector<std::pair<int, int>> result; int main() { int vcount = 0; std::cin >> vcount; for (int i = 0; i < vcount; i++) { std::cin >> degree[i] >> xor_sum[i]; if (degree[i] == 1) { queue.push(i); } } while (!queue.empty()) { int cur = queue.front(); queue.pop(); int next = xor_sum[cur]; if (degree[cur] > 0 && degree[next] > 0) { result.push_back(std::make_pair(cur, next)); degree[next]--; degree[cur]--; xor_sum[next] ^= cur; } if (degree[next] == 1) { queue.push(next); } } std::cout << result.size() << std::endl; for (int i = 0; i < result.size(); i++) { std::cout << result[i].first << << result[i].second << std::endl; } return 0; } |
#include <bits/stdc++.h> const int N = 65550; int ru[N], sum[N]; int n; int s[N], t[N], cc = 0; int main() { int i; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d%d , &ru[i], &sum[i]); for (i = 0; i < n; i++) { int now = i; while (ru[now] == 1) { cc++; s[cc] = now; t[cc] = sum[now]; ru[now]--; ru[sum[now]]--; sum[sum[now]] ^= now; now = sum[now]; } } printf( %d n , cc); for (i = 1; i <= cc; i++) printf( %d %d n , s[i], t[i]); return 0; } |
// ctorng 2/22/2017
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// Ports for tsmc16_2rw (sram_2p_uhde)
//
// CLK // in
// AA // in
// CENA // active low
// QA // out
//
// AB // in
// DB // in
// CENB // active low
// WENB // active low
//
// STOVAB// 1'b0 (is really a don't care, but we drive it)
// STOV // 1'b0 default
// EMA // 3'd2 default
// EMAW // 2'd1 default
// EMAS // 1'b0 default
// EMAP // 1'b0 default
// RET1N // 1'b1, active low, 1'b1 is disabled (retention mode)
//
`define bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1r1w_lg``lgEls``_w``bits``_bit mem ( \
.CLK (clk_i) \
,.AA (r_addr_i) \
,.CENA (~r_v_i) \
,.QA (r_data_o) \
\
,.AB (w_addr_i) \
,.DB (w_data_i) \
,.CENB (~w_v_i) \
,.WENB (~w_mask_i) \
\
,.STOV (1'd0 ) \
,.STOVAB(1'd0 ) \
,.EMA (3'd3 ) \
,.EMAW (2'd1 ) \
,.EMAS (1'b0 ) \
,.EMAP (1'b0 ) \
,.RET1N (1'b1 ) \
); \
end
`define bsg_mem_1r1w_sync_mask_write_bit_macro_rf(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1r1w_rf_lg``lgEls``_w``bits``_bit mem ( \
.CLKA (clk_i) \
,.AA (r_addr_i) \
,.CENA (~r_v_i) \
,.QA (r_data_o) \
\
,.CLKB (clk_i) \
,.AB (w_addr_i) \
,.DB (w_data_i) \
,.CENB (~w_v_i) \
,.WENB (~w_mask_i) \
\
,.STOV (1'd0 ) \
,.EMAA (3'd3 ) \
,.EMAB (3'd3 ) \
,.EMASA (1'd1 ) \
,.RET1N (1'b1 ) \
); \
end
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
)
( input clk_i
, input reset_i
, input w_v_i
, input [width_p-1:0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_mask_write_bit_macro(64,88,6) else
`bsg_mem_1r1w_sync_mask_write_bit_macro(256,128,8) else
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
begin
//$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x) old_val %x",reset_i, w_addr_i,w_data_i,w_mask_i,mem[r_addr_i]);
$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[100 + 10][100 + 10]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> a[i][j]; } } int sum = 0; for (int i = 0; i < n; i++) { sum += a[i][i]; } for (int i = n - 1; i >= 0; i--) { sum += a[i][n - i - 1]; } for (int i = 0; i < n; i++) { sum += a[i][n / 2]; } for (int i = 0; i < n; i++) { sum += a[n / 2][i]; } sum -= a[n / 2][n / 2] * 3; cout << sum; } |
// ICNBC functions
// Copyright (c) 2014 Dominic Spill, Tariq Bashir
// This file is part of Unambiguous Encapsulation
// License: GPL v2
//
`timescale 1ns/1ps
module tb_icnbc;
parameter N = 8;
parameter MIN_LD = 2;
parameter MEM_DEPTH=256;
reg clk;
reg rst;
reg [N-1:0] n;
reg start;
reg [N-1:0] min_ld;
wire [3:0] codes [N-1:0];
initial
begin
clk <= 1'b0;
rst = 1'b1;
end
always
#5 clk = ~clk;
initial
begin
repeat(10) @(negedge clk);
rst = 1'b0; //disable reset
@(negedge clk);
start = 1;
n = N;
min_ld = MIN_LD;
end
/* icnbc AUTO_TEMPLATE
(
);
*/
icnbc #(.N(N),.depth(MEM_DEPTH),.width(N)) LCBBC_INST
(/*AUTOINST*/
// Outputs
.codes (codes[3:0][N-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.n (n[N-1:0]),
.min_ld (min_ld[N-1:0]),
.start (start));
/* -----\/----- EXCLUDED -----\/-----
initial
begin
#15000;
$finish;
end
-----/\----- EXCLUDED -----/\----- */
initial
begin
$monitor("codeword = %b\t ",codes);
end
endmodule // tb_icnbc
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int gi() { int x = 0, o = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } int n, m, a[N], mx[N], mn[N]; map<pair<int, int>, int> f; map<int, int> lst; vector<pair<int, int> > key; set<pair<int, int> > ban; void work(int *mx) { f.clear(); lst.clear(); key.clear(); ban.clear(); for (int i = 1; i <= n; i++) key.push_back(make_pair(0, i)); for (int i = 1; i <= m; i++) if (a[i] > 1) { key.push_back(make_pair(i, a[i] - 1)); ban.insert(make_pair(i, a[i])); } for (int i = 1; i <= m + 1; i++) { key.push_back(make_pair(i, n)); ban.insert(make_pair(i, n + 1)); } sort(key.begin(), key.end()); reverse(key.begin(), key.end()); for (auto t : key) { if (ban.find(make_pair(t.first, t.second + 1)) != ban.end()) lst[t.first - t.second - 1] = t.first; if (ban.find(make_pair(t.first, t.second)) != ban.end()) continue; if (lst.count(t.first - t.second)) { int x = lst[t.first - t.second], y = x - t.first + t.second; if (ban.find(make_pair(x, y - 1)) != ban.end()) f[t] = f[make_pair(x, y - 2)]; else f[t] = f[make_pair(x, y - 1)]; } else f[t] = t.second + m + 1 - t.first; } for (int i = 1; i <= n; i++) mx[i] = f[make_pair(0, i)]; } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) a[i] = gi(); if (n == 1) return cout << 0, 0; work(mx); for (int i = 1; i <= m; i++) a[i] = n - a[i] + 1; work(mn); reverse(mn + 1, mn + n + 1); for (int i = 1; i <= n; i++) mn[i] = n - mn[i] + 1; long long ans = 0; for (int i = 1; i <= n; i++) ans += mx[i] - mn[i] + 1; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void pv(T a, T b) { for (T i = a; i != b; ++i) cerr << *i << ; cerr << endl; } int main() { for (long long N, M; cin >> N >> M;) { for (int i = 0; i < (int)(N); ++i) { long long S, F, T; cin >> S >> F >> T; if (S == F) { cout << T << endl; continue; } long long loop = (M - 1) * 2; long long ans = 0; if (S < F) { ans = T / loop * loop; T = T % loop; if (S - 1 < T) ans += (M - 1) * 2; ans += F - 1; } else { ans = T / loop * loop; T = T % loop; if (M - S + M - 1 < T) ans += (M - 1) * 2; ans += M - 1; ans += (M - F); } cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int d[1005], s[1005], sufmax[1005], mxpos[1005], pred[1005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; ++n; for (int i = 1; i < n; ++i) cin >> d[i]; for (int i = 1; i < n; ++i) cin >> s[i]; for (int i = n - 1; i >= 1; --i) { if (s[i] > sufmax[i + 1]) { mxpos[i] = i; sufmax[i] = s[i]; } else { mxpos[i] = mxpos[i + 1]; sufmax[i] = sufmax[i + 1]; } } for (int i = 1; i < n; ++i) pred[i] = pred[i - 1] + d[i]; int tott = 0, oil = s[1]; for (int i = 1; i < n;) { int j = i; do { oil -= d[j]; ++j; while (oil < 0) tott += k, oil += s[i]; oil += s[j]; } while (s[j] < s[i] && j < n); i = j; } cout << tott + pred[n - 1] << endl; } |
//altera message_off 10230
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double x, y; cin >> x >> y; double ans = (x * x + y * y) / (x * 2); ans -= x; printf( %.12lf , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int solveA(vector<int> a, vector<int> b) { int n = (int)((a).size()); vector<int> m(n); for (int i = (0); i <= ((n)-1); i++) m[b[i]] = i; for (int i = (0); i <= ((n)-1); i++) a[i] = m[a[i]]; b[0] = a[0]; for (int i = (1); i <= ((n - 1)); i++) b[i] = max(b[i - 1], a[i]); int res = 0; for (int i = (0); i <= ((n)-1); i++) res += (a[i] != b[i]); return res; } int solveB(vector<int> a, vector<int> b) { int res = 0, n = (int)((a).size()); vector<int> used(n + 1, false); while (a.size() || b.size()) { if (a.size() && b.size() && a.back() == b.back()) b.pop_back(), a.pop_back(); else if (b.size() && used[b.back()]) b.pop_back(); else if (a.size() && a.back() != b.back()) { used[a.back()] = true; a.pop_back(); res++; } } return res; } int solve(vector<int> a, vector<int> b) { int n = (int)((a).size()); vector<int> m(n); for (int i = (0); i <= ((n)-1); i++) m[b[i]] = i; for (int i = (0); i <= ((n)-1); i++) a[i] = m[a[i]]; for (int i = (0); i <= ((n - 1) - 1); i++) if (a[i] > a[i + 1]) { return n - 1 - i; } return 0; } int main() { int n = 100; scanf( %d , &n); vector<int> a(n), b(n); for (int i = (0); i <= ((n)-1); i++) scanf( %d , &a[i]), a[i]--; for (int i = (0); i <= ((n)-1); i++) scanf( %d , &b[i]), b[i]--; cout << solve(a, b) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_LP_V
`define SKY130_FD_SC_LP__NAND4_LP_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_lp (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_lp (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_LP_V
|
#include <bits/stdc++.h> using namespace std; struct Root { int p, c; long long e, x; vector<int> v; Root(int p, long long e) : p(p), e(e) {} }; const int MAXN = 200200; bool oncirc[MAXN]; vector<pair<int, long long> > e[MAXN]; vector<Root> circ; long long ans[MAXN]; bool mark[MAXN]; int dfs(int v, int p) { if (mark[v]) { return v; } else { mark[v] = true; } for (vector<pair<int, long long> >::const_iterator it = e[v].begin(); it != e[v].end(); ++it) { int w = it->first; if (w == p) { continue; } int t = dfs(w, v); if (t != -1) { circ.push_back(Root(w, it->second)); return v == t ? -1 : t; } } return -1; } int findcirc(int n) { int m; dfs(0, -1); m = circ.size(); for (int i = 0; i < m; ++i) { oncirc[circ[i].p] = true; } return m; } Root* root; long long dd[MAXN], cc[MAXN], ss[MAXN], xx[MAXN]; void gao1(int v, int p) { root->v.push_back(v); cc[v] = 1; ss[v] = 0; for (vector<pair<int, long long> >::const_iterator it = e[v].begin(); it != e[v].end(); ++it) { int w = it->first; if (w == p || oncirc[w]) { continue; } dd[w] = dd[v] + it->second; gao1(w, v); cc[v] += cc[w]; ss[v] += ss[w] + cc[w] * it->second; } } void gao2(int v, int p, int n) { for (vector<pair<int, long long> >::const_iterator it = e[v].begin(); it != e[v].end(); ++it) { int w = it->first; if (w == p || oncirc[w]) { continue; } xx[w] = xx[v] + (ss[v] - (ss[w] + cc[w] * it->second)) + (n - cc[w]) * it->second; gao2(w, v, n); } } void calctree(Root& r) { root = &r; dd[r.p] = 0; gao1(r.p, -1); xx[r.p] = 0; r.c = cc[r.p]; gao2(r.p, -1, r.c); for (vector<int>::const_iterator it = r.v.begin(); it != r.v.end(); ++it) { ans[*it] = xx[*it] + ss[*it]; } r.x = ans[r.p]; } long long ee[MAXN + MAXN]; void calccirc(int n, int m) { long long circlen = 0; long long total = 0; long long cursum = 0; int curcnt = 0; int q = 0; for (int i = 0; i < m; ++i) { circlen += circ[i].e; total += circ[i].x; ee[i + 1 + m] = ee[i + 1] = circ[i].e; } ee[0] = 0; partial_sum(ee, ee + m + m + 1, ee); while (2 * (ee[q] - ee[0]) <= circlen) { cursum += (ee[q] - ee[0]) * circ[q % m].c; curcnt += circ[q % m].c; ++q; } for (int i = q; i < m; ++i) { cursum += (circlen - (ee[i] - ee[0])) * circ[i % m].c; } for (int i = 0; i < m; ++i) { while (2 * (ee[q] - ee[i]) <= circlen) { cursum -= (circlen - 2 * (ee[q] - ee[i])) * circ[q % m].c; curcnt += circ[q % m].c; ++q; } for (vector<int>::const_iterator it = circ[i].v.begin(); it != circ[i].v.end(); ++it) { ans[*it] += cursum + total - circ[i].x + dd[*it] * (n - circ[i].c); } curcnt -= circ[i].c; cursum += (n - curcnt) * circ[i].e; cursum -= curcnt * circ[i].e; } } int main() { int n, m, a, b, c; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d%d , &a, &b, &c); --a; --b; e[a].push_back(make_pair(b, c)); e[b].push_back(make_pair(a, c)); } m = findcirc(n); for (int i = 0; i < m; ++i) { calctree(circ[i]); } calccirc(n, m); for (int i = 0; i < n; ++i) { printf( %I64d%c , ans[i], i == n - 1 ? n : ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long i, j, k, l, n, m, s, sum, K; double an; const long long N = 1020; long long f[N][N], lu[N][N], ld[N][N], ru[N][N], rd[N][N]; long long Lu[N][N], Ld[N][N], Ru[N][N], Rd[N][N]; int hang[N], lie[N]; char a[N][N]; void work(long long x, long long y) { long long s = 0; long long sum = 0; for (long long i = 1; i < y; i++) { sum += s; f[x][i] += sum; s++; } sum += 3 * s; for (long long i = y + 1; i <= m; i++) { sum += s; f[x][i] += sum; s++; } s = 0; sum = 0; for (long long i = m; i > y; i--) { sum += s; f[x][i] += sum; s++; } sum += 3 * s; for (long long i = y - 1; i >= 1; i--) { sum += s; f[x][i] += sum; s++; } s = 0; sum = 0; for (long long i = 1; i < x; i++) { sum += s; f[i][y] += sum; s++; } sum += 3 * s; for (long long i = x + 1; i <= n; i++) { sum += s; f[i][y] += sum; s++; } s = 0; sum = 0; for (long long i = n; i > x; i--) { sum += s; f[i][y] += sum; s++; } sum += 3 * s; for (long long i = x - 1; i >= 1; i--) { sum += s; f[i][y] += sum; s++; } } int main() { scanf( %I64d%I64d , &n, &m); for (long long i = 1; i <= n; i++) { scanf( %s , a[i] + 1); for (long long j = 1; j <= m; j++) if (a[i][j] == X ) { hang[i] = j; lie[j] = i; break; } } for (long long i = 1; i <= n; i++) { long long s = 0; long long sum = 0; for (long long j = 1; j <= m; j++) { sum += s; lu[i][j] = lu[i - 1][j] + sum + Lu[i - 1][j] * 1; if (a[i][j] != X ) s++; Lu[i][j] = Lu[i - 1][j] + s; } } for (long long i = 1; i <= n; i++) { long long s = 0; long long sum = 0; for (long long j = m; j >= 1; j--) { sum += s; ru[i][j] = ru[i - 1][j] + sum + Ru[i - 1][j] * 1; if (a[i][j] != X ) s++; Ru[i][j] = Ru[i - 1][j] + s; } } for (long long i = n; i >= 1; i--) { long long s = 0; long long sum = 0; for (long long j = 1; j <= m; j++) { sum += s; ld[i][j] = ld[i + 1][j] + sum + Ld[i + 1][j] * 1; if (a[i][j] != X ) s++; Ld[i][j] = Ld[i + 1][j] + s; } } for (long long i = n; i >= 1; i--) { long long s = 0; long long sum = 0; for (long long j = m; j >= 1; j--) { sum += s; rd[i][j] = rd[i + 1][j] + sum + Rd[i + 1][j] * 1; if (a[i][j] != X ) s++; Rd[i][j] = Rd[i + 1][j] + s; } } long long sx = 0; for (long long i = 1; i <= n; i++) { bool ok = false; for (long long j = 1; j <= m; j++) if (a[i][j] == X ) { sx++; work(i, j); ok = true; break; } if (!ok) work(i, 0); } for (long long j = 1; j <= m; j++) { bool ok = false; for (long long i = 1; i <= n; i++) if (a[i][j] == X ) { ok = true; break; } if (!ok) work(0, j); } for (long long i = 1; i <= n; i++) for (long long j = 1; j <= m; j++) if (a[i][j] != X ) { an += lu[i - 1][j - 1] + ru[i - 1][j + 1] + ld[i + 1][j - 1] + rd[i + 1][j + 1]; an += (Lu[i - 1][j - 1] + Ru[i - 1][j + 1] + Ld[i + 1][j - 1] + Rd[i + 1][j + 1]) * 2; an += f[i][j]; } for (i = 1; i < n; i++) { int j = i; while (hang[j] && hang[j + 1] && (hang[j + 1] > hang[j])) j++; for (int x = i; x < j; x++) for (int y = x + 1; y <= j; y++) { if (hang[x] < hang[y]) an += 4 * (hang[x] - 1) * (m - hang[y]); else an += 4 * (hang[y] - 1) * (m - hang[x]); } i = j; } for (i = 1; i < n; i++) { int j = i; while (hang[j] && hang[j + 1] && (hang[j + 1] < hang[j])) j++; for (int x = i; x < j; x++) for (int y = x + 1; y <= j; y++) { if (hang[x] < hang[y]) an += 4 * (hang[x] - 1) * (m - hang[y]); else an += 4 * (hang[y] - 1) * (m - hang[x]); } i = j; } for (i = 1; i < m; i++) { int j = i; while (lie[j] && lie[j + 1] && (lie[j + 1] > lie[j])) j++; for (int x = i; x < j; x++) for (int y = x + 1; y <= j; y++) { if (lie[x] < lie[y]) an += 4 * (lie[x] - 1) * (n - lie[y]); else an += 4 * (lie[y] - 1) * (n - lie[x]); } i = j; } for (i = 1; i < m; i++) { int j = i; while (lie[j] && lie[j + 1] && (lie[j + 1] < lie[j])) j++; for (int x = i; x < j; x++) for (int y = x + 1; y <= j; y++) { if (lie[x] < lie[y]) an += 4 * (lie[x] - 1) * (n - lie[y]); else an += 4 * (lie[y] - 1) * (n - lie[x]); } i = j; } an = an / ((n * m - sx) * (n * m - sx)); printf( %.8lf , an); return 0; } |
module IMUL2
(input wire [15:0] iSourceData0, iSourceData1,
output reg [31:0] oResult
);
wire [31:0] oMux1, oMux2, oMux3, oMux4, oMux5, oMux6,oMux7,oMux8;
wire [31:0]cero, uno, dos, tres;
assign cero = 0;
assign uno = iSourceData0;
assign dos = iSourceData0<<1;
assign tres = (iSourceData0<<1) + iSourceData0;
MUX4X1 Mux1(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[1], iSourceData1[0]}),
.oOutput(oMux1)
);
MUX4X1 Mux2(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[3], iSourceData1[2]}),
.oOutput(oMux2)
);
MUX4X1 Mux3(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[5], iSourceData1[4]}),
.oOutput(oMux3)
);
MUX4X1 Mux4(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[7], iSourceData1[6]}),
.oOutput(oMux4)
);
MUX4X1 Mux5(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[9], iSourceData1[8]}),
.oOutput(oMux5)
);
MUX4X1 Mux6(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[11], iSourceData1[10]}),
.oOutput(oMux6)
);
MUX4X1 Mux7(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[13], iSourceData1[12]}),
.oOutput(oMux7)
);
MUX4X1 Mux8(
.iInput0(cero),
.iInput1(uno),
.iInput2(dos),
.iInput3(tres),
.iSelect({iSourceData1[15], iSourceData1[14]}),
.oOutput(oMux8)
);
always @(*) begin
oResult = oMux1 +(oMux2<<2)+ (oMux3<<4) + (oMux4<<6) + (oMux5<<8) + (oMux6<<10) + (oMux7<<12) +(oMux8<<14);
end
endmodule |
#include <bits/stdc++.h> #pragma GCC optimize -O3 using ll = long long; using ull = unsigned long long; using ld = long double; using namespace std; const int MX = 7007; ll f[MX]; bool better(ll x, ll y) { return ((x ^ y) & x) != 0; } ll x[MX], y[MX]; bool ok[MX]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n; cin >> n; vector<pair<ll, ll>> a; map<ll, int> cnt; map<ll, ll> sum; for (int i = 0; i < n; i++) { cin >> x[i]; } for (int i = 0; i < n; i++) { cin >> y[i]; } for (int i = 0; i < n; i++) { a.emplace_back(x[i], y[i]); cnt[x[i]]++; sum[x[i]] += y[i]; } sort(a.begin(), a.end()); for (int i = n - 1; i >= 0; i--) { if (cnt[a[i].first] >= 2) { ok[i] = true; } for (int j = i + 1; j < n; j++) { if (!better(a[i].first, a[j].first) && ok[j]) { ok[i] = true; } } } ll ans = 0; for (int i = 0; i < n; i++) { if (ok[i]) { ans += a[i].second; } } cout << ans << n ; return 0; } |
/*
File: debouncer.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module debouncer (/*AUTOARG*/
// Outputs
clean_out,
// Inputs
clk, noisy_in
);
parameter N = 20; //debouncer counter width
input clk; //system clock
input noisy_in; //bouncy input (convention says it goes low when button is pressed)
output clean_out; //clean output (positive polarity)
wire expired;
wire sync_in;
reg [N-1:0] counter;
wire filtering;
synchronizer #(1) synchronizer(.out (sync_in),
.in (noisy_in),
.clk (clk),
.reset (1'b0));
//Counter that resets when sync_in is low
always @ (posedge clk)
if(sync_in)
counter[N-1:0]={(N){1'b1}};
else if(filtering)
counter[N-1:0]=counter[N-1:0]-1'b1;
assign filtering =|counter[N-1:0];
assign clean_out = filtering | sync_in;
endmodule // debouncer
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 1; long long gcd(long long a, long long b) { long long r; while (b > 0) { r = a % b; a = b; b = r; } return a; } int main() { long long n, k, a, b, maxkq = 0, minkq = 1e18, l, kq, g, tmp; cin >> n >> k >> a >> b; tmp = n * k; for (int i = 0; i < n; i++) { l = (k * i + a - b) % tmp; if (l < 0) l += n * k; g = gcd(l, n * k); kq = (n * k) / g; if (kq < minkq) minkq = kq; if (kq > maxkq) maxkq = kq; l = (k * i + a + b) % tmp; g = gcd(l, n * k); kq = (n * k) / g; if (kq < minkq) minkq = kq; if (kq > maxkq) maxkq = kq; l = (k * i - a + b) % tmp; if (l < 0) l += n * k; g = gcd(l, n * k); kq = (n * k) / g; if (kq < minkq) minkq = kq; if (kq > maxkq) maxkq = kq; l = (k * i - a - b) % tmp; if (l < 0) l += n * k; g = gcd(l, n * k); kq = (n * k) / g; if (kq < minkq) minkq = kq; if (kq > maxkq) maxkq = kq; } cout << minkq << << maxkq; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.06.2017 19:13:32
// Design Name:
// Module Name: Prueba_codigos_teclado
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Prueba_codigos_teclado(
input CLK100MHZ,
input CPU_RESETN,
input PS2_CLK,
input PS2_DATA,
output [7:0] LED,
output [7:0] AN,
output CA,CB,CC,CD,CE,CF,CG,DP
);
wire reset;
wire reloj_lento;
wire [7:0] data;
wire [4:0] val;
wire [2:0] control;
assign reset=~CPU_RESETN;
teclado tec(
.ps2_data(data),
.val(val),
.control(control),
.leds (LED[7:0])
);
// clk,rst,kd,kc,new_data,data_type,kbs_tot,parity_error
kbd_ms driver_tec(
.clk(CLK100MHZ),
.rst(reset),
.kd(PS2_DATA),
.kc(PS2_CLK),
.new_data(data),
.data_type(),
.kbs_tot(),
.parity_error()
);
clock_divider clock_div(
.clk(CLK100MHZ),
.rst(reset),
.clk_div(reloj_lento)
);
display dis(
.clk_display(reloj_lento),
.num({24'b0,data}),
.puntos(),
.anodos(AN[7:0]),
.segmentos({CA,CB,CC,CD,CE,CF,CG,DP})
);
endmodule
|
`include "bch_defs.vh"
module xilinx_error_one #(
parameter T = 2,
parameter DATA_BITS = 5,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk_in,
input in,
output reg out = 0
);
`include "bch_params.vh"
localparam TCQ = 1;
localparam P = bch_params(DATA_BITS, T);
localparam M = `BCH_M(P);
localparam IN = M + 1;
localparam OUT = 1 + BITS;
wire clk;
(* KEEP = "TRUE" *)
reg [IN-1:0] all_in;
(* KEEP = "TRUE" *)
reg [OUT-1:0] all_out;
wire start; /* Latch inputs, start calculating */
wire [2*M-1:0] sigma;
wire first; /* First valid output data */
wire [BITS-1:0] err;
(* KEEP = "TRUE" *)
reg in1 = 0, in2 = 0, out1 = 0;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
assign start = all_in[0];
assign sigma = {all_in[M:1], {M-1{1'b0}}, 1'b1};
always @(posedge clk) begin
in1 <= #TCQ in;
in2 <= #TCQ in1;
out <= #TCQ out1;
out1 <= #TCQ all_out[0];
all_in <= #TCQ (all_in << 1) | in2;
all_out <= #TCQ (all_out >> 1) ^ {first, err};
end
bch_error_one #(P, BITS, PIPELINE_STAGES) u_error_one(
.clk(clk),
.start(start),
.sigma(sigma),
.first(first),
.err(err)
);
endmodule
|
module probador(clk, rw, addr, data_in, data_out, ack, req, reset);
//Salidas y entradas
parameter data_witdh = 32;
parameter addr_witdh = 5;
parameter reg_witdh = 28;
output clk;
output rw;
reg rw;
output req;
reg req;
input ack;
wire ack;
output [addr_witdh-1: 0] addr;
reg addr;
output [data_witdh-1: 0] data_in;
reg data_in;
input [data_witdh-1: 0] data_out;
wire data_out;
output reset;
reg reset = 1;
//Valores iniciales para las entradas
//Cambio en las entradas según temporizador (en segundos)
initial begin
//Prueba ascendente
$display("Inicia prueba");
#1 reset = 0;
addr = 5'b00000;
req = 1'b1;
rw = 1'b0;
data_in = 32'h00000001;
#6 rw = 1'b1;
#1 addr = 5'b00100;
req = 1'b1;
rw = 1'b0;
data_in = 32'h01010001;
#6 rw = 1'b1;
#1 req =1'b0;
#1 addr = 5'b10110;
req = 1'b1;
rw = 1'b0;
data_in = 32'h11011010;
#6 rw = 1'b1;
#11 $finish;
end
//Pulso de reloj cada segundo
reg clk = 0;
always #1 clk = !clk;
//contador c1 (Q, RCO, CLK, ENB, MODO, D, reset);
//Vista en pantalla
initial
$monitor("ack: %b", ack);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int i; int main() { string s; cin >> s; int k; i = 0; while (s[i] == 0 ) { i++; } int f = 0, v = 0; bool b = false; while (i != s.size()) { if (s[i] == 4 ) f++; else if (s[i] == 7 ) v++; i++; } if (b) cout << -1; else { if (f != 0 && f == v) cout << 4; else if (f > v) cout << 4; else if (v > f) cout << 7; else cout << -1; } } |
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / 7SERIES PHASER REF
// /__/ /\ Filename : PHASER_REF.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 23APR2010 Initial UNI/UNP/SIM from yml
// 02JUL2010 add functionality
// 29SEP2010 update functionality based on rtl
// add width checks
// 28OCT2010 CR580289 ref_clock_input_freq_MHz_min/max < vs <=
// 09NOV2010 CR581863 blocking statements, clock counts to lock.
// 11NOV2010 CR582599 warning in place of LOCK
// 01DEC2010 clean up display of real numbers
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP make default
// 16APR2012 655365 else missing from delay_LOCKED always block
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_REF (
LOCKED,
CLKIN,
PWRDWN,
RST
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam INCLK_DELAY = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam INCLK_DELAY = 0;
localparam out_delay = 10;
`endif
localparam MODULE_NAME = "PHASER_REF";
localparam real REF_CLK_JITTER_MAX = 100.000;
output LOCKED;
input CLKIN;
input PWRDWN;
input RST;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire delay_CLKIN;
wire delay_PWRDWN;
wire delay_RST;
wire delay_GSR;
reg delay_LOCKED = 1'b1;
real ref_clock_input_period = 11.0;
real ref_clock_input_freq_MHz = 1.68;
real time_last_rising_edge = 1.0;
real last_ref_clock_input_period = 13.0;
real last_ref_clock_input_freq_MHz = 1.69;
integer same_period_count = 0;
integer different_period_count = 0;
integer same_period_count_last = 0;
integer count_clks = 0;
real ref_clock_input_freq_MHz_min = 400.000; // valid min freq in MHz
real ref_clock_input_freq_MHz_max = 1066.000; // valid max freq in MHz
reg IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
assign #(out_delay) LOCKED = delay_LOCKED;
assign #(INCLK_DELAY) delay_CLKIN = CLKIN;
assign #(in_delay) delay_PWRDWN = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign #(in_delay) delay_RST = RST ^ IS_RST_INVERTED_BIN;
assign delay_GSR = GSR;
always @(posedge delay_CLKIN)
begin
last_ref_clock_input_period <= ref_clock_input_period;
last_ref_clock_input_freq_MHz <= ref_clock_input_freq_MHz;
same_period_count_last <= same_period_count;
ref_clock_input_period <= $time - time_last_rising_edge;
ref_clock_input_freq_MHz <= 1e6/($time - time_last_rising_edge);
time_last_rising_edge <= $time/1.0;
if ( (delay_RST==0) && (delay_PWRDWN ==0) &&
(ref_clock_input_period - last_ref_clock_input_period <= REF_CLK_JITTER_MAX) &&
(last_ref_clock_input_period - ref_clock_input_period <= REF_CLK_JITTER_MAX) )
begin
if (same_period_count < 6) same_period_count <= same_period_count + 1;
if ( same_period_count >= 3 && same_period_count != same_period_count_last && different_period_count != 0)
begin
different_period_count <= 0; //reset different_period_count
end
end
else // detecting different clock-preiod
begin
different_period_count = different_period_count + 1;
if ( different_period_count >= 1 && same_period_count != 0 )
begin
same_period_count <= 0 ; //reset same_period_count
end
end
end
always @(posedge delay_CLKIN or posedge delay_RST or posedge delay_PWRDWN) begin
if ( delay_RST||delay_PWRDWN)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ((same_period_count >= 1) && (count_clks < 6))
begin
count_clks <= count_clks + 1;
end
else if (different_period_count >= 1)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ( (count_clks >= 5) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 >= ref_clock_input_freq_MHz_min ) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 <= ref_clock_input_freq_MHz_max ) )
begin
delay_LOCKED <= 1'b1;
end
end
always @(posedge delay_CLKIN)
if ( (count_clks == 5) &&
( ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 < ref_clock_input_freq_MHz_min) ||
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 > ref_clock_input_freq_MHz_max) ) ) begin
$display("Warning: Invalid average CLKIN frequency detected = %4.3f MHz", (ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000);
$display(" on %s instance %m at time %t ps.", MODULE_NAME, $time);
$display(" The valid CLKIN frequency range is:");
$display(" Minimum = %4.3f MHz", ref_clock_input_freq_MHz_min );
$display(" Maximum = %4.3f MHz", ref_clock_input_freq_MHz_max );
end
`ifdef XIL_TIMING
specify
$period (negedge CLKIN, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_REF
`endcelldefine
|
//======================================================================
//
// sha512_h_constants.v
// ---------------------
// The H initial constants for the different modes in SHA-512.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha512_h_constants(
input wire [1 : 0] mode,
output wire [63 : 0] H0,
output wire [63 : 0] H1,
output wire [63 : 0] H2,
output wire [63 : 0] H3,
output wire [63 : 0] H4,
output wire [63 : 0] H5,
output wire [63 : 0] H6,
output wire [63 : 0] H7
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] tmp_H0;
reg [63 : 0] tmp_H1;
reg [63 : 0] tmp_H2;
reg [63 : 0] tmp_H3;
reg [63 : 0] tmp_H4;
reg [63 : 0] tmp_H5;
reg [63 : 0] tmp_H6;
reg [63 : 0] tmp_H7;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign H0 = tmp_H0;
assign H1 = tmp_H1;
assign H2 = tmp_H2;
assign H3 = tmp_H3;
assign H4 = tmp_H4;
assign H5 = tmp_H5;
assign H6 = tmp_H6;
assign H7 = tmp_H7;
//----------------------------------------------------------------
// mode_mux
//
// Based on the given mode, the correct H constants are selected.
//----------------------------------------------------------------
always @*
begin : mode_mux
case(mode)
0:
begin
// SHA-512/224
tmp_H0 = 64'h8c3d37c819544da2;
tmp_H1 = 64'h73e1996689dcd4d6;
tmp_H2 = 64'h1dfab7ae32ff9c82;
tmp_H3 = 64'h679dd514582f9fcf;
tmp_H4 = 64'h0f6d2b697bd44da8;
tmp_H5 = 64'h77e36f7304c48942;
tmp_H6 = 64'h3f9d85a86a1d36c8;
tmp_H7 = 64'h1112e6ad91d692a1;
end
1:
begin
// SHA-512/256
tmp_H0 = 64'h22312194fc2bf72c;
tmp_H1 = 64'h9f555fa3c84c64c2;
tmp_H2 = 64'h2393b86b6f53b151;
tmp_H3 = 64'h963877195940eabd;
tmp_H4 = 64'h96283ee2a88effe3;
tmp_H5 = 64'hbe5e1e2553863992;
tmp_H6 = 64'h2b0199fc2c85b8aa;
tmp_H7 = 64'h0eb72ddc81c52ca2;
end
2:
begin
// SHA-384
tmp_H0 = 64'hcbbb9d5dc1059ed8;
tmp_H1 = 64'h629a292a367cd507;
tmp_H2 = 64'h9159015a3070dd17;
tmp_H3 = 64'h152fecd8f70e5939;
tmp_H4 = 64'h67332667ffc00b31;
tmp_H5 = 64'h8eb44a8768581511;
tmp_H6 = 64'hdb0c2e0d64f98fa7;
tmp_H7 = 64'h47b5481dbefa4fa4;
end
3:
begin
// SHA-512
tmp_H0 = 64'h6a09e667f3bcc908;
tmp_H1 = 64'hbb67ae8584caa73b;
tmp_H2 = 64'h3c6ef372fe94f82b;
tmp_H3 = 64'ha54ff53a5f1d36f1;
tmp_H4 = 64'h510e527fade682d1;
tmp_H5 = 64'h9b05688c2b3e6c1f;
tmp_H6 = 64'h1f83d9abfb41bd6b;
tmp_H7 = 64'h5be0cd19137e2179;
end
endcase // case (addr)
end // block: mode_mux
endmodule // sha512_h_constants
//======================================================================
// sha512_h_constants.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; struct node { int point, w; } p[30][30]; int n, m; int s[30][30], w[30][30], Min[30], f[3000000]; int Get() { char c = getchar(); while (!isalpha(c)) c = getchar(); return c; } void init(int x, int y) { int t1 = 0, t2 = 0, mx = 0; for (int i = 1; i <= n; i++) if (s[i][y] == s[x][y]) { t1 |= 1 << (i - 1); t2 += w[i][y]; mx = max(mx, w[i][y]); } p[x][y] = (node){t1, t2 - mx}; } int Getlow(int x) { int ss[200]; int num = 0; if (x == 0) return 1; while (x) { ss[++num] = x % 2; x /= 2; } ss[++num] = 0; for (int i = 1; i <= num; i++) if (ss[i] == 0) return i; } int main() { for (int i = 1; i <= 29; i++) Min[i] = 19240012; for (int i = 1; i <= 3000000 - 1; i++) f[i] = 30000000; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) s[i][j] = Get(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> w[i][j]; Min[i] = min(Min[i], w[i][j]); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) init(i, j); f[0] = 0; for (int i = 0; i < (1 << n); i++) { int p_ = Getlow(i); f[i | (1 << (p_ - 1))] = min(f[i | (1 << (p_ - 1))], f[i] + Min[p_]); for (int j = 1; j <= m; j++) f[i | p[p_][j].point] = min(f[i | p[p_][j].point], f[i] + p[p_][j].w); } cout << f[(1 << n) - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, sz1, sz2, val; int d1[200005], d2[200005], d[200005]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &val); if (val != 0) d1[sz1++] = val; } for (int i = 0; i < n; i++) { scanf( %d , &val); if (val != 0) d2[sz2++] = val; } for (int i = 0; i < sz1; i++) { int val = d1[i]; int id = (i + 1) % sz1; d[val] = d1[id]; } for (int i = 0; i < sz2; i++) { int val = d2[i]; int id = (i + 1) % sz2; if (d[val] == d2[id]) continue; printf( NO n ); return 0; } printf( YES n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> const double Pi = 3.14159265; const int N = 2e5 + 10; const unsigned long long base = 163; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-10; const double pi = acos(-1); using namespace std; long long inv[N]; long long dp[N]; int main() { long long p = mod; long long n; cin >> n; inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = (p - p / i) * inv[p % i] % p; long long ans = 1; for (int i = n; i >= 2; --i) { dp[i] = n / i * inv[n - n / i]; for (int j = i + i; j <= n; j += i) { dp[i] -= dp[j]; dp[i] %= mod; } dp[i] += mod; dp[i] %= mod; ans += dp[i]; ans %= mod; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } vector<int> t(n); for (int i = 0; i < n; i++) { cin >> t[i]; } a.push_back((int)1.01e9); t.push_back(0); ++n; vector<int> order(n); iota(order.begin(), order.end(), 0); sort(order.begin(), order.end(), [&](int i, int j) { return a[i] < a[j]; }); unsigned long long ans = 0; int last = 0; multiset<int> s; long long sum = 0; for (int i : order) { while (a[i] > last && !s.empty()) { ++last; auto it = prev(s.end()); sum -= *it; s.erase(it); ans += sum; } last = a[i]; s.insert(t[i]); sum += t[i]; } cout << ans << n ; return 0; } |
//#############################################################################
//# Purpose: SPI slave IO state-machine #
//# NOTE: only cpol=0, cpha=0 supported for now!! #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
`include "spi_regmap.vh"
module spi_slave_io #( parameter PW = 104 // packet width
)
(
//IO interface
input sclk, // slave clock
input mosi, // slave input
input ss, // slave select
output miso, // slave output
//Control
input spi_en, // spi enable
input cpol, // cpol
input cpha, // cpha
input lsbfirst, // lsbfirst
//register file interface
output spi_clk, // spi clock for regfile
output spi_write, // regfile write
output [5:0] spi_addr, // regfile addres
output [7:0] spi_wdata, // data for regfile
input [7:0] spi_rdata, // data for regfile
//core interface (synced to core clk)
input clk, // core clock
input nreset, // async active low reset
output reg access_out, // read or write core command
output [PW-1:0] packet_out, // packet
input wait_in // temporary pushback
);
//###############
//# LOCAL WIRES
//###############
reg [1:0] spi_state;
reg [7:0] bit_count;
reg [7:0] command_reg;
reg fetch_command;
wire [7:0] rx_data;
wire [63:0] tx_data;
wire rx_shift;
wire tx_load;
wire tx_wait;
wire ss_sync;
wire ss_pulse;
wire spi_fetch;
wire byte_done;
//#################################
//# MODES: TODO!
//#################################
//cpol=0,cpha=0
//(launch on negedge, capture on posedge)
assign shift = ~ss & spi_en;
assign rx_clk = sclk;
assign tx_clk = ~sclk;
assign tx_load = next_byte;
//#################################
//# STATE MACHINE
//#################################
`define SPI_IDLE_STATE 2'b00 // when ss is high
`define SPI_CMD_STATE 2'b01 // 8 cycles for command/addr
`define SPI_DATA_STATE 2'b10 // stay in datamode until done
//state machine
always @ (posedge sclk or posedge ss)
if(ss)
spi_state[1:0] <= `SPI_IDLE_STATE;
else
case (spi_state[1:0])
`SPI_IDLE_STATE : spi_state[1:0] <= `SPI_CMD_STATE;
`SPI_CMD_STATE : spi_state[1:0] <= next_byte ? `SPI_DATA_STATE : `SPI_CMD_STATE;
`SPI_DATA_STATE : spi_state[1:0] <= `SPI_DATA_STATE;
endcase // case (spi_state[1:0])
//bit counter
always @ (posedge sclk or posedge ss)
if(ss)
bit_count[7:0] <= 'b0;
else
bit_count[7:0] <= bit_count[7:0] + 1'b1;
assign next_byte = (spi_state[1:0]!=`SPI_IDLE_STATE) &
(bit_count[2:0]==3'b000);
assign byte_done = (spi_state[1:0]!=`SPI_IDLE_STATE) &
(bit_count[2:0]==3'b111);
// command/address register
// auto increment for every byte
always @ (posedge sclk or negedge nreset)
if(!nreset)
command_reg[7:0] <= 'b0;
else if((spi_state[1:0]==`SPI_CMD_STATE) & byte_done)
command_reg[7:0] <= spi_wdata[7:0];
else if(byte_done)
command_reg[7:0] <= {command_reg[7:6],
command_reg[5:0] + 1'b1};
//#################################
//# SPI RX SHIFT REGISTER
//#################################
assign shift = ~ss & spi_en;
oh_ser2par #(.PW(8),
.SW(1))
rx_ser2par (// Outputs
.dout (rx_data[7:0]),
// Inputs
.clk (rx_clk),
.din (mosi),
.lsbfirst (lsbfirst), //msb first
.shift (shift));
//####################################
//# REMOTE TRANSAXTION SHIFT REGISTER
//####################################
oh_ser2par #(.PW(PW),
.SW(1))
e_ser2par (// Outputs
.dout (packet_out[PW-1:0]),
// Inputs
.clk (rx_clk),
.din (mosi),
.lsbfirst (lsbfirst), //msb first
.shift (shift));//rx_shift
//#################################
//# TX SHIFT REGISTER
//#################################
oh_par2ser #(.PW(8),
.SW(1))
tx_par2ser (.dout (miso),
.access_out (),
.wait_out (tx_wait),
.clk (tx_clk), // shift out on positive edge
.nreset (~ss),
.din (spi_rdata[7:0]),
.shift (shift),
.lsbfirst (lsbfirst),
.load (tx_load),
.datasize (8'd7),
.fill (1'b0),
.wait_in (1'b0));
//#################################
//# REGISTER FILE INTERFACE
//#################################
assign spi_clk = rx_clk;
assign spi_addr[5:0] = command_reg[5:0];
assign spi_write = spi_en &
byte_done &
~ss &
(command_reg[7:6]==`SPI_WR) &
(spi_state[1:0]==`SPI_DATA_STATE);
assign spi_wdata[7:0] = lsbfirst ? {mosi, rx_data[7:1]}
: {rx_data[6:0], mosi};
//###################################
//# REMOTE FETCH LOGIC
//###################################
//sync the ss to free running clk
oh_dsync dsync (.dout (ss_sync),
.clk (clk),
.nreset(nreset),
.din (ss));
//create single cycle pulse
oh_rise2pulse r2p (.nreset (nreset),
.out (ss_pulse),
.clk (clk),
.in (ss_sync));
assign spi_fetch = ss_pulse & (command_reg[7:6]==`SPI_FETCH);
// pipeleining and holding pulse if there is wait
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <= 1'b0;
else if(~wait_in)
access_out <= spi_fetch;
endmodule // spi_slave_io
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; const int maxn = 345; int ai[maxn]; int bi[maxn]; bool used[maxn]; int m, r, t; void init() { for (int i = 1; i <= m; i++) { scanf( %d , &ai[i]); ai[i]++; } } vector<int> V; void play() { memset(bi, 0, sizeof(bi)); memset(used, 0, sizeof(used)); V.clear(); if (t < r) { printf( -1 n ); return; } long long sum = 0; for (int i = 1; i <= m; i++) { int st = 0; while (bi[ai[i]] < r) { for (int j = ai[i] - st; j <= ai[i] - st + t - 1; j++) { if (j <= 0 || j > 320) continue; bi[j]++; } sum++; st++; } } printf( %I64d n , sum); } int main() { while (scanf( %d%d%d , &m, &t, &r) != EOF) { init(); play(); } return 0; } |
#include <bits/stdc++.h> using namespace std; pair<long long, long long> p1[1005]; pair<long long, long long> p2[1005]; vector<long long> v; int main() { long long i, j, n, x, y, a, b; cin >> n; for (i = 0; i < n; i++) cin >> p1[i].first >> p1[i].second; for (i = 0; i < n; i++) cin >> p2[i].first >> p2[i].second; sort(p1, p1 + n); sort(p2, p2 + n); cout << p1[0].first + p2[n - 1].first << << p1[0].second + p2[n - 1].second; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 1
(* X_CORE_INFO = "sample_generator_v1_0,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_sample_generator_0_1,sample_generator_v1_0,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_1 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
#include <bits/stdc++.h> const int MAXN = 1e5 + 19; int qpow(int a, int b, int p) { int res = 1; while (b) { if (b & 1) res = (long long)res * a % p; a = (long long)a * a % p, b >>= 1; } return res; } int n, m, k, p; int fa[MAXN], size[MAXN]; int getf(int node) { return fa[node] == node ? node : fa[node] = getf(fa[node]); } int main() { std::scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; ++i) fa[i] = i, size[i] = 1; for (int i = 1; i <= m; ++i) { int u, v; std::scanf( %d%d , &u, &v); if (getf(u) != getf(v)) { size[getf(v)] += size[getf(u)]; fa[getf(u)] = getf(v); } } int ans = 1; for (int i = 1; i <= n; ++i) if (fa[i] == i) ++k, ans = (long long)ans * size[i] % p; if (k >= 2) ans = (long long)ans * qpow(n, k - 2, p) % p; else ans = 1; std::printf( %d n , ans % p); return 0; } |
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module processing_unit
(
// Closk & reset
input wire CLK,
input wire RST,
// Data input
input wire I_STB,
input wire [31:0] I_DAT,
// Data output
output wire O_STB,
output wire [31:0] O_DAT
);
// ============================================================================
wire [15:0] i_dat_a = I_DAT[15: 0];
wire [15:0] i_dat_b = I_DAT[31:16];
reg o_stb;
reg [31:0] o_dat;
always @(posedge CLK)
o_dat <= i_dat_a * i_dat_b;
always @(posedge CLK or posedge RST)
if (RST) o_stb <= 1'd0;
else o_stb <= I_STB;
assign O_STB = o_stb;
assign O_DAT = o_dat;
// ============================================================================
endmodule
|
#include <bits/stdc++.h> using namespace std; char str[100010]; int ct[100010][4]; int main() { int N, x[5], R, L, M; scanf( %s , str); N = strlen(str); for (int i = 1; i <= N; i++) { for (int j = 0; j < 3; j++) ct[i][j] = ct[i - 1][j]; ct[i][str[i - 1] - x ]++; } scanf( %d , &M); for (int i = 0; i < M; i++) { scanf( %d%d , &L, &R); L--; if (R - L < 3) { puts( YES ); continue; } for (int j = 0; j < 3; j++) x[j] = ct[R][j] - ct[L][j]; if (x[0] <= x[1] && x[1] <= x[2] && x[2] - x[0] <= 1) puts( YES ); else if (x[1] <= x[2] && x[2] <= x[0] && x[0] - x[1] <= 1) puts( YES ); else if (x[2] <= x[0] && x[0] <= x[1] && x[1] - x[2] <= 1) puts( YES ); else puts( NO ); } return 0; } |
#include <bits/stdc++.h> using namespace std; string a, b; int main() { cin >> a >> b; if (a == b) { cout << a << endl; return 0; } else { cout << 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int compare(const void* a, const void* b) { return (*(int*)a - *(int*)b); } int main() { int n; long long k, sum2, sum3; int a[100005], c[100005]; long long b[100005]; int i, j, count; cin >> n; cin >> k; for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); count = 0; for (i = 0; i < n; i++) { j = i; while (a[j] == a[i] && j < n) j++; b[count] = j - i; c[count] = a[i]; count++; i = j - 1; } sum2 = 0; for (i = 0; i < count; i++) { if (sum2 + b[i] * n >= k) { sum3 = 0; for (j = 0; j < count; j++) { sum3 += (b[i] * b[j]); if (sum2 + sum3 >= k) { printf( %d %d , c[i], c[j]); return 0; } } } else sum2 += (b[i] * n); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; int n, q; vector<pair<int, int> > query[maxn]; vector<int> G[maxn]; long long ans[maxn]; long long add[maxn]; void dfs(int v, int p, int d, long long sum) { for (auto p : query[v]) { int l = d; int r = d + p.first + 1; add[l] += p.second; if (r < maxn) add[r] -= p.second; } sum += add[d]; ans[v] = sum; for (int u : G[v]) { if (u == p) continue; dfs(u, v, d + 1, sum); } for (auto p : query[v]) { int l = d; int r = d + p.first + 1; add[l] -= p.second; if (r < maxn) add[r] += p.second; } } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d%d , &x, &y); G[x].emplace_back(y); G[y].emplace_back(x); } scanf( %d , &q); while (q--) { int v, d, x; scanf( %d%d%d , &v, &d, &x); query[v].push_back(make_pair(d, x)); } dfs(1, 0, 1, 0); for (int i = 1; i <= n; i++) { printf( %I64d , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int i = 1; i <= 2 * n / 3; i++) printf( %d %d n , i, 1); for (int i = 1; i <= n - 2 * n / 3; i++) printf( %d %d n , i * 2, 4); return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_SRAM_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 14: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 14: 0] data_out;
wire [ 14: 0] out_port;
wire [ 14: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {15 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[14 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DIFFINBUF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
output O_B,
input DIFF_IN_N,
input DIFF_IN_P,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "DIFFINBUF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_B_out;
reg O_out;
reg O_OSC_in;
reg O_B_OSC_in;
wire O_B_delay;
wire O_delay;
wire DIFF_IN_N_in;
wire DIFF_IN_P_in;
wire VREF_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire DIFF_IN_N_delay;
wire DIFF_IN_P_delay;
wire VREF_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) O_B = O_B_delay;
// inputs with no timing checks
assign #(in_delay) DIFF_IN_N_delay = DIFF_IN_N;
assign #(in_delay) DIFF_IN_P_delay = DIFF_IN_P;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_B_delay = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
assign DIFF_IN_N_in = DIFF_IN_N_delay;
assign DIFF_IN_P_in = DIFF_IN_P_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= ~O_OSC_in;
O_B_OSC_in <= ~O_B_OSC_in;
end
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= 1'bx;
O_B_OSC_in <= 1'bx;
end
end
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-106] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
$finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-111] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(DIFF_IN_P_in or DIFF_IN_N_in or DQS_BIAS_BIN) begin
if (DIFF_IN_P_in == 1'b1 && DIFF_IN_N_in == 1'b0) begin
O_out <= 1'b1;
O_B_out <= 1'b0;
end
else if (DIFF_IN_P_in == 1'b0 && DIFF_IN_N_in == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else if ((DIFF_IN_P_in === 1'bz || DIFF_IN_P_in == 1'b0) && (DIFF_IN_N_in === 1'bz || DIFF_IN_N_in == 1'b1)) begin
if (DQS_BIAS_BIN == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
end
else if ((DIFF_IN_P_in === 1'bx) || (DIFF_IN_N_in === 1'bx)) begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
// O_out <= DIFF_IN_P_in;
// O_B_out <= DIFF_IN_N_in;
end
specify
(DIFF_IN_N => O) = (0:0:0, 0:0:0);
(DIFF_IN_N => O_B) = (0:0:0, 0:0:0);
(DIFF_IN_P => O) = (0:0:0, 0:0:0);
(DIFF_IN_P => O_B) = (0:0:0, 0:0:0);
(OSC_EN *> O) = (0:0:0, 0:0:0);
(OSC_EN *> O_B) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//#############################################################################
//# Function: Isolation (Low) buffer for multi supply domains #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isolo #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
input [DW-1:0] in, // input signal
output [DW-1:0] out // out = ~iso & in
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic
asic_iso_lo iiso [DW-1:0] (.iso(iso),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin : gen
assign out[DW-1:0] = {(DW){~iso}} & in[DW-1:0];
end
endgenerate
endmodule // oh_buf
|
#include <bits/stdc++.h> using namespace std; unsigned long long get_idx(int p) { int idx = 1; while (idx < p) idx *= 2; return idx; } void update(vector<unsigned long long> &tree, unsigned long long idx, unsigned long long val) { tree[idx] = val; idx /= 2; while (idx) { tree[idx] = tree[idx * 2] | tree[idx * 2 + 1]; idx /= 2; } } int main() { unsigned long long n, k, x, a = 1; unsigned long long ans = 0; cin >> n >> k >> x; vector<unsigned long long> data(n); for (int i = 0; i < k; i++) a *= x; for (int i = 0; i < n; i++) cin >> data[i]; unsigned long long idx = get_idx(n); vector<unsigned long long> tree(idx * 2); for (int i = idx; i < idx + n; i++) update(tree, i, data[i - idx]); for (int i = 0; i < n; i++) { update(tree, i + idx, data[i] * a); ans = max(tree[1], ans); update(tree, i + idx, data[i]); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 3000020, M = 120; int L, R, p, ans, tot, cnt, g[N], f[N], P[M]; bool buc[N], vis[M]; void dfs(int k, int res) { g[++cnt] = res; for (int i = k; i <= tot; i++) { if (1ll * P[i] * res <= 1ll * R) dfs(i, res * P[i]); } } signed main() { memset(f, 0x3f, sizeof(f)); cin >> L >> R >> p; for (int i = 2; i <= p; i++) { if (!vis[i]) P[++tot] = i; for (int j = 1; j <= tot && i * P[j] <= p; j++) { vis[i * P[j]] = 1; if (i % P[j] == 0) break; } } dfs(1, 1); sort(g + 1, g + cnt + 1); f[1] = 0; for (int i = 2; i <= p; i++) { int j = 1; for (int k = 1; k <= cnt; k++) { while (j <= cnt && 1ll * g[j] != 1ll * g[k] * i) j++; if (j == cnt + 1) break; f[j] = min(f[j], f[k] + 1); if (f[j] + i <= p && g[j] >= L && !buc[j]) buc[j] = 1, ans++; } } cout << ans; return 0; } |
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_clshift
// ============================================================
// File Name: arithshiftbidir.v
// Megafunction Name(s):
// lpm_clshift
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module arithshiftbidir (
distance,
data,
direction,
result);
input [4:0] distance;
input [31:0] data;
input direction;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift lpm_clshift_component (
.distance (distance),
.direction (direction),
.data (data),
.result (sub_wire0));
defparam
lpm_clshift_component.lpm_type = "LPM_CLSHIFT",
lpm_clshift_component.lpm_shifttype = "ARITHMETIC",
lpm_clshift_component.lpm_width = 32,
lpm_clshift_component.lpm_widthdist = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "1"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "32"
// Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "5"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "ARITHMETIC"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "5"
// Retrieval info: USED_PORT: distance 0 0 5 0 INPUT NODEFVAL distance[4..0]
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
// Retrieval info: CONNECT: @distance 0 0 5 0 distance 0 0 5 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
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