text stringlengths 59 71.4k |
|---|
module BarrelShifter(input [31:0] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
/*
Data processing immediate IR[27:25] == 000 & IR[4] = 0/ IR[6:5] Shiftype / IR[11:7] Shift Amount/ Shift val Rm
Data register shift IR[27:25] == 000 / IR[6:5] Shiftype / Rs Shift Amount/ Shift val Rm
Data processing immediate IR[27:25] == 001 / ROR Shiftype / IR[11:7] Shift Amount / Shift val IR[7:0]
Load/Store immediate IR[27:25] == 010
Load/Store register offset IR[27:25] == 011
branch and branch with link IR[27:25] == 101
*/
reg [31:0] shiftVal,shiftAmount;
reg [1:0] shiftType;
always@(IR or Rm or Rs or SR29_IN)
begin
case(IR[27:25])
3'b000:
begin
if(!IR[4])//Immediate Rs
begin
$display("Immediate Rm");
shiftVal = Rm;
shiftAmount = IR[11:7];
shiftType = IR[6:5];
end
else
begin
$display("Registe rm"); // Registe rs
shiftVal = Rm;
shiftAmount = Rs[5:0];
shiftType = IR[6:5];
end
end
3'b001:
begin//Imediate IR[7:0]
$display("Imediate IR[7:0]");
shiftVal = IR[7:0];
shiftAmount = IR[11:8]*2;
shiftType = 2'b11;
end
3'b010:
begin//Imediate IR[7:0]
$display("Load/Store-Immediate Rm");
_Out = {IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11:0]};
end
3'b011:
begin//Imediate IR[7:0]
$display("Load/Store-offsett/index Rm");
shiftVal = Rm;
shiftAmount = IR[11:7];
shiftType = IR[6:5];
end
3'b101:
begin//branch
$display("Branch");
_Out = 4*{IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23:0]};
end
endcase
end
reg [32:0] temp,temp2;
reg [31:0] _Out;
reg _SR29_OUT;
integer i=0;
assign Out = _Out;
assign SR29_OUT = _SR29_OUT;
always@(*)
begin
case(shiftType)
2'b00:
begin
$display("LSL");
if(shiftAmount==32)
_Out = 0 ;
else if (shiftAmount>=33)
{_SR29_OUT,_Out} = 0 ;
else begin
temp = {SR29_IN,shiftVal };
temp2 = 0;
for(i = 0; i <= 32 - shiftAmount[4:0] ;i = i + 1) begin
temp2[32-i] = temp[32-i-shiftAmount[4:0] ] ;
end
{_SR29_OUT,_Out} = temp2;
end
end
2'b01:
begin
$display("LSR");
if(shiftAmount==32)
_Out = 0 ;
else if (shiftAmount>=33)
{_SR29_OUT,_Out} = 0 ;
else begin
temp = {shiftVal,SR29_IN};
temp2 = 0;
for(i = 0; i <= 32-shiftAmount[4:0] ;i = i + 1) begin
temp2[i] = temp[i+shiftAmount[4:0] ] ;
end
{_Out,_SR29_OUT} = temp2;
end
end
2'b10:
begin
$display("ASR");
if(shiftAmount==32)
begin
_Out = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31]};
end
else if (shiftAmount>=33)
begin
{_SR29_OUT,_Out} = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31]};
end
else begin
temp = {shiftVal,SR29_IN };
//Lazy to encode in loop
temp2 = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31]};
for(i = 0; i <= 32-shiftAmount[4:0] ;i = i + 1) begin
temp2[i] = temp[i+shiftAmount[4:0] ] ;
end
{_Out,_SR29_OUT} = temp2;
end
end
2'b11:
begin
$display("ROR");
temp = {shiftVal,SR29_IN};
temp2 = temp;
for(i = 0; i <= 32 ;i = i + 1) begin
temp2[i] = temp[(i+shiftAmount[4:0])%33] ;
$display("[%3d]=[%3d]",i,(i+shiftAmount[4:0])%33);
end
{_Out,_SR29_OUT} = temp2;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int main() { scanf( %d , &n); for (int i = 0; i < 2 * n + 1; i++) { for (int j = 0; j < 2 * n + 1; j++) { if (i < n + 1) { if (j < n - i) { printf( ); } else if (j < n + i) { if (j <= n) { printf( %d , j - n + i); } else { printf( %d , abs(j - n - i)); } } else if (j == n + i) { printf( 0 ); } } else { int temp = i; i = 2 * n - i; if (j < n - i) { printf( ); } else if (j < n + i) { if (j <= n) { printf( %d , j - n + i); } else { printf( %d , abs(j - n - i)); } } else if (j == n + i) { printf( 0 ); } i = temp; } } printf( n ); } } |
`ifndef _alu
`define _alu
module alu(
input [5:0] funct,
input [5:0] opcode,
input [31:0] a, b,
output reg [31:0] out,
output zero);
// control (opcode -> ...)
wire regdst;
wire [1:0] branch_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
control ctl1(.branch(branch_s2),
/*AUTOINST*/
// Outputs
.regdst (regdst),
.memread (memread),
.memtoreg (memtoreg),
.aluop (aluop[1:0]),
.memwrite (memwrite),
.alusrc (alusrc),
.regwrite (regwrite),
// Inputs
.opcode (opcode[5:0])); //fixme: opcode may need be stored in rob/rs
// ALU control
wire [3:0] aluctl;
alu_control alu_ctl1(.aluop(aluop),
/*AUTOINST*/
// Outputs
.aluctl (aluctl[3:0]),
// Inputs
.funct (funct[5:0]));//fixme: funct may need be stored in rob/rs
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
// overflow occurs (with 2's complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on wheter addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (aluctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (aluctl)
4'b0010: out <= add_ab; // a + b
4'b0000: out <= a & b; // and
4'b1100: out <= ~(a | b); // nor
4'b0001: out <= a | b; // or
4'b0111: out <= {{31{1'b0}}, slt}; // set if less than
4'b0110: out <= sub_ab; // a - b
4'b1101: out <= a ^ b; // xor
default: out <= 0;
endcase
end
endmodule
`endif
|
`timescale 1ns/100ps
module top;
reg pass = 1'b1;
integer idelay = 2;
real rdelay = 2.0;
real rin = 1.0;
reg ctl = 1'b1;
wire outr, outi, muxr, muxi;
wire real rout;
reg in = 1'b1;
assign #(idelay) outi = in;
assign #(rdelay) outr = ~in;
assign #(rdelay) rout = rin;
assign #(idelay) muxi = ctl ? in : 1'b0;
assign #(rdelay) muxr = ctl ? ~in : 1'b1;
initial begin
// Wait for everything to settle including the delay value!
#2.1;
if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin
$display("FAILED: initial value, expected 1'b1/1'b0/1.0, got %b/%b/%f",
outi, outr, rout);
pass = 1'b0;
end
if (muxi !== 1'b1 || muxr !== 1'b0) begin
$display("FAILED: initial value (mux), expected 1'b1/1'b0, got %b/%b",
muxi, muxr);
pass = 1'b0;
end
in = 1'b0;
rin = 2.0;
#1.9;
if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin
$display("FAILED: mid value, expected 1'b1/1'b0/1.0, got %b/%b/%f",
outi, outr, rout);
pass = 1'b0;
end
if (muxi !== 1'b1 || muxr !== 1'b0) begin
$display("FAILED: mid value (mux), expected 1'b1/1'b0, got %b/%b",
muxi, muxr);
pass = 1'b0;
end
#0.2;
if (outi !== 1'b0 || outr !== 1'b1 || rout != 2.0) begin
$display("FAILED: final value, expected 1'b0/1'b1/2.0, got %b/%b/%f",
outi, outr, rout);
pass = 1'b0;
end
if (muxi !== 1'b0 || muxr !== 1'b1) begin
$display("FAILED: final value (mux), expected 1'b0/1'b1, got %b/%b",
muxi, muxr);
pass = 1'b0;
end
idelay = 3;
in = 1'b1;
#2.9;
if (outi !== 1'b0) begin
$display("FAILED: initial change, expected 1'b0, got %b", outi);
pass = 1'b0;
end
#0.2;
if (outi !== 1'b1) begin
$display("FAILED: initial change, expected 1'b1, got %b", outi);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: phy_clock_io.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for CK/CK# clock forwarding to memory
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_clock_io.v,v 1.3 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_clock_io.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_clock_io #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter CK_WIDTH = 2, // # of clock output pairs
parameter WRLVL = "OFF", // Enable write leveling
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem, // full rate core clock
input clk, // half rate core clock
input rst, // half rate core clk reset
output [CK_WIDTH-1:0] ddr_ck_p, // forwarded diff. clock to memory
output [CK_WIDTH-1:0] ddr_ck_n // forwarded diff. clock to memory
);
//***************************************************************************
generate
genvar ck_i;
for (ck_i = 0; ck_i < CK_WIDTH; ck_i = ck_i + 1) begin: gen_ck
phy_ck_iob #
(
.TCQ (TCQ),
.WRLVL (WRLVL),
.DRAM_TYPE (DRAM_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP)
)
u_phy_ck_iob
(
.clk_mem (clk_mem),
.clk (clk),
.rst (rst),
.ddr_ck_p (ddr_ck_p[ck_i]),
.ddr_ck_n (ddr_ck_n[ck_i])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; void checkmin(int &x, int y) { if (x > y) x = y; } void checkmax(int &x, int y) { if (x < y) x = y; } inline int read() { int x = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } const int N = 20; const int M = (1 << 20); int n; long long a[N], sum[M]; int dp[M], vis[M], sz[M]; signed main() { n = read(); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); if (!a[i]) n--, i--; } int full = (1 << n) - 1; for (int i = 0; i <= full; i++) for (int j = 0; j < n; j++) if (i >> j & 1) sum[i] += a[j], sz[i]++; for (int mask1 = 1; mask1 <= full; mask1++) { for (int mask2 = (mask1 - 1) & mask1; (mask2 << 1) >= mask1; mask2 = mask1 & (mask2 - 1)) { int mask3 = mask1 ^ mask2; long long tmp = abs(sum[mask2] - sum[mask3]); if (tmp < sz[mask1] && (sz[mask1] - tmp) & 1) { vis[mask1] = 1; break; } } } for (int i = 1; i <= full; i++) if (vis[i]) { int rest = full ^ i; checkmax(dp[i], 1); for (int j = rest; j; j = rest & (j - 1)) checkmax(dp[i | j], dp[j] + dp[i]); } int mx = 0; for (int mask = 1; mask <= full; mask++) checkmax(mx, dp[mask]); printf( %d n , n - mx); return 0; } |
#include <bits/stdc++.h> using namespace std; typedef pair<long long, long long> ll; typedef vector<long long> vl; typedef vector<ll> vll; typedef vector<vl> vvl; template <typename T> ostream &operator<<(ostream &o, vector<T> v) { if (v.size() > 0) o << v[0]; for (unsigned i = 1; i < v.size(); i++) o << << v[i]; return o << n ; } template <typename U, typename V> ostream &operator<<(ostream &o, pair<U, V> p) { return o << ( << p.first << , << p.second << ) ; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (unsigned i = 0; i < v.size(); i++) in >> v[i]; return in; } template <typename T> istream &operator>>(istream &in, pair<T, T> &p) { in >> p.first; in >> p.second; return in; } vvl g(111000); vl ind(111000, 0), vis(111000, false); long long c = 0; bool rec(long long node, long long p) { vl ch; ind[node] = c++; vis[node] = 1; for (auto &it : g[node]) { if (it == p) continue; if (!vis[it]) { if (!rec(it, node)) ch.push_back((it)); } else if (ind[node] < ind[it]) ch.push_back((it)); } for (long long i = 0; i + 1 < ch.size(); i += 2) cout << ch[i] << << node << << ch[i + 1] << n ; if (ch.size() % 2 == 1) { cout << p << << node << << ch[ch.size() - 1] << n ; return true; } return false; } int main() { long long n, m; cin >> n >> m; if (m % 2 == 1) { cout << No solution << n ; return 0; } while (m--) { long long x, y; cin >> x >> y; g[x].push_back((y)); g[y].push_back((x)); } rec(1, -1); return 0; } |
#include <bits/stdc++.h> using namespace std; int X[1 << 11]; int Y[1 << 11]; int B[1 << 11]; int NX[1 << 11]; int NY[1 << 11]; int E[1 << 11][1 << 11]; int gN; int dfs(int a) { if (a == gN - 1) return 1; B[a] = 1; int i; for (i = (0); i < (gN); ++i) if (B[i] == 0 && E[a][i] > 0 && dfs(i) != 0) { --E[a][i]; ++E[i][a]; return 1; } return 0; } void fwd(int a) { B[a] = 1; int i; for (i = (0); i < (gN); ++i) if (B[i] == 0 && E[a][i] > 0) fwd(i); } void bwd(int a) { B[a] = 1; int i; for (i = (0); i < (gN); ++i) if (B[i] == 0 && E[i][a] > 0) bwd(i); } int main() { int n; scanf( %d , &n); int i, j; for (i = (0); i < (n); ++i) scanf( %d%d , &X[i], &Y[i]); vector<pair<pair<int, int>, int>> vx(n), vy(n); for (i = (0); i < (n); ++i) { vx[i] = make_pair(pair<int, int>(X[i], Y[i]), i); vy[i] = make_pair(pair<int, int>(Y[i], X[i]), i); } sort((vx).begin(), (vx).end()); sort((vy).begin(), (vy).end()); vector<pair<int, int>> x, y; for (i = (1); i < (n); ++i) if (vx[i].first.first == vx[i - 1].first.first) x.push_back(pair<int, int>(vx[i - 1].second, vx[i].second)); for (i = (1); i < (n); ++i) if (vy[i].first.first == vy[i - 1].first.first) y.push_back(pair<int, int>(vy[i - 1].second, vy[i].second)); int nx = int((x).size()); int ny = int((y).size()); memset(NX, -1, sizeof(NX)); memset(NY, -1, sizeof(NY)); for (i = (0); i < (nx); ++i) NX[x[i].first] = x[i].second; for (i = (0); i < (ny); ++i) NY[y[i].first] = y[i].second; memset(E, 0, sizeof(E)); for (i = (0); i < (nx); ++i) for (j = (0); j < (ny); ++j) { int ax = x[i].first; int bx = x[i].second; int ay = y[j].first; int by = y[j].second; if (Y[ay] <= Y[ax] || Y[bx] <= Y[ay]) continue; if (X[ax] <= X[ay] || X[by] <= X[ax]) continue; E[i][nx + j] = 1; } for (i = (0); i < (nx); ++i) E[nx + ny][i] = 1; for (i = (0); i < (ny); ++i) E[i + nx][nx + ny + 1] = 1; gN = nx + ny + 2; int flow = 0; for (i = (0); i < (nx); ++i) for (j = (0); j < (ny); ++j) if (E[gN - 2][i] > 0 && E[i][nx + j] > 0 && E[nx + j][gN - 1] > 0) { --E[gN - 2][i]; ++E[i][gN - 2]; --E[i][nx + j]; ++E[nx + j][i]; --E[nx + j][gN - 1]; ++E[gN - 1][nx + j]; ++flow; } while (true) { memset(B, 0, sizeof(B)); if (dfs(nx + ny) == 0) break; ++flow; } for (i = (0); i < (nx); ++i) if (B[i] == 0) { int a = x[i].first; int b = x[i].second; NX[a] = -1; } for (i = (0); i < (ny); ++i) if (B[nx + i] != 0) { int a = y[i].first; int b = y[i].second; NY[a] = -1; } memset(B, 0, sizeof(B)); vector<pair<pair<int, int>, pair<int, int>>> rx; for (i = (0); i < (int((vx).size())); ++i) { int a = vx[i].second; if (B[a] != 0) continue; B[a] = 1; int b = a; while (NX[b] != -1) { b = NX[b]; B[b] = 1; } if (X[a] != X[b]) throw 0; rx.push_back( make_pair(pair<int, int>(X[a], Y[a]), pair<int, int>(X[b], Y[b]))); } memset(B, 0, sizeof(B)); vector<pair<pair<int, int>, pair<int, int>>> ry; for (i = (0); i < (int((vy).size())); ++i) { int a = vy[i].second; if (B[a] != 0) continue; B[a] = 1; int b = a; while (NY[b] != -1) { b = NY[b]; B[b] = 1; } if (Y[a] != Y[b]) throw 0; ry.push_back( make_pair(pair<int, int>(X[a], Y[a]), pair<int, int>(X[b], Y[b]))); } if (int((rx).size()) + int((ry).size()) != 2 * n - (nx + ny - flow)) throw 0; printf( %d n , int((ry).size())); for (i = (0); i < (int((ry).size())); ++i) printf( %d %d %d %d n , ry[i].first.first, ry[i].first.second, ry[i].second.first, ry[i].second.second); printf( %d n , int((rx).size())); for (i = (0); i < (int((rx).size())); ++i) printf( %d %d %d %d n , rx[i].first.first, rx[i].first.second, rx[i].second.first, rx[i].second.second); return 0; }; |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; vector<string> v, l, b; for (long long int i = 0; i < n; i++) { string s; cin >> s; v.push_back(s); } long long int c = -1; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m + 2; j++) { if (v[i][j] == 1 ) { c = i; break; } } if (c != -1) break; } if (c == -1) { cout << 0; return 0; } for (long long int i = c; i < n; i++) { l.push_back(v[i]); } n = n - c; long long int f = n; for (long long int i = n - 1; i >= 0; i--) { for (long long int j = 0; j < m + 2; j++) { if (l[i][j] == 1 ) { f = i; break; } } if (f != n) break; } if (f == n) { cout << 0; return 0; } for (long long int i = 0; i <= f; i++) { b.push_back(l[i]); } long long int g = n; n = f + 1; long long int k = 0; for (long long int i = m + 1; i >= 0; i--) { if (b[n - 1][i] == 1 ) { k = i; break; } } if (n == 1) { cout << k + g - 1 - f; } else { long long int a[n][m + 2]; memset(a, 0, sizeof(a)); a[n - 1][0] = 2 * k; a[n - 1][m + 1] = m + 1; a[n - 2][0] = 2 * k + 1; a[n - 2][m + 1] = m + 2; for (long long int i = n - 2; i > 0; i--) { long long int x1 = 0; long long int x2 = m + 1; for (long long int j = m + 1; j >= 0; j--) { if (b[i][j] == 1 ) { x1 = j; break; } } for (long long int j = 0; j <= (m + 1); j++) { if (b[i][j] == 1 ) { x2 = j; break; } } a[i - 1][0] = 1 + min(m + 1 + a[i][m + 1], a[i][0] + 2 * x1); a[i - 1][m + 1] = 1 + min(m + 1 + a[i][0], a[i][m + 1] + 2 * (m + 1 - x2)); } long long int x1 = 0; long long int x2 = m + 1; for (long long int j = m + 1; j >= 0; j--) { if (b[0][j] == 1 ) { x1 = j; break; } } for (long long int j = 0; j <= (m + 1); j++) { if (b[0][j] == 1 ) { x2 = j; break; } } cout << min(a[0][0] + x1, a[0][m + 1] + m + 1 - x2) + g - 1 - f << endl; } } |
#include <bits/stdc++.h> using namespace std; set<pair<pair<int, int>, pair<int, int> > > s; vector<int> ed[2][300000]; int n, m, k; int a[300000], b[300000]; long long ans[300000]; bool add(int x, int y, int dx, int dy) { pair<pair<int, int>, pair<int, int> > g = make_pair(make_pair(x, y), make_pair(dx, dy)); if (s.find(g) != s.end()) return false; s.insert(g); return true; } void go(int x, int y, int dx, int dy, long long t) { int tt = 1; int d = x - y + m; if (dx - dy != 0) { tt = 0; d = x + y; } bool f = add(x, y, dx, dy); if (!f) return; for (int j = 0; j < ed[tt][d].size(); j++) { int kx = a[ed[tt][d][j]]; int ky = b[ed[tt][d][j]]; kx = kx - x; ky = ky - y; kx = kx / dx; ky = ky / dy; int g = ed[tt][d][j]; if (ans[g] != -1) continue; ans[g] = t + min(kx, ky); } if (dx == 1 && dy == 1) { int v = min(n - x, m - y); x += v; y += v; if (x == n && y == m) return; if (y == m) go(x, y, 1, -1, t + v); else go(x, y, -1, 1, t + v); } if (dx == -1 && dy == -1) { int v = min(x, y); x -= v; y -= v; if (x == 0 && y == 0) return; if (y == 0) go(x, y, -1, 1, t + v); else go(x, y, 1, -1, t + v); } if (dx == 1 && dy == -1) { int v = min(n - x, y); x += v; y -= v; if (x == n && y == 0) return; if (y == 0) go(x, y, 1, 1, t + v); else go(x, y, -1, -1, t + v); } if (dx == -1 && dy == 1) { int v = min(x, m - y); x -= v; y += v; if (x == 0 && y == m) return; if (x == 0) go(x, y, 1, 1, t + v); else go(x, y, -1, -1, t + v); } } int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> k; for (int i = 1; i <= k; i++) ans[i] = -1; for (int i = 1; i <= k; i++) { cin >> a[i] >> b[i]; ed[0][a[i] + b[i]].push_back(i); ed[1][a[i] - b[i] + m].push_back(i); } go(0, 0, 1, 1, 0); for (int i = 1; i <= k; i++) cout << ans[i] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; struct modint { int n; modint() : n(0) {} modint(int n) : n(n) {} }; modint operator+(modint a, modint b) { return modint((a.n += b.n) >= mod ? a.n - mod : a.n); } modint operator*(modint a, modint b) { return modint(1LL * a.n * b.n % mod); } bool operator<(modint a, modint b) { return a.n < b.n; } bool operator!=(modint a, modint b) { return a.n != b.n; } const int S = 4; using modints = array<modint, S>; modints operator+(modints a, modints b) { modints ret; for (int i = 0; i < S; i++) { ret[i] = a[i] + b[i]; } return ret; } modints operator*(modints a, modints b) { modints ret; for (int i = 0; i < S; i++) { ret[i] = a[i] * b[i]; } return ret; } bool operator<(modints a, modints b) { for (int i = 0; i < S; i++) { if (a[i] != b[i]) return a[i] < b[i]; } return false; } const int N = 1e5; int n; vector<int> g[N]; vector<int> gg[N]; modints rnd[N]; int height[N]; vector<int> h; modints val[N]; modints one; map<modints, int> mp; pair<int, int> ans; int cnt = 0; void add(modints a) { if (mp[a]++ == 0) { cnt++; } } void del(modints a) { if (mp[a]-- == 1) { cnt--; } assert(mp[a] >= 0); } void dfs(int u, int p) { for (int v : g[u]) if (v != p) { dfs(v, u); height[u] = max(height[u], height[v] + 1); } val[u] = one; for (int v : g[u]) if (v != p) { val[u] = val[u] * (rnd[height[u]] + val[v]); } add(val[u]); } void dfs2(int u, int p) { auto tmp = val[u]; del(tmp); int n = g[u].size(); h.clear(); h.push_back(0); for (int v : g[u]) { h.push_back(height[v] + 1); } sort(h.rbegin(), h.rend()); int h0 = h[0]; int h1 = h[1]; modints L0 = one; modints L1 = one; vector<modints> R0(n); vector<modints> R1(n); R0[n - 1] = one; R1[n - 1] = one; for (int i = n - 2; i >= 0; i--) { R0[i] = R0[i + 1] * (rnd[h0] + val[g[u][i + 1]]); R1[i] = R1[i + 1] * (rnd[h1] + val[g[u][i + 1]]); } ans = max(ans, make_pair(cnt, u)); for (int i = 0; i < n; i++) { int v = g[u][i]; if (height[v] + 1 != h0) { height[u] = h0; val[u] = L0 * R0[i]; } else { height[u] = h1; val[u] = L1 * R1[i]; } L0 = L0 * (rnd[h0] + val[v]); L1 = L1 * (rnd[h1] + val[v]); if (v == p) continue; add(val[u]); dfs2(v, u); del(val[u]); } add(tmp); } int main() { mt19937 mt(time(NULL) ^ 1234567); uniform_int_distribution<int> uni(0, mod - 1); for (int i = 0; i < N; i++) { for (int j = 0; j < S; j++) { rnd[i][j] = uni(mt); } } for (int i = 0; i < S; i++) { one[i] = 1; } cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; g[u].push_back(v); g[v].push_back(u); } if (n == 1) { cout << 1 << endl; return 0; } dfs(0, -1); dfs2(0, -1); cout << ans.second + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; long long bins(long long l, long long r) { while (l + 1 < r) { long long m = (l + r) >> 1; cout << ? << l << << m << endl; cout.flush(); char c; cin >> c; if (c == e ) return 0; if (c == y ) { l = m; } else { r = m; } } return r; } signed main() { string s; cin >> s; long long x, y; while (s == start ) { x = 0, y = 1; char c = y ; bool z = false; while (c != x ) { if (!z) z = true; else x = y, y *= 2; cout << ? << x << << y << endl; cout.flush(); cin >> c; if (c == e ) return 0; } long long p = bins(x, y); cout << ! << p << endl; cout.flush(); cin >> s; if (s == mistake ) { return 0; } if (s == end ) return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e6 + 100; const long long MAXL = 21; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long x, r, l; cin >> x >> l >> r; long long ans = 0; long long a = 1; while (2 * a <= x) a = 2 * a; for (long long i = l; i <= r; i++) ans += bool(x & (a / (i & -i))); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 10000; const int maxm = 20000; const int maxk = 10; const int inf = 25; int tot_edge, sz; int head[maxn]; int nxt[maxm]; int to[maxm]; int cap[maxm]; int flow[maxk + 1][maxm]; int qu[maxn]; int prv[maxn]; int when[maxn]; int pass_flow[maxn]; int last_time; int level[maxn], edge_pos[maxn]; int read() { int xx = 0, ff = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) ff = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { xx = (xx << 3) + (xx << 1) + ch - 0 ; ch = getchar(); } return xx * ff; } void add_edge(int u, int v, int w) { nxt[tot_edge] = head[u]; head[u] = tot_edge; to[tot_edge] = v; cap[tot_edge] = w; tot_edge++; } bool bfs(int s, int t, int *flow) { sz = 0; qu[sz++] = t; int pnt = 0; memset(level, -1, sizeof(level)); level[t] = 0; while (pnt < sz && level[s] == -1) { int u = qu[pnt++]; for (int e = head[u]; e >= 0; e = nxt[e]) { int v = to[e]; if (level[v] == -1 && flow[e ^ 1] < cap[e ^ 1]) { level[v] = level[u] + 1; qu[sz++] = v; } } } return level[s] != -1; } int dinic(int s, int t, int *flow) { int ret = 0; while (bfs(s, t, flow)) { copy(head, head + maxn, edge_pos); function<int(int, int)> find_path = [&](int u, int res) { if (u == t) return res; for (int &e = edge_pos[u]; e >= 0; e = nxt[e]) { int v = to[e]; if (flow[e] == cap[e] || level[u] - 1 != level[v]) continue; int push = find_path(v, min(res, cap[e] - flow[e])); if (push > 0) { flow[e] += push; flow[e ^ 1] -= push; if (flow[e] == cap[e]) e = nxt[e]; return push; } } return 0; }; for (int f; (f = find_path(s, 1e9)) > 0;) ret += f; } return ret; } int augment(int s, int t, int *flow) { last_time++; sz = 0; qu[sz++] = s; when[s] = last_time; int pnt = 0; pass_flow[s] = inf; pass_flow[t] = 0; while (pnt < sz && when[t] != last_time) { int u = qu[pnt++]; assert(pass_flow[u] > 0); for (int e = head[u]; e >= 0; e = nxt[e]) { int v = to[e]; if (when[v] != last_time && flow[e] < cap[e]) { pass_flow[v] = min(pass_flow[u], cap[e] - flow[e]); prv[v] = e; when[v] = last_time; qu[sz++] = v; if (v == t) break; } } } int f = pass_flow[t]; if (f == 0) return f; do { int e = prv[t]; flow[e] += f; flow[e ^ 1] -= f; assert(to[e] == t); t = to[e ^ 1]; } while (t != s); return f; } int max_flow(int s, int t, int *flow) { int res = 0, cur = 0; do { cur = augment(s, t, flow); res += cur; } while (cur); return res; } int n, m, k, q; int masked[1 << maxk]; void go(int n, int m, int mask, int pointer) { for (int i = 0; (mask >> i & 1) == 0 && i < k; ++i) { int n_mask = mask | (1 << i); copy(flow[pointer], flow[pointer] + m, flow[pointer + 1]); cap[2 * i] = inf; masked[n_mask] = masked[mask] + max_flow(0, n - 1, flow[pointer + 1]); go(n, m, n_mask, pointer + 1); cap[2 * i] = 0; } } int wei[maxk]; int suma[1 << maxk]; int eptr; struct info { int u, v, w; } edges[maxm]; vector<int> adj[maxn]; void relabel(int n, int m) { sz = 0; qu[sz++] = 0; int pnt = 0; memset(level, -1, sizeof(level)); level[0] = 0; level[n - 1] = n - 1; while (pnt < sz) { int u = qu[pnt++]; for (auto v : adj[u]) { if (level[v] == -1) { level[v] = sz; qu[sz++] = v; } } } for (int i = 0; i < n; ++i) if (level[i] == -1) level[i] = sz++; for (int i = 0; i < m; ++i) { edges[i].u = level[edges[i].u]; edges[i].v = level[edges[i].v]; } } int main() { memset(head, -1, sizeof head); n = read(); m = read(); k = read(); q = read(); for (int i = 0; i < m; ++i) { int u, v, w; u = read(); v = read(); w = read(); u--; v--; edges[i] = {u, v, w}; adj[u].push_back(v); } relabel(n, m); for (int i = 0; i < m; ++i) { add_edge(edges[i].u, edges[i].v, edges[i].w); add_edge(edges[i].v, edges[i].u, 0); } masked[0] = dinic(0, n - 1, flow[0]); go(n, 2 * m, 0, 0); int top = (1 << k) - 1; for (int i = 0; i < q; ++i) { for (int j = 0; j < k; ++j) wei[j] = read(); int answer = masked[top]; for (int j = 1; j < (1 << k); j++) { int x = __builtin_ctz(j); suma[j] = suma[j ^ (1 << x)] + wei[x]; answer = min(answer, masked[top ^ j] + suma[j]); } printf( %d n , answer); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, nc, a[111], b[111]; string c[111]; struct Node { int lab; Node *left, *right; Node(int x) { lab = x; left = NULL; right = NULL; } }; void printfalse() { cout << IMPOSSIBLE ; exit(0); } Node *solve(int x, int y) { if (x > y) return NULL; if (x == y) return new Node(x); int l = -1, r = n + 1; for (int i = (1); i <= (nc); i++) { int u = a[i], v = b[i]; if (u == x) { if (c[i][0] == L ) { l = max(l, v); } else { r = min(r, v); } } } for (int s = (max(x, l)); s <= (min(y, r - 1)); s++) { bool ok = true; for (int i = (1); i <= (nc); i++) { int u = a[i], v = b[i]; if (x < min(u, v) && min(u, v) <= s && s < max(u, v)) { ok = false; } } if (!ok) continue; Node *r = new Node(x); r->left = solve(x + 1, s); r->right = solve(s + 1, y); return r; } printfalse(); } void print(Node *r) { if (r == NULL) return; print(r->left); cout << r->lab << ; print(r->right); } bool find(Node *u, int v) { if (u == NULL) return false; if (u->lab == v) return true; return find(u->left, v) || find(u->right, v); } void visit(Node *u) { if (u == NULL) return; for (int i = (1); i <= (nc); i++) if (a[i] == u->lab) { if (c[i][0] == L ) { if (!find(u->left, b[i])) printfalse(); } else { if (!find(u->right, b[i])) printfalse(); } } visit(u->left); visit(u->right); } int main() { cin >> n >> nc; for (int i = (1); i <= (nc); i++) { cin >> a[i] >> b[i] >> c[i]; } Node *r = solve(1, n); visit(r); print(r); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4BB_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SEDFXTP_PP_SYMBOL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sedfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_1_V
`define SKY130_FD_SC_HD__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_1_V
|
#include <bits/stdc++.h> using namespace std; long long a[27]; int main() { long long n; string s; cin >> n; cin >> s; long long c = 0, i, d; for (i = 0; i < (2 * n) - 2; i++) { if (s[i] >= a && s[i] <= z ) { d = s[i] - a ; a[d]++; } else { d = s[i] - A ; if (a[d] > 0) { a[d]--; } else { c++; } } } cout << c << endl; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; const long long oo = 1LL << 60; const long long kNumMoves = 4; const long long kMoves[kNumMoves][2] = {{1, 0}, {-1, 0}, {0, -1}, {0, 1}}; int n, v, e; vector<int> a, b; vector<vector<int> > conn, edges; vector<int> ansX, ansY, ansD; vector<int> topSort; vector<int> seen; void DFS_Topological(int node) { if (seen[node]) return; seen[node] = 1; for (int i = 0; i < int(n); ++i) { if (edges[node][i] && !seen[i]) { DFS_Topological(i); conn[node].push_back(i); conn[i].push_back(node); } } topSort.push_back(node); } int AddTransfusionStep(int src, int dest, int delta) { int mxMoveOut = min(a[src], delta); int mxMoveIn = min(v - a[dest], mxMoveOut); a[src] -= mxMoveIn; a[dest] += mxMoveIn; if (mxMoveIn) ansX.push_back(src + 1), ansY.push_back(dest + 1), ansD.push_back(mxMoveIn); return mxMoveIn; } int Transfuse_Out(int node, int dest, int delta) { if (!delta || seen[node] || seen[dest]) return 0; int step1 = AddTransfusionStep(node, dest, delta); if (step1 == delta) return delta; for (int i = 0; i < int(conn[dest].size()); ++i) { int newDest = conn[dest][i]; if (newDest == node) continue; if (seen[newDest]) continue; AddTransfusionStep(dest, newDest, v); Transfuse_Out(dest, newDest, v); AddTransfusionStep(dest, newDest, v); } int step2 = AddTransfusionStep(node, dest, delta - step1); return step1 + step2; } int Transfuse_In(int node, int dest, int delta) { if (!delta || seen[node] || seen[dest]) return 0; int step1 = AddTransfusionStep(dest, node, delta); if (step1 == delta) return delta; for (int i = 0; i < int(conn[dest].size()); ++i) { int newDest = conn[dest][i]; if (newDest == node) continue; if (seen[newDest]) continue; AddTransfusionStep(newDest, dest, v); Transfuse_In(dest, newDest, v); AddTransfusionStep(newDest, dest, v); } int step2 = AddTransfusionStep(dest, node, delta - step1); return step1 + step2; } bool Transfuse(int node) { int delta = a[node] - b[node]; if (delta > 0) { for (int i = 0; i < int(conn[node].size()); ++i) { int dest = conn[node][i]; if (seen[dest]) continue; delta -= Transfuse_Out(node, dest, delta); } return (delta == 0 && a[node] == b[node]); } else if (delta < 0) { delta = -delta; for (int i = 0; i < int(conn[node].size()); ++i) { int dest = conn[node][i]; if (seen[dest]) continue; delta -= Transfuse_In(node, dest, delta); } return (delta == 0 && a[node] == b[node]); } return true; } bool FindTransfusions() { seen.clear(); seen.resize(n, 0); for (int i = 0; i < int(n); ++i) DFS_Topological(i); seen.clear(); seen.resize(n, 0); for (int i = 0; i < int(n); ++i) { if (!Transfuse(topSort[i])) return false; seen[topSort[i]] = 1; } return true; } int main() { cin >> n >> v >> e; a.resize(n), b.resize(n); for (int i = 0; i < int(n); ++i) cin >> a[i]; for (int i = 0; i < int(n); ++i) cin >> b[i]; conn.resize(n); edges.resize(n, vector<int>(n, 0)); for (int i = 0; i < int(e); ++i) { int x, y; cin >> x >> y; --x, --y; edges[x][y] = edges[y][x] = 1; } if (FindTransfusions()) { cout << ansX.size() << endl; for (int i = 0; i < int(ansX.size()); ++i) cout << ansX[i] << << ansY[i] << << ansD[i] << endl; } else { cout << NO ; } int i; cin >> i; return 0; } |
#include <bits/stdc++.h> using namespace std; long long fast_power(long long x, long long y) { if (y == 0) return 1; long long temp = fast_power(x, y / 2); temp = ((temp % 1000000007) * (temp % 1000000007)) % 1000000007; if (y % 2 != 0) temp = ((temp % 1000000007) * (x % 1000000007)) % 1000000007; return temp; } long long f[1000001]; long long inv[1000001]; long long ncr(long long n, long long r) { return ((((f[n] % 1000000007) * (inv[n - r] % 1000000007)) % 1000000007) * inv[r]) % 1000000007; } long long nCr(long long n, long long r) { long long f = 1; long long x = 1; for (long long i = n; i > n - r; i--) { f *= i; f /= x++; } return f; } long long npr(long long n, long long r) { return (f[n] % 1000000007 * inv[n - r] % 1000000007) % 1000000007; } int main() { long long n, r, t; cin >> n >> r >> t; f[0] = 1; inv[0] = 1; for (long long i = 1; i <= n; i++) { f[i] = (f[i - 1] * i) % 1000000007; inv[i] = fast_power(f[i], 1000000007 - 2); } long long sum = 0; if (n >= 4) for (long long i = 4; i < t; i++) { if (t - i <= r) sum += nCr(n, i) * nCr(r, t - i); } cout << sum << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010; const double eps = 1e-8; int n, T, cnt1, cnt2; long double sum1; double sum2; struct water { int a, t; } A[N], B[N], Tmp[N]; bool cmp1(const water &a, const water &b) { return a.t < b.t; } bool cmp2(const water &a, const water &b) { return a.t > b.t; } int dcmp(long double x) { return (fabs(x) < eps) ? 0 : x < 0 ? -1 : 1; } int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) scanf( %d , &Tmp[i].a); for (int i = 1; i <= n; i++) scanf( %d , &Tmp[i].t); for (int i = 1; i <= n; i++) { if (Tmp[i].t <= T) A[++cnt1] = Tmp[i]; else B[++cnt2] = Tmp[i]; sum1 += 1ll * Tmp[i].a * Tmp[i].t; sum2 += Tmp[i].a; } sort(A + 1, A + cnt1 + 1, cmp1); sort(B + 1, B + cnt2 + 1, cmp2); if (!dcmp(sum1 / sum2 - T)) printf( %.8lf , sum2), exit(0); int flag = 0; if (dcmp(sum1 / sum2 - T) < 0) { for (int i = 1; i <= cnt1; i++) { long double del = (sum1 - T * sum2) / (A[i].t - T); if (dcmp(del - A[i].a) <= 0) { sum1 -= del * A[i].t; sum2 -= del; flag = 1; break; } else sum1 -= 1ll * A[i].a * A[i].t, sum2 -= A[i].a; } } else { for (int i = 1; i <= cnt2; i++) { long double del = (sum1 - T * sum2) / (B[i].t - T); if (dcmp(del - B[i].a) <= 0) { sum1 -= del * B[i].t; sum2 -= del; flag = 1; break; } else sum1 -= 1ll * B[i].a * B[i].t, sum2 -= B[i].a; } } if (flag) printf( %.8lf n , sum2); else puts( 0.000000 ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long scan_d() { char t = getchar(); long long you = 0; while (t > 9 || t < 0 ) t = getchar(); while (t <= 9 && t >= 0 ) { you *= 10; you += t - 0 ; t = getchar(); } return you; } long long dp[1050][1050]; long long op[1001]; int main() { for (int i = 0; i <= 1010; i++) dp[1][i] = 1; for (int i = 2; i <= 1010; i++) for (int o = i - 1; o <= 1010; o++) { dp[i][o] = dp[i - 1][o - 1] + dp[i][o - 1]; dp[i][o] %= 1000000007; } long long y; y = scan_d(); long long sum = 0; for (int i = 1; i <= y; i++) { op[i] = scan_d(); } long long ans = 1; for (int i = 1; i <= y; i++) { sum += op[i]; ans *= dp[op[i]][sum - 1]; ans %= 1000000007; } cout << ans << endl; } |
module Auto2(clock0,clock180,reset,leds,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock0;
input wire clock180;
input wire reset;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [7:0] alu_result;
wire swc_ready;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0,swc_ready}),
.ireg_2(8'h00),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
Auto2Rom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
Auto2RomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
Alu
alu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result));
Swc
swc (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.ready(swc_ready));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.leds(leds));
VGA1
vga (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[3]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // Auto2
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, n, k; cin >> t; while (t--) { long long ats = 0; cin >> n >> k; while (n) { ats += n % k; n -= n % k; while (n % k == 0 && n) n /= k, ats++; } cout << ats << n ; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 19:32:43 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_xlconstant_0_2 -prefix
// system_xlconstant_0_2_ system_xlconstant_0_2_sim_netlist.v
// Design : system_xlconstant_0_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_2
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_TB_V
`define SKY130_FD_SC_HD__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_TB_V
|
`default_nettype none
`timescale 1ns / 1ps
module joypad_snes_adapter(
input wire clock,
input wire reset,
// to gameboy
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
// to controller
input wire controller_data,
output wire controller_latch,
output wire controller_clock
);
////////////////////////////////////////////////////////
// http://www.gamefaqs.com/snes/916396-snes/faqs/5395
//
// Note: This implementation does *not* match the
// timings specified in the documentation above.
// Instead, it uses a much simpler and slower 1KHz
// clock which provides pretty good responsiveness
// to button presses. Also note that the Atlys board
// only provides a 3.3V Vcc instead of the spec'd 5V.
//
// Note: Color of wires on my controller ext. cable
// Vcc (+5V) - Green
// Clock - Blue
// Latch - Yellow
// Data - Red
// Ground - Brown
////////////////////////////////////////////////////////
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
//reg [15:0] button_state;
/**
* State transitions occur on the clock's positive edge.
*/
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
/**
* Button reading occurs on the negative edge to give
* values from the controller time to settle.
*/
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
// button order is
// B Y SELECT START UP DOWN LEFT RIGHT A X L R - - - -
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_es (
// hdmi interface
hdmi_clk,
hdmi_hs_de,
hdmi_vs_de,
hdmi_data_de,
hdmi_data);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input hdmi_hs_de;
input hdmi_vs_de;
input [(DATA_WIDTH-1):0] hdmi_data_de;
output [(DATA_WIDTH-1):0] hdmi_data;
// internal registers
reg hdmi_hs_de_d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
reg hdmi_hs_de_2d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
reg hdmi_hs_de_3d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
reg hdmi_hs_de_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_5d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data = 'd0;
// internal wires
wire [(DATA_WIDTH-1):0] hdmi_sav_s;
wire [(DATA_WIDTH-1):0] hdmi_eav_s;
// hdmi embedded sync insertion
assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
always @(posedge hdmi_clk) begin
hdmi_hs_de_d <= hdmi_hs_de;
case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
hdmi_hs_de_d, hdmi_hs_de})
5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}};
5'b10000: hdmi_data_d <= hdmi_eav_s;
default: hdmi_data_d <= hdmi_data_de;
endcase
hdmi_hs_de_2d <= hdmi_hs_de_d;
hdmi_data_2d <= hdmi_data_d;
hdmi_hs_de_3d <= hdmi_hs_de_2d;
hdmi_data_3d <= hdmi_data_2d;
hdmi_hs_de_4d <= hdmi_hs_de_3d;
hdmi_data_4d <= hdmi_data_3d;
hdmi_hs_de_5d <= hdmi_hs_de_4d;
hdmi_data_5d <= hdmi_data_4d;
case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d,
hdmi_hs_de_2d, hdmi_hs_de_d})
5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}};
5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}};
5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}};
5'b01111: hdmi_data <= hdmi_sav_s;
default: hdmi_data <= hdmi_data_5d;
endcase
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long dx[] = {-1, 0, 1, 0}; long long dy[] = {0, -1, 0, 1}; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> v(n); vector<long long> a; for (long long i = 0; i < n; i++) { cin >> v[i]; if (v[i] == 0) a.push_back(i); } for (long long i = 0; i < n; i++) { long long k = upper_bound(a.begin(), a.end(), i) - a.begin(); long long ans = abs(i - a[k]); if (k > 0) { ans = min(ans, abs(i - a[k - 1])); } cout << ans << ; } } |
#include <bits/stdc++.h> using namespace std; typedef pair<long long, long long> ll; typedef vector<long long> vl; typedef vector<ll> vll; typedef vector<vl> vvl; template <typename T> ostream &operator<<(ostream &o, vector<T> v) { if (v.size() > 0) o << v[0]; for (unsigned i = 1; i < v.size(); i++) o << << v[i]; return o << n ; } template <typename U, typename V> ostream &operator<<(ostream &o, pair<U, V> p) { return o << ( << p.first << , << p.second << ) ; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (unsigned i = 0; i < v.size(); i++) in >> v[i]; return in; } template <typename T> istream &operator>>(istream &in, pair<T, T> &p) { in >> p.first; in >> p.second; return in; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(20); long long k, b, n; cin >> k >> b >> n; vl a(n); cin >> a; map<long long, long long> ma; ma[0]++; long long tot = 0; long long ans = 0; long long z = 0; for (long long i = (0); i < (long long)n; i++) { tot += a[i]; tot %= (k - 1); if (a[i] == 0) z++; else z = 0; long long tmp = (tot + k - 1 - b) % (k - 1); if (b == k - 1 or b == 0) { if (b == 0) ans += z; else ans += ma[tmp] - z; } else ans += ma[tmp]; ma[tot]++; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long int x; cin >> x; cout << 25; } |
#include <bits/stdc++.h> using namespace std; int n, m; long long sum[1505][1505]; long long ans[1505]; long long t[1505]; int main() { int i, j, x; long long val, now, res; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) scanf( %I64d , &val), sum[i][j] = sum[i][j - 1] + val; for (i = 1; i <= m; i++) ans[i] = sum[1][i]; for (i = 2; i <= n; i++) { if (i % 2 == 0) { now = -(long long)1e15; for (x = m; x > 0; x--) { t[x] = now + sum[i][x]; now = max(now, ans[x]); } } else { now = -(long long)1e15; for (x = 1; x <= m; x++) { t[x] = now + sum[i][x]; now = max(now, ans[x]); } } for (x = 1; x <= m; x++) ans[x] = t[x]; } res = -(long long)1e15; for (x = 1; x <= m; x++) res = max(res, ans[x]); printf( %I64d , res); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_HH_T_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_HH_T_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_HH_T
);
localparam N = 5; // Para definir el número de bits del contador (hasta 23->5 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 5'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 10)
begin
if (enUP)
begin
if (q_act >= 5'd23) q_next = 5'd0;
else q_next = q_act + 5'd1;
end
else if (enDOWN)
begin
if (q_act == 5'd0) q_next = 5'd23;
else q_next = q_act - 5'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_HH_T = {digit1,digit0};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 0x3f3f3f3f; const long long llinf = 1e18; const long long nax = 0; long long n; vector<long long> arr(5005); vector<bool> ada(5005), masuk(5005); int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; for (int i = 0; i < n; ++i) { cin >> arr[i]; } sort(arr.begin(), arr.begin() + n); for (int i = 0; i < n; ++i) { if (masuk[i]) { continue; } for (int j = i + 1; j < n; ++j) { if (arr[j] <= arr[i]) continue; if (!ada[j]) { masuk[i] = 1, ada[j] = 1; break; } } } int ans = n; for (int i = 0; i < n; ++i) { if (masuk[i]) ans--; } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 7010; map<long long, int> cnt; int n; long long ar[N], br[N]; bitset<N> bit[N]; bitset<N> res; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i]; cnt[ar[i]]++; } for (int i = 1; i <= n; i++) { cin >> br[i]; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if ((ar[i] | ar[j]) == ar[i]) { bit[i][j] = 1; } else { bit[i][j] = 0; } } } for (int i = 1; i <= n; i++) { if (cnt[ar[i]] >= 2) { res = (res | bit[i]); } } long long ans = 0; for (int i = 1; i <= n; i++) { if (res[i]) { ans += br[i]; } } cout << ans << n ; return 0; } |
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_prbs_gen
*/
module test_lfsr_prbs_gen_prbs9;
// Parameters
parameter LFSR_WIDTH = 9;
parameter LFSR_POLY = 9'h021;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 0;
parameter INVERT = 0;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
enable
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_prbs_gen_prbs9.lxt");
$dumpvars(0, test_lfsr_prbs_gen_prbs9);
end
lfsr_prbs_gen #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.INVERT(INVERT),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, d, done[300005] = {0}; vector<int> graph[300005]; map<pair<int, int>, int> edge; set<int> p; void go() { queue<pair<int, int> > q; for (auto it : p) q.push({it, 0}); while (!q.empty()) { int x = q.front().first, P = q.front().second; q.pop(); if (done[x]) continue; done[x] = 1; for (auto it : graph[x]) { if (done[it] && it != P) printf( %d , edge[{min(x, it), max(x, it)}]); else if (it != P) q.push({it, x}); } } } int main() { scanf( %d , &n); scanf( %d , &k); scanf( %d , &d); for (__typeof(k) i = 0 - (0 > k); i != k - (0 > k); i += 1 - 2 * (0 > k)) { int x; scanf( %d , &x); p.insert(x); } for (__typeof(n - 1) i = 0 - (0 > n - 1); i != n - 1 - (0 > n - 1); i += 1 - 2 * (0 > n - 1)) { int u, v; scanf( %d , &u); scanf( %d , &v); graph[u].push_back(v); graph[v].push_back(u); edge[{min(u, v), max(u, v)}] = i + 1; } printf( %d n , (int)p.size() - 1); go(); printf( n ); return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// camctl.v: BCAM Controller //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// Controller / Mealy FSM
module camctl
( input clk , // clock / input
input rst , // global registers reset / input
input wEnb , // CAM write enable / input
input oldPattV , // is old (rewritten) pattern valid? / input from setram
input oldPattMultiOcc, // does old pattern has multi(other)-occurrences? / input from setram
input newPattMultiOcc, // does new pattern has multi(other)-occurrences? / input from setram
input oldEqNewPatt,
output reg wEnb_setram , // write enable to sets RAM / output to setram
output reg wEnb_idxram , // write enable to indices RAM / output to idxram
output reg wEnb_vacram , // write enable to vacancy RAM / output to vacram
output reg wEnb_indc , // write enable / full indicators MLABs / output to iitram9b
output reg wEnb_indx , // write enable / indicator index RAM / output to iitram9b
output reg wEnb_iVld , // write enable / indicator valid RAM / output to iitram9b
output reg wIVld , // write indicator validity / output to iitram9b
output reg oldNewbPattWr ); // old pattern / new pattern (inverted) write / output
// state declaration
reg [1:0] curStt, nxtStt ;
localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b10;
// synchronous process
always @(posedge clk, posedge rst)
if (rst) curStt <= S0 ;
else curStt <= nxtStt;
// combinatorial process
always @(*) begin
{wEnb_setram,wEnb_idxram,wEnb_vacram,wEnb_indc,wEnb_indx,wEnb_iVld,wIVld,oldNewbPattWr} = 8'h00;
case (curStt)
S0: nxtStt = wEnb?S1:S0; // idle; read RAM and generate status
S1: begin // delete old pattern
nxtStt = S2 ;
wEnb_indc = !(oldEqNewPatt && oldPattV) && oldPattV && oldPattMultiOcc;
wEnb_iVld = !(oldEqNewPatt && oldPattV) && oldPattV && !oldPattMultiOcc;
oldNewbPattWr = oldPattV ;
end
S2: begin // write new pattarn
nxtStt = S0 ;
wEnb_setram = !(oldEqNewPatt && oldPattV) && 1'b1 ;
// wEnb_idxram = !newPattMultiOcc ;
wEnb_idxram = !(oldEqNewPatt && oldPattV) && 1'b1 ;
wEnb_vacram = !(oldEqNewPatt && oldPattV) && (oldPattV && !oldPattMultiOcc) || !newPattMultiOcc;
wEnb_indc = !(oldEqNewPatt && oldPattV) && 1'b1 ;
wEnb_indx = !(oldEqNewPatt && oldPattV) && !newPattMultiOcc ;
wEnb_iVld = !(oldEqNewPatt && oldPattV) && !newPattMultiOcc ;
wIVld = 1'b1 ;
oldNewbPattWr = 1'b0 ;
end
endcase
end
endmodule
|
/****************************************
Mul Unit
- Booth Algorithm
- 32bit Adder
Make : 2010/12/07
Update :
****************************************/
`default_nettype none
module execute_mul_booth32(
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [63:0] oDATA,
output wire oHSF,
output wire oHOF,
output wire oHCF,
output wire oHPF,
output wire oHZF,
output wire oLSF,
output wire oLOF,
output wire oLCF,
output wire oLPF,
output wire oLZF
);
/****************************************
wire
****************************************/
wire [63:0] w_tmp_out;
wire [63:0] w0_tmp;
wire [63:0] w1_tmp;
wire [63:0] w2_tmp;
wire [63:0] w3_tmp;
wire [63:0] w4_tmp;
wire [63:0] w5_tmp;
wire [63:0] w6_tmp;
wire [63:0] w7_tmp;
wire [63:0] w8_tmp;
wire [63:0] w9_tmp;
wire [63:0] w10_tmp;
wire [63:0] w11_tmp;
wire [63:0] w12_tmp;
wire [63:0] w13_tmp;
wire [63:0] w14_tmp;
wire [63:0] w15_tmp;
wire [63:0] w16_tmp;
/****************************************
Booth - Encoder
****************************************/
assign w0_tmp = func_booth_algorithm(iDATA_0, iDATA_1[1], iDATA_1[0], 1'b0);
assign w1_tmp = func_booth_algorithm(iDATA_0, iDATA_1[3], iDATA_1[2], iDATA_1[1]);
assign w2_tmp = func_booth_algorithm(iDATA_0, iDATA_1[5], iDATA_1[4], iDATA_1[3]);
assign w3_tmp = func_booth_algorithm(iDATA_0, iDATA_1[7], iDATA_1[6], iDATA_1[5]);
assign w4_tmp = func_booth_algorithm(iDATA_0, iDATA_1[9], iDATA_1[8], iDATA_1[7]);
assign w5_tmp = func_booth_algorithm(iDATA_0, iDATA_1[11], iDATA_1[10], iDATA_1[9]);
assign w6_tmp = func_booth_algorithm(iDATA_0, iDATA_1[13], iDATA_1[12], iDATA_1[11]);
assign w7_tmp = func_booth_algorithm(iDATA_0, iDATA_1[15], iDATA_1[14], iDATA_1[13]);
assign w8_tmp = func_booth_algorithm(iDATA_0, iDATA_1[17], iDATA_1[16], iDATA_1[15]);
assign w9_tmp = func_booth_algorithm(iDATA_0, iDATA_1[19], iDATA_1[18], iDATA_1[17]);
assign w10_tmp = func_booth_algorithm(iDATA_0, iDATA_1[21], iDATA_1[20], iDATA_1[19]);
assign w11_tmp = func_booth_algorithm(iDATA_0, iDATA_1[23], iDATA_1[22], iDATA_1[21]);
assign w12_tmp = func_booth_algorithm(iDATA_0, iDATA_1[25], iDATA_1[24], iDATA_1[23]);
assign w13_tmp = func_booth_algorithm(iDATA_0, iDATA_1[27], iDATA_1[26], iDATA_1[25]);
assign w14_tmp = func_booth_algorithm(iDATA_0, iDATA_1[29], iDATA_1[28], iDATA_1[27]);
assign w15_tmp = func_booth_algorithm(iDATA_0, iDATA_1[31], iDATA_1[30], iDATA_1[29]);
assign w16_tmp = func_booth_algorithm(iDATA_0, 1'b0, 1'b0, iDATA_1[31]);
/****************************************
Booth - Exeout
****************************************/
assign w_tmp_out = w0_tmp + w1_tmp<<2 + w2_tmp<<4 + w3_tmp<<6 +
w4_tmp<<8 + w5_tmp<<10 + w6_tmp<<12 + w7_tmp<<14 +
w8_tmp<<16 + w9_tmp<<18 + w10_tmp<<20 + w11_tmp<<22 +
w12_tmp<<24 + w13_tmp<<26 + w14_tmp<<28 + w15_tmp<<30 + w16_tmp<<32;
function [63:0] func_booth_algorithm;
input [31:0] func_booth_algorithm_a;
input func_booth_algorithm_b2;
input func_booth_algorithm_b1;
input func_booth_algorithm_b0;
reg [2:0] reg_func_booth_algorithm_tmp;
reg [2:0] reg_func_booth_algorithm_cmd;
begin
reg_func_booth_algorithm_tmp = {func_booth_algorithm_b2, func_booth_algorithm_b1, func_booth_algorithm_b0};
case(reg_func_booth_algorithm_tmp)
3'h0 : reg_func_booth_algorithm_cmd = 3'h0;
3'h1 : reg_func_booth_algorithm_cmd = 3'h1;
3'h2 : reg_func_booth_algorithm_cmd = 3'h1;
3'h3 : reg_func_booth_algorithm_cmd = 3'h2;
3'h4 : reg_func_booth_algorithm_cmd = {1'b1, 2'h2};
3'h5 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
3'h6 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
default : reg_func_booth_algorithm_cmd = 3'h0;
endcase
if(reg_func_booth_algorithm_cmd[2] == 0)begin
//Plus
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a};
end
else begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a} << 1;
end
end
else begin
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = -{{32{1'b0}}, func_booth_algorithm_a};//(~{{32{1'b0}}, func_booth_algorithm_a}) + {{63{1'b0}}, 1'b1};
end
else begin
func_booth_algorithm = -({{32{1'b0}}, func_booth_algorithm_a} << 1);//(~({{32{1'b0}}, func_booth_algorithm_a} << 1)) + {{63{1'b0}}, 1'b1};
end
end
end
endfunction
/****************************************
Assign
****************************************/
assign oDATA = w_tmp_out;
assign oLSF = w_tmp_out[31];
assign oLCF = w_tmp_out[32];
assign oLOF = w_tmp_out[32] ^ w_tmp_out[31];
assign oLPF = w_tmp_out[0];
assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0;
assign oHSF = w_tmp_out[32];
assign oHCF = 1'b0;
assign oHOF = w_tmp_out[63];
assign oHPF = w_tmp_out[32];
assign oHZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int MX = 1147483646; const long long MX2 = 9223372036854775800; const int MOD = 1000000007; int p[30]; int find(int n) { if (p[n] < 0) return n; return p[n] = find(p[n]); } void uni(int e1, int e2) { e1 = find(e1); e2 = find(e2); if (e1 == e2) return; p[e1] = e2; return; } int main() { int n; scanf( %d , &n); char s1[100011], s2[100011]; vector<pair<int, int> > ans; fill(p, p + 30, -1); scanf( %s %s , s1, s2); int a1, a2; for (int i = 0; i < n; i++) { a1 = find(int(s1[i] - a )); a2 = find(int(s2[i] - a )); if (a1 != a2) { ans.push_back({a1, a2}); uni(a1, a2); } } printf( %d n , ans.size()); for (pair<int, int> x : ans) { printf( %c %c n , x.first + a , x.second + a ); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool func(deque<int>& v) { int x = v.back(); if (x > 1) { v.pop_back(); int y = x / 2; int y2 = x - y; if (y == 1) v.push_front(y); else v.push_back(y); if (y2 == 1) v.push_front(y2); else v.push_back(y2); return true; } return false; } void printv(deque<int>& v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } int main() { int k; int xyz[3]; cin >> xyz[0] >> xyz[1] >> xyz[2] >> k; sort(xyz, xyz + 3); deque<int> first, second, third; first.push_back(xyz[2]); second.push_back(xyz[1]); third.push_back(xyz[0]); int i = 0; while (i < k) { if (func(first)) i++; else break; if (i < k && func(second)) i++; if (i < k && func(third)) i++; } cout << (long long int)first.size() * second.size() * third.size(); } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module read data from the Audio ADC on the Altera DE2 board. *
* *
******************************************************************************/
module altera_up_audio_in_deserializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
done_channel_sync,
serial_audio_in_data,
read_left_audio_data_en,
read_right_audio_data_en,
// Bidirectionals
// Outputs
left_audio_fifo_read_space,
right_audio_fifo_read_space,
left_channel_data,
right_channel_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15;
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input done_channel_sync;
input serial_audio_in_data;
input read_left_audio_data_en;
input read_right_audio_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] left_audio_fifo_read_space;
output reg [ 7: 0] right_audio_fifo_read_space;
output [DW: 0] left_channel_data;
output [DW: 0] right_channel_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire valid_audio_input;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [ 6: 0] left_channel_fifo_used;
wire [ 6: 0] right_channel_fifo_used;
// Internal Registers
reg [DW: 0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_audio_fifo_read_space <= 8'h00;
else
begin
left_audio_fifo_read_space[7] <= left_channel_fifo_is_full;
left_audio_fifo_read_space[6:0] <= left_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_audio_fifo_read_space <= 8'h00;
else
begin
right_audio_fifo_read_space[7] <= right_channel_fifo_is_full;
right_audio_fifo_read_space[6:0] <= right_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_in_shift_reg <= 'h0;
else if (bit_clk_rising_edge & valid_audio_input)
data_in_shift_reg <=
{data_in_shift_reg[(DW - 1):0],
serial_audio_in_data};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_audio_bit_counter Audio_Out_Bit_Counter (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bit_clk_rising_edge),
.bit_clk_falling_edge (bit_clk_falling_edge),
.left_right_clk_rising_edge (left_right_clk_rising_edge),
.left_right_clk_falling_edge (left_right_clk_falling_edge),
// Bidirectionals
// Outputs
.counting (valid_audio_input)
);
defparam
Audio_Out_Bit_Counter.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
altera_up_sync_fifo Audio_In_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_falling_edge & ~left_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_left_audio_data_en & ~left_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_data)
);
defparam
Audio_In_Left_Channel_FIFO.DW = DW,
Audio_In_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Left_Channel_FIFO.AW = 6;
altera_up_sync_fifo Audio_In_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_rising_edge & ~right_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_right_audio_data_en & ~right_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_data)
);
defparam
Audio_In_Right_Channel_FIFO.DW = DW,
Audio_In_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Right_Channel_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 7; int n, m, q; vector<int> E[maxn]; int op[maxn], a[maxn], b[maxn], c[maxn]; int ans[maxn]; bitset<1001> Bit[1001]; bitset<1001> C; void dfs(int x) { if (x == 0) { for (int i = 0; i < E[x].size(); i++) { ans[E[x][i]] = ans[x]; dfs(E[x][i]); } } if (op[x] == 1) { int flag = 0; if (!Bit[a[x]][b[x]]) { flag = 1; ans[x]++; Bit[a[x]][b[x]] = 1; } for (int i = 0; i < E[x].size(); i++) { ans[E[x][i]] = ans[x]; dfs(E[x][i]); } if (flag) Bit[a[x]][b[x]] = 0; } if (op[x] == 2) { int flag = 0; if (Bit[a[x]][b[x]]) { flag = 1; ans[x]--; Bit[a[x]][b[x]] = 0; } for (int i = 0; i < E[x].size(); i++) { ans[E[x][i]] = ans[x]; dfs(E[x][i]); } if (flag) Bit[a[x]][b[x]] = 1; } if (op[x] == 3) { ans[x] = ans[x] - Bit[a[x]].count(); Bit[a[x]] ^= C; ans[x] = ans[x] + Bit[a[x]].count(); for (int i = 0; i < E[x].size(); i++) { ans[E[x][i]] = ans[x]; dfs(E[x][i]); } Bit[a[x]] ^= C; } if (op[x] == 4) { for (int i = 0; i < E[x].size(); i++) { ans[E[x][i]] = ans[x]; dfs(E[x][i]); } } } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) C[i] = 1; for (int i = 1; i <= q; i++) { scanf( %d , &op[i]); if (op[i] == 1) scanf( %d%d , &a[i], &b[i]); if (op[i] == 2) scanf( %d%d , &a[i], &b[i]); if (op[i] == 3) scanf( %d , &a[i]); if (op[i] == 4) scanf( %d , &a[i]), E[a[i]].push_back(i); else E[i - 1].push_back(i); } dfs(0); for (int i = 1; i <= q; i++) printf( %d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 2e5; int p[MAXN + 10], rub[MAXN + 10]; bool mark[MAXN + 10]; bool palin(int x) { stringstream sst; sst << x; string s; sst >> s; for (int i = 0; i < s.length(); i++) if (s[i] != s[s.length() - i - 1]) return false; return true; } int main() { ios::sync_with_stdio(false); rub[1] = 1; cerr << palin(121) << endl; long double a, b; cin >> a >> b; for (int i = 2; i <= MAXN; i++) { if (palin(i)) { rub[i] = rub[i - 1] + 1; } else rub[i] = rub[i - 1]; if (!mark[i]) { p[i] = p[i - 1] + 1; for (int j = i + i; j <= MAXN; j += i) mark[j] = true; } else p[i] = p[i - 1]; } long double x = a / b; int Max = 0; for (int i = 1; i <= MAXN; i++) if ((long double)p[i] / (long double)rub[i] <= x) Max = i; cout << Max << endl; return 0; } |
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ram
(
input clk,
input bclk,
input ena,
input bena,
input w,
input bw,
input [8:0] a,
input [8:0] ba,
input [31:0] d,
input [31:0] bd,
output reg [31:0] q,
output reg [31:0] bq
);
// 512 x 32 ram
reg [511:0] [31:0] r;
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
always @(posedge bclk)
begin
if(bena && bw)
r[ba] <= bd;
if(bena)
bq <= r[ba];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int DEBUG = 0; int main(int argc, char **argv) { DEBUG = (argc >= 2) ? atoi(argv[1]) : 0; int t; cin >> t; for (int c = 0; c < t; c++) { char tmp; int board[8][8]; int kx[2]; int ky[2]; int eger = 0; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { cin >> tmp; if (tmp == . ) { board[i][j] = 1; } else if (tmp == # ) { board[i][j] = 0; } else { kx[eger] = i; ky[eger] = j; board[i][j] = 1; eger++; } } } bool good = false; if ((kx[0] - kx[1] + 12) % 4 == 0 && (ky[0] - ky[1] + 12) % 4 == 0) { int v = (kx[0] + ky[0]) % 4; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { if (board[i][j] == 1 && (i + j) % 4 == v) { good = true; } } } } if (good) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O21A_BEHAVIORAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=8 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end//always
endmodule
//----------------------------------------------------------------------
module MUX4X1 #(parameter SIZE=32)
(
input wire[SIZE-1:0] iInput0,
input wire[SIZE-1:0] iInput1,
input wire[SIZE-1:0] iInput2,
input wire[SIZE-1:0] iInput3,
input wire[1:0] iSelect,
output reg[SIZE-1:0] oOutput
);
always @(*) begin
case (iSelect)
2'd0: oOutput=iInput0;
2'd1: oOutput=iInput1;
2'd2: oOutput=iInput2;
2'd3: oOutput=iInput3;
endcase
end
endmodule
//*********************************************************************
//RAM Controller
//*********************************************************************
module RAM_controller(
inout [15:0], // Input/Output port
output reg address [17:0], // Address
output reg CE, //Chip Select Enaeble (en cero)
output UB, //High Byte [16-bit data word] (en cero)
output LB,// Low byte [16-bit data word] (en cero)
output WE, //write-enable (en cero)
output OE //read-enable (en cero)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; long long a[maxn]; int n; long long k; long long d[maxn]; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); long long sum = 0; int num = 0; for (int i = 1; i <= n; i++) { d[i] = sum - (a[i] * (n - i) * (i - num - 1)); if (d[i] < k) { printf( %d n , i); num++; } else sum += a[i] * (i - num - 1); } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter SERDES = 1;
parameter MMCM = 1;
parameter MMCM_DEVICE_TYPE = 0;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clock and divided clock
input mmcm_rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal signals
wire clk_in_s;
// instantiations
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
generate
if (MMCM == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_mmcm_drp (
.clk (clk_in_s),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
if ((MMCM == 0) && (SERDES == 0)) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (clk));
assign div_clk = clk;
end
if ((MMCM == 0) && (SERDES == 1)) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_2_V
`define SKY130_FD_SC_HD__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_2_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_timer:1.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_timer_0_0 (
RST_N,
CLK,
BUS_WE,
BUS_ADDR,
BUS_WDATA,
BUS_RDATA,
EXPIRED
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_WE" *)
input wire BUS_WE;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_ADDR" *)
input wire [3 : 0] BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_WDATA" *)
input wire [31 : 0] BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_RDATA" *)
output wire [31 : 0] BUS_RDATA;
output wire EXPIRED;
fmrv32im_timer inst (
.RST_N(RST_N),
.CLK(CLK),
.BUS_WE(BUS_WE),
.BUS_ADDR(BUS_ADDR),
.BUS_WDATA(BUS_WDATA),
.BUS_RDATA(BUS_RDATA),
.EXPIRED(EXPIRED)
);
endmodule
|
#include<iostream> #include<algorithm> using namespace std; class node{ public: int a; int b; }; bool com(node a,node b){ return a.a<b.a; } int main(){ int times=0; cin>>times; while(times--){ int t=0; cin>>t; node *arr=new node[t+5](); for(int i=0;i<t;i++){ scanf( %d ,&arr[i].a); arr[i].b=i+1; } if(t==1){ cout<<arr[0].a<<endl; continue; } sort(arr,arr+t,com); bool fl=false; for(int i=0;i<t;i++){ if(i==0){ if(arr[i].a!=arr[i+1].a){ cout<<arr[i].b<<endl; fl=true; break; } } if(i==t-1){ if(arr[i].a!=arr[i-1].a){ cout<<arr[i].b<<endl; fl=true; break; } } if(arr[i].a!=arr[i+1].a&&arr[i].a!=arr[i-1].a){ cout<<arr[i].b<<endl; fl=true; break; } } if(!fl) cout<<-1<<endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> values; map<int, bool> reverseVisited; map<int, vector<int> > rev; stack<int> lastVisited; map<int, bool> visited; map<int, vector<int> > cities; void dfs(int init) { visited[init] = true; for (int i = 0; i < cities[init].size(); i++) { if (!visited[cities[init][i]]) { dfs(cities[init][i]); } } lastVisited.push(init); } void dfs2(int init, long long int &mini, long long int &ww) { reverseVisited[init] = true; if (mini > values[init]) mini = values[init], ww = 1; else if (mini == values[init]) ww++; for (int i = 0; i < rev[init].size(); i++) { if (!reverseVisited[rev[init][i]]) dfs2(rev[init][i], mini, ww); } } int main() { std::ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; i++) { int w; cin >> w; values[i] = w; } int m; cin >> m; while (m--) { int u, v; cin >> u >> v; cities[u].push_back(v); rev[v].push_back(u); visited[u] = false; reverseVisited[v] = false; } for (int i = 1; i <= n; i++) { if (!visited[i]) { dfs(i); } } long long int minMoney = 0, numWays = 1; while (!lastVisited.empty()) { long long int po = 1000000007; int q = lastVisited.top(); lastVisited.pop(); if (!reverseVisited[q]) { long long int ww = 0; dfs2(q, po, ww); minMoney += po; if (ww > 0) numWays *= ww; numWays %= 1000000007; } } cout << minMoney << << numWays << endl; } |
#include <bits/stdc++.h> using namespace std; long long getint() { char ch = getchar(); long long f = 1, x = 0; while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return f * x; } const int N = 200200; int n; struct dat { long long w, h, c; } a[N]; int bg[N], ed[N]; int cnt; int ans; bool operator<(const dat &a, const dat &b) { return (a.w == b.w) ? a.h < b.h : a.w < b.w; } long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } bool validate() { for (int i = 2; i <= cnt; i++) { if (ed[i] - bg[i] != ed[i - 1] - bg[i - 1]) return false; for (int j = bg[i], k = bg[i - 1]; j <= ed[i]; j++, k++) { if (a[j].h != a[k].h) return false; } long long g1, g2; for (int j = bg[i], k = bg[i - 1]; j < ed[i]; j++, k++) { g1 = gcd(a[j].c, a[j + 1].c); g2 = gcd(a[k].c, a[k + 1].c); if (a[j].c / g1 != a[k].c / g2 || a[j + 1].c / g1 != a[k + 1].c / g2) return false; } } return true; } void init() { n = getint(); for (int i = 1; i <= n; i++) { a[i].w = getint(); a[i].h = getint(); a[i].c = getint(); } sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { ++cnt; bg[cnt] = i; while (a[i].w == a[i + 1].w) i++; ed[cnt] = i; } } int main() { init(); if (!validate()) { puts( 0 ); return 0; } long long g = a[1].c; for (int i = 2; i <= n; i++) { g = gcd(g, a[i].c); } for (long long i = 1; i * i <= g; i++) { if (g % i == 0) { ans += (i * i == g) ? 1 : 2; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char** mat; short ***sparse, ***rem; void build() { sparse = new short**[n + 1]; rem = new short**[n + 1]; for (int i = 0; i <= n; ++i) { sparse[i] = new short*[m + 1]; rem[i] = new short*[m + 1]; } for (int i = 0; i <= n; ++i) { for (int j = 0; j <= m; ++j) { sparse[i][j] = new short[4]; memset(sparse[i][j], 0, sizeof(short) * 4); rem[i][j] = new short[4]; memset(rem[i][j], 0, sizeof(short) * 4); } } for (int i = 1; i <= n; ++i) { int prev = 0; for (int j = 1; j <= m; ++j) { if (mat[i][j]) { sparse[i][j][0] = prev; prev = j; } } prev = 0; for (int j = m; j > 0; --j) { if (mat[i][j]) { sparse[i][j][1] = prev; prev = j; } } } for (int j = 1; j <= m; ++j) { int prev = 0; for (int i = 1; i <= n; ++i) { if (mat[i][j]) { sparse[i][j][2] = prev; prev = i; } } prev = 0; for (int i = n; i > 0; --i) { if (mat[i][j]) { sparse[i][j][3] = prev; prev = i; } } } } void remove(int p, int q) { int prox, prev; prox = sparse[p][q][0]; prev = sparse[p][q][1]; if (prev) sparse[p][prev][0] = prox; if (prox) sparse[p][prox][1] = prev; rem[p][q][0] = prox; prox = sparse[p][q][1]; prev = sparse[p][q][0]; if (prev) sparse[p][prev][1] = prox; if (prox) sparse[p][prox][0] = prev; rem[p][q][1] = prox; prox = sparse[p][q][2]; prev = sparse[p][q][3]; if (prev) sparse[prev][q][2] = prox; if (prox) sparse[prox][q][3] = prev; rem[p][q][2] = prox; prox = sparse[p][q][3]; prev = sparse[p][q][2]; if (prev) sparse[prev][q][3] = prox; if (prox) sparse[prox][q][2] = prev; rem[p][q][3] = prox; } void insert(int p, int q) { int x; x = rem[p][q][0]; if (x) sparse[p][x][1] = q; x = rem[p][q][1]; if (x) sparse[p][x][0] = q; x = rem[p][q][2]; if (x) sparse[x][q][3] = p; x = rem[p][q][3]; if (x) sparse[x][q][2] = p; for (int i = 0; i < 4; ++i) rem[p][q][i] = 0; } int solve(int p, int q) { int tot = 0; stack<pair<int, int> > s; while (p and q) { int prox, prev; if (mat[p][q] == L ) { prox = sparse[p][q][0]; if (p and q) remove(p, q); if (p and q) s.push(make_pair(p, q)); q = prox; } else if (mat[p][q] == R ) { prox = sparse[p][q][1]; if (p and q) remove(p, q); if (p and q) s.push(make_pair(p, q)); q = prox; } else if (mat[p][q] == U ) { prox = sparse[p][q][2]; if (p and q) remove(p, q); if (p and q) s.push(make_pair(p, q)); p = prox; } else { prox = sparse[p][q][3]; if (p and q) remove(p, q); if (p and q) s.push(make_pair(p, q)); p = prox; } tot++; } while (s.size()) { pair<int, int> p = s.top(); s.pop(); insert(p.first, p.second); } return tot; } int main(int argc, char* argv[]) { cin >> n >> m; mat = new char*[n + 1]; for (int i = 0; i <= n; ++i) mat[i] = new char[m + 1]; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> mat[i][j]; if (mat[i][j] == . ) mat[i][j] = 0; } } build(); int ans = 0, freq = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { int x = mat[i][j] ? solve(i, j) : 0; if (x > ans) { ans = x; freq = 1; } else if (x == ans) freq++; } } cout << ans << << freq << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; long long c[200005]; int b[200005]; int a[100005]; void up(int n, int k) { if (!n) return; while (n <= 200000) { b[n]++; c[n] += k; k++; n <<= 1; } } void solve(int n) { int cur = 0; long long num = n * 2; up(num, 1); num = n; cur = 0; while (num) { if (num & 1) { up(num / 2 * 2, cur + 2); } b[num]++; c[num] += cur; num >>= 1; cur++; } } int main() { scanf( %d , &n); memset(c, 0, sizeof(c)); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); solve(a[i]); } long long res = 1000000000; for (int i = 0; i <= 200000; i++) { if (b[i] == n) { res = min(res, c[i]); } } printf( %lld n , res); } |
#include <bits/stdc++.h> using namespace std; int find(int a[], int n) { int max = 1; int m = a[1]; for (int i = 2; i < n; i++) { if (m <= a[i]) { max = i; m = a[i]; } } return max; } int main() { int c = 0; int n; cin >> n; int a[n]; cin >> a[0]; for (int i = 1; i < n; i++) { int temp; cin >> a[i]; } int m = 0; do { m = find(a, n); if (a[m] >= a[0]) { a[m]--; a[0]++; c++; } else break; } while (true); cout << c << n ; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const int mod = inf + 7; const double eps = 1e-9; const double pi = acos(-1.0); int n, ind = -1; int a[100100], b[100100]; pair<int, int> c[100100]; int v[100100], pos[100100]; vector<pair<int, int> > ans; bool is_happy(int x) { if (x == 0) return true; int c = x % 10; if (c != 4 && c != 7) return false; return is_happy(x / 10); } void sw(int x, int y) { if (x == y) return; ans.push_back(make_pair(x, y)); swap(a[x], a[y]); pos[a[x]] = x; pos[a[y]] = y; } int main() { cin >> n; for (int i = 0; i < n; i++) { scanf( %d , a + i); b[i] = a[i]; c[i] = make_pair(a[i], i); if (is_happy(a[i])) ind = i; } sort(b, b + n); bool ok = 1; for (int i = 0; i < n; i++) ok &= (a[i] == b[i]); if (ok) { printf( 0 n ); return 0; } if (ind == -1) { if (ok) printf( 0 n ); else printf( -1 n ); return 0; } sort(c, c + n); for (int i = 0; i < n; i++) a[c[i].second] = i; for (int i = 0; i < n; i++) pos[a[i]] = i; int x = a[ind]; for (int i = 0; i < n; i++) { if (i == x) continue; if (a[i] == i) continue; int target = pos[i]; sw(ind, i); ind = i; sw(ind, target); ind = target; } printf( %d n , (int)ans.size()); for (__typeof(ans.begin()) it = ans.begin(); it != ans.end(); it++) { printf( %d %d n , it->first + 1, it->second + 1); } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
);
input aclr;
input [55:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [55:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [55:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [55:0] q = sub_wire0[55:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 56,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "56"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "56"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "56"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 56 0 INPUT NODEFVAL "data[55..0]"
// Retrieval info: USED_PORT: q 0 0 56 0 OUTPUT NODEFVAL "q[55..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 56 0 data 0 0 56 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 56 0 @q 0 0 56 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XGMII control/data interleave
*/
module xgmii_interleave
(
input wire [63:0] input_xgmii_d,
input wire [7:0] input_xgmii_c,
output wire [72:0] output_xgmii_dc
);
assign output_xgmii_dc[7:0] = input_xgmii_d[7:0];
assign output_xgmii_dc[8] = input_xgmii_c[0];
assign output_xgmii_dc[16:9] = input_xgmii_d[15:8];
assign output_xgmii_dc[17] = input_xgmii_c[1];
assign output_xgmii_dc[25:18] = input_xgmii_d[23:16];
assign output_xgmii_dc[26] = input_xgmii_c[2];
assign output_xgmii_dc[34:27] = input_xgmii_d[31:24];
assign output_xgmii_dc[35] = input_xgmii_c[3];
assign output_xgmii_dc[43:36] = input_xgmii_d[39:32];
assign output_xgmii_dc[44] = input_xgmii_c[4];
assign output_xgmii_dc[52:45] = input_xgmii_d[47:40];
assign output_xgmii_dc[53] = input_xgmii_c[5];
assign output_xgmii_dc[61:54] = input_xgmii_d[55:48];
assign output_xgmii_dc[62] = input_xgmii_c[6];
assign output_xgmii_dc[70:63] = input_xgmii_d[63:56];
assign output_xgmii_dc[71] = input_xgmii_c[7];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
reg GSR;
task setGSR;
`ifdef ATTRIBUTES
/* verilator public */
`endif
input value;
GSR = value;
endtask
`else
`ifdef ATTRIBUTES
reg GSR /*verilator public*/;
`else
reg GSR;
`endif
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2'bxx;
// both inputs are z
#10 {A, B} = 2'bzz;
// one input is a zero
#10 {A, B} = 2'b0x;
#10 {A, B} = 2'bx0;
#10 {A, B} = 2'b0z;
#10 {A, B} = 2'bz0;
// one input is a one
#10 {A, B} = 2'b1x;
#10 {A, B} = 2'bx1;
#10 {A, B} = 2'b1z;
#10 {A, B} = 2'bz1;
// one input x, other z
#10 {A, B} = 2'bxz;
#10 {A, B} = 2'bzx;
// normal bit operands
#10 {A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2'bxx: gate_output = 1'bx;
// both inputs are z
2'bzz: gate_output = 1'bx;
// output should be zero (one input is a one)
2'b1x: gate_output = 0;
2'bx1: gate_output = 0;
2'b1z: gate_output = 0;
2'bz1: gate_output = 0;
// output is x (one input is a zero)
2'b0x: gate_output = 1'bx;
2'bx0: gate_output = 1'bx;
2'b0z: gate_output = 1'bx;
2'bz0: gate_output = 1'bx;
// inputs x, z
2'bxz: gate_output = 1'bx;
2'bzx: gate_output = 1'bx;
// normal operation on bit
2'b00: gate_output = 1;
2'b01: gate_output = 0;
2'b10: gate_output = 0;
2'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1e5 + 1; int n; int main() { scanf( %d , &n); n = abs(n); int i = 0; while (1) { int s = i * (i + 1); s /= 2; if (s >= n) { if (s % 2 && n % 2) { printf( %d , i); exit(0); } if (s % 2 == 0 && n % 2 == 0) { printf( %d , i); exit(0); } } i++; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module trace_cntrl_mul_32s_32s_32_7_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[32 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
reg signed [32 - 1 : 0] buff1;
reg signed [32 - 1 : 0] buff2;
reg signed [32 - 1 : 0] buff3;
reg signed [32 - 1 : 0] buff4;
assign p = buff4;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end
end
endmodule
`timescale 1 ns / 1 ps
module trace_cntrl_mul_32s_32s_32_7(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
trace_cntrl_mul_32s_32s_32_7_MulnS_0 trace_cntrl_mul_32s_32s_32_7_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = (3e5) + 10, mod = 1e9 + 7; int n, a[maxn]; map<int, int> mark; int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int ans = 0; int num = 0; for (int i = 0; i < n; i++) { if (a[i] > num) return cout << i + 1 << endl, 0; if (a[i] == num) num++; } cout << -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4_PP_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_PP_BLACKBOX_V
|
module step_ex_im(clk, rst_, ena_, rdy_,
r0_din, r0_dout, r0_we_,
immed, high);
input clk;
input rst_;
input ena_;
output rdy_;
output[7:0] r0_din;
input[7:0] r0_dout;
output r0_we_;
input[3:0] immed;
input high;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg r0_din_en;
assign r0_din = r0_din_en ?
high ? {immed, r0_dout[3:0]} : {r0_dout[7:4], immed} :
8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
r0_din_en <= 1;
r0_we_en <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
r0_din_en <= 1;
r0_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void DEBUG(vector<long long> a) { printf( { ); for (long long x : a) printf( %lld , x); printf( } n ); } int mod; void DEBUG(long long mask) { printf( mask: ); for (int i = 0; i < mod; ++i) printf( %d , (mask >> i) & 1); printf( n ); } struct TorSum { int n, m; long long** a; long long** pref; TorSum(){}; TorSum(long long** _a) : n(mod), m(mod) { a = new long long*[n]; for (int i = 0; i < n; ++i) { a[i] = new long long[m]; for (int j = 0; j < m; ++j) a[i][j] = _a[i][j]; } pref = new long long*[n + 1]; for (int i = 0; i <= n; ++i) { pref[i] = new long long[m + 1]; for (int x = 0; x < mod; ++x) pref[i][x] = 0; } for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) pref[i + 1][j + 1] = a[i][j] + pref[i + 1][j] + pref[i][j + 1] - pref[i][j]; } long long stupid(int lx, int rx, int ly, int ry) { if (lx == -1 || rx == -1 || ly == -1 || ry == -1) return 0; long long res = 0; for (int x = lx;; x = (x + 1) % n) { for (int y = ly;; y = (y + 1) % m) { res += a[x][y]; if (y == ry) break; } if (x == rx) break; } return res; } long long get_sum_safe(int lx, int rx, int ly, int ry) { return pref[rx][ry] - pref[rx][ly] - pref[lx][ry] + pref[lx][ly]; } long long get_sum(int lx, int rx, int ly, int ry) { if (lx == -1 || rx == -1 || ly == -1 || ry == -1) return 0; if (lx <= rx) { if (ly <= ry) { return get_sum_safe(lx, rx + 1, ly, ry + 1); } return get_sum_safe(lx, rx + 1, 0, m) - get_sum_safe(lx, rx + 1, ry + 1, ly); } else { if (ly <= ry) { return get_sum_safe(0, n, ly, ry + 1) - get_sum_safe(rx + 1, lx, ly, ry + 1); } return get_sum_safe(0, n, 0, m) - get_sum_safe(0, n, ry + 1, ly) - get_sum_safe(rx + 1, lx, 0, m) + get_sum_safe(rx + 1, lx, ry + 1, ly); } } }; int mlog(long long r, long long d) { int k = 0; for (long long pw = 1; pw <= r / d; ++k) pw *= d; return k; } long long mpow(long long x, int k) { long long res = 1; while (k--) res *= x; return res; } int a[66]; vector<pair<int, int>> split_segment(long long mask) { int n = mod; int cnt = 0; for (int i = 0; i < n; ++i) { a[i] = (mask >> i) & 1; cnt += a[i]; } if (cnt == 0) return {}; if (cnt == n) return {{0, n - 1}}; vector<pair<int, int>> res; for (int i = 0; i < n; ++i) { int l = i; while (l < n && !a[l]) ++l; if (l == n) break; int r = l; while (r < n && a[r]) ++r; res.push_back({l, r - 1}); i = r; } if (res[0].first == 0 && res.back().second == n - 1) { int r = res[0].second; int l = res.back().first; res.erase(res.begin()); res.erase(--res.end()); res.push_back({l, r}); } return res; } const int D = 22; const int MOD = 66; const int N = 30000; const int LOG = 16; using Zet = long long*; int d; int logn; int gen[D]; vector<int> big_gen; long long pwd[66]; long long jump[N][LOG]; pair<vector<pair<int, int>>, vector<pair<int, int>>> segments[N * D]; void add(Zet arr, Zet to_add, int shift) { for (int i = 0; i + shift < mod; ++i) arr[i] += to_add[i + shift]; for (int i = mod - shift; i < mod; ++i) arr[i] += to_add[i + shift - mod]; } Zet zeroes; unordered_map<long long, Zet> cnt; Zet get_cnt(long long r) { if (r <= 0) return zeroes; if (cnt.count(r)) return cnt[r]; Zet res = new long long[mod]; for (int x = 0; x < mod; ++x) res[x] = 0; int k = mlog(r, d); long long dk = mpow(d, k); if (dk == r) dk /= d; int i = 0; for (; r >= (i + 1) * dk; ++i) add(res, get_cnt(dk), (mod - gen[i]) % mod); add(res, get_cnt(r - i * dk), (mod - gen[i % d]) % mod); cnt[r] = res; return res; }; void inters(long long& mask1, long long mask2, int shift) { long long shift_mask = mask2 & ((1LL << shift) - 1); mask1 &= ((mask2 >> shift) | (shift_mask << (mod - shift))); } long long query(int l, int r, int pos) { long long res = (1LL << mod) - 1; while (l != r) { for (int i = logn;; --i) { if (l % pwd[i] == 0 && l + pwd[i] <= r) { inters(res, jump[pos][i], big_gen[l]); l += pwd[i]; pos += pwd[i]; break; } } } return res; }; unordered_map<long long, TorSum> solver; long long get_sum(long long R, int lx, int rx, int ly, int ry) { if (!solver.count(R)) { Zet* a = new Zet[mod]; for (int i = 0; i < mod; ++i) { a[i] = new long long[mod]; for (int x = 0; x < mod; ++x) a[i][x] = 0; } for (int i = 0; pwd[i] - 1 <= R; ++i) { for (int digit = 0; digit < d - 1; ++digit) { if (R < (digit + 1) * pwd[i] - 1) break; Zet kek = get_cnt((R - (digit + 1) * pwd[i] + 1) / pwd[i + 1] + 1); for (int r = 0; r < mod; ++r) a[(r + gen[digit] + i * gen[d - 1]) % mod] [(r + gen[digit + 1]) % mod] += kek[r]; } } solver[R] = TorSum(a); } return solver[R].get_sum(lx, rx, ly, ry); }; long long solve(long long R) { long long res = 0; for (int rem = 0; rem < pwd[logn] && rem <= R; ++rem) { vector<pair<int, int>>& v1 = segments[rem].first; vector<pair<int, int>>& v2 = segments[rem].second; for (auto& [lx, rx] : v1) for (auto& [ly, ry] : v2) res += get_sum((R - rem) / pwd[logn], lx, rx, ly, ry); } return res; }; int main() { scanf( %d %d , &d, &mod); for (int i = 0; i < d; ++i) scanf( %d , &gen[i]); int n; scanf( %d , &n); vector<int> a(n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); logn = 1; for (int i = 0; i < d; ++i) big_gen.push_back(gen[i]); for (; (int)(big_gen).size() < n; ++logn) { vector<int> new_big_gen; for (int i = 0; i < d; ++i) { for (int x : big_gen) new_big_gen.push_back((x + gen[i]) % mod); } big_gen = new_big_gen; } int pos = 0; pwd[pos] = 1; while (pwd[pos] < (long long)4e17) { long long x = d * pwd[pos]; pwd[++pos] = x; } int start, end; double time; start = clock(); for (int i = n - 1; i >= 0; --i) { jump[i][0] = (1LL << (a[i] + 1)) - 1; for (int k = 1; i + pwd[k] <= n; ++k) { jump[i][k] = (1LL << mod) - 1; for (int ii = 0; ii < d; ++ii) inters(jump[i][k], jump[i + ii * pwd[k - 1]][k - 1], gen[ii]); } } end = clock(); start = clock(); for (int rem = 0; rem <= pwd[logn] - n; ++rem) { long long draw = query(rem, rem + n, 0); segments[rem] = {split_segment(draw), {{0, mod - 1}}}; } end = clock(); start = clock(); for (int rem = pwd[logn] - n + 1; rem < pwd[logn]; ++rem) { long long draw1 = query(rem, pwd[logn], 0); long long draw2 = query(0, n - (pwd[logn] - rem), pwd[logn] - rem); segments[rem] = {split_segment(draw1), split_segment(draw2)}; } end = clock(); zeroes = new long long[mod]; for (int x = 0; x < mod; ++x) zeroes[x] = 0; cnt[0] = zeroes; Zet ozero = new long long[mod]; for (int x = 0; x < mod; ++x) ozero[x] = 0; ozero[0] = 1; cnt[1] = ozero; start = clock(); long long l, r; scanf( %lld %lld , &l, &r); --l; --r; printf( %lld n , solve(r - n + 1) - solve(l - 1)); end = clock(); } |
`include "hglobal.v"
`default_nettype none
module nd_fifo
#(parameter
FSZ=1, // 1, 2 or 4
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE)
(
`NS_DECLARE_GLB_CHNL(gch),
`NS_DECLARE_OUT_CHNL(snd0),
`NS_DECLARE_IN_CHNL(rcv0)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(gch_clk, gch_reset, snd0)
`NS_DEBOUNCER_REQ(gch_clk, gch_reset, rcv0)
localparam FIFO_IDX_WIDTH = ((($clog2(FSZ)-1) >= 0)?($clog2(FSZ)-1):(0));
reg [0:0] rg_rdy = `NS_OFF;
// out0 regs
`NS_DECLARE_REG_MSG(rgo0)
reg [0:0] rgo0_req = `NS_OFF;
reg [0:0] rgo0_busy = `NS_OFF;
// inp0 regs
reg [0:0] rgi0_ack = `NS_OFF;
// fifos
`NS_DECLARE_FIFO(bf0)
reg [0:0] added_hd = `NS_OFF;
always @(posedge gch_clk)
begin
if(gch_reset) begin
rg_rdy <= `NS_OFF;
end
if(! gch_reset && ! rg_rdy) begin
rg_rdy <= `NS_ON;
`NS_REG_MSG_INIT(rgo0)
rgo0_req <= `NS_OFF;
rgi0_ack <= `NS_OFF;
`NS_FIFO_INIT(bf0);
added_hd <= `NS_OFF;
end
if(! gch_reset && rg_rdy) begin
if(rcv0_ckd_req && (! rgi0_ack)) begin
`NS_FIFO_TRY_ADD_HEAD(bf0, rcv0, added_hd)
end
`NS_FIFO_ACK_ADDED_HEAD(bf0, rgi0_ack, added_hd)
`NS_FIFO_TRY_SET_OUT(bf0, rgo0, snd0_ckd_ack, rgo0_req, rgo0_busy);
if((! rcv0_ckd_req) && rgi0_ack) begin
rgi0_ack <= `NS_OFF;
end
end
end
assign gch_ready = rg_rdy;
//out1
`NS_ASSIGN_MSG(snd0, rgo0)
assign snd0_req_out = rgo0_req;
//inp0
assign rcv0_ack_out = rgi0_ack;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_2_V
`define SKY130_FD_SC_HDLL__MUX2_2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_2_V
|
#include <bits/stdc++.h> using namespace std; class segmentTree { public: int* tree; int N; int size; void update(int qidx, int val) { update(qidx, val, 0, N - 1, 0); } void update(int qidx, int val, int left, int right, int idx) { if (left == right && left == qidx) { tree[idx] = val; } else if (qidx >= left && qidx <= right) { int mid = (left + right) / 2; update(qidx, val, left, mid, 2 * idx + 1); update(qidx, val, mid + 1, right, 2 * idx + 2); tree[idx] = min(tree[2 * idx + 1], tree[2 * idx + 2]); } } int query(int qleft, int qright) { return query(qleft, qright, 0, N - 1, 0); } int query(int qleft, int qright, int left, int right, int index) { if (left >= qleft && right <= qright) return tree[index]; if (right < qleft || left > qright) return INT_MAX; int mid = (left + right) / 2; return min(query(qleft, qright, left, mid, 2 * index + 1), query(qleft, qright, mid + 1, right, 2 * index + 2)); } segmentTree(int n) { N = n; int start = 2; while ((start - 1) < 2 * N) start *= 2; size = start - 1; tree = new int[size]; memset(tree, -1, sizeof(int) * size); } }; const int MX = 1e5 + 69; int used[MX], used2[MX]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); memset(used, 0, sizeof used); memset(used2, 0, sizeof used2); int n; cin >> n; segmentTree tree = segmentTree(n + 1); int totmex = 1; vector<int> submex; for (int i = 0; i < n; i++) { int w; cin >> w; used[w]++; while (used[totmex]) totmex++; if (w != 1) { submex.push_back(1); } else { tree.update(1, i); continue; } int lastw = tree.query(w, w); int minbelow = tree.query(1, w - 1); if (minbelow > lastw) submex.push_back(w); tree.update(w, i); } for (int w = 2; w <= n; w++) { int lastw = tree.query(w, w); int minbelow = tree.query(1, w - 1); if (minbelow > lastw) submex.push_back(w); } submex.push_back(totmex); for (int v : submex) used2[v]++; for (int ans = 1; ans < 1e9; ans++) if (!used2[ans]) { cout << ans << n ; exit(0); } } |
// based on https://people.ece.cornell.edu/land/courses/ece5760/DE2/indexVGA.html
// dla simulation
module vgadla
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output wire [8:0] ledg,
output wire [17:0] ledr
);
localparam INIT = 0;
localparam TEST1 = 1;
localparam TEST2 = 2;
localparam TEST3 = 3;
localparam TEST4 = 4;
localparam TEST5 = 5;
localparam TEST6 = 6;
localparam DRAW = 7;
localparam UPDATE = 8;
localparam NEW = 9;
localparam FG = 16'hffff;
wire init;
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
wire xl, yl;
reg [9:0] xw, yw;
reg [30:0] xr;
reg [28:0] yr;
reg [19:0] addr;
reg [15:0] data;
reg [3:0] state;
reg [3:0] sum;
reg [8:0] ledg_;
reg [17:0] ledr_;
reg lock;
reg we;
assign sram_addr = addr;
// hi byte select enabled
assign sram_ub_n = 0;
// low byte select enabled
assign sram_lb_n = 0;
// chip enable
assign sram_ce_n = 0;
// output enable is overriden by WE
assign sram_oe_n = 0;
assign sram_we_n = we;
assign sram_dq = (we) ? 16'hzzzz : data;
// assign color based on contents of sram
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
assign xl = xr[27] ^ xr[30];
assign yl = yr[26] ^ yr[28];
assign init = ~key[0];
assign ledg = ledg_;
assign ledr = ledr_;
always @ (posedge vga_ctrl_clk) begin
if (init) begin
addr <= {x, y};
we <= 1'b0;
data <= 16'b0;
xr <= 31'h55555555;
yr <= 29'h55555555;
xw <= 10'd155;
yw <= 10'd120;
state <= INIT;
end
else if ((~vga_vs | ~vga_hs) & key[1]) begin
case (state)
// white dot at center of screen
INIT: begin
addr <= {10'd160,10'd120};
we <= 1'b0;
data <= FG;
state <= TEST1;
end
// read left neighbor
TEST1: begin
lock <= 1'b1;
sum <= 0;
we <= 1'b1;
addr <= {xw - 10'd1, yw};
state <= TEST2;
end
// check left and read right neighbor
TEST2: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw + 10'd1, yw};
state <= TEST3;
end
// check right and read top neighbor
TEST3: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw - 10'd1};
state <= TEST4;
end
// check top and read bottom neighbor
TEST4: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw + 10'd1};
state <= TEST5;
end
// read bottom neighbor
TEST5: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
state <= TEST6;
end
// if there is a neighbor draw, otherwise
// just update
TEST6: begin
if (lock & sum > 0) begin
ledr_ <= {4'b0, xw[9:0], sum[3:0]};
ledg_ <= {yw[8:0]};
state <= DRAW;
end
else begin
ledr_ <= 18'b0;
ledg_ <= 9'b0;
state <= UPDATE;
end
end
// draw white dot at that location
DRAW: begin
we <= 1'b0;
addr <= {xw, yw};
data <= FG;
state <= NEW;
end
// update walker and random
UPDATE: begin
we <= 1'b1;
if (xw < 10'd318 & xr[30] == 1)
xw <= xw + 1;
else if (xw > 10'd2 & xr[30] == 0)
xw <= xw - 1;
if (yw < 10'd237 & yr[28] == 1)
yw <= yw + 1;
else if (yw > 10'd2 & yr[28] == 0)
yw <= yw - 1;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
// begin a new phase
// init random walker
// and update random value
NEW: begin
we <= 1'b1;
if (xr[30])
xw <= 10'd318;
else
xw <= 10'd2;
if (yr[28])
yw <= 10'd238;
else
yw <= 10'd2;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
endcase
end
else begin
// not drawing lock writes
// and read from current x and y
// for color
lock <= 1'b0;
addr <= {x, y};
we <= 1'b1;
end
end
// delay a little before resetting the device for board to power up
reset_delay r0(
.clk(clk50),
.rst(rst)
);
// vga needs ~25 mhz for 640x480 at 60 hz
// c0 is the rate at which we update the vga signals at
// c1 is a phase delay of 90 degree which we output to the vga clock
// meaning vga clock gets clocked and updated a little later than we
// update the internal vga signals like sync rgb data
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
// vga controller that gets color from r, g, b
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
`timescale 1ns/1ns
module vgadla_test();
reg clk50;
reg [3:0] key;
reg [17:0] sw;
wire [15:0] sram_dq;
wire [19:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire vga_clk;
wire vga_hs;
wire vga_vs;
wire vga_blank;
wire vga_sync;
wire [7:0] vga_r;
wire [7:0] vga_g;
wire [7:0] vga_b;
wire [8:0] ledg;
wire [17:0] ledr;
initial begin
clk50 = 0;
key = 'hf;
sw = 0;
#5 key[0] = 0;
#12000 key[0] = 1;
end
always begin
#20 clk50 = ~clk50;
$monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",
$time, v.state, v.we, v.sram_dq, v.data, v.sum, v.xw, v.yw, v.xr, v.yr);
end
vgadla v(
.clk50(clk50),
.key(key),
.sw(sw),
.sram_dq(sram_dq),
.sram_addr(sram_addr),
.sram_ub_n(sram_ub_n),
.sram_lb_n(sram_lb_n),
.sram_we_n(sram_we_n),
.sram_ce_n(sram_ce_n),
.sram_oe_n(sram_oe_n),
.vga_clk(vga_clk),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.ledg(ledg),
.ledr(ledr)
);
endmodule |
#include <bits/stdc++.h> using namespace std; int px[4000010]; int py[4000010]; char c[2010][2010]; int n, m; bool pd(int x, int y, int d) { if (x < 0 || y < 0 || x + d >= n || y + d >= m) return false; for (int t = 1; t <= px[0]; t++) if ((px[t] != x) && (px[t] != x + d) && (py[t] != y) && (py[t] != y + d)) return false; for (int i = 0; i <= d; i++) { if (c[x + i][y] == . ) c[x + i][y] = + ; if (c[x][y + i] == . ) c[x][y + i] = + ; if (c[x + i][y + d] == . ) c[x + i][y + d] = + ; if (c[x + d][y + i] == . ) c[x + d][y + i] = + ; } for (int i = 0; i < n; i++) printf( %s n , c[i]); return true; } int main() { int i, j; scanf( %d%d , &n, &m); int x0 = n, x1 = -1, y0 = m, y1 = -1; px[0] = 0; py[0] = 0; for (i = 0; i < n; i++) { scanf( %s , c[i]); for (j = 0; j < m; j++) { if (c[i][j] == w ) { px[++px[0]] = i; py[++py[0]] = j; x0 = min(x0, i); x1 = max(x1, i); y0 = min(y0, j); y1 = max(y1, j); } } } if (px[0] > n * 4) { printf( -1 n ); return 0; } int d = max(x1 - x0, y1 - y0); if (pd(x0, y0, d)) return 0; if (pd(x0, max(y1 - d, 0), d)) return 0; if (pd(max(x1 - d, 0), y0, d)) return 0; printf( -1 n ); return 0; } |
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
module DE1_SoCRegTest (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output reg [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
wire clk;
reg [6:0] hold;
reg regWR;
wire [1:0] slowClk;
wire clkControl, rst, enterLow, enterHigh;
reg [4:0] readAdd0, readAdd1, writeAdd;
reg [31:0] writeData;
//reg [
wire [31:0] readOutput0, readOutput1;
//reg [15:0] data;
//assign data[6:0] <= SW[6:0]
assign clkControl = SW[8];
assign enterLow = SW[7];
assign enterHigh = SW[6];
assign rst = SW[9];
clkSlower counter(slowClk, CLOCK_50, rst);
registerFile regs(clk, readAdd0, readAdd1, writeAdd, regWR, writeData, readOutput0, readOutput1);
always @(posedge clk) begin
if(rst) begin
hold <= 0;
regWR <= 1;
LEDR <= 0;
end else if(enterLow) begin
regWR <= 0;
writeData <= 32'hFFFF0000 + hold[3:0];
writeAdd <= hold[3:0];
end else if(enterHigh) begin
regWR <= 0;
writeData <= 32'h0000FFF0 + hold[3:0];
writeAdd <= 5'b10000 + hold[3:0];
end else begin
regWR <= 1;
readAdd0 <= hold[3:0];
readAdd1 <= 16 + hold[3:0];
LEDR[7:0] <= KEY[0] ? readOutput1[7:0] : readOutput0[7:0];
end
hold <= hold + 1'b1;
end
assign clk = clkControl ? slowClk[0] : slowClk[1];
endmodule |
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/11/2016
Founction: pwm capture deal
Note:
****************************************************************************/
module pwm_capture(
pwm_input,clk,rst_n,enable,tx_start,tx_data,tx_complete,capture_tx_rst,bps_start_t
);
input pwm_input;
input clk;
input rst_n;
input enable;
input tx_complete;
input capture_tx_rst;
input bps_start_t;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] neg_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg[31:0] dutycyclecounter;
reg pos_counter_flag;
reg neg_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
wire neg_btn;
wire tx_end;
/*******************************************************************************
*counter
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n) begin
counter <= 'h0;
end
else if(enable) begin
counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0 ;
end
end
/*******************************************************************************
*Instance
*********************************************************************************/
neg_capture neg_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.neg_btn(neg_btn)
);
pos_capture pos_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.pos_btn(pos_btn)
);
captuer_tx captuer_tx_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready(ready),
.periodcounter(periodcounter),
.dutycyclecounter(dutycyclecounter),
.tx_data(tx_data),
.tx_complete(tx_complete),
.capture_tx_rst(capture_tx_rst),
.tx_end(tx_end),
.bps_start_t(bps_start_t)
);
/*******************************************************************************
*Capture pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
pos_counter <= 'h0;
pos_counter_flag <= 'h0;
end
else if(pos_btn && (pos_counter_flag != 1'b1))begin
pos_counter <= counter;
pos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture neg counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
neg_counter <= 'h0;
neg_counter_flag <= 'h0;
end
else if(neg_btn && pos_counter_flag && (neg_counter_flag != 1'b1))begin
neg_counter <= counter;
neg_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture next pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
nextpos_counter <= 'h0;
nextpos_counter_flag <= 'h0;
end
else if(pos_btn && pos_counter_flag && neg_counter_flag && (nextpos_counter_flag != 1'b1))begin
nextpos_counter <= counter;
nextpos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Calculate the dutycycle
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dutycyclecounter <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag)begin
dutycyclecounter <= neg_counter - pos_counter;
end
end
/*******************************************************************************
*Calculate the period
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
periodcounter <= 'h0;
ready <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag && nextpos_counter_flag)begin
periodcounter <= nextpos_counter - pos_counter;
ready <=(tx_end) ? 'h0:'h1;
end
end
endmodule |
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for typedefs using unpacked arrays (including dynamic arrays).
module unp_array_typedef();
typedef logic [7:0] bit_darray [];
typedef logic [15:0] bit_unparray [4];
typedef string string_darray [];
typedef string string_unparray [2];
typedef real real_darray [];
typedef real real_unparray [5];
typedef int int_darray [];
typedef int int_unparray [3];
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word;
typedef word word_darray [];
typedef word word_unparray [2];
bit_darray bit_darr;
bit_unparray bit_unparr;
string_darray string_darr;
string_unparray string_unparr;
real_darray real_darr;
real_unparray real_unparr;
int_darray int_darr;
int_unparray int_unparr;
// TODO at the moment dynamic arrays of struct are not supported
// word_darray word_darr;
word_unparray word_unparr;
initial begin
// Bit type
bit_darr = new[3];
bit_darr[0] = "a";
bit_darr[1] = "b";
bit_darr[2] = "c";
if(bit_darr[0] !== "a" || bit_darr[1] !== "b" || bit_darr[2] !== "c")
begin
$display("FAILED 1");
$finish();
end
bit_unparr[0] = 16'h1234;
bit_unparr[1] = 16'h5678;
bit_unparr[2] = 16'h9abc;
if(bit_unparr[0] !== 16'h1234 || bit_unparr[1] !== 16'h5678 || bit_unparr[2] !== 16'h9abc)
begin
$display("FAILED 2");
$finish();
end
// String type
string_darr = new[3];
string_darr[0] = "icarus";
string_darr[1] = "verilog";
string_darr[2] = "test";
if(string_darr[0] != "icarus" || string_darr[1] != "verilog" || string_darr[2] != "test") begin
$display("FAILED 3");
$finish();
end
string_unparr[0] = "test_string";
string_unparr[1] = "another test";
if(string_unparr[0] != "test_string" || string_unparr[1] != "another test") begin
$display("FAILED 4");
$finish();
end
// Real type
real_darr = new[3];
real_darr[0] = -1.20;
real_darr[1] = 2.43;
real_darr[2] = 7.4;
if(real_darr[0] != -1.20 || real_darr[1] != 2.43 || real_darr[2] != 7.4) begin
$display("FAILED 5");
$finish();
end
real_unparr[0] = 1.0;
real_unparr[1] = 2.5;
real_unparr[2] = 3.0;
real_unparr[3] = 4.5;
real_unparr[4] = 5.0;
if(real_unparr[0] != 1.0 || real_unparr[1] != 2.5 || real_unparr[2] != 3.0 ||
real_unparr[3] != 4.5 || real_unparr[4] != 5.0) begin
$display("FAILED 6");
$finish();
end
// Integer type
int_darr = new[3];
int_darr[0] = -3;
int_darr[1] = 3;
int_darr[2] = 72;
if(int_darr[0] !== -3 || int_darr[1] != 3 || int_darr[2] != 72) begin
$display("FAILED 7");
$finish();
end
int_unparr[0] = 22;
int_unparr[1] = 18;
int_unparr[2] = 9;
if(int_unparr[0] !== 22 || int_unparr[1] != 18 || int_unparr[2] != 9) begin
$display("FAILED 8");
$finish();
end
// Struct
// TODO at the moment dynamic arrays of struct are not supported
/* word_darr = new[3];
word_darr[0].high = 8'h11;
word_darr[0].low = 8'h22;
word_darr[1].high = 8'h33;
word_darr[1].low = 8'h44;
word_darr[2].high = 8'h55;
word_darr[2].low = 8'h66;
if(word_darr[0].low !== 8'h22 || word_darr[0].high !== 8'h11 ||
word_darr[1].low !== 8'h44 || word_darr[1].high !== 8'h33) begin
word_darr[2].low !== 8'h66 || word_darr[2].high !== 8'h55) begin
$display("FAILED 9");
$finish();
end*/
// TODO not available at the moment
//word_unparr[0].high = 8'haa;
//word_unparr[0].low = 8'h55;
//word_unparr[1].high = 8'h02;
//word_unparr[1].low = 8'h01;
//if(word_unparr[0].low !== 8'h55 || word_unparr[0].high !== 8'haa ||
//word_unparr[1].low !== 8'h01 || word_unparr[1].high !== 8'h02) begin
//$display("FAILED 10");
//$finish();
//end
word_unparr[0] = 16'haa55;
word_unparr[1] = 16'h0102;
if(word_unparr[0] !== 16'haa55 || word_unparr[1] !== 16'h0102)
begin
$display("FAILED 10");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, q; string s; int main() { cin >> n >> q; while (q--) { vector<pair<long long, long long> > v; long long x, l = 1, r = n, cur = n / 2 + 1; cin >> x >> s; while (cur != x) { v.push_back({l, r}); if (x < cur) { r = cur - 1; cur = (l + r) / 2; } else { l = cur + 1; cur = (l + r) / 2; } } for (int i = 0; i < s.size(); i++) { if (s[i] == U ) { if (!v.empty()) { l = v.back().first, r = v.back().second; cur = (l + r) / 2; v.pop_back(); } } if (s[i] == L ) { if (l != r) { v.push_back({l, r}); r = cur - 1; cur = (l + r) / 2; } } if (s[i] == R ) { if (l != r) { v.push_back({l, r}); l = cur + 1; cur = (l + r) / 2; } } } cout << cur << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, x; cin >> a >> b >> x; string s = ; if (a >= b) { s.push_back( 0 ); a--; } else { s.push_back( 1 ); b--; } while (x) { if (x == 1) { if (s.back() == 1 ) { while (b) s.push_back( 1 ), b--; while (a) s.push_back( 0 ), a--; } else { while (a) s.push_back( 0 ), a--; while (b) s.push_back( 1 ), b--; } } else if (s.back() == 1 ) { s.push_back( 0 ); a--; } else { s.push_back( 1 ); b--; } x--; } cout << s << endl; } |
#include <bits/stdc++.h> using namespace std; double eps = 1e-6; double pi = acos(0.0) * 2; double dinf = 1e250; long long INF = static_cast<long long>(2e18); long long inf = static_cast<long long>(1e9 + 7); long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <class T> void OUT(T a) { cout << a; exit(0); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long extgcd(long long a, long long b, long long& x, long long& y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = extgcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; for (long long i = 0; i < n; i++) { long long x, y, k; cin >> x >> y >> k; if (x < 0) x = -x; if (y < 0) y = -y; if (x < y) swap(x, y); if (x > k) cout << -1 << endl; else { if ((x & 1) != (y & 1)) { k -= 1; x -= 1; } else if ((x & 1) != (k & 1)) { x -= 1; y -= 1; k -= 2; } cout << k << endl; } } return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_demux
*/
module test_eth_demux_64_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
reg [M_COUNT-1:0] m_eth_hdr_ready = 0;
reg [M_COUNT-1:0] m_eth_payload_axis_tready = 0;
reg enable = 0;
reg drop = 0;
reg [1:0] select = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire [M_COUNT-1:0] m_eth_hdr_valid;
wire [M_COUNT*48-1:0] m_eth_dest_mac;
wire [M_COUNT*48-1:0] m_eth_src_mac;
wire [M_COUNT*16-1:0] m_eth_type;
wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire [M_COUNT-1:0] m_eth_payload_axis_tvalid;
wire [M_COUNT-1:0] m_eth_payload_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tid,
s_eth_payload_axis_tdest,
s_eth_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
enable,
drop,
select
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tid,
m_eth_payload_axis_tdest,
m_eth_payload_axis_tuser
);
// dump file
$dumpfile("test_eth_demux_64_4.lxt");
$dumpvars(0, test_eth_demux_64_4);
end
eth_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame outputs
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tid(m_eth_payload_axis_tid),
.m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Control
.enable(enable),
.drop(drop),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e5 + 13; long long root, sz[maxN], h[maxN], ans, val[maxN], m, n, pw[maxN], pre[maxN]; map<long long, long long> mp; vector<long long> vec; vector<pair<long long, long long>> adj[maxN]; bool mark[maxN], fl; void dfs(long long v, long long p) { sz[v] = 1; for (auto a : adj[v]) { long long u = a.first, w = a.second; if (u != p && !mark[u]) { dfs(u, v); sz[v] += sz[u]; } } } long long getpw(long long a, long long b) { long long ret = 1; for (; b; b >>= 1, a = 1ll * a * a % m) if (b & 1) ret = 1ll * ret * a % m; return ret; } void precomp() { pw[0] = 1; for (long long i = 1; i < n + 5; i++) pw[i] = pw[i - 1] * 10 % m; long long tmp = m, tot = m; for (long long p = 2; p * p <= tmp; p++) if (tmp % p == 0) { tot = tot / p * (p - 1); while (tmp % p == 0) tmp /= p; } if (tmp > 1) tot = tot / tmp * (tmp - 1); pre[0] = 1; pre[1] = getpw(10, tot - 1); for (long long i = 2; i < n + 5; i++) pre[i] = 1ll * pre[i - 1] * pre[1] % m; } void du(long long v, long long p) { for (auto a : adj[v]) { long long u = a.first, w = a.second; if (u != p && !mark[u]) { h[u] = h[v] + 1; val[u] = ((val[v]) + w * pw[h[v]]) % m; if (val[u] == 0) ans++; du(u, v); } } } void dd(long long v, long long p, long long cur) { if (v != root) vec.push_back(v); reverse(adj[v].begin(), adj[v].end()); for (auto a : adj[v]) { long long u = a.first, w = a.second; if (u != p && !mark[u]) { long long nwcur = (cur * 10 + w) % m; long long wnt = ((1ll * pre[h[u]] * ((-nwcur) % m + m)) + m) % m; ans += mp[wnt]; dd(u, v, nwcur); if (nwcur == 0 && fl) ans++; if (v == root) { while (vec.size()) { long long u = vec.back(); vec.pop_back(); mp[val[u]]++; } } } } } void calc(long long v) { long long tmp = ans; h[v] = 0; val[v] = 0; du(v, -1); mp.clear(); fl = 0; dd(v, -1, 0); mp.clear(); fl = 1; dd(v, -1, 0); } void solve(long long v) { dfs(v, -1); root = v; long long p = -1; bool fl = true; while (fl) { fl = false; for (auto a : adj[v]) { long long u = a.first; if (!mark[u] && u != p && sz[u] > sz[root] / 2) { p = v; v = u; fl = true; break; } } } mark[v] = true; root = v; calc(v); for (auto a : adj[v]) { long long u = a.first; if (!mark[u]) solve(u); } } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; precomp(); for (long long i = 0; i < n - 1; i++) { long long a, b, w; cin >> a >> b >> w; a++; b++; w %= m; adj[a].push_back({b, w}); adj[b].push_back({a, w}); } solve(1); cout << ans << endl; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule
|
#include <bits/stdc++.h> int main() { int d1, d2, d3, sum = 0; scanf( %d%d%d , &d1, &d2, &d3); if (d1 >= d2) { sum += d2; } else { sum += d1; } if (d1 + d2 >= d3) { sum += d3; } else { sum += d1 + d2; } if ((d1 >= d2) && (d1 <= d2 + d3)) { sum += d1; } else if ((d1 >= d2) && (d1 > d2 + d3)) { sum += d2 + d3; } else if ((d2 >= d1) && (d2 <= d1 + d3)) { sum += d2; } else { sum += d1 + d3; } printf( %d , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200001; int cs1[N]; int cs2[N]; int ss1[N]; int ss2[N]; int sum(int i, int cs[]) { int s = 0; while (i > 0) { s += cs[i]; i -= i & -i; } return s; } void add(int i, int k, int cs[]) { while (i < N) { cs[i] += k; i += i & -i; } } int main() { int n, k, a, b, q; cin >> n >> k >> a >> b >> q; for (int i = 0; i < q; ++i) { int c; scanf( %d , &c); if (c == 1) { int d, aa; scanf( %d%d , &d, &aa); add(d, min(aa, b - ss1[d]), cs1); add(d, min(aa, a - ss2[d]), cs2); ss1[d] = min(ss1[d] + aa, b); ss2[d] = min(ss2[d] + aa, a); } else { int p; scanf( %d , &p); int o = sum(n, cs2) - sum(p + k - 1, cs2) + sum(p - 1, cs1); printf( %d n , o); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvp (
VPWR,
VGND,
Z ,
A ,
TE
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE ;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; pair<int, int> a[105]; for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i + 1; } sort(a, a + n); for (int i = 0; i < n / 2; i++) cout << a[i].second << << a[n - i - 1].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)4e18; int n, q; long long c[110000]; long long v[110000]; long long d[110000]; int u[110000]; int main() { ios::sync_with_stdio(0); cin >> n >> q; for (int i = 0; i < n; ++i) cin >> v[i]; for (int i = 0; i < n; ++i) cin >> c[i]; while (q--) { long long a, b; cin >> a >> b; for (int i = 0; i <= n; ++i) d[i] = -inf; long long et = 0; pair<long long, int> m1 = make_pair(-inf, -1); pair<long long, int> m2 = make_pair(-inf, -1); for (int i = 0; i < n; ++i) { long long ans = max(v[i] * b, d[c[i]]); ans = max(ans, d[c[i]] + v[i] * a); if (m1.second != c[i]) ans = max(ans, m1.first + v[i] * b); else ans = max(ans, m2.first + v[i] * b); if (ans > m1.first) if (m1.second != c[i]) m2 = m1, m1 = make_pair(ans, c[i]); else m1.first = ans; else if (ans > m2.first && c[i] != m1.second) m2 = make_pair(ans, c[i]); d[c[i]] = max(d[c[i]], ans); et = max(et, ans); } cout << et << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int t, a, b, c, d, k; cin >> t; while (t--) { cin >> a >> b >> c >> d >> k; int pen = (a + c - 1) / c; int penc = (b + d - 1) / d; if (pen + penc <= k) cout << pen << << penc << endl; else cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int P = 998244353, INF = 0x3f3f3f3f; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long qpow(long long a, long long n) { long long r = 1 % P; for (a %= P; n; a = a * a % P, n >>= 1) if (n & 1) r = r * a % P; return r; } long long inv(long long first) { return first <= 1 ? 1 : inv(P % first) * (P - P / first) % P; } inline int rd() { int first = 0; char p = getchar(); while (p < 0 || p > 9 ) p = getchar(); while (p >= 0 && p <= 9 ) first = first * 10 + p - 0 , p = getchar(); return first; } const int N = 1e6 + 10; int n, m, a[N], w[N], s1, s0; int in[N]; int dp[55][55][55]; int solve(int a, int w) { memset(dp, 0, sizeof dp); dp[0][0][0] = 1; int ans = 0; if (a) { for (int i = 1; i <= m + 1; ++i) for (int j = 0; j <= i - 1; ++j) for (int k = 0; k <= j; ++k) if (dp[i - 1][j][k]) { int &r = dp[i - 1][j][k]; int now = w + k, tot = s1 + s0 + j - (i - 1 - j), p = (long long)now * in[tot] % P; dp[i][j + 1][k + 1] = (dp[i][j + 1][k + 1] + (long long)p * r) % P; now = s1 - w + j - k, p = (long long)now * in[tot] % P; dp[i][j + 1][k] = (dp[i][j + 1][k] + (long long)p * r) % P; now = s0 - (i - 1 - j), p = (long long)now * in[tot] % P; dp[i][j][k] = (dp[i][j][k] + (long long)p * r) % P; if (i - 1 == m) ans = (ans + (long long)(w + k) * r) % P; } return ans; } for (int i = 1; i <= m + 1; ++i) for (int j = 0; j <= i - 1; ++j) for (int k = 0; k <= min(w, j); ++k) if (dp[i - 1][j][k]) { int &r = dp[i - 1][j][k]; int now = w - k, tot = s0 + s1 - j + (i - 1 - j), p = (long long)now * in[tot] % P; dp[i][j + 1][k + 1] = (dp[i][j + 1][k + 1] + (long long)p * r) % P; now = s1 + (i - 1 - j), p = (long long)now * in[tot] % P; dp[i][j][k] = (dp[i][j][k] + (long long)p * r) % P; now = s0 - w - j + k, p = (long long)now * in[tot] % P; dp[i][j + 1][k] = (dp[i][j + 1][k] + (long long)p * r) % P; if (i - 1 == m) ans = (ans + (long long)(w - k) * r) % P; } return ans; } int main() { in[0] = 1; for (int i = 1; i <= N - 1; ++i) in[i] = inv(i); scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , a + i); for (int i = 1; i <= n; ++i) { scanf( %d , w + i); if (a[i]) s1 += w[i]; else s0 += w[i]; } for (int i = 1; i <= n; ++i) printf( %d n , solve(a[i], w[i])); } |
#include <bits/stdc++.h> using namespace std; set<string> ss; string s; void readInput() { cin >> s; } void solve() { for (int i = 0; i <= s.length(); i++) { for (char c = a ; c <= z ; c++) { string tmp; tmp += s.substr(0, i) + c + s.substr(i, s.length()); ss.insert(tmp); } } cout << ss.size(); } int main() { readInput(); solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc = 0;
int x = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
x = 32'hcafe1234;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
x = cyc;
$write("[%0t] cyc=%0d x=%x\n", $time, cyc, x);
if (x !== cyc) $stop;
if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const double EPS = 1e-6; const string alpha = abcdefghijklmnopqrstuvwxyz ; const long long INFINF = 1e18; const int INF = 1e9; const int maxN = 1e6; int T; void tc() { int N; cin >> N; string second = ; int d = 0; for (int i = 0; i < N; i++) { if (d < N) { second += 8 ; d += 4; } else { second += 9 ; } } reverse(second.begin(), second.end()); cout << second << endl; } int main() { cin >> T; while (T--) { tc(); } } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module bt656cap_colorspace(
input vid_clk,
input stb_i,
input field_i,
input [31:0] ycc422,
output reg stb_o,
output reg field_o,
output [31:0] rgb565
);
/* Datapath */
wire signed [7:0] cb = ycc422[31:24] - 8'd128;
wire signed [7:0] y0 = ycc422[23:16] - 8'd128;
wire signed [7:0] cr = ycc422[15: 8] - 8'd128;
wire signed [7:0] y1 = ycc422[ 7: 0] - 8'd128;
reg mult_sela;
reg [1:0] mult_selb;
wire signed [7:0] mult_opa = mult_sela ? cr : cb;
reg signed [9:0] mult_opb;
always @(*) begin
case(mult_selb)
2'd0: mult_opb = 10'd359; // 1.402
2'd1: mult_opb = 10'd454; // 1.772
2'd2: mult_opb = 10'd88; // 0.344
2'd3: mult_opb = 10'd183; // 0.714
endcase
end
reg signed [17:0] mult_result;
wire signed [9:0] mult_result_t = mult_result[17:8];
always @(posedge vid_clk) mult_result <= mult_opa*mult_opb;
reg signed [9:0] int_r0;
reg signed [9:0] int_g0;
reg signed [9:0] int_b0;
reg signed [9:0] int_r1;
reg signed [9:0] int_g1;
reg signed [9:0] int_b1;
reg load_y;
reg add_r;
reg sub_g;
reg add_b;
always @(posedge vid_clk) begin
if(load_y) begin
int_r0 <= y0;
int_g0 <= y0;
int_b0 <= y0;
int_r1 <= y1;
int_g1 <= y1;
int_b1 <= y1;
end
if(add_r) begin
int_r0 <= int_r0 + mult_result_t;
int_r1 <= int_r1 + mult_result_t;
end
if(sub_g) begin
int_g0 <= int_g0 - mult_result_t;
int_g1 <= int_g1 - mult_result_t;
end
if(add_b) begin
int_b0 <= int_b0 + mult_result_t;
int_b1 <= int_b1 + mult_result_t;
end
end
/* Output generator */
reg fsm_stb;
reg fsm_field;
wire signed [9:0] fsm_r0 = int_r0;
wire signed [9:0] fsm_g0 = int_g0 - mult_result_t;
wire signed [9:0] fsm_b0 = int_b0;
wire signed [9:0] fsm_r1 = int_r1;
wire signed [9:0] fsm_g1 = int_g1 - mult_result_t;
wire signed [9:0] fsm_b1 = int_b1;
reg [7:0] out_r0;
reg [7:0] out_g0;
reg [7:0] out_b0;
reg [7:0] out_r1;
reg [7:0] out_g1;
reg [7:0] out_b1;
always @(posedge vid_clk) begin
stb_o <= 1'b0;
if(fsm_stb) begin
stb_o <= 1'b1;
field_o <= fsm_field;
out_r0 <= (fsm_r0[7:0] | {8{fsm_r0[8]}}) & {8{~fsm_r0[9]}};
out_g0 <= (fsm_g0[7:0] | {8{fsm_g0[8]}}) & {8{~fsm_g0[9]}};
out_b0 <= (fsm_b0[7:0] | {8{fsm_b0[8]}}) & {8{~fsm_b0[9]}};
out_r1 <= (fsm_r1[7:0] | {8{fsm_r1[8]}}) & {8{~fsm_r1[9]}};
out_g1 <= (fsm_g1[7:0] | {8{fsm_g1[8]}}) & {8{~fsm_g1[9]}};
out_b1 <= (fsm_b1[7:0] | {8{fsm_b1[8]}}) & {8{~fsm_b1[9]}};
end
end
assign rgb565 = {out_r0[7:3], out_g0[7:2], out_b0[7:3],
out_r1[7:3], out_g1[7:2], out_b1[7:3]};
/* Forward field */
always @(posedge vid_clk) begin
if(stb_i)
fsm_field <= field_i;
end
/* Controller */
reg [2:0] state;
reg [2:0] next_state;
parameter S1 = 3'd0;
parameter S2 = 3'd1;
parameter S3 = 3'd2;
parameter S4 = 3'd3;
parameter S5 = 3'd4;
initial state = S1;
always @(posedge vid_clk) begin
state <= next_state;
//$display("state: %d->%d (%d)", state, next_state, stb_i);
end
always @(*) begin
mult_sela = 1'bx;
mult_selb = 2'bx;
load_y = 1'b0;
add_r = 1'b0;
sub_g = 1'b0;
add_b = 1'b0;
fsm_stb = 1'b0;
next_state = state;
case(state)
S1: begin
load_y = 1'b1;
mult_sela = 1'b1; // 1.402*Cr
mult_selb = 2'd0;
if(stb_i)
next_state = S2;
end
S2: begin
add_r = 1'b1;
mult_sela = 1'b0; // 1.772*Cb
mult_selb = 2'd1;
next_state = S3;
end
S3: begin
add_b = 1'b1;
mult_sela = 1'b0; // 0.344*Cb
mult_selb = 2'd2;
next_state = S4;
end
S4: begin
sub_g = 1'b1;
mult_sela = 1'b1; // 0.714*Cr
mult_selb = 2'd3;
next_state = S5;
end
S5: begin
fsm_stb = 1'b1;
load_y = 1'b1;
mult_sela = 1'b1; // 1.402*Cr
mult_selb = 2'd0;
if(stb_i)
next_state = S2;
else
next_state = S1;
end
endcase
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 1ns / 1ns
module U1 (OUT);
parameter VALUE = -384;
output [9:0] OUT;
assign OUT = VALUE;
endmodule
module U2 (OUT);
parameter VALUE = 96;
output [9:0] OUT;
assign OUT = VALUE;
endmodule
module main;
wire [9:0] out1, out2;
U1 u1 (out1);
U2 u2 (out2);
initial #1 begin
if (out1 !== 10'h280) begin
$display("FAILED -- out1 = %b", out1);
$finish;
end
if (out2 !== 10'h060) begin
$display("FAILED -- out2 = %b", out2);
$finish;
end
$display("PASSED");
end // initial #1
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <>
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
wire dummy;
AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY"))
adder_cin (
.a(CI),
.b(1'b0),
.c(1'b0),
.o({CIx, dummy})
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
AL_MAP_ADDER #(
.ALUTYPE("ADD")
) adder_i (
.a(AA[i]),
.b(BB[i]),
.c(C[i]),
.o({COx[i],Y[i]})
);
wire cout;
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.a(1'b0),
.b(1'b0),
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
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