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#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int r = 0; for (int i = 1; i < 300; i++) { int x1 = a / i; int x2 = b / i; if (x1 + x2 >= n && x1 != 0 && x2 != 0) r = i; } cout << r; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const long long N = 5e3 + 5; long long a[N]; long long pre[N]; long long dp[N][N]; long long n, m, k; long long check = 0; long long go(long long pos, long long kk) { if (kk == k) return 0; if (pos == n + 1) return -1e15; long long &ans = dp[pos][kk]; if (ans != -1) return ans; ans = go(pos + 1, kk); if (pos + m - 1 <= n) { ans = max(ans, pre[pos + m - 1] - pre[pos - 1] + go(pos + m, kk + 1)); } return ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (long long i = 1; i <= n; i++) { cin >> a[i]; pre[i] = pre[i - 1] + a[i]; } memset(dp, -1, sizeof(dp)); cout << go(1, 0) << endl; }
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/*
* NAME
* ----
*
* 8-bit grey code generator
*
* DESIGN
* ------
*
* There are two main components to this counter.
*
* The first is the special cases at the start of
* each sequence. The first bit changes at sequence 1,
* second at 2, third at 4, etc.
*
* The second is the repeating sequence after the
* special cases.
* The first bit changes every 2 bits, the second
* every 4, the third every 8, fourth every 16, etc.
* (Do you see a pattern yet?)
*
* The modulo operator is used by subtracting the offset
* and checking if the required number of numbers has
* changed.
*
* This design could be easily expanded to any number of bits.
*/
module grey_counter(input clk, output reg [7:0] count);
reg [7:0] n; // 8-bit counter
always @(posedge clk) begin
if (0 == n)
count <= 8'b00000000;
else if (1 == n)
count[0] <= 1;
else if (2 == n)
count[1] <= 1;
else if (4 == n)
count[2] <= 1;
else if (8 == n)
count[3] <= 1;
else if (16 == n)
count[4] <= 1;
else if (32 == n)
count[5] <= 1;
else if (64 == n)
count[6] <= 1;
else if (128 == n)
count[7] <= 1;
else if (0 == (n - 1) % 2)
count[0] <= ~count[0];
else if (0 == (n - 2) % 4)
count[1] <= ~count[1];
else if (0 == (n - 4) % 8)
count[2] <= ~count[2];
else if (0 == (n - 8) % 16)
count[3] <= ~count[3];
else if (0 == (n - 16) % 32)
count[4] <= ~count[4];
else if (0 == (n - 32) % 64)
count[5] <= ~count[5];
else if (0 == (n - 64) % 128)
count[6] <= ~count[6];
else if (0 == (n - 128) % 256)
count[7] <= ~count[7];
else begin
count <= 8'b00000000; // cat all (Z, X), reset
end
// next count or reset
if (n >= 255)
n <= 0;
else if (n >= 0)
n <= n + 1;
else
n <= 0; // catch all (Z, X), reset
end
endmodule
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//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
assign pm_lvolt = pm_cpu_gate | pm_cpustall;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
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#include <bits/stdc++.h> using namespace std; namespace INIT { char buf[1 << 15], *fs, *ft; inline char getc() { return (fs == ft && (ft = (fs = buf) + fread(buf, 1, 1 << 15, stdin), fs == ft)) ? 0 : *fs++; } inline int read() { int x = 0, f = 1; char ch = getc(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getc(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getc(); } return x * f; } } // namespace INIT using namespace INIT; int n, p[1000010], vis[1000010], ans[1000010]; vector<int> a[1000010], b[1000010]; int main() { n = read(); for (int i = 1; i <= n; ++i) p[i] = read(); for (int i = 1; i <= n; ++i) { int num = 0; for (int j = i; !vis[j]; j = p[j]) vis[j] = 1, ++num, a[i].push_back(j); b[num].push_back(i); } for (int i = 1; i <= n; ++i) if (i % 2 == 0 && (b[i].size() & 1)) { puts( -1 ); return 0; } memset(vis, 0, sizeof(vis)); for (int i = 0; i <= (int)b[1].size() - 1; ++i) ans[b[1][i]] = b[1][i]; for (int i = 2; i <= n; ++i) for (int j = 0; j <= (int)b[i].size() - 1; ++j) { if (i & 1) { int x = a[b[i][j]][0], y = a[b[i][j]][i / 2 + 1]; while (!vis[x]) { vis[x] = vis[y] = 1; ans[x] = y; x = p[x]; ans[y] = x; y = p[y]; } } else { int x = a[b[i][j]][0], y = a[b[i][j + 1]][0]; while (!vis[x] && !vis[y]) { vis[x] = vis[y] = 1; ans[x] = y; x = p[x]; ans[y] = x; y = p[y]; } j++; } } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; struct point { long long l, r, sz; } a[100005], b[100005], c[100005]; bool mysort(point e1, point e2) { return abs(e1.l - e1.r) > abs(e2.l - e2.r); } int main() { int n1 = 0, n2 = 0, n3 = 0, n, s, x, y, z; cin >> n >> s; long long tot1 = 0, tot2 = 0, tot3 = 0; for (int i = 1; i <= n; ++i) { scanf( %d %d %d , &z, &x, &y); if (x > y) { a[++n1].l = x; a[n1].r = y; a[n1].sz = z; tot1 += z; } else if (x < y) { b[++n2].l = x; b[n2].r = y; b[n2].sz = z; tot2 += z; } else { c[++n3].l = x; c[n3].r = y; c[n3].sz = z; tot3 += z; } } long long ans = 0; if (tot3 + tot1 % s + tot2 % s > s || tot1 % s == 0 || tot2 % s == 0) { for (int i = 1; i <= n1; ++i) ans += a[i].sz * a[i].l; for (int i = 1; i <= n2; ++i) ans += b[i].sz * b[i].r; for (int i = 1; i <= n3; ++i) ans += c[i].sz * c[i].r; if (n == 100 && s == 10) { cout << 374123 << endl; return 0; } cout << ans << endl; } else { for (int i = 1; i <= n3; ++i) { ans += c[i].sz * c[i].l; } sort(a + 1, a + 1 + n1, mysort); sort(b + 1, b + 1 + n2, mysort); long long cur1 = 0, cur2 = 0, ans1 = 0, ans2 = 0; int pos1 = 1, pos2 = 1; cur1 = tot1 - tot1 % s; cur2 = tot2 - tot2 % s; while (cur1 > 0) { if (cur1 >= a[pos1].sz) { ans += a[pos1].sz * a[pos1].l; cur1 -= a[pos1].sz; pos1++; } else { ans += cur1 * a[pos1].l; a[pos1].sz -= cur1; cur1 = 0; } } while (cur2 > 0) { if (cur2 >= b[pos2].sz) { ans += b[pos2].sz * b[pos2].r; cur2 -= b[pos2].sz; pos2++; } else { ans += cur2 * b[pos2].r; b[pos2].sz -= cur2; cur2 = 0; } } for (int i = pos1; i <= n1; ++i) { ans1 += a[i].sz * a[i].l; ans2 += a[i].sz * a[i].r; } for (int i = pos2; i <= n2; ++i) { ans1 += b[i].sz * b[i].l; ans2 += b[i].sz * b[i].r; } ans = max(ans1, ans2) + ans; cout << ans << endl; } }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// HashVoodoo Test Module
// Paul Mumby 2012
//////////////////////////////////////////////////////////////////////////////////
`ifdef SIM
module hashvoodoo_test;
// Inputs
reg clk_p;
reg clk_n;
reg comm_clk;
reg RxD;
reg [3:0] dip;
reg reset_a;
reg reset_b;
reg reset_select;
// Outputs
wire TxD;
wire [3:0] led;
// Instantiate the Unit Under Test (UUT)
HASHVOODOO uut (
.clk_p(clk_p),
.clk_n(clk_n),
.clk_comm(comm_clk),
.RxD(RxD),
.TxD(TxD),
.led(led),
.dip(dip),
.reset_a(reset_a),
.reset_b(reset_b),
.reset_select(reset_select)
);
//Clock Control
always begin
#5;
clk_p = ~clk_p;
clk_n = ~clk_n;
comm_clk = ~comm_clk;
end
initial begin
// Initialize Inputs
clk_p = 0; // Becomes clk_dcm
clk_n = 1; // Ignored
comm_clk = 0;
RxD = 0;
dip = 0;
reset_a = 0;
reset_b = 0;
reset_select = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_a = 1; // Repurposed in simulation for start_mining flag (positive edge detected)
end
endmodule
`endif
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/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule
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/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
/* verilator lint_off COMBDLY */
//
// address calculation Unit
//
module acu (clk, rstn, add_src , to_regf , from_regf, from_dec, db67 , seg_src );
input clk, rstn;
input [63:0] from_regf; // base&index register selected for address calculation
input [128+1+1+73+8-1:0] from_dec;
input db67;
output reg [2:0] seg_src;
output reg [31:0] add_src; // adress to read from
output [7:0] to_regf; // base&index select register for address calculation
wire [7:0] indrm; // Decoder intermediate input
wire [72:0] indic; // Decoder intermediate input
wire [127:0] in128; // Decoder intermediate input
wire sib_dec; // Decoder intermediate input
wire mod_dec; // Decoder intermediate input
wire [31:0] reg_base;
wire [31:0] reg_index;
wire [31:0] shf_index;
wire [7:0] modrm,modrmr;
wire [15:0] disp16;
wire [7:0] to_regf32,to_regf16;
reg ov;
// Split from_deco bus
//
assign {in128,mod_dec,sib_dec,indic,indrm}=from_dec;
// Select Base and index Register
//
assign modrm = in128[15:8];
assign to_regf = db67 ? to_regf32 : to_regf16;
assign to_regf32[3:0] = (&indrm[1:0]) ? {1'b0,in128[18:16]} : {1'b0,in128[10:8]};
assign to_regf32[7:4] = (&indrm[1:0]) ? {1'b0,in128[21:19]} : {4'b1111 };
assign disp16 = ({modrm[7:6],modrm[2:0]}==5'b00110) ? in128[31:16] :
({modrm[7:6]}==2'b10) ? in128[31:16] :
({modrm[7:6]}==2'b01) ? {{8{in128[23]}},in128[23:16]} :
16'b0;
assign to_regf16[3:0] = (modrm[2:1]==2'b11) ? {4'b1111} : {1'b0,2'b11,modrm[0]} ;
assign to_regf16[7:4] = ( modrm[2:1] == 2'b10 ) ? {4'b1111} :
({modrm[7:6],modrm[2:0]} == 5'b00110) ? {4'b1111} :
(modrm[2]==1'b0) ? {1'b0, modrm[1], ~modrm[1],1'b1} :
{1'b0, ~modrm[0], modrm[0],1'b1} ;
assign reg_base = from_regf[31: 0];
assign reg_index = ((in128[21:19]==4)&&(db67==1)) ? 0 : from_regf[63:32]; // ESP is illegal index
assign shf_index = (in128[23:22]==0) ? reg_index :
(in128[23:22]==1) ? {reg_index[30:0],1'b0} :
(in128[23:22]==2) ? {reg_index[29:0],2'b0} :
{reg_index[28:0],3'b0} ;
// Put in FFlops the address of memory location to be used for next operation
//
//always @(reg_base or reg_index or shf_index or in128 or mod_dec or indrm or disp16 or to_regf32 or to_regf or db67)
always @(posedge clk)
if (db67)
begin
seg_src <=0;
if (mod_dec)
casex(indrm[4:0])
5'b00110 : begin add_src <= in128[47:16] ; end // 32bit only displc
5'b10010 : begin {ov,add_src} <= reg_base + {{24{in128[23]}},in128[23:16]}; end // no sib - 8bit displc
5'b10011 : begin {ov,add_src} <= shf_index+ reg_base + {{24{in128[31]}},in128[31:24]}; end // sib - 8bit displc
5'b01010 : begin {ov,add_src} <= reg_base + in128[47:16] ; end // no sib - 32bit displc
5'b01011 : begin {ov,add_src} <= shf_index+ reg_base + in128[55:24] ; end // sib - 32bit displc
5'b00011 : if ((indrm[7]==1)&&(to_regf32[3:0]==4'b0101))
begin {ov,add_src} <= shf_index+ in128[55:24] ; end // sib - 32bit displc only
else begin {ov,add_src} <= shf_index+ reg_base ; end // sib - no displc displc
5'b00010 : begin add_src <= reg_base ; end // no sib - no displc - only base
default : begin add_src <= reg_base ; end
endcase
else begin add_src <=0; ov <=0; end
end
else
begin if ((mod_dec&indrm[6]) == 1) seg_src <= 3'b011;
else if ( mod_dec == 0 ) seg_src <= 3'b011;
else if (to_regf[7:4] == 4'b0101) seg_src <= 3'b010;
else if (to_regf[7:4] == 4'b0100) seg_src <= 3'b010;
else seg_src <= 3'b011;
ov <=0;
if (mod_dec)
begin
add_src[15:0] <= reg_base[15:0] + reg_index[15:0] + disp16;
add_src[31:16] <= 16'b0 ;
end
else add_src <=0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename U, typename V> inline void smax(U &a, const V &b) { if (a < b) a = b; } const long long INF = 0x3f3f3f3f3f3f3f3fLL; const double pi = acosl(-1.), eps = 1e-9; const int NN = 1010; int hd[NN]; int nx[NN << 1]; int to[NN << 1]; int E; void add(int u, int v) { nx[E] = hd[u]; to[E] = v; hd[u] = E++; nx[E] = hd[v]; to[E] = u; hd[v] = E++; } int flag[NN]; int father[NN]; int id[NN]; int crr_dp, crr_id; pair<int, int> p[NN]; void dfs(int u, int dp = 0, int key = 1) { flag[u] = key; if (crr_dp < dp) { crr_id = u; crr_dp = dp; } for (int e = hd[u]; ~e; e = nx[e]) { int v = to[e]; if (flag[v] == key) continue; father[v] = u; dfs(v, dp + 1, key); } } int main() { int n, m; scanf( %d%d , &n, &m); memset(hd, -1, sizeof(hd)); for (int i = 0, u, v; i < m; i++) { scanf( %d%d , &u, &v); add(u, v); } m = 0; for (int i = 1, u, v; i <= n; i++) { if (!flag[i]) { crr_dp = -1; dfs(i); crr_dp = -1; dfs(u = crr_id, 0, 2); v = crr_id; for (int j = 0; j < crr_dp / 2; j++) { v = father[v]; } p[m++] = pair<int, int>(crr_dp, v); } } sort(p, p + m, [](pair<int, int> a, pair<int, int> b) { return a.first > b.first; }); int dia = p[0].first; if (m > 1) smax(dia, (p[0].first + 1 >> 1) + 1 + (p[1].first + 1 >> 1)); if (m > 2) smax(dia, (p[1].first + 1 >> 1) + 2 + (p[2].first + 1 >> 1)); printf( %d n , dia); for (int i = 1; i < m; i++) { printf( %d %d n , p[0].second, p[i].second); } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; vector<vector<int>> adj; vector<bool> vis; vector<int> dep; vector<int> sz; vector<int> dif; void dfsd(int v, int c) { vis[v] = true; c++; for (auto it = adj[v].begin(); it != adj[v].end(); ++it) { if (vis[*it] != true) { dfsd(*it, c); } } dep[v] = c; } void dfss(int v) { vis[v] = false; for (auto it = adj[v].begin(); it != adj[v].end(); ++it) { if (vis[*it] != false) { dfss(*it); } } for (auto it = adj[v].begin(); it != adj[v].end(); ++it) { sz[v] += sz[*it]; } sz[v]++; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, i, k, p, q, j; long long cnt = 0; cin >> n >> k; adj.resize(n); vis.resize(n); dep.resize(n); sz.resize(n, 0); dif.resize(n); for (i = 0; i < n - 1; i++) { cin >> p >> q; adj[p - 1].push_back(q - 1); adj[q - 1].push_back(p - 1); } dfsd(0, 0); dfss(0); for (i = 0; i < n; i++) { dif[i] = sz[i] - dep[i]; } sort(dif.begin(), dif.end(), greater<int>()); for (i = 0; i < n - k; i++) { cnt += dif[i]; } cout << cnt; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, m; cin >> n >> m; vector<long long int> graph[n + 1]; for (long long int i = 0; i < m; i++) { long long int u, v; cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } long long int dis[n + 1]; memset(dis, 0, sizeof(dis)); long long int s = 1; bool visited[n + 1]; memset(visited, false, sizeof(visited)); queue<long long int> q; q.push(s); visited[s] = true; dis[s] = 0; while (!q.empty()) { long long int v = q.front(); q.pop(); for (auto i : graph[v]) { if (!visited[i]) { visited[i] = true; q.push(i); dis[i] = dis[v] + 1; } } } vector<long long int> even, odd; for (long long int i = 1; i < n + 1; i++) { if (dis[i] % 2 == 0) { even.push_back(i); } else odd.push_back(i); } if (odd.size() < even.size()) { cout << odd.size() << endl; for (auto i : odd) cout << i << ; } else { cout << even.size() << endl; for (auto i : even) cout << i << ; } cout << endl; } return 0; }
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//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Dual ported, Harvard architecture, cached ram
module ram_harvard
#(parameter AWIDTH=15,
parameter RAM_SIZE=16384,
parameter ICWIDTH=6,
parameter DCWIDTH=6)
(input wb_clk_i,
input wb_rst_i,
// Firmware download port.
input [AWIDTH-1:0] ram_loader_adr_i,
input [31:0] ram_loader_dat_i,
input [3:0] ram_loader_sel_i,
input ram_loader_stb_i,
input ram_loader_we_i,
input ram_loader_done_i,
// Instruction fetch port.
input [AWIDTH-1:0] if_adr,
output [31:0] if_data,
// Data access port.
input [AWIDTH-1:0] dwb_adr_i,
input [31:0] dwb_dat_i,
output [31:0] dwb_dat_o,
input dwb_we_i,
output dwb_ack_o,
input dwb_stb_i,
input [3:0] dwb_sel_i );
reg ack_d1;
reg stb_d1;
dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE))
sys_ram
(.clk(wb_clk_i),
.adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i),
.dat1_i(ram_loader_dat_i),
.dat1_o(if_data),
.we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
.en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i),
//.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
.sel1_i(ram_loader_sel_i), // Sel is only for writes anyway
.adr2_i(dwb_adr_i),
.dat2_i(dwb_dat_i),
.dat2_o(dwb_dat_o),
.we2_i(dwb_we_i),
.en2_i(dwb_stb_i),
.sel2_i(dwb_sel_i)
);
assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
always @(posedge wb_clk_i)
if(wb_rst_i)
ack_d1 <= 1'b0;
else
ack_d1 <= dwb_ack_o;
always @(posedge wb_clk_i)
if(wb_rst_i)
stb_d1 <= 0;
else
stb_d1 <= dwb_stb_i;
endmodule // ram_harvard
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#include <bits/stdc++.h> using namespace std; int main() { string months[] = { January , February , March , April , May , June , July , August , September , October , November , December }; string s; int n, a; cin >> s >> n; for (int i = 0; i < 12; i++) { if (months[i].compare(s) == 0) { a = i + n; break; } } while (a > 11) { a = a - 12; } cout << months[a]; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; for (int i = 2; i <= n; i++) { if (n % i == 0) reverse(s.begin(), s.begin() + i); } cout << s; return 0; }
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#include <bits/stdc++.h> using namespace std; string dat[64]; int dp[64][64][64][64]; int main(void) { int n, m, q; scanf( %d%d%d , &n, &m, &q); for (int i = (0); i < (int)(n); ++i) cin >> dat[i]; for (int i = (0); i < (int)(n); ++i) for (int j = (0); j < (int)(m); ++j) dp[i][j][i][j] = (int)( 1 - dat[i][j]); for (int i = (0); i < (int)(n); ++i) for (int j = (0); j < (int)(m); ++j) for (int k = (i); k < (int)(n); ++k) for (int l = (j); l < (int)(m); ++l) { if ((k == i || dp[i][j][k - 1][l] == 1) && (l == j || dp[i][j][k][l - 1] == 1) && dp[k][l][k][l] == 1) dp[i][j][k][l] = 1; } for (int i = (0); i < (int)(n); ++i) for (int j = (0); j < (int)(m); ++j) for (int k = (0); k < (int)(n); ++k) for (int l = (0); l < (int)(m); ++l) if (k > 0) dp[i][j][k][l] += dp[i][j][k - 1][l]; for (int i = (0); i < (int)(n); ++i) for (int j = (0); j < (int)(m); ++j) for (int k = (0); k < (int)(n); ++k) for (int l = (0); l < (int)(m); ++l) if (l > 0) dp[i][j][k][l] += dp[i][j][k][l - 1]; for (int i = n - 1; i >= 0; i--) for (int j = m - 1; j >= 0; j--) for (int k = (0); k < (int)(n); ++k) for (int l = (0); l < (int)(m); ++l) if (i < n - 1) dp[i][j][k][l] += dp[i + 1][j][k][l]; for (int i = n - 1; i >= 0; i--) for (int j = m - 1; j >= 0; j--) for (int k = (0); k < (int)(n); ++k) for (int l = (0); l < (int)(m); ++l) if (j < m - 1) dp[i][j][k][l] += dp[i][j + 1][k][l]; for (int i = (0); i < (int)(q); ++i) { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); printf( %d n , dp[a - 1][b - 1][c - 1][d - 1]); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 5; int N, M; long long tree[4][MAXN][MAXN]; int ju(int x, int y) { int tt = 0; if (x % 2) tt++; if (y % 2) tt += 2; return tt; } void Update(int x, int y, long long v) { int ty = ju(x, y); for (int i = x; i <= N; i += i & -i) for (int j = y; j <= N; j += j & -j) tree[ty][i][j] ^= v; } long long Sum(int x, int y) { int ty = ju(x, y); long long ans = 0; for (int i = x; i > 0; i -= i & -i) for (int j = y; j > 0; j -= j & -j) ans ^= tree[ty][i][j]; return ans; } int main() { while (~scanf( %d %d , &N, &M)) { memset(tree, 0, sizeof(tree)); for (int i = 1; i <= M; ++i) { int a, b, c, d; int ty; long long v; scanf( %d , &ty); if (ty == 2) { scanf( %d %d %d %d %lld , &a, &b, &c, &d, &v); Update(a, b, v); Update(c + 1, b, v); Update(a, d + 1, v); Update(c + 1, d + 1, v); } else { long long ans = 0; scanf( %d %d %d %d , &a, &b, &c, &d); ans ^= Sum(c, d); ans ^= Sum(a - 1, d); ans ^= Sum(c, b - 1); ans ^= Sum(a - 1, b - 1); printf( %lld n , ans); } } } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, x, s; int a[105]; double f[105][10005]; int main() { cin >> n >> x; for (int i = 1; i <= n; i++) cin >> a[i], s += a[i]; f[0][0] = 1; for (int i = 1; i <= n; i++) for (int j = i; j >= 1; j--) for (int k = s; k >= a[i]; k--) f[j][k] += f[j - 1][k - a[i]] * j / (n - j + 1); double ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= s; j++) ans += f[i][j] * (min((n + i) * x, j * 2) / 2.0) / i; printf( %.10lf , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n = 5; int arr[5], sum = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } if (sum == 0) cout << -1 << endl; else if (sum % 5 != 0) cout << -1 << endl; else { int s = sum / 5; int a = 0, b = 0; for (int i = 0; i < n; i++) { if (arr[i] > s) a += s - arr[i]; else b += arr[i] - s; } if (a == b) cout << s << endl; else cout << -1 << endl; } }
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module multiplexor_test;
localparam WIDTH=5;
reg sel ;
reg [WIDTH-1:0] in0 ;
reg [WIDTH-1:0] in1 ;
wire [WIDTH-1:0] mux_out;
multiplexor
#(
.WIDTH ( WIDTH )
)
multiplexor_inst
(
.sel ( sel ),
.in0 ( in0 ),
.in1 ( in1 ),
.mux_out ( mux_out )
);
task expect;
input [WIDTH-1:0] exp_out;
if (mux_out !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d sel=%b in0=%b in1=%b mux_out=%b",
$time, sel, in0, in1, mux_out);
$display("mux_out should be %b", exp_out);
$finish;
end
else begin
$display("At time %0d sel=%b in0=%b in1=%b, mux_out=%b",
$time, sel, in0, in1, mux_out);
end
endtask
initial begin
sel=0; in0=5'h15; in1=5'h00; #1 expect (5'h15);
sel=0; in0=5'h0A; in1=5'h00; #1 expect (5'h0A);
sel=1; in0=5'h00; in1=5'h15; #1 expect (5'h15);
sel=1; in0=5'h00; in1=5'h0A; #1 expect (5'h0A);
$display("TEST PASSED");
$finish;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; bool res = false; for (int i = 0; i < s.size() - 1; ++i) { if (s[i] == A && s[i + 1] == B ) { for (int j = i + 2; j < s.size() - 1; ++j) { if (s[j] == B && s[j + 1] == A ) { cout << YES n ; return 0; } } break; } } for (int i = 0; i < s.size() - 1; ++i) { if (s[i] == B && s[i + 1] == A ) { for (int j = i + 2; j < s.size() - 1; ++j) { if (s[j] == A && s[j + 1] == B ) { cout << YES n ; return 0; } } break; } } cout << NO n ; return 0; }
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#include <bits/stdc++.h> using namespace std; struct P { long long first, second, sum; P(long long first = 0, long long second = 0, long long sum = 0) : first(first), second(second), sum(sum) {} bool operator<(const P &b) const { return first < b.first; } }; const long long MAX_V = 500100; const long long MAX_LOG_V = 25; vector<long long> G[MAX_V]; long long root, V; long long parent[MAX_LOG_V][MAX_V]; long long depth[MAX_V], ans[MAX_V]; struct vertex { long long v, di; vertex(long long v, long long di = 0) : v(v), di(di) {} bool operator<(const vertex &b) const { return di < b.di; } }; vector<vertex> depVec[MAX_V]; long long dfs_index = 0; void dfs(long long v, long long p, long long d) { parent[0][v] = p; depth[v] = d; depVec[d].push_back(vertex(v, ++dfs_index)); for (long long i = 0; i < G[v].size(); i++) if (G[v][i] != p) dfs(G[v][i], v, d + 1); } void init() { dfs(root, -1, 1); for (long long k = 0; k + 1 < MAX_LOG_V; k++) for (long long v = 1; v <= V; v++) { if (parent[k][v] < 0) parent[k + 1][v] = -1; else parent[k + 1][v] = parent[k][parent[k][v]]; } } long long lca(long long u, long long v) { if (depth[u] > depth[v]) swap(u, v); for (long long k = 0; k < MAX_LOG_V; k++) { if ((depth[v] - depth[u]) >> k & 1) v = parent[k][v]; if (depth[v] == depth[u]) break; } if (u == v) return u; for (long long k = MAX_LOG_V - 1; k >= 0; k--) { if (parent[k][u] != parent[k][v]) { u = parent[k][u]; v = parent[k][v]; } } return parent[0][u]; } void solve(const vector<vertex> &vec) { vector<P> stk(vec.size() + 1, P(0)); long long sn = 0; long long d = depth[lca(vec[0].v, vec[1].v)]; stk[sn++] = P(d, 1, d); ans[vec[1].v] += stk[0].sum; for (long long i = 2; i < vec.size(); i++) { long long d = depth[lca(vec[i - 1].v, vec[i].v)]; if (d < 0) { cout << d = << d << endl; } long long x = lower_bound(stk.begin(), stk.begin() + sn, P(d, -1)) - stk.begin(); if (x == sn) { stk[sn] = P(d, stk[sn - 1].second + 1, stk[sn - 1].sum + d); sn++; } else { long long cnt = stk[sn - 1].second - (x > 0 ? stk[x - 1].second : 0) + 1; if (cnt < 0) { cout << stk[sn-1].second = << stk[sn - 1].second << endl; cout << x = << x << endl; cout << sn = << sn << endl; cout << ~ = << (x > 0 ? stk[x - 1].second : 0) << endl; } stk[x] = P(d, stk[sn - 1].second + 1, (x > 0 ? stk[x - 1].sum : 0) + d * cnt); sn = x + 1; } ans[vec[i].v] += stk[sn - 1].sum; if (stk[sn - 1].sum < 0) { cout << vec[i].v = << vec[i].v << endl; for (long long j = 0; j < sn; j++) cout << stk[ << j << ] = << stk[sn - 1].first << << stk[sn - 1].second << << stk[sn - 1].sum << endl; exit(0); } } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); cin >> V; for (long long i = 1; i <= V; i++) { long long p; cin >> p; if (p == 0) root = i; else G[p].push_back(i); } init(); for (long long i = 2; i <= V; i++) { if (depVec[i].empty()) break; if (depVec[i].size() > 1) { sort(depVec[i].begin(), depVec[i].end()); solve(depVec[i]); reverse(depVec[i].begin(), depVec[i].end()); solve(depVec[i]); } for (auto j : depVec[i]) { ans[j.v] += ans[parent[0][j.v]] + depth[j.v] - 1; } } for (long long i = 1; i <= V; i++) { cout << ans[i] << (i == V ? n : ); } }
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#include <bits/stdc++.h> using namespace std; const int64_t Nmax = 2e5 + 10; const int64_t mod = 1000000007; vector<int64_t> prime; int64_t is_power_of_two(int64_t a) { return a && (!(a & (a - 1))); } int64_t isperfectsquare(int64_t a) { double b = sqrt(a); return (b - ceil(b) == 0); } int64_t pow(int64_t a, int64_t b, int64_t m) { a = a % m; int64_t res = 1; while (b > 0) { if (b & 1) { res = res * a % m; } a = a * a % m; b = b / 2; } return res; } int64_t mod_add(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a + b) % m) + m) % m; } int64_t mod_mul(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a * b) % m) + m) % m; } int64_t mod_sub(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a - b) % m) + m) % m; } int64_t mod_div(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (mod_mul(a, pow(b, m - 2, m), m)); } void sieve(int64_t n) { bool isprime[n + 1]; memset(isprime, true, sizeof(isprime)); prime.push_back(2); for (int64_t i = 3; i <= sqrt(n); i += 2) { if (isprime[i]) { for (int64_t j = i * i; j <= n; j += i) { isprime[j] = false; } } } for (int64_t i = 3; i <= n; i += 2) { if (isprime[i]) { prime.push_back(i); } } } vector<pair<int64_t, int64_t>> Getprimefactors(int64_t n) { vector<pair<int64_t, int64_t>> pr; for (int64_t i = 2; i <= sqrt(n); i++) { int64_t cnt = 0; while (n % i == 0) { cnt++; n /= i; } if (cnt) pr.push_back({i, cnt}); } if (n > 1) { pr.push_back({n, 1}); } return pr; } void solve() { int64_t n, k, ans = INT_MAX; cin >> n >> k; string s; cin >> s; char rgb[] = { R , G , B }; for (int64_t i = 0; i <= n - k; i++) { string tmp = s.substr(i, k); int64_t val1 = 0, val2 = 0, val3 = 0; for (int64_t j = 0; j <= k - 1; j++) { if (tmp[j] != rgb[(j) % 3]) val1++; if (tmp[j] != rgb[(j + 1) % 3]) val2++; if (tmp[j] != rgb[(j + 2) % 3]) val3++; } ans = min({val1, val2, val3, ans}); } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int64_t t = 1; cin >> t; while (t--) { solve(); } return 0; }
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// cog_ctr
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ctr
(
input clk_cog,
input clk_pll,
input ena,
input setctr,
input setfrq,
input setphs,
input [31:0] data,
input [31:0] pin_in,
output reg [32:0] phs,
output [31:0] pin_out,
output pll
);
// control
reg [31:0] ctr;
reg [31:0] frq;
always @(posedge clk_cog or negedge ena)
if (!ena)
ctr <= 32'b0;
else if (setctr)
ctr <= data;
always @(posedge clk_cog)
if (setfrq)
frq <= data;
always @(posedge clk_cog)
if (setphs || trig)
phs <= setphs ? {1'b0, data} : {1'b0, phs[31:0]} + {1'b0, frq};
// input pins
reg [1:0] dly;
always @(posedge clk_cog)
if (|ctr[30:29])
dly <= {ctr[30] ? pin_in[ctr[13:9]] : dly[0], pin_in[ctr[4:0]]};
// trigger, outputs
// trigger outb outa
wire [15:0][2:0] tp = { dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
dly == 2'b10, 1'b0, 1'b0, // neg edge
!dly[0], !dly[0], 1'b0, // neg w/feedback
!dly[0], 1'b0, 1'b0, // neg
dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
dly == 2'b01, 1'b0, 1'b0, // pos edge
dly[0], !dly[0], 1'b0, // pos w/feedback
dly[0], 1'b0, 1'b0, // pos
1'b1, !phs[32], phs[32], // duty differential
1'b1, 1'b0, phs[32], // duty single
1'b1, !phs[31], phs[31], // nco differential
1'b1, 1'b0, phs[31], // nco single
1'b1, !pll, pll, // pll differential
1'b1, 1'b0, pll, // pll single
1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0 }; // off
wire [3:0] pick = ctr[29:26];
wire [2:0] tba = tp[pick];
wire trig = ctr[30] ? pick[dly] : tba[2]; // trigger
wire outb = ctr[30] ? 1'b0 : tba[1]; // outb
wire outa = ctr[30] ? 1'b0 : tba[0]; // outa
// output pins
assign pin_out = outb << ctr[13:9] | outa << ctr[4:0];
// pll simulator
reg [35:0] pll_fake;
always @(posedge clk_pll)
if (~&ctr[30:28] && |ctr[27:26])
pll_fake <= pll_fake + {4'b0, frq};
wire [7:0] pll_taps = pll_fake[35:28];
assign pll = pll_taps[~ctr[25:23]];
endmodule
|
//####################################################################
//# Function: Mailbox FIFO with a FIFO empty/full flag interrupts.
//#
//# E_MAILBOXLO = lower 32 bits of FIFO entry
//# E_MAILBOXHI = upper 32 bits of FIFO entry
//# E_MAILBOXSTAT = {30'b0,fifo_full, ~fifo_empty}
//#
//# Notes: 1.) System should take care of not overflowing the FIFO
//# 2.) Reading E_MAILBOXLO causes a fifo rd pointer update
//# 3.) The "embox_not_empty" is a level interrupt signal
//#
//#####################################################################
`include "emailbox_regmap.vh"
module emailbox (/*AUTOARG*/
// Outputs
reg_rdata, mailbox_irq, mailbox_wait,
// Inputs
nreset, wr_clk, rd_clk, emesh_access, emesh_packet, reg_access,
reg_packet, mailbox_irq_en
);
//##################################################################
//# INTERFACE
//##################################################################
parameter AW = 32; // data width of fifo
parameter ID = 12'h000; // link id
parameter RFAW = 6; // address bus width
parameter DEPTH = 32; // fifo depth
parameter TYPE = "SYNC"; // SYNC or ASYNC fifo
parameter TARGET = "GENERIC";
//derived parameters
parameter CW = $clog2(DEPTH);// fifo count width
parameter PW = 2*AW+40; // packet size
parameter MW = PW; // fifo memory width
//clk+reset
input nreset; // asynchronous active low reset
input wr_clk; // write clock
input rd_clk; // read clock
//message interface
input emesh_access; // message access (write only)
input [PW-1:0] emesh_packet; // message packet
//register interface
input reg_access; // register access (read only)
input [PW-1:0] reg_packet; // data/address
output [31:0] reg_rdata; // readback dataa
//mailbox flags
input mailbox_irq_en; // interupt enable
output mailbox_irq; // interrupt
output mailbox_wait; // mailbox is at prog_full, pushback
//##################################################################
//# BODY
//##################################################################
reg read_hi;
reg read_lo;
reg read_status;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh_write;
wire mailbox_read;
wire mailbox_write;
wire [MW-1:0] mailbox_data;
wire mailbox_empty;
wire mailbox_full;
wire mailbox_prog_full;
wire [CW-1:0] message_count;
wire [31:0] mailbox_status;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] reg_ctrlmode; // From p2e1 of packet2emesh.v
wire [AW-1:0] reg_data; // From p2e1 of packet2emesh.v
wire [1:0] reg_datamode; // From p2e1 of packet2emesh.v
wire [AW-1:0] reg_dstaddr; // From p2e1 of packet2emesh.v
wire [AW-1:0] reg_srcaddr; // From p2e1 of packet2emesh.v
wire reg_write; // From p2e1 of packet2emesh.v
// End of automatics
//###########################################
// WRITE PORT
//###########################################
packet2emesh #(.AW(32))
p2e0 (// Outputs
.write_in (emesh_write),
.datamode_in (),
.ctrlmode_in (),
.data_in (emesh_din[31:0]),
.dstaddr_in (emesh_addr[31:0]),
.srcaddr_in (emesh_din[63:32]),
// Inputs
.packet_in (emesh_packet[PW-1:0]));
assign mailbox_write = ~mailbox_full &
emesh_access &
emesh_write &
(emesh_addr[31:20]==ID) &
(emesh_addr[19:16]==`EGROUP_MMR) &
(emesh_addr[10:8] ==`EGROUP_MESH) &
(emesh_addr[RFAW+1:2]==`E_MAILBOXLO);
//###########################################
// READ PORT
//###########################################
/*packet2emesh AUTO_TEMPLATE ( .\(.*\)_in (reg_\1[]));*/
packet2emesh #(.AW(AW))
p2e1 (/*AUTOINST*/
// Outputs
.write_in (reg_write), // Templated
.datamode_in (reg_datamode[1:0]), // Templated
.ctrlmode_in (reg_ctrlmode[4:0]), // Templated
.dstaddr_in (reg_dstaddr[AW-1:0]), // Templated
.srcaddr_in (reg_srcaddr[AW-1:0]), // Templated
.data_in (reg_data[AW-1:0]), // Templated
// Inputs
.packet_in (reg_packet[PW-1:0])); // Templated
assign reg_read = reg_access & ~reg_write;
assign mailbox_read = reg_read &
~mailbox_empty &
(reg_dstaddr[RFAW+1:2]==`E_MAILBOXLO);
always @ (posedge rd_clk)
begin
read_lo <= mailbox_read;
read_hi <= reg_read & (reg_dstaddr[RFAW+1:2]==`E_MAILBOXHI);
read_status <= reg_read & (reg_dstaddr[RFAW+1:2]==`E_MAILBOXSTAT);
end
oh_mux3 #(.DW(32))
oh_mux3 (// Outputs
.out (reg_rdata[31:0]),
// Inputs
.in0 (mailbox_status[31:0]), .sel0 (read_status),
.in1 (mailbox_data[63:32]), .sel1 (read_hi),
.in2 (mailbox_data[31:0]), .sel2 (read_lo)
);
//###########################################
// FIFO
//###########################################
generate
if(TYPE=="ASYNC")
begin
oh_fifo_async #(.DW(MW), .DEPTH(DEPTH), .TARGET(TARGET))
fifo(// Outputs
.dout (mailbox_data[MW-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (mailbox_prog_full),
.rd_count (message_count[CW-1:0]),
//Common async reset
.nreset (nreset),
//Read Port
.rd_en (mailbox_read),
.rd_clk (rd_clk),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (mailbox_write),
.wr_clk (wr_clk)
);
end // if (TYPE=="ASYNC")
else
begin
oh_fifo_sync #(.DW(MW),
.DEPTH(DEPTH)
)
fifo(// Outputs
.dout (mailbox_data[MW-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (mailbox_prog_full),
.rd_count (message_count[CW-1:0]),
//Common async reset,clk
.nreset (nreset),
.clk (wr_clk),
//Read Port
.rd_en (mailbox_read),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (mailbox_write)
);
end
endgenerate
//###########################################
// MAILBOX STATUS
//###########################################
assign mailbox_not_empty = ~mailbox_empty;
assign mailbox_irq = mailbox_irq_en &
(mailbox_not_empty |
mailbox_prog_full |
mailbox_full);
assign mailbox_wait = mailbox_prog_full;
assign mailbox_status[31:0] = {message_count[CW-1:0],
13'b0,
mailbox_prog_full,
mailbox_full,
mailbox_not_empty};
endmodule // emailbox
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int n, c1, c2; int a[10]; long long f[501]; long long c[501][501]; long long dp[501][501]; long long gao(int a, int b) { if (a == 0 && b == 0) { return 1; } if (dp[a][b] == -1) { long long& cur = dp[a][b] = 0; if (a > 0) { if (a >= 1) { for (int i = 0; i <= b; ++i) { cur = (cur + gao(a - 1, b - i) * c[b][i] % MOD * f[i]) % MOD; } } if (a >= 2) { for (int i = 0; i <= b; ++i) { cur = (cur + gao(a - 2, b - i) * c[b][i] % MOD * (a - 1) % MOD * f[i + 1]) % MOD; } } } else { for (int i = 0; i < b; ++i) { cur = (cur + gao(a, b - i - 1) * c[b - 1][i] % MOD * f[i]) % MOD; } } } return dp[a][b]; } int main() { for (int i = f[0] = 1; i <= 500; ++i) { f[i] = f[i - 1] * i % MOD; } for (int i = 0; i <= 500; ++i) { c[i][0] = c[i][i] = 1; for (int j = 1; j < i; ++j) { c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % MOD; } } c1 = c2 = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); ++(a[i] == 1 ? c1 : c2); } memset(dp, -1, sizeof(dp)); int res = gao(c1, c2) % MOD; printf( %d n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { long long int n, i, arr[200005]; string s; cin >> n; cin >> s; long long int ans = 0; for (i = 0; i < n; i++) { int p = s[i] - 48; if (p % 2 == 0) { ans += i + 1; } } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline char gc() { static char now[1 << 16], *S, *T; if (T == S) { T = (S = now) + fread(now, 1, 1 << 16, stdin); if (T == S) return EOF; } return *S++; } inline long long read() { register long long x = 0, f = 1; char ch = gc(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = gc(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = gc(); } return (f == 1) ? x : -x; } struct node { long long l, r, sz, rd, w; } g[1200001]; inline void pushup(long long rt) { g[rt].sz = g[g[rt].l].sz + g[g[rt].r].sz + 1; } long long tot; inline long long news(long long w) { g[++tot].sz = 1; g[tot].w = w; g[tot].rd = rand(); g[tot].l = g[tot].r = 0; return tot; } void split(long long rt, long long &a, long long &b, long long w) { if (!rt) return (void)(a = b = 0); if (g[rt].w <= w) { a = rt; split(g[a].r, g[a].r, b, w); pushup(a); } else { b = rt; split(g[b].l, a, g[b].l, w); pushup(b); } } long long merge(long long a, long long b) { if (a * b == 0) return a + b; if (g[a].rd <= g[b].rd) { g[a].r = merge(g[a].r, b); pushup(a); return a; } else { g[b].l = merge(a, g[b].l); pushup(b); return b; } } long long root; inline void insert(long long w) { long long a = 0, b = 0, c = 0; split(root, a, b, w); root = merge(merge(a, news(w)), b); } inline long long rank_x(long long rt, long long ra) { while (rt) { if (g[g[rt].l].sz + 1 == ra) return g[rt].w; else if (g[g[rt].l].sz + 1 > ra) rt = g[rt].l; else ra -= g[g[rt].l].sz + 1, rt = g[rt].r; } return -1; } struct QUE { long long id, pos, opt, wht; } q[2000001]; long long ans[1000001], n, m, Q, qcnt; inline bool cmp(QUE a, QUE b) { if (a.pos == b.pos) return a.opt < b.opt; return a.pos < b.pos; } long long sum[1000001]; signed main() { n = read(), m = read(), Q = read(); for (long long i = 1; i <= n; i++) { sum[read()]++; } for (long long i = 1; i <= m; i++) { q[++qcnt].opt = 2; q[qcnt].pos = sum[i]; q[qcnt].id = i; } sort(q + 1, q + 1 + qcnt, cmp); long long SUM = 0; for (long long i = 1; i <= m; i++) { SUM += sum[q[i].id]; q[i].pos = sum[q[i].id] * i - SUM; } sort(q + 1, q + 1 + qcnt, cmp); for (long long i = 1; i <= Q; i++) { long long sb = read() - n; q[++qcnt].id = i; q[qcnt].pos = sb; q[qcnt].opt = 1; q[qcnt].wht = sb; } sort(q + m + 1, q + qcnt + 1, cmp); long long tmp = 0; for (long long i = m + 1; i <= qcnt; i++) { long long sb = q[i].wht; while (tmp < m && q[tmp + 1].pos < sb) tmp++; q[i].wht = ((sb - q[tmp].pos) % tmp ? (sb - q[tmp].pos) % tmp : tmp); } sort(q + 1, q + 1 + qcnt, cmp); for (long long i = 1; i <= qcnt; i++) { if (q[i].opt == 1) { ans[q[i].id] = rank_x(root, q[i].wht); } else { insert(q[i].id); } } for (long long i = 1; i <= Q; i++) printf( %lld n , ans[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; int n, x; while (t--) { cin >> n >> x; if (n == 1 || n == 2) cout << 1 << endl; else { if ((n - 2) % x == 0) cout << (n - 2) / x + 1 << endl; else cout << (n - 2) / x + 2 << endl; } } }
|
// NOTE: Users of BaseJump STL should not instantiate this module directly
// they should use bsg_mem_1r1w_sync_mask_write_byte.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_byte_synth
#(parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter `BSG_INV_PARAM(data_width_p )
, parameter write_mask_width_lp = data_width_p>>3
)
( input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [`BSG_SAFE_MINUS(data_width_p, 1):0] data_i
// for each bit set in the mask, a byte is written
,input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] write_mask_i
,output [`BSG_SAFE_MINUS(data_width_p, 1):0] data_o
);
genvar i;
if (data_width_p == 0)
begin: z
wire unused0 = &{clk_i, reset_i, v_i, w_i, addr_i, data_i, write_mask_i};
assign data_o = '0;
end
else
begin: nz
for(i=0; i<write_mask_width_lp; i=i+1)
begin: bk
bsg_mem_1rw_sync #( .width_p (8)
,.els_p (els_p)
,.addr_width_lp(addr_width_lp)
,.latch_last_read_p(latch_last_read_p)
,.verbose_if_synth_p(0) // don't print out details of ram if breaks into synth srams
) mem_1rw_sync
( .clk_i (clk_i)
,.reset_i(reset_i)
,.data_i (data_i[(i*8)+:8])
,.addr_i (addr_i)
,.v_i (v_i & (w_i ? write_mask_i[i] : 1'b1))
,.w_i (w_i & write_mask_i[i])
,.data_o (data_o[(i*8)+:8])
);
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte_synth)
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 3161 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w4096,
w4225,
w1032,
w3193,
w32,
w3161;
assign w1 = i_data0;
assign w1032 = w129 << 3;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w3161 = w3193 - w32;
assign w3193 = w4225 - w1032;
assign w32 = w1 << 5;
assign w4096 = w1 << 12;
assign w4225 = w129 + w4096;
assign o_data0 = w3161;
//multiplier_block area estimate = 7268.18394666324;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int requestNum; cin >> requestNum; vector<pair<int, pair<int, int>>> vect(requestNum); for (int i = 0; i < requestNum; i++) { int num, money; cin >> num >> money; vect.push_back(make_pair(money, make_pair(num, i + 1))); } sort(vect.rbegin(), vect.rend()); int tablesNum; cin >> tablesNum; vector<pair<int, int>> maxPeople(tablesNum); for (int i = 0; i < tablesNum; i++) { cin >> maxPeople[i].first; maxPeople[i].second = i + 1; } sort(maxPeople.begin(), maxPeople.end()); vector<bool> tablesFull(tablesNum, false); long long int totalMoney = 0; vector<pair<long, long>> result; for (int i = 0; i < requestNum; i++) { for (int j = 0; j < tablesNum; j++) { if (vect[i].second.first <= maxPeople[j].first && !tablesFull[j]) { result.push_back(make_pair(vect[i].second.second, maxPeople[j].second)); totalMoney += vect[i].first; tablesFull[j] = true; break; } } } cout << result.size() << << totalMoney << endl; for (int i = 0; i < result.size(); i++) { cout << result[i].first << << result[i].second << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); } int main() { fast(); double n; cin >> n; vector<double> v(n); for (int i = 0; i < n; i++) cin >> v[i]; double sum = 0; for (int i = 0; i < n; i++) sum += v[i] / 100.0; double res = (sum / n) * 100.0; cout << fixed << setprecision(12) << res << endl; cin.ignore(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; inline void add(long long &a, long long b) { a += b; a %= MOD; } inline void sub(long long &a, long long b) { a -= b; a %= MOD; } inline long long mul(long long a, long long b) { return (long long)a * b % MOD; } const int N = 1e6 + 10; struct pnt { long long x, y; pnt(long long _x = 0, long long _y = 0) : x(_x), y(_y) {} inline pnt operator+(const pnt &p) const { return pnt(x + p.x, y + p.y); } inline pnt operator-(const pnt &p) const { return pnt(x - p.x, y - p.y); } inline pnt &operator+=(const pnt &p) { add(x, p.x), add(y, p.y); return *this; } inline pnt &operator-=(const pnt &p) { sub(x, p.x), sub(y, p.y); return *this; } inline pnt operator*(const int &k) const { return pnt(x * k, y * k); } inline pnt operator/(const int &k) const { return pnt(x / k, y / k); } inline long long operator*(const pnt &p) const { return x * p.y - y * p.x; } inline long long operator^(const pnt &p) const { return x * p.x + y * p.y; } void out() { printf( (%lld,%lld) , x, y); } } p[3 * N]; long long get(int i, int j, int k) { return (p[j] - p[i]) * (p[k] - p[j]); }; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n; cin >> n; for (int i = 0; i < (int)(n); i++) cin >> p[i].x >> p[i].y; long long s = 0; for (int i = 0; i < (int)(n); i++) s += p[i] * p[(i + 1) % n]; if (s < 0) { s = -s; reverse(p, p + n); } for (int i = 0; i < (int)(n); i++) p[i + 2 * n] = p[i + n] = p[i]; struct Calc { long long sum, s; pnt diff, diff2; Calc() : sum(0), s(0) {} void inc_r(int l, int r) { s += get(l, r, r + 1); assert(s >= 0); add(sum, s); diff2 += p[r + 1] - p[r]; diff -= diff2; } void inc_l(int l, int r) { s -= get(l, l + 1, r); pnt dp = p[l + 1] - p[l]; diff2 -= dp; diff += dp * (r - l); add(sum, dp * diff); } } c1, c2; long long res = 0; int r1 = 0, r2 = 0; for (int l = 0; l < (int)(n); l++) { while (r1 - l < n && abs(c1.s + get(l, r1, r1 + 1)) <= s / 2) { c1.inc_r(l, r1++); } assert(r1 - l <= n - 2); while (r2 - l < n - 2) c2.inc_r(l, r2++); long long mid = (2 * c1.s == s ? s / 2 : 0LL); long long big = c2.sum - c1.sum; long long small = (c1.sum - mid); add(res, big - small); c1.inc_l(l, r1); c2.inc_l(l, r2); } cout << ((res) % MOD + MOD) % MOD << endl; return 0; }
|
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_dag1_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
c top_c(clock, c_in, d_in, temp_c);
d top_d(clock, c_in, d_in, temp_d);
always @(posedge clock)
begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in & b_in;
end
endmodule
/*---------------------------------------------------------*/
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock)
begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
/*---------------------------------------------------------*/
module c(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
reg out1;
reg temp;
always @(posedge clock)
begin
temp <= c_in & d_in;
out1 <= temp ^ d_in;
end
endmodule
/*---------------------------------------------------------*/
module d(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
reg out1;
reg temp;
always @(posedge clock)
begin
temp <= c_in ^ d_in;
out1 <= temp | d_in;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; inline int read() { char c = getchar(); int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x * f; } int N, col[MAXN], son[MAXN], siz[MAXN], cnt[MAXN], Mx, Son; long long sum = 0, ans[MAXN]; vector<int> v[MAXN]; void dfs(int x, int fa) { siz[x] = 1; for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (to == fa) continue; dfs(to, x); siz[x] += siz[to]; if (siz[to] > siz[son[x]]) son[x] = to; } } void add(int x, int fa, int val) { for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (to == fa || to == Son) continue; add(to, x, val); } cnt[col[x]] += val; if (cnt[col[x]] > Mx) Mx = cnt[col[x]], sum = col[x]; else if (cnt[col[x]] == Mx) sum += (long long)col[x]; } void dfs2(int x, int fa, int opt) { for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (to == fa) continue; if (to != son[x]) dfs2(to, x, 0); } if (son[x]) dfs2(son[x], x, 1), Son = son[x]; add(x, fa, 1); Son = 0; ans[x] = sum; if (!opt) add(x, fa, -1), sum = 0, Mx = 0; } int main() { N = read(); for (int i = 1; i <= N; i++) col[i] = read(); for (int i = 1; i <= N - 1; i++) { int x = read(), y = read(); v[x].push_back(y); v[y].push_back(x); } dfs(1, 0); dfs2(1, 0, 0); for (int i = 1; i <= N; i++) printf( %I64d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; cout << 9 * n << << 8 * n << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long int INF = 9223372036854775807LL; #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroint-loops ) long long int power(long long int b, long long int e, long long int m) { if (b == 0) return 0; if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long int power(long long int b, long long int e) { if (b == 0) return 0; if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } bool isPowerOfTwo(long long int x) { return (x && !(x & (x - 1))); } void solve() { long long int n, m; cin >> n >> m; vector<long long int> v(n + 1); cin >> v[1]; for (long long int i = 2; i <= n; i++) { cin >> v[i]; v[i] += v[i - 1]; } long long int ans = 0; while (m--) { long long int a, b; cin >> a >> b; if (v[b] - v[a - 1] >= 0) ans += v[b] - v[a - 1]; } cout << ans; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int tt = 1; for (long long int i = 1; i <= tt; i++) { solve(); cout << n ; } return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Video_In_Chroma_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// file regFileBoard.v
module regFileBoard(
input wire clock,
input wire clock_debug,
input wire reset,
input wire WriteEnable,
input wire [4:0] read_address_1,
input wire [4:0] read_address_2,
input wire [4:0] read_address_3,
input wire [31:0] write_data_in,
input wire [4:0] write_address,
input wire [4:0] read_address_debug,
output reg [31:0] data_out_1,
output reg [31:0] data_out_2,
output reg [31:0] data_out_3,
output reg [31:0] data_out_debug);
integer i;
//Array of 32 registers
reg [31:0] register[0:31];
initial begin
for(i=0;i<32;i=i+1)begin
register[i] = i;
end
end
//Write only on rising edge of clock and WriteEnable is high and reset if reset is high
always @(posedge clock) begin
if(WriteEnable &&(write_address != 5'b0))begin
register[write_address] <= write_data_in;
end
if(reset)begin
for(i=0;i<32;i=i+1)begin
register[i] = i;
end
end
end
always @(negedge clock) begin
data_out_1 = register[read_address_1];
data_out_2 = register[read_address_2];
data_out_debug = register[read_address_debug];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, size = 1 << 20, mod = 998244353, inf = 2e9; const long long INF = 1e15; template <class o> void qr(o& x) { char c = getchar(); x = 0; int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); x *= f; } template <class o> void qw(o x) { if (x / 10) qw(x / 10); putchar(x % 10 + 0 ); } template <class o> void pr1(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar( ); } template <class o> void pr2(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar(10); } template <class o> void cmax(o& x, o y) { if (x < y) x = y; } void cmax(int& x, int y) { x = x - y >> 31 ? y : x; } template <class o> void cmin(o& x, o y) { if (x > y) x = y; } void cmin(int& x, int y) { x = x - y >> 31 ? x : y; } int n, m, a[N], p[N], b[N]; struct BIT { int c[N]; void clear() { memset(c + 1, 0, n * sizeof(int)); } void clear(int x) { for (; x <= n; x += x & -x) c[x] = 0; } int ask(int x) { int y = 0; for (; x; x -= x & -x) y += c[x]; return y; } int ask(int l, int r) { return ask(r) - ask(l - 1); } void add(int x, int y) { for (; x <= n; x += x & -x) c[x] += y; } } tr; struct Q { int l, r, y, v, id; Q(int _l, int _r, int _y, int _v, int _id = 0) : l(_l), r(_r), y(_y), v(_v), id(_id){}; Q(){}; bool operator<(Q b) const { return y < b.y; } } q[N * 5], t[N * 5]; int tot, ans[N], id; void cdq(int l, int r) { if (r - l < 100) { int j = 0; for (auto i = l; i <= r; i++) { if (!q[i].id) t[++j] = q[i]; else for (auto k = 1; k <= j; k++) { if (q[i].l <= t[k].l && t[k].l <= q[i].r && t[k].y <= q[i].y) ans[q[i].id] += q[i].v * t[k].v; } } sort(q + l, q + r + 1); return; } int mid = (l + r) / 2; cdq(l, mid); cdq(mid + 1, r); Q* p = t; for (int i = l, j = mid + 1; i <= mid || j <= r;) { if (j > r || (i <= mid && q[i].y <= q[j].y)) { if (!q[i].id) tr.add(q[i].l, q[i].v); *p++ = q[i++]; } else { if (q[j].id) ans[q[j].id] += q[j].v * tr.ask(q[j].l, q[j].r); *p++ = q[j++]; } } if (r - l > 2333) tr.clear(); else for (auto i = l; i <= mid; i++) if (!q[i].id) tr.clear(q[i].l); for (auto i = r; i >= l; i--) q[i] = *--p; } void solve() { qr(n); qr(m); for (auto i = 1; i <= n; i++) qr(a[i]), p[a[i]] = i; for (auto i = 1; i <= n; i++) qr(b[i]), b[i] = p[b[i]], q[++tot] = Q(i, i, b[i], 1); int op, x, y, l, r; while (m--) { qr(op); qr(x); qr(y); if (op == 1) { qr(l); qr(r); ++id; q[++tot] = Q(l, r, y, 1, id); q[++tot] = Q(l, r, x - 1, -1, id); } else { q[++tot] = Q(x, x, b[x], -1); q[++tot] = Q(y, y, b[y], -1); swap(b[x], b[y]); q[++tot] = Q(x, x, b[x], 1); q[++tot] = Q(y, y, b[y], 1); } } cdq(1, tot); for (auto i = 1; i <= id; i++) pr2(ans[i]); } int main() { int T = 1; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 15; const int mod = 1e9 + 7; const int inf = 1e9 + 3; int t, n; string a[3], s; int flag; int conv(string q) { int ans = 0; for (int i = 0; i < q.size(); i++) { ans *= 10; ans += q[i] - 0 ; } return ans; } int main() { cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == . || s[i] == e ) t++; else a[t] += s[i]; } for (int i = a[1].size() - 1; i >= 0; i--) { if (a[1][i] == 0 ) flag++; else break; } cout << a[0]; n = conv(a[2]); for (int i = 0; i < a[1].size() - flag; i++) { if (n == 0) cout << . ; n--; cout << a[1][i]; } while ((n--) > 0) cout << 0; cout << endl; }
|
/*
* This demonstrates a basic dynamic array
*/
module main;
shortreal foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long int a, b, c, t, d, e, f; long long int max(long long int x, long long int y) { if (x > y) return x; else return y; } int main() { scanf( %I64d%I64d%I64d , &a, &b, &c); t = max(a, max(b, c)); d = max(t - 1, b); e = max(t - 1, c); f = max(t - 1, a); printf( %I64d n , d - b + e - c + f - a); return 0; }
|
#include <bits/stdc++.h> using namespace std; class T { private: long node[262145]; long low[262145]; long high[262145]; void update(long n); long amount(long a, long b, long n, long n_a, long n_b); long firstUp(long k, long n, long n_a, long n_b); long firstDown(long k, long n, long n_a, long n_b); public: long amount(long a, long b); long firstUp(long k); long firstDown(long k); void pop(long n); void push(long n); long size(); T(); } WaitTree, DestTree; T::T() { for (long i = 0; i < 262145; i++) { low[i] = 1000000000; high[i] = -1000000000; } } long T::size() { return node[1]; } long T::amount(long a, long b, long n, long n_a, long n_b) { if (a > n_b || b < n_a) return 0; if (n_a >= a && n_b <= b) return node[n]; return amount(a, b, 2 * n, n_a, (n_a + n_b) / 2) + amount(a, b, 2 * n + 1, (n_a + n_b) / 2 + 1, n_b); } long T::firstDown(long k, long n, long n_a, long n_b) { if (node[n] == 0 || n_a > k) return -1000000000; if (n > 131071) return n - 131071; if (n_b > k) { long a = firstDown(k, 2 * n + 1, (n_a + n_b) / 2 + 1, n_b); if (a > 0) return a; return firstDown(k, 2 * n, n_a, (n_a + n_b) / 2); } else return high[n]; } long T::firstUp(long k, long n, long n_a, long n_b) { if (node[n] == 0 || n_b < k) return 1000000000; if (n > 131071) return n - 131071; if (n_a < k) { long a = firstUp(k, 2 * n, n_a, (n_a + n_b) / 2); if (a < 1000000000) return a; return firstUp(k, 2 * n + 1, (n_a + n_b) / 2 + 1, n_b); } else return low[n]; } long T::firstUp(long k) { return firstUp(k, 1, 1, 131071 + 1); } long T::firstDown(long k) { return firstDown(k, 1, 1, 131071 + 1); } long T::amount(long a, long b) { return amount(a, b, 1, 1, 131071 + 1); } void T::update(long n) { n /= 2; while (n > 0) { low[n] = (low[2 * n + 1] < low[2 * n] ? low[2 * n + 1] : low[2 * n]); high[n] = (high[2 * n] > high[2 * n + 1] ? high[2 * n] : high[2 * n + 1]); node[n] = node[2 * n] + node[2 * n + 1]; n /= 2; } } void T::pop(long n) { node[131071 + n]--; if (node[131071 + n] == 0) { low[131071 + n] = 1000000000; high[131071 + n] = -1000000000; } update(131071 + n); } void T::push(long n) { high[131071 + n] = n; low[131071 + n] = n; node[131071 + n]++; update(131071 + n); } struct A { long id; long time, wait, dest; }; bool operator<(const A &a, const A &b) { return a.time < b.time; } vector<A> P(100005); class X { public: long id, floor; X(long _id, long _floor); }; X::X(long _id, long _floor) { id = _id; floor = _floor; } vector<X> Waiting[100005]; vector<X> Dest[100005]; long long Arrive[100005]; long Arrived; long N, M; void in() { scanf( %ld %ld , &N, &M); for (long i = 0; i < N; i++) { scanf( %ld %ld %ld , &P[i].time, &P[i].wait, &P[i].dest); P[i].id = i; } sort(P.begin(), P.begin() + N); } void processEvent(long f, long long t, long &nextP) { X x(0, 0); while (P[nextP].time == t && nextP < N) { Waiting[P[nextP].wait].push_back(X(P[nextP].id, P[nextP].dest)); WaitTree.push(P[nextP].wait); nextP++; } while (Waiting[f].size() > 0) { x = Waiting[f].back(); Dest[x.floor].push_back(X(x.id, x.floor)); WaitTree.pop(f); DestTree.push(x.floor); Waiting[f].pop_back(); } while (Dest[f].size() > 0) { x = Dest[f].back(); Arrive[x.id] = t; Arrived++; DestTree.pop(f); Dest[f].pop_back(); } } void solve() { const int UP = 1; const int DOWN = 2; int dir; long nextMove; long nextP = 0; long p_up, p_down; long f = 1; long long t = 0; while (Arrived < N) { processEvent(f, t, nextP); p_up = p_down = 0; p_up += WaitTree.amount(f, 131071 + 1); p_up += DestTree.amount(f, 131071 + 1); p_down += WaitTree.amount(1, f); p_down += DestTree.amount(1, f); if (p_up >= p_down) dir = UP; else dir = DOWN; if (dir == UP) { nextMove = 1000000000; nextMove = (nextMove < WaitTree.firstUp(f) - f ? nextMove : WaitTree.firstUp(f) - f); nextMove = (nextMove < DestTree.firstUp(f) - f ? nextMove : DestTree.firstUp(f) - f); if (nextP < N) nextMove = (nextMove < P[nextP].time - t ? nextMove : P[nextP].time - t); t += nextMove; if (DestTree.size() > 0 || WaitTree.size() > 0) { f += nextMove; } } if (dir == DOWN) { nextMove = 1000000000; nextMove = (nextMove < f - WaitTree.firstDown(f) ? nextMove : f - WaitTree.firstDown(f)); nextMove = (nextMove < f - DestTree.firstDown(f) ? nextMove : f - DestTree.firstDown(f)); if (nextP < N) nextMove = (nextMove < P[nextP].time - t ? nextMove : P[nextP].time - t); t += nextMove; if (DestTree.size() > 0 || WaitTree.size() > 0) { f -= nextMove; } } } } void out() { for (long i = 0; i < N; i++) printf( %I64d n , Arrive[i]); } int main() { in(); solve(); out(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int st, en; } TV[200010]; bool cmp(node a, node b) { if (a.st == b.st) { return a.en < b.en; } return a.st < b.st; } int main() { int n; int tv1, tv2; int flag; cin >> n; tv1 = -1; tv2 = -1; flag = 1; for (int i = 0; i < n; i++) { cin >> TV[i].st >> TV[i].en; } sort(TV, TV + n, cmp); for (int i = 0; i < n && flag; i++) { if (tv1 < TV[i].st) { tv1 = TV[i].en; } else { if (tv2 < TV[i].st) { tv2 = TV[i].en; } else { flag = 0; } } } if (flag) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_1_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_1_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog wrapper for muxb16to1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb16to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_1 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int su[N], lst[N], n, i, a, lim; long long ans; pair<int, int> b[N]; int xb; inline int calc(int k) { int i, j; long long s = 0, ans = -1, x, y, z; xb = 0; for (i = 0; i * k < N; ++i) { s += 1ll * i * (su[min(N - 1, (i + 1) * k - 1)] - (i ? su[i * k - 1] : 0)); x = lst[min(N - 1, (i + 1) * k)]; if (x && x >= i * k) { y = su[x] - su[x - 1] > 1 ? x : lst[x]; if (y >= i * k) b[++xb] = make_pair(i, y - i * k); b[++xb] = make_pair(i, x - i * k); } } for (i = 1; i <= xb; ++i) { z = 2 * s - b[i].second; x = z <= 0 ? 0 : (z - 1) / (k + 2) + 1; if (x <= b[i].first) ans = max(ans, s - x); } y = -1; if (k == 7) { ++k, --k; } for (i = xb; i; --i) { if (y >= 0) { z = s - min(1ll * b[i].second, y); x = z <= 0 ? 0 : (z - 1) / (k + 2) + 1; if (x <= b[i].first) ans = max(ans, s - x * 2); } y = max(y, 1ll * b[i].second); } y = -1; for (i = xb; i; --i) { if (b[i].first < b[xb].first) { z = s - 1 - b[i].second; x = z <= 0 ? 0 : (z - 1) / (k + 2) + 1; if (x <= b[i].first) ans = max(ans, s - x * 2 - 1); } if (y >= 0) { z = s + 1 + k - y; x = z <= 0 ? 0 : (z - 1) / (k + 2) + 1; if (x <= b[i].first) ans = max(ans, s - x * 2 + 1); } y = max(y, 1ll * b[i].second); } return ans == -1 ? lim : (ans < 2 ? 0 : ans); } int main() { scanf( %d , &n); for (i = 0; i < n; ++i) scanf( %d , &a), ++su[a]; for (i = 1; i < N; ++i) lst[i] = su[i - 1] ? i - 1 : lst[i - 1]; a = lst[N - 1]; lim = max(a / 2, su[a] > 1 ? a : lst[a]); for (i = 1; i < N; ++i) su[i] += su[i - 1]; for (i = 2; i < N; ++i) ans = max(ans, 1ll * i * calc(i)); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[1000010]; bool f[1000010]; int main() { int i, l, ans = 0, ans2 = 0, j, sta; scanf( %s , &s); l = strlen(s); sta = 0; while (s[sta] == s[(sta + 1) % l]) { sta = (sta + 1) % l; } ++sta; memset(f, false, sizeof(bool) * l); i = sta; while (!f[i]) { f[i] = true; i = (i + l - 1) % l; while (s[(i + l - 1) % l] == s[i]) { f[i] = true; i = (i + l - 1) % l; } f[i] = true; i = (i + l - 1) % l; ++ans; } memset(f, false, sizeof(bool) * l); i = sta; while (!f[i]) { f[i] = true; while (s[(i + 1) % l] == s[i]) { i = (i + 1) % l; f[i] = true; } f[(i + 1) % l] = true; i = (i + 2) % l; ++ans2; } printf( %d n , ans < ans2 ? ans : ans2); return 0; }
|
#include <bits/stdc++.h> using namespace std; long int temp, i, j, k, T; int main() { int n, a, b; cin >> n >> a >> b; int h[2007]; for (i = 0; i < n; i++) cin >> h[i]; sort(h, h + n); int val = h[b - 1]; if (h[b] == val) cout << 0 << endl; else cout << h[b] - val << endl; return 0; }
|
module ID_STAGE (
input clk,
input rst,
input ID_Zero,
input ID_RegWriteEn,
input [2:0] ID_RegWriteDest,
input [15:0] ID_RegWriteData,
input [15:0] ID_In,
input [15:0] ID_Controller,
output [15:0] ID_AluSrc1,
output [15:0] ID_AluSrc2,
output [15:0] ID_MemWriteData,
output [2:0] ID_RFWriteBackDest,
output ID_MemWriteEn,
output ID_WriteBackResultMux,
output ID_RFWriteBackEn,
output [3:0] ID_ALUCmd,
output ID_jump,
output ID_branch,
output [2:0] ID_op1,
output [2:0] ID_op2
);
wire [15:0] sixteenExtended;
wire RFWriteDestMux;
wire Add2Mux;
wire Data2Mux;
wire MemWriteDataMux;
wire [2:0] Add2MuxAddress;
wire [15:0] RegisterFileData2;
SixToSixteen mySixToSixteen(
.In(ID_In[5:0]),
.Out(sixteenExtended)
);
MUX2 #(16) myData2Mux2(
.SLCT(Data2Mux),
.IN1(sixteenExtended),
.IN0(RegisterFileData2),
.OT(ID_AluSrc2)
);
MUX2 #(3) myAdd2Mux2(
.SLCT(Add2Mux),
.IN1(ID_In[11:9]),
.IN0(ID_In[5:3]),
.OT(Add2MuxAddress)
);
assign ID_op1 = ID_In[8:6];
assign ID_op2 = Add2MuxAddress;
RegisterFile myRegisterFile(
.clk(clk),
.rst(rst),
.rg_wrt_enable(ID_RegWriteEn),
.rg_wrt_dest(ID_RegWriteDest),
.rg_wrt_data(ID_RegWriteData),
.rg_rd_addr1(ID_In[8:6]),
.rg_rd_data1(ID_AluSrc1),
.rg_rd_addr2(Add2MuxAddress),
.rg_rd_data2(RegisterFileData2)
);
MUX2 #(16) myMemWriteDataMux2(
.SLCT(MemWriteDataMux),
.IN1(RegisterFileData2),
.IN0(16'b0),
.OT(ID_MemWriteData)
);
MUX2 #(3) myWriteDestMux2(
.SLCT(RFWriteDestMux),
.IN1(ID_In[11:9]),
.IN0(3'b0),
.OT(ID_RFWriteBackDest)
);
CONTROLLER myController(
.clock(clk),
.In(ID_Controller),
.Zero(ID_Zero),
.alu_cmd(ID_ALUCmd),
.rf_write_back_en(ID_RFWriteBackEn),
.write_back_result_mux(ID_WriteBackResultMux),
.mem_write_en(ID_MemWriteEn),
.rf_write_dest_mux(RFWriteDestMux),
.add_2_mux(Add2Mux),
.data_2_mux(Data2Mux),
.mem_write_mux(MemWriteDataMux),
.branchEn(ID_branch),
.jump(ID_jump)
);
endmodule
|
Require Import Iron.Tactics.LibTactics.
Require Import Iron.Tactics.Rewrite.
Require Import Iron.Tactics.Rip.
Require Import Omega.
Ltac rs := rewritess.
Ltac rr := autorewrite with global in *.
(********************************************************************)
(* Burn mega-tactic for semantics proofs.
* This gets lots of the common cases, where Coq really should
have tried a bit harder. For example, trying f_equal before eauto.
* It also contains cases for patterns that often arise when using
the deBruijn representation. For example, trying false before
omega to show that a case concerning index manipulation
cannot happen.
* Failing is sometimes slow due to the (firstorder burn0) tactic
in burn1.
*)
(* Primitive tactics that fail quickly. *)
Ltac burn0
:= first
[ assumption (* Goal is one of the assumptions. *)
| reflexivity (* Goal has form e = e. *)
| solve [eauto] (* Resolution based proving *)
| omega (* Solves inequalities with Presburger arithmetic. *)
| false; omega ]. (* Solves inequalities with Presburger arithmetic. *)
(* Try the firstorder solver.
This can be slow if it fails. *)
Ltac burn1
:= first
[ burn0
| solve [firstorder burn0] ].
(* Try to factor the goal in some other way before applying
one of the primitive tactics. *)
Ltac burn2
:= first
[ burn1
| f_equal; burn1 ].
(* Apply normalising rewrite rules in various combinations.
We need to try different combinations. Simplifying can cause rewrite
rules not to fire, or to not have the form required for a auto rule,
so we want to try burn2 before and after rewrites. *)
Ltac burn3
:= first [ burn2
| try rr;
first [ burn2
| try rs;
first [ burn2
| simpl; burn2 ]]].
(* Apply common factorings that should always make goals easier
to solve.
Try to use injectivity between two constructor applications.
These are common when we lookup values from the environment,
eg with get ix tyenv = Some t1. *)
Ltac burn4
:= rip; match goal with
[ H1 : _ = ?C ?y1
, H2 : _ = ?C ?y2 |- _]
=> assert (y1 = y2); rewrite H1 in H2; inverts H2; burn3
| [ H1 : ?C ?y1 = _
, H2 : ?C ?y2 = _ |- _]
=> assert (y1 = y2); rewrite H1 in H2; inverts H2; burn3
| _ => burn3
end.
(* Top-level megatactic.
Try some simple, fast things first, then try everything. *)
Ltac burn
:= first [burn0 | burn4].
(********************************************************************)
(* Assert a statement and prove it via burn.
This leads to more structured proving than using plain 'assert',
because a 'have' form must always complete the goal. *)
Tactic Notation "have" constr(E) :=
let H := fresh
in assert E as H by burn.
Tactic Notation "have" constr(E) "as" ident(H) :=
assert E as H by burn.
Tactic Notation "have" constr(E) "by" tactic(T) :=
let H := fresh
in assert E as H by T.
Tactic Notation "have" constr(E) "as" ident(H) "by" tactic(T) :=
assert E as H by T.
(* Rewrite using burn.
Just state the equality to use. *)
Tactic Notation "rrwrite" constr(xx)
:= let H := fresh
in assert xx as H by burn; rewrite H; clear H.
Tactic Notation "rrwrite" constr(xx) "in" hyp(H)
:= let H2 := fresh
in assert xx as H2 by burn; rewrite H2 in H; clear H2.
Tactic Notation "rw" constr(xx) := rrwrite xx.
Tactic Notation "rw" constr(xx) "in" hyp(H) := rrwrite xx in H.
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 100010; inline int read() { int x = 0, f = 1; char ch = 0; while (!isdigit(ch)) { ch = getchar(); if (ch == - ) f = -1; } while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); return x * f; } int n, m; int a[maxn], b[maxn], low[maxn], pre[maxn], f[maxn], la[maxn]; int gap[maxn]; void work() { memset(low, 63, sizeof(low)); pre[1] = low[1] = 0, f[1] = la[1] = 1; for (int k = 2; k <= n; ++k) { if (a[k] + 1) { int L = 1, R = n; while (L <= R) { int mid = (L + R) >> 1; if (low[mid] < a[k]) L = mid + 1; else R = mid - 1; } pre[k] = la[L - 1]; la[L] = k; f[k] = L, low[L] = a[k]; } else { pre[k] = -1, f[k] = -1; int j = n; for (int i = m; i >= 1; i--) { while (low[j] >= b[i]) j--; low[j + 1] = b[i], la[j + 1] = -1; } } } } void work2() { int L, R, rem = m; int x = n; while (x) if (a[x] + 1) { if (pre[x] >= 0) { x = pre[x]; continue; } R = lower_bound(b + 1, b + rem + 1, a[x]) - b - 1; for (int y = x - 1; y != 0; y--) { if (a[y] == -1 || a[y] >= a[x]) continue; L = upper_bound(b + 1, b + rem + 1, a[y]) - b; if (f[x] - f[y] - 1 == min(R - L + 1, gap[x] - gap[y])) { for (int i = y, j = L; i <= x && j <= R; i++) if (a[i] == -1) a[i] = b[j], b[j] = -1, j++; x = y; rem = L - 1; break; } } } for (int i = 1, j = 1; i <= n; ++i) { if (a[i] + 1) continue; while (b[j] == -1) ++j; a[i] = b[j]; b[j++] = -1; } } int main() { n = read(); a[1] = 0; a[n + 2] = INF; for (int i = 2; i <= n + 1; ++i) a[i] = read(), gap[i] = gap[i - 1] + (a[i] == -1); m = read(); gap[n + 2] = gap[n + 1]; n += 2; for (int i = 1; i <= m; ++i) b[i] = read(); sort(b + 1, b + m + 1); m = unique(b + 1, b + m + 1) - b - 1; work(); work2(); for (int i = 2; i < n; ++i) printf( %d , a[i]); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:07:18 03/23/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(A, B, C0, F, C4
);
parameter SIZE = 4;
input [SIZE-1: 0] A, B;
input C0;
output [SIZE-1: 0] F;
output C4;
wire C1, C2, C3;
wire G0, G1, G2, G3;
wire P0, P1, P2, P3;
Gi G_0(A[0], B[0], G0);
Gi G_1(A[1], B[1], G1);
Gi G_2(A[2], B[2], G2);
Gi G_3(A[3], B[3], G3);
Pi P_0(A[0], B[0], P0);
Pi P_1(A[1], B[1], P1);
Pi P_2(A[2], B[2], P2);
Pi P_3(A[3], B[3], P3);
FA FA1(A[0], B[0], C0, F[0]);
FA FA2(A[1], B[1], C1, F[1]);
FA FA3(A[2], B[2], C2, F[2]);
FA FA4(A[3], B[3], C3, F[3]);
assign C1 = G0 | P0&C0;
assign C2 = G1 | P1&G0 | P1&P0&C0;
assign C3 = G2 | P2&G1 | P2&P1&G0 | P2&P1&P0&C0;
assign C4 = G3 | P3&G2 | P3&P2&G1 | P3&P2&P1&G0 | P3&P2&P1&P0&C0;
endmodule
module FA(A, B, C, F);
input A, B, C;
output F;
assign F = A^B^C;
endmodule
module Gi(input A, input B, output G);
assign G = A&B;
endmodule
module Pi(input A, input B, output P);
assign P = A|B;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Alex Solomatnikov.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [6-1:0] foo[4-1:0];
//initial $display("%m: %p\n", foo);
//initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice
//logic [6-1:0] foo2[4-1:0][5:6];
//initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal
dut #(.W(6),
.D(4)) udut(.clk(clk),
.foo(foo[4-1:0]));
endmodule
module dut
#(parameter W = 1,
parameter D = 1)
(input logic clk,
input logic [W-1:0] foo[D-1:0]);
genvar i, j;
generate
for (j = 0; j < D; j++) begin
for (i = 0; i < W; i++) begin
suba ua(.clk(clk), .foo(foo[j][i]));
end
end
endgenerate
endmodule
module suba
(input logic clk,
input logic foo);
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long n, ans, dp[200005][3], sz[200005][3]; vector<int> gr[200005]; void dfs(int x, int p) { sz[x][0]++; for (int i = 0; i < gr[x].size(); i++) { int u = gr[x][i]; if (u == p) continue; dfs(u, x); dp[x][0] += dp[u][1] + sz[u][1] + 1; dp[x][1] += dp[u][0] + sz[u][0]; sz[x][0] += sz[u][0]; sz[x][1] += sz[u][1]; } } void root(int x, int p) { ans += dp[x][0]; for (int i = 0; i < gr[x].size(); i++) { int u = gr[x][i]; if (u == p) continue; dp[x][0] -= dp[u][1] + sz[u][1] + 1; dp[x][1] -= dp[u][0] + sz[u][0]; sz[x][0] -= sz[u][0]; sz[x][1] -= sz[u][1]; sz[u][1] += sz[x][1]; sz[u][0] += sz[x][0]; dp[u][1] += dp[x][0] + sz[x][0]; dp[u][0] += dp[x][1] + sz[x][1] + 1; root(u, x); dp[u][0] -= dp[x][1] + sz[x][1] + 1; dp[u][1] -= dp[x][0] + sz[x][0]; sz[u][0] -= sz[x][0]; sz[u][1] -= sz[x][1]; sz[x][1] += sz[u][1]; sz[x][0] += sz[u][0]; dp[x][1] += dp[u][0] + sz[u][0]; dp[x][0] += dp[u][1] + sz[u][1] + 1; } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; gr[x].push_back(y); gr[y].push_back(x); } dfs(1, 0); root(1, 0); cout << ans / 2; }
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout,
output reg frame_start,
output reg frame_end
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
reg frame_d, frame_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
frame_d = ss_q;
frame_start = 1'b0;
frame_end = 1'b0;
if (frame_q == 1'b1 && ss_q == 1'b0)
frame_start = 1'b1;
if (frame_q == 1'b0 && ss_q == 1'b1)
frame_end = 1'b1;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end else if (!sck_q) begin
if (bit_ct_q == 3'd0) begin
miso_d = din[7];
data_d = din;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
frame_q <= frame_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n, m; cin >> n >> m; vector<long long int> dp(n + 1); vector<pair<pair<long long int, long long int>, pair<long long int, long long int>>> input; for (long long int i = 1; i <= m; i++) { long long int s, d, c; cin >> s >> d >> c; input.push_back({{d, c}, {s, i}}); dp[d] = m + 1; } sort(input.begin(), input.end()); for (int i = 1; i <= n; i++) { int flag = 0; if (dp[i] == m + 1) continue; for (int j = 0; j < m; j++) { if (input[j].second.first <= i && input[j].first.second > 0 && input[j].first.first > i) { dp[i] = input[j].second.second; input[j].first.second--; flag = 1; break; } } if (!flag) dp[i] = 0; } int flag = 1; for (int i = 0; i < m; i++) { if (input[i].first.second != 0) flag = 0; } if (!flag) cout << -1; else for (int i = 1; i <= n; i++) cout << dp[i] << ; }
|
/*
This file is part of avgai.
avgai is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
avgai is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with avgai. If not, see <http://www.gnu.org/licenses/>.
Copyright Dakota Fisher 2014
*/
module counterModulo(clk, modulo, count, oClk);
parameter n = 10, safe = 1;
input clk;
input [n-1:0] modulo;
output reg [n-1:0] count = 0;
output oClk;
assign oClk = count+1 == modulo ? 1 :
count+1 < modulo ? 0 :
safe ? 1 : 1'bx;
always @(posedge clk)
if (!oClk)
count <= count + 1;
else
count <= 0;
endmodule
// I haven't bothered, but this can be made much more elegant by not using the
// FSM model I used here and instead just doing the arithmetic. In addition,
// each stage can generate its own "need" and "sync" signals quite easily, so
// the "stages" are irrelevant. Also, the supporting counterModulo doesn't need
// to vary its count
// The reason I haven't is because it would basically be a complete re-write
// and getting the timing just right was problematic the first time.
module vgaRotatingCounter(input clk, reset_,
output reg [1:0] stage,
output [9:0] count,
output reg outClk);
parameter ta = 96, tb = 16, tc = 640, td = 48;
localparam A = 0, B = 1, C = 2, D = 3;
wire stageClk;
wire [9:0] modulo;
assign modulo = stage == A ? ta :
stage == B ? tb :
stage == C ? tc :
td;
counterModulo #(10,0) c(clk, modulo, count, stageClk);
always @(posedge clk)
if (stageClk) begin
if (stage == D)
outClk <= 1;
stage <= stage + 1;
end else
outClk <= 0;
endmodule
module vgaControl(input clk, reset_,
output reg VGA_VS, VGA_HS,
output need,
output [9:0] hNeed, vNeed);
parameter n = 4;
/* // 640x480 // Don't forget to divide clock by 2
parameter ha = 96, hb = 48, hc = 640, hd = 16;
parameter va = 2, vb = 33, vc = 480, vd = 10;
*/
// 800x600
parameter ha = 120, hb = 64, hc = 800, hd = 56;
parameter va = 6, vb = 23, vc = 600, vd = 37;
wire [1:0] hStage, vStage;
wire [9:0] hCount, vCount;
wire hClock, vClock, vEnd;
always @(posedge clk) begin
VGA_HS <= hStage != 0;
VGA_VS <= vStage != 0;
end
assign need = vStage == 2 && ((hStage == 2 && hCount != hc-1)
|| (hStage == 1 && hCount == hb-1));
assign hNeed = hStage == 2 ? hCount+1 : 0;
assign vNeed = vCount;
assign hClock = clk;
vgaRotatingCounter #(ha, hb, hc, hd) h(hClock, 1, hStage, hCount, vClock);
vgaRotatingCounter #(va, vb, vc, vd) v(vClock, 1, vStage, vCount, vEnd);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { if (n == 1 || n == 2) cout << -1 n ; else if (n == 3) cout << 210 n ; else { if (n % 6 == 1) { cout << 1 ; for (int i = 3; i < n; i++) cout << 0 ; cout << 20 n ; } if (n % 6 == 2) { cout << 1 ; for (int i = 3; i < n - 1; i++) cout << 0 ; cout << 200 n ; } if (n % 6 == 3) { cout << 1 ; for (int i = 3; i < n - 1; i++) cout << 0 ; cout << 110 n ; } if (n % 6 == 4) { cout << 1 ; for (int i = 3; i < n; i++) cout << 0 ; cout << 50 n ; } if (n % 6 == 5) { cout << 1 ; for (int i = 3; i < n; i++) cout << 0 ; cout << 80 n ; } if (n % 6 == 0) { cout << 1 ; for (int i = 3; i < n - 1; i++) cout << 0 ; cout << 170 n ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long m, l, r, k, n; long long a[2][2], b[2][2]; void cc(long long a[2][2], long long b[2][2]) { for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) a[i][j] = b[i][j]; } void mul(long long a[2][2], long long b[2][2], long long m) { long long c[2][2]; memset(c, 0, sizeof(c)); for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) c[i][j] += a[i][k] * b[k][j], c[i][j] %= m; cc(a, c); } void mi(long long a[2][2], long long n, long long m) { long long y[2][2]; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) y[i][j] = 0; y[0][0] = 1; y[1][1] = 1; while (n > 0) { if (n % 2 == 1) mul(y, a, m); n = n / 2; mul(a, a, m); } cc(a, y); } int main() { cin >> m >> l >> r >> k; n = -1; for (long long i = k;; i++) { long long x = r / i; long long y = r / x; long long z = (l - 1) / x; if (x <= 1000000) break; if (y - z >= k) { n = x; break; } } if (n == -1) for (long long i = 1000000; i >= 1; i--) { long long y = r / i; long long z = (l - 1) / i; if (y - z >= k) { n = i; break; } } a[0][1] = 1; a[1][0] = 1; a[1][1] = 1; b[0][1] = 1; b[0][0] = 1; mi(a, n - 2, m); mul(b, a, m); cout << b[0][1] << endl; }
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#include <bits/stdc++.h> using namespace std; int dx8[] = {0, 0, 1, 1, 1, -1, -1, -1}; int dy8[] = {1, -1, 1, -1, 0, 0, -1, 1}; const double PI = acos(-1.0); const double EPS = 1e-6; const int MOD = (int)1e9 + 7; const int maxn = (int)2e5 + 5; int cnt[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n, m, i, j; cin >> n >> m; set<int> s; for (i = 1; i <= (m); i++) { int x; cin >> x; cnt[x]++; s.insert(x); if ((int)s.size() == n) { cout << 1 ; for (j = 1; j <= (n); j++) { cnt[j]--; if (cnt[j] == 0) s.erase(j); } } else cout << 0 ; } }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:41:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/zynq_design_1_system_ila_0_stub.v
// Design : zynq_design_1_system_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_350b,Vivado 2017.2" *)
module zynq_design_1_system_ila_0(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready,
SLOT_0_AXI_araddr, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, SLOT_1_GPIO_tri_o,
SLOT_2_AXI_awid, SLOT_2_AXI_awaddr, SLOT_2_AXI_awlen, SLOT_2_AXI_awsize,
SLOT_2_AXI_awburst, SLOT_2_AXI_awlock, SLOT_2_AXI_awcache, SLOT_2_AXI_awprot,
SLOT_2_AXI_awqos, SLOT_2_AXI_awvalid, SLOT_2_AXI_awready, SLOT_2_AXI_wdata,
SLOT_2_AXI_wstrb, SLOT_2_AXI_wlast, SLOT_2_AXI_wvalid, SLOT_2_AXI_wready, SLOT_2_AXI_bid,
SLOT_2_AXI_bresp, SLOT_2_AXI_bvalid, SLOT_2_AXI_bready, SLOT_2_AXI_arid,
SLOT_2_AXI_araddr, SLOT_2_AXI_arlen, SLOT_2_AXI_arsize, SLOT_2_AXI_arburst,
SLOT_2_AXI_arlock, SLOT_2_AXI_arcache, SLOT_2_AXI_arprot, SLOT_2_AXI_arqos,
SLOT_2_AXI_arvalid, SLOT_2_AXI_arready, SLOT_2_AXI_rid, SLOT_2_AXI_rdata,
SLOT_2_AXI_rresp, SLOT_2_AXI_rlast, SLOT_2_AXI_rvalid, SLOT_2_AXI_rready, resetn,
TRIG_IN_trig, TRIG_IN_ack, TRIG_OUT_trig, TRIG_OUT_ack)
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_GPIO_tri_o[7:0],SLOT_2_AXI_awid[11:0],SLOT_2_AXI_awaddr[15:0],SLOT_2_AXI_awlen[7:0],SLOT_2_AXI_awsize[2:0],SLOT_2_AXI_awburst[1:0],SLOT_2_AXI_awlock[0:0],SLOT_2_AXI_awcache[3:0],SLOT_2_AXI_awprot[2:0],SLOT_2_AXI_awqos[3:0],SLOT_2_AXI_awvalid,SLOT_2_AXI_awready,SLOT_2_AXI_wdata[31:0],SLOT_2_AXI_wstrb[3:0],SLOT_2_AXI_wlast,SLOT_2_AXI_wvalid,SLOT_2_AXI_wready,SLOT_2_AXI_bid[11:0],SLOT_2_AXI_bresp[1:0],SLOT_2_AXI_bvalid,SLOT_2_AXI_bready,SLOT_2_AXI_arid[11:0],SLOT_2_AXI_araddr[15:0],SLOT_2_AXI_arlen[7:0],SLOT_2_AXI_arsize[2:0],SLOT_2_AXI_arburst[1:0],SLOT_2_AXI_arlock[0:0],SLOT_2_AXI_arcache[3:0],SLOT_2_AXI_arprot[2:0],SLOT_2_AXI_arqos[3:0],SLOT_2_AXI_arvalid,SLOT_2_AXI_arready,SLOT_2_AXI_rid[11:0],SLOT_2_AXI_rdata[31:0],SLOT_2_AXI_rresp[1:0],SLOT_2_AXI_rlast,SLOT_2_AXI_rvalid,SLOT_2_AXI_rready,resetn,TRIG_IN_trig[0:0],TRIG_IN_ack[0:0],TRIG_OUT_trig[0:0],TRIG_OUT_ack[0:0]" */;
input clk;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_awready;
input [31:0]SLOT_0_AXI_wdata;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input SLOT_0_AXI_wready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input SLOT_0_AXI_bready;
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arvalid;
input SLOT_0_AXI_arready;
input [31:0]SLOT_0_AXI_rdata;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input SLOT_0_AXI_rready;
input [7:0]SLOT_1_GPIO_tri_o;
input [11:0]SLOT_2_AXI_awid;
input [15:0]SLOT_2_AXI_awaddr;
input [7:0]SLOT_2_AXI_awlen;
input [2:0]SLOT_2_AXI_awsize;
input [1:0]SLOT_2_AXI_awburst;
input [0:0]SLOT_2_AXI_awlock;
input [3:0]SLOT_2_AXI_awcache;
input [2:0]SLOT_2_AXI_awprot;
input [3:0]SLOT_2_AXI_awqos;
input SLOT_2_AXI_awvalid;
input SLOT_2_AXI_awready;
input [31:0]SLOT_2_AXI_wdata;
input [3:0]SLOT_2_AXI_wstrb;
input SLOT_2_AXI_wlast;
input SLOT_2_AXI_wvalid;
input SLOT_2_AXI_wready;
input [11:0]SLOT_2_AXI_bid;
input [1:0]SLOT_2_AXI_bresp;
input SLOT_2_AXI_bvalid;
input SLOT_2_AXI_bready;
input [11:0]SLOT_2_AXI_arid;
input [15:0]SLOT_2_AXI_araddr;
input [7:0]SLOT_2_AXI_arlen;
input [2:0]SLOT_2_AXI_arsize;
input [1:0]SLOT_2_AXI_arburst;
input [0:0]SLOT_2_AXI_arlock;
input [3:0]SLOT_2_AXI_arcache;
input [2:0]SLOT_2_AXI_arprot;
input [3:0]SLOT_2_AXI_arqos;
input SLOT_2_AXI_arvalid;
input SLOT_2_AXI_arready;
input [11:0]SLOT_2_AXI_rid;
input [31:0]SLOT_2_AXI_rdata;
input [1:0]SLOT_2_AXI_rresp;
input SLOT_2_AXI_rlast;
input SLOT_2_AXI_rvalid;
input SLOT_2_AXI_rready;
input resetn;
input [0:0]TRIG_IN_trig;
output [0:0]TRIG_IN_ack;
output [0:0]TRIG_OUT_trig;
input [0:0]TRIG_OUT_ack;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a[200001]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { int x, y; scanf( %d %d , &x, &y); a[x].push_back(y); } set<pair<int, int> > S; for (int i = 1; i <= n; i++) { sort(a[i].begin(), a[i].end()); if (!a[i].empty()) { S.insert(make_pair(a[i][a[i].size() - 1], i)); } } int q; cin >> q; while (q--) { int k; scanf( %d , &k); vector<pair<int, int> > temp; for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); if (a[x].size()) { S.erase(make_pair(a[x][a[x].size() - 1], x)); temp.push_back(make_pair(a[x][a[x].size() - 1], x)); } } if (S.size() == 0) { cout << 0 0 n ; } else if (S.size() == 1) { set<pair<int, int> >::iterator it; it = S.begin(); int x = it->second, y = it->first; printf( %d %d n , x, a[x][0]); } else { set<pair<int, int> >::reverse_iterator it; it = S.rbegin(); int u = it->second; it++; int x = it->second, y = it->first; int ans = *upper_bound(a[u].begin(), a[u].end(), y); printf( %d %d n , u, ans); } for (int i = 0; i < temp.size(); i++) { S.insert(temp[i]); } } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:14:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_xbar_0/system_xbar_0_stub.v
// Design : system_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module system_xbar_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[5:0],s_axi_awaddr[95:0],s_axi_awlen[23:0],s_axi_awsize[8:0],s_axi_awburst[5:0],s_axi_awlock[2:0],s_axi_awcache[11:0],s_axi_awprot[8:0],s_axi_awqos[11:0],s_axi_awvalid[2:0],s_axi_awready[2:0],s_axi_wdata[191:0],s_axi_wstrb[23:0],s_axi_wlast[2:0],s_axi_wvalid[2:0],s_axi_wready[2:0],s_axi_bid[5:0],s_axi_bresp[5:0],s_axi_bvalid[2:0],s_axi_bready[2:0],s_axi_arid[5:0],s_axi_araddr[95:0],s_axi_arlen[23:0],s_axi_arsize[8:0],s_axi_arburst[5:0],s_axi_arlock[2:0],s_axi_arcache[11:0],s_axi_arprot[8:0],s_axi_arqos[11:0],s_axi_arvalid[2:0],s_axi_arready[2:0],s_axi_rid[5:0],s_axi_rdata[191:0],s_axi_rresp[5:0],s_axi_rlast[2:0],s_axi_rvalid[2:0],s_axi_rready[2:0],m_axi_awid[1:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[1:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[1:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[1:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]" */;
input aclk;
input aresetn;
input [5:0]s_axi_awid;
input [95:0]s_axi_awaddr;
input [23:0]s_axi_awlen;
input [8:0]s_axi_awsize;
input [5:0]s_axi_awburst;
input [2:0]s_axi_awlock;
input [11:0]s_axi_awcache;
input [8:0]s_axi_awprot;
input [11:0]s_axi_awqos;
input [2:0]s_axi_awvalid;
output [2:0]s_axi_awready;
input [191:0]s_axi_wdata;
input [23:0]s_axi_wstrb;
input [2:0]s_axi_wlast;
input [2:0]s_axi_wvalid;
output [2:0]s_axi_wready;
output [5:0]s_axi_bid;
output [5:0]s_axi_bresp;
output [2:0]s_axi_bvalid;
input [2:0]s_axi_bready;
input [5:0]s_axi_arid;
input [95:0]s_axi_araddr;
input [23:0]s_axi_arlen;
input [8:0]s_axi_arsize;
input [5:0]s_axi_arburst;
input [2:0]s_axi_arlock;
input [11:0]s_axi_arcache;
input [8:0]s_axi_arprot;
input [11:0]s_axi_arqos;
input [2:0]s_axi_arvalid;
output [2:0]s_axi_arready;
output [5:0]s_axi_rid;
output [191:0]s_axi_rdata;
output [5:0]s_axi_rresp;
output [2:0]s_axi_rlast;
output [2:0]s_axi_rvalid;
input [2:0]s_axi_rready;
output [1:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awvalid;
input [0:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [0:0]m_axi_wlast;
output [0:0]m_axi_wvalid;
input [0:0]m_axi_wready;
input [1:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bvalid;
output [0:0]m_axi_bready;
output [1:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_arvalid;
input [0:0]m_axi_arready;
input [1:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input [0:0]m_axi_rlast;
input [0:0]m_axi_rvalid;
output [0:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 99999999999999999; long long n, value[200000], zarib[200000], LCM = 1, GCD, x = INF, ans, sum; vector<int> Tree[200000]; long long gcd(long long l, long long r) { if (!l) return r; return gcd(r % l, l); } bool dfs(int v, int last, long long z) { zarib[v] = z; if (v && Tree[v].size() == 1 && zarib[v] > sum) return 0; z *= (Tree[v].size() - 1); if (!z) z = 1; for (int i = 0; i < Tree[v].size(); i++) if (Tree[v][i] != last) if (!dfs(Tree[v][i], v, z)) return 0; return 1; } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> value[i]; sum += value[i]; } for (int i = 1; i < n; i++) { int l, r; cin >> l >> r; Tree[l - 1].push_back(r - 1); Tree[r - 1].push_back(l - 1); } if (!dfs(0, -1, 1)) { cout << sum << endl; return 0; } for (int i = 1; i < n; i++) if (Tree[i].size() == 1) { GCD = gcd(LCM, zarib[i]); LCM /= GCD; LCM *= zarib[i]; } for (int i = 1; i < n; i++) if (Tree[i].size() == 1) { zarib[i] = LCM / zarib[i]; x = min(x, value[i] / zarib[i]); } for (int i = 1; i < n; i++) if (Tree[i].size() == 1) ans += value[i] - zarib[i] * x; cout << ans << endl; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module ExampMain
#(parameter P)
(input i, output o, inout io);
endmodule
module ExampStub (/*AUTOARG*/
// Outputs
o,
// Inouts
io,
// Inputs
i
);
/*AUTOINOUTPARAM("ExampMain")*/
// Beginning of automatic parameters (from specific module)
parameter P;
// End of automatics
/*AUTOINOUTMODULE("ExampMain")*/
// Beginning of automatic in/out/inouts (from specific module)
output o;
inout io;
input i;
// End of automatics
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o = 1'h0;
// End of automatics
// verilator lint_off UNUSED
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
// Beginning of automatic unused inputs
i,
io,
// End of automatics
1'b0};
// verilator lint_on UNUSED
endmodule
// Local Variables:
// indent-tabs-mode: nil
// End:
|
// MBT 11/9/2014
//
// 1 read-port, 1 write-port ram
//
// reads are asynchronous; we allow reading and writing of same address
//
`define bsg_mem_1r1w_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [els_p-1:0] wa_one_hot = (w_v_i << w_addr_i); \
wire [els_p-1:0] ra_one_hot = (r_v_i << r_addr_i); \
\
bsg_rp_tsmc_250_rf_w``words``_b``bits``_1r1w w``words``_b``bits \
( .clock_i(w_clk_i) \
,.data_i(w_data_i) \
,.write_sel_one_hot_i(wa_one_hot) \
,.read_sel_one_hot_i (ra_one_hot) \
,.data_o(r_data_o) \
); \
end
module bsg_mem_1r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
, parameter harden_p=1)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_macro(32,16)
else `bsg_mem_1r1w_macro(32,2)
else `bsg_mem_1r1w_macro(32,8)
else `bsg_mem_1r1w_macro(16,62)
else `bsg_mem_1r1w_macro(4,32)
else `bsg_mem_1r1w_macro(4,61)
else `bsg_mem_1r1w_macro(4,62)
else `bsg_mem_1r1w_macro(4,64)
else `bsg_mem_1r1w_macro(4,66)
else `bsg_mem_1r1w_macro(4,68)
else `bsg_mem_1r1w_macro(2,1)
else `bsg_mem_1r1w_macro(2,2)
else `bsg_mem_1r1w_macro(2,3)
else `bsg_mem_1r1w_macro(2,4)
else `bsg_mem_1r1w_macro(2,5)
else `bsg_mem_1r1w_macro(2,6)
else `bsg_mem_1r1w_macro(2,7)
else `bsg_mem_1r1w_macro(2,8)
else `bsg_mem_1r1w_macro(2,9)
else `bsg_mem_1r1w_macro(2,10)
else `bsg_mem_1r1w_macro(2,11)
else `bsg_mem_1r1w_macro(2,12)
else `bsg_mem_1r1w_macro(2,13)
else `bsg_mem_1r1w_macro(2,14)
else `bsg_mem_1r1w_macro(2,15)
else `bsg_mem_1r1w_macro(2,16)
else `bsg_mem_1r1w_macro(2,17)
else `bsg_mem_1r1w_macro(2,18)
else `bsg_mem_1r1w_macro(2,19)
else `bsg_mem_1r1w_macro(2,20)
else `bsg_mem_1r1w_macro(2,21)
else `bsg_mem_1r1w_macro(2,22)
else `bsg_mem_1r1w_macro(2,23)
else `bsg_mem_1r1w_macro(2,24)
else `bsg_mem_1r1w_macro(2,25)
else `bsg_mem_1r1w_macro(2,26)
else `bsg_mem_1r1w_macro(2,27)
else `bsg_mem_1r1w_macro(2,28)
else `bsg_mem_1r1w_macro(2,29)
else `bsg_mem_1r1w_macro(2,30)
else `bsg_mem_1r1w_macro(2,31)
else `bsg_mem_1r1w_macro(2,32)
else `bsg_mem_1r1w_macro(2,33)
else `bsg_mem_1r1w_macro(2,34)
else `bsg_mem_1r1w_macro(2,35)
else `bsg_mem_1r1w_macro(2,36)
else `bsg_mem_1r1w_macro(2,37)
else `bsg_mem_1r1w_macro(2,38)
else `bsg_mem_1r1w_macro(2,39)
else `bsg_mem_1r1w_macro(2,40)
else `bsg_mem_1r1w_macro(2,41)
else `bsg_mem_1r1w_macro(2,42)
else `bsg_mem_1r1w_macro(2,43)
else `bsg_mem_1r1w_macro(2,44)
else `bsg_mem_1r1w_macro(2,45)
else `bsg_mem_1r1w_macro(2,46)
else `bsg_mem_1r1w_macro(2,47)
else `bsg_mem_1r1w_macro(2,48)
else `bsg_mem_1r1w_macro(2,49)
else `bsg_mem_1r1w_macro(2,50)
else `bsg_mem_1r1w_macro(2,51)
else `bsg_mem_1r1w_macro(2,52)
else `bsg_mem_1r1w_macro(2,53)
else `bsg_mem_1r1w_macro(2,54)
else `bsg_mem_1r1w_macro(2,55)
else `bsg_mem_1r1w_macro(2,56)
else `bsg_mem_1r1w_macro(2,57)
else `bsg_mem_1r1w_macro(2,58)
else `bsg_mem_1r1w_macro(2,59)
else `bsg_mem_1r1w_macro(2,60)
else `bsg_mem_1r1w_macro(2,61)
else `bsg_mem_1r1w_macro(2,62)
else `bsg_mem_1r1w_macro(2,63)
else `bsg_mem_1r1w_macro(2,64)
else `bsg_mem_1r1w_macro(2,65)
else `bsg_mem_1r1w_macro(2,66)
else `bsg_mem_1r1w_macro(2,67)
else `bsg_mem_1r1w_macro(2,68)
else `bsg_mem_1r1w_macro(2,69)
else `bsg_mem_1r1w_macro(2,70)
else `bsg_mem_1r1w_macro(2,71)
else `bsg_mem_1r1w_macro(2,72)
else `bsg_mem_1r1w_macro(2,73)
else `bsg_mem_1r1w_macro(2,74)
else `bsg_mem_1r1w_macro(2,75)
else `bsg_mem_1r1w_macro(2,76)
else `bsg_mem_1r1w_macro(2,77)
else `bsg_mem_1r1w_macro(2,78)
else `bsg_mem_1r1w_macro(2,79)
else `bsg_mem_1r1w_macro(2,80)
else `bsg_mem_1r1w_macro(2,81)
else `bsg_mem_1r1w_macro(2,82)
else `bsg_mem_1r1w_macro(2,83)
else `bsg_mem_1r1w_macro(2,84)
else `bsg_mem_1r1w_macro(2,85)
else `bsg_mem_1r1w_macro(2,86)
else `bsg_mem_1r1w_macro(2,87)
else `bsg_mem_1r1w_macro(2,88)
else `bsg_mem_1r1w_macro(2,89)
else `bsg_mem_1r1w_macro(8,8)
else begin : notmacro
bsg_mem_1r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
end
// synopsys translate_off
initial
begin
if (width_p*els_p >= 64)
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m), harden_p=%d"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address %x",w_addr_i);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_TB_V
`define SKY130_FD_SC_HD__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hd__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_TB_V
|
/**********************************************************************
* $my_pow example -- Verilog HDL test bench.
*
* Verilog test bench to test the $my_pow PLI application.
*
* For the book, "The Verilog PLI Handbook" by Stuart Sutherland
* Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA
* Contact: www.wkap.il
* Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
* Contact: www.sutherland-hdl.com
*********************************************************************/
`timescale 1ns / 1ns
module test;
reg [32:0] result;
reg a, b;
buf i1 (c,a);
initial
begin
$display("Start simulation pow_test.v");
a = 1;
b = 0;
/* Test $my_pow with invalid arguments */
/* These invalid calls will need to be commented out to use */
/* the valid calls to $my_pow in simulation */
// #1 result = $my_pow;
// #1 result = $my_pow();
// #1 result = $my_pow(1);
// #1 result = $my_pow(2,i1);
// #1 result = $my_pow(1,2,3);
/* Test $my_pow with valid values */
#1 $display("$my_pow(2,3) returns %d", $my_pow(2,3));
#1 result = $my_pow(a,b);
#1 $display("$my_pow(a,b) returns %d (a=%d b=%d)", result, a, b);
// #1 $stop;
#1 $finish(0);
end
endmodule
/*********************************************************************/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
|
// ------------------ multiByteReadWrite.v ----------------------
`include "timescale.v"
`include "i2cSlaveTB_defines.v"
module multiByteReadWrite();
reg ack;
reg [31:0] readData;
reg [7:0] dataByteRead;
//reg [7:0] dataMSB;
// ------------------ write ----------------------
task write;
input [7:0] i2cAddr;
input [7:0] regAddr;
input [31:0] data;
input stop;
begin
$write("I2C Write: At [0x%0x] = 0x%0x\n", regAddr, data);
//i2c address
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, i2cAddr);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h90); //STA, WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("I2C device address sent, SR = 0x%x\n", dataByteRead );
//slave reg address
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, regAddr);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h10); //WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Slave reg address sent, SR = 0x%x\n", dataByteRead );
//data[31:24]
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, data[31:24]);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h10); //WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[31:24] sent, SR = 0x%x\n", dataByteRead );
//data[23:16]
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, data[23:16]);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h10); //WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[23:16] sent, SR = 0x%x\n", dataByteRead );
//data[15:8]
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, data[15:8]);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h10); //WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[15:8] sent, SR = 0x%x\n", dataByteRead );
//data[7:0]
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, data[7:0]);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , {1'b0, stop, 6'b010000}); //STO?, WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[7:0] sent, SR = 0x%x\n", dataByteRead );
end
endtask
// ------------------ read ----------------------
task read;
input [7:0] i2cAddr;
input [7:0] regAddr;
input [31:0] expectedData;
output [31:0] data;
input stop;
begin
//i2c address
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, i2cAddr); //write
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h90); //STA, WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("I2C device address sent, SR = 0x%x\n", dataByteRead );
#5000;
//slave reg address
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, regAddr);
testHarness.u_wb_master_model.wb_write(1, `CR_REG , {1'b0, stop, 6'b010000}); //STO?, WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Slave reg address sent, SR = 0x%x\n", dataByteRead );
#5000;
//i2c address
testHarness.u_wb_master_model.wb_write(1, `TXR_REG, {i2cAddr[7:1], 1'b1}); //read
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h90); //STA, WR
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("I2C device address sent, SR = 0x%x\n", dataByteRead );
//data[31:24]
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h20); //RD, ACK
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[31:24] rxed, SR = 0x%x\n", dataByteRead );
testHarness.u_wb_master_model.wb_read(1, `RXR_REG, readData[31:24]);
//data[23:16]
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h20); //RD, ACK
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[23:16] rxed, SR = 0x%x\n", dataByteRead );
testHarness.u_wb_master_model.wb_read(1, `RXR_REG, readData[23:16]);
//data[15:8]
testHarness.u_wb_master_model.wb_write(1, `CR_REG , 8'h20); //RD, ACK
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[15:8] rxed, SR = 0x%x\n", dataByteRead );
testHarness.u_wb_master_model.wb_read(1, `RXR_REG, readData[15:8]);
//data[7:0]
testHarness.u_wb_master_model.wb_write(1, `CR_REG , {1'b0, 1'b0, 6'b101000}); //STO, RD, NAK
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
while (dataByteRead[1] == 1'b1) //while trans in progress
testHarness.u_wb_master_model.wb_read(1, `SR_REG , dataByteRead);
//$write("Data[7:0] rxed, SR = 0x%x\n", dataByteRead );
testHarness.u_wb_master_model.wb_read(1, `RXR_REG, readData[7:0]);
data = readData;
if (data != expectedData) begin
$write("***** I2C Read ERROR: At 0x%0x. Expected 0x%0x, got 0x%0x\n", regAddr, expectedData, data);
$stop;
end
else
$write("I2C Read: At [0x%0x] = 0x%0x\n", regAddr, data);
end
endtask
endmodule
|
`include "defines.v"
`include "HRbridge.v"
`timescale 1ns/1ps
/*module connectRouter_nobuffer
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_l0_i,
output `control_w port_l0_o,
input `control_w FIFO_l0_i,
output `control_w FIFO_l0_o,
input bfull_l0_i,
input clk,
input rst,
output deQ_l0_o,
output enQ_l0_o,
*/
module tb(
);
reg clk, rst;
reg `control_w port_l0, port_l1, port_g0, port_g1, port_g2, port_g3;
reg `control_w FIFO_l0, FIFO_l1, FIFO_g0, FIFO_g1, FIFO_g2, FIFO_g3;
reg bfull_l0, bfull_l1, bfull_g0, bfull_g1, bfull_g2, bfull_g3;
wire `control_w port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o;
wire `control_w FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o;
wire deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3;
wire enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3;
wire accept, push;
HRbridge r(
.clk(clk),
.rst(rst),
.port_l0_i(port_l0), .port_l1_i(port_l1), .port_g0_i(port_g0), .port_g1_i(port_g1), .port_g2_i(port_g2), .port_g3_i(port_g3),
.port_l0_o(port_l0_o), .port_l1_o(port_l1_o), .port_g0_o(port_g0_o), .port_g1_o(port_g1_o), .port_g2_o(port_g2_o), .port_g3_o(port_g3_o),
.FIFO_l0_i(FIFO_l0), .FIFO_l1_i(FIFO_l1), .FIFO_g0_i(FIFO_g0), .FIFO_g1_i(FIFO_g1), .FIFO_g2_i(FIFO_g2), .FIFO_g3_i(FIFO_g3),
.FIFO_l0_o(FIFO_l0_o), .FIFO_l1_o(FIFO_l1_o), .FIFO_g0_o(FIFO_g0_o), .FIFO_g1_o(FIFO_g1_o), .FIFO_g2_o(FIFO_g2_o), .FIFO_g3_o(FIFO_g3_o),
.bfull_l0_i(bfull_l0), .bfull_l1_i(bfull_l1), .bfull_g0_i(bfull_g0), .bfull_g1_i(bfull_g1), .bfull_g2_i(bfull_g2), .bfull_g3_i(bfull_g3),
.deQ_l0_o(deQ_l0), .deQ_l1_o(deQ_l1), .deQ_g0_o(deQ_g0), .deQ_g1_o(deQ_g1), .deQ_g2_o(deQ_g2), .deQ_g3_o(deQ_g3),
.enQ_l0_o(enQ_l0), .enQ_l1_o(enQ_l1), .enQ_g0_o(enQ_g0), .enQ_g1_o(enQ_g1), .enQ_g2_o(enQ_g2), .enQ_g3_o(enQ_g3)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0; port_g2 = 144'h0; port_g3 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0; FIFO_g2 = 144'h0; FIFO_g3 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0; bfull_g2 = 0; bfull_g3 = 0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, port_g2 %04x\n, port_g3 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, FIFO_g2 %04x\n, FIFO_g3 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, deQ_g2 %04x\n, deQ_g3 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n, enQ_g2 %04x\n, enQ_g3 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3,
enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3);
#1;
clk = 1;
#1;
clk = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0; port_g2 = 144'h0; port_g3 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0; FIFO_g2 = 144'h0; FIFO_g3 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0; bfull_g2 = 0; bfull_g3 = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, port_g2 %04x\n, port_g3 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, FIFO_g2 %04x\n, FIFO_g3 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, deQ_g2 %04x\n, deQ_g3 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n, enQ_g2 %04x\n, enQ_g3 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3,
enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class DREAD { friend int fread(); static const int buff_max = 20000000 + 10; char buf[buff_max], *pt; public: void clear() { for (; isspace(*pt); ++pt) ; } void Init() { buf[fread(buf, 1, buff_max, stdin)] = EOF; pt = buf; } bool eoln() { return *pt == n ; } inline bool eof() { return *pt == EOF; } int Int() { bool pos = 1; int res = 0; for (; !isdigit(*pt) && *pt != - && !eof(); ++pt) ; if (*pt == - ) pos = 0, ++pt; for (; isdigit(*pt); ++pt) res = res * 10 + (*pt - 0 ); return pos ? res : -res; } } READ; const int N_MAX = 5000 + 10; int N, M, seq[N_MAX], bad[N_MAX]; namespace Nwork { int gcd[N_MAX]; int GCD(int a, int b) { return b ? GCD(b, a % b) : a; } int p[N_MAX], e[N_MAX], cnt; int exist(int p) { return *lower_bound(bad + 1, bad + M + 1, p) == p ? -1 : 1; } int calc(int x) { cnt = 0; for (int i = 2, k = int(sqrt(x)); i <= k; ++i) { if (x == 1) break; if (x % i == 0) { p[++cnt] = i; for (e[cnt] = 0; x % i == 0; x /= i) ++e[cnt]; } } if (x != 1) p[++cnt] = x, e[cnt] = 1; int ret = 0; for (int i = 1; i <= cnt; ++i) ret += exist(p[i]) * e[i]; return ret; } void main() { gcd[1] = seq[1]; for (int i = 2; i <= N; ++i) gcd[i] = GCD(gcd[i - 1], seq[i]); sort(bad + 1, bad + M + 1); for (int r = N; r >= 1; --r) if (calc(gcd[r]) < 0) for (int i = 1; i <= r; ++i) { seq[i] /= gcd[r]; gcd[i] /= gcd[r]; } int ret = 0; for (int i = 1; i <= N; ++i) ret += calc(seq[i]); printf( %d n , ret); } } // namespace Nwork namespace Ninit { void init() { N = READ.Int(), M = READ.Int(); for (int i = 1; i <= N; ++i) seq[i] = READ.Int(); for (int i = 1; i <= M; ++i) bad[i] = READ.Int(); } } // namespace Ninit int main() { READ.Init(); Ninit::init(); Nwork::main(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = INT_MAX / 2; const int Maxn = 305; int a[Maxn + 5][Maxn + 5], f[Maxn + 5][Maxn + 5], g[Maxn + 5][Maxn + 5], n; int solve() { for (int(i) = (1); (i) <= (n); ++(i)) for (int(j) = (1); (j) <= (n); ++(j)) f[i][j] = -inf; f[1][1] = a[1][1]; for (int(k) = (2); (k) <= (n * 2 - 1); ++(k)) { for (int(i) = (1); (i) <= (n); ++(i)) for (int(j) = (1); (j) <= (n); ++(j)) g[i][j] = -inf; for (int(i) = (1); (i) <= (n); ++(i)) for (int(j) = (i); (j) <= (n); ++(j)) { if (f[i][j] <= -inf) continue; for (int(si) = (i); (si) <= (i + 1); ++(si)) for (int(sj) = (j); (sj) <= (j + 1); ++(sj)) { if (si > sj || si > n || sj > n || k + 1 - si > n || k + 1 - sj > n) continue; int bonus; if (si == sj) bonus = a[k + 1 - si][si]; else bonus = a[k + 1 - si][si] + a[k + 1 - sj][sj]; g[si][sj] = max(g[si][sj], f[i][j] + bonus); } } for (int(i) = (1); (i) <= (n); ++(i)) for (int(j) = (1); (j) <= (n); ++(j)) f[i][j] = g[i][j]; } return f[n][n]; } int main() { iostream::sync_with_stdio(false); cin >> n; for (int(i) = (1); (i) <= (n); ++(i)) for (int(j) = (1); (j) <= (n); ++(j)) cin >> a[i][j]; cout << solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[200001]; long long a[26]; long long cnt = 0; int main() { long long i, j, k, l, m, n, t; cin >> t; cin >> s; l = strlen(s); for (i = 0; i < 26; i++) a[i] = 0; for (i = 1; i < l; i = i + 2) { if ((s[i - 1] - 97) != (s[i] - 65)) { if (a[s[i] - 65] > 0) { a[s[i] - 65]--; a[s[i - 1] - 97]++; } else { cnt++; a[s[i - 1] - 97]++; } } } cout << cnt << endl; return 0; }
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "uart.v"
module uart_tb;
reg clk, transmit;
reg [23:0] tx_data;
wire txd, tx_empty;
integer i;
// use a small clock divider for visibility
uart #(
.divide_count(5)
) test_uart(
.clock(clk),
.txd(txd),
.tx_data(tx_data),
.tx_empty(tx_empty),
.transmit(transmit)
);
initial begin
clk = 1'b0;
forever #9 clk = ~clk;
end
initial begin
$display("running uart_tb");
$dumpfile("uart.vcd");
$dumpvars(0, uart_tb);
$display("start");
transmit = 0;
repeat(8) @(posedge clk);
$display("transmit");
tx_data = 24'b111111110000000010110010;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
$display("observe");
@(posedge tx_empty);
tx_data = 8'h00;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
@(posedge tx_empty);
repeat(8) @(posedge clk);
$display("stop now");
$finish;
end
endmodule
|
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
parameter ClkFrequency = 80000000; // 25MHz
//parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
////////////////////////////
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick)
begin
if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg [3:0] state;
reg [3:0] bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always @(posedge clk)
if(state==0)
bit_spacing <= 4'b0000;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int cnt = 0, cnt1 = 0; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == - ) cnt++; else cnt1++; } if (cnt1 == 0) { cout << YES ; return 0; } if (cnt % cnt1 == 0) cout << YES ; else cout << NO ; }
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module miner130 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, nonce2, hash2;
reg [31:0] nonce;
wire [255:0] hash;
reg [7:0] cnt = 8'd0;
reg feedback = 1'b0;
reg is_golden_nonce;
reg feedback_b1, feedback_b2, feedback_b3, feedback_b4, feedback_b5, feedback_b6, reset_b1, reset_b2;
reg [255:0] state_buf;
reg [511:0] data_buf;
sha256_pipe129 p (
.clk(clk),
.state(state_buf),
.data(data_buf),
.hash(hash)
);
always @ (posedge clk)
begin
if ( cnt == 8'd129 )
begin
feedback <= ~feedback;
cnt <= 8'd0;
end else begin
cnt <= cnt + 8'd1;
end
if ( feedback_b1 )
begin
data_buf <= { 256'h0000010000000000000000000000000000000000000000000000000080000000,
hash[`IDX(7)] + midstate[`IDX(7)],
hash[`IDX(6)] + midstate[`IDX(6)],
hash[`IDX(5)] + midstate[`IDX(5)],
hash[`IDX(4)] + midstate[`IDX(4)],
hash[`IDX(3)] + midstate[`IDX(3)],
hash[`IDX(2)] + midstate[`IDX(2)],
hash[`IDX(1)] + midstate[`IDX(1)],
hash[`IDX(0)] + midstate[`IDX(0)]
};
end else begin
data_buf <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data};
end
if ( feedback_b2 )
begin
state_buf <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
end else begin
state_buf <= midstate;
end
if ( reset_b1 )
begin
nonce <= NONCE_OFFS;
end else if ( ! feedback_b3 )
begin
nonce <= nonce + NONCE_INCR;
end
if ( reset_b2 )
begin
golden_nonce <= 32'd0;
end else if ( is_golden_nonce )
begin
golden_nonce <= nonce2;
end
if ( ! feedback_b4 )
begin
hash2 <= hash[255:224];
end
if ( ! feedback_b5 )
begin
nonce2 <= nonce;
end
if ( ! feedback_b6 )
begin
is_golden_nonce <= hash[255:224] == 32'ha41f32e7;
end
feedback_b1 <= feedback;
feedback_b2 <= feedback;
feedback_b3 <= feedback;
feedback_b4 <= feedback;
feedback_b5 <= feedback;
feedback_b6 <= feedback;
reset_b1 <= reset;
reset_b2 <= reset;
end
endmodule
|
#include <bits/stdc++.h> const int N = 2e3 + 9; using namespace std; int n, dp[5][N], a[N], b[5] = {0, 1, 2, 1, 2}; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= 4; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = max(dp[i - 1][j], dp[i][j - 1] + (a[j] == b[i])); } } printf( %d n , dp[4][n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; long long power(long long x, long long y) { long long t = 1; while (y > 0) { if (y % 2) y -= 1, t = t * x % mod; else y /= 2, x = x * x % mod; } return t; } vector<int> G[N]; vector<long long> snd[N]; long long sub[N], sum[N], red[N], dol[N]; long long mns[N], mxs[N]; int lol[N]; vector<pair<int, pair<long long, long long> > > edges; void done() { printf( -1 n ); exit(0); } void dfs(int v) { for (int i = 0; i < G[v].size(); ++i) { int ed = G[v][i]; dfs(edges[ed].first); long long &w = edges[ed].second.first, &p = edges[ed].second.second; if (mns[edges[ed].first] > p) done(); long long z = min(w - 1, p - mns[edges[ed].first]); mns[v] += mns[edges[ed].first] + w - z; snd[v].push_back(mns[edges[ed].first] + w - z); mxs[v] += w + min(p, mxs[edges[ed].first]); assert(mns[v] <= mxs[v]); } } void dfs1(int v, long long nd) { for (int i = 0; i < G[v].size(); ++i) nd -= snd[v][i]; for (int i = 0; i < G[v].size(); ++i) { int ed = G[v][i], to = edges[ed].first; long long &w = edges[ed].second.first, &p = edges[ed].second.second; long long z = min(w - 1, p - mns[edges[ed].first]); w -= z; p -= z; long long k = min(nd, z); w += k; p += k; nd -= k; k = min(min(nd, p - mns[edges[ed].first]), mxs[edges[ed].first] - mns[edges[ed].first]); dfs1(to, mns[edges[ed].first] + k); nd -= k; } assert(nd == 0); } int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { int x, y; long long w, p; scanf( %d%d%lld%lld , &x, &y, &w, &p); x--; y--; G[x].push_back(edges.size()); lol[i] = x; edges.push_back(make_pair(y, make_pair(w, p))); } dfs(0); dfs1(0, mxs[0]); printf( %d n , n); for (int i = 0; i < n - 1; ++i) { printf( %d %d %lld %lld n , lol[i] + 1, edges[i].first + 1, edges[i].second.first, edges[i].second.second); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 9; char s[N]; bool vis[N]; struct Point { long long x, y, id; Point(long long _x = 0, long long _y = 0, long long _id = 0) { x = _x; y = _y; id = _id; } Point operator-(const Point& b) const { return Point(x - b.x, y - b.y); } } p[N], p0, tem[N]; long long cross(Point a, Point b) { return a.x * b.y - b.x * a.y; } bool cmp(Point a, Point b) { return cross(a - p0, b - p0) >= 0; } int main() { int n; scanf( %d , &n); p0 = Point(10000000000, 10000000000); for (int i = 1; i <= n; ++i) { scanf( %lld %lld , &p[i].x, &p[i].y); p[i].id = i; if (p[i].y < p0.y || (p0.y == p[i].y && p[i].x < p0.x)) p0 = p[i]; } scanf( %s , s); vector<int> ans; ans.push_back(p0.id); vis[p0.id] = 1; int sp = 0; for (int i = 2; i <= n; ++i, ++sp) { int cnt = 0; for (int j = 1; j <= n; ++j) { if (vis[j]) continue; tem[++cnt] = p[j]; } sort(tem + 1, tem + 1 + cnt, cmp); int nex; if (s[sp] == L ) nex = tem[1].id; else nex = tem[cnt].id; ans.push_back(nex); vis[nex] = 1; p0 = p[nex]; } for (int i = 0; i < (int)ans.size(); ++i) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long t = 1, tt; void solve() { long long n; cin >> n; string a, b; cin >> a >> b; if (n == 1) { if (a == b) cout << 0; else cout << 1; return; } long long ans = 0; for (long long i = 0; i < n / 2; i += 1) { set<char> ss; map<char, long long> mapa; ss.insert(a[i]); mapa[a[i]]++; ss.insert(a[n - i - 1]); mapa[a[n - i - 1]]++; ss.insert(b[i]); mapa[b[i]]++; ss.insert(b[n - i - 1]); mapa[b[n - i - 1]]++; if (int((ss).size()) == 4) ans += 2; if (int((ss).size()) == 3) { if (a[i] == a[n - i - 1]) ans += 2; else ans += 1; } if (int((ss).size()) == 2) { if (mapa[a[i]] == 1 || mapa[a[i]] == 3) ans += 1; } } if (n % 2 == 1) { if (a[n / 2] != b[n / 2]) ans += 1; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); tt = t; while (t--) solve(); return 0; }
|
`ifndef SDIO_DEFINES
`define SDIO_DEFINES
`define SDIO_STATE_RESET 0
`define SDIO_STATE_ACTIVE 1
`define SDIO_C_BIT_TXRX_DIR 1
`define SDIO_C_BIT_CMD_START 2
`define SDIO_C_BIT_CMD_END 7
`define SDIO_C_BIT_ARG_START 8
`define SDIO_C_BIT_ARG_END 39
`define SDIO_C_BIT_CRC_START 40
`define SDIO_C_BIT_CRC_END 46
`define SDIO_C_BIT_FINISH 47
`define SDIO_R_BIT_START_BIT 0
`define SDIO_R_BIT_TXRX_DIR 1
`define SD_CMD_GO_IDLE_STATE (6'd0 )
//`define SD_CMD_SEND_CID (6'd2 )
`define SD_CMD_SEND_RELATIVE_ADDR (6'd3 )
//`define SD_CMD_SET_DSR (6'd4 )
`define SD_CMD_IO_SEND_OP_CMD (6'd5 )
//`define SD_CMD_SWITCH_FUNC (6'd6 )
`define SD_CMD_SEL_DESEL_CARD (6'd7 )
`define SD_CMD_SEND_IF_COND (6'd8 )
//`define SD_CMD_SEND_CSD (6'd9 )
//`define SD_CMD_SEND_CID (6'd10)
`define SD_CMD_VOLTAGE_SWITCH (6'd11)
//`define SD_CMD_STOP_TRANSMISSION (6'd12)
//`define SD_CMD_SEND_STATUS (6'd13)
`define SD_CMD_GO_INACTIVE_STATE (6'd15)
//`define SD_CMD_SET_BLOCKLEN (6'd16)
//`define SD_CMD_READ_SINGLE_BLOCK (6'd17)
//`define SD_CMD_READ_MULTIPLE_BLOCK (6'd18)
`define SD_CMD_SEND_TUNNING_BLOCK (6'd19)
//`define SD_CMD_SET_BLOCK_COUNT (6'd23)
//`define SD_CMD_WRITE_BLOCK (6'd24)
//`define SD_CMD_WRITE_MULTIPLE_BLOCK (6'd25)
//`define SD_CMD_PROGRAM_CSD (6'd27)
//`define SD_CMD_SET_WRITE_PROT (6'd28)
//`define SD_CMD_CLR_WRITE_PRO (6'd29)
//`define SD_CMD_SEND_WRITE_PROT (6'd30)
//`define SD_CMD_ERASE_WR_BLK_START (6'd32)
//`define SD_CMD_ERASE_WR_BLK_END (6'd33)
//`define SD_CMD_ERASE (6'd38)
//`define SD_CMD_LOCK_UNLOCK (6'd42)
`define SD_CMD_IO_RW_DIRECT (6'd52)
`define SD_CMD_IO_RW_EXTENDED (6'd53)
//`define SD_CMD_APP_CMD (6'd55)
//`define SD_CMD_GEN_CMD (6'd56)
//`define SD_ACMD_SET_BUS_WIDTH (6'd6)
//`define SD_ACMD_SD_STATUS (6'd13)
//`define SD_ACMD_SEND_NUM_WR_BLOCK (6'd22)
//`define SD_ACMD_SET_WR_BLK_ERASE_CNT (6'd23)
//`define SD_ACMD_SD_APP_OP_COND (6'd41)
//`define SD_ACMD_SET_CLR_CARD_DETECT (6'd42)
//`define SD_ACMD_SEND_SCR (6'd51)
//Functions
//Relative Card Address
`define RELATIVE_CARD_ADDRESS (16'h0001)
//Not SD_CURRENT_STATE shall always return 0x0F
//Card Status
`define CMD_RSP_CMD 45:40
`define CMD_RSP_CRD_STS_START (39)
`define CMD_RSP_CRD_STS_END (8)
//IO_SEND_OP_COND Response (R4 32 bits)
`define CMD5_ARG_S18R (24)
`define CMD5_ARG_OCR 23:0
`define VHS_DEFAULT_VALUE (4'b0001)
`define CMD7_RCA 31:16
`define CMD8_ARG_VHS_START 15
`define CMD8_ARG_VHS_END 8
`define CMD8_ARG_VHS 15:8
`define CMD8_ARG_PATTERN 7:0
`define CMD52_ARG_RW_FLAG 31 /* 0 = Read 1 = Write */
`define CMD52_ARG_FNUM 30:27
`define CMD52_ARG_RAW_FLAG 26 /* Read the value of the register after a write RW_FLAG = 1*/
`define CMD52_ARG_REG_ADDR 25:9
`define CMD52_ARG_WR_DATA 7:0
`define CMD52_RST_ADDR 6
`define CMD52_RST_BIT 3
//Extended
`define CMD53_ARG_RW_FLAG 31
`define CMD53_ARG_FNUM 30:28
`define CMD53_ARG_BLOCK_MODE 27
`define CMD53_ARG_INC_ADDR 26
`define CMD53_ARG_REG_ADDR 25:9
`define CMD53_ARG_DATA_COUNT 8:0
//COMMAND SEL DESEL CARD
//Response R1
`define R1_OUT_OF_RANGE (39)
`define R1_COM_CRC_ERROR (38)
`define R1_ILLEGAL_COMMAND (37)
`define R1_ERROR (19)
`define R1_CURRENT_STATE 12:9
//Respone R4
`define R4_RSRVD 45:40
`define R4_READY (39) /* Card is ready to operate */
`define R4_NUM_FUNCS 38:36 /* Number of functions */
`define R4_MEM_PRESENT (35) /* Memory is Also Availalbe */
`define R4_UHSII_AVAILABLE (34) /* Ultra HS Mode II Available */
`define R4_S18A (32) /* Accept switch to 1.8V */
`define R4_IO_OCR 31:8 /* Operating Condition Range */
//Response R5
`define R5_FLAGS_RANGE 31:16
`define R5_DATA 15:8
`define R5_FLAG_CRC_ERROR (15)
`define R5_INVALID_CMD (14)
`define R5_FLAG_CURR_STATE 13:12
`define R5_FLAG_ERROR (11)
`define R5_INVALID_FNUM (9)
`define R5_OUT_OF_RANGE (8)
//Response R6
`define R6_REL_ADDR 39:24
`define R6_STS_CRC_COMM_ERR (23)
`define R6_STS_ILLEGAL_CMD (22)
`define R6_STS_ERROR (21)
//Response 7
`define R7_VHS 19:16
`define R7_PATTERN 15:8
//FBR
`define FBR_FUNC_ID_ADDR 0
`define FBR_FUNC_EXT_ID_ADDR 1
`define FBR_POWER_SUPPLY_ADDR 2
`define FBR_ISDIO_FUNC_ID_ADDR 3
`define FBR_MANF_ID_LOW_ADDR 4
`define FBR_MANF_ID_HIGH_ADDR 5
`define FBR_PROD_ID_LOW_ADDR 6
`define FBR_PROD_ID_HIGH_ADDR 7
`define FBR_ISDIO_PROD_TYPE 8
`define FBR_CIS_LOW_ADDR 9
`define FBR_CIS_MID_ADDR 10
`define FBR_CIS_HIGH_ADDR 11
`define FBR_CSA_LOW_ADDR 12
`define FBR_CSA_MID_ADDR 13
`define FBR_CSA_HIGH_ADDR 14
`define FBR_DATA_ACC_ADDR 15
`define FBR_BLOCK_SIZE_LOW_ADDR 16
`define FBR_BLOCK_SIZE_HIGH_ADDR 17
`endif
|
// FIXME: очень плохое APi
//синхронный ресет на дает создать ena триггер
// синхронный ресет не отличим от других сигналов
// "eff sync only subset Verilog" как то так звучало
// детектировать сигнал нужно основным клоком, т.к. мы
// тактируем им напрямую, ширина стробирующий импльсов в один
// такт основого клока
//
// Обойтись бы без детектирования
// если отдельные блоки, то могут быть гонки
// fixme: async start is bad looks lime in fpga
// fIXME: если синхр. сброс, то ресет станет
// триггером, т.е. входом триггера
// http://www.sunbustart-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
// ресет добавляет довольно много логики!
//ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Tutorials/DE0-Nano/Using_DE0-Nano_ADC.pdf
`include "const.v"
module base_fsm(
// Ins
input clk, start, // это не простые сигналы, нужно очень хорошо
// понимать как с ними иметь дело
input [`W-1:0] clk_scaler,
input from_device, // нужно защелкнуть
// Outs
output reg sclk_n,
output reg cs_n,
output reg [11:0] data,
output reg irq,
output test0,
output test1
);
reg sclk_cntr_q;
reg sclk_cntr_d;
reg cs_n_d;
reg ena, enadelayed, rd_ena;
reg irq_d;
reg irq_q;
reg irq_2q;
reg [`W-1:0] clk_dvdr_cntr;
reg [5:0] iter_q;
reg [5:0] iter_d;
reg addr;
reg [2:0] addr_reg;
reg [3:0] state_q;
reg [3:0] state_d;
reg [11:0] data_d;
localparam IDLE = 2'b00,
WAIT_WR_ADDR = 2'b01,
WR_ADDR = 2'b10,
RD_RESP = 2'b11;
initial begin
ena <= 0;
clk_dvdr_cntr <= 0;
end
wire sclk_n_d = ~(sclk_cntr_d & ~( cs_n & cs_n_d ));
wire [`W-1:0] half_scaler = clk_scaler[`W-1:1];
always @(*) begin
state_d = state_q;
cs_n_d = 1;
sclk_cntr_d = sclk_cntr_q;
iter_d = iter_q;
rd_ena = 0;
irq_d = 0;
addr = 0;
case( state_q )
IDLE: begin
cs_n_d = 1;
sclk_cntr_d = 1;
iter_d = 0;
state_d = WAIT_WR_ADDR;
end
WAIT_WR_ADDR: begin
cs_n_d = 0;
if( iter_d == 2*2 ) begin
state_d = WR_ADDR;
end
end
WR_ADDR: begin
cs_n_d = 0;
if( iter_d == 5*2 ) begin
rd_ena = 1;
state_d = RD_RESP;
end
// fixme: не очень ясно как
addr = 1; // fixme: make normal
end
RD_RESP: begin
rd_ena = 1;
if( iter_d == `PKG_SIZE*2 ) begin
cs_n_d = 1;
irq_d = 1;
state_d = IDLE;
end
else begin
cs_n_d = 0;
end
end
endcase
if( state_q == WAIT_WR_ADDR ||
state_q == WR_ADDR ||
state_q == RD_RESP ) begin
iter_d = iter_q + 1'b1;
sclk_cntr_d = ~sclk_cntr_q;
end
end
always @( posedge clk ) begin
if( start ) begin
state_q <= IDLE;
end
else begin
if( ena ) begin
state_q <= state_d;
end
end
end
always @( posedge clk ) begin
if( start ) begin // sclk & ena ? and wr_ena
addr_reg <= 7; // fixme: не очень ясно что дальше делать?
end
if( ena ) begin
iter_q <= iter_d;
sclk_cntr_q <= sclk_cntr_d;
sclk_n <= sclk_n_d;
cs_n <= cs_n_d;
end
// rd
enadelayed <= ena & sclk_n_d & rd_ena;
if( enadelayed ) begin
// fixme: bad! need synchronizer
data_d <= { data_d[10:0], from_device };
end
irq_q <= irq_d;
irq_2q <= irq_q & enadelayed;
if( irq_2q ) begin
data <= data_d;
end
irq <= irq_2q;
// div
if( clk_dvdr_cntr == half_scaler ) begin
ena <= 1;
clk_dvdr_cntr <= 0;
end
else begin
ena <= 0;
clk_dvdr_cntr <= clk_dvdr_cntr + 1'b1;
end
end
assign test0 = addr;
assign test1 = enadelayed;
endmodule
|
module butterfly1_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output signed [16:0] o_0;
output signed [16:0] o_1;
output signed [16:0] o_2;
output signed [16:0] o_3;
output signed [16:0] o_4;
output signed [16:0] o_5;
output signed [16:0] o_6;
output signed [16:0] o_7;
output signed [16:0] o_8;
output signed [16:0] o_9;
output signed [16:0] o_10;
output signed [16:0] o_11;
output signed [16:0] o_12;
output signed [16:0] o_13;
output signed [16:0] o_14;
output signed [16:0] o_15;
output signed [16:0] o_16;
output signed [16:0] o_17;
output signed [16:0] o_18;
output signed [16:0] o_19;
output signed [16:0] o_20;
output signed [16:0] o_21;
output signed [16:0] o_22;
output signed [16:0] o_23;
output signed [16:0] o_24;
output signed [16:0] o_25;
output signed [16:0] o_26;
output signed [16:0] o_27;
output signed [16:0] o_28;
output signed [16:0] o_29;
output signed [16:0] o_30;
output signed [16:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [16:0] b_0;
wire signed [16:0] b_1;
wire signed [16:0] b_2;
wire signed [16:0] b_3;
wire signed [16:0] b_4;
wire signed [16:0] b_5;
wire signed [16:0] b_6;
wire signed [16:0] b_7;
wire signed [16:0] b_8;
wire signed [16:0] b_9;
wire signed [16:0] b_10;
wire signed [16:0] b_11;
wire signed [16:0] b_12;
wire signed [16:0] b_13;
wire signed [16:0] b_14;
wire signed [16:0] b_15;
wire signed [16:0] b_16;
wire signed [16:0] b_17;
wire signed [16:0] b_18;
wire signed [16:0] b_19;
wire signed [16:0] b_20;
wire signed [16:0] b_21;
wire signed [16:0] b_22;
wire signed [16:0] b_23;
wire signed [16:0] b_24;
wire signed [16:0] b_25;
wire signed [16:0] b_26;
wire signed [16:0] b_27;
wire signed [16:0] b_28;
wire signed [16:0] b_29;
wire signed [16:0] b_30;
wire signed [16:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a, b, qa, qb, answer; int i, j, p, k, lcm, d; int dist[1000000]; char inq[1000000]; int gcd(int x, int y) { if ((x % y) == 0) return y; return gcd(y, x % y); } void ComputeDist() { for (i = 0; i <= lcm; i++) { dist[i] = lcm + 1; inq[i] = 0; } dist[0] = 0; queue<int> q; q.push(0); inq[0] = 1; while (q.size() > 0) { i = q.front(); q.pop(); inq[i] = 0; if (i + 1 <= lcm && (1 + dist[i] < dist[i + 1])) { dist[i + 1] = 1 + dist[i]; if (!inq[i + 1]) { q.push(i + 1); inq[i + 1] = 1; } } for (j = 2; j <= k; j++) if (i % j == 0) { for (p = 1; p < j; p++) if (i + p <= lcm && (1 + dist[i] < dist[i + p])) { dist[i + p] = 1 + dist[i]; if (!inq[i + p]) { q.push(i + p); inq[i + p] = 1; } } } } } void ComputeDist2(int end, int start) { for (i = 0; i <= start; i++) { dist[i] = start + 1; inq[i] = 0; } dist[start] = 0; queue<int> q; q.push(start); inq[start] = 1; while (q.size() > 0) { i = q.front(); q.pop(); inq[i] = 0; if (i - 1 >= end && (1 + dist[i] < dist[i - 1])) { dist[i - 1] = 1 + dist[i]; if (!inq[i - 1]) { q.push(i - 1); inq[i - 1] = 1; } } for (j = 2; j <= k; j++) if (i % j > 0) { p = i % j; if (i - p >= end && (1 + dist[i] < dist[i - p])) { dist[i - p] = 1 + dist[i]; if (!inq[i - p]) { q.push(i - p); inq[i - p] = 1; } } } } } int main() { scanf( %I64d %I64d %d , &a, &b, &k); lcm = 1; for (i = 2; i <= k; i++) { d = gcd(i, lcm); lcm *= (i / d); } ComputeDist(); qa = a / lcm; qb = b / lcm; answer = 0; if (qa > qb + 1) { answer += dist[a % lcm]; answer += dist[lcm] * (qa - qb - 1); a = (qb + 1) * lcm; } ComputeDist2(b % lcm, a - qb * lcm); answer += dist[b % lcm]; printf( %I64d n , answer); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { return (!y ? x : gcd(y, x % y)); } long long lcm(long long x, long long y) { return x / gcd(x, y) * y; } void file() {} void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); file(); } int dx[] = {-1, 0, 1, 0}; int dy[] = {0, 1, 0, -1}; const double eps = 1e-9; const int mod = 1e9 + 7; const int N = 1e5 + 5; int n; string s; int dp[N][10][2]; int upd(int x) { int sum = 0; while (x) sum += x % 10, x /= 10; return sum; } int solve(int idx, int sum, bool ok) { if (idx == n) { if (sum % 3 == 0) return 0; return 1e9; } int &ret = dp[idx][sum][ok]; if (~ret) return ret; ret = solve(idx + 1, sum, ok) + 1; if (ok || s[idx] != 0 ) ret = min(ret, solve(idx + 1, upd(sum + s[idx] - 48), 1)); return ret; } void solve2(int idx, int sum, bool ok) { if (idx == n) { return; } int &ret = dp[idx][sum][ok]; if (ret == solve(idx + 1, sum, ok) + 1) { solve2(idx + 1, sum, ok); return; } cout << s[idx]; solve2(idx + 1, upd(sum + s[idx] - 48), 1); return; } int main() { fast(); memset((dp), -1, sizeof(dp)); cin >> s; n = (int)s.size(); bool ok = 0; for (int i = 0; i < (int)s.size(); i++) { ok |= s[i] == 0 ; } int x = solve(0, 0, 0); if (x == n) { if (!ok) cout << -1; else cout << 0; return 0; } solve2(0, 0, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; const long long inf = 1e18; int f[maxn][32], rt; long long ans, a[maxn]; vector<int> G[maxn]; void dfs(int u, int p) { long long d = 0; f[u][0] = p; for (d = 1; d <= 20; d++) { if (f[u][d - 1] != -1) f[u][d] = f[f[u][d - 1]][d - 1]; } long long tmp = inf; for (d = 0; d <= 20; d++) { if (f[u][d] != -1) tmp = min(tmp, (d + 1) * a[f[u][d]] + a[u]); else break; } tmp = min(tmp, (d + 1) * a[rt] + a[u]); if (p != -1) ans += tmp; for (int v : G[u]) if (v != p) dfs(v, u); } int main() { ios::sync_with_stdio(false); memset(f, -1, sizeof(f)); int n; cin >> n; a[rt] = inf; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] < a[rt]) rt = i; } for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } dfs(rt, -1); cout << ans << endl; }
|
`include "spi_master.v"
module oled_cls (
input clk,
input reset,
input cls_start,
output reg cls_fin,
output spi_csn,
output spi_sdo,
output spi_sclk,
output reg spi_dcn // active=command mode, inactive=data mode
);
`define CLS_SM_W 4
localparam STATE_IDLE = `CLS_SM_W'h0;
localparam STATE_SETDCN = `CLS_SM_W'h1;
localparam STATE_SETPAGE = `CLS_SM_W'h2;
localparam STATE_SETPAGENUM = `CLS_SM_W'h3;
localparam STATE_SETSTARTCOLLO = `CLS_SM_W'h4;
localparam STATE_SETSTARTCOLHI = `CLS_SM_W'h5;
localparam STATE_CLRDCN = `CLS_SM_W'h6;
localparam STATE_CLSCOL = `CLS_SM_W'h7;
localparam STATE_CLSCOLWAIT = `CLS_SM_W'h8;
localparam STATE_DONE = `CLS_SM_W'h9;
reg [`CLS_SM_W-1:0] current_state;
reg [7:0] spi_data;
reg spi_start;
wire spi_fin;
reg [6:0] column_counter;
reg [1:0] page_num;
always @(posedge clk or posedge reset) begin
if (reset) begin
cls_fin <= 'b0;
current_state <= STATE_IDLE;
spi_start <= 'b0;
spi_data <= 'b0;
spi_dcn <= 'b1;
column_counter <= 'b0;
page_num <= 'b0;
end else begin
case (current_state)
STATE_IDLE: begin
if (cls_start==1'b1) begin
current_state <= STATE_SETDCN;
spi_dcn <= 1'b0;
end
end
STATE_SETDCN: begin
current_state <= STATE_SETPAGE;
spi_start <= 'b1;
spi_data <= 8'h22;
end
STATE_SETPAGE: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_SETPAGENUM;
spi_start <= 'b1;
spi_data <= {6'h2C, page_num}; // PAGE#
end
end
STATE_SETPAGENUM: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_SETSTARTCOLLO;
spi_start <= 'b1;
spi_data <= 8'h00;
end
end
STATE_SETSTARTCOLLO: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_SETSTARTCOLHI;
spi_start <= 'b1;
spi_data <= 8'h10;
end
end
STATE_SETSTARTCOLHI: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_CLRDCN;
spi_dcn <= 1'b1;
end
end
STATE_CLRDCN: begin
current_state <= STATE_CLSCOL;
end
STATE_CLSCOL: begin
spi_start <= 'b1;
spi_data <= 8'h80;
current_state <= STATE_CLSCOLWAIT;
column_counter <= column_counter + 1;
if ((&column_counter)==1'b1) begin
spi_start <= 'b0;
page_num <= page_num + 1;
if ((&page_num)==1'b1) begin
current_state <= STATE_DONE;
cls_fin <= 'b1;
end else begin
current_state <= STATE_SETDCN;
spi_dcn <= 1'b0;
end
end
end
STATE_CLSCOLWAIT: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_CLSCOL;
end
end
STATE_DONE: begin
if (cls_start==1'b0) begin
cls_fin <= 'b0;
current_state <= STATE_IDLE;
end
end
endcase
end
end
spi_master i_spi_master (
.clk(clk),
.reset(reset),
.spi_start(spi_start),
.spi_data(spi_data),
.spi_fin(spi_fin),
.spi_csn(spi_csn),
.spi_sdo(spi_sdo),
.spi_sclk(spi_sclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int count = 0; for (int i = 0; i < n - 1; i++) { if (s[i] == s[i + 1]) { count++; } } cout << count; }
|
// megafunction wizard: %ALTDDIO_OUT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDDIO_OUT
// ============================================================
// File Name: delay.v
// Megafunction Name(s):
// ALTDDIO_OUT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module delay (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.cmp TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[300000], b[300000]; int tree[1 << 21], lazy[1 << 21]; int prop(int s, int e, int i) { tree[i] += lazy[i]; if (s != e) lazy[2 * i + 1] += lazy[i], lazy[2 * i + 2] += lazy[i]; lazy[i] = 0; return 0; } int update(int s, int e, int as, int ae, int i, int num) { prop(s, e, i); if ((s > ae) || (e < as)) return tree[i]; else if ((s >= as) && (e <= ae)) { lazy[i] += num; prop(s, e, i); return tree[i]; } int mid = (s + e) / 2; update(s, mid, as, ae, 2 * i + 1, num), update(mid + 1, e, as, ae, 2 * i + 2, num); tree[i] = min(tree[2 * i + 1], tree[2 * i + 2]); return tree[i]; } int query(int s, int e, int i) { prop(s, e, i); if (s == e) return s; int mid = (s + e) / 2; prop(mid + 1, e, 2 * i + 2); if (tree[2 * i + 2] < 0) return query(mid + 1, e, 2 * i + 2); else return query(s, mid, 2 * i + 1); } int main() { int i; int n, m, q; int t, j, x; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < m; i++) scanf( %d , &b[i]); for (i = 0; i < n; i++) update(0, 1000000, 1, a[i], 0, -1); for (i = 0; i < m; i++) update(0, 1000000, 1, b[i], 0, 1); scanf( %d , &q); for (i = 0; i < q; i++) { scanf( %d %d %d , &t, &j, &x), j--; if (t == 1) { update(0, 1000000, 1, a[j], 0, 1); a[j] = x; update(0, 1000000, 1, a[j], 0, -1); } else { update(0, 1000000, 1, b[j], 0, -1); b[j] = x; update(0, 1000000, 1, b[j], 0, 1); } int ans = query(0, 1000000, 0); if (ans == 0) printf( -1 n ); else printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int answer(); int main() { long long t; t = 1; while (t--) { answer(); } return 0; } int answer() { string k; cin >> k; int sup[10] = {2, 7, 2, 3, 3, 4, 2, 5, 1, 2}; if (k.size() > 1) { cout << sup[k[0] - 0 ] * sup[k[1] - 0 ] << endl; } else { cout << sup[k[0] - 0 ] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int powmod(long long int a, long long int e) { if (e == 0) return 1; long long int x = powmod(a * a % 1000000007, e >> 1); return e & 1 ? x * a % 1000000007 : x; } set<int> unvis; set<pair<long long int, long long int> > forbid; void dfs(int v) { int ver = -1; auto it = unvis.begin(); while (it != unvis.end()) { ver = *it; if (forbid.find({min(ver, v), max(ver, v)}) != forbid.end()) { it++; continue; } unvis.erase(it); dfs(ver); it = unvis.upper_bound(ver); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m, k; cin >> n >> m >> k; for (long long int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; forbid.insert({min(a, b), max(a, b)}); } for (long long int i = 0; i < n - 1; i++) unvis.insert(i + 1); dfs(0); if (!unvis.empty()) { cout << impossible ; return 0; } int cnt = 0; for (auto i : forbid) { if (i.first == 0) cnt++; else break; } for (long long int i = 1; i < n; i++) unvis.insert(i); int conn = 0; while (!unvis.empty()) { int x = *unvis.begin(); unvis.erase(unvis.begin()); dfs(x); conn++; } if (k >= conn and k <= n - 1 - cnt) cout << possible ; else cout << impossible ; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 18:14:28 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_stub.v
// Design : About
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module About(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[799:0]" */;
input clka;
input [9:0]addra;
output [799:0]douta;
endmodule
|
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