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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: swrvr_dlib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// DP library
// 2:1 MUX WITH ENCODED SELECT
module dp_mux2es (dout, in0, in1, sel) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
reg [SIZE-1:0] dout ;
always @ (sel or in0 or in1)
begin
case (sel)
1'b1: dout = in1 ;
1'b0: dout = in0;
default:
begin
if (in0 == in1) begin
dout = in0;
end
else
dout = {SIZE{1'bx}};
end
endcase // case(sel)
end
endmodule // dp_mux2es
// ----------------------------------------------------------------------
// 4:1 MUX WITH DECODED SELECTS
module dp_mux4ds (dout, in0, in1, in2, in3,
sel0_l, sel1_l, sel2_l, sel3_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk4 ($one_cold ({sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [3:0] sel = {sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3)
case ({sel3_l,sel2_l,sel1_l,sel0_l})
4'b1110 : dout = in0 ;
4'b1101 : dout = in1 ;
4'b1011 : dout = in2 ;
4'b0111 : dout = in3 ;
4'b1111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux4ds
// ----------------------------------------------------------------------
// 5:1 MUX WITH DECODED SELECTS
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk5 ($one_cold ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
in0 or in1 or in2 or in3 or in4)
case ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
5'b11110 : dout = in0 ;
5'b11101 : dout = in1 ;
5'b11011 : dout = in2 ;
5'b10111 : dout = in3 ;
5'b01111 : dout = in4 ;
5'b11111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux5ds
// --------------------------------------------------------------------
// 8:1 MUX WITH DECODED SELECTS
module dp_mux8ds (dout, in0, in1, in2, in3,
in4, in5, in6, in7,
sel0_l, sel1_l, sel2_l, sel3_l,
sel4_l, sel5_l, sel6_l, sel7_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input [SIZE-1:0] in5;
input [SIZE-1:0] in6;
input [SIZE-1:0] in7;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
input sel5_l;
input sel6_l;
input sel7_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk8 ($one_cold ({sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
sel4_l or sel5_l or sel6_l or sel7_l or in4 or in5 or in6 or in7)
case ({sel7_l,sel6_l,sel5_l,sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
8'b11111110 : dout = in0 ;
8'b11111101 : dout = in1 ;
8'b11111011 : dout = in2 ;
8'b11110111 : dout = in3 ;
8'b11101111 : dout = in4 ;
8'b11011111 : dout = in5 ;
8'b10111111 : dout = in6 ;
8'b01111111 : dout = in7 ;
8'b11111111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux8ds
// ----------------------------------------------------------------------
// 3:1 MUX WITH DECODED SELECTS
module dp_mux3ds (dout, in0, in1, in2,
sel0_l, sel1_l, sel2_l);
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0_l;
input sel1_l;
input sel2_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk3 ($one_cold ({sel2_l,sel1_l,sel0_l}));
`endif
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
case ({sel2_l,sel1_l,sel0_l})
3'b110 : dout = in0 ;
3'b101 : dout = in1 ;
3'b011 : dout = in2 ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux3ds
// ----------------------------------------------------------------------
module dp_buffer(dout, in);
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in;
assign dout = in;
endmodule // dp_buffer
|
module sineTable_tb ();
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire signed [17:0] sine;
reg signed [17:0] expectedSine;
reg [11:0] angle;
reg [11:0] angleD1;
reg clk;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
always #1 clk = ~clk;
initial begin
clk = 1'b0;
angle = 0;
angleD1 = 0;
// Let sine table start outputting valid data
@(posedge clk);
@(posedge clk);
// Run sine table over several frequencies
for (i=1; i<2**11; i=i<<1) begin // double frequency each time
@(posedge clk) angle = angle + i;
while (angle != 0) begin
@(posedge clk) angle = angle + i;
if ((sine - expectedSine > 1) || (sine - expectedSine < -1)) begin
$display("FAILED @ angle=%d", angleD1);
$finish(2);
end
end
end
$display("PASSED");
$finish(2);
end
always @(posedge clk) begin
angleD1 <= angle;
expectedSine <= $rtoi($floor($sin(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
end
sineTable #(
.ANGLE_WIDTH(12),
.OUT_WIDTH(18)
) uut (
.clk(clk), ///< System Clock
.angle(angle), ///< [ANGLE_WIDTH-1:0] Angle to take sine of
.sine(sine) ///< [OUT_WIDTH-1:0] Sine of angle
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_LP_V
`define SKY130_FD_SC_LP__NAND3B_LP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_LP_V
|
#include <bits/stdc++.h> using namespace std; long long pw[20][120], p[120], V, B, fA, fB, fC, ans; int num[120], n, T, i, j; void dfs_B(int l, long long x) { if ((double)x * x > V) return; if (l == n + 1) { B = max(B, x); return; } for (int i = 0; i <= num[l]; ++i) dfs_B(l + 1, x * pw[l][i]); } void dfs_A(int l, long long A) { if ((double)A * A * A > V) return; if (l == n + 1) { long long x = (int)sqrt(V / A); if (2 * A * x + V / A >= ans) return; V /= A; B = 0; dfs_B(1, 1); if (A * B + A * (V / B) + V < ans) { ans = A * B + A * (V / B) + V; fA = A; fB = B; fC = V / B; } V *= A; return; } for (int i = num[l]; i >= 0; --i) { num[l] -= i; dfs_A(l + 1, A * pw[l][i]); num[l] += i; } } int main() { for (scanf( %d , &T); T--;) { scanf( %d , &n); V = 1; for (i = 1; i <= n; ++i) { scanf( %I64d%d , &p[i], &num[i]); pw[i][0] = 1; for (j = 1; j <= num[i]; ++j) pw[i][j] = pw[i][j - 1] * p[i]; V *= pw[i][num[i]]; } ans = 1ll << 62; dfs_A(1, 1); printf( %I64d %I64d %I64d %I64d n , ans * 2, fA, fB, fC); } }
|
#include <bits/stdc++.h> using namespace std; long long t, n, m; long long pre[405][405], a[405][405], sum[405]; long long get(long long a, long long b, long long c) { return pre[b][c] - pre[a - 1][c]; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> t; while (t--) { cin >> n >> m; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { char f; cin >> f; a[i][j] = f - 0 ; pre[i][j] = pre[i - 1][j] + a[i][j]; } } long long res = 1000000000000000000; for (long long l = 1; l <= n - 4; l++) { for (long long r = l + 4; r <= n; r++) { long long mx = -1000000000000000000; for (long long k = 1; k <= 3; k++) sum[k] = sum[k - 1] + get(l + 1, r - 1, k) + (2 - a[l][k] - a[r][k]); for (long long k = 4; k <= m; k++) { sum[k] = sum[k - 1] + get(l + 1, r - 1, k) + (2 - a[l][k] - a[r][k]); mx = max(mx, sum[k - 3] - (r - l - 1) + get(l + 1, r - 1, k - 3)); res = min(res, sum[k - 1] + (r - l - 1) - get(l + 1, r - 1, k) - mx); } } } cout << res << n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long MOD = 1e9 + 7; const long long maxn = 2e5 + 7; const long long maxm = 2e5 + 7; int n; bool isPrime(int a) { for (int i = 2; i <= sqrt(a); i++) { if (a % i == 0) { return 0; } } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n; for (int m = 1;; m++) { if (!isPrime(n * m + 1)) { cout << m << endl; return 0; } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`ifdef VERILATOR
`define c(v,vs) ($c(vs)) // Don't constify a value
`else
`define c(v,vs) (v)
`endif
module t (/*AUTOARG*/
// Outputs
ow4_u
);
bit fail;
reg signed [3:0] w4_s;
reg signed [4:0] w5_s;
reg [2:0] w3_u;
reg [3:0] w4_u;
reg [4:0] w5_u;
reg [5:0] w6_u;
reg [15:0] w16a_u;
reg [15:0] w16_u;
reg [31:0] w32_u;
real r;
reg signed [4:0] bug754_a;
integer i;
//verilator lint_off WIDTH
wire a = (5'b0 == (5'sb11111 >>> 3'd7));
wire b = (5'sb11111 == (5'sb11111 >>> 3'd7));
wire c = (1'b0+(5'sb11111 >>> 3'd7));
wire d = (1'sb0+(5'sb11111 >>> 3'd7));
wire e = (5'b0 == (5'sb11111 / 5'sd3));
wire f = (5'sb0 == (5'sb11111 / 5'sd3));
wire g = (5'b01010 == (5'b11111 / 5'sd3));
initial begin
// verilator lint_off STMTDLY
#1;
`ifdef VCS // I-2014.03
`checkh({a, b, c, d, e, f, g}, 7'b1101111);
`else
`checkh({a, b, c, d, e, f, g}, 7'b1101011);
`endif
//======================================================================
if ((-1 >>> 3) != -1) $stop; // Decimals are signed
i = 3'sb111 >>> 3;
`checkh(i, -1);
i = -1 >>> 3;
`checkh(i, -1);
bug754_a = -1;
w4_u = |0 != (bug754_a >>> 3'd7);
`checkh(w4_u, 4'b0);
// Sanity check: -1>>7 == -1
w5_u = (5'sb11111 >>> 3'd7);
`checkh(w5_u, 5'b11111);
// bug756
w4_u = (5'b0 == (5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b0001);
w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0
`checkh(w4_u, 4'b0001);
w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>>
`ifdef VCS // I-2014.03
`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
`else
`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
`endif
// Does == sign propagate from lhs to rhs? Yes, but not in VCS
w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero
`ifdef VCS // I-2014.03
`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
`else
`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
`endif
w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter
`checkh(w4_u, 4'b0000);
w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero
`checkh(w4_u, 4'b0001);
// Does == width propagate from lhs to rhs? Yes
w4_u = (3'b100==(3'b111 << 2));
`checkh(w4_u, 4'b0001);
w4_u = (4'b100==(3'b111 << 2));
`checkh(w4_u, 4'b0000);
w4_u = (4'b1100==(3'b111 << 2));
`checkh(w4_u, 4'b0001);
// Does >>> sign propagate from input same as for +? Yes
w4_u = (1'b0+(5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b0000);
w4_u = (1'sb0+(5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b1111);
// Does << width propagate from input same as for +? Yes
w4_u = (3'b0+(3'b111 << 2));
`checkh(w4_u, 4'b1100); // width 4 =='s LHS
w4_u = (4'b0+(3'b111 << 2));
`checkh(w4_u, 4'b1100);
w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==?????
`checkh(w4_u, 4'b0001);
w4_u = ((5'b0 == (5'sb11111 >>> 3'd7)));
`checkh(w4_u, 4'b0001);
// bug756
w5_s = -1;
w3_u = 7;
w4_u = |0 != (w5_s >>> w3_u);
`checkh(w4_u, 4'b0000);
// bug763
w3_u = 2;
w4_u = (w3_u >> 2'b11) >> 1;
`checkh(w4_u, 4'b0000);
// bug766
w16a_u = 16'h1234;
w16_u = (w16a_u >> 16) >>> 32'h7ffffff1;
`checkh(w16_u, 16'h0000);
// bug768
w4_s = 4'sd4;
w4_u = $signed(5'd1 > w4_s-w4_s);
`checkh(w4_u, 4'b1111);
w4_s = `c(4,"4"); // Eval at runtime
w4_u = $signed(5'd1 > w4_s-w4_s);
`checkh(w4_u, 4'b1111);
// bug772
w4_s = w4_u << 1 <<< 0/0;
`ifndef VERILATOR // In v4 can't check value as not 4-state
`checkh(w4_s, 4'bxxxx);
`endif
// bug773
w5_u = `c(31, 31);
w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u);
`checkh(w5_s, 5'b0);
// bug774
w4_u = `c(4, 5);
w6_u = `c(6, 35);
w4_u = 64'd0 | (w4_u << w6_u);
`checkh(w4_u, 0);
// bug776
w4_u = `c(4, 1);
w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u);
`checkh(w4_u, 4'b1111);
// bug828
// verilator lint_off WIDTH
w32_u = 32'(signed'({4'b0001,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0180);
w32_u = 32'(signed'({4'b0011,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0380);
w32_u = signed'(32'({4'b0001,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0180);
w32_u = signed'(32'({4'b0011,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0380);
// verilator lint_on WIDTH
w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning
`checkh(w32_u, 32'h0000_0380);
if (fail) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
// bug775
output [3:0] ow4_u; // Must be consumed
assign ow4_u = ((0/0) ? 1 : 2) % 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int a, b; node(int a = 0, int b = 1e9) : a(a), b(b) {} int get(int x) { return a * x + b; } }; struct Eins { vector<node> st; int n; Eins(int n) : n(n) { st.resize(n << 2 | 1); } void modify(int id, int l, int r, node v) { int mid = l + r >> 1; if (st[id].get(mid) > v.get(mid)) { swap(st[id], v); } if (l == r) return; if (st[id].get(l) > v.get(l)) modify(id << 1, l, mid, v); if (st[id].get(r) > v.get(r)) modify(id << 1 | 1, mid + 1, r, v); } int get(int id, int l, int r, int x) { int ans = st[id].get(x); if (l == r) return ans; int mid = l + r >> 1; if (x <= mid) return min(ans, get(id << 1, l, mid, x)); return min(ans, get(id << 1 | 1, mid + 1, r, x)); } }; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<string> s(n + 1); vector<Eins> Tree(m + 1, Eins(n + 1)); auto sqr = [&](int x) { return x * x; }; for (int i = 0; i <= n; i++) { cin >> s[i]; int last = -1; for (int j = 0; j <= m; j++) { if (s[i][j] == 1 ) { if (last == -1) { for (int p = 0; p <= j; p++) { Tree[p].modify(1, 0, n, node(-2 * i, sqr(i) + sqr(p - j))); } } else { for (int p = last + 1; p <= j; p++) { Tree[p].modify( 1, 0, n, node(-2 * i, sqr(i) + min(sqr(p - j), sqr(last - p)))); } } last = j; } else if (j == m && last != -1) { for (int p = last + 1; p <= m; p++) { Tree[p].modify(1, 0, n, node(-2 * i, sqr(i) + sqr(p - last))); } } } } long long ans = 0; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { ans += Tree[j].get(1, 0, n, i) + sqr(i); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; int m = max((3 * a) / 10, a - (a * c) / 250); int v = max((3 * b) / 10, b - (b * d) / 250); if (m > v) cout << Misha << endl; else if (v > m) cout << Vasya << endl; else cout << Tie << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T BMOD(T p, T e, T m) { T ret = 1; while (e) { if (e & 1) ret = (ret * p) % m; p = (p * p) % m; e >>= 1; } return (T)ret; } template <class T> inline T MODINV(T a, T m) { return BMOD(a, m - 2, m); } template <class T> inline T isPrime(T a) { for (T i = 2; i <= sqrt(double(a)); i++) { if (a % i == 0) { return 0; } } return 1; } template <class T> inline T lcm(T a, T b) { return (a / __gcd(a, b)) * b; } template <class T> inline T power(T a, T b) { return (b == 0) ? 1 : a * power(a, b - 1); } template <class T> inline string to_str(T t) { stringstream ss; ss << t; return ss.str(); } int main() { int h, m; scanf( %d:%d , &h, &m); h %= 12; double a = h * 30.0 + (m / 2.0); double b = m * 6.0; printf( %.10lf %.10lf n , a, b); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_PP_BLACKBOX_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2008 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Rounding "macro"
// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
module round_reg
#(parameter bits_in=0,
parameter bits_out=0)
(input clk,
input [bits_in-1:0] in,
output reg [bits_out-1:0] out,
output reg [bits_in-bits_out:0] err);
wire [bits_out-1:0] temp;
wire [bits_in-bits_out:0] err_temp;
round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
always @(posedge clk)
out <= temp;
always @(posedge clk)
err <= err_temp;
endmodule // round_reg
|
//
// usb 3.0 tx scrambling and elastic buffer padding
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_scramble (
input wire clock,
input wire local_clk,
input wire reset_n,
input wire enable,
input wire skp_inhibit,
input wire skp_defer,
input wire [3:0] raw_datak,
input wire [31:0] raw_data,
input wire raw_active,
output reg raw_stall,
output reg [3:0] proc_datak,
output reg [31:0] proc_data,
output reg err_empty_accum
);
`include "usb3_const.v"
reg reset_n_1;
reg enable_1;
// indicates presence of COM at last symbol position (K28.5)
wire comma = { (pl_data[7:0] == 8'hBC) & pl_datak[0] };
reg comma_1;
reg [31:0] pl_data;
reg [3:0] pl_datak;
reg pl_active;
// step 1.
// accept incoming data, but inject SKP sets to allow remote elastic buffer
// to catch up and compensate for spread spectrum clocking.
wire insert_skp = enable && symbols_since_skp > 78;
// nominal SKP insertion rate is every 354 symbols.
// however due to SSC profiles varying across the industry (i.e. +/- 2500ppm vs. -5000 to 0 ppm)
// err on the safe side and send more SKP.
reg [15:0] symbols_since_skp;
reg [2:0] num_queued_skp;
reg [31:0] ac_data;
reg [3:0] ac_datak;
always @(posedge local_clk) begin
pl_data <= raw_data;
pl_datak <= raw_datak;
pl_active <= raw_active;
reset_n_1 <= reset_n;
comma_1 <= comma;
enable_1 <= enable;
raw_stall <= 0;
// increment symbol sent counter
if(enable_1) `INC(symbols_since_skp);
if(insert_skp) begin
symbols_since_skp <= 0;
// increment number of queued sets up to 4
if(num_queued_skp < 4)
`INC(num_queued_skp);
end
if(enable_1) begin
if(num_queued_skp == 0 || pl_active) begin
// don't inject SKP
ac_data[31:24] <= pl_datak[3] ? pl_data[31:24] : pl_data[31:24] ^ sp_pick32[31:24];
ac_data[23:16] <= pl_datak[2] ? pl_data[23:16] : pl_data[23:16] ^ sp_pick32[23:16];
ac_data[15:8 ] <= pl_datak[1] ? pl_data[15:8 ] : pl_data[15:8 ] ^ sp_pick32[15:8 ];
ac_data[ 7:0 ] <= pl_datak[0] ? pl_data[ 7:0 ] : pl_data[ 7:0 ] ^ sp_pick32[ 7:0 ];
ac_datak <= pl_datak;
end else if(num_queued_skp == 1) begin
// only 1 ordered set needed
ac_data <= {16'h3C3C, pl_data[15:0] ^ sp_pick16[15:0]};
ac_datak <= {2'b11, pl_datak[1:0]};
raw_stall <= 1;
`DEC(num_queued_skp);
end else begin
// 2 or more sets needed
ac_data <= {32'h3C3C3C3C};
ac_datak <= {4'b1111};
raw_stall <= 1;
num_queued_skp <= num_queued_skp - 2'h2;
end
end else begin
ac_data <= pl_data;
ac_datak <= pl_datak;
end
proc_data <= ac_data;
proc_datak <= ac_datak;
err_empty_accum <= 0;
if(~enable_1) begin
symbols_since_skp <= 0;
num_queued_skp <= 0;
end
if(~reset_n) begin
symbols_since_skp <= 0;
end
end
always @(*) begin
//
// combinational to give us 1 cycle foresight so that
// the lfsr pool can have next word prepared in time
//
if(enable_1) begin
if(num_queued_skp == 0 || pl_active) begin
// don't inject SKP
sp_read_num = 4;
end else if(num_queued_skp == 1) begin
// only 1 ordered set needed
sp_read_num = 2;
end else begin
// 2 or more sets needed
sp_read_num = 0;
end
end else begin
sp_read_num = 0;
end
end
//
// scrambling LFSR pool
//
reg [63:0] sp_data;
reg [3:0] sp_depth;
reg [3:0] sp_read_num;
wire sp_dofill = ((sp_depth+8 - sp_read_num) <= 12);
wire [15:0] sp_pick16 = sp_pick32[31:16];
wire [31:0] sp_pick32 = (sp_depth == 4) ? sp_data[31:0] :
(sp_depth == 6) ? sp_data[47:16] :
(sp_depth == 8) ? sp_data[63:32] : 32'hFFFFFFFF;
always @(posedge local_clk) begin
sp_depth <= sp_depth - sp_read_num + (sp_dofill ? 4'h4 : 4'h0);
if(sp_dofill) sp_data <= {sp_data[31:0], ds_out};
if(~reset_n_1 | comma_1) begin
sp_depth <= 0;
//sp_data <= 32'hEEEEEEEE;
end
end
//
// data scrambling for TX
//
wire [31:0] ds_out = {ds_out_swap[7:0], ds_out_swap[15:8],
ds_out_swap[23:16], ds_out_swap[31:24]};
wire [31:0] ds_out_swap;
usb3_lfsr iu3srx(
.clock ( local_clk ),
.reset_n ( reset_n ),
.data_in ( 32'h0 ),
.scram_en ( comma | sp_dofill),
.scram_rst ( comma | ~reset_n),
.scram_init ( 16'h7DBD ),
.data_out ( ds_out_swap )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR2_BEHAVIORAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int64_t a, b, x, y, z; scanf( %I64d%I64d%I64d%I64d%I64d , &a, &b, &x, &y, &z); int64_t addA, addB; if (2LL * x + y - a > 0) addA = 2LL * x + y - a; else int64_t addA = 0; if (3LL * z + y - b > 0) addB = 3LL * z + y - b; else addB = 0; printf( %I64d n , addA + addB); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 200005; int n, m; long long ans[Maxn]; struct Segment { long long l, r; int pos; } A[Maxn], land[Maxn]; bool cmp(const Segment &a, const Segment &b) { return a.l < b.l || a.l == b.l && a.r < b.r; } struct node { int pos; long long val; node() {} node(int _pos, long long _val) { pos = _pos; val = _val; } } p[Maxn]; bool operator<(node a, node b) { return a.val > b.val; } bool cmp2(const node &a, const node &b) { return a.val < b.val; } priority_queue<node> H; int Get() { char ch; int v = 0; bool f = false; while (!isdigit(ch = getchar())) if (ch == - ) f = true; v = ch - 48; while (isdigit(ch = getchar())) v = v * 10 + ch - 48; if (f) return -v; else return v; } int main() { n = Get(), m = Get(); for (int i = 1; i <= n; i++) scanf( %I64d%I64d , &land[i].l, &land[i].r); for (int i = 1; i <= m; i++) scanf( %I64d , &p[i].val), p[i].pos = i; for (int i = 1; i <= n - 1; i++) A[i].l = land[i + 1].l - land[i].r, A[i].r = land[i + 1].r - land[i].l, A[i].pos = i; n--; sort(A + 1, A + 1 + n, cmp); sort(p + 1, p + 1 + m, cmp2); if (m < n) { puts( No ); return 0; } long long mx = 0; for (int i = 1, j = 1; i <= m; i++) { while (A[j].l <= p[i].val && j <= n) H.push(node(A[j].pos, A[j].r)), j++; while (!H.empty() && H.top().val < p[i].val) H.pop(); if (!H.empty()) { node tmp = H.top(); ans[tmp.pos] = p[i].pos; H.pop(); } } bool flag = true; for (int i = 1; i <= n; i++) if (ans[i] == 0) flag = false; if (flag) { puts( Yes ); for (int i = 1; i <= n - 1; i++) printf( %d , ans[i]); printf( %d n , ans[n]); } else puts( No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, v[100002], nr; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i]; } sort(v + 1, v + n + 1); for (int i = 1; i <= n - 2; i++) { if (v[i] + v[i + 1] > v[i + 2]) nr++; } if (nr == 0) cout << NO n ; else cout << YES n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FAH_PP_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MN = 52; const long long mod = 1e9 + 7; int N; long long dp[2][MN][MN][MN][MN]; vector<int> d; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> N; d.resize(N); for (int i = 0; i < N; i++) { cin >> d[i]; } int cur = 0, next = 1; dp[cur][d[0] == 2][d[0] == 3][d[1] == 2][d[1] == 3] = 1; for (int i = 1; i < N - 1; i++) { memset(dp[next], 0, sizeof(dp[next])); for (int p1 = 0; p1 <= N; p1++) for (int p2 = 0; p1 + p2 <= N; p2++) for (int c1 = 0; c1 + p1 + p2 <= N; c1++) for (int c2 = 0; c1 + c2 + p1 + p2 <= N; c2++) { if (dp[cur][p1][p2][c1][c2] == 0) continue; long long val = dp[cur][p1][p2][c1][c2]; if (p1 == 0 && p2 == 0) { dp[cur][c1][c2][0][0] += val; dp[cur][c1][c2][0][0] %= mod; continue; } for (int type = 0; type <= 1; type++) { int way; if (type == 0) { way = p1; if (p1 == 0) continue; p1--; } else { way = p2; if (p2 == 0) continue; p1++, p2--; } if (d[i + 1] == 2) { dp[next][p1][p2][c1 + 1][c2] += val * way; dp[next][p1][p2][c1 + 1][c2] %= mod; if (c1 >= 1) { dp[next][p1][p2][c1 - 1][c2] += val * way * c1; dp[next][p1][p2][c1 - 1][c2] %= mod; } if (c2 >= 1) { dp[next][p1][p2][c1 + 1][c2 - 1] += val * way * c2; dp[next][p1][p2][c1 + 1][c2 - 1] %= mod; } } else { dp[next][p1][p2][c1][c2 + 1] += val * way; dp[next][p1][p2][c1][c2 + 1] %= mod; if (c1 >= 1) { dp[next][p1][p2][c1 - 1 + 1][c2] += val * way * c1; dp[next][p1][p2][c1 - 1 + 1][c2] %= mod; } if (c2 >= 1) { dp[next][p1][p2][c1 + 2][c2 - 1] += val * way * c2; dp[next][p1][p2][c1 + 2][c2 - 1] %= mod; } if (c1 >= 2) { dp[next][p1][p2][c1 - 2][c2] += val * way * c1 * (c1 - 1) / 2; dp[next][p1][p2][c1 - 2][c2] %= mod; } if (c2 >= 2) { dp[next][p1][p2][c1 + 2][c2 - 2] += val * way * c2 * (c2 - 1) / 2; dp[next][p1][p2][c1 + 2][c2 - 2] %= mod; } if (c1 >= 1 && c2 >= 1) { dp[next][p1][p2][c1 - 1 + 1][c2 - 1] += val * way * c2 * c1; dp[next][p1][p2][c1 - 1 + 1][c2 - 1] %= mod; } } if (type == 0) { p1++; } else { p1--, p2++; } } } cur ^= 1, next ^= 1; } cout << dp[cur][0][0][0][0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T POW(T b, T p) { T r = 1; while (p) { if (p & 1) r = (r * b); b = (b * b); p >>= 1; } return r; } template <typename T> T BigMod(T b, T p, T m) { T r = 1; while (p) { if (p & 1) r = (r * b) % m; b = (b * b) % m; p >>= 1; } return r; } int main() { long long n, a, b, c, cnt; while (cin >> n) { a = 1; b = 1; cnt = 0; while (1) { c = a + b; a = b; b = c; if (c <= n) cnt++; else break; } cout << cnt << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> tree[100005]; int bad[100005]; vector<int> result; int SubTree[100005]; int dfs(int v, int pv) { SubTree[v] = (int)(bad[v] == 1); for (auto u : tree[v]) { if (u == pv) continue; SubTree[v] += dfs(u, v); } if (SubTree[v] == 1) result.push_back(v); return SubTree[v]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int N; cin >> N; for (int i = 0; i < N - 1; i++) { int a, b, c; cin >> a >> b >> c; tree[a].push_back(b); tree[b].push_back(a); if (c == 2) { bad[a] = bad[b] = 1; } } dfs(1, 0); cout << result.size() << n ; for (auto i : result) cout << i << ; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; using db = double; using str = string; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<db, db>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<db>; using vs = vector<str>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; template <class T> using V = vector<T>; template <class T, size_t SZ> using AR = array<T, SZ>; const int MOD = 1e9 + 7; const ll INF = 1e18; const ll infl = 1e18 + 5; const int infi = 1e9 + 5; const int xd[4] = {1, 0, -1, 0}, yd[4] = {0, 1, 0, -1}; mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return 31 - __builtin_clz(x); } ll cdiv(ll a, ll b) { return a / b + ((a ^ b) > 0 && a % b); } ll fdiv(ll a, ll b) { return a / b - ((a ^ b) < 0 && a % b); } template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T, class U> T fstTrue(T lo, T hi, U f) { hi++; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo) / 2; f(mid) ? hi = mid : lo = mid + 1; } return lo; } template <class T, class U> T lstTrue(T lo, T hi, U f) { lo--; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo + 1) / 2; f(mid) ? lo = mid : hi = mid - 1; } return lo; } template <class T> void remDup(vector<T>& v) { sort(begin(v), end(v)); v.erase(unique(begin(v), end(v)), end(v)); } template <class T, class U> void erase(T& t, const U& u) { auto it = t.find(u); assert(it != end(t)); t.erase(u); } template <class T> void re(T& x) { cin >> x; } void re(db& d) { str t; re(t); d = stod(t); } void re(ld& d) { str t; re(t); d = stold(t); } template <class T, class... U> void re(T& t, U&... u) { re(t); re(u...); } template <class T> void re(complex<T>& c) { T a, b; re(a, b); c = {a, b}; } template <class T, class U> void re(pair<T, U>& p) { re(p.f, p.s); } template <class T> void re(vector<T>& x) { for (auto& a : x) re(a); } template <class T, size_t SZ> void re(AR<T, SZ>& x) { for (auto& a : x) re(a); } str to_string(char c) { return str(1, c); } str to_string(const char* s) { return (str)s; } str to_string(str s) { return s; } str to_string(bool b) { return to_string((int)b); } template <class T> str to_string(complex<T> c) { stringstream ss; ss << c; return ss.str(); } str to_string(vector<bool> v) { str res = { ; for (int i = (0); i < ((int)(v).size()); ++i) res += char( 0 + v[i]); res += } ; return res; } template <size_t SZ> str to_string(bitset<SZ> b) { str res = ; for (int i = (0); i < (SZ); ++i) res += char( 0 + b[i]); return res; } template <class T> str to_string(T v) { bool fst = 1; str res = ; for (const auto& x : v) { if (!fst) res += ; fst = 0; res += to_string(x); } return res; } template <class T, class U> str to_string(pair<T, U> p) { return to_string(p.f) + + to_string(p.s); } template <class T> void pr(T x) { cout << to_string(x); } template <class T, class... U> void pr(const T& t, const U&... u) { pr(t); pr(u...); } void ps() { pr( n ); } template <class T, class... U> void ps(const T& t, const U&... u) { pr(t); if (sizeof...(u)) pr( ); ps(u...); } void pdbg(ll t) { cerr << t; } void pdbg(int t) { cerr << t; } void pdbg(str t) { cerr << t; } void pdbg(char t) { cerr << t; } void pdbg(ld t) { cerr << t; } void pdbg(db t) { cerr << t; } void pdbg(ull t) { cerr << t; } template <class T, class V> void pdbg(pair<T, V> p) { cerr << { ; pdbg(p.ff); cerr << , ; pdbg(p.ss); cerr << } ; } template <class T> void pdbg(vector<T> v) { cerr << [ ; for (T i : v) { pdbg(i); cerr << ; } cerr << ] ; } template <class T> void pdbg(set<T> v) { cerr << [ ; for (T i : v) { pdbg(i); cerr << ; } cerr << ] ; } template <class T> void pdbg(multiset<T> v) { cerr << [ ; for (T i : v) { pdbg(i); cerr << ; } cerr << ] ; } template <class T, class V> void pdbg(map<T, V> v) { cerr << [ ; for (auto i : v) { pdbg(i); cerr << ; } cerr << ] ; } void solve() { ll n; re(n); str s; re(s); str t; re(t); ll a1 = 0, b1 = 0; ll a2 = 0, b2 = 0; for (int i = (0); i < (n); ++i) { if (s[i] == a ) { a1 += 1; } else { b1 += 1; } if (t[i] == a ) { a2 += 1; } else { b2 += 1; } } if ((a1 + a2) % 2 == 0 && (b1 + b2) % 2 == 0) { ll ans = 0; ll ab = 0, ba = 0; vl aa1; vl aa2; vl bb1; vl bb2; for (int i = (0); i < (n); ++i) { if (s[i] == a && t[i] == b ) { ab += 1; aa1.push_back(i + 1); bb2.push_back(i + 1); } else if (s[i] == b && t[i] == a ) { ba += 1; bb1.push_back(i + 1); aa2.push_back(i + 1); } } ans += ab / 2; ans += ba / 2; if (ab % 2 == 1) { ans += 2; } ps(ans); if (aa1.size() != 0 || aa2.size() != 0) { while (aa1.size() > 1) { cout << aa1[aa1.size() - 1] << << bb2[aa1.size() - 2] << endl; aa1.pop_back(); bb2.pop_back(); aa1.pop_back(); bb2.pop_back(); } while (aa2.size() > 1) { cout << aa2[aa2.size() - 1] << << bb1[aa2.size() - 2] << endl; aa2.pop_back(); bb1.pop_back(); aa2.pop_back(); bb1.pop_back(); } if (aa1.size() == 1) { cout << aa1[0] << << bb2[0] << endl; cout << aa1[0] << << bb1[0] << endl; aa1.pop_back(); bb1.pop_back(); aa2.pop_back(); bb2.pop_back(); } } } else { cout << -1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll T = 1; for (int i = (0); i < (T); ++i) solve(); return 0; }
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// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module dotp_wrapper_tom_sv (
clock,
resetn,
valid_in,
stall_in,
valid_out,
stall_out,
a0, a1, a2, a3,
b0, b1, b2, b3,
result
);
input clock;
input resetn;
input valid_in;
input stall_in;
output valid_out;
output stall_out;
input [511:0] a0;
input [511:0] a1;
input [511:0] a2;
input [511:0] a3;
input [511:0] b0;
input [511:0] b1;
input [511:0] b2;
input [511:0] b3;
output [31:0] result;
wire input_accepted;
wire output_accepted;
assign input_accepted = valid_in & ~stall_out;
assign output_accepted = valid_out & ~stall_in;
reg [7:0] occ_counter;
wire [31:0] core_result;
wire core_valid;
assign stall_out = occ_counter[6];
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
occ_counter <= 8'b0;
end
else
begin
occ_counter <= occ_counter + input_accepted - output_accepted;
end
end
acl_fp_dot_product_64 dot_product (
.clock(clock),
.resetn(resetn),
.valid_in(input_accepted),
.datain_a_00(a0[31:0]),
.datain_a_01(a0[63:32]),
.datain_a_02(a0[95:64]),
.datain_a_03(a0[127:96]),
.datain_a_04(a0[159:128]),
.datain_a_05(a0[191:160]),
.datain_a_06(a0[223:192]),
.datain_a_07(a0[255:224]),
.datain_a_08(a0[287:256]),
.datain_a_09(a0[319:288]),
.datain_a_10(a0[351:320]),
.datain_a_11(a0[383:352]),
.datain_a_12(a0[415:384]),
.datain_a_13(a0[447:416]),
.datain_a_14(a0[479:448]),
.datain_a_15(a0[511:480]),
.datain_a_16(a1[31:0]),
.datain_a_17(a1[63:32]),
.datain_a_18(a1[95:64]),
.datain_a_19(a1[127:96]),
.datain_a_20(a1[159:128]),
.datain_a_21(a1[191:160]),
.datain_a_22(a1[223:192]),
.datain_a_23(a1[255:224]),
.datain_a_24(a1[287:256]),
.datain_a_25(a1[319:288]),
.datain_a_26(a1[351:320]),
.datain_a_27(a1[383:352]),
.datain_a_28(a1[415:384]),
.datain_a_29(a1[447:416]),
.datain_a_30(a1[479:448]),
.datain_a_31(a1[511:480]),
.datain_a_32(a2[31:0]),
.datain_a_33(a2[63:32]),
.datain_a_34(a2[95:64]),
.datain_a_35(a2[127:96]),
.datain_a_36(a2[159:128]),
.datain_a_37(a2[191:160]),
.datain_a_38(a2[223:192]),
.datain_a_39(a2[255:224]),
.datain_a_40(a2[287:256]),
.datain_a_41(a2[319:288]),
.datain_a_42(a2[351:320]),
.datain_a_43(a2[383:352]),
.datain_a_44(a2[415:384]),
.datain_a_45(a2[447:416]),
.datain_a_46(a2[479:448]),
.datain_a_47(a2[511:480]),
.datain_a_48(a3[31:0]),
.datain_a_49(a3[63:32]),
.datain_a_50(a3[95:64]),
.datain_a_51(a3[127:96]),
.datain_a_52(a3[159:128]),
.datain_a_53(a3[191:160]),
.datain_a_54(a3[223:192]),
.datain_a_55(a3[255:224]),
.datain_a_56(a3[287:256]),
.datain_a_57(a3[319:288]),
.datain_a_58(a3[351:320]),
.datain_a_59(a3[383:352]),
.datain_a_60(a3[415:384]),
.datain_a_61(a3[447:416]),
.datain_a_62(a3[479:448]),
.datain_a_63(a3[511:480]),
.datain_b_00(b0[31:0]),
.datain_b_01(b0[63:32]),
.datain_b_02(b0[95:64]),
.datain_b_03(b0[127:96]),
.datain_b_04(b0[159:128]),
.datain_b_05(b0[191:160]),
.datain_b_06(b0[223:192]),
.datain_b_07(b0[255:224]),
.datain_b_08(b0[287:256]),
.datain_b_09(b0[319:288]),
.datain_b_10(b0[351:320]),
.datain_b_11(b0[383:352]),
.datain_b_12(b0[415:384]),
.datain_b_13(b0[447:416]),
.datain_b_14(b0[479:448]),
.datain_b_15(b0[511:480]),
.datain_b_16(b1[31:0]),
.datain_b_17(b1[63:32]),
.datain_b_18(b1[95:64]),
.datain_b_19(b1[127:96]),
.datain_b_20(b1[159:128]),
.datain_b_21(b1[191:160]),
.datain_b_22(b1[223:192]),
.datain_b_23(b1[255:224]),
.datain_b_24(b1[287:256]),
.datain_b_25(b1[319:288]),
.datain_b_26(b1[351:320]),
.datain_b_27(b1[383:352]),
.datain_b_28(b1[415:384]),
.datain_b_29(b1[447:416]),
.datain_b_30(b1[479:448]),
.datain_b_31(b1[511:480]),
.datain_b_32(b2[31:0]),
.datain_b_33(b2[63:32]),
.datain_b_34(b2[95:64]),
.datain_b_35(b2[127:96]),
.datain_b_36(b2[159:128]),
.datain_b_37(b2[191:160]),
.datain_b_38(b2[223:192]),
.datain_b_39(b2[255:224]),
.datain_b_40(b2[287:256]),
.datain_b_41(b2[319:288]),
.datain_b_42(b2[351:320]),
.datain_b_43(b2[383:352]),
.datain_b_44(b2[415:384]),
.datain_b_45(b2[447:416]),
.datain_b_46(b2[479:448]),
.datain_b_47(b2[511:480]),
.datain_b_48(b3[31:0]),
.datain_b_49(b3[63:32]),
.datain_b_50(b3[95:64]),
.datain_b_51(b3[127:96]),
.datain_b_52(b3[159:128]),
.datain_b_53(b3[191:160]),
.datain_b_54(b3[223:192]),
.datain_b_55(b3[255:224]),
.datain_b_56(b3[287:256]),
.datain_b_57(b3[319:288]),
.datain_b_58(b3[351:320]),
.datain_b_59(b3[383:352]),
.datain_b_60(b3[415:384]),
.datain_b_61(b3[447:416]),
.datain_b_62(b3[479:448]),
.datain_b_63(b3[511:480]),
.result(core_result),
.enable(1'b1),
.valid_out(core_valid));
/*acl_fifo #(
.DATA_WIDTH(32),
.DEPTH(64)
) collection_fifo (
.clock(clock),
.resetn(resetn),
.data_in( core_result ),
.data_out( result ),
.valid_in( core_valid ),
.valid_out( valid_out ),
.stall_in( stall_in ),
.stall_out( )
);*/
assign result = core_result;
assign valid_out = core_valid;
endmodule
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#include <bits/stdc++.h> using namespace std; const long long INF = 1000 * 1000 * 1000; struct rib { long long b, u, c, f; size_t back; }; void add_rib(vector<vector<rib> >& g, long long a, long long b, long long u, long long c) { rib r1 = {b, u, c, 0, g[b].size()}; rib r2 = {a, 0, -c, 0, g[a].size()}; g[a].push_back(r1); g[b].push_back(r2); } namespace k { long long n, m, k, c, d; } vector<long long> vr[55]; long long lr[50]; int main() { long long n = 6001, m, k = INF; vector<vector<rib> > g(n); long long s, t; cin >> k::n >> k::m >> k::k >> k::c >> (k::d); long long tim = 100; for (int i = 1; i < k::k + 1; i++) { cin >> lr[i]; add_rib(g, 0, lr[i], 1, 0); } for (int j = 0; j < tim - 1; j++) { for (int i = 2; i < k::n + 1; i++) add_rib(g, j * 50 + i, (j + 1) * 50 + i, 50, k::c); } for (int j = 1; j < tim; j++) { add_rib(g, j * 50 + 1, 1, 50, 0); } for (int i = 0; i < k::m; i++) { long long x, y; cin >> x >> y; vr[x].push_back(y); vr[y].push_back(x); for (int j = 0; j < tim - 1; j++) { for (int l = 0; l < 50; l++) { add_rib(g, j * 50 + x, (j + 1) * 50 + y, 1, (k::c) + (k::d) * ((l + 1) * (l + 1) - (l * l))); add_rib(g, j * 50 + y, (j + 1) * 50 + x, 1, (k::c) + (k::d) * ((l + 1) * (l + 1) - (l * l))); } } } s = 0, t = 1; long long flow = 0, cost = 0; while (flow < k) { vector<long long> id(n, 0); vector<long long> d(n, INF); vector<long long> q(n); vector<long long> p(n); vector<size_t> p_rib(n); long long qh = 0, qt = 0; q[qt++] = s; d[s] = 0; while (qh != qt) { long long v = q[qh++]; id[v] = 2; if (qh == n) qh = 0; for (size_t i = 0; i < g[v].size(); ++i) { rib& r = g[v][i]; if (r.f < r.u && d[v] + r.c < d[r.b]) { d[r.b] = d[v] + r.c; if (id[r.b] == 0) { q[qt++] = r.b; if (qt == n) qt = 0; } else if (id[r.b] == 2) { if (--qh == -1) qh = n - 1; q[qh] = r.b; } id[r.b] = 1; p[r.b] = v; p_rib[r.b] = i; } } } if (d[t] == INF) break; long long addflow = k - flow; for (long long v = t; v != s; v = p[v]) { long long pv = p[v]; size_t pr = p_rib[v]; addflow = min(addflow, g[pv][pr].u - g[pv][pr].f); } for (long long v = t; v != s; v = p[v]) { long long pv = p[v]; size_t pr = p_rib[v], r = g[pv][pr].back; g[pv][pr].f += addflow; g[v][r].f -= addflow; cost += g[pv][pr].c * addflow; } flow += addflow; } cout << cost << n ; }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename C> class mcmf { public: static constexpr T eps = (T)1e-9; struct edge { int from; int to; T c; T f; C cost; }; vector<vector<int> > g; vector<edge> edges; vector<C> d; vector<int> q; vector<bool> in_queue; vector<int> pe; int n; int st, fin; T flow; C cost; mcmf(int _n, int _st, int _fin) : n(_n), st(_st), fin(_fin) { assert(0 <= st && st < n && 0 <= fin && fin < n && st != fin); g.resize(n); d.resize(n); in_queue.resize(n); pe.resize(n); flow = 0; cost = 0; } void clear_flow() { for (const edge &e : edges) { e.f = 0; } flow = 0; } void add(int from, int to, T forward_cap, T backward_cap, C cost) { assert(0 <= from && from < n && 0 <= to && to < n); g[from].push_back((int)edges.size()); edges.push_back({from, to, forward_cap, 0, cost}); g[to].push_back((int)edges.size()); edges.push_back({to, from, backward_cap, 0, -cost}); } bool expath() { fill(d.begin(), d.end(), numeric_limits<C>::max()); q.clear(); q.push_back(st); d[st] = 0; in_queue[st] = true; int beg = 0; bool found = false; while (beg < (int)q.size()) { int i = q[beg++]; if (i == fin) { found = true; } in_queue[i] = false; for (int id : g[i]) { const edge &e = edges[id]; if (e.c - e.f > eps && d[i] + e.cost < d[e.to]) { d[e.to] = d[i] + e.cost; pe[e.to] = id; if (!in_queue[e.to]) { q.push_back(e.to); in_queue[e.to] = true; } } } } if (d[fin] >= 0) found = 0; if (found) { T push = numeric_limits<T>::max(); int v = fin; while (v != st) { const edge &e = edges[pe[v]]; push = min(push, e.c - e.f); v = e.from; } v = fin; while (v != st) { edge &e = edges[pe[v]]; e.f += push; edge &back = edges[pe[v] ^ 1]; back.f -= push; v = e.from; } flow += push; cost += push * d[fin]; } return found; } pair<T, C> max_flow_min_cost() { while (expath()) { } return make_pair(flow, cost); } }; const int MG1 = 1e5; int n1, n2, m, r, b; string s1, s2; int eu[200], ev[200], er[200]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n1 >> n2 >> m >> r >> b >> s1 >> s2; mcmf<int, int> a(n1 + n2 + 2, n1 + n2, n1 + n2 + 1); memset(er, -1, sizeof(er)); for (int i = 0, j = 0; i < m; ++i) { cin >> eu[i] >> ev[i], --eu[i], --ev[i]; if (s1[eu[i]] == U && s2[ev[i]] == U ) continue; if (s1[eu[i]] == U && s2[ev[i]] == R ) { a.add(n1 + n2, n1 + ev[i], 1, 0, r); er[i] = j++; continue; } if (s1[eu[i]] == U && s2[ev[i]] == B ) { a.add(n1 + ev[i], n1 + n2 + 1, 1, 0, b); er[i] = j++; continue; } if (s1[eu[i]] == R && s2[ev[i]] == U ) { a.add(eu[i], n1 + n2 + 1, 1, 0, r); er[i] = j++; continue; } if (s1[eu[i]] == B && s2[ev[i]] == U ) { a.add(n1 + n2, eu[i], 1, 0, b); er[i] = j++; continue; } a.add(eu[i], n1 + ev[i], 1, 0, r); a.add(n1 + ev[i], eu[i], 1, 0, b); er[i] = j; j += 2; } int tmg = 0; for (int i = 0; i < n1; ++i) { if (s1[i] == R ) { a.add(n1 + n2, i, 1, 0, -MG1); a.add(n1 + n2, i, 200, 0, 0); tmg -= MG1; } else if (s1[i] == B ) { a.add(i, n1 + n2 + 1, 1, 0, -MG1); a.add(i, n1 + n2 + 1, 200, 0, 0); tmg -= MG1; } } for (int i = 0; i < n2; ++i) { if (s2[i] == R ) { a.add(n1 + i, n1 + n2 + 1, 1, 0, -MG1); a.add(n1 + i, n1 + n2 + 1, 200, 0, 0); tmg -= MG1; } else if (s2[i] == B ) { a.add(n1 + n2, n1 + i, 1, 0, -MG1); a.add(n1 + n2, n1 + i, 200, 0, 0); tmg -= MG1; } } pair<int, int> p = a.max_flow_min_cost(); int cost = p.second - tmg; if (cost >= MG1) { cout << -1; return 0; } cout << cost << n ; for (int i = 0; i < m; ++i) { if (s1[eu[i]] == U && s2[ev[i]] == U ) { cout << U ; continue; } if (s1[eu[i]] == U && s2[ev[i]] == R ) { if (a.edges[2 * er[i]].f) cout << R ; else cout << U ; continue; } if (s1[eu[i]] == U && s2[ev[i]] == B ) { if (a.edges[2 * er[i]].f) cout << B ; else cout << U ; continue; } if (s1[eu[i]] == R && s2[ev[i]] == U ) { if (a.edges[2 * er[i]].f) cout << R ; else cout << U ; continue; } if (s1[eu[i]] == B && s2[ev[i]] == U ) { if (a.edges[2 * er[i]].f) cout << B ; else cout << U ; continue; } if (a.edges[2 * er[i]].f) cout << R ; else if (a.edges[2 * (er[i] + 1)].f) cout << B ; else cout << U ; } }
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; const int inf = 0x3f3f3f3f; const long long int INF = 1e15; const int mod = 1e9 + 7; const int maxn = 2e3 + 5; int cas = 1; int sum[maxn]; vector<int> v; map<int, int> mp; void solve() { int n, k; while (~scanf( %d%d , &n, &k)) { memset(sum, 0, sizeof(sum)); v.clear(); mp.clear(); for (int i = 1; i <= n; i++) { int u; scanf( %d , &u); sum[i] = sum[i - 1] + u; } sort(sum + 1, sum + 1 + n); int len = unique(sum + 1, sum + 1 + n) - (sum + 1); for (int i = 1; i <= k; i++) { int u; scanf( %d , &u); for (int j = 1; j <= len; j++) { v.push_back(u - sum[j]); } } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { mp[v[i]]++; } int res = 0; for (int i = 0; i < v.size(); i++) { if (mp[v[i]] >= k) { res++; mp[v[i]] = 0; } } printf( %d n , res); } } int main() { int t = 1; while (t--) { solve(); } }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> int DEBUG = 1; using namespace std; const int N = 100 * 1000 + 5; const long long INF = 1e17; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long n, k; long long a, b; long long x; long long MIN = +INF; long long MAX = -INF; long long dist(long long v, long long u) { if (v > u) swap(v, u); return min(u - v, x - (u - v)); } void check(long long s2) { long long d = dist(a, s2); long long L = d; long long cur = x / gcd(L, x); MAX = max(MAX, cur); MIN = min(MIN, cur); } int main() { cin >> n >> k; cin >> a >> b; x = n * k; for (long long e = 0; e < x; e += k) { check((e - b + x) % x); check((e + b) % x); } cout << MIN << << MAX << endl; return 0; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cluster_header_sync.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The sync pulse cluster header is instatiated as a hard macro.
// This model is for simulation only.
module cluster_header_sync (/*AUTOARG*/
// Outputs
dram_rx_sync_local, dram_tx_sync_local, jbus_rx_sync_local,
jbus_tx_sync_local, so,
// Inputs
dram_rx_sync_global, dram_tx_sync_global, jbus_rx_sync_global,
jbus_tx_sync_global, cmp_gclk, cmp_rclk, si, se
);
output dram_rx_sync_local;
output dram_tx_sync_local;
output jbus_rx_sync_local;
output jbus_tx_sync_local;
output so;
input dram_rx_sync_global;
input dram_tx_sync_global;
input jbus_rx_sync_global;
input jbus_tx_sync_global;
input cmp_gclk;
input cmp_rclk;
input si;
input se;
wire dram_rx_so;
wire dram_tx_so;
wire jbus_rx_so;
bw_clk_cclk_sync sync_wrapper (
.dram_rx_sync_local(dram_rx_sync_local),
.dram_tx_sync_local(dram_tx_sync_local),
.jbus_rx_sync_local(jbus_rx_sync_local),
.jbus_tx_sync_local(jbus_tx_sync_local),
.so(so),
.dram_rx_sync_global(dram_rx_sync_global),
.dram_tx_sync_global(dram_tx_sync_global),
.jbus_rx_sync_global(jbus_rx_sync_global),
.jbus_tx_sync_global(jbus_tx_sync_global),
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_rclk),
.si(si),
.se(se)
);
endmodule // cluster_header_sync
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_M_V
`define SKY130_FD_SC_LP__A32O_M_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_m (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_M_V
|
#include <bits/stdc++.h> using namespace std; long long a, b; vector<long long> A, B, C; int main() { scanf( %lld %lld , &a, &b); for (long long i = 1; i <= sqrt(a); i++) if (a % i == 0) A.push_back(i); for (long long i = 1; i <= sqrt(b); i++) if (b % i == 0) B.push_back(i); for (long long i = 1; i <= sqrt(a + b); i++) if ((a + b) % i == 0) C.push_back(i); long long ans; for (long long i : C) { for (long long j : A) { if (j <= i && a / j <= (a + b) / i) ans = 2 * i + (2 * (a + b) / i); } for (long long j : B) { if (j <= i && b / j <= (a + b) / i) ans = 2 * i + (2 * (a + b) / i); } } printf( %lld n , ans); }
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#include <bits/stdc++.h> const int MAX_N = 20; int n, k, t; int e[MAX_N + 1][MAX_N + 1]; int choosen[MAX_N + 1]; int mid; int cnt; void dfs(int x, int now_cost_sum) { if (x > n) { cnt++; return; } dfs(x + 1, now_cost_sum); for (int y = 1; y <= n && cnt < t; y++) { if (!choosen[y] && e[x][y] && now_cost_sum + e[x][y] <= mid) { choosen[y] = 1; dfs(x + 1, now_cost_sum + e[x][y]); choosen[y] = 0; } } } int main() { scanf( %d%d%d , &n, &k, &t); for (int i = 1; i <= k; i++) { int h, w, r; scanf( %d%d%d , &h, &w, &r); e[h][w] = r; } int low = 0, high = 1000 * n; while (low < high) { mid = (low + high) >> 1; cnt = 0; dfs(1, 0); if (cnt >= t) high = mid; else low = mid + 1; } printf( %d n , low); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, SLEEP_B, VPWR, KAGND );
and and0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_sleepb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int tree[(1 << 20)]; void add(int x, int val) { for (int i = x; i < (1 << 20); i = ((i) | (i + 1))) tree[i] += val; } int sum(int x) { int ans = 0; for (int i = x; i > 0; i = ((i) & (i - 1))) ans += tree[i - 1]; return ans; } int N, Q; map<int, int> idtohook; map<int, int> appearance; priority_queue<pair<int, int> > segments; map<int, int> nextL, nextR; vector<pair<int, pair<int, int> > > query; map<int, int> zip; vector<int> ans; int input(void) { int ans; scanf( %d , &ans); return ans; } void count_query(int low, int high) { query.push_back(make_pair(0, make_pair(low, high))); zip[low] = zip[high] = 0; } void enter_query(int id) { int hook = -1; while (1) { pair<int, int> p = segments.top(); segments.pop(); int L = p.second; int R = L + p.first; if (nextR[L] != R || nextL[R] != L) continue; hook = (L + R + 1) / 2; nextL[hook] = L; nextL[R] = hook; nextR[L] = hook; nextR[hook] = R; segments.push(make_pair(hook - L, L)); segments.push(make_pair(R - hook, hook)); break; } query.push_back(make_pair(1, make_pair(hook, 1))); idtohook[id] = hook; zip[hook] = 0; } void leave_query(int id) { int hook = idtohook[id]; int L = nextL[hook], R = nextR[hook]; nextL[hook] = nextR[hook] = -1; nextL[R] = L; nextR[L] = R; segments.push(make_pair(R - L, L)); query.push_back(make_pair(1, make_pair(hook, -1))); } void solve(void) { int i; i = 0; for (__typeof((zip).begin()) itr = (zip).begin(); itr != (zip).end(); itr++) { (itr->second) = i; i++; } for ((i) = 0; (i) < (int)(query.size()); (i)++) { int type = query[i].first; if (type == 0) { int low = zip[query[i].second.first]; int high = zip[query[i].second.second]; int tmp = sum(high + 1); if (low > 0) tmp -= sum(low); ans.push_back(tmp); } else { int pos = zip[query[i].second.first]; add(pos, query[i].second.second); } } } int main(void) { int i; N = input(); Q = input(); segments.push(make_pair(N + 1, 0)); nextR[0] = N + 1; nextL[N + 1] = 0; zip[0] = zip[N + 1] = 0; for ((i) = 0; (i) < (int)(Q); (i)++) { int x = input(); if (x == 0) { int low = input(), high = input(); count_query(low, high); } else { appearance[x]++; int tmp = appearance[x]; if (tmp % 2 == 1) { enter_query(x); } else { leave_query(x); } } } solve(); for ((i) = 0; (i) < (int)(ans.size()); (i)++) printf( %d n , ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; bool cmp(pair<long long int, long long int> a, pair<long long int, long long int> b) { return a.first < b.first; } bool check(int a) { int sum = 0; while (a > 0) { sum += (a % 10); a /= 10; } if (sum == 10) return true; return false; } bool prime[10005]; void seivertexe() { memset(prime, 1, sizeof(prime)); prime[0] = 0; prime[1] = 0; for (long long int i = 2; i <= 10000; i++) { if (prime[i] == 1) { for (long long int j = i * i; j <= 10000; j += i) prime[j] = 0; } } } template <typename T> std::string NumberToString(T Number) { std::ostringstream ss; ss << Number; return ss.str(); } bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long int power(long long int x, long long int y) { if (y == 0) return 1; else if (y % 2 == 0) return (power(x, y / 2) % 1000000007 * power(x, y / 2) % 1000000007) % 1000000007; else return (x % 1000000007 * (power(x, y / 2) % 1000000007 * power(x, y / 2) % 1000000007) % 1000000007) % 1000000007; } long long int factorial1(long long int n) { return (n == 1 || n == 0) ? 1 : (n % 1000000007 * factorial1(n - 1) % 1000000007) % 1000000007; } long long int fact(long long int n); long long int nCr(long long int n, long long int r) { return fact(n) % 1000000007 / ((fact(r) % 1000000007 * fact(n - r) % 1000000007)) % 1000000007; } long long int fact(long long int n) { long long int res = 1; for (int i = 2; i <= n; i++) res = (res * i) % 1000000007; return res % 1000000007; } void solve() {} int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int arr[n + 1]; map<long long int, long long int> mp1, mp2, mp3; for (long long int i = 1; i <= n; i++) { cin >> arr[i]; mp1[arr[i]]++; } long long int k = 0; long long int flag = 0; long long int arr1[2 * n + 2]; for (long long int i = 1; i <= n; i++) { long long int x = arr[i]; if (x > 2 * n) { flag = 1; cout << -1 << n ; break; } if (mp2[x] > 0) { flag = 1; cout << -1 << n ; break; } arr1[k++] = arr[i]; long long int y = arr[i] + 1; while (mp1[y] != 0 || mp2[y] != 0) { y++; } if (y > 2 * n) { flag = 1; cout << -1 << n ; break; } else { mp2[y]++; mp2[x]++; arr1[k++] = y; } } if (!flag) { for (long long int i = 0; i < 2 * n; i++) { cout << arr1[i] << ; } cout << n ; } } return 0; }
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////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mwram_gen.v: Generic mixed width RAM; not synthesizable with Altera's devices. //
// May not be synthesizable with other vendors; //
// Check your vendor's recommended HDL coding style. //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mwram_gen
#( parameter WR_DW = 1 , // write data width
parameter RD_DW = 32 , // read data width (a multiply of WR_DW)
parameter RD_D = 512, // read depth
parameter IZERO = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(RD_D*RD_DW/WR_DW)-1:0] wAddr , // write address
input [WR_DW -1:0] wData , // write data
input [`log2(RD_D) -1:0] rAddr , // read address
output reg [RD_DW -1:0] rData ); // read data
localparam WR_D = RD_D*RD_DW/WR_DW ; // write depth
localparam WR_AW = `log2(WR_D) ; // write address width
localparam RD_AW = `log2(RD_D) ; // read address width
localparam DSELW = `log2(RD_DW/WR_DW); // data selector width
reg [RD_DW-1:0] mem [0:RD_D-1]; // memory array
integer iA;
initial
if (IZERO)
for (iA=0; iA<WR_D; iA=iA+1)
mem[iA[WR_AW-1:DSELW]][iA[DSELW-1:0]*WR_DW +: WR_DW] <= {WR_DW{1'b0}};
always @ (posedge clk) begin
if (wEnb) mem[wAddr[WR_AW-1:DSELW]][wAddr[DSELW-1:0]*WR_DW +: WR_DW] <= wData;
rData <= mem[rAddr]; // q doesn't get d in this clock cycle
end
endmodule
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#include <bits/stdc++.h> using namespace std; long long a[150500]; int main() { ios_base::sync_with_stdio(false); int t; cin >> t; vector<long long> ans; for (int f = 0; f < t; f++) { long long n, m; cin >> n >> m; vector<long long> l; l.push_back(m % 10); for (long long i = m + m; l[0] != i % 10; i += m) l.push_back(i % 10); long long c = n / m / l.size() * accumulate(l.begin(), l.end(), 0); for (int i = 0; i < n / m % l.size(); i++) c += l[i]; ans.push_back(c); } for (auto i : ans) cout << i << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long int binpowmod(long long int a, long long int b, long long int m) { a %= m; long long int res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } unsigned long long modInverse(unsigned long long n, int p) { return binpowmod(n, p - 2, p); } int main() { long long int t, n, j, k, i, f, h, l, r, t1, t2, a, b, x, ans; cin >> t; while (t--) { cin >> n; string s; cin >> s; f = 0; x = -1; for (i = 0; i < n; ++i) { if (s[i] == 0 ) { f = 1; x = i + 1; break; } } if (f) { if (x <= n / 2) { cout << x << << n << << x + 1 << << n << n ; } else { cout << 1 << << x << << 1 << << x - 1 << n ; } } else cout << 1 << << n / 2 << << ((n + 1) / 2) + 1 << << n << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (k > n) { cout << -1 ; return 0; } if (n == 1) { cout << a ; return 0; } if (n > 1 && k == 1) { cout << -1 ; return 0; } string str; char c1 = a , c2 = b ; for (int i = 0; i < n; i++) { str += c1; if (i % 2 == 0) c1 = b ; else c1 = a ; } char ch = a + k - 1; int l = str.size() - 1; for (int i = 0; i < k - 2; i++) str[l--] = ch--; cout << str; return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long read() { long long num = 0, neg = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) neg = -1; c = getchar(); } while (isdigit(c)) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } return num * neg; } const long long mod = 998244353; long long n, a[100010], m, g[300010], f[300010], ans; inline long long qpow(long long x, long long k) { long long res = 1; while (k) { if (k & 1) res = res * x % mod; x = x * x % mod; k >>= 1; } return res; } int main() { n = read(); g[0] = n - 1; for (int i = 1; i <= n; i++) a[i] = read(), m += a[i]; for (int i = 1; i <= m; i++) g[i] = (m * (n - 1) % mod + (n - 1) * i % mod * g[i - 1] % mod) % mod * qpow(m - i, mod - 2) % mod; f[m] = g[m]; for (int i = m - 1; i >= 0; i--) f[i] = (f[i + 1] + g[i]) % mod; for (int i = 1; i <= n; i++) ans = (ans + f[a[i]]) % mod; ans = (ans - ((n - 1) * f[0] % mod) + mod) % mod; printf( %lld n , ans * qpow(n, mod - 2) % mod); return 0; }
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#include <bits/stdc++.h> using namespace std; string st[30] = { zero , one , two , three , four , five , six , seven , eight , nine , ten , eleven , twelve , thirteen , fourteen , fifteen , sixteen , seventeen , eighteen , nineteen , twenty , thirty , forty , fifty , sixty , seventy , eighty , ninety }; int main() { int n; while (cin >> n) { if (n <= 20) cout << st[n]; else if (n % 10 == 0) cout << st[20 + n / 10 - 2]; else if (n < 30) cout << st[20] + - + st[n % 10]; else if (n < 40) cout << st[21] + - + st[n % 10]; else if (n < 50) cout << st[22] + - + st[n % 10]; else if (n < 60) cout << st[23] + - + st[n % 10]; else cout << st[20 + n / 10 - 2] + - + st[n % 10]; cout << endl; } return 0; }
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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:14 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF8.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF8.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF8 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of uart
//
// ====================================================================
module sirv_uart_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_port_txd,
input io_port_rxd
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_uart u_sirv_uart(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_port_txd (io_port_txd ),
.io_port_rxd (io_port_rxd )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char A[1005][1005]; int P[1000005], MinX[1000005], MinY[1000005], MaxX[1000005], MaxY[1000005], M[1005][1005]; int xr[] = {-1, 1, 0, 0}; int xc[] = {0, 0, -1, 1}; int n, m; void dfs(int x, int y, int i) { if ((x < 0) || (x >= n) || (y < 0) || (y >= m) || (A[x][y] == . ) || (M[x][y])) return; M[x][y] = 1; MinX[i] = min(MinX[i], x); MinY[i] = min(MinY[i], y); MaxX[i] = max(MaxX[i], x); MaxY[i] = max(MaxY[i], y); for (int j = 0; j < 4; ++j) { dfs(x + xr[j], y + xc[j], i); } } bool check_convex_island(int len) { set<int> X, Y; for (int i = 0; i < n; ++i) X.insert(i); for (int i = 0; i < m; ++i) Y.insert(i); int x, i, j, ans = 1; for (x = 0; x < len; ++x) { int minx = MinX[x]; int miny = MinY[x]; int maxx = MaxX[x]; int maxy = MaxY[x]; for (i = minx; i <= maxx; ++i) { if (!X.count(i)) return false; X.erase(i); for (j = miny; A[i][j] == . ; ++j) ; for (; (j <= maxy) && (A[i][j] == # ); ++j) ; for (; (j <= maxy) && (A[i][j] == . ); ++j) ; ans &= (j > maxy); } for (j = miny; j <= maxy; ++j) { if (!Y.count(j)) return false; Y.erase(j); for (i = minx; A[i][j] == . ; ++i) ; for (; (i <= maxx) && (A[i][j] == # ); ++i) ; for (; (i <= maxx) && (A[i][j] == . ); ++i) ; ans &= (i > maxx); } } return ans; } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); int i, j, k, x, y, z, a, b; for (i = 0; i <= 1000000; ++i) MinX[i] = MinY[i] = 1000000007; cin >> n >> m; for (i = 0; i < n; ++i) cin >> A[i]; int ans = 1, len = 0; set<int> X, Y; for (i = 0; i < n; ++i) X.insert(i); for (i = 0; i < m; ++i) Y.insert(i); for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { if (A[i][j] == . ) continue; if (X.find(i) != X.end()) X.erase(i); if (Y.find(j) != Y.end()) Y.erase(j); if (!M[i][j]) dfs(i, j, len++); } } ans &= ((X.size() == 0 && Y.size() == 0) || (X.size() && Y.size())); ans &= check_convex_island(len); if (ans) cout << len << endl; else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct vect { int h, p1, p2; }; struct point { int p1, p2; }; int n, mod, nr, t; long long solf; int viz[200005]; point poz[200005]; map<int, vect> h; vector<int> aib[200005]; void precalc() { int i, j, x; for (i = 0; i < n; i++) if (!viz[i]) { x = 1; j = i; nr++; do { viz[j] = nr; poz[j].p1 = x; x++; j = (j + mod) % n; } while (!viz[j]); j = i; do { poz[j].p2 = poz[j].p1 + x - 1; j = (j + mod) % n; } while (!poz[j].p2); for (j = 0; j <= 2 * x; j++) aib[nr].push_back(0); } } void update(int ind, int poz, int val) { while (poz < aib[ind].size()) { aib[ind][poz] += val; poz += poz & -poz; } } int query(int ind, int poz) { int sol = 0; while (poz > 0) { sol += aib[ind][poz]; poz -= poz & -poz; } return sol; } int find(int x) { int st = poz[x].p1, dr = poz[x].p2, m, sol = dr - 1; int nr = st - query(viz[x], st); while (st <= dr) { m = (st + dr) >> 1; if (m - query(viz[x], m) > nr) { sol = m; dr = m - 1; } else st = m + 1; } solf += sol - poz[x].p1; sol = ((1LL * (sol - poz[x].p1) * mod) % n + x) % n; return sol; } int main() { scanf( %d %d %d n , &n, &mod, &t); precalc(); vect x; char ch; int id, hash, y, z; while (t--) { scanf( %c , &ch); if (ch == - ) { scanf( %d n , &id); x = h[id]; update(x.h, x.p1, -1); update(x.h, x.p2, -1); h[id] = (vect){0, 0, 0}; } else { scanf( %d %d n , &id, &hash); x.h = viz[hash]; x.p1 = poz[hash].p1; x.p2 = poz[hash].p2; y = query(x.h, x.p1); z = query(x.h, x.p1 - 1); if (y != z) hash = find(hash); x.h = viz[hash]; x.p1 = poz[hash].p1; x.p2 = poz[hash].p2; h[id] = x; update(x.h, x.p1, 1); update(x.h, x.p2, 1); } } printf( %I64d n , solf); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chrisky hu
//
// Create Date: 19:25:03 10/15/2015
// Design Name:
// Module Name: dht11_decode
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dht11_driver(
input clk1mhz,
input rst_n,
input start_signal,
inout dht11_dat,
output reg [7:0] output_temp,
output reg[7:0] output_humidity,
output reg [3:0]status
);
integer clock_count;
integer data_count;
integer global_count;
reg direction;
wire data_in;
reg data_out;
reg [39:0] data;
assign dht11_dat = direction ? 1'bz:data_out;
assign data_in = dht11_dat;
reg[3:0] state;
always@(posedge clk1mhz, negedge rst_n)
begin
if (~rst_n)
begin
state<=4'b0;
status <=4'b0;
data<=40'b0;
output_temp <= 8'b0;
output_humidity <=8'b0;
global_count<=0;
clock_count <=0;
data_count<=0;
end
else
begin
status<=state;
clock_count<=clock_count+1;
case( state)
4'b0:
begin
clock_count<=0;
data_count<=0;
global_count<=0;
direction <= 1'b0;
data_out<=1'b1;
if(start_signal==1'b0)
state <=4'd1;
end
4'b1:
begin
if(start_signal==1'b1)
begin
state<=4'd2;
clock_count<=0;
end
end
4'd2:
begin
direction<=1'd0;
data_out<=1'd0;
if(clock_count==30000)
begin
state <=4'd3;
clock_count<=0;
end
end
4'd3:
begin
data_out<=1'd1;
if (clock_count == 20)
begin
direction<=1'b1;
data_out<=1'bz;
state <=4'd4;
end
end
4'd4:
begin
if(data_in == 1'b0)
state <=4'd5;
end
4'd5:
begin
if(data_in == 1'b1)
state <=4'd6;
end
4'd6:
begin
if(data_in == 1'b0)
state <=4'd7;
end
4'd7:
begin
if(data_in == 1'b1)
begin
state<=4'd8;
clock_count<=0;
end
end
4'd8:
begin
global_count<=global_count+1;
output_temp[0]<=data[23];
output_temp[1]<=data[22];
output_temp[2]<=data[21];
output_temp[3]<=data[20];
output_temp[4]<=data[19];
output_temp[5]<=data[18];
output_temp[6]<=data[17];
output_temp[7]<=data[16];
output_humidity[0]<=data[7];
output_humidity[1]<=data[6];
output_humidity[2]<=data[5];
output_humidity[3]<=data[4];
output_humidity[4]<=data[3];
output_humidity[5]<=data[2];
output_humidity[6]<=data[1];
output_humidity[7]<=data[0];
if (global_count>10000) //stuck , reset
begin
state<=4'd0;
end
else
begin
if(data_in == 1'b0)
begin
data_count <=data_count+1;
if(clock_count>40)
begin
data[data_count] <= 1'b1;
end
else
begin
data[data_count] <= 1'b0;
end
if(data_count == 39)
begin
state<=4'd9;
end
else
begin
state<=4'd7;
end
clock_count <=0;
end
end
end
4'd9:
begin
if(start_signal==1'b1)
state <=4'd10;
end
4'd10:
begin
if(start_signal==1'b0)
state <=4'd0;
end
endcase
end
end
endmodule
|
Require Import Arith.
Require Import List.
Require Import Setoid.
Require Import Program.
Set Transparent Obligations.
(** {1 Type Algebra} *)
(** To simplify the technicalities, we focus on first-order types
whose syntax is:
τ := ι ∣ ι → τ
They correspond to arities, i.e. natural numbers. Thus, we can
denote them by the following function that computes Aⁿ → A. *)
Fixpoint type_of_arity (A : Type) n :=
match n with
| O => A
| S n => A -> type_of_arity A n
end.
(** Once a type A is inhabited, it is easy to write find an inhabitant
for any type Aⁿ → A. *)
Fixpoint default_value {A} (default : A) k : type_of_arity A k :=
match k with
| O => default
| S n => fun (x : A) => default_value default n
end.
(** {1 Signatures} *)
(** A term constructor is assigned an arity n and an
interpretation as coq term of type Aⁿ → A. *)
Definition constructor_signature A :=
sigT (A := nat) (fun n => type_of_arity A n).
Definition mk_constructor {A} k (x : type_of_arity A k)
: constructor_signature A :=
existT (fun n => type_of_arity A n) k x.
(** A constructor identifier is simply a natural number. *)
Definition constructor := nat.
(** A signature over A associates an arity and an interpretation
to a list of constructors. *)
Definition signature A := list (constructor_signature A).
(** We implement a signature lookup as a total function
producing [None] in case of failure. *)
Definition arity_descriptor := option nat.
Definition arity {A} (sgn : signature A) f : arity_descriptor :=
match List.nth_error sgn f with
| None => None
| Some (existT _ k _) => Some k
end.
(** [Find] is a predicate over signatures, arities and constructor
interpretations. It denotes the property of an arity and an
interpretation to be in a signature. *)
Class Find {A : Type}
(sgn : signature A) (k : nat) (x : type_of_arity A k) := {
(** The property is witnessed by the index of the pair in the
signature. *)
index : nat;
(** These equalities are useful to specialize total functions to
the case where the arity and the constructor are in the
signature. *)
found : nth_error sgn index = Some (mk_constructor k x);
arity_of_index : arity sgn index = Some k
}.
(** [FindHead] is an instance of the predicate [Find] where the
pair is at the beginning of the signature. *)
Program Instance FindHead {A : Type}
(k : nat) (x : type_of_arity A k) (l : signature A) :
(Find ((mk_constructor k x) :: l) k x) := {
index := O
}.
(** [FindTail] is an instance of the predicate [Find where the
pair is the tail of the signature. *)
Program Instance FindTail {A : Type}
(k : nat) (x : (type_of_arity A k))
(l : nat) (y : (type_of_arity A l))
(sgn : signature A)
(Tail : Find sgn k x)
: (Find ((mk_constructor l y) :: sgn) k x) := {
index := (S index);
found := found
}.
Next Obligation.
unfold arity. simpl. rewrite <- arity_of_index. unfold arity. reflexivity.
Defined.
(** As usual with index types, we need some coercion functions. This
one is meant to convert a value of type Aⁿ → A into a value of
type Aⁿ' → A if n = n'. *)
Lemma coerce_type_of_arity: forall A k k', k = k' ->
type_of_arity A k -> type_of_arity A k'.
Proof.
intros A k k' Hkk' H. now rewrite <- Hkk'.
Defined.
(** Apply an interpretation of arity k to a list of As. If the list of
As is not of length k, then a default value is returned. As for
[arity], we artificially define a total function to avoid the use
of too complex dependent types, which may be unpractical for "a
posteriori" reasoning. *)
Fixpoint apply
{A} (default : A)
(k : nat) (f : type_of_arity A k)
(ts : list A)
: A :=
match ts with
| nil =>
(match k return (type_of_arity A k -> A) with
| O => fun x => x
| _ => fun x => default
end f)
| cons x xs =>
(match k return (type_of_arity A k -> A) with
| O => fun _ => default
| S k => fun (g : A -> type_of_arity A k) => apply default k (g x) xs
end) f
end.
Eval compute in (apply 0 2 (fun x y => x + y) (4 :: 5 :: nil)).
(** Finally, we are ready to define the interpretation
of a constructor [f] of arity [k] in a signature [sgn]. *)
Definition constructor_interpretation {A}
(default : A)
(sgn : signature A) (f : constructor) (k : nat)
: type_of_arity A k
:=
match List.nth_error sgn f with
| None => default_value default k
| Some (existT _ k' x) =>
match eq_nat_dec k' k with
| left H => coerce_type_of_arity A k' k H x
| _ => default_value default k
end
end.
(** Apply a constructor [f] to a list of arguments by applying them to the
the interpretation of [f] found in a given signature. *)
Definition apply_constructor {A}
(default : A)
(sgn : signature A)
(f : constructor)
(ts : list A)
: A :=
match arity sgn f with
| None => default
| Some k => apply default k (constructor_interpretation default sgn f k) ts
end.
(** {1 First order terms} *)
(** First order term are built from constructors applied to
list of terms. This definition does not enforce the
well-formedness of terms: a constructor may be applied
to the wrong number of arguments. Yet, as we will reify
well-typed Coq terms, this property is guaranteed
at the meta-level. *)
Inductive term : Type :=
| App : forall (f : constructor) (ts : list term),
term.
(** A term is interpreted recursively using constructor interpretations. *)
Fixpoint term_interpretation {A} (default : A) (sgn : signature A) (t : term)
: A :=
match t with
| App f ts =>
let xs := List.map (term_interpretation default sgn) ts in
apply_constructor default sgn f xs
end.
Example sgn1 : signature nat := [
mk_constructor O 41;
mk_constructor 1 S;
mk_constructor 2 plus
].
Program Example t1 := App 1 (cons (App 0 nil) nil).
Compute (term_interpretation 0 sgn1 t1).
(** {1 Reification of first order terms} *)
(** A predicate stating that there exists a reification of [T]
of type [A] as a first order term in the signature [sgn]. *)
Class ReifyTerm {A} (default : A) (sgn : signature A) (T : A) := {
term_reification : term;
term_reification_correct : term_interpretation default sgn term_reification = T
}.
(** To define this predicate, we states an (incomplete) set of rules to
syntactically catch Coq's terms of the form [F T₁ T₂ … T_n] for all
n from 0 to a big enough constant (here we chose 3). *)
(** The proof of correctness for each of these
rules is always the same: *)
Ltac sound_reification_rule :=
unfold apply_constructor; rewrite arity_of_index;
unfold constructor_interpretation;
rewrite found; simpl; unfold coerce_type_of_arity;
(repeat rewrite term_reification_correct); auto.
(** A rule for this predicate: a constant*)
Program Instance ReifyConstant {A} (default : A) (sgn : signature A)
(T : A) (S : Find sgn 0 T) : ReifyTerm default sgn T := {
term_reification := App (index (k := 0) (x := T)) nil
}.
Next Obligation. sound_reification_rule. Defined.
Program Instance ReifyApp1 {A} (default : A) (sgn : signature A)
(F : A -> A) (FFind : Find sgn 1 F)
(T : A) (RT : ReifyTerm default sgn T)
: ReifyTerm default sgn (F T) := {
term_reification := App (index (k := 1) (x := F)) [ term_reification ]
}.
Next Obligation. sound_reification_rule. Defined.
Program Instance ReifyApp2 {A} (default : A) (sgn : signature A)
(F : type_of_arity A 2) (FFind : Find sgn 2 F)
(T1 : A) (RT1 : ReifyTerm default sgn T1)
(T2 : A) (RT2 : ReifyTerm default sgn T2)
: ReifyTerm default sgn (F T1 T2) := {
term_reification := App (index (k := 2) (x := F))
[ term_reification (T := T1);
term_reification (T := T2) ]
}.
Next Obligation. sound_reification_rule. Defined.
Program Instance ReifyApp3 {A} (default : A) (sgn : signature A)
(F : type_of_arity A 3) (FFind : Find sgn 3 F)
(T1 : A) (RT1 : ReifyTerm default sgn T1)
(T2 : A) (RT2 : ReifyTerm default sgn T2)
(T3 : A) (RT3 : ReifyTerm default sgn T3)
: ReifyTerm default sgn (F T1 T2 T3) := {
term_reification := App (index (k := 3) (x := F))
[ term_reification (T := T1);
term_reification (T := T2);
term_reification (T := T3) ]
}.
Next Obligation. sound_reification_rule. Defined.
Compute (term_reification (sgn := sgn1) (default := 0)
(T := plus 41 (S (S (S 41))))).
(** {1 Reification of congruence closure problem.} *)
(** An equality is a pair of two first-order terms. *)
Definition equality := (term * term)%type.
(** We interpret equalities using Coq's equality. *)
Definition equality_interpretation {A} (default : A) sgn (e : equality) :=
let (x, y) := e in
term_interpretation default sgn x = term_interpretation default sgn y.
(** A congruence closure problem is composed of an equality
to prove and a list of equality to be used to achieve
that goal. *)
Record problem := {
hypothesis : list equality;
goal : equality
}.
(** The interpretation of hypotheses in a signature is the conjunction
of the interpretation of the equalities. *)
Fixpoint conjunction_interpretation {A} (default : A) (sgn : signature A)
(cs : list equality) :=
match cs with
| nil => True
| e :: cs =>
equality_interpretation default sgn e
/\ conjunction_interpretation default sgn cs
end.
(** A problem is interpreted as an implication. *)
Definition problem_interpretation {A} (default : A) (sgn : signature A)
(p : problem) :=
conjunction_interpretation default sgn (hypothesis p) ->
equality_interpretation default sgn (goal p).
(** [assume p e] is [p] with an extra hypothesis [e]. *)
Definition assume (p : problem) (e : equality) : problem :=
{|
hypothesis := e :: (hypothesis p);
goal := goal p
|}.
(** A predicate stating that [P] has a reification in a signature [sgn]. *)
Class ProblemReification {A} (default : A) (sgn : signature A) (P : Prop) := {
problem_reification : problem;
problem_reification_correct :
problem_interpretation default sgn problem_reification <-> P
}.
(** An equality is a goal for a problem with no hypothesis. *)
Program Instance problem_base {A} (default : A) (sgn : signature A)
(x y : A)
(xr : ReifyTerm default sgn x)
(yr : ReifyTerm default sgn y)
: ProblemReification default sgn (x = y) := {
problem_reification := {|
hypothesis := nil;
goal := (term_reification (T := x), (term_reification (T := y)))
|}
}.
Next Obligation.
unfold problem_interpretation. simpl.
repeat (rewrite term_reification_correct).
tauto.
Defined.
(** An implication of the form [x = y ⇒ P] can be recursively reified. *)
Program Instance problem_hyp {A} (default : A) (sgn : signature A)
(P : Prop)
(x y : A)
(xr : ReifyTerm default sgn x)
(yr : ReifyTerm default sgn y)
(RP : ProblemReification default sgn P)
:
ProblemReification default sgn (x = y -> P)
:= {
problem_reification :=
assume problem_reification
(term_reification (T := x), (term_reification (T := y)))
}.
Next Obligation.
unfold problem_interpretation. simpl.
repeat (rewrite term_reification_correct).
generalize problem_reification_correct.
intuition.
Defined.
Implicit Arguments problem_reification [A sgn ProblemReification].
Print Implicit problem_reification.
Example p1 :=
(problem_reification (A := nat) (sgn := sgn1) 0
(41 = 41 -> S 41 = S 41)).
Compute p1.
Compute (problem_interpretation O sgn1 p1).
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#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int ans = a; if (b < 0) { int t = abs(b); while (t--) { --a; if (a == 0) a = n; } } else { while (b--) { ++a; if (a == n + 1) a = 1; } } cout << a << endl; }
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#include <bits/stdc++.h> using namespace std; int arr[1000000]; int main() { int n, x, counter = 0; cin >> n >> x; for (int i = 0; i < n; i++) scanf( %d , &arr[i]); sort(arr, arr + n); while (arr[((n + 1) / 2 - 1)] != x) { arr[n++] = x; sort(arr, arr + n); counter++; } cout << counter; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& i : v) os << i << ; return os; } template <typename T, typename U> istream& operator>>(istream& is, pair<T, U>& p) { is >> p.first >> p.second; return is; } template <typename T, typename U> ostream& operator<<(ostream& os, pair<T, U>& p) { os << p.first << << p.second; return os; } int main() { long long b; cin >> b; vector<pair<long long, long long>> v; long long p = 2; while (p * p <= b) { if (b % p == 0) { v.emplace_back(p, 0); while (b % p == 0) { b /= p; v.back().second++; } } ++p; } if (b != 1) v.emplace_back(b, 1); long long c = 1; for (auto p : v) { c *= p.second + 1; } cout << c << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T1> void deb(T1 e) { cout << e << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } long long sqr(long long n) { return n * n; } double LOG(long long a, long long b) { return (log(a) / log(b)); } long long GCD(long long a, long long b) { if (a < 0) return GCD(-a, b); if (b < 0) return GCD(a, -b); return (!b) ? a : GCD(b, a % b); } long long LCM(long long a, long long b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return (a * (b / GCD(a, b))); } long long BigMod(long long B, long long P, long long M) { if (!P) return 1; if (!(P % 2)) return sqr(BigMod(B, P / 2, M)) % M; return (B % M) * (BigMod(B, P - 1, M)) % M; } int par[205]; int dp[105][105][105]; string s1, s2, vir; string ans; int rec(int x, int y, int z) { if (z == (int)vir.size()) return -(1 << 30); if (x == (int)s1.size() || y == (int)s2.size()) return 0; int &ret = dp[x][y][z]; if (ret != -1) return ret; ret = rec(x + 1, y, z); ret = max(ret, rec(x, y + 1, z)); if (s1[x] == s2[y]) { int k = z; while (k > 0 && s1[x] != vir[k]) k = par[k - 1]; if (s1[x] == vir[k]) k++; ret = max(ret, rec(x + 1, y + 1, k) + 1); } return ret; } void prec(int x, int y, int z) { if (z == (int)vir.size()) return; if (x == (int)s1.size() || y == (int)s2.size()) return; int &ret = dp[x][y][z]; if (ret == rec(x + 1, y, z)) return prec(x + 1, y, z); if (ret == rec(x, y + 1, z)) return prec(x, y + 1, z); if (s1[x] == s2[y]) { int k = z; while (k > 0 && s1[x] != vir[k]) k = par[k - 1]; if (s1[x] == vir[k]) k++; if (ret == rec(x + 1, y + 1, k) + 1) { ans += s1[x]; return prec(x + 1, y + 1, k); } } return; } int main(void) { cin >> s1 >> s2 >> vir; memset(par, 0, sizeof(par)); int k = 0; string cur = vir; for (int i = 1; i < (int)cur.size(); i++) { while (k > 0 && cur[i] != cur[k]) k = par[k - 1]; if (cur[i] == cur[k]) k++; par[i] = k; } memset(dp, -1, sizeof(dp)); int res = rec(0, 0, 0); if (!res) { deb(res); return 0; } ans = ; prec(0, 0, 0); deb(ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long double pi = 3.14159265358979323; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); vector<int> a(100000, 0); vector<int> ans; for (int i = 0; i < (int)n + m; ++i) { if (a[i] < k) { for (int j = 0; j < (int)k - a[i]; ++j) ans.push_back(i); int t = a[i]; for (int j = i; j < n + i; ++j) a[j] += k - t; } else if (a[i + 1] == 0) { for (int j = i; j < n + i; ++j) a[j]++; ans.push_back(i); } } printf( %d n , ans.size()); for (int i = 0; i < (int)ans.size(); ++i) { printf( %d , ans[i] + 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } const int N = 1e3 + 5; int f[N][N]; struct node { long long x, y; } a[N], b[N]; bool cmp(node x, node y) { return x.y < y.y; } long long area(node a, node b, node c) { return a.x * b.y - a.y * b.x + b.x * c.y - b.y * c.x + c.x * a.y - c.y * a.x; } bool toleft(node a, node b, node c) { if (c.y <= a.y || c.y > b.y) return 0; return area(a, b, c) > 0; } int n, m; int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) scanf( %lld%lld , &a[i].x, &a[i].y); for (int i = 1; i <= m; ++i) scanf( %lld%lld , &b[i].x, &b[i].y); sort(a + 1, a + n + 1, cmp); int ans = 0; for (int i = 1; i < n; ++i) for (int j = i + 1; j <= n; ++j) for (int k = 1; k <= m; ++k) if (toleft(a[i], a[j], b[k])) f[i][j]++; for (int i = 1; i < n; ++i) for (int j = i + 1; j < n; ++j) for (int k = j + 1; k <= n; ++k) if (f[i][j] + f[j][k] == f[i][k]) ans++; printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, x = 0, y = 0, x0 = 0, y0 = 0, k = 1, ans = 1; string s; cin >> n >> s; for (int i = 0; i < n; i++) { if (s[i] == L ) x--; if (s[i] == R ) x++; if (s[i] == D ) y--; if (s[i] == U ) y++; if (abs(x - x0) + abs(y - y0) < k) { ans++; k = 1; x0 = x; if (s[i] == L ) x0++; if (s[i] == R ) x0--; y0 = y; if (s[i] == D ) y0++; if (s[i] == U ) y0--; } else k++; } printf( %d , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> X; map<long long, pair<int, long long> > M; pair<int, long long> go(long long x) { if (x <= 1) return {x, x}; if (M.find(x) != M.end()) return M[x]; int i = upper_bound(X.begin(), X.end(), x) - X.begin() - 1; int p1, p2; long long q1, q2; pair<int, long long> P1; P1 = go(x - X[i]); p1 = P1.first; q1 = P1.second; P1 = go(X[i] - 1); p2 = P1.first; q2 = P1.second; return M[x] = max(make_pair(p1 + 1, q1 + X[i]), {p2, q2}); } int main() { for (int i = 0; i <= 1e5 + 7; ++i) X.push_back(1LL * i * i * i); long long x; cin >> x; pair<int, long long> Ans; Ans = go(x); cout << Ans.first << << Ans.second << n ; }
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#include <bits/stdc++.h> using namespace std; int n, a, b, d[500], s; int main() { scanf( %d , &n); for (int i = 1; i <= 2 * n; i++) scanf( %d , &d[i]); for (int i = 1; i <= 2 * n; i++) for (int j = 1; j <= 2 * n; j++) if (d[i] == d[i + (2 * j - 1)]) s++; printf( %d , s); scanf( ); }
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// DEFINES
`define BITS 32 // Bit width of the operands
module fir(clock,
reset,
x,
k0,
k1,
k2,
k3,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] x;
input [`BITS-1:0] k0;
input [`BITS-1:0] k1;
input [`BITS-1:0] k2;
input [`BITS-1:0] k3;
output [`BITS-1:0] out;
wire [`BITS-1:0] x0k0;
wire [`BITS-1:0] x1k1;
wire [`BITS-1:0] x2k2;
wire [`BITS-1:0] x3k3;
wire [`BITS-1:0] add0;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] add2;
wire [`BITS-1:0] add3;
reg [`BITS-1:0] x_reg1;
reg [`BITS-1:0] x_reg2;
reg [`BITS-1:0] x_reg3;
reg [`BITS-1:0] x_reg4;
reg [`BITS-1:0] x_reg5;
reg [`BITS-1:0] x_reg6;
reg [`BITS-1:0] x_reg7;
reg [`BITS-1:0] x_reg8;
reg [`BITS-1:0] x_reg9;
reg [`BITS-1:0] x_reg10;
reg [`BITS-1:0] x_reg11;
reg [`BITS-1:0] x_reg12;
reg [`BITS-1:0] x_reg13;
reg [`BITS-1:0] x_reg14;
reg [`BITS-1:0] x_reg15;
reg [`BITS-1:0] x_reg16;
reg [`BITS-1:0] x_reg17;
reg [`BITS-1:0] x_reg18;
wire [`BITS-1:0] out;
wire [`BITS-1:0] out_temp;
reg [`BITS-1:0] out_reg;
assign out= out_reg;
// ASSIGN STATEMENTS
//assign x0k0 = k0 * x;
wire [7:0] x0k0_control;
fpu_mul x0k0_mul
(
.clk(clock),
.opa(k0),
.opb(x),
.out(x0k0),
.control(x0k0_control)
);
//assign x1k1 = k1 * x_reg1;
wire [7:0] x1k1_control;
fpu_mul x1k1_mul
(
.clk(clock),
.opa(k1),
.opb(x_reg6),
.out(x1k1),
.control(x1k1_control)
);
//assign x2k2 = k2 * x_reg2;
wire [7:0] x2k2_control;
fpu_mul x2k2_mul
(
.clk(clock),
.opa(k2),
.opb(x_reg12),
.out(x2k2),
.control(x2k2_control)
);
//assign x3k3 = k3 * x_reg3;
wire [7:0] x3k3_control;
fpu_mul x3k3_mul
(
.clk(clock),
.opa(k3),
.opb(x_reg18),
.out(x3k3),
.control(x3k3_control)
);
//assign add0 = x0k0 + x1k1;
wire [7:0] add0_control;
fpu_add add0_add
(
.clk(clock),
.opa(x0k0),
.opb(x1k1),
.out(add0),
.control(add0_control)
);
//assign add1 = add0 + x2k2;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(add0),
.opb(x2k2),
.out(add1),
.control(add1_control)
);
//assign out = add1 + x3k3;
wire [7:0] out_temp_control;
fpu_add out_temp_add
(
.clk(clock),
.opa(add1),
.opb(x3k3),
.out(out_temp),
.control(out_temp_control)
);
always @(posedge clock)
begin
out_reg <= out_temp;
x_reg1 <= x;
x_reg2 <= x_reg1;
x_reg3 <= x_reg2;
x_reg4 <= x_reg3;
x_reg5 <= x_reg4;
x_reg6 <= x_reg5;
x_reg7 <= x_reg6;
x_reg8 <= x_reg7;
x_reg9 <= x_reg8;
x_reg10 <= x_reg9;
x_reg11 <= x_reg10;
x_reg12 <= x_reg11;
x_reg13 <= x_reg12;
x_reg14 <= x_reg13;
x_reg15 <= x_reg14;
x_reg16 <= x_reg15;
x_reg17 <= x_reg16;
x_reg18 <= x_reg17;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; using LD = long double; const int MX = 1 << 18 | 3; int N, a[MX], Q; LL sum; int main() { ios::sync_with_stdio(0); cout << fixed << setprecision(10); cin >> N >> Q; for (int i = 0; i < (1 << N); i++) cin >> a[i], sum += a[i]; cout << (LD)sum / (1 << N) << n ; while (Q--) { int u, x; cin >> u >> x; sum = sum - a[u] + x; a[u] = x; cout << (LD)sum / (1 << N) << n ; } return 0; }
|
`timescale 1ns/1ns
// Fast Multisource Pulse Registration System
// Module:
// Flexible, 3-fifo multidirectional FX2 USB-2 interface
// (c) Sergey V. Polyakov 2006-forever
module fx2_bidir(
fx2_clk, fx2_fd, fx2_slrd, fx2_slwr, fx2_flags,
fx2_sloe, fx2_wu2, fx2_fifoadr, fx2_pktend,
sample, sample_rdy, sample_ack,
cmd, cmd_wr,
reply, reply_rdy, reply_ack, reply_end
);
/*
* This is the state machine to handle interactions between the FX2 USB
* controller and the timetagger. We must handle three streams of data,
*
* fifo8: commands from the host to the device
* fifo2: command replies from the device to the host
* fifo6: data from the device.
*
*/
//************************************************************************
//FPGA interface
//************************************************************************
input [7:0] sample;
input sample_rdy;
output sample_ack;
output [7:0] cmd;
output cmd_wr;
input [7:0] reply;
input reply_rdy;
output reply_ack;
input reply_end;
//************************************************************************
//FX2 interface
//************************************************************************
input fx2_clk;
output fx2_wu2; // WU2 (USB wakeup, always high)
inout [7:0] fx2_fd;
output [1:0] fx2_fifoadr; // FIFO address
input [2:0] fx2_flags; // 0: FIFO2 data available, 1: FIFO6 not full, 2: FIFO8 not full
output fx2_slrd, fx2_slwr;
output fx2_sloe; // FIFO data bus output enable
output fx2_pktend; // Packet end
// Alias "FX2" ports as "FIFO" ports to give them more meaningful names.
// FX2 USB signals are active low, take care of them now
// Note: You probably don't need to change anything in this section
wire fifo_clk = fx2_clk;
wire fifo2_empty = ~fx2_flags[0]; wire fifo2_data_available = ~fifo2_empty;
wire fifo6_full = ~fx2_flags[1]; wire fifo6_ready_to_accept_data = ~fifo6_full;
wire fifo8_full = ~fx2_flags[2]; wire fifo8_ready_to_accept_data = ~fifo8_full;
assign fx2_wu2 = 1'b1;
// Wires associated with bidirectional protocol
wire sample_ack;
wire [7:0] fifo_dataout;
wire fifo_dataout_oe;
wire fifo_wr;
// Wires associated with packet length monitoring and reporting via FIFO8
wire request_length;
wire [7:0] length_byte;
// FX2 inputs
wire fifo_rd, fifo_pktend, fifo_datain_oe;
wire fx2_slrd = ~fifo_rd;
wire fx2_slwr = ~fifo_wr;
assign fx2_sloe = ~fifo_datain_oe;
assign fx2_pktend = ~fifo_pktend;
wire [1:0] fifo_fifoadr;
assign fx2_fifoadr = fifo_fifoadr;
// FX2 bidirectional data bus
wire [7:0] fifo_datain = fx2_fd;
assign fx2_fd = fifo_dataout_oe ? fifo_dataout : 8'hZZ;
/*
* Here we wait until we receive some data from either PC or FPGA (default is FPGA).
* If PC speaks, send an end_packet to its fifo to let it grab the collected data.
* Whenever FPGA is ready to transmit data, and the FIFO is not busy talking to PC,
* accept FPGA's data and signal this back to FPGA
*/
/*
* state[3:2]: FIFOADR
* 00: fifo2: Command from PC
* 10: fifo6: Data
* 11: fifo8: Command reply
*/
reg [3:0] state;
always @(posedge fifo_clk)
case(state)
// Idle
4'b1001: // Idle state
if (fifo2_data_available) // There is data to be recieved
state <= 4'b0001;
else if (reply_rdy && fifo8_ready_to_accept_data) // Send command reply if one is waiting
state <= 4'b1110;
else if (sample_rdy && fifo6_ready_to_accept_data) // If fifo6 gets emptied, send more
state <= 4'b1011;
// Data transmit path
4'b1011: // Listen/Transmit state
if (reply_rdy && fifo8_ready_to_accept_data) // If we are trying to send something, handle it next
state <= 4'b1110;
else if (fifo2_data_available) // If host is sending something, handle it first
state <= 4'b0001;
else if (fifo6_full) // fifo is full, go to idle
state <= 4'b1001;
// Command receive path:
4'b0001: state <= 4'b0011; // Wait for turnaround to read from PC
4'b0011: if (fifo2_empty) state <= 4'b1001; // Receive data
// Command reply path:
4'b1110: if (reply_end) state <= 4'b1111; // Transmit data
4'b1111: state <= 4'b1000; // Transmit end-of-packet
4'b1000: // Wait for turnaround to transmit an end-of-packet
begin
#2 state <= 4'b1010;
end
default: state <= 4'b1011;
endcase
assign fifo_fifoadr = state[3:2];
// Transmit from PC to FPGA
assign fifo_rd = (state==4'b0011);
assign cmd[7:0] = (state==4'b0011) ? fifo_datain[7:0] : 8'b0;
assign cmd_wr = (state==4'b0011);
assign fifo_datain_oe = (state[3:2] == 2'b00);
// Transmit from FPGA to PC
wire can_xmit_sample = (state==4'b1011) && sample_rdy && fifo2_empty && fifo6_ready_to_accept_data;
assign sample_ack = can_xmit_sample;
assign fifo_dataout = (state==4'b1011) ? sample :
(state==4'b1110) ? reply : 8'bX;
assign fifo_wr = can_xmit_sample || (state==4'b1110);
assign fifo_dataout_oe = can_xmit_sample || (state==4'b1110);
assign fifo_pktend = (state==4'b1111);
assign reply_ack = (state==4'b1110);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_TB_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_TB_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlymetal6s6s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_TB_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; string a(n, 0 ); string b(n, 0 ); int flag = 0; for (int i = 0; i < n; i++) { if (s[i] == 2 ) { if (flag == 0) { a[i] = 1 ; b[i] = 1 ; } else { a[i] = 0 ; b[i] = 2 ; } } if (s[i] == 1 ) { if (flag == 0) { a[i] = 1 ; flag = 1; } else { b[i] = 1 ; } } } cout << a << n ; cout << b << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; char s[100005]; char b[100005]; int main() { cin >> s; int cnt = 0; char x = a ; for (int i = strlen(s); i >= 0; --i) { if (s[i] >= x) { x = s[i]; b[cnt++] = x; } } while (cnt--) { printf( %c , b[cnt]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int cnt[1000000 + 10]; int a[1000000 + 10]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] <= m) { cnt[a[i]]++; } } for (int i = m; i >= 1; i--) { for (int j = i; (j += i) <= m;) { cnt[j] += cnt[i]; } } int i, j; for (i = j = 1; i <= m; i++) { if (cnt[i] > cnt[j]) { j = i; } } cout << j << << cnt[j] << endl; for (i = 0; i < n; i++) { if (j % a[i] == 0) { cout << i + 1 << ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
/**
* udp_dff$PE_pp$PG: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pe_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg DATA_EN;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DATA_EN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DATA_EN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DATA_EN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DATA_EN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DATA_EN = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DATA_EN = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PE_pp$PG dut (.D(D), .DATA_EN(DATA_EN), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { string p; getline(cin, p); bool f = 0; for (int i = 0; i < p.size(); i++) { if (p[i] >= a && p[i] <= z ) { if (p[i] == a || p[i] == i || p[i] == u || p[i] == e || p[i] == o || p[i] == y ) f = 1; else f = 0; } if (p[i] >= A && p[i] <= Z ) { if (p[i] == A || p[i] == I || p[i] == U || p[i] == E || p[i] == O || p[i] == Y ) f = 1; else f = 0; } } if (f) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_4_V
`define SKY130_FD_SC_HDLL__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } set<int> vals; set<int> cur; for (int i = 0; i < n; ++i) { { set<int> cur2; transform(cur.begin(), cur.end(), inserter(cur2, cur2.end()), [&a, i](int x) { return x | a[i]; }); cur = cur2; } cur.insert(a[i]); copy(cur.begin(), cur.end(), inserter(vals, vals.begin())); } cout << vals.size() << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; double dp[15][15]; int n, t, i, j, ans = 0; void work() { double t; dp[1][1] += 1; for (i = 1; i <= n; i++) { for (j = 1; j <= i; j++) { if (dp[i][j] > 1) { t = dp[i][j] - 1; dp[i][j] = 1; dp[i + 1][j] += t / 2; dp[i + 1][j + 1] += t / 2; } } } } int main() { scanf( %d%d , &n, &t); while (t--) { work(); } for (i = 1; i <= n; i++) { for (j = 1; j <= i; j++) { if (abs(1 - dp[i][j]) < 0.0000001) { ans++; } } } cout << ans << endl; }
|
`timescale 1ns / 1ps
module lights(
input clk,
input rx,
output tx,
output [2*12-1:0] leds
);
wire clk_uart;
uart_clk uart_clk_i(.CLKIN_IN(clk),
.CLKFX_OUT(clk_uart),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT());
wire rx_i;
reg [4:0] rx_sync = 0;
always @ (posedge clk_uart) rx_sync <= {rx_sync[3:0], rx};
assign rx_i = rx_sync[4];
// ~30 fps animation at 25 Mhz clk means need 21 bit advance counter using
// top bit as program advance clock. This gives ~ 11 Hz.
reg [26:0] clk_div; initial clk_div = 0;
always @ (posedge clk_uart) clk_div <= clk_div + 1;
wire clk_step = clk_div[17];
reg clk_step_l; initial clk_step_l = 0;
always @ (posedge clk_uart) clk_step_l <= clk_step;
reg step; initial step = 0;
always @ (posedge clk_uart)
if (clk_step && ~clk_step_l) step <= 1;
else step <= 0;
wire [7:0] pwm_counter = clk_div[13:6]; // 191 Hz
wire [71:0] leds_p, leds_r, leds_i;
reg [71:0] leds_mux;
wire [7:0] pat_up_a;
wire [71:0] pat_up_d;
wire pat_up_we;
wire [1:0] pattern_type; // 0: free running, 1: stored pattern, 2: random, 3: individual LEDs
led specific_leds[11:0](
.pwm_counter(pwm_counter),
.values(leds_mux),
.leds(leds)
);
stored_pattern p(clk_uart, step, pat_up_a, pat_up_d, pat_up_we, leds_p);
random r(clk_uart, step, pwm_counter, leds_r);
serial s(clk_uart, rx_i, tx, pat_up_a, pat_up_d, pat_up_we, pattern_type, leds_i);
wire clk_switch = clk_div[26];
always @ (*)
case (pattern_type)
0: begin
case(clk_switch)
0: leds_mux <= leds_p;
1: leds_mux <= leds_r;
endcase
end
1: leds_mux <= leds_p;
2: leds_mux <= leds_r;
3: leds_mux <= leds_i;
endcase
endmodule
module random(
input clk,
input step,
input [7:0] pwm_counter,
output [71:0] leds
);
reg [23:0] initializer = 24'hffffff;
always @ (posedge clk)
if (initializer) if (pwm_counter[2]) initializer <= {initializer[22:0], 1'b0};
random_led l[11:0](
.clk({12{clk}}),
.rst(initializer),
.step({12{step}}),
.values(leds)
);
endmodule
module random_led(
input clk,
input [1:0] rst,
input step,
output [5:0] values);
twinkler each_color[1:0](.clk({2{clk}}),
.rst(rst),
.step({2{step}}),
.signal(values));
endmodule
module lfsr3(input clk, input step, input rst, output value);
reg [7:0] lfsr = 0;
wire feedback = lfsr[7] ^ lfsr[5] ^ lfsr[4] ^ lfsr[3];
always @ (posedge clk)
if (rst) lfsr <= lfsr + 1;
else if (step) lfsr <= {lfsr[6:0], feedback};
assign value = lfsr[7] & lfsr[6] & lfsr[5] & lfsr[4] & lfsr[3];
endmodule
module twinkler(
input clk,
input rst,
input step,
output [2:0] signal);
wire go;
lfsr3 rng(.clk(clk), .step(step), .rst(rst), .value(go));
reg [2:0] intensity = 0;
assign signal = intensity;
reg direction = 0;
reg state; initial state = 0;
always @ (posedge clk) begin
case (state)
0: if (go) state <= 1;
1: begin
case (direction)
0: begin
if (step) begin
intensity <= intensity + 1;
if (intensity == 3'b110) direction <= 1;
end
end
1: begin
if (step) begin
intensity <= intensity - 1;
if (intensity == 3'b001) begin
direction <= 0;
state <= 0;
end
end
end
endcase
end
endcase
end
endmodule
module stored_pattern(
input clk,
input step,
input [7:0] pat_up_a,
input [71:0] pat_up_d,
input pat_up_we,
output [71:0] leds
);
wire [71:0] led_values;
assign leds = led_values;
reg [7:0] prog_addr = 0;
// 12 LEDs. 8 bits of color per LED; 4 bits per color. 96 bits per program
// step. BRAMs have 256 x 72 at their widest. Could we reduce the colors so
// that each BRAM load contains an entire program? Well ... if so, there
// would be 6 bits per LED. That would be 8 shades per color. That might be
// ok given this is a V1 product.
ram72bit pattern_ram (
.clka(clk), // input clka
.wea(pat_up_we), // input [0 : 0] wea
.addra(pat_up_we ? pat_up_a : prog_addr), // input [7 : 0] addra
.dina(pat_up_d), // input [71 : 0] dina
.douta(led_values) // output [71 : 0] douta
);
always @ (posedge clk) if (step) prog_addr <= prog_addr + 1;
reg [16:0] clk_div; initial clk_div = 0;
always @ (posedge clk) clk_div <= clk_div + 1;
endmodule
module led(
input [7:0] pwm_counter,
// Red, green, with green LSBs.
input [5:0] values,
output [1:0] leds
);
pwm pwms[1:0](
.counter({2{pwm_counter}}),
.value(values),
.signal(leds)
);
endmodule
module pwm(
input [7:0] counter,
input [2:0] value,
output reg signal
);
reg [7:0] counter_value;
always @ (*) begin
case (value)
0: counter_value <= 0;
1: counter_value <= 15;
2: counter_value <= 35;
3: counter_value <= 63;
4: counter_value <= 99;
5: counter_value <= 143;
6: counter_value <= 195;
7: counter_value <= 255;
endcase
end
// Generate PWM signal
always @ (*) begin
signal <= (counter_value > counter);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000009; long long A[200000]; long long root(long long a) { long long i = a; if (A[i] != i) { A[i] = root(A[i]); } return A[a]; } void unio(long long a, long long b) { long long ra = root(a); long long rb = root(b); if (ra != rb) { A[ra] = rb; } } signed main() { long long n, m; cin >> n >> m; long long val = 1; for (long long i = 1; i <= n; i++) { A[i] = i; } for (long long i = 1; i <= m; i++) { long long a, b; cin >> a >> b; if (root(a) == root(b)) { val = (val * 2LL) % mod; } else { unio(a, b); } val--; val = (val + mod) % mod; cout << val << endl; val++; } }
|
#include <bits/stdc++.h> using namespace std; const int nmax = 100005; int n, cnt, one, two1, two2, p[nmax]; vector<int> v[nmax]; bitset<nmax> viz; int main() { cin.sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) if (!viz[i]) { cnt++; for (int j = i; !viz[j]; j = p[j]) { viz[j] = 1; v[cnt].push_back(j); } } for (int i = 1; i <= n; i++) if (v[i].size() == 1) { one = v[i][0]; break; } if (one) { printf( YES n ); for (int i = 1; i <= n; i++) if (i != one) printf( %d %d n , i, one); return 0; } for (int i = 1; i <= n; i++) if (v[i].size() == 2) { two1 = v[i][0]; two2 = v[i][1]; break; } if (two1) { for (int i = 1; i <= cnt; i++) if (v[i].size() & 1) { printf( NO n ); return 0; } printf( YES n ); printf( %d %d n , two1, two2); for (int i = 1; i <= cnt; i++) if (v[i][0] != two1) for (int j = 0; j < (int)v[i].size(); j++) { if (j & 1) printf( %d %d n , two1, v[i][j]); else printf( %d %d n , two2, v[i][j]); } return 0; } printf( NO n ); return 0; }
|
#include <bits/stdc++.h> const double eps = 1e-15; const int N = 10000 + 10; struct node { double x, y, z; node() {} node(double _x, double _y, double _z) { x = _x; y = _y; z = _z; } }; node a[N], st; int n; double Time[N], len[N], v1, v2; double sqr(double x) { return x * x; } bool eq(double x, double y) { return fabs(x - y) <= eps; } double D(node i, node j) { return sqrt(sqr(i.x - j.x) + sqr(i.y - j.y) + sqr(i.z - j.z)); } int main() { scanf( %d , &n); for (int i = 0; i <= n; ++i) scanf( %lf%lf%lf , &a[i].x, &a[i].y, &a[i].z); scanf( %lf%lf , &v1, &v2); scanf( %lf%lf%lf , &st.x, &st.y, &st.z); if (eq(st.x, a[0].x) && eq(st.y, a[0].y) && eq(st.z, a[0].z)) { puts( YES ); puts( 0 ); printf( %.10f %.10f %.10f n , a[0].x, a[0].y, a[0].z); } else { Time[0] = 0; for (int i = 1; i <= n; ++i) { len[i] = D(a[i - 1], a[i]); Time[i] = Time[i - 1] + len[i] / v2 + eps; } int idx = -1; for (int i = 1; i <= n; ++i) if (D(st, a[i]) <= Time[i] * v1 + eps) { idx = i; break; } if (idx == -1) puts( NO ); else { puts( YES ); double L = len[idx] / v2; double dx = a[idx - 1].x - a[idx].x, dy = a[idx - 1].y - a[idx].y, dz = a[idx - 1].z - a[idx].z; double l = 0, r = len[idx] / v2, mid; for (int i = 0; i < 100; ++i) { mid = (l + r) / 2; if (D(node(a[idx].x + dx * mid / L + eps, a[idx].y + dy * mid / L + eps, a[idx].z + dz * mid / L + eps), st) <= v1 * (Time[idx] - mid) + eps) l = mid; else r = mid; } printf( %.10f n , Time[idx] - l); printf( %.10f %.10f %.10f n , a[idx].x + dx * l / L + eps, a[idx].y + dy * l / L + eps, a[idx].z + dz * l / L + eps); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e2; pair<pair<int, int>, bool> pr[maxn][maxn][2]; queue<pair<pair<int, int>, bool> > q; vector<int> neighbor[maxn]; void bfs(int s, int t) { for (int i = 0; i < maxn; i++) for (int j = 0; j < maxn; j++) for (int k = 0; k < 2; k++) pr[i][j][k] = make_pair(make_pair(-1, -1), false); q.push(make_pair(make_pair(s, t), 0)); while (!q.empty()) { int v = q.front().first.second, u = q.front().first.first; bool b = q.front().second; q.pop(); if (!b) { for (int i = 0; i < neighbor[u].size(); i++) if (pr[neighbor[u][i]][v][!b].first.first == -1) { pr[neighbor[u][i]][v][!b] = make_pair(make_pair(u, v), b); q.push(make_pair(make_pair(neighbor[u][i], v), !b)); } } else { for (int i = 0; i < neighbor[v].size(); i++) if (pr[u][neighbor[v][i]][!b].first.first == -1 && neighbor[v][i] != u && (u != s || neighbor[v][i] != t)) { pr[u][neighbor[v][i]][!b] = make_pair(make_pair(u, v), b); q.push(make_pair(make_pair(u, neighbor[v][i]), !b)); } } } } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; neighbor[u - 1].push_back(v - 1); neighbor[v - 1].push_back(u - 1); } bfs(0, n - 1); if (pr[n - 1][0][0].first.first == -1) cout << -1; else { vector<int> fi, se; pair<pair<int, int>, bool> kl = make_pair(make_pair(n - 1, 0), 0); while (kl.first.first != -1) { if (kl.second) se.push_back(kl.first.second); else fi.push_back(kl.first.first); kl = pr[kl.first.first][kl.first.second][kl.second]; } cout << fi.size() - 1 << endl; for (int i = fi.size() - 1; i > -1; i--) cout << fi[i] + 1 << ; cout << endl; for (int i = se.size() - 1; i > -1; i--) cout << se[i] + 1 << ; cout << 1; } }
|
#include <bits/stdc++.h> using namespace std; const int size = 300000001; bitset<size> gut; int main() { int l, r; cin >> l >> r; gut.set(); for (int i = 3; i * i <= r; i += 2) { if (gut[i]) for (int j = i * i; j <= r; j += (i << 1)) { gut[j] = false; } } int rez = 0; rez = (l <= 2 && r >= 2); for (int i = 5; i <= r; i += 4) { if (i >= l && gut[i]) rez++; } cout << rez << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 30.06.2017 15:34:25
// Design Name:
// Module Name: t_if
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_if;
// Inputs
reg [31:0] pcBranch;
reg [27:0] waInstruction;
reg clk, reset, jump, pcSrc;
// Outputs
wire [31:0] pcPlus4, instruction;
// Initialise the Unit Under Test (UUT)
instructionfetch uut(
.PCPlus4F( pcPlus4 ),
.instruction( instruction ),
.PCBranchF( pcBranch ),
.WAinstrF( waInstruction ),
.clk( clk ),
.reset( reset ),
.JumpF( jump ),
.PCSrcF( pcSrc )
);
// Initialise the clock
initial begin
clk = 0;
forever begin
#20 clk = 1;
#20 clk = 0;
end
end
initial begin
// Initialise Inputs
pcBranch = 0;
waInstruction = 0;
jump = 0;
pcSrc = 0;
reset = 0;
reset = 1; // Reset program counter
#40 reset = 0; // continue normal operation
#260 // Allow normal PC operation to occur for 100 ns
// State 2: Jump Instruction
jump = 1; pcSrc = 0; waInstruction = 27'h000000;
#40 jump = 0; pcSrc = 0; waInstruction = 27'h000000;
// State 1: Branch Instruction
#40 jump = 0; pcSrc = 1; pcBranch = 32'h0000001C;
#40 jump = 0; pcSrc = 0; pcBranch = 32'h00000000;
#100; // Wait 100 until next state is tested
end
endmodule
|
/*
* Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module synverll_sdiv_32x32(
input system_clock,
input system_reset,
input __call_sdiv_req,
output __call_sdiv_ready,
output __call_sdiv_done,
input [31:0] __call_sdiv_args_0,
input [31:0] __call_sdiv_args_1,
output signed [31:0] __call_sdiv_q,
output signed [31:0] __call_sdiv_r
);
reg [33:0] flag_done;
reg [33:0] flag_signed;
reg [30:0] reg_args_0, reg_args_1;
wire [30:0] wire_q, wire_r;
assign __call_sdiv_done = flag_done[33];
assign __call_sdiv_ready = 1;
assign __call_sdiv_q = {flag_signed[33], wire_q};
assign __call_sdiv_r = {0, wire_r};
always @(posedge system_clock or negedge system_reset) begin
if(!system_reset) begin
flag_done <= 0;
flag_signed <= 0;
reg_args_0 <= 0;
reg_args_1 <= 0;
end else begin
flag_done[33:0] <= {flag_done[32:0], __call_sdiv_req};
flag_signed[33:0] <= {flag_signed[32:0], (__call_sdiv_args_0[31] ^ __call_sdiv_args_1[31])};
reg_args_0[30:0] <= (__call_sdiv_args_0[31])?(~__call_sdiv_args_0[30:0]+1):(__call_sdiv_args_0[30:0]);
reg_args_1[30:0] <= (__call_sdiv_args_1[31])?(~__call_sdiv_args_1[30:0]+1):(__call_sdiv_args_1[30:0]);
end
end
aq_div31x31 u_aq_div31x31(
.RST_N ( system_reset ),
.CLK ( system_clock ),
.DINA ( reg_args_0 ),
.DINB ( reg_args_1 ),
.QOUT ( wire_q ),
.ROUT ( wire_r )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; long long x, q = k - 1, flag, a[k], i, j; for (i = 0; i < n; i++) { cin >> x; if (!i) a[q--] = x; else { flag = 0; for (j = k - 1; j > q; j--) { if (a[j] == x) { flag = 1; break; } } if (flag == 0) { if (q < 0) { for (j = k - 1; j > 0; j--) a[j] = a[j - 1]; a[0] = x; } else a[q--] = x; } } } cout << k - (q + 1) << endl; for (i = q + 1; i < k; i++) cout << a[i] << ; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <>
//
// Create Date: 12/29/2016 07:26:09 PM
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_divider #
(
parameter DIVIDER = 15
)
(
input IN_SIG,
output wire OUT_SIG
);
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
localparam BITS = clogb2(DIVIDER-1);
// higher and out of the range of [0, DIVIDER-1]
localparam MAX = 1 << BITS;
// how many counts to keep the out clock low
localparam integer HIGH = DIVIDER / 2;
reg [BITS:0] counter = 0;
always @(posedge IN_SIG)
begin
counter = counter + 1;
if (counter >= DIVIDER) begin
counter = 0;
end
end
assign OUT_SIG = (counter <= HIGH);
endmodule
|
`timescale 1 ns/1 ps
module someTwoPortVendorMem_4096_32_8 (QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
input CENB;
input WENB;
input [11:0] AB;
input [31:0] DB;
input OENB;
reg [31:0] mem [4096:0];
reg [31:0] QA,QB;
initial
begin
$display("%m : someTwoPortVendorMem_4096_32_8 instantiated.");
end
always @(posedge CLKA)
begin
if((CENA == 0)&&(WENA==0))
begin
mem[AA] <= DA;
end
else if((CENA == 0)&&(WENA==1))
begin
QA <=mem[AA];
end
end
always @(posedge CLKB)
begin
if((CENB == 0)&&(WENB==0))
begin
mem[AB] <= DB;
end
else if((CENB == 0)&&(WENB==1))
begin
QB <=mem[AB];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m; cin >> n >> m; string a, b; cin >> a >> b; reverse(a.begin(), a.end()); reverse(b.begin(), b.end()); vector<long long> v(n, 0), u(m, 0); for (long long i = 0; i < n; i++) { if (a[i] == 1 ) { v[i] = 1; } } for (long long i = 0; i < m; i++) { if (b[i] == 1 ) { u[i] = 1; } } for (long long i = m - 2; i >= 0; i--) { u[i] += u[i + 1]; } map<long long, long long> mp; mp[0] = 1; for (long long i = 1; i < 2 * pow(10, 5) + 4; i++) { mp[i] = mp[i - 1] * 2 % 998244353; } long long ans = 0; for (long long i = 0; i < min(v.size(), u.size()); i++) { if (v[i] == 1) { long long x = (mp[i] % 998244353 * u[i] % 998244353) % 998244353; ans = (ans + x) % 998244353; } } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long test = 1; while (test--) solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, ar[3100], cur; vector<int> v; bool valid, used[10000]; pair<int, string> tab[3100]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> tab[i].second >> tab[i].first; } sort(tab, tab + n); valid = true; for (int i = 0; i < n; i++) { if (tab[i].first > i) valid = false; } if (valid) { cur = tab[0].first; for (int i = 0; i < n; i++) { ar[i] = 10; if (tab[i].first > cur) { for (int j = 0; j < v.size(); j++) { ar[v[j]]++; } int bil = tab[i].first - cur; int j = i; while (bil > 0) { j--; if (used[j]) continue; used[j] = true; v.push_back(j); bil--; } cur = tab[i].first; } } for (int j = 0; j < v.size(); j++) { ar[v[j]]++; } for (int i = 0; i < n; i++) { cout << tab[i].second << << ar[i] << endl; } } else { cout << -1 << endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:18 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_stub.v
// Design : bram_2048_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_2048_1(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [10:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_TB_V
`define SKY130_FD_SC_HS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_TB_V
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_TB_V
`define SKY130_FD_SC_HD__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 7; const long long INF = (long long)1e9 + 7; char st[N]; map<long long, long long> s[200]; long long c[N]; int main() { int n; long long t, ans = 0, x = 0; for (char i = a ; i <= z ; i++) cin >> c[i]; gets(st); gets(st); n = strlen(st); for (int i = 0; i < n; i++) { x += c[st[i]]; ans += s[st[i]][x - c[st[i]]]; s[st[i]][x]++; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int x[4], y[4], a[4], b[4]; vector<int> v[2]; void yes() { puts( YES ); exit(0); } void add(bool is, int at, int to) { if (is) v[is].push_back(y[at]), v[is].push_back(y[to]); else v[is].push_back(x[at]), v[is].push_back(x[to]); } void can(int a, int b) { if (v[0][0] <= a && v[0][1] >= a && v[1][0] <= b && v[1][1] >= b) yes(); } int main() { for (int i = 0; i < 4; i++) scanf( %d%d , x + i, y + i); add(x[0] == x[1], 0, 1); add(x[1] == x[2], 1, 2); sort(v[0].begin(), v[0].end()); sort(v[1].begin(), v[1].end()); for (int i = 0; i < 4; i++) { scanf( %d%d , a + i, b + i); can(a[i], b[i]); } can((a[0] + a[2]) / 2, (b[0] + b[2]) / 2); int dis = b[0] != b[2] ? abs(b[0] - b[2]) : abs(a[0] - a[2]), mx = (a[0] + a[2]) / 2, my = (b[0] + b[2]) / 2; for (int i = 0; i < 4; i++) { int dis1 = abs(x[i] - mx) + abs(y[i] - my); if (dis1 * 2 <= dis) yes(); } puts( NO ); }
|
#include <bits/stdc++.h> using namespace std; const int dx[4] = {0, 0, -1, 1}; const int dy[4] = {-1, 1, 0, 0}; int main() { int i, j, k, n; long int mx, mn, sm = 0; int t; cin >> t; while (t--) { int f = 0; cin >> n; vector<pair<int, int>> v(n); for (i = 0; i < n; i++) { int a, b; cin >> a >> b; v[i] = (make_pair(a, b)); } if (v[0].first < v[0].second) f = 1; for (i = 1; i < n; i++) { int x = v[i].first - v[i - 1].first; int y = v[i].second - v[i - 1].second; if (x < 0 || y < 0 || (v[i].first < v[i].second) || (v[i - 1].first < v[i - 1].second) || y > x) { f = 1; break; } } if (f) cout << NO << n ; else { cout << YES << n ; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int Mod = 1000000007; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double e = exp(1); const double PI = acos(-1); const double ERR = 1e-10; int head[maxn], cnt, n, tot, mstnum; int dfn[maxn], father[maxn], rank_[maxn], sz[maxn]; pair<int, int> range[maxn]; long long c[maxn]; bool mark[maxn]; set<int> se; unordered_map<long long, int> mp; struct node { int v, nxt; } Edge[2 * maxn]; struct edge { int u, v, id; long long w; edge() {} edge(int _id, int _u, int _v, long long _w) : id(_id), u(_u), v(_v), w(_w) {} } mst[2 * maxn]; bool operator<(edge a, edge b) { return a.w < b.w; } vector<edge> ve[maxn]; void init() { for (int i = 0; i <= n; i++) { head[i] = -1; father[i] = i; rank_[i] = 0; } cnt = 0; tot = 0; mstnum = 0; } void addedge(int u, int v) { Edge[cnt].v = v; Edge[cnt].nxt = head[u]; head[u] = cnt++; } void dfs(int id, int fa) { sz[id] = 1; range[id].first = 0x3f3f3f3f; range[id].second = -1; for (int i = head[id]; i != -1; i = Edge[i].nxt) { int v = Edge[i].v; if (v == fa) continue; dfs(v, id); range[id].first = min(range[id].first, range[v].first); range[id].second = max(range[id].second, range[v].second); sz[id] += sz[v]; } if (sz[id] == 1) { dfn[id] = ++tot; range[id].first = range[id].second = tot; } } int find(int id) { return father[id] == id ? id : father[id] = find(father[id]); } void merge(int x, int y) { x = find(x); y = find(y); if (x != y) { if (rank_[x] > rank_[y]) father[y] = x; else { father[x] = y; if (rank_[x] == rank_[y]) rank_[y]++; } } } int main() { int u, v; scanf( %d , &n); init(); for (int i = 1; i <= n; i++) { scanf( %lld , &c[i]); } for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); addedge(u, v); addedge(v, u); } dfs(1, -1); long long ans = 0; int num = 0; for (int i = 1; i <= n; i++) { mst[i] = edge(i, range[i].first - 1, range[i].second, c[i]); } sort(mst + 1, mst + 1 + n); for (int i = 1; i <= n; i++) { if (mp.find(mst[i].w) == mp.end()) { mp[mst[i].w] = ++num; } ve[mp[mst[i].w]].push_back(mst[i]); } for (int i = 1; i <= num; i++) { for (auto ed : ve[i]) { int x = find(ed.u); int y = find(ed.v); int id = ed.id; if (x != y) { se.insert(id); } } for (auto ed : ve[i]) { int x = find(ed.u); int y = find(ed.v); if (x != y) { ans += ed.w; merge(x, y); } } } printf( %lld %d n , ans, (int)se.size()); for (auto x : se) { printf( %d , x); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.F << : << m.S << ) ; return os << } ; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } long long const M = 1e9; bool check(long long v, long long n, long long k) { long long s = n; long long d = k; while (n / k >= 1) { s = s + n / k; k = k * d; } return (s >= v); } int main() { long long n, k; cin >> n >> k; long long l = 0; long long r = M; while (r - l > 1) { long long mid = (l + r) >> 1; if (check(n, mid, k)) r = mid; else l = mid; } cout << r << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MXN = 2e5 + 5; int x[MXN]; int y[MXN]; int d[MXN]; int xr[MXN]; int par[MXN]; int siz[MXN]; int sol[MXN]; int type[MXN]; int basis[30]; stack<pair<int *, int>> stk; vector<array<int, 3>> st[2 << 18]; void change(int &ref, int val) { stk.push({&ref, ref}); ref = val; } array<int, 2> get(int x) { int len = 0; while (par[x]) { len ^= xr[x]; x = par[x]; } return {x, len}; } void join(int x, int y, int d) { auto [px, xrx] = get(x); auto [py, xry] = get(y); if (px == py) { int cycle = xrx ^ d ^ xry; for (int i = 29; i >= 0; --i) { if (cycle >> i & 1) { if (basis[i]) { cycle ^= basis[i]; } else { change(basis[i], cycle); break; } } } } else { if (siz[px] < siz[py]) { swap(px, py); } change(siz[px], siz[px] + siz[py]); change(xr[py], xrx ^ d ^ xry); change(par[py], px); } } void dfs(int lo, int hi, int nd = 0) { int sz = stk.size(); for (auto [x, y, d] : st[nd]) { join(x, y, d); } if (lo + 1 == hi) { sol[lo] ^= get(x[lo])[1]; sol[lo] ^= get(y[lo])[1]; for (int i = 29; i >= 0; --i) { sol[lo] = min(sol[lo], sol[lo] ^ basis[i]); } } else { int mid = (lo + hi) / 2; dfs(lo, mid, 2 * nd + 1); dfs(mid, hi, 2 * nd + 2); } while (sz < (int)stk.size()) { auto [ptr, val] = stk.top(); *ptr = val; stk.pop(); } } void add(int l, int r, array<int, 3> e, int lo, int hi, int nd = 0) { if (l <= lo && hi <= r) return st[nd].push_back(e); int mid = (lo + hi) / 2; if (l < mid) add(l, r, e, lo, mid, 2 * nd + 1); if (mid < r) add(l, r, e, mid, hi, 2 * nd + 2); } int main() { ios::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; map<array<int, 2>, array<int, 2>> mp; for (int i = 0; i < m; ++i) { int x, y, d; cin >> x >> y >> d; mp[{x, y}] = {0, d}; } int q; cin >> q; int sz = 0; for (int i = 0; i < q; ++i) { cin >> type[i] >> x[i] >> y[i]; if (type[i] == 1) cin >> d[i]; sz += type[i] == 3; } int cq = 0; for (int i = 0; i < q; ++i) { if (type[i] == 1) { mp[{x[i], y[i]}] = {cq, d[i]}; } else if (type[i] == 2) { auto [pq, d] = mp[{x[i], y[i]}]; mp.erase({x[i], y[i]}); if (pq < cq) add(pq, cq, {x[i], y[i], d}, 0, sz); } else { x[cq] = x[i]; y[cq] = y[i]; cq++; } } for (auto [a, b] : mp) { if (b[0] < sz) add(b[0], sz, {a[0], a[1], b[1]}, 0, sz); } for (int i = 1; i <= n; ++i) { siz[i] = 1; } dfs(0, sz); for (int i = 0; i < sz; ++i) { cout << sol[i] << n ; } }
|
#include <bits/stdc++.h> using namespace std; int u[1005], v[1005], fa[1005], n, m, k; bool zt[1005][1005]; int getv(int x) { if (x == fa[x]) return x; fa[x] = getv(fa[x]); return fa[x]; } void merge(int x, int y) { x = getv(x); y = getv(y); if (x == y) return; if (x < y) { int t = x; x = y; y = t; } fa[x] = y; for (int i = 1; i <= m; i++) { if (zt[x][i]) zt[y][i] = true; } } unsigned long long ha(char zf[1005]) { unsigned long long rt = 0; for (int i = 0; zf[i]; i++) rt = rt * 13131 + zf[i]; return rt; } map<unsigned long long, int> mp; char zf[1005]; int wz[1005], rw[1005], yw[1005]; int w2[1005], r2[1005], y2[1005]; bool b1[1005], b2[1005]; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) scanf( %d%d , &u[i], &v[i]); for (int i = 1; i <= k; i++) { int a, s; scanf( %s%d%d , zf, &a, &s); rw[i] = a; mp[ha(zf)] = i; for (int j = 0; j < s; j++) { int b; scanf( %d , &b); zt[a][b] = 1; yw[b] = a; } } for (int a = 1; a <= m; a++) { for (int i = 1; i <= m; i++) { if (!b1[i] && (zt[getv(u[i])][i] || zt[getv(v[i])][i])) { merge(u[i], v[i]); b1[i] = true; } } } for (int i = 1; i <= n; i++) wz[i] = getv(i); for (int i = 1; i <= m; i++) yw[i] = getv(yw[i]); for (int i = 1; i <= k; i++) rw[i] = getv(rw[i]); for (int i = 1; i <= n; i++) { fa[i] = i; for (int j = 1; j <= m; j++) zt[i][j] = 0; } for (int i = 1; i <= k; i++) { int a, s; scanf( %s%d%d , zf, &a, &s); r2[mp[ha(zf)]] = a; for (int j = 0; j < s; j++) { int b; scanf( %d , &b); zt[a][b] = 1; y2[b] = a; } } for (int a = 1; a <= m; a++) { for (int i = 1; i <= m; i++) { if (!b2[i] && (zt[getv(u[i])][i] || zt[getv(v[i])][i])) { merge(u[i], v[i]); b2[i] = true; } } } for (int i = 1; i <= n; i++) w2[i] = getv(i); for (int i = 1; i <= m; i++) y2[i] = getv(y2[i]); for (int i = 1; i <= k; i++) r2[i] = getv(r2[i]); bool zd = false; for (int i = 1; i <= n; i++) { if (wz[i] != w2[i]) zd = true; } for (int i = 1; i <= k; i++) { if (rw[i] != r2[i]) zd = true; } for (int i = 1; i <= m; i++) { if (yw[i] != y2[i]) zd = true; } for (int i = 1; i <= m; i++) { if (b1[i] != b2[i]) zd = true; } if (zd) printf( NO ); else printf( YES ); return 0; }
|
// bsg_clk_gen_osc
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the standard cell library
// that we verify to be glitch-free using spice simulation (presumably because it is based on a
// t-gate design). If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 40 by running with sdf annotations.
//
// Gen 2 specific info (starting with 40nm) MBT 5-26-2018
//
// This Gen 2 clock generator has been slight redesigned in order to address the races
// in the gen 1 design that prevented automation.
//
// We use the bsg_tag_client_unsync implementation in order to reduce the load on
// the internally generated clock. Additionally, we separate out the we_r trigger
// signal so that it is explicitly set. This means that to set the frequency
// on average, three packets will need to be sent. First, a packet will be sent
// to set clock configuration bits. Then a packet will be sent to enable the we_r
// signal. Finally a packet will be sent to clear the we_r signal.
// This applies only for the oscillator programming.
//
// The trigger is synchronized inside the ADT; and then the synchronized signal
// is buffered and passed on to the CDT and then to the FDT, mirroring the
// flow of the clock signal through the units.
//
// The goal of this approach is to ensure that a new value is latched into the
// oscillator's configuration registers atomically, and during the first negative
// clock phase after a positive edge.
//
//
// The downsampler uses the normal interface.
//
//
// Gen 1 specific info (for reference)
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
//
//
//
`timescale 1ps/1ps
`include "bsg_clk_gen.vh"
module bsg_clk_gen_osc
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input async_reset_i
,output clk_o
);
wire fb_clk;
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s tag_r_async;
wire tag_trigger_r_async;
wire adt_to_cdt_trigger_lo, cdt_to_fdt_trigger_lo;
// this is a raw interface; and wires will toggle
// as the bits shift in. the wires are also
// unsynchronized with respect to the target domain.
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(tag_r_async)
);
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(1)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(tag_trigger_r_async)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
wire [15:0] fb_clk_dly_time;
assign #(fb_clk_dly_time) fb_clk_del = fb_clk;
// synopsys translate_off
bsg_clk_gen_osc_tag_payload_s tag_r_sync;
always @(posedge clk_o or posedge async_reset_i)
tag_r_sync <= (async_reset_i)? '0 :
((tag_trigger_r_async)? tag_r_async : tag_r_sync);
assign fb_clk_dly_time = 125+((1<<$bits(tag_r_sync))-tag_r_sync)*5;
// synopsys translate_on
bsg_rp_clk_gen_atomic_delay_tuner adt_BSG_DONT_TOUCH
(.i(fb_clk_del)
,.we_async_i (tag_trigger_r_async )
,.we_inited_i(bsg_tag_trigger_i.en )
,.async_reset_neg_i(async_reset_neg )
,.sel_i(tag_r_async.adg[0] )
,.we_o(adt_to_cdt_trigger_lo )
,.o(adt_lo )
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt_BSG_DONT_TOUCH
(.i (adt_lo)
,.we_i (adt_to_cdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg )
,.sel_i (tag_r_async.cdt )
,.we_o (cdt_to_fdt_trigger_lo)
,.o (cdt_lo)
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt_BSG_DONT_TOUCH
(.i (cdt_lo)
,.we_i (cdt_to_fdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg)
,.sel_i (tag_r_async.fdt)
,.o (fb_clk) // in the actual critical loop
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_clk_gen_osc)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_2_V
`define SKY130_FD_SC_LS__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 7; long long M = 1e9 + 7; long long dp[N]; long long g[N][30]; int n; vector<int> a; int ch[N][N]; int main() { ch[0][0] = 1; cin >> n; for (int i = 1; i <= n; i++) { for (int j = 0; j <= i; j++) { if (j == 0) { ch[j][i] = 1; continue; } ch[j][i] = (ch[j - 1][i - 1] + ch[j][i - 1]) % M; } } for (int i = 1; i <= n; i++) { char c; cin >> c; if (!a.size()) a.push_back(c - a + 1); else if (a.back() != c - a + 1) a.push_back(c - a + 1); } dp[0] = 1; for (int i = 0; i < a.size(); i++) { for (int j = a.size(); j >= 2; j--) { dp[j] += -g[j][a[i]] - g[j - 1][a[i]] + dp[j - 1]; g[j][a[i]] = dp[j - 1] - g[j - 1][a[i]]; dp[j] %= M; g[j][a[i]] %= M; } if (g[1][a[i]] == 0) dp[1]++; g[1][a[i]] = 1; } long long res = 0; for (int i = 1; i <= n; i++) { dp[i] = (((dp[i] % M) + M) % M); res = (res + ch[i - 1][n - 1] * dp[i]) % M; } cout << res; return 0; }
|
/*****************************************************************************
* *
* Module: Altera_UP_Audio_Bit_Counter *
* Description: *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
*****************************************************************************/
module Altera_UP_Audio_Bit_Counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'd31;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [4:0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
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