text
stringlengths 59
71.4k
|
|---|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
// 2010/01/09/ Corrected dfifo_has_enough_room threshold logic.
// It has to set higher in Read Only port.
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input cmd_valid_i,
input data_valid_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input user_bl_cnt_is_1,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
input gen_rdy_i,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output [6:0] rd_buff_avail_o,
input rd_mdata_fifo_empty,
output rd_mdata_en
);
reg empty_r;
reg rd_first_data;
wire full;
wire empty;
wire wr_en;
reg rd_en;
reg data_valid_r;
reg user_bl_cnt_not_1;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en;
assign rd_buff_avail_o = buf_avail_r;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room & wait_done;
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin // prbs_blen from cmd_gen is random, it can be two 64 in consecutive
// the logic here to prevent cmd_gen send any further read command if
// any large bl command has been sent.
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 62 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
assign wr_en = cmd_valid_i & !full & dfifo_has_enough_room_d1 & wait_done;
always @ (posedge clk_i)
data_valid_r <= #TCQ data_valid_i;
always @ (posedge clk_i)
begin
if (data_valid_i && user_bl_cnt_is_1) // current count is 1 and data_is_valie, then next cycle is not 1
user_bl_cnt_not_1 <= #TCQ 1'b1;
else
user_bl_cnt_not_1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1) begin
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
// MCB FIFO size is 64.
// buf_available is calculated by:
// FIFO DEPTH - ( Write Poitner - Read Pointer)
buf_avail_r <= #TCQ 64 - (rd_data_counts_asked - rd_data_received_counts);
always @(gen_rdy_i, empty,empty_r,rd_mdata_fifo_empty,rd_first_data ,data_valid_i,data_valid_r,user_bl_cnt_not_1)
begin
if (FAMILY == "SPARTAN6")
rd_en = gen_rdy_i & !empty;
else
if ( MEM_BURST_LEN == 4)
rd_en = (~empty & empty_r & ~rd_first_data) | (~rd_mdata_fifo_empty & ~empty ) | (user_bl_cnt_not_1 & data_valid_i);
else
rd_en = (data_valid_i & ~data_valid_r) | (user_bl_cnt_not_1 & data_valid_i);
end
always @ (posedge clk_i)
empty_r <= #TCQ empty;
always @ (posedge clk_i)
begin
if (rst_i)
rd_first_data <= #TCQ 1'b0;
else if (~empty && empty_r)
rd_first_data <= #TCQ 1'b1;
end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool cmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int N = 444444; int fa[N], ch[N][26], l[N], f[N], a[N], c[N], pos[N], top[N]; char s[N]; int last = 1, cnt = 1, n, ans = 1; void ins(int c, int k) { int p = last, np = ++cnt; last = np, l[np] = l[p] + 1, pos[np] = k; for (; p && !ch[p][c]; p = fa[p]) ch[p][c] = np; if (!p) fa[np] = 1; else { int q = ch[p][c]; if (l[q] == l[p] + 1) fa[np] = q; else { int nq = ++cnt; l[nq] = l[p] + 1, pos[nq] = pos[q]; memcpy(ch[nq], ch[q], sizeof(ch[q])); fa[nq] = fa[q], fa[np] = fa[q] = nq; for (; ch[p][c] == q; p = fa[p]) ch[p][c] = nq; } } } void calc() { for (int i = 1; i <= cnt; ++i) ++c[l[i]]; for (int i = 1; i <= cnt; ++i) c[i] += c[i - 1]; for (int i = 1; i <= cnt; ++i) a[c[l[i]]--] = i; } int L[N * 25], R[N * 25], rt[N], tot; void modify(int &now, int l, int r, int x) { now = ++tot; if (l == r) return; int mid = l + r >> 1; if (x <= mid) modify(L[now], l, mid, x); else modify(R[now], mid + 1, r, x); } int merge(int x, int y) { if (!x || !y) return x | y; int z = ++tot; L[z] = merge(L[x], L[y]); R[z] = merge(R[x], R[y]); return z; } int query(int x, int l, int r, int ql, int qr) { if (!x) return 0; if (ql <= l && qr >= r) return 1; int mid = l + r >> 1; if (ql <= mid && query(L[x], l, mid, ql, qr)) return 1; if (qr > mid && query(R[x], mid + 1, r, ql, qr)) return 1; return 0; } int main() { scanf( %d , &n); scanf( %s , s + 1); for (int i = 1; i <= n; ++i) ins(s[i] - a , i), modify(rt[last], 1, n, i); calc(); for (int i = cnt; i > 1; --i) rt[fa[a[i]]] = merge(rt[fa[a[i]]], rt[a[i]]); for (int i = 2; i <= cnt; ++i) { int u = a[i], ff = fa[u]; if (ff == 1) { f[u] = 1, top[u] = u; continue; } int x = query(rt[top[ff]], 1, n, pos[u] - l[u] + l[top[ff]], pos[u] - 1); if (x) f[u] = f[ff] + 1, top[u] = u; else f[u] = f[ff], top[u] = top[ff]; cmax(ans, f[u]); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { map<int, int> pos1; map<int, int> pos2; int n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; pos1[a[i]] = i; } for (int i = 0; i < n; i++) { cin >> b[i]; pos2[b[i]] = i; } map<int, int> h; for (int i = 1; i <= n; i++) { if (pos1[i] <= pos2[i]) { h[pos2[i] - pos1[i]]++; } else { h[n - pos1[i] + pos2[i]]++; } } int mx = 0; for (int i = 0; i <= 2 * n; i++) { if (h[i] > mx) mx = h[i]; } cout << mx; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; struct Point { int x, y; void read() { int a, b; scanf( %d%d , &a, &b); x = a + b; y = a - b; } bool operator<(const Point p) const { return x != p.x ? x < p.x : y < p.y; } } p[N]; int n; int pre_min[N], pre_max[N]; int suf_min[N], suf_max[N]; bool check(long long mid) { for (int l = 1, r = 1; r <= n; r++) { while (p[r].x - p[l].x > mid && l <= n) l++; int mx = max(pre_max[l - 1], suf_max[r + 1]); int mn = min(pre_min[l - 1], suf_min[r + 1]); if (mx - mn <= mid) return true; } return false; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) p[i].read(); sort(p + 1, p + 1 + n); pre_min[0] = INT_MAX; pre_max[0] = INT_MIN; suf_min[n + 1] = INT_MAX; suf_max[n + 1] = INT_MIN; for (int i = 1; i <= n; i++) { pre_max[i] = max(pre_max[i - 1], p[i].y); pre_min[i] = min(pre_min[i - 1], p[i].y); } for (int i = n; i >= 1; i--) { suf_max[i] = max(suf_max[i + 1], p[i].y); suf_min[i] = min(suf_min[i + 1], p[i].y); } long long ans, low = 0, high = 1LL << 50, mid; while (low <= high) { mid = (low + high) >> 1; if (check(mid)) high = mid - 1, ans = mid; else low = mid + 1; } printf( %.10f n , ans / 2.0); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dirx[] = {1, -1, 0, 0, 1, 1, -1, -1}, diry[] = {0, 0, 1, -1, 1, -1, 1, -1}; bool Set(int n, int pos) { return bool(n & (1 << pos)); } int32_t main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; string a, b; cin >> a >> b; int dp[n + 1][m + 1], ans = -1; memset(dp, 0, sizeof(dp)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { dp[i][j] = max(0, max(dp[i - 1][j], dp[i][j - 1]) - 1); if (a[i - 1] == b[j - 1]) dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + 2); ans = max(ans, dp[i][j]); } } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbn (
VPWR ,
VGND ,
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, intgate, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; typedef struct node_t { int l, r, k, id; friend bool operator<(const node_t& a, const node_t& b) { if (a.r == b.r) return a.l > b.l; return a.r < b.r; } void print() { printf( l = %d, r = %d, k = %d, id = %d n , l, r, k, id); } } node_t; const int maxn = 1e5 + 5; node_t Q[maxn], P[maxn]; int ans[maxn]; int main() { ios::sync_with_stdio(false); int n, m; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d %d , &Q[i].l, &Q[i].r); Q[i].id = i; } scanf( %d , &m); for (int i = 0; i < m; ++i) { scanf( %d %d %d , &P[i].l, &P[i].r, &P[i].k); P[i].id = i + 1; } sort(Q, Q + n); sort(P, P + m); set<pair<int, int> > st; set<pair<int, int> >::iterator iter, titer; int i, j, k; i = 0; for (j = 0; j < m; ++j) { while (i < n && Q[i].r <= P[j].r) { st.insert(make_pair(Q[i].l, Q[i].id)); ++i; } iter = st.lower_bound(make_pair(P[j].l, -1)); while (iter != st.end() && P[j].k-- > 0) { ans[iter->second] = P[j].id; titer = iter; iter++; st.erase(titer); } } if (i < n || st.size() > 0) { puts( NO ); } else { puts( YES ); for (int i = 0; i < n; ++i) { printf( %d , ans[i]); } putchar( n ); } return 0; }
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// Galois Field multiplier.
//
//------------------------------------------------------------------------------
`ifndef _ZL_GF_MUL_V_
`define _ZL_GF_MUL_V_
module zl_gf_mul #
(
parameter Gf_width = 0,
parameter Gf_poly = 0
)
(
input [Gf_width-1:0] a,
input [Gf_width-1:0] b,
output [Gf_width-1:0] out
);
// compute a*b
function [Gf_width*2-2:0] a_conv_b;
input [Gf_width-1:0] a;
input [Gf_width-1:0] b;
//
reg [Gf_width*2-2:0] retval;
integer i,j;
begin
retval = 0;
for(i=0;i<Gf_width*2-1;i=i+1) begin
for(j=0;j<Gf_width;j=j+1) begin
if(i>=j && i-j<Gf_width) begin
retval[i] = retval[i] ^ (a[j]&b[i-j]);
end
end
end
a_conv_b = retval;
end
endfunction
// mod by gf poly
function [Gf_width-1:0] mod_gf;
input [Gf_width*2-2:0] f;
//
reg [Gf_width-1:0] retval;
integer i;
begin
retval = 0;
for(i=0;i<Gf_width*2-1;i=i+1) begin
retval =
{retval[Gf_width-2:0], f[Gf_width*2-2-i]}
^ ({Gf_width{retval[Gf_width-1]}}
& Gf_poly[Gf_width-1:0]);
end
mod_gf = retval;
end
endfunction
assign out = mod_gf(a_conv_b(a,b));
endmodule // zl_gf_mul
`endif // _ZL_GF_MUL_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_1_V
`define SKY130_FD_SC_LP__O31A_1_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hdll__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Multiplier - computes a*b
*/
module dsp_mult #
(
parameter WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI stream inputs
*/
input wire [WIDTH-1:0] input_a_tdata,
input wire input_a_tvalid,
output wire input_a_tready,
input wire [WIDTH-1:0] input_b_tdata,
input wire input_b_tvalid,
output wire input_b_tready,
/*
* AXI stream output
*/
output wire [(WIDTH*2)-1:0] output_tdata,
output wire output_tvalid,
input wire output_tready
);
reg [WIDTH-1:0] input_a_reg_0 = 0;
reg [WIDTH-1:0] input_a_reg_1 = 0;
reg [WIDTH-1:0] input_b_reg_0 = 0;
reg [WIDTH-1:0] input_b_reg_1 = 0;
reg [(WIDTH*2)-1:0] output_reg_0 = 0;
reg [(WIDTH*2)-1:0] output_reg_1 = 0;
wire transfer = input_a_tvalid & input_b_tvalid & output_tready;
assign input_a_tready = input_b_tvalid & output_tready;
assign input_b_tready = input_a_tvalid & output_tready;
assign output_tdata = output_reg_1;
assign output_tvalid = input_a_tvalid & input_b_tvalid;
always @(posedge clk) begin
if (rst) begin
input_a_reg_0 <= 0;
input_a_reg_1 <= 0;
input_b_reg_0 <= 0;
input_b_reg_1 <= 0;
output_reg_0 <= 0;
output_reg_1 <= 0;
end else begin
if (transfer) begin
// pipeline for Xilinx DSP slice
// register
input_a_reg_0 <= input_a_tdata;
input_b_reg_0 <= input_b_tdata;
// pipeline
input_a_reg_1 <= input_a_reg_0;
input_b_reg_1 <= input_b_reg_0;
// multiply
output_reg_0 <= $signed(input_a_reg_1) * $signed(input_b_reg_1);
// pipeline
output_reg_1 <= output_reg_0;
end
end
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_scrambler
*
* Description:
*
* This module implements a parallel scrambler based on the
* polynomial 1+ x^(-14) + x^(-15).
* Such Scrambler is typically shown as a 15 bit Linear Feedback Shift Register
* (LFSR) with bits shifting from register 1 on the left to register 15 on the
* right, with register 14 and 15 combining to shift into register 1.
* The HMC Serializer outputs data[0] first from parallel tx data[n:0],
* so if data[n:0] is to be bitwise scrambled with LFSR[n:0], we need the LFSR
* to shift from n -> 0, the opposite direction from the typical illustration.
* This implementation shifts data from LFSR[14] on the left to LFSR[0] on the
* right, with LFSR[1] and [0] combining to shift into LFSR[14]. This way
* LFSR[14:0] can bitwise scramble data[14:0] and be compatible with serializ-
* ation that shifts out on the data[0] side.
* Put otherwise: Polynomial 1+ x^(-14) + x^(-15) is equiv to
* x^15 + x^1 + x^0
* This parallelized version calculates the next LANE_WIDTH steps of values for
* the LFSR. These bits are used to scramble the parallel input, and to
* choose the next value of lfsr (lfsr_steps[LANE_WIDTH-1]).
*/
`default_nettype none
module tx_scrambler #(
parameter LANE_WIDTH = 16,
parameter HMC_RX_AC_COUPLED = 1
)
(
input wire clk,
input wire res_n,
input wire disable_scrambler,
input wire [14:0] seed, // unique per lane
input wire [LANE_WIDTH-1:0] data_in,
output reg [LANE_WIDTH-1:0] data_out,
input wire rf_run_length_enable,
output wire rf_run_length_bit_flip
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire [LANE_WIDTH-1:0] data_out_tmp;
wire [LANE_WIDTH-1:0] run_length_d_out;
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
wire [14:0] lfsr_steps [LANE_WIDTH-1:0]; // LFSR values for serial time steps
reg seed_set;
// SEQUENTIAL PROCESS
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if (!res_n) begin
seed_set <= 1'b0;
lfsr[14:0] <= 15'h0;
data_out <= {LANE_WIDTH {1'b0}};
end
else
begin
if(!seed_set) begin
lfsr[14:0] <= seed;
seed_set <= 1'b1;
end else begin
if (disable_scrambler) begin
lfsr[14:0] <= 15'h0;
end else begin
lfsr[14:0] <= lfsr_steps[LANE_WIDTH-1];
end
end
data_out <= run_length_d_out;
end
end // serial shift right with left input
// SCRAMBLE
genvar j;
generate
assign data_out_tmp [0] = data_in[0] ^ lfsr[0]; // single bit scrambled.
assign lfsr_steps[0] = { (lfsr[1] ^ lfsr[0]) , lfsr[14:1] }; // lfsr at next bit clock
for(j = 1; j < LANE_WIDTH; j = j + 1) begin : scrambler_gen
assign data_out_tmp[j] = data_in[j] ^ lfsr_steps[j-1][0];
assign lfsr_steps[j] = { (lfsr_steps[j-1][1] ^ lfsr_steps[j-1][0]) , lfsr_steps[j-1][14:1] };
end
endgenerate
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
generate
if(HMC_RX_AC_COUPLED==1) begin
tx_run_length_limiter #(
.LANE_WIDTH(LANE_WIDTH)
)
run_length_limiter_I
(
.clk(clk),
.res_n(res_n),
.enable(rf_run_length_enable),
.data_in(data_out_tmp),
.data_out(run_length_d_out),
.rf_bit_flip(rf_run_length_bit_flip)
);
end else begin
assign rf_run_length_bit_flip = 1'b0;
assign run_length_d_out = data_out_tmp;
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int maxn = 6e5 + 10; int n, k, l[maxn][2]; int fa[maxn], sz[maxn]; string s; int get_fa(int x) { if (x == fa[x]) return x; return fa[x] = get_fa(fa[x]); } int calc(int x) { int y; if (x <= k) y = x + k; else y = x - k; x = get_fa(x), y = get_fa(y); if (x == 0 || y == 0) return sz[x + y]; return min(sz[x], sz[y]); } void merge_dis(int x, int y) { x = get_fa(x); y = get_fa(y); if (y == 0) { swap(x, y); } fa[y] = x; if (x != 0) sz[x] += sz[y]; } int main() { scanf( %d%d , &n, &k); cin >> s; for (int i = 1; i <= (int)3e5; i++) fa[i] = i, fa[i + k] = i + k, sz[i + k] = 1; for (int i = 1, c; i <= k; i++) { scanf( %d , &c); for (int j = 0, x; j < c; j++) { scanf( %d , &x); if (l[x][0] == 0) l[x][0] = i; else l[x][1] = i; } } int ans = 0; for (int i = 1; i <= n; i++) { if (l[i][1] == 0) { int x = l[i][0]; if (x) { ans -= calc(x); if (s[i - 1] == 1 ) fa[get_fa(x + k)] = 0; else fa[get_fa(x)] = 0; ans += calc(x); } } else { int x = l[i][0], y = l[i][1]; if (s[i - 1] == 1 ) { if (get_fa(x) != get_fa(y)) { ans -= calc(x); ans -= calc(y); merge_dis(x, y); merge_dis(x + k, y + k); ans += calc(x); } } else { if (get_fa(x + k) != get_fa(y)) { ans -= calc(x); ans -= calc(y); merge_dis(x + k, y); merge_dis(x, y + k); ans += calc(x); } } } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool compare(pair<pair<long long int, long long int>, long long int> p1, pair<pair<long long int, long long int>, long long int> p2) { return p1.first.first < p2.first.first; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int i, te, j, x, n, m, k, t, y, a, b, r; te = 1; while (te--) { string s; cin >> s; n = s.length(); long long int a[n], c[n], ans = 0, cnt = 0, co = 0; for (i = 0; i < n; i++) { if (s[i] == o ) co++; c[i] = co; } for (i = n - 1; i >= 0; i--) { if (s[i] == o ) { ans += cnt; } if (s[i] == v && s[i - 1] == v && i >= 1) { cnt++; } a[i] = ans; } cnt = 0; for (i = 0; i <= n - 1; i++) { if (s[i] == v && s[i + 1] == v ) { cnt += a[i]; } } cout << cnt << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_4_V
`define SKY130_FD_SC_HD__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: data_select
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Uses "sel" input signals to select data to output on "data" bus.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module data_select(
x_axis,
y_axis,
z_axis,
temp_data,
data,
sel
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [15:0] x_axis;
input [15:0] y_axis;
input [15:0] z_axis;
input [7:0] temp_data;
input [1:0] sel;
output [15:0] data;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
reg [15:0] data;
// ==============================================================================
// Implementation
// ==============================================================================
always @(sel, x_axis, y_axis, z_axis, temp_data) begin
case (sel)
2'b00 : data <= x_axis;
2'b01 : data <= y_axis;
2'b10 : data <= z_axis;
2'b11 : data <= {8'h00, temp_data};
endcase
end
endmodule
|
`define ADDER_WIDTH 017
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ee_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ee_e.v,v 1.1 2004/04/06 10:50:31 wig Exp $
// $Date: 2004/04/06 10:50:31 $
// $Log: inst_ee_e.v,v $
// Revision 1.1 2004/04/06 10:50:31 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ee_e
//
// No `defines in this module
module inst_ee_e
//
// Generated module inst_ee
//
(
cgs_ramclk,
itm_scani,
nreset,
nreset_s,
si_vclkx2,
tmi_sbist_fail,
tmi_scano
);
// Generated Module Inputs:
input cgs_ramclk;
input nreset;
input nreset_s;
input si_vclkx2;
input [12:0] tmi_sbist_fail;
input [70:0] tmi_scano;
// Generated Module Outputs:
output [70:0] itm_scani;
// Generated Wires:
wire cgs_ramclk;
wire [70:0] itm_scani;
wire nreset;
wire nreset_s;
wire si_vclkx2;
wire [12:0] tmi_sbist_fail;
wire [70:0] tmi_scano;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ee_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_above(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input valid_i,
output [31:0] r,
output reg valid_o
);
reg r_one;
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= valid_i;
case({a[31], b[31]})
2'b00: r_one <= a[30:0] > b[30:0];
2'b01: r_one <= 1'b1;
2'b10: r_one <= 1'b0;
2'b11: r_one <= a[30:0] < b[30:0];
endcase
end
assign r = r_one ? 32'h3f800000: 32'h00000000;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v); template <typename A, typename B> ostream &operator<<(ostream &cout, pair<A, B> const &p) { return cout << ( << p.first << , << p.second << ) ; } template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v) { cout << [ ; for (int i = 0; i < v.size(); i++) { if (i) cout << , ; cout << v[i]; } return cout << ] ; } template <typename A, typename B> istream &operator>>(istream &cin, pair<A, B> &p) { cin >> p.first; return cin >> p.second; } mt19937_64 rng(std::chrono::steady_clock::now().time_since_epoch().count()); void usaco(string filename) { freopen((filename + .in ).c_str(), r , stdin); freopen((filename + .out ).c_str(), w , stdout); } const long double pi = 3.14159265358979323846; long long n, m, q, k, l, r, x, y, z; const long long template_array_size = 1e6 + 16318; long long a[template_array_size]; long long b[template_array_size]; long long c[template_array_size]; string second, t; long long ans = 0; string op[5005]; string val[5005]; pair<long long, long long> dep[5005]; map<string, long long> rev; long long dp[5005]; long long check(long long x, long long p, long long t) { if (x == -1) return t; if (dp[x] != -1) return dp[x]; if (op[x] == = ) return dp[x] = val[x][p] - 0 ; else if (op[x] == OR ) return dp[x] = check(dep[x].first, p, t) | check(dep[x].second, p, t); else if (op[x] == AND ) return dp[x] = check(dep[x].first, p, t) & check(dep[x].second, p, t); else return dp[x] = check(dep[x].first, p, t) ^ check(dep[x].second, p, t); } void solve(int tc = 0) { cin >> n >> m; string v; getline(cin, v); rev[ ? ] = -1; for (long long i = 0; i < n; i++) { vector<string> x; getline(cin, v); istringstream is(v); while (is >> v) { x.push_back(v); } rev[x[0]] = i; if (x.size() == 3) { op[i] = = ; val[i] = x[2]; } else { op[i] = x[3]; dep[i] = {rev[x[2]], rev[x[4]]}; } } string rmin = , rmax = ; for (long long i = 0; i < m; i++) { long long c0 = 0, c1 = 0; memset(dp, -1, sizeof(dp)); for (long long j = 0; j < n; j++) { c0 += check(j, i, 0); } memset(dp, -1, sizeof(dp)); for (long long j = 0; j < n; j++) { c1 += check(j, i, 1); } if (c0 == c1) { rmin += 0 ; rmax += 0 ; } else if (c0 < c1) { rmin += 0 ; rmax += 1 ; } else { rmin += 1 ; rmax += 0 ; } } cout << rmin << n << rmax << n ; } int main() { { ios_base::sync_with_stdio(false); } { cin.tie(NULL); } cout << setprecision(15) << fixed; int tc = 1; for (int t = 0; t < tc; t++) solve(t); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int i, j, n, ans = 0, k1, k2; cin >> n; long long int arr[n]; vector<vector<long long int> > vec(26); for (i = 0; i < n; i++) { cin >> arr[i]; vec[arr[i] - 1].push_back(i); } long long int dp1[n][26], dp2[n][26]; for (i = 0; i < n; i++) for (j = 0; j < 26; j++) { dp1[i][j] = 0; dp2[i][j] = 0; } dp1[0][arr[0] - 1]++; for (i = 1; i < n; i++) { for (j = 0; j < 26; j++) if (arr[i] == j + 1) dp1[i][j] += dp1[i - 1][j] + 1; else dp1[i][j] += dp1[i - 1][j]; } dp2[n - 1][arr[n - 1] - 1]++; for (i = n - 2; i >= 0; i--) { for (j = 0; j < 26; j++) if (arr[i] == j + 1) dp2[i][j] += dp2[i + 1][j] + 1; else dp2[i][j] += dp2[i + 1][j]; } for (i = 0; i < 26; i++) { long long int dd = vec[i].size(); ans = max(ans, dd); } for (i = 0; i < 26; i++) { for (k1 = 0; k1 < vec[i].size(); k1++) { for (k2 = k1; k2 < vec[i].size(); k2++) { long long int d1 = vec[i][k1], d2 = vec[i][k2]; for (j = 0; j < 26; j++) if (i != j) ans = max(ans, k2 - k1 + 1 + 2 * min(dp1[d1][j], dp2[d2][j])); } } } cout << ans << endl; } return 0; }
|
`include "../../../rtl/verilog/gfx/gfx_clip.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
module clip_bench();
parameter point_width = 16;
reg clk_i;
reg rst_i;
reg clipping_enable_i;
reg zbuffer_enable_i;
reg [31:2] zbuffer_base_i;
reg [point_width-1:0] target_size_x_i;
reg [point_width-1:0] target_size_y_i;
//clip pixels
reg [point_width-1:0] clip_pixel0_x_i;
reg [point_width-1:0] clip_pixel0_y_i;
reg [point_width-1:0] clip_pixel1_x_i;
reg [point_width-1:0] clip_pixel1_y_i;
// from raster
reg [point_width-1:0] raster_pixel_x_i;
reg [point_width-1:0] raster_pixel_y_i;
reg [point_width-1:0] raster_u_i;
reg [point_width-1:0] raster_v_i;
reg [31:0] flat_color_i;
reg raster_write_i;
wire ack_o;
// from cuvz
reg [point_width-1:0] cuvz_pixel_x_i;
reg [point_width-1:0] cuvz_pixel_y_i;
reg signed [point_width-1:0] cuvz_pixel_z_i;
reg [point_width-1:0] cuvz_u_i;
reg [point_width-1:0] cuvz_v_i;
reg [7:0] cuvz_a_i;
reg [31:0] cuvz_color_i;
reg cuvz_write_i;
// Interface against wishbone master (reader)
reg z_ack_i;
wire [31:2] z_addr_o;
reg [31:0] z_data_i;
wire [3:0] z_sel_o;
wire z_request_o;
reg wbm_busy_i;
//to render
wire [point_width-1:0] pixel_x_o;
wire [point_width-1:0] pixel_y_o;
wire [point_width-1:0] pixel_z_o;
wire [point_width-1:0] u_o;
wire [point_width-1:0] v_o;
reg [point_width-1:0] bezier_factor0_i;
reg [point_width-1:0] bezier_factor1_i;
wire [point_width-1:0] bezier_factor0_o;
wire [point_width-1:0] bezier_factor1_o;
wire [31:0] color_o;
wire write_o;
reg ack_i;
initial begin
$dumpfile("clip.vcd");
$dumpvars(0,clip_bench);
// init values
clk_i = 0;
rst_i = 1;
cuvz_write_i = 0;
raster_write_i = 0;
clipping_enable_i = 0;
clip_pixel0_x_i = 0;
clip_pixel0_y_i = 0;
clip_pixel1_x_i = 10;
clip_pixel1_y_i = 10;
raster_pixel_x_i = 0;
raster_pixel_y_i = 0;
cuvz_pixel_x_i = 0;
cuvz_pixel_y_i = 0;
cuvz_pixel_z_i = -12;
cuvz_a_i = 0;
bezier_factor0_i = 0;
bezier_factor1_i = 0;
wbm_busy_i = 0;
zbuffer_enable_i = 1;
zbuffer_base_i = 32'h33000000;
target_size_x_i = 100;
target_size_y_i = 100;
z_data_i = 32'h80008000;
ack_i = 0;
flat_color_i = 0;
cuvz_color_i = 1;
//timing
#4 rst_i = 0;
#4 cuvz_write_i = 1;
#2 cuvz_write_i = 0;
#10 cuvz_write_i = 1;
cuvz_pixel_x_i = 20;
cuvz_pixel_y_i = 20;
cuvz_pixel_z_i = 12;
#2 cuvz_write_i = 0;
#10 raster_write_i = 1;
clipping_enable_i = 1;
raster_pixel_x_i = 20;
raster_pixel_y_i = 20;
#2 raster_write_i = 0;
// end sim
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
z_ack_i <= #1 z_request_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_clip clip(
.clk_i (clk_i),
.rst_i (rst_i),
.clipping_enable_i(clipping_enable_i),
.zbuffer_enable_i (zbuffer_enable_i),
.zbuffer_base_i (zbuffer_base_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.clip_pixel0_x_i (clip_pixel0_x_i),
.clip_pixel0_y_i (clip_pixel0_y_i),
.clip_pixel1_x_i (clip_pixel1_x_i),
.clip_pixel1_y_i (clip_pixel1_y_i),
.raster_pixel_x_i (raster_pixel_x_i),
.raster_pixel_y_i (raster_pixel_y_i),
.raster_u_i (raster_u_i),
.raster_v_i (raster_v_i),
.flat_color_i (flat_color_i),
.raster_write_i (raster_write_i),
.cuvz_pixel_x_i (cuvz_pixel_x_i),
.cuvz_pixel_y_i (cuvz_pixel_y_i),
.cuvz_pixel_z_i (cuvz_pixel_z_i),
.cuvz_u_i (cuvz_u_i),
.cuvz_v_i (cuvz_v_i),
.cuvz_a_i (cuvz_a_i),
.cuvz_color_i (cuvz_color_i),
.cuvz_write_i (cuvz_write_i),
.ack_o (ack_o),
.z_ack_i (z_ack_i),
.z_addr_o (z_addr_o),
.z_data_i (z_data_i),
.z_sel_o (z_sel_o),
.z_request_o (z_request_o),
.wbm_busy_i (wbm_busy_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_z_o (pixel_z_o),
.u_o (u_o),
.v_o (v_o),
.bezier_factor0_i (bezier_factor0_i),
.bezier_factor1_i (bezier_factor1_i),
.bezier_factor0_o (bezier_factor0_o),
.bezier_factor1_o (bezier_factor1_o),
.color_o (color_o),
.write_o (write_o),
.ack_i (ack_i)
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr72(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [71:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(ena) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:26];
word[24] <= word[25] ^ word[0];
word[23:19] <= word[24:20];
word[18] <= word[19] ^ word[0];
word[17:0] <= word[18:1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int x, long long int y) { return y == 0 ? x : gcd(y, x % y); } int main() { long long int a; cin >> a; if (a > 2) { if (a * a % 2) cout << (a * a - 1) / 2 << << (a * a + 1) / 2; else cout << (a * a / 2 - 2) / 2 << << (a * a / 2 + 2) / 2; } else { cout << -1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } bool isprime(int n) { for (int i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } int main() { int n; scanf( %d , &n); int ans = 0; if (n <= 3) ans = 1; else if (n % 2 == 0) ans = 2; else if (isprime(n)) ans = 1; else if (isprime(n - 2)) ans = 2; else ans = 3; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const long long LINF = 4000000000000000000LL; const double eps = 1e-9; void prepare() {} int a, n; int day[10000008]; void read() { scanf( %d%d , &a, &n); } void solve() { read(); for (int i = 1; i * i < a + n; i++) { int ii = i * i; for (int j = ii; j < a + n; j += ii) day[j] = i * i; } long long res = 0; for (int i = a; i < a + n; i++) res += i / day[i]; cout << res << endl; } int main() { prepare(); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_M_V
`define SKY130_FD_SC_LP__HA_M_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_m (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_m (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_M_V
|
#include <bits/stdc++.h> static const int N = 1 << 17; struct Fenwick { int n; int t[N * 4]; void set(int n) { this->n = n; } void add(int x, int v) { for (int i = x; i <= n; i += (i & -i)) t[i] += v; } void clear(int x) { for (int i = x; i <= n; i += (i & -i)) t[i] = 0; } int query(int x) { int ans = 0; for (int i = x; i > 0; i -= (i & -i)) ans += t[i]; return ans; } int query(int l, int r) { return query(r) - query(l - 1); } } fenwick; int readInt() { int x = 0, f = 1; int c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return x * f; } struct node { long long x, R, l, r, q; bool operator<(node const& o) const { return R < o.R; } } s[N]; bool cmp(const node& a, const node& b) { return a.q < b.q; } long long ans; int n, k, cc; long long d[N * 4]; void merge(int l, int r) { if (l == r) return; int m = (l + r) >> 1; merge(l, m); merge(m + 1, r); int st = m + 1, e = m; for (int i = l; i <= m; ++i) { while (e < r && s[e + 1].q <= s[i].q + k) { ++e; fenwick.add(s[e].x, +1); } while (st <= e && s[st].q < s[i].q - k) { fenwick.add(s[st].x, -1); ++st; } ans += fenwick.query(s[i].l, s[i].r); } for (int i = m + 1; i <= r; ++i) fenwick.clear(s[i].x); std::inplace_merge(s + l, s + m + 1, s + r + 1, cmp); } int solve() { n = readInt(); k = readInt(); cc = 0; for (int i = 1; i <= n; ++i) { s[i].x = readInt(); s[i].R = readInt(); s[i].q = readInt(); d[cc++] = s[i].x; d[cc++] = s[i].x - s[i].R; d[cc++] = s[i].x + s[i].R; } std::sort(d, d + cc); cc = std::unique(d, d + cc) - d; for (int i = 1; i <= n; ++i) { s[i].l = std::lower_bound(d, d + cc, s[i].x - s[i].R) - d; s[i].r = std::lower_bound(d, d + cc, s[i].x + s[i].R) - d; s[i].x = std::lower_bound(d, d + cc, s[i].x) - d; ++s[i].l; ++s[i].r; ++s[i].x; } std::sort(s + 1, s + n + 1); fenwick.set(cc); ans = 0; merge(1, n); printf( %lld n , ans); return 0; } int main(int argc, char* argv[]) { solve(); }
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; const int N=4e2+2,p=998244353; vector<int> lj[N]; int dis[N][N],dl[N],ans[N][N],rd[N][N],cnt[N],pre[N][N],lb[N*3][2]; int n,m,s,t,i,j,tou,wei,x,y,r; bool ed[N]; int main() { scanf( %d%d ,&n,&m); for (i=1;i<=m;i++) scanf( %d%d ,&x,&y),lj[lb[i][0]=x].push_back(lb[i][1]=y),lj[y].push_back(x); for (i=1;i<=m;i++) lb[i+m][0]=lb[i][1],lb[i+m][1]=lb[i][0];m<<=1; for (s=1;s<=n;s++) { dis[s][dl[tou=wei=1]=s]=rd[s][s]=1; while (tou<=wei) for (auto v:lj[x=dl[tou++]]) if (!dis[s][v]) dis[s][dl[++wei]=v]=dis[s][pre[s][v]=x]+(rd[s][v]=1); else if (dis[s][v]==dis[s][x]+1) ++rd[s][v]; } for (s=1;s<=n;s++) { for (t=1;t<s;t++) printf( %d ,ans[s][t]); //for (i=1;i<=n;i++) printf( %d: pre%d dis%d rd%d n ,i,pre[i],dis[i],rd[i]); for (t=s;t<=n;t++) { for (x=t;x!=s&&rd[s][x]<=1;x=pre[s][x]); if (x!=s) {printf( 0 );continue;} for (x=t;x!=s;x=pre[s][x]) ed[x]=1;r=1; for (i=1;i<=m;i++) if (dis[s][lb[i][0]]+1==dis[s][lb[i][1]]&&dis[t][lb[i][0]]+1==dis[t][lb[i][1]]) ++cnt[lb[i][1]]; //if (s==1&&t==1) for (i=1;i<=n;i++) printf( %d%c ,cnt[i],i==n?10:32); for (i=1;i<=n;i++) if (!ed[i]&&i!=s) r=(ll)r*cnt[i]%p; memset(cnt,0,sizeof(cnt)); for (x=t;x!=s;x=pre[s][x]) ed[x]=0; ans[t][s]=r;printf( %d ,r); }puts( ); } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1); long long powm(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return res; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } const long long maxn = 2 * 1e5 + 10; map<long long, long long> dif; void solve() { long long n; cin >> n; long long a[n + 2]; for (long long i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (long long i = 2; i <= n; i++) { long long cur = a[i] - a[i - 1]; dif[cur]++; } if (dif.size() > 2) { cout << 0 << endl; } else if (n == 1) { cout << -1 << endl; } else if (n == 2) { if ((a[2] - a[1]) % 2 == 0 && a[2] != a[1]) { cout << 3 << endl; cout << a[1] - (a[2] - a[1]) << << a[1] + (a[2] - a[1]) / 2 << << a[2] + (a[2] - a[1]) << endl; } else if (a[1] == a[2]) { cout << 1 << endl; cout << a[1] << endl; } else { cout << 2 << endl; cout << a[1] - (a[2] - a[1]) << << a[2] + (a[2] - a[1]) << endl; } } else if (dif.size() == 2 && n > 1) { long long mx = 0, d = 1000000000, z = 0; vector<long long> s; for (auto i : dif) { if (i.first == 0) z = 1; if (mx <= i.second) { mx = i.second; d = min(d, i.first); } s.push_back(i.first); } if (z || dif[s[0]] < n - 2 || s[1] % 2 != 0 || (s[1] % 2 == 0 && s[1] / 2 != s[0])) cout << 0 << endl; else { for (long long i = 2; i <= n; i++) { if (a[i] - a[i - 1] != d) { if ((a[i] - a[i - 1]) > d && (a[i] - a[i - 1]) % 2 == 0 && (a[i] - a[i - 1]) / 2 == d) { cout << 1 << endl; cout << a[i - 1] + d << endl; } else { cout << 0 << endl; break; } } } } } else if (dif.size() == 1) { long long d = 0; for (auto i : dif) { d = i.first; } if (d) { cout << 2 << endl; cout << a[1] - (a[2] - a[1]) << << a[n] + (a[2] - a[1]) << endl; } else { cout << 1 << endl; cout << a[1] << endl; } } else cout << 0 << endl; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t = 1; for (long long i = 1; i <= t; i++) { solve(); } return 0; }
|
module SPW_ULIGHT_FIFO(
input FPGA_CLK1_50,
input [1:0] KEY,
input din_a,
input sin_a,
//input din_b,
//input sin_b,
output dout_a,
output sout_a,
//output dout_b,
//output sout_b,
//////////// LED ////////////
/* 3.3-V LVTTL */
output [7:0] LED
);
wire reset_spw_n_b;
wire top_auto_start;
wire top_link_start;
wire top_link_disable;
wire read_enable_rx;
wire f_full_rx;
wire f_empty_rx;
wire f_empty_tx;
wire f_full_tx;
wire [2:0] clock_sel;
wire [5:0] top_fsm_i;
wire clk_400_mhz;
wire clk_pll_mhz;
wire ppll_100_MHZ;
wire pll_tx_locked_export;
wire [8:0] datarx_out_flag;
wire [13:0] monitor_a;
wire top_tx_tick;
wire [7:0] top_tx_time;
wire [5:0] counter_fifotx;
wire [5:0] counter_fiforx;
wire top_tx_write;
wire [8:0] top_tx_data;
wire [7:0] time_out;
wire tick_out;
wire clk_250_sys;
assign LED[7:7] = pll_tx_locked_export;
ulight_fifo u0 (
.auto_start_external_connection_export (top_auto_start), // auto_start_external_connection.export
.clk_clk (FPGA_CLK1_50), // clk.clk
.clock_sel_external_connection_export (clock_sel), // clock_sel_external_connection.export
.data_flag_rx_external_connection_export (datarx_out_flag), // data_flag_rx_external_connection.export
.data_info_external_connection_export (monitor_a), // data_info_external_connection.export
.data_read_en_rx_external_connection_export (read_enable_rx), // data_read_en_rx_external_connection.export
.fifo_empty_rx_status_external_connection_export (f_empty_rx), // fifo_empty_rx_status_external_connection.export
.fifo_empty_tx_status_external_connection_export (f_empty_tx), // fifo_empty_tx_status_external_connection.export
.fifo_full_rx_status_external_connection_export (f_full_rx), // fifo_full_rx_status_external_connection.export
.fifo_full_tx_status_external_connection_export (f_full_tx), // fifo_full_tx_status_external_connection.export
.led_pio_test_external_connection_export (LED[4:0]), // led_pio_test_external_connection.export
.link_disable_external_connection_export (top_link_disable), // link_disable_external_connection.export
.link_start_external_connection_export (top_link_start), // link_start_external_connection.export
/*
.memory_mem_a (<connected-to-memory_mem_a>), // memory.mem_a
.memory_mem_ba (<connected-to-memory_mem_ba>), // .mem_ba
.memory_mem_ck (<connected-to-memory_mem_ck>), // .mem_ck
.memory_mem_ck_n (<connected-to-memory_mem_ck_n>), // .mem_ck_n
.memory_mem_cke (<connected-to-memory_mem_cke>), // .mem_cke
.memory_mem_cs_n (<connected-to-memory_mem_cs_n>), // .mem_cs_n
.memory_mem_ras_n (<connected-to-memory_mem_ras_n>), // .mem_ras_n
.memory_mem_cas_n (<connected-to-memory_mem_cas_n>), // .mem_cas_n
.memory_mem_we_n (<connected-to-memory_mem_we_n>), // .mem_we_n
.memory_mem_reset_n (<connected-to-memory_mem_reset_n>), // .mem_reset_n
.memory_mem_dq (<connected-to-memory_mem_dq>), // .mem_dq
.memory_mem_dqs (<connected-to-memory_mem_dqs>), // .mem_dqs
.memory_mem_dqs_n (<connected-to-memory_mem_dqs_n>), // .mem_dqs_n
.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
.memory_oct_rzqin (<connected-to-memory_oct_rzqin>), // .oct_rzqin
*/
.pll_0_locked_export (pll_tx_locked_export), // pll_0_locked.export
.pll_0_outclk0_clk (clk_400_mhz),
//.pll_0_outclk1_clk (clk_250_sys), // pll_0_outclk0.clk
.reset_reset_n (reset_spw_n_b), // reset.reset_n
.timecode_ready_rx_external_connection_export (tick_out), // timecode_ready_rx_external_connection.export
.timecode_rx_external_connection_export (time_out), // timecode_rx_external_connection.export
.timecode_tx_data_external_connection_export (top_tx_time), // timecode_tx_data_external_connection.export
.timecode_tx_enable_external_connection_export (top_tx_tick), // timecode_tx_enable_external_connection.export
.timecode_tx_ready_external_connection_export (top_tx_ready_tick), // timecode_tx_ready_external_connection.export
.write_data_fifo_tx_external_connection_export (top_tx_data), // write_data_fifo_tx_external_connection.export
.write_en_tx_external_connection_export (top_tx_write), // write_en_tx_external_connection.export
.fsm_info_external_connection_export (top_fsm_i), // fsm_info_external_connection.export
.counter_tx_fifo_external_connection_export (counter_fifotx), // counter_tx_fifo_external_connection.export
.counter_rx_fifo_external_connection_export (counter_fiforx) // counter_rx_fifo_external_connection.export
);
spw_ulight_con_top_x A_SPW_TOP(
.ppll_100_MHZ(ppll_100_MHZ),
.ppllclk(clk_pll_mhz),
.reset_spw_n_b(reset_spw_n_b),
//.clk_sys_250_mhz(clk_250_sys),
.top_sin(sin_a),
.top_din(din_a),
.top_auto_start(top_auto_start),
.top_link_start(top_link_start),
.top_link_disable(top_link_disable),
.top_tx_write(top_tx_write),
.top_tx_data(top_tx_data),
.top_tx_tick(top_tx_tick),
.top_tx_time(top_tx_time),
.read_rx_fifo_en(read_enable_rx),
.datarx_flag(datarx_out_flag),
.tick_out(tick_out),
.time_out(time_out),
.top_dout(dout_a),
.top_sout(sout_a),
.f_full(f_full_tx),
.f_empty(f_empty_tx),
.f_full_rx(f_full_rx),
.f_empty_rx(f_empty_rx),
.top_tx_ready_tick(top_tx_ready_tick),
.top_fsm(top_fsm_i),
//.data_info(data_a),
.counter_fifo_tx(counter_fifotx),
.counter_fifo_rx(counter_fiforx)
);
debounce_db db_system_spwulight_b(
.CLK(FPGA_CLK1_50),
.PB(KEY[1]),
.PB_state(reset_spw_n_b),
.PB_down(LED[5:5])
);
clock_reduce R_400_to_2_5_10_100_200_300MHZ(
.clk(clk_400_mhz),
.clock_sel(clock_sel),
.reset_n(pll_tx_locked_export),
.clk_reduced(clk_pll_mhz),
.clk_100_reduced(ppll_100_MHZ)
);
detector_tokens m_x(
.rx_din(dout_a),
.rx_sin(sout_a),
.rx_resetn(reset_spw_n_b),
.info(monitor_a)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback () ////
//// - Julius Baxter () ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom #(
parameter ADDR_WIDTH = 5,
parameter B3_BURST = 0
)
(
input wb_clk,
input wb_rst,
input [(ADDR_WIDTH + 2) - 1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o
);
reg [ADDR_WIDTH-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
default: wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if (B3_BURST) begin : gen_B3_BURST
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) |
(burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; vector<long long int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<long long int> pks; for (int i = 1; i < n - 1; i++) { if (a[i] > a[i - 1] && a[i] > a[i + 1]) pks.push_back(i); } long long int maxi = 0, l = 0; for (long long int i = 0; i <= n - k; i++) { long long int tmp1 = upper_bound(pks.begin(), pks.end(), i) - pks.begin(); long long int tmp2 = lower_bound(pks.begin(), pks.end(), i + k - 1LL) - pks.begin(); long long int cnt = tmp2 - tmp1; if (cnt > maxi) { maxi = cnt; l = i; } } cout << maxi + 1 << << l + 1 << endl; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode = 0;
// verilator lint_off LITENDIAN
reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [34:0] vec_wide;
// verilator lint_on LITENDIAN
reg [31:0] wrd0 [15:0];
wire [3:0] sel = 4'h3;
wire [31:0] selout = wrd0[sel];
// Must take LSBs into account in bit extract widths.
wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB
wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB
wire [3:0] sixfrom = 13;
wire [4:0] sixfrom2 = 16;
wire sixtext = sixt[sixfrom];
wire sixtext2 = sixt2[sixfrom2];
// Non-power of 2 memory overwriting checks
reg [2:0] np2_mem [5:0] /*verilator public*/;
reg [2:0] np2_guard [7:6] /*verilator public*/;
integer i;
always @ (posedge clk) begin
if (_mode!=0) begin
wrd0[0] = 32'h1;
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
mem_narrow[i] = i[7:0];
mem_wide[i] = {i[7:0],70'hfeed};
end
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_narrow[i] !== i[7:0]) $stop;
if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop;
end
//
vec_wide <= 0;
//
np2_guard[6] = 0;
np2_guard[7] = 0;
//
$write("selout %b %b %b\n", selout, sixtext, sixtext2);
end
if (_mode == 1) begin
_mode <= 2;
//
i=0;
mem_dly_narrow[0] <= ~i[7:0];
mem_dly_wide[0] <= {~i[7:0],70'hface};
i=1;
mem_dly_narrow[i] <= ~i[7:0];
mem_dly_wide[i] <= {~i[7:0],70'hface};
//
for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR
// verilator lint_off width
np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB
// verilator lint_on width
if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop;
end
// verilator lint_off SELRANGE
if (np2_mem[6] !== np2_mem[7]) begin
$write("Mem[6]!=Mem[7] during randomize...\n");
//$stop; // Random value, so this can happen
end
// verilator lint_on SELRANGE
//if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's
//
vec_wide[32:31] <= 2'b11;
vec_wide[34] <= 1'b1;
$display("%x",vec_wide);
end
if (_mode == 2) begin
_mode <= 3;
//
for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_dly_narrow[i] !== ~i[7:0]) $stop;
if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop;
end
//
//$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]);
if (vec_wide != {4'b101_1,31'd0}) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); return x * f; } int n, m; vector<int> G[20], G2[20]; int low[20], dfn[20]; int cur; bool tarjan(int u, int fa) { bool flg = 0; low[u] = dfn[u] = ++cur; bool flg2 = 1; for (auto v : G2[u]) { if (!dfn[v]) { if (!tarjan(v, u)) flg2 = 0; low[u] = min(low[u], low[v]); if (dfn[v] == low[v]) flg2 = 0; } else if (v != fa || flg) low[u] = min(low[u], dfn[v]); else flg = 1; } return flg2; } vector<pair<int, int> > del; int curcnt; int ans = 0x3f3f3f3f; vector<int> Gans[20]; void delete_edge(int x) { if (!x) return; if (G2[x].empty()) return; int rrrnd = (rand() % G2[x].size() + G2[x].size()) % G2[x].size(); int y = G2[x][rrrnd]; del.emplace_back(x, y); G2[x].erase(find(G2[x].begin(), G2[x].end(), y)); G2[y].erase(find(G2[y].begin(), G2[y].end(), x)); memset(low, 0, sizeof low); memset(dfn, 0, sizeof dfn); cur = 0; if (!tarjan(1, -1)) { Ret: G2[x].push_back(y); G2[y].push_back(x); del.pop_back(); return; } for (int i = 1; i <= n; i++) if (!dfn[i]) goto Ret; curcnt--; if (curcnt < ans) { ans = curcnt; for (int i = 1; i <= n; i++) Gans[i] = G2[i]; } } void add_edge(int x) { if (del.empty()) return; G2[del[x].first].push_back(del[x].second); G2[del[x].second].push_back(del[x].first); del.erase(del.begin() + x); curcnt++; } int main() { srand(19260817); int stt = clock(); n = read(), m = read(); for (int i = 1, x, y; i <= m; i++) { x = read(), y = read(); G[x].push_back(y); G[y].push_back(x); } curcnt = ans = m; for (int i = 1; i <= n; i++) Gans[i] = G[i]; const int max_time = 1950; for (int _ = 1; _ <= 1000; _++) { for (int i = 1; i <= n; i++) G2[i] = G[i]; curcnt = m; for (int __ = 1; __ <= 1000; __++) { if (rand() % 4) delete_edge((rand() % n + n) % n + 1); else if (!del.empty()) { add_edge(rand() % del.size()); } } if (clock() - stt > max_time) break; } printf( %d n , ans); for (int i = 1; i <= n; i++) for (int j = 0; j < Gans[i].size(); j++) if (Gans[i][j] > i) printf( %d %d n , i, Gans[i][j]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int length; bool true_false; char S[100], aux, digits[4] = 123 ; cin >> S; length = strlen(S); for (int i = 0, x = 0, j; i < length; i += 2) { true_false = false; if (S[i] != digits[x]) { for (j = i + 2; j < length; j += 2) { if (S[i] != digits[x]) { if (S[j] == digits[x]) { aux = S[i]; S[i] = S[j]; S[j] = aux; i += 2; } else { if (j == length - 1) { true_false = true; } } } else { i += 2; } } } if (true_false) { x++; i -= 2; } } for (int i = 0, x = 0, j; i < length; i += 2) { if (S[i] != digits[x]) { x++; if (S[i] != digits[x]) { for (j = i + 2; j < length; j++) { if (S[j] == S[i]) { aux = S[j - 2]; S[j - 2] = S[i]; S[i] = aux; break; } } } } } cout << S << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 9; const int mod = 1e9 + 7; int32_t main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; if (n % m == 0) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, h; int bb[109][109][109]; int a[109], b[109], c[109][109]; int main() { scanf( %d%d%d , &n, &m, &h); for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= h; k++) { bb[i][j][k] = 1; } } } for (int i = 1; i <= m; i++) { scanf( %d , &a[i]); for (int j = 1; j <= n; j++) { for (int k = a[i] + 1; k <= h; k++) { bb[i][j][k] = 0; } } } for (int j = 1; j <= n; j++) { scanf( %d , &b[j]); for (int i = 1; i <= m; i++) { for (int k = b[j] + 1; k <= h; k++) { bb[i][j][k] = 0; } } } for (int j = 1; j <= n; j++) { for (int i = 1; i <= m; i++) { scanf( %d , &c[i][j]); if (c[i][j] == 0) { for (int k = 1; k <= h; k++) bb[i][j][k] = 0; } } } for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { for (int k = 2; k <= h; k++) { if (bb[i][j][k]) bb[i][j][1]++; } } } for (int j = 1; j <= n; j++) { for (int i = 1; i <= m; i++) { printf( %d , bb[i][j][1]); } printf( n ); } }
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 4761 2008-12-27 01:11:00Z jnaous $
//
// Module: small_fifo.v
// Project: UNET
// Description: small fifo with no fallthrough i.e. data valid after rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 11/2/09 -- Modified to have both prog threshold and almost full
///////////////////////////////////////////////////////////////////////////////
//suppose the one packet length smaller than 2048byte,when almost full is asserted,the fifo still can accept a full packet,than depth mast bigger than 256
`timescale 1ns/1ps
//almost full depth 8
module data_fifo
#(parameter WIDTH = 72,
parameter FIFO_DEPTH = 256,
parameter PROG_FULL_THRESHOLD = 8
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
output [5:0] data_count,
input reset,
input clk
);
reg [WIDTH-1:0] queue [256 : 0];
reg [7 : 0] rd_ptr;
reg [7 : 0] wr_ptr;
reg [7 : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == 255;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= 7;
assign empty = depth == 'h0;
assign data_count = depth;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == 255 && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; const int N = 300010; int a[N], f[N][21], la[21]; int main() { int n, q; scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); for (int j = 0; j <= 18; j++) if (!(a[i] & (1 << j))) for (int k = 0; k <= 18; k++) if (a[i] & (1 << k)) f[i][j] = max(f[i][j], f[la[k]][j]); for (int j = 0; j <= 18; j++) if (a[i] & (1 << j)) f[i][j] = i, la[j] = i; } for (int i = 1; i <= q; i++) { int l, r; scanf( %d%d , &l, &r); bool flag = false; for (int j = 0; j <= 18; j++) if ((a[l] & (1 << j)) && f[r][j] >= l) flag = true; if (flag) printf( Shi n ); else printf( Fou n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename... T> inline void inp(T &...args) { ((cin >> args), ...); } template <typename T> inline istream &operator>>(istream &in, vector<T> &a) { for (auto &x : a) in >> x; return in; } template <typename T, typename U> inline istream &operator>>(istream &in, pair<T, U> &a) { in >> a.first >> a.second; return in; } void solve(int &T) { long long int n, k; cin >> n >> k; vector<long long int> a(n); cin >> a; map<long long int, long long int> m; for (long long int i = (0); ((1) > 0 ? i < (n) : i > (n)); i += (1)) { m[a[i]]++; } set<long long int> s; for (long long int i = (0); ((1) > 0 ? i < (n) : i > (n)); i += (1)) { if (a[i] <= k) { long long int x = a[i]; long long int y = k - a[i]; if (m.count(y) and !s.count(min(x, y))) { if (x == y and m[y] >= 2) { s.insert(min(x, y)); } else s.insert(min(x, y)); } } } 11; int ok = 1; vector<long long int> ans(n, 0); for (long long int i = (0); ((1) > 0 ? i < (n) : i > (n)); i += (1)) { if (s.count(a[i])) { ans[i] = 1; if (k % 2 == 0 and a[i] == k / 2) { ans[i] = ok; ok ^= 1; } } } for (auto &X : ans) { cout << X << ; } cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; cin >> t; for (int i = 1; i <= t; i++) { if (0) cerr << Case # << i << n ; solve(i); } return 0; }
|
`timescale 1ps / 1ps
module main;
reg clk = 0;
always #200 clk = !clk;
reg [2:0] in = "111";
reg [1:0] out;
reg out_golden;
reg out_del;
integer seed = 1234;
integer rvec_file;
integer ret;
integer soe0 = 0;
initial begin
$sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
$dumpfile("test.vcd");
$dumpvars(0,main);
assert($urandom(seed));
`ifdef GENTEST
rvec_file = $fopen("../simple.rvec", "w");
`else
rvec_file = $fopen("../simple.rvec", "r");
`endif
if (rvec_file == 0) begin
$display("data_file handle was NULL");
$finish;
end
end
integer num_cycles = 0;
integer max_cycles = 10000;
always @ (posedge clk) begin
std::randomize(in);
if (num_cycles == max_cycles) begin
$display("SoE: %d\n",soe0);
$fclose(rvec_file);
$finish;
end
num_cycles = num_cycles + 1;
end
simple DUT (clk,in[0],in[1],in[2],out[0],out[1]);
always @(posedge clk) begin
// delay signal
#440 out_del = out[1];
end
always @ (posedge clk) begin
//#440
`ifdef GENTEST
// write output to generate golden result
$fwrite(rvec_file, "%b\n", out[1]);
`else
$fscanf(rvec_file, "%b\n", out_golden);
//if (out_del != out_golden) begin
if (out[1] != out_golden) begin
//$display("ERROR At time %t: out[0]=%b",$time,out[0]);
soe0 = soe0 + 1;
end
`endif
end // always @ (posedge clk)
always @(posedge clk) begin
//$display("At time %t: out[0]=%b,%b - out[1]=%b,%b",$time,out[0],out_golden[0],out[1],out_golden[1]);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << , ; err(++it, args...); } namespace fastIO { bool IOerror = 0; inline char nc() { static char buf[100000], *p1 = buf + 100000, *pend = buf + 100000; if (p1 == pend) { p1 = buf; pend = buf + fread(buf, 1, 100000, stdin); if (pend == p1) { IOerror = 1; return -1; } } return *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline void read(int &x) { char ch; while (blank(ch = nc())) ; if (IOerror) return; for (x = ch - 0 ; (ch = nc()) >= 0 && ch <= 9 ; x = x * 10 + ch - 0 ) ; } } // namespace fastIO using namespace fastIO; const double PI = acos(-1.0); const double eps = 1e-8; const int maxn = 2e6 + 7; const long long mod = 1e9 + 7; long long fac[maxn], finv[maxn]; long long qp(long long b, long long n) { long long r = 1; if (n <= 0) n += mod - 1; b %= mod; for (; n; n >>= 1, b = b * b % mod) if (n & 1) r = r * b % mod; return r; } long long pw[maxn]; void init() { fac[1] = fac[0] = finv[0] = 1; for (int i = 2; i < maxn; ++i) fac[i] = fac[i - 1] * i % mod; finv[maxn - 1] = qp(fac[maxn - 1], mod - 2); for (int i = maxn - 2; i >= 1; --i) finv[i] = finv[i + 1] * (i + 1) % mod; } long long C(int n, int m) { return n >= m ? fac[n] * finv[n - m] % mod * finv[m] % mod : 0; } long long A(int n, int m) { return n >= m ? fac[n] * finv[n - m] % mod : 0; } int main() { int n, m, a, b; cin >> n >> m >> a >> b; init(); long long res = 0; pw[0] = 1; for (int i = 1; i < maxn; ++i) pw[i] = pw[i - 1] * m % mod; for (int i = 0; i <= n - 2; ++i) { long long tmp = A(n - 2, i) * C(m - 1, i) % mod * pw[n - 2 - i] % mod * (i + 2) % mod * qp(n, n - i - 3) % mod; res = (res + tmp) % mod; } cout << res << endl; }
|
#include <bits/stdc++.h> char str1[200], str2[200]; char lenstr1, lenstr2; int dp1[200]; int dp2[200]; int got[200] = {0}; int twice; int twicep; int countc; int calel(int st) { int ite = st; int len = 1; for (int i = 0; i < lenstr2; i++) { int flag = 0; while (str1[st] != str2[i]) { st++; if (st == lenstr1) { len++; st = 0; if (flag) return 1; flag = 1; } } st++; if (st == lenstr1) { len++; st = 0; } } dp1[ite] = len; dp2[ite] = st; return 0; } int main() { int s1, s2; scanf( %d%d , &s1, &s2); scanf( %s%s , str1, str2); lenstr1 = strlen(str1); lenstr2 = strlen(str2); for (int i = 0; i < lenstr1; i++) if (calel(i)) { printf( 0 n ); return 0; } got[0] = 1; for (int i = 0;;) { int j = dp2[i]; if (got[j]) { twice = got[i] + dp1[i] - 1; twicep = j; break; } got[j] = got[i] + dp1[i] - 1; i = j; } if (twice >= s1) { countc = 0; int i, j; for (i = 0, j = 1; j <= s1;) { j += dp1[i] - 1; i = dp2[i]; countc++; } if (i == 0 && countc != 1) countc++; } else { countc = 0; int p1 = 1; for (int i = 0; i != twicep;) { p1 += dp1[i] - 1; i = dp2[i]; countc++; } int left = s1 - p1; int i = twicep; int single = 0; do { i = dp2[i]; single++; } while (i != twicep); int sinlen = twice - p1; countc += single * (left / sinlen); int p2 = p1 + left / sinlen * sinlen; for (i = twicep;;) { p2 += dp1[i] - 1; i = dp2[i]; if (p2 > s1) break; countc++; } if (i == 0) countc++; } printf( %d n , countc / s2); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 10, mod = 1e9 + 7; int fact[N], invfact[N]; inline int add(int x, int y) { x += y; if (x >= mod) x -= mod; return x; } inline int sub(int x, int y) { x -= y; if (x < 0) x += mod; return x; } inline int mul(int x, int y) { return (((long long)x) * y) % mod; } inline int powr(int a, long long b) { int x = 1 % mod; while (b) { if (b & 1) x = mul(x, a); a = mul(a, a); b >>= 1; } return x; } inline int inv(int a) { return powr(a, mod - 2); } void pre() { fact[0] = invfact[0] = 1; for (int i = 1; i < N; i++) fact[i] = mul(i, fact[i - 1]); invfact[N - 1] = inv(fact[N - 1]); for (int i = N - 2; i >= 1; i--) invfact[i] = mul(invfact[i + 1], i + 1); assert(invfact[1] == 1); } inline int C(int n, int k) { if (n < k || k < 0) return 0; return mul(fact[n], mul(invfact[k], invfact[n - k])); } int n, k; int C2[N + 10], A[N], E[N]; inline int getC2(int i) { if (i > k) return 0; return C2[i]; } int F[N][N]; int main() { pre(); cin >> n >> k; F[0][0] = 1; for (int i = 1; i <= n; i++) { F[i][0] = 1; cin >> A[i]; for (int j = 1; j <= i; j++) { F[i][j] = add(F[i - 1][j], mul(A[i], F[i - 1][j - 1])); } } C2[0] = 1; for (int i = 1; i <= n + 10; i++) C2[i] = mul(C2[i - 1], mul(k - i + 1, inv(i))); int invn = inv(n); int _div = 1; for (int i = 0; i <= n - 1; i++) { E[i] = mul(getC2(i + 1), _div); _div = mul(_div, invn); E[i] = mul(E[i], fact[i]); } int ans = 0; for (int i = 0; i <= n - 1; i++) { ans = add( ans, mul(F[n][i], mul(n - i, mul(powr(mod - 1, n - 1 - i), E[n - 1 - i])))); } ans = mul(ans, invn); cout << ans; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_xcvr_rx_if (
// jesd interface
input rx_clk,
input [ 3:0] rx_ip_sof,
input [31:0] rx_ip_data,
output reg rx_sof,
output reg [31:0] rx_data);
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg [ 3:0] rx_ip_sof_d = 'd0;
// dword may contain more than one frame per clock
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
rx_ip_sof_d <= rx_ip_sof;
if (rx_ip_sof != 4'h0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof_d;
if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data <= rx_ip_data;
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data <= {rx_ip_data[ 7:0], rx_ip_data_d[31: 8]};
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]};
end else if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]};
end else begin
rx_data <= 32'd0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, m, k, x[100039], y[100039], z, now, cur, flag[100039]; long long d[100039], ans = 1e15; struct yyy { int to; long long w; int z; } tmps; struct ljb { int head, h[100039]; yyy f[600039]; inline void add(int x, int y, long long z) { f[++head] = (yyy){y, z, h[x]}; h[x] = head; } } s; struct tree { int x, y, num; } f[100039]; inline bool cmp1(tree x, tree y) { return x.x < y.x; } inline bool cmp2(tree x, tree y) { return x.y < y.y; } inline bool cmp3(tree x, tree y) { return x.num < y.num; } inline int calc(int a, int b) { return ((abs(x[a] - x[b])) < (abs(y[a] - y[b])) ? (abs(x[a] - x[b])) : (abs(y[a] - y[b]))); } inline int calc1(int a, int b) { return abs(x[a] - x[b]) + abs(y[a] - y[b]); } struct ques { int to; long long w; bool operator<(const ques &x) const { return w > x.w; } } tmp; priority_queue<ques> q; int main() { memset(d, 0x3f, sizeof(d)); memset(s.h, -1, sizeof(s.h)); register int i; scanf( %d%d , &n, &n); scanf( %d%d%d%d , &x[0], &y[0], &x[n + 1], &y[n + 1]); ans = abs(x[0] - x[n + 1]) + abs(y[0] - y[n + 1]); for (i = 1; i <= n; i++) scanf( %d%d , &f[i].x, &f[i].y), x[i] = f[i].x, y[i] = f[i].y, f[i].num = i; sort(f + 1, f + n + 1, cmp1); for (i = 2; i <= n; i++) s.add(f[i - 1].num, f[i].num, calc(f[i - 1].num, f[i].num)), s.add(f[i].num, f[i - 1].num, calc(f[i - 1].num, f[i].num)); sort(f + 1, f + n + 1, cmp2); for (i = 2; i <= n; i++) s.add(f[i - 1].num, f[i].num, calc(f[i - 1].num, f[i].num)), s.add(f[i].num, f[i - 1].num, calc(f[i - 1].num, f[i].num)); for (i = 1; i <= n; i++) s.add(0, i, calc(0, i)); for (i = 1; i <= n; i++) s.add(i, n + 1, calc1(i, n + 1)); q.push((ques){0, 0}); d[0] = 0; while (!q.empty()) { tmp = q.top(); q.pop(); cur = s.h[tmp.to]; while (~cur) { tmps = s.f[cur]; if (d[tmps.to] > d[tmp.to] + tmps.w) d[tmps.to] = d[tmp.to] + tmps.w, q.push((ques){tmps.to, d[tmps.to]}); cur = tmps.z; } } printf( %lld n , ((d[n + 1]) < (ans) ? (d[n + 1]) : (ans))); }
|
#include <bits/stdc++.h> using namespace std; template <typename T> int size(T &a) { return (int)a.size(); } template <typename T> T sqr(T a) { return a * a; } const int INF = int(1e9); struct pt { int cnt; long long sumr; long long suml; long long f; int pr; int x; int lefm; int rim; pt *L, *R; }; const int MAXN = int(1e5); pt buf[MAXN * 2]; int sz = 0; pt *init(int x) { buf[sz].cnt = 1; buf[sz].L = buf[sz].R = NULL; buf[sz].x = x; buf[sz].pr = (rand() << 20) + rand(); buf[sz].suml = 0; buf[sz].sumr = 0; buf[sz].f = 0; buf[sz].lefm = buf[sz].rim = x; return &buf[sz++]; } int getcnt(pt *p) { return p == NULL ? 0 : p->cnt; } int getlefm(pt *p) { return p == NULL ? 2 * INF : p->lefm; } int getrim(pt *p) { return p == NULL ? -2 * INF : p->rim; } long long getf(pt *p) { return p == NULL ? 0 : p->f; } long long getsuml(pt *p) { return p == NULL ? 0 : p->suml; } long long getsumr(pt *p) { return p == NULL ? 0 : p->sumr; } void update(pt *&p) { if (p == NULL) return; p->cnt = getcnt(p->L) + getcnt(p->R) + 1; p->lefm = min(getlefm(p->L), p->x); p->rim = max(getrim(p->R), p->x); int n1 = getcnt(p->L); int n2 = getcnt(p->R); p->f = getf(p->L) + getf(p->R); p->f += getsumr(p->L) + (long long)n1 * (p->x - getrim(p->L)); p->f += getsuml(p->R) + (long long)n2 * (getlefm(p->R) - p->x); p->f += (long long)n1 * n2 * ((p->x - getrim(p->L)) + (getlefm(p->R) - p->x)); p->f += getsumr(p->L) * n2 + getsuml(p->R) * n1; p->suml = getsuml(p->L) + (p->x - p->lefm) + getsuml(p->R) + (long long)(n2 ? (getlefm(p->R) - p->lefm) : 0) * n2; p->sumr = getsumr(p->R) + (p->rim - p->x) + getsumr(p->L) + (long long)(n1 ? (p->rim - getrim(p->L)) : 0) * n1; } void merge(pt *a, pt *b, pt *&p) { if (a == NULL) { p = b; } else if (b == NULL) { p = a; } else if (a->pr < b->pr) { merge(a, b->L, b->L); p = b; update(p); } else { merge(a->R, b, a->R); p = a; update(p); } } void split(pt *t, pt *&a, pt *&b, int by) { if (t == NULL) { a = b = NULL; } else { if (t->x <= by) { split(t->R, t->R, b, by); a = t; update(a); } else { split(t->L, a, t->L, by); b = t; update(b); } } } int curx[MAXN]; void remove(pt *&t, int x) { pt *p, *q; pt *a, *b; split(t, p, q, x); split(p, a, b, x - 1); merge(a, q, t); } void insert(pt *&t, pt *i) { pt *p, *q; split(t, p, q, i->x); merge(p, i, t); merge(t, q, t); } long long query(pt *&t, int l, int r) { pt *p, *q, *a, *b; split(t, p, q, r); split(p, a, b, l - 1); long long res = getf(b); merge(a, b, t); merge(t, q, t); return res; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = (0); i < (n); ++i) cin >> curx[i]; pt *root = NULL; for (int i = (0); i < (n); ++i) { insert(root, init(curx[i])); } int q; cin >> q; for (int iter = (0); iter < (q); ++iter) { int t; cin >> t; if (t == 1) { int p, d; cin >> p >> d; --p; remove(root, curx[p]); curx[p] += d; insert(root, init(curx[p])); } else { int l, r; cin >> l >> r; cout << query(root, l, r) << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long n; vector<long> prec; int main() { ios_base::sync_with_stdio(0); prec.push_back(2); prec.push_back(7); prec.push_back(2); prec.push_back(3); prec.push_back(3); prec.push_back(4); prec.push_back(2); prec.push_back(5); prec.push_back(1); prec.push_back(2); cin >> n; cout << prec[n / 10] * prec[n % 10] << endl; cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> #define ALL(x) x.begin(), x.end() #define pb push_back #define db1(x) cout << #x << = << x << endl #define db2(x, y) cout << #x << = << x << , << #y << = << y << endl using namespace std; void localFileInput() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); #endif } typedef long long ll; typedef pair<int, int> pii; const ll mod = 1e9+7; const int N = 1e5+10; int n, m, a[N]; struct Node { int r; double p; void input() { scanf( %d%lf , &r, &p); } }b[N]; int r[N]; bool cmp(Node a , Node b) { return a.r < b.r; } void sol() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++ i) scanf( %d , &a[i]); for (int i = 1; i <= m; ++ i) b[i].input(); sort(b + 1, b + 1 + m, cmp); for (int i = 1; i <= m; ++ i) r[i] = b[i].r; int id = 0; for (int i = n; i >= 1; -- i) if(a[i] != i) { id = i; break; } if(id == 0) { puts( 1.000000 ); return ; } int st = lower_bound(r+1, r+1+m, id) - r; double ans = 1.0; for (int i = st; i <= m; ++ i) ans = ans * (1 - b[i].p); printf( %.6f n , 1-ans); } int main() { localFileInput(); int _; scanf( %d , &_); while(_ --) sol(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, inf = 0x3f3f3f3f; int main() { int a, b, h1, h2; while (cin >> h1 >> h2) { cin >> a >> b; int add = a * 12, de = b * 12, first = 8 * a; if (a <= b) { if (h1 + first >= h2) puts( 0 ); else puts( -1 ); continue; } int ans = 0; h1 += first; if (h1 >= h2) puts( 0 ); else { add -= de; ans += (h2 - h1) / add; if ((h2 - h1) % add) ans++; printf( %d n , ans); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> const int MAXN = 1001; using namespace std; char s[MAXN + 1], heidi[MAXN + 1]; int main() { int n, i, poz; scanf( %s , &s); n = strlen(s); i = 0; poz = 0; heidi[0] = h ; heidi[1] = e ; heidi[2] = i ; heidi[3] = d ; heidi[4] = i ; while (i < n && poz < 5) { if (s[i] == heidi[poz]) poz++; i++; } if (poz == 5) printf( YES ); else printf( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ar[500005]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , &ar[i]); } string s; cin >> s; long long gain = 0; long long loss = 0; long long bob = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == B ) { bob += ar[i]; } } long long ma = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == A ) { gain += ar[i]; } else { loss += ar[i]; } ma = max(ma, gain - loss); } gain = 0; loss = 0; for (int i = s.length() - 1; i >= 0; i--) { if (s[i] == A ) { gain += ar[i]; } else { loss += ar[i]; } ma = max(ma, gain - loss); } bob += ma; printf( %lld , bob); }
|
#include <bits/stdc++.h> using namespace std; char s1[5010], s2[5010]; int dp[5010][5010]; int main() { int i, j, ind, n, m, ans; cin >> n >> m; cin >> s1; cin >> s2; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { dp[i][j] = max(dp[i - 1][j], dp[i][j - 1]) - 1; if (s1[i - 1] == s2[j - 1]) { dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + 2); dp[i][j] = max(dp[i][j], 2); } } } ans = 0; for (i = 0; i <= n; i++) { for (j = 0; j <= m; j++) ans = max(ans, dp[i][j]); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int N, M; int p[1010]; long long X[1010]; int A[1010]; long long B[1010]; int U[2020]; int V[2020]; int up[1010]; bool chk[2020]; bool vst[1010]; bool chkv[1010]; long long mn[2020]; vector<int> adj[1010]; priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > pq; int par(int x) { if (x == p[x]) return x; return p[x] = par(p[x]); } void unite(int a, int b) { a = par(a); b = par(b); p[a] = b; } void add(int e) { int a = U[e], b = V[e]; assert(vst[a] || vst[b]); if (vst[b]) swap(a, b); if (vst[b]) { int t = par(b); while (t > 1) { B[1] += B[t]; p[t] = 1; t = up[t]; t = par(t); } t = par(a); while (t > 1) { B[1] += B[t]; p[t] = 1; t = up[t]; t = par(t); } } else { int t = par(a); vst[b] = true; up[b] = t; } chk[e] = true; } void dfs(int v) { X[v] += B[v]; for (int i : adj[v]) { X[i] += X[v]; dfs(i); } } void add_edges() { for (int i = 1; i <= N; i++) { adj[i].clear(); X[i] = 0; } for (int i = 2; i <= N; i++) { if (p[i] != i || !vst[i]) continue; adj[par(up[i])].push_back(i); } dfs(1); for (int i = 1; i <= M; i++) { if (chk[i]) continue; int a = U[i], b = V[i]; a = par(a); b = par(b); if (a == b) { chk[i] = true; continue; } if (vst[a]) { if (mn[i] > A[V[i]] - X[a] + 1) { mn[i] = A[V[i]] - X[a] + 1; pq.emplace(mn[i], i); } } if (vst[b]) { if (mn[i] > A[U[i]] - X[b] + 1) { mn[i] = A[U[i]] - X[b] + 1; pq.emplace(mn[i], i); } } } } int main() { int tc; scanf( %d , &tc); while (tc--) { scanf( %d%d , &N, &M); int mxv = 0; for (int i = 2; i <= N; i++) { scanf( %d , &A[i]); if (A[mxv] < A[i]) mxv = i; } B[1] = 0; for (int i = 2; i <= N; i++) scanf( %lld , &B[i]); for (int i = 1; i <= M; i++) scanf( %d%d , &U[i], &V[i]); while (pq.size()) pq.pop(); for (int i = 1; i <= N; i++) p[i] = i; for (int i = 1; i <= N; i++) { chkv[i] = vst[i] = false; X[i] = up[i] = 0; } for (int i = 1; i <= M; i++) chk[i] = false; vst[1] = true; long long ans = 0; for (int i = 1; i <= M; i++) mn[i] = 1LL << 60; add_edges(); while (pq.size()) { if (vst[mxv]) break; pair<long long, int> t = pq.top(); pq.pop(); if (t.first > mn[t.second] || chk[t.second]) continue; if (par(U[t.second]) == par(V[t.second])) { chk[t.second] = true; continue; } ans = max(ans, t.first); add(t.second); add_edges(); } assert(vst[mxv]); printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int j = 0; j < q; j++) { int n; long long int k; cin >> n >> k; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long int mi, ma; mi = a[0]; ma = a[n - 1]; long long int diff = ma - mi; if (diff % 2 == 0) diff = diff / 2; else diff = diff / 2 + 1; if (k >= diff) { cout << mi + k << endl; } else cout << -1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000009; const int MAXN = 128; const int MAXK = 4; struct TrieNode { int next[MAXK], fail; int danger; void init() { fail = -1; danger = 0; for (int i = 0; i < MAXK; ++i) next[i] = -1; } } T[MAXN]; int root, Top; void Init() { root = 0, Top = 1; T[root].init(); } int GetId(char ch) { switch (ch) { case A : return 0; case G : return 1; case C : return 2; case T : return 3; } } void TrieIns(char *s) { int i = 0; int p = root; while (s[i]) { int idx = GetId(s[i]); if (T[p].next[idx] == -1) { T[Top].init(); T[p].next[idx] = Top++; } p = T[p].next[idx]; i++; } T[p].danger = strlen(s); } void Build_AC_Automation() { int cur, tmp; queue<int> q; T[root].fail = root; T[root].danger = 0; q.push(root); while (!q.empty()) { cur = q.front(); q.pop(); for (int i = 0; i < MAXK; ++i) { if (T[cur].next[i] != -1) { tmp = T[cur].next[i]; if (cur == root) T[tmp].fail = root; else { T[tmp].fail = T[T[cur].fail].next[i]; T[tmp].danger = max(T[tmp].danger, T[T[tmp].fail].danger); } q.push(tmp); } else { if (cur == root) T[cur].next[i] = root; else T[cur].next[i] = T[T[cur].fail].next[i]; } } } } long long dp[1010][128][11]; int n, m; int main() { memset(dp, 0, sizeof(dp)); cin >> n >> m; Init(); for (int i = 0; i < m; ++i) { char str[20]; cin >> str; TrieIns(str); } Build_AC_Automation(); dp[0][0][0] = 1; for (int i = 0; i < n; ++i) { for (int j = 0; j < Top; ++j) { for (int k = 0; k <= 10; ++k) { if (dp[i][j][k] == 0) continue; for (int t = 0; t < MAXK; ++t) { int aa = T[j].next[t]; if (T[aa].danger > k) { dp[i + 1][aa][0] += dp[i][j][k]; dp[i + 1][aa][0] %= MOD; } else if (k + 1 <= 10) { dp[i + 1][aa][k + 1] += dp[i][j][k]; dp[i + 1][aa][k + 1] %= MOD; } } } } } long long ans = 0; for (int i = 0; i < Top; ++i) { ans = ans + dp[n][i][0]; ans %= MOD; } cout << ans % MOD << endl; }
|
//
// rom.v -- parallel flash ROM interface
//
module rom(clk, reset,
en, wr, size, addr,
data_out, wt,
ce_n, oe_n, we_n, rst_n, byte_n, a, d);
// internal interface signals
input clk;
input reset;
input en;
input wr;
input [1:0] size;
input [20:0] addr;
output reg [31:0] data_out;
output reg wt;
// flash ROM interface signals
output ce_n;
output oe_n;
output we_n;
output rst_n;
output byte_n;
output [19:0] a;
input [15:0] d;
reg [3:0] state;
reg a0;
// the following control signals are all
// either constantly asserted or deasserted
assign ce_n = 0;
assign oe_n = 0;
assign we_n = 1;
assign rst_n = 1;
assign byte_n = 1;
// the flash ROM is organized in 16-bit halfwords
// address line a0 is controlled by the state machine
// (this is necessary for word accesses)
assign a[19:1] = addr[20:2];
assign a[0] = a0;
// the state machine
always @(posedge clk) begin
if (reset == 1) begin
state <= 0;
wt <= 1;
end else begin
if (state == 0) begin
// wait for start of access
if (en == 1 && wr == 0) begin
state <= 1;
if (size[1] == 1) begin
// word access
a0 <= 0;
end else begin
// halfword or byte access
a0 <= addr[1];
end
end
end else
if (state == 6) begin
if (size[1] == 1) begin
// word access
// latch upper halfword
data_out[31:24] <= d[7:0];
data_out[23:16] <= d[15:8];
state <= 7;
a0 <= 1;
end else begin
// halfword or byte access
data_out[31:16] <= 16'h0000;
if (size[0] == 1) begin
// halfword access
data_out[15:8] <= d[7:0];
data_out[7:0] <= d[15:8];
end else begin
// byte access
data_out[15:8] <= 8'h00;
if (addr[0] == 0) begin
// even address
data_out[7:0] <= d[7:0];
end else begin
// odd address
data_out[7:0] <= d[15:8];
end
end
state <= 13;
wt <= 0;
end
end else
if (state == 12) begin
// word access (state is only reached in this case)
// latch lower halfword
data_out[15:8] <= d[7:0];
data_out[7:0] <= d[15:8];
state <= 13;
wt <= 0;
end else
if (state == 13) begin
// end of access
wt <= 1;
state <= 0;
end else begin
// wait for flash ROM access time to pass
state <= state + 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1005; const long long mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; cout << (n + 1) / 2 - 1; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> a(n); for (int &i : a) { cin >> i; } vector<vector<bool> > match(n + 1, vector<bool>(n + 1, false)); for (int i = 0, x, y; i < m; i++) { cin >> x >> y; x--; y--; match[x][y] = true; match[y][x] = true; } int ans = INT_MAX; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { for (int z = j + 1; z < n; z++) { if (match[i][j] && match[j][z] && match[z][i]) { ans = min(ans, a[i] + a[j] + a[z]); } } } } if (ans == INT_MAX) ans = -1; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1000000007; const long double PI = 3.14159265; long long int powerWithMod(long long int base, long long int exponent, long long int MODulus = LLONG_MAX) { long long int ansult = 1; base %= MODulus; while (exponent > 0) { if (exponent % 2 == 1) ansult = (ansult * base) % MODulus; exponent >>= 1; base = (base * base) % MODulus; } return ansult; } long long int gcdExtended(long long int a, long long int b, long long int *x, long long int *y) { cout << a << << b << << *x << << *y << n ; if (a == 0) { *x = 0, *y = 1; return b; } long long int x1, y1; long long int gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; cout << AFTER << a << << b << << *x << << *y << n ; return gcd; } long long int MODInverse(long long int a, long long int m) { long long int x, y; long long int g = gcdExtended(a, m, &x, &y); cout << g << << x << << y << n ; long long int ans = (x % m + m) % m; return ans; } using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long int n, a = 0, x, m = 0; cin >> n; for (int i = 1; i <= n; i++) cin >> x, a += x, m = max(x, m); cout << max(m, (a + n - 2) / (n - 1)) << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/30 20:05:27
// Design Name:
// Module Name: Mealy_FSM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mealy_FSM(
input Clk,
input reset,
input ain,
output reg [3:0] count,
output reg yout
);
reg [1:0] state, nextState;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
// update state
always @(posedge Clk) begin
if(reset) begin
state <= s0;
count <= 0;
end
else begin
state <= nextState;
if (nextState != state) count <= count + 1;
end
end
// compute nextState and yout
always @(ain or state or reset) begin
yout = 0;
case(state)
s0: begin
if (ain) begin
nextState <= s1;
end
else begin
nextState <= s0;
if (~reset) yout <= 1;
end
end
s1: begin
if (ain) beg
nextState <= s2;
end
else begin
nextState <= s1;
end
end
s2: begin
if (ain) begin
nextState <= s3;
end
else begin
nextState <= s2;
end
end
s3: begin
if (ain) begin
nextState <= s1;
yout <= 1;
end
else begin
nextState <= s3;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[2010], b[2010]; bool vis[2010]; char *p1, *p2, buf[100000]; int rd() { int x = 0, f = 1; char c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++); while (c < 48) { if (c == - ) f = -1; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++); } while (c > 47) { x = (((x << 2) + x) << 1) + (c ^ 48), c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++); } return x * f; } map<int, int> MP; int n; bool check(int x) { for (int i = 1; i <= n - x + 1; i++) { memset(vis, false, sizeof vis); bool flag = true; for (int j = 1; j < i; j++) { if (vis[a[j]]) { flag = false; } vis[a[j]] = true; } for (int j = i + x; j <= n; j++) { if (vis[a[j]]) { flag = false; } vis[a[j]] = true; } if (flag) { return true; } } return false; } int main() { n = rd(); for (int i = 1; i <= n; i++) { a[i] = rd(); b[i] = a[i]; } sort(b + 1, b + n + 1); b[0] = b[1] - 1; int cnt = 0; for (int i = 1; i <= n; i++) { if (b[i] != b[i - 1]) { MP[b[i]] = ++cnt; } } for (int i = 1; i <= n; i++) { a[i] = MP[a[i]]; } if (cnt == n) { puts( 0 ); return 0; } int ans = n; int l = 1, r = n; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else { l = mid + 1; } } cout << ans << endl; }
|
// spw_babasu_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module spw_babasu_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 1
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [31:0] h2f_WDATA, // .wdata
output wire [3:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [31:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
spw_babasu_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY) // .rready
);
spw_babasu_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 998244353; vector<long long int> prime; long long int n = 1000001; vector<bool> vis(n, true); void sieve() { vis[0] = vis[1] = false; for (long long int i = 2; i * i <= n; i++) if (vis[i]) for (long long int j = i * i; j <= n; j += i) vis[j] = false; for (long long int i = 2; i <= n; i++) if (vis[i]) prime.push_back(i); } bool check(long long int n, long long int k) { if (n < 2 * k) return false; if (k == 1) return vis[n]; if (k == 2) { if (n % 2) return vis[n - 2]; return true; } return true; } int32_t main() { sieve(); long long int n; cin >> n; for (auto it = lower_bound(prime.begin(), prime.end(), n); it != prime.end(); it++) { if (*it > ((n * (n - 1)) >> 1)) break; if (!check((*it) << 1, n)) continue; long long int m = *it; cout << m << endl; m -= n; for (long long int i = 1; i <= n; i++) { long long int z = i + 1; if (z > n) z = 1; cout << i << << z << endl; } long long int diff = 2, init = (n >> 1) + (n & 1); while (m--) { cout << init << << init + diff << endl; diff += 2; init--; } return 0; } cout << -1 ; return 0; }
|
module reg_wo_4burst(
input wire clk,
input wire [15:0] bus_ad, // raw mux data
input wire [18:0] my_a,
input wire [2:0] bus_a, // high address bits
input wire adv, // active high, so connect to !EIM_LBA
input wire rw, // low = write, high = read, so connect to EIM_RW
input wire cs, // active high, so connect to !EIM_CS[1]
output wire [63:0] reg_d,
output reg [15:0] rbk_d, // readback tri-state interface
output wire strobe // pulses one cycle after access is done
);
reg [63:0] bstate;
reg [2:0] bcount;
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
reg activated_d;
always @(posedge clk) begin
activated_d <= activated;
end
assign strobe = activated_d & !activated; // pulse on falling edge of activated
////// write path
always @(posedge clk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r} == my_a) ) begin
activated <= 1'b1;
bcount <= 3'b0;
end else if( !cs_r ) begin
activated <= 1'b0;
bcount <= 3'b0;
end else begin
activated <= activated;
// chip select is active, and we're beyond the address latch stage
if( bcount <= 3'b111 ) begin
bcount <= bcount + 3'b01;
end else begin
bcount <= bcount;
end
end // else: !if( !cs_r )
end // always @ (posedge clk)
always @(posedge clk) begin
if( activated && !rw_r ) begin
case (bcount)
3'b00: begin
bstate[15:0] <= bus_ad_r;
end
3'b01: begin
bstate[31:16] <= bus_ad_r;
end
3'b10: begin
bstate[47:32] <= bus_ad_r;
end
3'b11: begin
bstate[63:48] <= bus_ad_r;
end
default: begin
bstate <= bstate;
end
endcase // case (bcount)
end else begin // if ( activated )
bstate <= bstate;
end // else: !if( activated )
end // always @ (posedge clk)
assign reg_d = bstate;
always @(activated or bcount or rw_r or bstate) begin
if( activated && rw_r ) begin
case (bcount) // bcount is delayed by one due to adr-to-oe turnaround provision
3'b0001: begin
rbk_d = bstate[15:0];
end
3'b010: begin
rbk_d = bstate[31:16];
end
3'b011: begin
rbk_d = bstate[47:32];
end
3'b100: begin
rbk_d = bstate[63:48];
end
default: begin
rbk_d = 16'hZZZZ;
end
endcase // case (bcount)
end else begin // if ( activated && rw )
rbk_d = 16'hZZZZ;
end // else: !if( activated && rw )
end
endmodule // reg_wo_4burst
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int m, n, a[100009], b[100009]; long long sa, sb; long long proca() { long long ans = 0; ans += sa; for (int(x) = (1); (x) < (n); ++(x)) { ans += min(sa, (long long)b[x]); } return ans; } long long procb() { long long ans = 0; ans += sb; for (int(x) = (1); (x) < (m); ++(x)) ans += min(sb, (long long)a[x]); return ans; } int main() { while (scanf( %d%d , &m, &n) == 2) { sa = sb = 0; for (int(x) = (0); (x) < (m); ++(x)) { scanf( %d , &a[x]); sa += a[x]; } for (int(x) = (0); (x) < (n); ++(x)) { scanf( %d , &b[x]); sb += b[x]; } sort(a, a + m); reverse(a, a + m); sort(b, b + n); reverse(b, b + n); cout << min(proca(), procb()) << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2b (
VPWR,
VGND,
X ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long a[200005]; unordered_map<long long, long long> f, done; vector<long long> v; int main() { std::ios_base::sync_with_stdio(0); cin.tie(0); long long n; long long ans = 0; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; f[a[i]]++; } for (int i = 1; i <= n; i++) { if (f[i] == 0) { ans++; v.push_back(i); } } cout << ans << endl; long long ptr = 0; for (long long i = 1; i <= n; i++) { if (f[a[i]] == 1) { if (done[a[i]] == 0) { cout << a[i] << ; done[a[i]]++; } else { cout << v[ptr] << ; ptr++; } } else { if (v[ptr] > a[i] && done[a[i]] == 0) { cout << a[i] << ; f[a[i]]--; done[a[i]]++; } else { f[a[i]]--; cout << v[ptr] << ; done[v[ptr]]++; ptr++; } } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__AND2_PP_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 * 1000 + 1000; int arr[MAXN]; vector<int> pt[MAXN]; int mrk[MAXN]; int32_t main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; for (int i = 0; i < n; i++) pt[arr[i]].push_back(i); int cnt = n; int cnt_2 = 1; while (cnt) { if (pt[1].size() == 0) { cout << -1 << endl; return 0; } int pt_2 = 1; while (pt[pt_2].size() > 0) { mrk[pt[pt_2][pt[pt_2].size() - 1]] = cnt_2; pt[pt_2].pop_back(); cnt--; pt_2++; } cnt_2++; } cout << *max_element(mrk, mrk + n) << endl; for (int i = 0; i < n; i++) cout << mrk[i] << ; cout << endl; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7407 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w33,
w1024,
w991,
w528,
w463,
w7408,
w7407;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w32 = w1 << 5;
assign w33 = w1 + w32;
assign w463 = w991 - w528;
assign w528 = w33 << 4;
assign w7407 = w7408 - w1;
assign w7408 = w463 << 4;
assign w991 = w1024 - w33;
assign o_data0 = w7407;
//multiplier_block area estimate = 6802.48789710589;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void solve() { long long int l, r; cin >> l >> r; long long int mposs = (r - 1) >> 1; if (r - mposs >= l) cout << mposs << n ; else cout << r % l << n ; } signed main() { int t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 5; int n; int fa[N], r[N]; int rt[N], ls[N * 30], rs[N * 30], siz[N * 30], tot; long long sum[N * 30], ans; void update(int &rt, int l, int r, int p) { if (!rt) rt = ++tot; if (l == r) { siz[rt] = 1, sum[rt] = p; return; } int mid = (l + r) >> 1; if (p <= mid) update(ls[rt], l, mid, p); else update(rs[rt], mid + 1, r, p); siz[rt] = siz[ls[rt]] + siz[rs[rt]]; sum[rt] = sum[ls[rt]] + sum[rs[rt]]; } int merge(int x, int y) { if (!x || !y) return x | y; ans -= sum[ls[x]] * siz[rs[x]] + sum[ls[y]] * siz[rs[y]]; ls[x] = merge(ls[x], ls[y]); rs[x] = merge(rs[x], rs[y]); ans += sum[ls[x]] * siz[rs[x]]; siz[x] += siz[y]; sum[x] += sum[y]; return x; } inline int findf(int x) { return x == fa[x] ? x : fa[x] = findf(fa[x]); } void unify(int x, int y) { x = findf(x), y = findf(y); fa[y] = x; ans -= sum[rt[x]] * x + sum[rt[y]] * y; rt[x] = merge(rt[x], rt[y]); ans += sum[rt[x]] * x; r[x] = r[y]; } int main() { scanf( %d , &n); for (int i = 1; i <= 400000; i++) fa[i] = i, r[i] = i; for (int i = 1, a, b; i <= n; i++) { scanf( %d%d , &a, &b); int p = rt[a] ? r[findf(a)] + 1 : a; ans -= 1ll * a * b; ans += 1ll * p * b; update(rt[p], 1, n, b); if (rt[p - 1]) unify(p - 1, p); if (rt[p + 1]) unify(p, p + 1); printf( %lld n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_V
|
/************************************************
The Verilog HDL code example is from the book
Computer Principles and Design in Verilog HDL
by Yamin Li, published by A JOHN WILEY & SONS
************************************************/
module CPU (clk,reset,pc,inst,Addr,Data_I,Data_O,WE,ACK,STB,debug_next_pc); // cpu kbd i/o
input clk, reset; // clock and reset
input [31:0] inst; // instruction
input [31:0] Data_I; // load data
input ACK;
output [31:0] pc; // program counter
output [31:0] Addr; // mem or i/o addr
output [31:0] Data_O; // store data
output WE; // data memory write
output STB;
// debug signals
output [31: 0] debug_next_pc;
// control signals
reg wreg; // write regfile
reg wmem,rmem; // write/read memory
reg [31:0] alu_out; // alu output
reg [4:0] dest_rn; // dest reg number
reg [31:0] next_pc; // next pc
wire [31:0] pc_plus_4 = pc + 4; // pc + 4
// instruction format
wire [05:00] opcode = inst[31:26];
wire [04:00] rs = inst[25:21];
wire [04:00] rt = inst[20:16];
wire [04:00] rd = inst[15:11];
wire [04:00] sa = inst[10:06];
wire [05:00] func = inst[05:00];
wire [15:00] imm = inst[15:00];
wire [25:00] addr = inst[25:00];
wire sign = inst[15];
wire [31:00] offset = {{14{sign}},imm,2'b00};
wire [31:00] j_addr = {pc_plus_4[31:28],addr,2'b00};
// instruction decode
wire i_add = (opcode == 6'h00) & (func == 6'h20); // add
wire i_sub = (opcode == 6'h00) & (func == 6'h22); // sub
wire i_and = (opcode == 6'h00) & (func == 6'h24); // and
wire i_or = (opcode == 6'h00) & (func == 6'h25); // or
wire i_xor = (opcode == 6'h00) & (func == 6'h26); // xor
wire i_sll = (opcode == 6'h00) & (func == 6'h00); // sll
wire i_srl = (opcode == 6'h00) & (func == 6'h02); // srl
wire i_sra = (opcode == 6'h00) & (func == 6'h03); // sra
wire i_jr = (opcode == 6'h00) & (func == 6'h08); // jr
wire i_addi = (opcode == 6'h08); // addi
wire i_andi = (opcode == 6'h0c); // andi
wire i_ori = (opcode == 6'h0d); // ori
wire i_xori = (opcode == 6'h0e); // xori
wire i_lw = (opcode == 6'h23); // lw
wire i_sw = (opcode == 6'h2b); // sw
wire i_beq = (opcode == 6'h04); // beq
wire i_bne = (opcode == 6'h05); // bne
wire i_lui = (opcode == 6'h0f); // lui
wire i_j = (opcode == 6'h02); // j
wire i_jal = (opcode == 6'h03); // jal
// pc
reg [31:0] pc;
always @ (posedge clk or posedge reset) begin
if (reset) pc <= 0;
// slave is not ready, you stay here
else begin
if (STB)
pc <= ACK ? next_pc : pc;
else
pc <= next_pc;
end
end
// data written to register file
wire [31:0] data_2_rf = i_lw ? Data_I : alu_out;
// register file
reg [31:0] regfile [1:31]; // $1 - $31
wire [31:0] a = (rs==0) ? 0 : regfile[rs]; // read port
wire [31:0] b = (rt==0) ? 0 : regfile[rt]; // read port
always @ (posedge clk) begin
if (wreg && (dest_rn != 0)) begin
regfile[dest_rn] <= data_2_rf; // write port
end
end
// output signals
assign WE = wmem; // data memory write
assign Data_O = b; // data to store
assign Addr = alu_out; // memory address
assign STB = rmem | wmem;
// control signals, will be combinational circuit
always @(*) begin
alu_out = 0; // alu output
dest_rn = rd; // dest reg number
wreg = 0; // write regfile
wmem = 0; // write memory (sw)
rmem = 0; // read memory (lw)
next_pc = pc_plus_4;
case (1'b1)
i_add: begin // add
alu_out = a + b;
wreg = 1; end
i_sub: begin // sub
alu_out = a - b;
wreg = 1; end
i_and: begin // and
alu_out = a & b;
wreg = 1; end
i_or: begin // or
alu_out = a | b;
wreg = 1; end
i_xor: begin // xor
alu_out = a ^ b;
wreg = 1; end
i_sll: begin // sll
alu_out = b << sa;
wreg = 1; end
i_srl: begin // srl
alu_out = b >> sa;
wreg = 1; end
i_sra: begin // sra
alu_out = $signed(b) >>> sa;
wreg = 1; end
i_jr: begin // jr
next_pc = a; end
i_addi: begin // addi
alu_out = a + {{16{sign}},imm};
dest_rn = rt;
wreg = 1; end
i_andi: begin // andi
alu_out = a & {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_ori: begin // ori
alu_out = a | {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_xori: begin // xori
alu_out = a ^ {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_lw: begin // lw
alu_out = a + {{16{sign}},imm};
dest_rn = rt;
rmem = 1;
wreg = 1; end
i_sw: begin // sw
alu_out = a + {{16{sign}},imm};
wmem = 1; end
i_beq: begin // beq
if (a == b)
next_pc = pc_plus_4 + offset; end
i_bne: begin // bne
if (a != b)
next_pc = pc_plus_4 + offset; end
i_lui: begin // lui
alu_out = {imm,16'h0};
dest_rn = rt;
wreg = 1; end
i_j: begin // j
next_pc = j_addr; end
i_jal: begin // jal
alu_out = pc_plus_4;
wreg = 1;
dest_rn = 5'd31;
next_pc = j_addr; end
default: ;
endcase
wreg = STB ? wreg & ACK : wreg;
end
// debug signals
assign debug_next_pc = next_pc;
endmodule
|
module test;
// Test declaring the enum as a 3-bit logic.
enum reg [2:0] { rstate[8] } reg_enum;
enum bit [2:0] { bstate[8] } bit_enum;
enum logic [2:0] { lstate[8] } log_enum;
initial begin
if ($bits(reg_enum) != 3) begin
$display("FAILED -- $bits(reg_enum) == %0d", $bits(reg_enum));
$finish;
end
if ($bits(bit_enum) != 3) begin
$display("FAILED -- $bits(bit_enum) == %0d", $bits(bit_enum));
$finish;
end
if ($bits(log_enum) != 3) begin
$display("FAILED -- $bits(log_enum) == %0d", $bits(log_enum));
$finish;
end
if ($bits(rstate0) != 3) begin
$display("FAILED -- $bits(rstate0) == %0d", $bits(rstate0));
$finish;
end
if ($bits(bstate0) != 3) begin
$display("FAILED -- $bits(bstate0) == %0d", $bits(bstate0));
$finish;
end
if ($bits(lstate0) != 3) begin
$display("FAILED -- $bits(lstate0) == %0d", $bits(lstate0));
$finish;
end
if (rstate0 !== 3'b000 || bstate0 !== 3'b000 || lstate0 !== 3'b000) begin
$display("FAILED -- rstate0 == %b", rstate0);
$finish;
end
if (rstate4 !== 3'b100 || bstate4 !== 3'b100 || lstate4 !== 3'b100) begin
$display("FAILED -- rstate4 == %b", rstate4);
$finish;
end
if (rstate7 !== 3'b111 || bstate7 !== 3'b111 || lstate7 !== 3'b111) begin
$display("FAILED -- rstate7 == %b", rstate7);
$finish;
end
$display ("PASSED");
end
endmodule // test
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__EBUFN_PP_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_PP_BLACKBOX_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate defparam with list
//
module NameA ();
parameter ident0 = 12;
parameter ident1 = 20 ;
wire [31:0] value0 = ident0;
wire [31:0] value1 = ident1;
endmodule
module main ();
defparam main.testmodA.ident0 = 15; // Validate single val
defparam main.testmodB.ident1 = 16, // Validate list of vals
main.testmodB.ident0 = 17; // Validate single val
reg error;
NameA testmodA ();
NameA testmodB ();
initial
begin
error = 0;
# 1;
if(main.testmodA.value0 !== 15)
begin
error = 1;
$display("FAILED - defparam.v main.testmodA.value0 != 15");
end
# 1;
if(main.testmodA.value1 !== 20)
begin
error = 1;
$display("FAILED - defparam.v main.testmodA.value1 != 20");
end
# 1;
if(main.testmodB.value0 !== 17)
begin
error = 1;
$display("FAILED - defparam.v main.testmodB.value0 != 17");
end
# 1;
if(main.testmodB.value1 !== 16)
begin
error = 1;
$display("FAILED - defparam.v main.testmodB.value1 != 16");
end
# 1;
if(error == 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double f[100]; int k[100]; double cpw[100]; int N; double calc(int i) { return (1 - cpw[i] * f[i]) / (1 - cpw[i]); } int main() { cin >> N; int c; int highInc = 0; double P = 1; for (int i = 0; i < N; i++) { cin >> c; cpw[i] = f[i] = 1.0 - (c / 100.0); k[i] = 1; if (calc(i) > calc(highInc)) highInc = i; P *= (1 - f[i]); } double expval = 0; double oldP; for (int i = 1; i <= 300000; i++) { oldP = P; P *= calc(highInc); k[highInc]++; cpw[highInc] *= f[highInc]; expval += i * (P - oldP); for (int j = 0; j < N; j++) if (calc(j) > calc(highInc)) highInc = j; } cout << fixed << setprecision(20) << expval + N << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv3sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv3sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
|
module chan_fifo_reader
(reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and tx_q
input wire [31:0] adc_time ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is ready
output reg rdreq ; //actually an ack to the current fifodata
output reg skip ; //finish reading current packet
output reg [15:0] tx_q ; //top 16 bit output of fifodata
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
output reg underrun ;
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
output wire [14:0] debug;
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
`define JITTER 5
//Samples format
// 16 bits interleaved complex samples
`define QI16 4'b0
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter TIMESTAMP = 3'd2;
parameter WAIT = 3'd3;
parameter WAITSTROBE = 3'd4;
parameter SEND = 3'd5;
// Header format
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
/* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
always @(posedge tx_clock)
begin
if (reset)
begin
reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
end
else
begin
case (reader_state)
IDLE:
begin
/*
* reset all the variables and wait for a tx_strobe
* it is assumed that the ram connected to this fifo_reader
* is a short hand fifo meaning that the header to the next packet
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
/* Process header */
HEADER:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
begin
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 1;
reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
end
// Decide if we wait, send or discard samples
WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
// Outdated
if ((timestamp < adc_time) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
reader_state <= IDLE;
skip <= 1;
end
// Let's send it
else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
begin
trash <= 0;
reader_state <= WAITSTROBE;
end
else
reader_state <= WAIT;
end
else
reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
reader_state <= IDLE;
skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
case(samples_format)
`QI16:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
endcase
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////
// Filename : cpu_tb.v
// Description : Troy Wide Word Processor Testbench
// Author : Dr. Rashed Z. Bhatti
// Created On : Thu Nov 29 02:35:07 2007
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
//////////////////////////////////////////////////////////
`timescale 1ns/10ps
// Define the clock cycle
`define CYCLE_TIME 5
// include files
`include "cpu.syn.v"
`include "dmem.v"
`include "imem.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// This testbench instantiates the following modules:
// a. 128 bit Troy Word Wide Processor as CPU,
// b. 256 X 32 bit word Instruction memory
// c. 256 X 128 bit word Data memory
module cpu_tb;
reg Clk, Reset;
wire [0:31] ProgramCounter;
wire [0:31] Instruction;
wire [0:20] MemAddr;
wire [0:127] DataIn, DataOut;
integer dmem_dump_file; // The channel descriptor for reg file final dump
integer i; // loop control variable
integer cycle_number;
///****************************Module Instantiations****************************
// Instruction Memory Instance
imem IM(
.addr (ProgramCounter[22:29]), // only 8 bits are used in this project
.dataOut (Instruction)
);
// CPU Instance
cpu TROY (
.clk (Clk),
.reset (Reset),
.instruction (Instruction), // 32 bit instruction
.pc (ProgramCounter), // 32 bit program counter
.dataIn (DataIn), // 128 bit data from dmem
.dataOut (DataOut), // 128 bit data to dmem
.memAddr (MemAddr), // 21 bit immediate address, only 8 bits are used
.memWrEn (MemWrEn), // dmem write enable
.memEn (MemEn) // dmeme enable (to avoid spurious reads)
);
//Data Memory Instance
dmem DMEM (
.clk (Clk),
.memAddr (MemAddr[13:20]), // 8 bit memory address
.dataIn (DataOut), // 128 bit data to dmem
.wrEn (MemWrEn), // dmem write enable
.memEn (MemEn), // dmeme enable (to avoid spurious reads)
.dataOut (DataIn) // 128 bit data from dmem
);
///****************************Module Instantiations Ends****************************
initial
begin
$sdf_annotate("../sdf/cpu.sdf",TROY,"TYPICAL","1.0:1.0:1.0","FROM_MTM");
$readmemh("imem.fill", IM.mem); // loading instruction memory
$readmemh("dmem.fill", DMEM.mem); // loading data memory
Clk <= 0; // initialize Clock
Reset <= 1'b1; // reset the CPU
repeat(5) @(negedge Clk); // wait for 5 clock cycles
Reset <= 1'b0; // de-activate reset signal after 5ns
// Convention for the last instruction
// We would have a last instruction NOP => 32'h00000000
wait (Instruction == 32'h00000000);
// Let us see how much did you stall
$display("The program completed in %d cycles", cycle_number);
// Let us now flush the pipe line
repeat(5) @(negedge Clk);
// Open file for output
dmem_dump_file = $fopen("dmem.dump"); // assigning the channel descriptor for output file
// Let us now dump first 128 locations of the data memory now
for (i=0; i<128; i=i+1)
begin
$fdisplay(dmem_dump_file, "Memory location #%d : %h ", i, DMEM.mem[i]);
end
$fdisplay(dmem_dump_file, "\nNumber of execution cycles = %d", cycle_number);
$fclose(dmem_dump_file);
$stop;
end // initial begin
// Clock Generation
always #(`CYCLE_TIME / 2) Clk <= ~Clk;
//************************** Cycle Counter *****************************************
always @ (posedge Clk)
begin
if (Reset)
cycle_number <= 0;
else
cycle_number <= cycle_number + 1;
end
endmodule
|
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN = 1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] timestamp_clock;
always @(posedge rxclk)
if (reset)
timestamp_clock <= 0;
else
timestamp_clock <= timestamp_clock + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il[0:NUM_CHAN];
wire WR;
wire have_space;
reg sel;
reg wr;
always@(posedge rxclk)
begin
if(reset)
begin
sel<=1;
wr<=0;
end
else if(rxstrobe)
begin
sel<=0;
wr<=1;
end
else if(wr&~sel)
sel<=1;
else if(wr&sel)
wr<=0;
else
wr<=0;
end
assign fifodata_il[0] = (sel)?ch_1:ch_0;
assign fifodata_il[1] = (sel)?ch_3:ch_2;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
// These are of size [NUM_CHAN:0] because the extra channel is used for the
// RX command channel. If there were no command channel, they would be
// NUM_CHAN-1.
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.timestamp_clock ( timestamp_clock ),
.channels ( NUM_CHAN ),
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// FIXME: what is the purpose of these two lines?
wire [15:0]ch[NUM_CHAN:0];
assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Of Size 0:NUM_CHAN due to extra command channel.
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il[i] ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & wr),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
wire [7:0] debug;
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, k, s, t; int read() { int x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } int n1, n2, n3, p1, p2, p3, m1, m2, m3, st; long long m, n, ans; int st2[1010000], sta[1010000]; struct data { int p, q; }; bool cmp(const data &a, const data &b) { return a.p < b.p; } struct da { data a[50]; int n; } a, b; long long qpow(long long x, int y) { long long ans = 1; while (y) { if (y & 1) ans *= x; x *= x; y >>= 1; } return ans; } void solve1(int x, long long y) { if (y > n) return; if (x == b.n + 1) { ans++; return; } solve1(x + 1, y); for (int i = 1; i <= b.a[x].q; i++) y *= b.a[x].p, solve1(x + 1, y); } void solve2(int x, long long y, int f) { if (!y) return; if (x == st + 1) { ans += y * f; return; } solve2(x + 1, y, f); for (int i = 1; i <= st2[x]; i++) y /= sta[x]; solve2(x + 1, y, -f); } void pre(da &a, int x) { int i, j, k; for (i = 1; i <= a.n; i++) while (x % a.a[i].p == 0) x /= a.a[i].p, a.a[i].q++; for (i = 2; i * i <= x; i++) if (x % i == 0) { a.n++; a.a[a.n].p = i; a.a[a.n].q = 0; while (x % i == 0) x /= i, a.a[a.n].q++; } if (x > 1) { a.n++; a.a[a.n].p = x; a.a[a.n].q = 1; } } int main() { int T = read(); while (T--) { n1 = read(); n2 = read(); n3 = read(); n = (long long)n1 * n2 * n3; m1 = read(); m2 = read(); m3 = read(); m = (long long)m1 * m2 * m3; p1 = read(); p2 = read(); p3 = read(); a.n = 0; b.n = 0; ans = 0; pre(a, n1); pre(a, n2); pre(a, n3); pre(b, p1); pre(b, p2); pre(b, p3); pre(b, 2); sort(a.a + 1, a.a + a.n + 1, cmp); sort(b.a + 1, b.a + b.n + 1, cmp); solve1(1, 1); j = 1; st = 0; for (i = 1; i <= a.n; i++) { while (b.a[j].p < a.a[i].p && j <= b.n) j++; if (j == b.n + 1) break; if (b.a[j].p == a.a[i].p && a.a[i].q > b.a[j].q) { sta[++st] = a.a[i].p; st2[st] = b.a[j].q + 1; } if (b.a[j].p > a.a[i].p) { sta[++st] = a.a[i].p; st2[st] = 1; } } for (; i <= a.n; i++) { sta[++st] = a.a[i].p; st2[st] = 1; } solve2(1, m, 1); cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, f = 0, d = 0; cin >> a >> b; for (int i = 1; i <= 6; i++) { int d1 = abs(a - i), d2 = abs(b - i); if (d1 < d2) f++; else if (d1 == d2) d++; } cout << f << << d << << 6 - f - d << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[30010], n; bool vis[30010]; void print(vector<int> v) { for (int i = 0; i < v.size(); i++) printf( %d , v[i]); printf( n ); } bool check(vector<int> v) { if (!v.size()) return false; if (v.size() == 1 || v.size() == 2) return true; int d = v[1] - v[0]; for (int i = 2; i < v.size(); i++) if (v[i] - v[i - 1] != d) return false; return true; } bool solve(int l, int r) { vector<int> v1, v2; for (int i = 1; i <= n; i++) vis[i] = 0; int d = a[r] - a[l]; int last = -1, get = a[l]; for (int i = 1; i <= n; i++) if (a[i] == get) get += d, v1.push_back(a[i]), last = i; else vis[i] = 1; for (int i = 1; i <= n; i++) if (vis[i]) v2.push_back(a[i]); if (check(v2)) { print(v1), print(v2); return true; } vis[last] = 1, v1.pop_back(), v2.clear(); for (int i = 1; i <= n; i++) if (vis[i]) v2.push_back(a[i]); if (check(v2)) { print(v1), print(v2); return true; } return false; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); if (n == 2) printf( %d n%d , a[1], a[2]); else if (!solve(1, 2) && !solve(2, 3) && !solve(1, 3)) printf( No solution ); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; string s; cin >> s; n = s.size(); int z = 0, o = 0; for (int i = 0; i < n; i++) { if (s[i] == 1 ) o++; else z++; } if (min(o, z) & 1) { cout << DA n ; } else { cout << NET n ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
|
/*
* Titor - System - Stuff I made because I was really frustrated with the debounce circuitry
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Negedge
`else
`define INC_Negedge
`timescale 1 ns / 100 ps
// Sean Moore
module Negedge(
linein,
lineout,
reset,
clk
);
`include "definition/Definition.v"
input linein;
output lineout;
reg linehold;
input reset;
input clk;
always @(posedge clk) begin
linehold <= linein;
end
assign lineout = ((linehold) && (!linein));
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_BLACKBOX_V
`define SKY130_FD_SC_LS__A222O_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_BLACKBOX_V
|
#include <bits/stdc++.h> int main(int argc, char **argv) { long count = 0; std::cin >> count; long sum = 0; long tmp; long size; do { sum += (tmp = count); size = (count / 2) + 1; int offset = (count % 2) ? 2 : 1; int start = (count % 2) ? 3 : 2; for (long i = start; i < size; i += offset) { if (!(count % i)) { tmp = i; break; } } count /= tmp; } while (count != 1); std::cout << sum + 1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_BLACKBOX_V
`define SKY130_FD_SC_LS__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_BLACKBOX_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.