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#include <bits/stdc++.h> using namespace std; int main() { int n, temp; cin >> n; string s; cin >> s; temp = n; for (int i = n - 2; i >= 0; i--) { if (s.substr(i, 2) == 10 || s.substr(i, 2) == 01 ) { temp -= 2; s.erase(i, 2); i++; } } cout << temp; return 0; }
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_xlconcat_1_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "zc702_xlconcat_1_0,xlconcat,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=1,NUM_PORTS=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_xlconcat_1_0 (
In0,
dout
);
input wire [0 : 0] In0;
output wire [0 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(1),
.NUM_PORTS(1)
) inst (
.In0(In0),
.In1(1'B0),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
`include "register_set.v"
`include "stimuli.v"
`include "register_set_syn.v"
`include "check.v"
module register_set_tb();
// Wires
logic [7:0] address;
logic [31:0] data_in;
logic [1:0] req;
logic [2047:0] mem_out;
logic [2047:0] mem_out_syn;
logic ack, ack_syn, clk, reset, wnr;
logic [31:0] data_out, data_out_syn;
initial begin
$dumpfile("tests/vcd/reg_set.vcd");
$dumpvars(0, register_set_tb);
end
// modulos
stimuli s(
.clk(clk),
.reset(reset),
.wnr(wnr),
.req(req),
.address(address),
.data_in(data_in)
);
register_set DUT(
.clk(clk),
.reset(reset),
.wnr(wnr),
.req(req),
.address(address),
.mem_data_out(mem_out),
.data_out(data_out),
.ack(ack),
.data_in(data_in)
);
register_set_syn DUT_Syn(
.clk(clk),
.reset(reset),
.wnr(wnr),
.req(req),
.address(address),
.mem_data_out(mem_out_syn),
.data_out(data_out_syn),
.ack(ack_syn),
.data_in(data_in)
);
check chck(
.reg_input(data_in),
.reg_out(data_out),
.reg_out_syn(data_out_syn),
.ack(ack),
.ack_syn(ack_syn),
.clk(clk),
.wnr(wnr),
.address(address),
.mem_out(mem_out),
.mem_out_syn(mem_out_syn)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 100; int m, n; long long sweets[MAXN]; vector<long long> sol; long long weightedSum; long long sums[MAXN]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> sweets[i]; } sort(sweets, sweets + n); for (int i = 0; i < n;) { for (int j = 0; j < m && i + j < n; j++) { sums[j] += sweets[i + j]; weightedSum += sums[j]; sol.push_back(weightedSum); } i += m; } for (int i = 0; i < sol.size(); i++) { cout << sol[i] << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Inf = (int)1e9; const long long InfL = (long long)1e18; const int MaxN = (int)2e5 + 5; vector<int> adj[MaxN], ans; int n, a, deg[MaxN], dead[MaxN]; void dfs2(int x, int p) { dead[x] = true; ans.push_back(x); for (auto u : adj[x]) --deg[u]; for (auto u : adj[x]) if (u != p && !dead[u]) dfs2(u, x); } void dfs1(int x, int p) { for (auto u : adj[x]) if (u != p) dfs1(u, x); if (!(deg[x] & 1)) dfs2(x, p); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (!a) continue; adj[i].push_back(a); deg[i]++; adj[a].push_back(i); deg[a]++; } dfs1(1, 0); if (ans.size() == n) { cout << YES << n ; for (int i = 0; i < n; i++) cout << ans[i] << n ; } else { cout << NO << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int a; cin >> a; string s; cin >> s; map<long long, long long> mp; long long ans = 0; for (int i = 0; i < s.size(); i++) { long long c = 0; for (int j = i; j < s.size(); j++) { c += (s[j] - 0 ); mp[c]++; } } for (auto i : mp) { if (!i.first) { if (!a) ans += (i.second * i.second); } else if (a % i.first == 0) { if (a == 0) ans += (mp[0] * i.second * 2); else ans += (mp[a / i.first] * i.second); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int count = 0; int n, m; cin >> n >> m; char a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } for (int i = 0; i < n - 1; i++) { if (a[i][m - 1] != D ) { count++; } } for (int i = 0; i < m - 1; i++) { if (a[n - 1][i] != R ) { count++; } } cout << count << endl; } }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module niosII_system_pixel_out_buffer (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [17: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2012 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/);
`define ASSERT(x) initial if (!(x)) $stop
// See IEEE 6.20.2 on value parameters
localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef;
localparam signed [63:0] SIGNED =64'sh99934567_89abcdef;
localparam real REAL=1.234;
`ASSERT(UNSIGNED > 0);
`ASSERT(SIGNED < 0);
// bullet 1
localparam A1_WIDE = UNSIGNED;
`ASSERT($bits(A1_WIDE)==64);
localparam A2_REAL = REAL;
`ASSERT(A2_REAL == 1.234);
localparam A3_SIGNED = SIGNED;
`ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0);
localparam A4_EXPR = (2'b01 + 2'b10);
`ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11);
// bullet 2
localparam [63:0] B_UNSIGNED = SIGNED;
`ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0);
// bullet 3
localparam signed C_SIGNED = UNSIGNED;
`ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0);
localparam unsigned C_UNSIGNED = SIGNED;
`ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0);
// bullet 4
// verilator lint_off WIDTH
localparam signed [59:0] D_SIGNED = UNSIGNED;
`ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0);
// verilator lint_on WIDTH
// verilator lint_off WIDTH
localparam unsigned [59:0] D_UNSIGNED = SIGNED;
`ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0);
// verilator lint_on WIDTH
// bullet 6
localparam UNSIZED = 23;
`ASSERT($bits(UNSIZED)>=32);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int heap(int a, int t) { int tmp; if (a > t) swap(a, t); if (t % a == 0) return a; return heap(a, t % a); } int main() { string x, y; cin >> x >> y; bool f = true; for (int i = 0; i < x.size(); i++) { if (x[i] != y[x.size() - 1 - i]) f = false; } if (f) cout << YES << endl; else cout << NO << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_t.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_t
//
// No `defines in this module
module ent_t
//
// Generated module inst_t
//
(
input wire sig_i_a,
input wire sig_i_a2,
input wire [6:0] sig_i_ae,
output wire sig_o_a,
output wire sig_o_a2,
output wire [7:0] sig_o_ae
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_SYMBOL_V
`define SKY130_FD_SC_MS__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { string s; int n, s2 = 0, ans = 0, s1 = 0; cin >> s; n = s.size() - 1; for (int i = n; i >= 0; i--) if (s[i] == 1 ) { s2 = i; break; } for (int i = 0; i <= n; i++) if (s[i] == 1 ) { s1 = i; break; } for (int i = 0; i <= n; i++) { if (i > s1 && i < s2 && s[i] == 0 ) ans++; } cout << ans << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s50kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_PP_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module bus_to_ip
#(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter DBUSWIDTH = 8
)
(
input wire BUS_RD,
input wire BUS_WR,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [DBUSWIDTH-1:0] BUS_DATA,
output wire IP_RD,
output wire IP_WR,
output wire [ABUSWIDTH-1:0] IP_ADD,
output wire [DBUSWIDTH-1:0] IP_DATA_IN,
input wire [DBUSWIDTH-1:0] IP_DATA_OUT
);
wire CS;
assign CS = (BUS_ADD >= BASEADDR && BUS_ADD <= HIGHADDR);
assign IP_ADD = CS ? BUS_ADD - BASEADDR : {ABUSWIDTH{1'b0}};
assign IP_RD = CS ? BUS_RD : 1'b0;
assign IP_WR = CS ? BUS_WR: 1'b0;
assign IP_DATA_IN = BUS_DATA;
//assign BUS_DATA = (CS && BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}});
// This is same as above but for Icarus + cocotb this change is needed, and yes, in one line, bug?
reg [DBUSWIDTH-1:0] TMP; always@(*) TMP = (CS & BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}}); assign BUS_DATA = TMP;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 5; int n, ri[N]; char s[N]; struct node { int ch[26], par, val; } t[N]; int sz = 1, root = 1, last = 1; void extend(int c) { int p = last, np = ++sz; t[np].val = t[p].val + 1; ri[np]++; for (; p && !t[p].ch[c]; p = t[p].par) t[p].ch[c] = np; if (!p) t[np].par = root; else { int q = t[p].ch[c]; if (t[q].val == t[p].val + 1) t[np].par = q; else { int nq = ++sz; t[nq] = t[q]; t[nq].val = t[p].val + 1; t[q].par = t[np].par = nq; for (; p && t[p].ch[c] == q; p = t[p].par) t[p].ch[c] = nq; } } last = np; } int vis[N]; void walk(int id) { int u = root, len = n + n - 1, ans = 0, nowLen = 0; for (int i = 1; i <= len; i++) { int c = s[i] - a ; if (t[u].ch[c]) u = t[u].ch[c], nowLen++; else { while (u && !t[u].ch[c]) u = t[u].par; if (!u) u = root, nowLen = 0; else nowLen = t[u].val + 1, u = t[u].ch[c]; } if (vis[u] != id && nowLen >= n) vis[u] = id, ans += ri[u]; if (n != 1) while (t[t[u].par].val + 1 >= n) u = t[u].par, nowLen = t[u].val; } printf( %d n , ans); } int c[N], a[N]; void RadixSort() { for (int i = 1; i <= sz; i++) c[t[i].val]++; for (int i = 1; i <= n; i++) c[i] += c[i - 1]; for (int i = sz; i >= 1; i--) a[c[t[i].val]--] = i; } void solve() { RadixSort(); int u; for (int i = sz; i >= 1; i--) u = a[i], ri[t[u].par] += ri[u]; int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i < n; i++) s[i + n] = s[i]; walk(i); } } int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i <= n; i++) extend(s[i] - a ); solve(); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:30:48 04/12/2016
// Design Name:
// Module Name: Registro_timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Registro_timer(
input wire hold,
input wire [7:0]in_rtc_dato,
input wire [7:0]in_count_dato,
input wire clk, //system clock
input wire reset, //system reset
input wire chip_select, //Control data
output wire [7:0]out_dato_vga,
output wire [7:0]out_dato_rtc
);
reg [7:0]reg_dato;
reg [7:0]next_dato;
//reg [7:0]dato_temp;
//Secuencial
always@(negedge clk, posedge reset)
begin
if(reset) reg_dato <= 0;
else reg_dato <= next_dato;
end
//Combinacional
always@*
begin
if (~hold) begin
case(chip_select)
1'b0: next_dato = in_rtc_dato;
1'b1: next_dato = in_count_dato;
endcase
end
else next_dato = reg_dato;
end
/////////////////////////////////////////////////
assign out_dato_vga = reg_dato;
assign out_dato_rtc = 8'h00;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^5 + x^2 + 1
// * data width: 5
//
// Info :
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC5_D11(
nextCRC5_D11,
Data,
crc
);
output reg [4:0] nextCRC5_D11;
input wire [10:0] Data;
input wire [4:0] crc;
reg [10:0] d;
reg [4:0] c;
reg [4:0] newcrc;
always @ (*)
begin
d [10:0] = Data [10:0];
c [4:0] = crc [4:0];
newcrc[0] = d[10] ^ d[9] ^ d[6] ^ d[5] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4];
newcrc[1] = d[10] ^ d[7] ^ d[6] ^ d[4] ^ d[1] ^ c[0] ^ c[1] ^ c[4];
newcrc[2] = d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4];
newcrc[3] = d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[4] ^ d[3] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[4];
newcrc[4] = d[10] ^ d[9] ^ d[8] ^ d[5] ^ d[4] ^ d[2] ^ c[2] ^ c[3] ^ c[4];
nextCRC5_D11 = newcrc;
end
endmodule
|
#include <bits/stdc++.h> using llong = long long; using namespace std; set<llong> factors; void f(llong num) { factors.insert(1); llong to = sqrt(num); for (auto i = 2; i <= to; ++i) { if (num % i == 0) { factors.insert(i); factors.insert(num / i); } } factors.insert(num); } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); llong n; cin >> n; f(n); set<llong> res; for (auto e : factors) { res.insert((n + 1 + 1) * (n / e + 1) / 2 - (n + 1)); } for (auto i : res) cout << i << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pi = pair<int, int>; void setIO(string name = ) { ios_base::sync_with_stdio(0); cin.tie(0); } int main() { setIO(); int a, b, c, d; cin >> a >> b >> c >> d; int pv = max(3 * a / 10, a - a / 250 * c); int pm = max(3 * b / 10, b - b / 250 * d); if (pv == pm) { cout << Tie ; } else if (pv > pm) { cout << Misha ; } else { cout << Vasya ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_TB_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_TB_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
module top();
// Inputs are registered
reg SLEEP;
reg VPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire VIRTPWR;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_lp__sleep_sergate_plv dut (.SLEEP(SLEEP), .VPWR(VPWR), .VPB(VPB), .VNB(VNB), .VIRTPWR(VIRTPWR));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; vector<int> cnt[N]; int res[N]; int main() { int n; while (cin >> n) { for (int i = 1; i < N; i++) cnt[i].clear(); for (int i = 1; i <= n; i++) { int v; cin >> v; cnt[v].push_back(i); } bool ok = true; for (int i = 1; i < N; i++) { if (i > 1 && cnt[i].size() > cnt[i - 1].size()) ok = false; for (int j = 0; j < cnt[i].size(); j++) { res[cnt[i][j]] = j + 1; } } if (!ok) { printf( %d n , -1); } else { printf( %d n , cnt[1].size()); for (int i = 1; i <= n; i++) printf( %d%c , res[i], i == n ? n : ); } } return 0; }
|
/*
* Copyright (c) 2002 Jane Skinner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Icarus 0.6, snapshot 20020728 or snapshot 20010806
// ==================================================
// -- confused by complex disables
//
// -- to run, incant
// iverilog tt.v
// vvp a.out
//
// Veriwell
// ========
// -- OK
//
module top;
integer loop_cntr, simple_fail, loop_fail;
reg fred, abort;
initial begin
#1;
simple_fail = 0;
loop_fail = 0;
fred = 0;
abort = 1;
#4;
fred = 1;
#4
if(simple_fail) $display("\n***** simple block disable FAILED *****");
else $display("\n***** simple block disable PASSED *****");
if(loop_fail) $display("***** complex block & loop disable FAILED *****\n");
else $display("***** complex block & loop disable PASSED *****\n");
$finish(0);
end
// simple block disable
initial begin: block_name
#2;
disable block_name;
simple_fail = 1;
end
// more complex: block disable inside for-loop
initial begin
#2;
begin: configloop
for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
wait (fred);
if (abort) begin
disable configloop;
end
loop_fail = 1;
end
end // configloop block
if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m, x; cin >> n >> m >> x; x--; if (n > m) { cout << 0 << endl; return 0; } vector<vector<long long>> dp(n + 1, vector<long long>(n + 1, 0)); dp[0][0] = 1; for (int i = 0; i < m; i++) { vector<vector<long long>> ndp(n + 1, vector<long long>(n + 1, 0)); for (int j = 0; j <= n; j++) for (int k = 0; j + k <= n; k++) { if (i != x) (ndp[j][k] += dp[j][k]) %= mod; if (j + k + 1 <= n) (ndp[j + 1][k] += dp[j][k]) %= mod; if (i != x && j) (ndp[j - 1][k + 1] += dp[j][k]) %= mod; if (j + k + 1 <= n) (ndp[j][k + 1] += dp[j][k]) %= mod; } swap(dp, ndp); } long long ans = dp[0][n]; for (int i = 1; i <= n; i++) (ans *= i) %= mod; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int V = 100000 + 5; int n, num[V]; int main() { int i, j; scanf( %d , &n); for (i = 0; i < n; ++i) scanf( %d , &num[i]); sort(num, num + n); printf( %d , num[n - 1]); for (i = 1; i < n - 1; ++i) printf( %d , num[i]); printf( %d n , num[0]); }
|
module RAMB16_S2_S2(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [12:0] ADDRA,
input [1:0] DIA,
// input DIPA,
// output [3:0] DOPA,
output [1:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [12:0] ADDRB,
input [1:0] DIB,
// input DIPB,
// output [3:0] DOPB,
output [1:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(2),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(1'b0),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(1'b0),.DOB(DOB));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void dbg_vector(const T& v) { for (size_t i = 0; i < v.size(); ++i) cout << v[i] << ; cout << endl; } void dbg() { cerr << endl; } template <typename Head, typename... Tail> void dbg(Head H, Tail... T) { cerr << H << ; dbg(T...); } struct pair_hash { template <class T1, class T2> size_t operator()(const pair<T1, T2>& p) const { auto h1 = std::hash<T1>{}(p.first); auto h2 = std::hash<T2>{}(p.second); return h1 ^ h2; } }; struct Comparator { template <class T1, class T2> bool operator()(const std::pair<T1, T2>& lhs, const std::pair<T1, T2>& rhs) const { if (lhs.first == rhs.first) return lhs.second < rhs.second; else return lhs.first < rhs.first; } }; inline long long lmin(long long a, long long b) { if (a < b) return a; return b; } inline long long lmax(long long a, long long b) { if (a > b) return a; return b; } long long INF = 1e18; long long MOD = 998244353; struct edge { long long w, x, y; edge(){}; edge(long long w, long long x, long long y) : w(w), x(x), y(y){}; }; struct EdgeComparator { bool operator()(const edge& lhs, const edge& rhs) const { if (lhs.w < rhs.w) return true; return false; } }; vector<int> prefix_function(string& s) { int n = s.size(); vector<int> p(n); for (int i = 1; i < n; ++i) { int j = p[i - 1]; while (s[i] != s[j] && j > 0) j = p[j - 1]; if (s[i] == s[j]) j++; p[i] = j; } return p; } vector<long long> matmul(vector<long long>& a, vector<long long>& b) { vector<long long> res(4); res[0] = (a[0] * b[0] + a[1] * b[2]) % MOD; res[1] = (a[0] * b[1] + a[1] * b[3]) % MOD; res[2] = (a[2] * b[0] + a[3] * b[2]) % MOD; res[3] = (a[2] * b[1] + a[3] * b[3]) % MOD; return res; } vector<long long> matpow(vector<long long>& m, long long n) { if (n == 1) return m; if (n % 2 == 0) { vector<long long> a = matpow(m, n >> 1); return matmul(a, a); } else { vector<long long> a = matpow(m, n - 1); return matmul(a, m); } } struct point { int x, y; point(){}; point(int x, int y) : x(x), y(y){}; }; struct rect { int x1, y1, x2, y2; rect(){}; rect(int x1, int y1, int x2, int y2) : x1(x1), y1(y1), x2(x2), y2(y2){}; }; bool cw(point& a, point& b) { int cross_product = a.x * b.y - a.y * b.x; return cross_product <= 0; } bool oneline(point& a, point& b) { int cross_product = a.x * b.y - a.y * b.x; return cross_product == 0; } int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; vector<vector<bool> > can(n, vector<bool>(5)); vector<vector<int> > p(n, vector<int>(5)); can[0][0] = true; can[0][1] = true; can[0][2] = true; can[0][3] = true; can[0][4] = true; for (int i = 1; i < n; ++i) { if (a[i] == a[i - 1]) { for (int k = 0; k <= 4; ++k) { for (int j = 0; j <= 4; ++j) { if (j != k && can[i - 1][j]) { can[i][k] = true; p[i][k] = j; break; } } } } else if (a[i] > a[i - 1]) { if (can[i - 1][0]) { can[i][1] = true; p[i][1] = 0; can[i][2] = true; p[i][2] = 0; can[i][3] = true; p[i][3] = 0; can[i][4] = true; p[i][4] = 0; } else if (can[i - 1][1]) { can[i][2] = true; p[i][2] = 1; can[i][3] = true; p[i][3] = 1; can[i][4] = true; p[i][4] = 1; } else if (can[i - 1][2]) { can[i][3] = true; p[i][3] = 2; can[i][4] = true; p[i][4] = 2; } else if (can[i - 1][3]) { can[i][4] = true; p[i][4] = 3; } else { cout << -1 << endl; return 0; } } else { if (can[i - 1][4]) { can[i][0] = true; p[i][0] = 4; can[i][1] = true; p[i][1] = 4; can[i][2] = true; p[i][2] = 4; can[i][3] = true; p[i][3] = 4; } else if (can[i - 1][3]) { can[i][0] = true; p[i][0] = 3; can[i][1] = true; p[i][1] = 3; can[i][2] = true; p[i][2] = 3; } else if (can[i - 1][2]) { can[i][0] = true; p[i][0] = 2; can[i][1] = true; p[i][1] = 2; } else if (can[i - 1][1]) { can[i][0] = true; p[i][0] = 1; } else { cout << -1 << endl; return 0; } } } vector<int> ans(n); if (can[n - 1][0]) { int i = n - 1; int cur = 0; ans[n - 1] = cur + 1; while (i > 0) { cur = p[i][cur]; ans[i - 1] = cur + 1; i--; } } else if (can[n - 1][1]) { int i = n - 1; int cur = 1; ans[n - 1] = cur + 1; while (i > 0) { cur = p[i][cur]; ans[i - 1] = cur + 1; i--; } } else if (can[n - 1][2]) { int i = n - 1; int cur = 2; ans[n - 1] = cur + 1; while (i > 0) { cur = p[i][cur]; ans[i - 1] = cur + 1; i--; } } else if (can[n - 1][3]) { int i = n - 1; int cur = 3; ans[n - 1] = cur + 1; while (i > 0) { cur = p[i][cur]; ans[i - 1] = cur + 1; i--; } } else if (can[n - 1][4]) { int i = n - 1; int cur = 4; ans[n - 1] = cur + 1; while (i > 0) { cur = p[i][cur]; ans[i - 1] = cur + 1; i--; } } for (int i = 0; i < n; ++i) cout << ans[i] << ; cout << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_SYMBOL_V
`define SKY130_FD_SC_HVL__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_SYMBOL_V
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int i, k; int n; cin >> n; if (n % 2 == 0) { k = n / 2; cout << k << n ; for (i = 0; i < k; i++) cout << 2 << ; } else { k = (n - 1) / 2; cout << k << n ; for (i = 0; i < k - 1; i++) { cout << 2 << ; } cout << 3 << ; } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 50; long long fac[N + 1]; void init() { fac[0] = 1; for (long long i = 1; i <= N; i++) { fac[i] = (i * fac[i - 1]) % 1000000007LL; } } long long pw(long long a, long long e) { if (e == 0) { return 1; } long long ret = pw(a, e / 2); ret = (ret * ret) % 1000000007LL; if (e % 2 == 1) { ret = (a * ret) % 1000000007LL; } return ret; } long long choose(long long x, long long y, long long x0, long long y0) { return (((((fac[x] * pw(fac[x0], 1000000007LL - 2)) % 1000000007LL) * pw(fac[x - x0], 1000000007LL - 2)) % 1000000007LL) * ((((fac[y] * pw(fac[y0], 1000000007LL - 2)) % 1000000007LL) * pw(fac[y - y0], 1000000007LL - 2)) % 1000000007LL)) % 1000000007LL; } long long X, Y; vector<pair<long long, long long> > adj[(N + 1) * (N + 1) * 2]; long long getVertex(long long x, long long y, long long sh) { return sh * (X + 1) * (Y + 1) + x * (Y + 1) + y; } queue<long long> q; long long dist[(N + 1) * (N + 1) * 2], ways[(N + 1) * (N + 1) * 2]; int main() { init(); long long n, k; cin >> n >> k; while (n--) { long long w; cin >> w; if (w == 50) { X++; } else { Y++; } } for (long long x = 0; x <= X; x++) { for (long long y = 0; y <= Y; y++) { for (long long x0 = 0; x0 <= x; x0++) { for (long long y0 = 0; y0 <= y; y0++) { if (x0 + y0 >= 1 && (50 * x0 + 100 * y0 <= k)) { long long w = choose(x, y, x0, y0); adj[getVertex(x, y, 0)].push_back(pair<long long, long long>( getVertex(X - x + x0, Y - y + y0, 1), w)); adj[getVertex(x, y, 1)].push_back(pair<long long, long long>( getVertex(X - x + x0, Y - y + y0, 0), w)); } } } } } long long start = getVertex(X, Y, 0), end = getVertex(X, Y, 1); for (long long u = 0; u <= (X + 1) * (Y + 1) * 2 - 1; u++) { dist[u] = 1000000000000000000LL; } q.push(start); dist[start] = 0; ways[start] = 1; while (!q.empty()) { long long u = q.front(); q.pop(); for (pair<long long, long long> vw : adj[u]) { long long v = vw.first, w = vw.second; if (dist[u] + 1 < dist[v]) { q.push(v); dist[v] = dist[u] + 1; ways[v] = (ways[u] * w) % 1000000007LL; } else if (dist[u] + 1 == dist[v]) { ways[v] = (ways[v] + ways[u] * w) % 1000000007LL; } } } cout << (dist[end] == 1000000000000000000LL ? -1 : dist[end]) << n << ways[end] << n ; }
|
#include <bits/stdc++.h> using namespace std; int n; long long int dp[3005][3005]; int a[3005]; int tree[3005 * 3005][2]; int cnt = 0; long long int check(int t) { return !((a[t - 3] == 0 && a[t - 2] == 0 && a[t - 1] == 1 && a[t] == 1) || (a[t - 3] == 0 && a[t - 2] == 1 && a[t - 1] == 0 && a[t] == 1) || (a[t - 3] == 1 && a[t - 2] == 1 && a[t - 1] == 1 && a[t] == 0) || (a[t - 3] == 1 && a[t - 2] == 1 && a[t - 1] == 1 && a[t] == 1)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) for (int j = i - 1; j <= n; j++) { if (j < i) dp[i][j] = 1; else { for (int k = 1; k <= min(j, (check(j) ? 4 : 3)); k++) dp[i][j] = (dp[i][j] + dp[i][j - k]) % 1000000007; } } long long int ans = 0; for (int i = 1; i <= n; i++) { int p = 0; for (int j = i; j >= 1; j--) { if (tree[p][a[j]]) p = tree[p][a[j]]; else { ans = (ans + dp[j][i]) % 1000000007; tree[p][a[j]] = cnt += 1; p = tree[p][a[j]]; } } printf( %d n , ans); } return 0; }
|
module test;
initial begin: A
reg [4:0] a;
reg [31:0] b, c, d;
a = 5'h14;
b = $signed(a);
c = {_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2)))};
d = $signed(_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2))));
$write("a is %0h; b is %0h; c is %0h; d is %0h\n", a, b, c, d);
end
function [4:0] _$Finv5;
input l;
reg [4:0] l;
_$Finv5 = ~l;
endfunction
function [7:0] _$Fsub8;
input l,r;
reg [7:0] l,r;
_$Fsub8 = l-r;
endfunction
function [7:0] _$Fadd8;
input l,r;
reg [7:0] l,r;
_$Fadd8 = l+r;
endfunction
function [31:0] _$Fsll32;
input l,r;
reg [31:0] l;
integer r;
begin
if(r < 0) begin
if(r + 32 <= 0) _$Fsll32 = 32'b0;
else _$Fsll32 = l >> -r;
end else if(r > 0) begin
if(r >= 32) _$Fsll32 = 32'b0;
else _$Fsll32 = l << r;
end else _$Fsll32 = l;
end
endfunction
function [31:0] _$Fsrl32;
input l,r;
reg [31:0] l;
integer r;
begin
if(r < 0) begin
if(r + 32 <= 0) _$Fsrl32 = 32'b0;
else _$Fsrl32 = l << -r;
end else if(r > 0) begin
if(r >= 32) _$Fsrl32 = 32'b0;
else _$Fsrl32 = l >> r;
end else _$Fsrl32 = l;
end
endfunction
endmodule
|
#include <bits/stdc++.h> const int p10[7] = {1, 10, 100, 1000, 10000, 100000, 1000000}; int N, S[10], can_be_zero[10], L, p[10], fill[10], O; char a[7]; int main() { for (int i = 0; i < 10; i++) can_be_zero[i] = 1; scanf( %d , &N); for (int i = 0; i < N; i++) { scanf( %s , a); L = 0; while (a[L]) L++; can_be_zero[a[0] - a ] = 0; for (int i = 0; i < L; i++) S[a[i] - a ] += p10[L - 1 - i]; } for (int i = 0; i < 10; i++) p[i] = i; std::sort(p, p + 10, [](int x, int y) { return S[x] > S[y]; }); for (int i = 0; i < 10; i++) fill[i] = -1; for (int i = 0; i < 10; i++) if (can_be_zero[p[i]]) { fill[p[i]] = 0; break; } for (int i = 0, u = 1; i < 10; i++) if (fill[p[i]] == -1) fill[p[i]] = u++; for (int i = 0; i < 10; i++) O += fill[i] * S[i]; printf( %d n , O); return 0; }
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
fail <= 1'h0;
pass <= 1'h0;
ready <= 1'h0;
// End of automatics
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
out0 = 8'h0;
// End of automatics
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
next_fail = 1'h0;
next_pass = 1'h0;
next_ready = 1'h0;
// End of automatics
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Q <= 8'h0;
// End of automatics
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_0(pclk, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="pclk,data[7:0],rgb[15:0]" */;
input pclk;
input [7:0]data;
output [15:0]rgb;
endmodule
|
// ---------------------------------------------
// external memory controller
// ---------------------------------------------
// The CPU runs at ~50MHz (20ns)
//
// When accessing byte-wide external memory, sufficient wait states
// need to be added to allow two slower memory cycles to happen
// (low byte then high byte)
//
// R1LV0408CSA-5SC RAM timings:
// -- Read access time is 55ns
//
// -- Min write pulse is 40ns, write happens on rising edge
// -- Address setup from falling edge of write is 0ns
// -- Address hold from rising edge of write is 0ns
// -- Data setup from rising edge of write is 25ns
// -- Address hold from rising edge of write is 0ns
//
// To err on the safe side, we allow 4 cycles for each byte access
//
// So a complete external memory access (both bytes) takes 8 cycles
//
// Which means the memory controller must insert 7 wait states
module memory_controller
(
clock,
reset_b,
// CPU Signals
ext_cs_b,
vpa,
cpu_rnw,
cpu_clken,
cpu_addr,
cpu_dout,
ext_dout,
// Ram Signals
ram_cs_b,
ram_oe_b,
ram_we_b,
ram_data,
ram_addr
);
parameter DSIZE = 16;
parameter ASIZE = 16;
parameter INDEX_BITS = 6; // Cache size is 2 ** INDEX_BITS
localparam CSIZE = clog2(DSIZE) - 1; // 16->3, 32->4
localparam TAG_BITS = ASIZE - INDEX_BITS;
localparam CACHE_WIDTH = DSIZE + 1 + TAG_BITS;
localparam CACHE_SIZE = 2 ** INDEX_BITS;
input clock;
input reset_b;
// CPU Signals
input ext_cs_b;
input vpa;
input cpu_rnw;
output cpu_clken;
input [ASIZE-1:0] cpu_addr;
input [DSIZE-1:0] cpu_dout;
output [DSIZE-1:0] ext_dout;
// Ram Signals
output ram_cs_b;
output ram_oe_b;
output ram_we_b;
inout [7:0] ram_data;
output [18:0] ram_addr;
wire [CSIZE - 3:0] ext_a_lsb;
reg ext_we_b;
reg [DSIZE-8-1:0] ram_data_last;
reg [CSIZE-1:0] count;
// Simple 2^N-entry direct mapped instruction cache:
// bits 15..0 == data (16 bits)
// bits 16 == valid
// bits 33-N..17 == tag (16 - N bits)
reg [CACHE_WIDTH-1:0] cache [0:CACHE_SIZE - 1]; (* RAM_STYLE="DISTRIBUTED" *)
wire [INDEX_BITS-1:0] addr_index = cpu_addr[INDEX_BITS-1:0];
wire [TAG_BITS-1:0] addr_tag = cpu_addr[ASIZE-1:INDEX_BITS];
wire [CACHE_WIDTH-1:0] cache_out = cache[addr_index];
wire [DSIZE-1:0] cache_dout = cache_out[DSIZE-1:0];
wire cache_valid = cache_out[DSIZE];
wire [TAG_BITS-1:0] cache_tag = cache_out[CACHE_WIDTH-1:DSIZE+1];
wire tag_match = cache_valid & (cache_tag == addr_tag);
wire cache_hit = vpa & tag_match;
integer i;
initial
for (i = 0; i < CACHE_SIZE; i = i + 1)
cache[i] = 0;
always @(posedge clock)
if (count == 2 ** CSIZE - 1)
if (cpu_rnw) begin
// Populate the cache at end of an instruction fetch from external memory
if (vpa)
cache[addr_index] <= {addr_tag, 1'b1, ext_dout};
end else begin
// Update the cache for consistecy if a cached instruction is overwritten
if (tag_match)
cache[addr_index] <= {addr_tag, 1'b1, cpu_dout};
end
// Count 0..7 during external memory cycles
always @(posedge clock)
if (!reset_b)
count <= 0;
else if (!ext_cs_b && !cache_hit || count > 0)
count <= count + 1;
// Drop clken for 7 cycles during an external memory access
assign cpu_clken = !(!ext_cs_b && !cache_hit && count < 2 ** CSIZE - 1);
// A0 = 0 for count 0,1,2,3 (low byte) and A0 = 1 for count 4,5,6,7 (high byte)
assign ext_a_lsb = count[CSIZE - 1 : 2];
// Generate clean write co-incident with cycles 1,2 and 5,6
// This gives a cycle of address/data setup and
// Important this is a register so it is glitch free
always @(posedge clock)
if (!cpu_rnw && !ext_cs_b && !count[1])
ext_we_b <= 1'b0;
else
ext_we_b <= 1'b1;
// The low byte is registered at the end of cycle 3
// The high byte is consumed directly from RAM at the end of cycle 7
always @(posedge clock)
if (count[1:0] == 2'b11)
ram_data_last <= (ram_data_last >> 8) | (ram_data << (DSIZE - 16));
assign ext_dout = cache_hit ? cache_dout : { ram_data, ram_data_last };
// ---------------------------------------------
// external RAM
// ---------------------------------------------
assign ram_addr = {cpu_addr, ext_a_lsb};
assign ram_cs_b = ext_cs_b;
assign ram_oe_b = !cpu_rnw;
assign ram_we_b = ext_we_b;
assign ram_data = cpu_rnw ? 8'bZ :
ext_a_lsb == 3 ? cpu_dout[31:24] :
ext_a_lsb == 2 ? cpu_dout[23:16] :
ext_a_lsb == 1 ? cpu_dout[15:8] :
cpu_dout[7:0] ;
// ---------------------------------------------
// functions
// ---------------------------------------------
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const long dad = 1e6; int n, m, l = 1, r; long long k; long long d[dad], a[dad], b[dad], res, ans[dad], dem[dad]; struct yasu { int id, l, r; } p[dad], c[dad]; bool cmp(yasu u, yasu v) { return (u.l / 300 < v.l / 300 || (u.l / 300 == v.l / 300 && u.r < v.r)); } void update(int u, long long gt1, long long gt2, long long gt3) { res += dem[c[u].l] * gt2; res += dem[c[u].r] * gt3; dem[c[u].id] += gt1; } int getint() { int ww = 0; char cc = getchar(); while (cc > 9 || cc < 0 ) cc = getchar(); while (cc >= 0 && cc <= 9 ) { ww = ww * 10 + cc - 0 ; cc = getchar(); } return ww; } long long getll() { long long ww = 0; char cc = getchar(); while (cc > 9 || cc < 0 ) cc = getchar(); while (cc >= 0 && cc <= 9 ) { ww = ww * 10 + cc - 0 ; cc = getchar(); } return ww; } void input() { scanf( %d%lld , &n, &k); for (int i = 1; i <= n; ++i) { d[i] = getll(); d[i] = d[i] == 1 ? 1 : -1; } for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i]); a[i] = a[i - 1] + a[i] * d[i]; } for (int i = 0; i <= n; ++i) { b[++*b] = a[i]; b[++*b] = a[i] + k; b[++*b] = a[i] - k; } sort(b + 1, b + *b + 1); *b = unique(b + 1, b + *b + 1) - b - 1; scanf( %d , &m); for (int i = 1; i <= m; ++i) { scanf( %d%d , &p[i].l, &p[i].r); --p[i].l; p[i].id = i; } for (int i = 0; i <= n; ++i) { c[i].id = lower_bound(b + 1, b + *b + 1, a[i]) - b; c[i].l = lower_bound(b + 1, b + *b + 1, a[i] - k) - b; c[i].r = lower_bound(b + 1, b + *b + 1, a[i] + k) - b; } sort(p + 1, p + m + 1, cmp); for (int i = 1; i <= m; ++i) { int l1 = p[i].l; int r1 = p[i].r; while (l < l1) { --dem[c[l].id]; res -= dem[c[l].r]; ++l; } while (l > l1) { --l; res += dem[c[l].r]; ++dem[c[l].id]; } while (r < r1) { ++r; res += dem[c[r].l]; ++dem[c[r].id]; } while (r > r1) { --dem[c[r].id]; res -= dem[c[r].l]; --r; } ans[p[i].id] = res; } for (int i = 1; i <= m; ++i) printf( %lld n , ans[i]); } void output() {} int main() { input(); output(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_2_V
`define SKY130_FD_SC_LP__MUX2_2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_2_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) using namespace std; const long double pi = acos(-1.0); const long long inf = (long long)1e18; const int N = (int)1e6; int n, m; long long need[N], start[N]; bool check(long long x) { int lowest = 0; for (int i = 0; (i < n) && (lowest < m); ++i) { long long pos = start[i], can = x; if (need[lowest] <= pos) { if (pos - need[lowest] > can) return false; else can = max(can - 2 * (pos - need[lowest]), (can - (pos - need[lowest])) / 2); } while ((lowest < m) && (need[lowest] - pos <= can)) ++lowest; } return (lowest == m); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %I64d , &start[i]); for (int i = 0; i < m; ++i) scanf( %I64d , &need[i]); if (check(0)) { printf( 0 n ); return 0; } long long l = 0, r = inf; while (l < r - 1) { long long m = (l + r) / 2; if (check(m)) r = m; else l = m; } printf( %I64d n , r); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a = min(m, n); if (a % 2 == 0) { cout << Malvika ; } else { cout << Akshat ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &f) { f = 0; _T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fu = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } template <typename T> struct hash_map_t { vector<T> v, val, nxt; vector<int> head; int mod, tot, lastv; T lastans; bool have_ans; hash_map_t(int md = 0) { head.clear(); v.clear(); val.clear(); nxt.clear(); tot = 0; mod = md; nxt.resize(1); v.resize(1); val.resize(1); head.resize(mod); have_ans = 0; } void clear() { *this = hash_map_t(mod); } bool count(int x) { int u = x % mod; for (register int i = head[u]; i; i = nxt[i]) { if (v[i] == x) { have_ans = 1; lastv = x; lastans = val[i]; return 1; } } return 0; } void ins(int x, int y) { int u = x % mod; nxt.push_back(head[u]); head[u] = ++tot; v.push_back(x); val.push_back(y); } int qry(int x) { if (have_ans && lastv == x) return lastans; count(x); return lastans; } }; const int N = 2505; int s[N][N], mx[N], mn[N]; char c[N][N]; int n, m, k; long long ans; inline int calc(int x, int y, int _x, int _y) { if (x > _x || y > _y) return 0; return s[_x][_y] - s[_x][y - 1] - s[x - 1][_y] + s[x - 1][y - 1]; } void solve(int x, int y, int _x, int _y) { if (x == _x || y == _y) return; if (_x - x == 1 && _y - y == 1) { if (calc(x + 1, y + 1, _x, _y) == k) ++ans; return; } if (_x - x >= _y - y) { int mid = (x + _x) >> 1; solve(x, y, mid, _y); solve(mid, y, _x, _y); for (register int i = y + 1; i <= _y; i++) { mn[0] = mx[0] = mid; for (register int j = 1; j <= k + 1; j++) mn[j] = x, mx[j] = _x; for (register int j = i; j <= _y; j++) { for (register int t = 1; t <= k + 1; t++) { while (calc(mn[t] + 1, i, mid, j) >= t) ++mn[t]; while (calc(mid + 1, i, mx[t], j) >= t) --mx[t]; } for (register int t = 0; t <= k; t++) { ans += (mn[t] - mn[t + 1]) * (mx[k - t + 1] - mx[k - t]); } } } } else { int mid = (y + _y) >> 1; solve(x, y, _x, mid); solve(x, mid, _x, _y); for (register int i = x + 1; i <= _x; i++) { mn[0] = mx[0] = mid; for (register int j = 1; j <= k + 1; j++) mn[j] = y, mx[j] = _y; for (register int j = i; j <= _x; j++) { for (register int t = 1; t <= k + 1; t++) { while (calc(i, mn[t] + 1, j, mid) >= t) ++mn[t]; while (calc(i, mid + 1, j, mx[t]) >= t) --mx[t]; } for (register int t = 0; t <= k; t++) { ans += (mn[t] - mn[t + 1]) * (mx[k - t + 1] - mx[k - t]); } } } } } int main() { read(n); read(m); read(k); for (register int i = 1; i <= n; i++) { scanf( %s , c[i] + 1); for (register int j = 1; j <= m; j++) { s[i][j] = s[i - 1][j] + s[i][j - 1] - s[i - 1][j - 1] + c[i][j] - 0 ; } } solve(0, 0, n, m); print(ans, n ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
function int f_no_no ();
int st = 2; st++; return st;
endfunction
function int f_no_st ();
static int st = 2; st++; return st;
endfunction
function int f_no_au ();
automatic int st = 2; st++; return st;
endfunction
function static int f_st_no ();
int st = 2; st++; return st;
endfunction
function static int f_st_st ();
static int st = 2; st++; return st;
endfunction
function static int f_st_au ();
automatic int st = 2; st++; return st;
endfunction
function automatic int f_au_no ();
int st = 2; st++; return st;
endfunction
function automatic int f_au_st ();
static int st = 2; st++; return st;
endfunction
function automatic int f_au_au ();
automatic int st = 2; st++; return st;
endfunction
initial begin
if (f_no_no() != 3) $stop;
if (f_no_no() != 4) $stop;
if (f_no_st() != 3) $stop;
if (f_no_st() != 4) $stop;
if (f_no_au() != 3) $stop;
if (f_no_au() != 3) $stop;
//
if (f_st_no() != 3) $stop;
if (f_st_no() != 4) $stop;
if (f_st_st() != 3) $stop;
if (f_st_st() != 4) $stop;
if (f_st_au() != 3) $stop;
if (f_st_au() != 3) $stop;
//
if (f_au_no() != 3) $stop;
if (f_au_no() != 3) $stop;
if (f_au_st() != 3) $stop;
if (f_au_st() != 4) $stop;
if (f_au_au() != 3) $stop;
if (f_au_au() != 3) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; string w = RPS ; string s; int t[4], n, m, a[105], ans[105]; int main() { ios::sync_with_stdio(0); int Q; cin >> Q; while (Q--) { memset(ans, 0, sizeof(ans)); cin >> n >> t[1] >> t[2] >> t[3] >> s; m = (n + 1) / 2; for (int i = 0; i < n; i++) switch (s[i]) { case R : a[i] = 2; break; case P : a[i] = 3; break; case S : a[i] = 1; break; } for (int i = 0; i < n; i++) if (t[a[i]]) { t[a[i]]--; ans[i] = a[i]; } if (n - (t[1] + t[2] + t[3]) < (n + 1) / 2) { cout << NO n ; continue; } cout << YES n ; for (int i = 0; i < n; i++) if (!ans[i]) { for (int j = 1; j <= 3; j++) if (t[j]) { t[j]--, ans[i] = j; break; } } for (int i = 0; i < n; i++) cout << w[ans[i]]; cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_8_V
`define SKY130_FD_SC_LS__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_8_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; long long gcd(long long x, long long y) { if (y == 0) return x; else return gcd(y, x % y); } long long ksm(long long a, long long b) { long long r = 1; while (b) { if (b & 1) r = (r * a) % mod; a = a * a % mod; b >>= 1; } return r; } void exgcd(long long a, long long b, long long& d, long long& x, long long& y) { if (!b) { d = a; x = 1; y = 0; } else { exgcd(b, a % b, d, y, x); y -= x * (a / b); } } long long inv(long long a, long long p) { long long d, x, y; exgcd(a, p, d, x, y); return d == 1 ? (x + p) % p : -1; } inline int read() { char c = getchar(); int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } const int maxn = 1e5 + 100; int n, m, k, t, a[1005][1005]; int r[1005], c[1005]; int main() { int x, y; cin >> x >> y; for (int i = 1; i <= x; i++) cin >> r[i]; for (int i = 1; i <= y; i++) cin >> c[i]; memset(a, 0, sizeof(a)); for (int i = 1; i <= x; i++) { if (r[i] == 0) a[i][1] = -1; else { for (int j = 1; j <= r[i]; j++) a[i][j] = 1; a[i][r[i] + 1] = -1; } } int flag = 1; for (int i = 1; i <= y; i++) { if (c[i] == 0) { if (a[1][i] == 1) flag = 0; a[1][i] = -1; } else { for (int j = 1; j <= c[i]; j++) { if (a[j][i] == -1) flag = 0; a[j][i] = 1; } if (a[c[i] + 1][i] == 1) flag = 0; a[c[i] + 1][i] = -1; } } if (!flag) { cout << 0 n ; return 0; } long long ans = 1; for (int i = 1; i <= x; i++) for (int j = 1; j <= y; j++) { if (a[i][j] == 0) ans = ans * 2ll % mod; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, ans = 0; cin >> n; long long int ar[n]; for (int i = 0; i < n; i++) { cin >> ar[i]; } sort(ar, ar + n); long long int s = 0; for (int i = 0; i < n; i++) { if (s <= ar[i]) { s += ar[i]; ans++; } } cout << ans; } int main() { int t = 1; while (t--) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long labs(long long a) { return a < 0 ? (-a) : a; } long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } const int MAXN = 1005; const int UNDEF = -1; const int IMPOS = INT_MAX - 2; char f[MAXN][MAXN]; int dph[MAXN], dpv[MAXN]; int n, m; int RecV(int i); int RecH(int j) { if (dph[j] != UNDEF) return dph[j]; dph[j] = IMPOS; for (int i = 0; i < n; i++) { if (f[i][j] == # ) { dph[j] = min(dph[j], RecV(i) + 1); } } return dph[j]; } int RecV(int i) { if (dpv[i] != UNDEF) return dpv[i]; dpv[i] = IMPOS; for (int j = 0; j < m; j++) { if (f[i][j] == # ) { dpv[i] = min(dpv[i], RecH(j) + 1); } } return dpv[i]; } int main() { cin >> n >> m; fill(dph, dph + MAXN, UNDEF); fill(dpv, dpv + MAXN, UNDEF); for (int(i) = 0; (i) < (n); (i)++) { cin >> f[i]; } dpv[n - 1] = 0; int res = RecV(0); if (res == IMPOS) { res = -1; } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int a, b, c, d; cin >> a >> b >> c >> d; cout << max(a + b, c + d) << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, q, num, tot, tp, cnt, ans, w[200100], head[200100], dfn[200100], c[200100], low[200100], sta[200100]; int dfc, sz[200100], d[200100], f[200100], son[200100], top[200100], tree[200100], mn[200100 * 4]; vector<int> v[200100]; multiset<int> s[200100]; struct point { int fr, to, nxt; } a[200100 * 2]; void add(int x, int y) { a[++tot].fr = x; a[tot].to = y; a[tot].nxt = head[x]; head[x] = tot; } void tarjan(int x) { dfn[x] = low[x] = ++num; sta[++tp] = x; for (int i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (!dfn[y]) { tarjan(y); low[x] = min(low[x], low[y]); if (low[y] == dfn[x]) { ++cnt; int now; do { now = sta[tp--]; add(cnt, now); add(now, cnt); } while (now != y); add(cnt, x); add(x, cnt); } } else low[x] = min(low[x], dfn[y]); } } void dfs1(int x, int fa) { f[x] = fa; d[x] = d[fa] + 1; sz[x] = 1; for (int i = head[x]; i; i = a[i].nxt) { int y = a[i].to; if (y == fa) continue; dfs1(y, x); sz[x] += sz[y]; if (sz[y] > sz[son[x]]) son[x] = y; } } void dfs2(int x, int lst) { top[x] = lst; dfn[x] = ++dfc; tree[dfc] = x; if (son[x]) dfs2(son[x], lst); for (int i = head[x]; i; i = a[i].nxt) if (!top[a[i].to]) dfs2(a[i].to, a[i].to); } void build(int x, int l, int r) { if (l == r) return mn[x] = w[tree[l]], void(); int mid = (l + r) >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); mn[x] = min(mn[x << 1], mn[x << 1 | 1]); } void modify(int x, int l, int r, int p, int y) { if (l == r) return mn[x] = y, void(); int mid = (l + r) >> 1; if (p <= mid) modify(x << 1, l, mid, p, y); else modify(x << 1 | 1, mid + 1, r, p, y); mn[x] = min(mn[x << 1], mn[x << 1 | 1]); } int query(int x, int l, int r, int L, int R) { if (l >= L && r <= R) return mn[x]; int mid = (l + r) >> 1, ret = 1e9; if (L <= mid) ret = min(ret, query(x << 1, l, mid, L, R)); if (R > mid) ret = min(ret, query(x << 1 | 1, mid + 1, r, L, R)); return ret; } int query(int x, int y, int ret = 1e9) { while (top[x] != top[y]) { if (d[top[x]] < d[top[y]]) swap(x, y); ret = min(ret, query(1, 1, cnt, dfn[top[x]], dfn[x])); x = f[top[x]]; } if (d[x] < d[y]) swap(x, y); ret = min(ret, query(1, 1, cnt, dfn[y], dfn[x])); if (y > n) ret = min(ret, w[f[y]]); return ret; } int main() { scanf( %d%d%d , &n, &m, &q); cnt = n; for (int i = 1; i <= n; i++) scanf( %d , &w[i]); for (int i = 1, x, y; i <= m; i++) scanf( %d%d , &x, &y), v[x].push_back(y), v[y].push_back(x); tarjan(1); dfs1(1, 0); dfs2(1, 1); memset(mn, 0x3f, sizeof(mn)); for (int i = 1; i <= n; i++) s[f[i]].insert(w[i]); for (int i = n + 1; i <= cnt; i++) w[i] = (*s[i].begin()); build(1, 1, cnt); for (int i = 1; i <= q; i++) { char ch[4]; int a, b; scanf( %s%d%d , ch + 1, &a, &b); if (ch[1] == C ) { if (f[a]) { multiset<int>::iterator pos = s[f[a]].find(w[a]); s[f[a]].erase(pos); s[f[a]].insert(b); w[f[a]] = (*s[f[a]].begin()); modify(1, 1, cnt, dfn[f[a]], (*s[f[a]].begin())); } w[a] = b; modify(1, 1, cnt, dfn[a], w[a]); } else printf( %d n , query(a, b)); } }
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#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const signed long long int LINF = LLONG_MAX; const double EPS = 1e-9; const int MOD = 1000000007; const int MAXN = 100001; const int ALPH = 26; const int DALPH = 52; string s; vector<int> z; vector<pair<int, int> > ans; vector<int> add, sum; int main() { cin >> s; z.resize((int)(s).size()); int l = 0, r = 0; z[0] = (int)(s).size(); for (int i = 1; i < (int)(s).size(); ++i) { int j = 0; if (i <= r) { int ind = i - l; j = min(z[ind], r - i + 1); } for (; i + j < (int)(s).size(); ++j) { if (s[j] != s[i + j]) { break; } } z[i] = j; if (i + j - 1 > r) { r = i + j - 1; l = i; } } add.resize((int)(s).size()); for (int i = 1; i < (int)(s).size(); ++i) { add[0]++; add[z[i]]--; } sum.resize((int)(s).size()); int cnt = 0; for (int i = 0; i < (int)(s).size(); ++i) { cnt += add[i]; sum[i] = cnt + 1; } for (int i = (int)(s).size() - 1; i >= 0; --i) { if (i + z[i] != (int)(s).size()) { continue; } ans.push_back(make_pair((z[i]), (sum[z[i] - 1]))); } printf( %d n , (int)(ans).size()); for (int i = 0; i < (int)(ans).size(); ++i) { printf( %d %d n , ans[i].first, ans[i].second); } }
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#include <bits/stdc++.h> using namespace std; int main() { int n, p; cin >> n >> p; string s; cin >> s; if (p > s.length() / 2) { reverse(s.begin(), s.end()); p = (n - p) + 1; } int sum = 0; int t[n], l = -1, r = 0; for (int i = 0; i < s.length() / 2; i++) { if (abs(int(s[i]) - int(s[n - i - 1])) > 13) { t[i] = 26 - abs(int(s[i]) - int(s[n - i - 1])); } else { t[i] = abs(int(s[i]) - int(s[n - i - 1])); } if (t[i] > 0) { r = i; if (l < 0) { l = i; } } sum += t[i]; } p--; if (l <= p && p <= r && p - l > r - p) { sum += r - p + r - l; } else if (l <= p && p <= r && p - l <= r - p) { sum += p - l + r - l; } else if (p <= l) { sum += r - p; } else if (r <= p) { sum += p - l; } if (l < 0) { cout << 0; } else { cout << sum; } }
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/*this module will realise the 8 Registers the processor provides.
Tofu tries not to create a bus system. The Idea is to hardwire everything, this will prevent floating wires.
*/
module regbank (addr1, addr2, addrdest, data1, data2, datadest, control, enable);
input wire [2:0] addr1, addr2, addrdest, datadest;
output wire [7:0] data1, data2;
input wire [2:0] control;
input wire enable;
reg [7:0] r0,r1,r2,r3,r4,r5,r6,r7;
always @ (posedge enable) begin
if (control[0]) begin
case(addr1)
0 : data1 = r0;
1 : data1 = r1;
2 : data1 = r2;
3 : data1 = r3;
4 : data1 = r4;
5 : data1 = r5;
6 : data1 = r6;
default : data1 = r7;
endcase
end
if (control[1]) begin
case(addr2)
0 : data2 = r0;
1 : data2 = r1;
2 : data2 = r2;
3 : data2 = r3;
4 : data2 = r4;
5 : data2 = r5;
6 : data2 = r6;
default : data1 = r7;
endcase
end
if (control[2]) begin
case(addrdest)
0 : r0 = datadest;
1 : r1 = datadest;
2 : r2 = datadest;
3 : r3 = datadest;
4 : r4 = datadest;
5 : r5 = datadest;
6 : r6 = datadest;
default : r7 = datadest;
endcase
end
end
endmodule
|
module fifo_TB;
reg clk;
reg reset;
reg rd;
reg wr;
reg[7:0] dataint;
fifo uttf(.rd(rd),.wr(wr),.din(dataint),.clock(clk),.reset(reset));
always
begin
clk =1'b1;
#10;
clk=1'b0;
#10;
end
initial
begin
reset = 1'b1;
#4 reset = 1'b0;
end
initial
begin
wr = 1'b0;
#3430;
wr=1'b1;
#34300;
wr = 1'b0;
#34300;
/*wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;*/
end
initial
begin
rd=1'b0;
#64300;
rd=1'b1;
#34300;
rd=1'b0;
#3430;
/*
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;*/
end
initial begin
#3430 dataint = 7'h1;
#34 dataint = 7'h0;
#34 dataint = 7'hA;
#34 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uttf);
#() $finish;
end
endmodule //
|
#include <bits/stdc++.h> using namespace std; char s[10]; int n; int notzero[12], cnt[12], ten[10], ans; int main() { ten[0] = 1; for (int i = 1; i < 8; ++i) ten[i] = 10 * ten[i - 1]; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %s , s); int len = strlen(s); notzero[s[0] - a ] = 1; for (int j = 0; j < len; ++j) cnt[s[j] - a ] += ten[len - j - 1]; } int zero = -1; for (int i = 0; i < 10; ++i) { if (notzero[i] == 0) { if (zero == -1 || cnt[i] > cnt[zero]) zero = i; } } vector<int> v; for (int i = 0; i < 10; ++i) { if (zero != i) v.push_back(cnt[i]); } sort(v.begin(), v.end()); for (int i = 0; i < 9; ++i) { ans += (9 - i) * v[i]; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void show(T a, int n) { for (int i = 0; i < n; ++i) cout << a[i] << ; cout << endl; } template <class T> void show(T a, int r, int l) { for (int i = 0; i < r; ++i) show(a[i], l); cout << endl; } const int N = 20; const int M = 5000; const int oo = 10000 * 10000 * 10; int n; char s[N + N]; long long h[N]; long long dp[N][N]; char tag[N][N]; void print(int i, int j) { if (!i && !j) return; if (tag[i][j] == H ) print(i - 1, j); else print(i, j - 1); putchar(tag[i][j]); } void solve() { int i, j, k; h[n] = 1; for (i = n - 1; i >= 1; --i) h[i] = h[i + 1] * 10; for (i = 1; i <= n; ++i) { int g = s[i] - 0 ; dp[i][0] = dp[i - 1][0] + g * h[i]; tag[i][0] = H ; dp[0][i] = dp[0][i - 1] + g * h[i]; tag[0][i] = M ; } for (i = 1; i <= n; ++i) { for (j = 1; j <= n; ++j) { int d = i + j; int g = s[d] - 0 ; dp[i][j] = (dp[i - 1][j] + g * h[i] > dp[i][j - 1] + g * h[j] ? dp[i - 1][j] + g * h[i] : dp[i][j - 1] + g * h[j]); if (dp[i - 1][j] + g * h[i] > dp[i][j - 1] + g * h[j]) tag[i][j] = H ; else tag[i][j] = M ; } } print(n, n); putchar(10); } int main() { int i, j, cas = 0; scanf( %d , &n); while (getchar() != 10) ; scanf( %s , s + 1); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_1_V
`define SKY130_FD_SC_HVL__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_1_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n, x[5000 + 5], y[5000 + 5], tot; int color[5000 + 5]; bool flag; int ksm(int b, int k) { int s = 1; while (k > 0) { if (k & 1) s = (1ll * s * b) % mod; k >>= 1; b = (1ll * b * b) % mod; } return s % mod; } int dis(int id1, int id2) { return abs(x[id1] - x[id2]) + abs(y[id1] - y[id2]); } void clearall() { flag = true; tot = 0; memset(color, 0, sizeof(color)); } void dfs(int u, int lim) { if (flag) { for (int i = 1; i <= n; i++) { if (flag) { if (u == i || dis(u, i) <= lim) continue; if (!color[i]) { color[i] = color[u] ^ 1; dfs(i, lim); } else { if (color[i] != color[u]) continue; flag = false; return; } } } } } bool check(int lim) { int i, j; clearall(); for (i = 1; i <= n; i++) if (!color[i]) { tot++; color[i] = 2; dfs(i, lim); if (!flag) break; } return flag; } int main() { int i, ans = -1; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); int l = 0, r = 10000; while (l < r - 5) { int mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } for (i = l; i <= r; i++) if (check(i)) { ans = i; break; } printf( %d n , ans); printf( %d n , ksm(2, tot)); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << ? << ; fflush(stdout); for (int i = 0; i < 100; i++) { cout << i << ; fflush(stdout); } cout << endl; int n; cin >> n; cout << ? << ; fflush(stdout); long long a = 0; for (int i = 0; i < 100; i++) { a += (1 << 7); cout << a << ; fflush(stdout); } cout << endl; int b; cin >> b; bitset<14> x(n), y(b), z; for (int i = 0; i < 14; i++) { if (i < 7) z[i] = y[i]; else z[i] = x[i]; } cout << ! << z.to_ulong(); }
|
#include <bits/stdc++.h> using namespace std; int n, v0, f[200012], nu = 0; struct eve { int x, v, l; inline bool operator<(const eve &b) const { return (x < b.x) || ((x == b.x) && (v < b.v)); } }; multiset<eve> s; inline void cha(int x, int v) { f[x] = v; if (v + v0 <= 1e9) s.insert((eve){v + v0, 0, -1}); } int d[200012 << 2], ma[200012 << 2]; inline void Add(int p, int v) { d[p] += v; ma[p] += v; } inline void pd(int x) { if (d[x]) { Add(x << 1, d[x]); Add(x << 1 | 1, d[x]); d[x] = 0; } } void build(int p, int l, int r) { ma[p] = r; if (l == r) return; int mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); } void change(int p, int l, int r, int L, int R, int v) { if ((R < l) || (r < L)) return; if ((L <= l) && (r <= R)) { Add(p, v); return; } pd(p); int mid = (l + r) >> 1; change(p << 1, l, mid, L, R, v); change(p << 1 | 1, mid + 1, r, L, R, v); ma[p] = max(ma[p << 1], ma[p << 1 | 1]); } int Ask(int p, int l, int r, int L, int R) { if ((R < l) || (r < L)) return 0; if ((L <= l) && (r <= R)) return ma[p]; pd(p); int mid = (l + r) >> 1; return max(Ask(p << 1, l, mid, L, R), Ask(p << 1 | 1, mid + 1, r, L, R)); } int main() { scanf( %d%d , &n, &v0); int i, l, r, x, o; eve p; memset(f, 0x3f, sizeof(f)); build(1, 0, n); for (i = 1; i <= n; i++) { scanf( %d%d , &l, &r); if (r < 0) continue; l = max(l, 0); s.insert((eve){l, 1, l}); s.insert((eve){r + 1, -1, l}); } cha(r = 0, -0x3f3f3f3f); while (!s.empty()) { p = *s.begin(); nu += p.v; l = p.x; s.erase(s.begin()); if (p.l >= 0) change(1, 0, n, lower_bound(f, f + n + 1, p.l) - f, n, -p.v); if ((!s.empty()) && ((s.begin()->x) == l)) continue; x = upper_bound(f, f + n + 1, l - v0) - f - 1; o = nu + Ask(1, 0, n, 0, x); while ((r < n) && (r < o)) cha(++r, l); } printf( %d , r); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_8_V
`define SKY130_FD_SC_HD__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { int s, k; cin >> k >> s; while (s >= 1) { for (int i = 1; i <= k; i++) { if (s >= i) { s = s - i; } else { cout << s << endl; return 0; } } } cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using D = double; using uint = unsigned int; const int maxn = 100005; ll t[maxn], others[maxn], me[maxn]; int f[maxn]; vector<int> from[maxn]; int kv[maxn]; ll ans[maxn]; int n, m; multiset<ll> global; multiset<ll> cur[maxn]; bool in[maxn], in2[maxn]; void pop(int x) { if (!in[x]) return; in[x] = false; if (cur[x].size() > 0) { global.erase(global.find(others[x] + *cur[x].begin())); global.erase(global.find(others[x] + *cur[x].rbegin())); } } void push(int x) { if (in[x]) return; in[x] = true; if (cur[x].size() > 0) { global.insert(others[x] + *cur[x].begin()); global.insert(others[x] + *cur[x].rbegin()); } } void delfrom(int a, int b) { if (!in2[a]) return; in2[a] = false; cur[b].erase(cur[b].find(ans[a])); } void addto(int a, int b) { if (in2[a]) return; in2[a] = true; cur[b].insert(ans[a]); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %lld , &t[i]); for (int i = 0; i < n; i++) { scanf( %d , &f[i]); f[i]--; kv[i]++; kv[f[i]]++; from[f[i]].push_back(i); } for (int i = 0; i < n; i++) { others[i] = t[i] / (kv[i] + 1); me[i] = t[i] - (kv[i] * others[i]); } for (int i = 0; i < n; i++) { ans[i] = me[i]; for (auto z : from[i]) ans[i] += others[z]; } for (int i = 0; i < n; i++) { for (auto z : from[i]) { cur[i].insert(ans[z]); } if (cur[i].size() > 0) { global.insert(others[i] + *cur[i].begin()); global.insert(others[i] + *cur[i].rbegin()); } in[i] = true; in2[i] = true; } for (int i = 0; i < m; i++) { int t; scanf( %d , &t); if (t == 1) { int a, b; scanf( %d%d , &a, &b); a--, b--; int was = f[a]; pop(a); pop(was); pop(f[was]); pop(f[f[was]]); pop(b); pop(f[b]); pop(f[f[b]]); delfrom(a, was); delfrom(was, f[was]); delfrom(f[was], f[f[was]]); delfrom(b, f[b]); delfrom(f[b], f[f[b]]); ans[was] -= others[a]; ans[f[was]] -= others[was]; kv[was]--; others[was] = ::t[was] / (kv[was] + 1); ans[was] -= me[was]; me[was] = ::t[was] - (kv[was] * others[was]); ans[was] += me[was]; ans[f[was]] += others[was]; f[a] = b; ans[b] += others[a]; ans[f[b]] -= others[b]; kv[b]++; others[b] = ::t[b] / (kv[b] + 1); ans[b] -= me[b]; me[b] = ::t[b] - (kv[b] * others[b]); ans[b] += me[b]; ans[f[b]] += others[b]; addto(a, b); addto(was, f[was]); addto(f[was], f[f[was]]); addto(b, f[b]); addto(f[b], f[f[b]]); push(a); push(was); push(f[was]); push(f[f[was]]); push(b); push(f[b]); push(f[f[b]]); } else if (t == 2) { int x; scanf( %d , &x); x--; printf( %lld n , ans[x] + others[f[x]]); } else { printf( %lld %lld n , *global.begin(), *global.rbegin()); } } return 0; }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtwiz_userdata_rx #(
parameter integer P_RX_USER_DATA_WIDTH = 32,
parameter integer P_RX_DATA_DECODING = 0,
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1
)(
input wire [(P_TOTAL_NUMBER_OF_CHANNELS*128)-1:0] rxdata_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] rxctrl0_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] rxctrl1_in,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH)-1:0] gtwiz_userdata_rx_out
);
// -------------------------------------------------------------------------------------------------------------------
// Receiver user data width sizing conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin : gen_gtwiz_userdata_rx_main
genvar ch_idx;
// If receiver data decoding is either not raw mode, or is raw mode but user data width is not modulus 10, then
// simply assign the user-facing data vector with the active data bits from the transceiver-facing RXDATA vector.
if ((P_RX_DATA_DECODING != 0) ||
((P_RX_DATA_DECODING == 0) && (P_RX_USER_DATA_WIDTH % 10 != 0))) begin : gen_rxdata
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_assign
assign gtwiz_userdata_rx_out[(P_RX_USER_DATA_WIDTH*ch_idx)+P_RX_USER_DATA_WIDTH-1:
(P_RX_USER_DATA_WIDTH*ch_idx)] =
rxdata_in[(128*ch_idx)+P_RX_USER_DATA_WIDTH-1:(128*ch_idx)];
end
end
// If receiver data decoding is raw mode and user data width is modulus 10, then assign the user-facing data vector
// with the specified combination of transceiver-facing RXDATA, RXCTRL0, and RXCTRL1 vectors. The interleaving of
// these vectors is always in a repeating 8-1-1 bit pattern, scaling with the user data width size.
else begin : gen_rxdata_rxctrl
case (P_RX_USER_DATA_WIDTH)
20:
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width20
assign gtwiz_userdata_rx_out [(ch_idx*20)+19:(ch_idx*20)] =
{rxctrl1_in[(ch_idx* 16)+1],
rxctrl0_in[(ch_idx* 16)+1],
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
rxctrl1_in[(ch_idx* 16)],
rxctrl0_in[(ch_idx* 16)],
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
end
40:
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width40
assign gtwiz_userdata_rx_out [(ch_idx*40)+39:(ch_idx*40)] =
{rxctrl1_in[(ch_idx* 16)+3],
rxctrl0_in[(ch_idx* 16)+3],
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
rxctrl1_in[(ch_idx* 16)+2],
rxctrl0_in[(ch_idx* 16)+2],
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
rxctrl1_in[(ch_idx* 16)+1],
rxctrl0_in[(ch_idx* 16)+1],
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
rxctrl1_in[(ch_idx* 16)],
rxctrl0_in[(ch_idx* 16)],
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
end
80:
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width80
assign gtwiz_userdata_rx_out [(ch_idx*80)+79:(ch_idx*80)] =
{rxctrl1_in[(ch_idx* 16)+7],
rxctrl0_in[(ch_idx* 16)+7],
rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
rxctrl1_in[(ch_idx* 16)+6],
rxctrl0_in[(ch_idx* 16)+6],
rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
rxctrl1_in[(ch_idx* 16)+5],
rxctrl0_in[(ch_idx* 16)+5],
rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
rxctrl1_in[(ch_idx* 16)+4],
rxctrl0_in[(ch_idx* 16)+4],
rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
rxctrl1_in[(ch_idx* 16)+3],
rxctrl0_in[(ch_idx* 16)+3],
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
rxctrl1_in[(ch_idx* 16)+2],
rxctrl0_in[(ch_idx* 16)+2],
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
rxctrl1_in[(ch_idx* 16)+1],
rxctrl0_in[(ch_idx* 16)+1],
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
rxctrl1_in[(ch_idx* 16)],
rxctrl0_in[(ch_idx* 16)],
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
end
160:
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width160
assign gtwiz_userdata_rx_out [(ch_idx*160)+159:(ch_idx*160)] =
{rxctrl1_in[(ch_idx* 16)+15],
rxctrl0_in[(ch_idx* 16)+15],
rxdata_in [(ch_idx*128)+127:(ch_idx*128)+120],
rxctrl1_in[(ch_idx* 16)+14],
rxctrl0_in[(ch_idx* 16)+14],
rxdata_in [(ch_idx*128)+119:(ch_idx*128)+112],
rxctrl1_in[(ch_idx* 16)+13],
rxctrl0_in[(ch_idx* 16)+13],
rxdata_in [(ch_idx*128)+111:(ch_idx*128)+104],
rxctrl1_in[(ch_idx* 16)+12],
rxctrl0_in[(ch_idx* 16)+12],
rxdata_in [(ch_idx*128)+103:(ch_idx*128)+96],
rxctrl1_in[(ch_idx* 16)+11],
rxctrl0_in[(ch_idx* 16)+11],
rxdata_in [(ch_idx*128)+95:(ch_idx*128)+88],
rxctrl1_in[(ch_idx* 16)+10],
rxctrl0_in[(ch_idx* 16)+10],
rxdata_in [(ch_idx*128)+87:(ch_idx*128)+80],
rxctrl1_in[(ch_idx* 16)+9],
rxctrl0_in[(ch_idx* 16)+9],
rxdata_in [(ch_idx*128)+79:(ch_idx*128)+72],
rxctrl1_in[(ch_idx* 16)+8],
rxctrl0_in[(ch_idx* 16)+8],
rxdata_in [(ch_idx*128)+71:(ch_idx*128)+64],
rxctrl1_in[(ch_idx* 16)+7],
rxctrl0_in[(ch_idx* 16)+7],
rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
rxctrl1_in[(ch_idx* 16)+6],
rxctrl0_in[(ch_idx* 16)+6],
rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
rxctrl1_in[(ch_idx* 16)+5],
rxctrl0_in[(ch_idx* 16)+5],
rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
rxctrl1_in[(ch_idx* 16)+4],
rxctrl0_in[(ch_idx* 16)+4],
rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
rxctrl1_in[(ch_idx* 16)+3],
rxctrl0_in[(ch_idx* 16)+3],
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
rxctrl1_in[(ch_idx* 16)+2],
rxctrl0_in[(ch_idx* 16)+2],
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
rxctrl1_in[(ch_idx* 16)+1],
rxctrl0_in[(ch_idx* 16)+1],
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
rxctrl1_in[(ch_idx* 16)],
rxctrl0_in[(ch_idx* 16)],
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
end
default:
begin : gen_default
// The default case is a configuration error scenario should never be exercised
assign gtwiz_userdata_rx_out = {P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH{1'b1}};
end
endcase
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int ok(double x, double a[]) { double z1 = 0, z2 = 0; for (int i = 0; i < n; i++) { if (x - a[i] > 0) { z1 += x - a[i]; } if (x - a[i] < 0) { double ans = 1 - (k * (double)1) / 100; z2 += (a[i] - x) * ans; } } if (z1 <= z2) { return 1; } return 0; } int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; double a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); double ans = 0, low = 0, high = 10000; int z = 0; while (low < high) { z++; double mid = (low + high) / 2; if (ok(mid, a) == 1) { low = mid; ans = mid; } else { high = mid; } if (z == 999) { break; } } cout << setprecision(12) << ans; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: nine_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module nine_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/nine_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/nine_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: tx_valid_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tx_valid_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [7:0] sub_wire1;
wire [0:0] sub_wire2;
wire rdempty = sub_wire0;
wire [7:0] wrusedw = sub_wire1[7:0];
wire [0:0] q = sub_wire2[0:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL data[0..0]
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL q[0..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_valid_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2, k, a; cin >> n1 >> n2; vector<int> arr1, arr2; for (int l = 0; l < n1; l++) { cin >> a; arr1.push_back(a); } for (int l = 0; l < n2; l++) { cin >> a; arr2.push_back(a); } sort(arr1.begin(), arr1.end()); sort(arr2.begin(), arr2.end()); for (int k = 0; k < arr1.size(); k++) { for (int l = 0; l < arr2.size(); l++) { if (arr1[k] == arr2[l]) { cout << arr1[k] << n ; return 0; } } } if (arr1[0] < arr2[0]) { k = 10 * arr1[0] + arr2[0]; cout << k << n ; } else { k = 10 * arr2[0] + arr1[0]; cout << k << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 5e5 + 10; vector<int> v[31]; long long par[31], X[31], Y[31], vis[31]; int xxx = 31; void bfs() { queue<tuple<int, int, int>> qu; qu.push(make_tuple(1, 0, xxx)); vis[1] = 1; X[1] = Y[1] = 1ll << xxx; while (!qu.empty()) { tuple<int, int, int> xx = qu.front(); qu.pop(); int s = get<0>(xx); int dd = get<1>(xx); int pp = get<2>(xx); int dir = 1; for (auto it : v[s]) { if (vis[it]) continue; vis[it] = 1; if (dir == dd) dir++; if (dir == 1) { X[it] = X[s] + (1ll << (pp - 1)); Y[it] = Y[s]; qu.push(make_tuple(it, 2, pp - 1)); dir++; } else if (dir == 2) { X[it] = X[s] - (1ll << (pp - 1)); Y[it] = Y[s]; qu.push(make_tuple(it, 1, pp - 1)); dir++; } else if (dir == 3) { X[it] = X[s]; Y[it] = Y[s] - (1ll << (pp - 1)); qu.push(make_tuple(it, 4, pp - 1)); dir++; } else { X[it] = X[s]; Y[it] = Y[s] + (1ll << (pp - 1)); qu.push(make_tuple(it, 3, pp - 1)); dir++; } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int flag = 0; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); if (v[a].size() > 4 || v[b].size() > 4) flag = 1; } if (flag) puts( NO ); else { bfs(); cout << YES n ; for (int i = 1; i <= n; i++) cout << X[i] << << Y[i] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1000 + 5; const int mod = 1000 * 1000 * 1000 + 7; int a[65], b[65]; int main() { ios_base::sync_with_stdio(false); long long l, r; cin >> l >> r; for (int i = 0; l > 0; l /= 2, i++) a[i] = l % 2; for (int i = 0; r > 0; r /= 2, i++) b[i] = r % 2; int i; for (i = 60; i >= 0 && a[i] == b[i]; i--) ; if (i == -1) cout << 0 << endl; else cout << (1ll << (i + 1)) - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, SF, FS; SF = FS = 0; string flights; cin >> n >> flights; for (int i = 0; i < flights.size() - 1; i++) { if (flights[i] == S && flights[i + 1] == F ) { SF++; } else if (flights[i] == F && flights[i + 1] == S ) { FS++; } } if (SF > FS) { cout << YES ; } else { cout << NO ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// File name : sata_test_top.v
// Note : This is the top module which connects SATA controller,
// Microblaze System and SATA test logic.
// Test/Verification Environment
// Dependencies : Nil
///////////////////////////////////////////////////////////////////////////////
module sata_test_top(
input fpga_0_RS232_Uart_1_RX_pin,
output fpga_0_RS232_Uart_1_TX_pin,
input fpga_0_clk_1_sys_clk_pin,
input fpga_0_rst_1_sys_rst_pin,
input TILE0_REFCLK_PAD_P_IN, // MGTCLKA, clocks GTP_X0Y0-2
input TILE0_REFCLK_PAD_N_IN, // MGTCLKA
input GTPRESET_IN, // GTP initialization
output TILE0_PLLLKDET_OUT, // GTP PLL locked
output TXP0_OUT, // SATA Connector TX P pin
output TXN0_OUT, // SATA Connector TX N pin
input RXP0_IN, // SATA Connector RX P pin
input RXN0_IN, // SATA Connector RX N pin
output DCMLOCKED_OUT, // PHY Layer DCM locked
output LINKUP, // SATA PHY initialisation completed LINK UP
output GEN2, // 1 when a SATA2 device detected, 0 when SATA1 device detected
output PHY_CLK_OUT, // PHY layer clock out
output CLK_OUT // LINK and Transport Layer clock out CLK_OUT = PHY_CLK_OUT / 2
);
// input fpga_0_RS232_Uart_1_RX_pin;
// output fpga_0_RS232_Uart_1_TX_pin;
// input fpga_0_clk_1_sys_clk_pin;
// input fpga_0_rst_1_sys_rst_pin;
wire host_read_en;
wire host_write_en;
wire [4:0] host_addr_reg;
wire [31:0] host_to_trnsp_data;
wire [31:0] trnsp_to_host_data;
wire reset_out;
wire write_hold_u;
wire read_hold_u;
wire dma_rqst;
wire [31:0] dma_rx_data_out;
wire dma_rx_ren;
wire [31:0] dma_tx_data_in;
wire dma_tx_wen;
wire sata_reset;
wire [31:0] MB2IP_Addr_pin;
wire MB2IP_CS_pin;
wire MB2IP_RNW_pin;
wire [31:0] MB2IP_Data_pin;
wire [31:0] IP2mb_Data_pin;
wire IP2MB_RdAck_pin;
wire IP2MB_WrAck_pin;
wire IP2MB_Error_pin;
wire [3:0] MB2IP_BE_pin;
wire ipf;
wire dma_terminated;
wire r_err;
wire illegal_state;
wire tx_fifo_reset;
wire rx_fifo_reset;
wire mb_rst_0;
reg mb_rst_1;
reg mb_rst_2;
reg mb_rst_3;
wire mb_rst_debounce;
reg fpga_0_rst_1_sys_rst_pin_1;
reg fpga_0_rst_1_sys_rst_pin_2;
always @(posedge fpga_0_clk_1_sys_clk_pin)
begin
fpga_0_rst_1_sys_rst_pin_1 <= fpga_0_rst_1_sys_rst_pin;
fpga_0_rst_1_sys_rst_pin_2 <= fpga_0_rst_1_sys_rst_pin_1;
end
assign mb_rst_0 = fpga_0_rst_1_sys_rst_pin_2;
always @(posedge fpga_0_clk_1_sys_clk_pin)
begin
mb_rst_1 <= mb_rst_0;
mb_rst_2 <= mb_rst_1;
mb_rst_3 <= mb_rst_2;
end
assign mb_rst_debounce = (mb_rst_1 & mb_rst_2 & mb_rst_3);
//assign data_out = trnsp_to_host_data;
//assign data_out = dma_rqst? dma_rx_data_out : trnsp_to_host_data;
(* BOX_TYPE = "user_black_box" *)
system mb_system (
.fpga_0_RS232_Uart_1_RX_pin (fpga_0_RS232_Uart_1_RX_pin),
.fpga_0_RS232_Uart_1_TX_pin (fpga_0_RS232_Uart_1_TX_pin),
.fpga_0_clk_1_sys_clk_pin (fpga_0_clk_1_sys_clk_pin),
.fpga_0_rst_1_sys_rst_pin (mb_rst_debounce),
.sata_test_logic_0_MB2IP_Clk_pin (MB2IP_Clk_pin),
.sata_test_logic_0_MB2IP_Reset_pin (MB2IP_Reset_pin),
.sata_test_logic_0_MB2IP_Addr_pin (MB2IP_Addr_pin),
.sata_test_logic_0_MB2IP_CS_pin (MB2IP_CS_pin),
.sata_test_logic_0_MB2IP_RNW_pin (MB2IP_RNW_pin),
.sata_test_logic_0_MB2IP_Data_pin (MB2IP_Data_pin),
.sata_test_logic_0_MB2IP_BE_pin (MB2IP_BE_pin),
.sata_test_logic_0_IP2mb_Data_pin (IP2mb_Data_pin),
.sata_test_logic_0_IP2MB_RdAck_pin (IP2MB_RdAck_pin),
.sata_test_logic_0_IP2MB_WrAck_pin (IP2MB_WrAck_pin),
.sata_test_logic_0_IP2MB_Error_pin (IP2MB_Error_pin)
);
// Instantiate the module
SATA_TOP SATA_TOP1(
.TILE0_REFCLK_PAD_P_IN (TILE0_REFCLK_PAD_P_IN),
.TILE0_REFCLK_PAD_N_IN (TILE0_REFCLK_PAD_N_IN),
.GTPRESET_IN (sata_reset), //(GTPRESET_IN),
.TILE0_PLLLKDET_OUT (TILE0_PLLLKDET_OUT),
.TXP0_OUT (TXP0_OUT),
.TXN0_OUT (TXN0_OUT),
.RXP0_IN (RXP0_IN),
.RXN0_IN (RXN0_IN),
.DCMLOCKED_OUT (DCMLOCKED_OUT),
.LINKUP (LINKUP),
.GEN2 (GEN2),
.PHY_CLK_OUT (PHY_CLK_OUT),
.CLK_OUT (CLK_OUT),
.HOST_READ_EN (host_read_en),
.HOST_WRITE_EN (host_write_en),
.HOST_ADDR_REG (host_addr_reg),
.HOST_DATA_IN (host_to_trnsp_data),
.HOST_DATA_OUT (trnsp_to_host_data),
.RESET_OUT (reset_out),
.WRITE_HOLD_U (write_hold_u),
.READ_HOLD_U (read_hold_u),
.PIO_CLK_IN (CLK_OUT),
.DMA_CLK_IN (CLK_OUT),
.DMA_RQST (dma_rqst),
.DMA_RX_DATA_OUT (dma_rx_data_out),
.DMA_RX_REN (dma_rx_ren),
.DMA_TX_DATA_IN (dma_tx_data_in),
.DMA_TX_WEN (dma_tx_wen),
.CE (1'b1),
.IPF (ipf),
.DMA_TERMINATED (dma_terminated),
.R_ERR (r_err),
.ILLEGAL_STATE (illegal_state),
.RX_FIFO_RESET (rx_fifo_reset),
.TX_FIFO_RESET (tx_fifo_reset)
);
// Instantiate the module
sata_test sata_test1(
.CLK (CLK_OUT),
.RESET (reset_out),
.CTRL_READ_EN (host_read_en),
.CTRL_WRITE_EN (host_write_en),
.CTRL_ADDR_REG (host_addr_reg),
.CTRL_DATA_OUT (host_to_trnsp_data),
.CTRL_DATA_IN (trnsp_to_host_data),
.SATA_WR_HOLD_IN (write_hold_u),
.SATA_RD_HOLD_IN (read_hold_u),
.DMA_RQST_OUT (dma_rqst),
.DMA_RX_DATA_IN (dma_rx_data_out),
.DMA_RX_REN_OUT (dma_rx_ren),
.DMA_TX_DATA_OUT (dma_tx_data_in),
.DMA_TX_WEN_OUT (dma_tx_wen),
.MB_ADRESS (MB2IP_Addr_pin),
.MB_CS (MB2IP_CS_pin),
.MB_RNW (MB2IP_RNW_pin),
.MB_DATA_IN (MB2IP_Data_pin),
.MB_DATA_OUT (IP2mb_Data_pin),
.MB_CLK (MB2IP_Clk_pin),
.MB_RESET (MB2IP_Reset_pin),
.GTP_RESET_IN (GTPRESET_IN),
.SATA_RESET_OUT (sata_reset),
.INTERRUPT_IN (ipf),
.DMA_TERMINATED (dma_terminated),
.R_ERR (r_err),
.ILLEGAL_STATE (illegal_state),
.LINKUP (LINKUP),
.MB_RD_ACK (IP2MB_RdAck_pin),
.RX_FIFO_RESET_OUT (rx_fifo_reset),
.TX_FIFO_RESET_OUT (tx_fifo_reset)
);
assign IP2MB_WrAck_pin = MB2IP_CS_pin && !MB2IP_RNW_pin;
assign IP2MB_Error_pin = 0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
parameter DW = 4;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] drv; // To/From test1 of Test1.v
wire [DW-1:0] drv2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Inouts
.drv (drv[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.drv2 (drv2[DW-1:0]),
// Inputs
.drv_a (drv_a[DW-1:0]),
.drv_b (drv_b[DW-1:0]),
.drv_e (drv_e[DW-1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, drv};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n", $time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv
);
wire drv_0, drv_1, drv_2, drv_3;
bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1
bufa3 (drv_3, drv_a[3], drv_e[3]),
bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule
module Test2 #(
parameter DW = 4
)(
input wire [DW-1:0] drv_a,
input wire [DW-1:0] drv_b,
input wire [DW-1:0] drv_e,
inout wire [DW-1:0] drv2
);
wire [DW-1:0] drv_all;
bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
assign drv2 = drv_all;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYGATE4S18_BEHAVIORAL_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s18 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; bool comp(long long a, long long b) { if (a > b) return true; else return false; } int isP(long long n) { if (n == 1) return 0; if (n == 2 || n == 3) return 1; for (long long i = 2; i <= sqrt(n); i++) { if (n % i == 0) return 0; } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t, n, k, va; bool ha; cin >> t; while (t--) { cin >> n >> k; if (n == 0) ha = false; else if (n == 1 || n == 2) ha = true; else if (n == 3) { if (k == 3) ha = true; else ha = false; } else { if (k % 3 != 0) { va = n % 3; if (va == 0) ha = false; else ha = true; } else { n %= (k + 1); if (n % 3 == 0) ha = false; else ha = true; if (n == k) ha = true; } } if (ha) cout << Alice n ; else cout << Bob n ; } return 0; }
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o);
parameter width = 16;
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [width-1:0] mask_i;
output pn_o;
reg [width-1:0] shifter;
wire parity = ^(shifter & mask_i);
always @(posedge clk_i)
if (rst_i | ~ena_i)
shifter <= #5 1;
else
if (strobe_i)
shifter <= #5 {shifter[width-2:0],parity};
assign pn_o = shifter[0];
endmodule // lfsr
|
#include <bits/stdc++.h> using namespace std; int n, deg[51]; long long dp[2][51][51][51][51]; inline void add(long long &a, long long b) { a += b; } void transition3(int b, int p1, int p2, int c1, int c2) { long long from = dp[b][p1][p2][c1][c2] % 1000000007; b ^= 1; if (p1 > 0) add(dp[b][p1 - 1][p2][c1][c2 + 1], from * p1); if (p2 > 0) add(dp[b][p1 + 1][p2 - 1][c1][c2 + 1], from * p2); if (p1 > 0 && c1 > 0) add(dp[b][p1 - 1][p2][c1 - 1 + 1][c2], from * p1 * c1); if (p2 > 0 && c1 > 0) add(dp[b][p1 + 1][p2 - 1][c1 - 1 + 1][c2], from * p2 * c1); if (p1 > 0 && c2 > 0) add(dp[b][p1 - 1][p2][c1 + 1 + 1][c2 - 1], from * p1 * c2); if (p2 > 0 && c2 > 0) add(dp[b][p1 + 1][p2 - 1][c1 + 1 + 1][c2 - 1], from * p2 * c2); if (p1 > 0 && c1 > 1) add(dp[b][p1 - 1][p2][c1 - 2][c2], from * p1 * c1 * (c1 - 1) / 2); if (p2 > 0 && c1 > 1) add(dp[b][p1 + 1][p2 - 1][c1 - 2][c2], from * p2 * c1 * (c1 - 1) / 2); if (p1 > 0 && c2 > 1) add(dp[b][p1 - 1][p2][c1 + 2][c2 - 2], from * p1 * c2 * (c2 - 1) / 2); if (p2 > 0 && c2 > 1) add(dp[b][p1 + 1][p2 - 1][c1 + 2][c2 - 2], from * p2 * c2 * (c2 - 1) / 2); if (p1 > 0 && c1 > 0 && c2 > 0) add(dp[b][p1 - 1][p2][c1 - 1 + 1][c2 - 1], from * p1 * c1 * c2); if (p2 > 0 && c1 > 0 && c2 > 0) add(dp[b][p1 + 1][p2 - 1][c1 - 1 + 1][c2 - 1], from * p2 * c1 * c2); if (p1 == 0 && p2 == 0 && c1 > 0) add(dp[b][c1 - 1][c2][0][1], from * c1); if (p1 == 0 && p2 == 0 && c2 > 0) add(dp[b][c1 + 1][c2 - 1][0][1], from * c2); } void transition2(int b, int p1, int p2, int c1, int c2) { long long from = dp[b][p1][p2][c1][c2] % 1000000007; b ^= 1; if (p1 > 0) add(dp[b][p1 - 1][p2][c1 + 1][c2], from * p1); if (p2 > 0) add(dp[b][p1 + 1][p2 - 1][c1 + 1][c2], from * p2); if (p1 > 0 && c1 > 0) add(dp[b][p1 - 1][p2][c1 - 1][c2], from * p1 * c1); if (p2 > 0 && c1 > 0) add(dp[b][p1 + 1][p2 - 1][c1 - 1][c2], from * p2 * c1); if (p1 > 0 && c2 > 0) add(dp[b][p1 - 1][p2][c1 + 1][c2 - 1], from * p1 * c2); if (p2 > 0 && c2 > 0) add(dp[b][p1 + 1][p2 - 1][c1 + 1][c2 - 1], from * p2 * c2); if (p1 == 0 && p2 == 0 && c1 > 0) add(dp[b][c1 - 1][c2][1][0], from * c1); if (p1 == 0 && p2 == 0 && c2 > 0) add(dp[b][c1 + 1][c2 - 1][1][0], from * c2); } void solveDP() { int ip1 = 0, ip2 = 0, ic1 = 0, ic2 = 0; if (deg[1] == 3 && deg[2] == 3) ip2 = 1, ic2 = 1; if (deg[1] == 3 && deg[2] == 2) ip2 = 1, ic1 = 1; if (deg[1] == 2 && deg[2] == 3) ip1 = 1, ic2 = 1; if (deg[1] == 2 && deg[2] == 2) ip1 = 1, ic1 = 1; dp[0][ip1][ip2][ic1][ic2] = 1; for (int v = 2; v <= n - 1; ++v) { int b = (v & 1); for (int p1 = 0; p1 <= v; ++p1) { for (int p2 = 0; p1 + p2 <= v; ++p2) { for (int c1 = 0; p1 + p2 + c1 <= v; ++c1) { for (int c2 = 0; p1 + p2 + c1 + c2 <= v; ++c2) { dp[b ^ 1][p1][p2][c1][c2] = 0; } } } } for (int p1 = 0; p1 <= v; ++p1) { for (int p2 = 0; p1 + p2 <= v; ++p2) { for (int c1 = 0; p1 + p2 + c1 <= v; ++c1) { for (int c2 = 0; p1 + p2 + c1 + c2 <= v; ++c2) { if (deg[v + 1] == 3) transition3(b, p1, p2, c1, c2); else transition2(b, p1, p2, c1, c2); } } } } } cout << dp[(n & 1)][0][0][0][0] % 1000000007; } void solve() { cin >> n; for (int i = 1; i <= (n); ++i) cin >> deg[i]; solveDP(); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int d[2 * N], c[2 * N], n, k, l, p, a = N, q, w, u; string s; int main() { cin >> n >> k >> l >> s; q = 0; w = N; while (q < w) { p = (q + w) >> 1; for (int i = n - 1; i >= 0; i--) { d[i] = d[i + 1] + (s[i] > 96); c[i] = c[i + 1]; if (d[i + l] + p < d[i]) d[i] = d[i + l] + p, c[i] = c[i + l] + 1; } if (c[0] > k) q = p + 1; else w = p, u = d[0] - p * k; } a = min(a, u); for (auto &p : s) p = (p + 32) % 125; q = 0; w = N; while (q < w) { p = (q + w) >> 1; for (int i = n - 1; i >= 0; i--) { d[i] = d[i + 1] + (s[i] > 96); c[i] = c[i + 1]; if (d[i + l] + p < d[i]) d[i] = d[i + l] + p, c[i] = c[i + l] + 1; } if (c[0] > k) q = p + 1; else w = p, u = d[0] - p * k; } a = min(a, u); printf( %i n , a); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int a[1000050]; vector<int> vec[1000050]; int pos[1000050]; int main() { int n, x; scanf( %d%d , &n, &x); for (int i = 0; i < n; i++) { scanf( %d , a + i); vec[a[i]].push_back(i); } pos[x + 1] = n; int st = 1; for (int i = x; i; i--) { pos[i] = pos[i + 1]; if (vec[i].size()) { if (vec[i].back() < pos[i]) { pos[i] = vec[i][0]; } else { st = i + 1; break; } } } int cur = -1; long long res = 0; for (int i = 1; i <= x; i++) { int p = lower_bound(pos + st, pos + x + 1, cur) - pos; p = max(p, i + 1); res += (x - p + 2); if (p == i) res--; if (vec[i].size()) { if (cur < vec[i][0]) cur = vec[i].back(); else break; } } printf( %lld n , res); return 0; }
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_switch
*/
module test_axis_switch_4x4_64;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT+1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_4x4_64.lxt");
$dumpvars(0, test_axis_switch_4x4_64);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 501; int dp[maxn][maxn]; int n; int a[maxn]; int dp2[maxn]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], dp[i][i] = a[i]; for (int len = 1; len <= n; len++) { for (int i = 1; i <= n - len + 1; i++) { for (int k = i; k < i + len - 1; k++) { if (dp[i][k] != 0 && dp[i][k] == dp[k + 1][i + len - 1]) { dp[i][i + len - 1] = dp[i][k] + 1; } } } } for (int i = 1; i <= n; i++) { dp2[i] = dp2[i - 1] + 1; for (int j = 1; j < i; j++) { if (dp[j][i] > 0) { dp2[i] = min(dp2[i], dp2[j - 1] + 1); } } } printf( %d n , dp2[n]); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Grid.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Grid (
address,
clock,
q);
input [14:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Grid.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "19200"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Grid.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "19200"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Grid_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; template <class S, class T> ostream& operator<<(ostream& st, pair<S, T> p) { st << ( << p.first << , << p.second << ) ; return st; } template <class T> ostream& operator<<(ostream& st, vector<T> v) { st << [ ; for (size_t i = 0; i < v.size(); ++i) { if (i != 0) { st << , ; } st << v[i]; } st << ] ; return st; } pair<int, int> get_parent_dsu(int v, vector<pair<int, int> >& parents) { if (parents[v].first != v) { pair<int, int> p = get_parent_dsu(parents[v].first, parents); parents[v] = make_pair(p.first, p.second ^ parents[v].second); } return parents[v]; } void union_dsu(int a, int b, int value, vector<int>& mass, vector<pair<int, int> >& parents) { pair<int, int> a_parent = get_parent_dsu(a, parents); pair<int, int> b_parent = get_parent_dsu(b, parents); a = a_parent.first; int a_dist = a_parent.second; b = b_parent.first; int b_dist = b_parent.second; if (a != b) { if (mass[a] > mass[b]) { swap(a, b); swap(a_dist, b_dist); } parents[a].first = b; parents[a].second = value ^ a_dist ^ b_dist; mass[b] += mass[a]; } } int perform_get_query(int a, int b, vector<pair<int, int> >& parents) { pair<int, int> a_parent = get_parent_dsu(a, parents); pair<int, int> b_parent = get_parent_dsu(b, parents); int result; if (a_parent.first == b_parent.first) { result = a_parent.second ^ b_parent.second; } else { result = -1; } return result; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); srand(time(0)); int q; cin >> q; int mapper_size = 0; map<int, int> mapper; vector<int> mass; vector<pair<int, int> > parents_dsu; int last = 0; for (int i = 0; i < q; ++i) { int t; cin >> t; int l, r, value; cin >> l >> r; l = l ^ last; r = r ^ last; if (l > r) { swap(l, r); } --l; if (mapper.count(l) == 0) { mass.push_back(1); parents_dsu.push_back(make_pair(mapper_size, 0)); mapper[l] = mapper_size++; } if (mapper.count(r) == 0) { mass.push_back(1); parents_dsu.push_back(make_pair(mapper_size, 0)); mapper[r] = mapper_size++; } int a = mapper[l]; int b = mapper[r]; if (t == 1) { cin >> value; value = last ^ value; union_dsu(a, b, value, mass, parents_dsu); } else { last = perform_get_query(a, b, parents_dsu); cout << last << endl; if (last == -1) { last = 1; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
// -*- Mode: Verilog -*-
// Filename : wb_dsp_equations_top.v
// Description : Container for all Equations
// Author : Philip Tracton
// Created On : Wed Jan 13 16:34:33 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jan 13 16:34:33 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_dsp_equations_top (/*AUTOARG*/
// Outputs
eq_adr_o, eq_dat_o, eq_sel_o, eq_we_o, eq_cyc_o, eq_stb_o,
eq_cti_o, eq_bte_o, equation_done,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i,
base_address, equation_enable
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output wire [aw-1:0] eq_adr_o;
output wire [dw-1:0] eq_dat_o;
output wire [3:0] eq_sel_o;
output wire eq_we_o;
output wire eq_cyc_o;
output wire eq_stb_o;
output wire [2:0] eq_cti_o;
output wire [1:0] eq_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input [aw-1:0] base_address;
input [7:0] equation_enable;
output equation_done;
/****************************************************************************
EQUATION: SUM
****************************************************************************/
wire [aw-1:0] sum_adr_o;
wire [dw-1:0] sum_dat_o;
wire [3:0] sum_sel_o;
wire sum_we_o;
wire sum_cyc_o;
wire sum_stb_o;
wire [2:0] sum_cti_o;
wire [1:0] sum_bte_o;
equation_sum #(.aw(aw), .dw(dw),.DEBUG(DEBUG))
sum(
// Outputs
.wb_adr_o(sum_adr_o),
.wb_dat_o(sum_dat_o),
.wb_sel_o(sum_sel_o),
.wb_we_o(sum_we_o),
.wb_cyc_o(sum_cyc_o),
.wb_stb_o(sum_stb_o),
.wb_cti_o(),
.wb_bte_o(),
.equation_done(sum_equation_done),
// Inputs
.wb_clk(wb_clk),
.wb_rst(wb_rst),
.wb_dat_i(wb_dat_i),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.base_address(base_address),
.equation_enable(equation_enable)
);
/****************************************************************************
Put all the equation output busses together. This is why they are required
to drive 0's on all signal when not active!
****************************************************************************/
assign eq_adr_o = sum_adr_o;
assign eq_dat_o = sum_dat_o;
assign eq_sel_o = sum_sel_o;
assign eq_we_o = sum_we_o;
assign eq_cyc_o = sum_cyc_o;
assign eq_stb_o = sum_stb_o;
assign eq_cti_o = sum_cti_o;
assign eq_bte_o = sum_bte_o;
assign eq_cti_o = 0;
assign eq_bte_o = 0;
assign equation_done = sum_equation_done;
endmodule // wb_dsp_equations_top
|
// Double buffering with dual-port RAM
// Uses single-port RAM to write switches to a section while reading from the same section to control LEDs,
// so each switch acts as if connected directly to the corresponding LED.
// Flip SW0 to change sections.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [4:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(5)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM64X1S #(
.INIT(64'h96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A5(sw[0]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.O(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_PP_V
|
#include<iostream> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a; cin >> a; cout << 2-a*a; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], sm = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sm += a[i]; } vector<int> ind, r; int need = sm / 2; if (a[0] > need) { cout << 1 << endl; cout << 1; return 0; } for (int i = 1; i < n; i++) { if ((2 * a[i]) <= a[0]) { ind.push_back(i + 1); r.push_back(a[i]); } } bool ok; int u = a[0]; for (auto x : r) { u += x; } if (u > need) { ok = true; } else { ok = false; } if (ok) { cout << ind.size() + 1 << endl; cout << 1 << ; for (auto x : ind) { cout << x << ; } } else { cout << 0; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string s[n]; for (int i = 0; i < n; i++) cin >> s[i]; vector<vector<int>> row(n), col(m); for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < m; j++) { if (s[i][j] == # ) { row[i].push_back(j); col[j].push_back(i); } } } deque<pair<int, int>> q; int rw[n]; int rvis[n]; for (int i = 0; i < n; i++) { rw[i] = INT_MAX; rvis[i] = 0; } int cw[m]; int cvis[m]; for (int i = 0; i < m; i++) { cw[i] = INT_MAX; cvis[i] = 0; } rw[n - 1] = 0; q.push_back(make_pair(0, n - 1)); while (q.size() > 0) { int type = q.front().first; int num = q.front().second; q.pop_front(); if (type == 0) { if (rvis[num] == 1) continue; else rvis[num] = 1; if (num == 0) break; for (int i = 0; i < row[num].size(); i++) { int cn = row[num][i]; if (cvis[cn] == 0 && cw[cn] > rw[num] + 1) { cw[cn] = rw[num] + 1; q.push_back(make_pair(1, cn)); } } } else if (type == 1) { if (cvis[num] == 1) continue; else cvis[num] = 1; for (int i = 0; i < col[num].size(); i++) { int rn = col[num][i]; if (rvis[rn] == 0 && rw[rn] > cw[num] + 1) { rw[rn] = cw[num] + 1; q.push_back(make_pair(0, rn)); } } } } if (rw[0] == INT_MAX) cout << -1; else cout << rw[0]; }
|
// file: timer_tb.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module timer_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
timer_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 200000; int ans[MAX_N + 5]; int main() { int tc; cin >> tc; while (tc--) { int n, i, j; string s; cin >> n >> s; int num = n, last = 0; for (i = 0; i < n; i++) { if (i == n - 1 || s[i] == > ) { for (j = i; j >= last; j--) ans[j] = num--; last = i + 1; } } for (i = 0; i < n; i++) cout << ans[i] << (i == n - 1 ? n : ); num = 1, last = 0; for (i = 0; i < n; i++) { if (i == n - 1 || s[i] == < ) { for (j = i; j >= last; j--) ans[j] = num++; last = i + 1; } } for (i = 0; i < n; i++) cout << ans[i] << (i == n - 1 ? n : ); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1003; int n, k; bitset<N * 3> A, dp, dpt; int main() { scanf( %d%d , &n, &k); for (int a; k; k--) scanf( %d , &a), A[a] = 1; dp[1500] = 1; for (int __ = 1; __ <= 1009; __++) { dpt = 0; for (int i = 0; i < 3000; i++) if (dp[i] == 1) dpt |= A << (i - n); dp = dpt; if (dp[1500] == 1) return !printf( %d n , __); } return !printf( -1 n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string digit[10] = { , one , two , three , four , five , six , seven , eight , nine }; string tenth[10] = { , ten , twenty , thirty , forty , fifty , sixty , seventy , eighty , ninety }; string tenx[10] = { ten , eleven , twelve , thirteen , fourteen , fifteen , sixteen , seventeen , eighteen , nineteen }; cin >> n; switch (n / 10) { case 0: cout << digit[n % 10] << endl; break; case 1: cout << tenx[n % 10] << endl; break; default: if (digit[n % 10] == ) cout << tenth[n / 10] << endl; else cout << tenth[n / 10] << - << digit[n % 10] << endl; break; } if (n == 0) printf( zero ); return (0); }
|
// Memory controller to access TVM VPI simulated RAM.
//
// You only see the wires and registers but no logics here.
// The real computation is implemented via TVM VPI
//
// Usage: create and pass instance to additional arguments of $tvm_session.
// Then it will be automatically hook up the RAM logic.
//
module tvm_vpi_mem_interface
#(
parameter READ_WIDTH = 8,
parameter WRITE_WIDTH = 8,
parameter ADDR_WIDTH = 32,
parameter SIZE_WIDTH = 32
)
(
input clk,
input rst,
// Read Ports
input read_en, // Read buffer enable
output [READ_WIDTH-1:0] read_data_out, // The data port for read
output read_data_valid, // Read is valid.
// Write ports
input write_en, // Write buffer enable
input [WRITE_WIDTH-1:0] write_data_in, // Input data to write.
output write_data_ready, // There are still pending write
// Status port
// Control signal ports to issue tasks
input host_read_req, // Read request
input [ADDR_WIDTH-1:0] host_read_addr, // The address to issue a read task
input [SIZE_WIDTH-1:0] host_read_size, // The size of a read
input host_write_req, // Write request.
input [ADDR_WIDTH-1:0] host_write_addr, // The write address
input [SIZE_WIDTH-1:0] host_write_size // The write size
);
reg [READ_WIDTH-1:0] reg_read_data;
reg reg_read_valid;
reg reg_write_ready;
// The wires up.
assign read_data_out = reg_read_data;
assign read_data_valid = reg_read_valid;
assign write_data_ready = reg_write_ready;
endmodule
|
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