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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int maxn = 1e6 + 10; const int mod = 1e9 + 7; typedef struct p { long long x, y; }; p a[maxn]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld %lld , &a[i].x, &a[i].y); } int isok = 1; if (n % 2) { printf( NO n ); return 0; } for (int i = 0; i < n / 2; i++) { int a1 = i, b1 = i + 1, a2 = (i + n / 2 + n) % n, b2 = (i + n / 2 + n + 1) % n; if (abs(a[a1].x - a[b1].x) != abs(a[a2].x - a[b2].x) || abs(a[a1].y - a[b1].y) != abs(a[a2].y - a[b2].y)) { isok = 0; break; } } if (isok) printf( YES n ); else printf( NO n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxN = (int)1e4 + 10; int n, w, b, x; long long dp[1005][maxN]; int c[maxN]; int cost[maxN]; int main() { cin >> n >> w >> b >> x; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n; i++) cin >> cost[i]; memset(dp, -1, sizeof dp); dp[0][0] = w; for (int i = 1; i <= n; i++) { for (int j = 0; j < maxN; j++) { long long cur_bal = dp[i - 1][j]; if (cur_bal == -1) continue; for (int k = 0; k <= c[i]; k++) { if (1LL * k * cost[i] > cur_bal) continue; dp[i][j + k] = max(min(cur_bal - (1LL * k * cost[i]) + x, 1LL * w + (1LL * b * (j + k))), dp[i][j + k]); } } } for (int i = maxN - 1; i >= 0; i--) { if (dp[n][i] != -1) { cout << i; return 0; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int f[300][300]; f[2][1] = 2; f[2][2] = 1; f[4][1] = 32; f[4][2] = 30; f[4][3] = 80; f[4][4] = 109; f[8][1] = 6824; f[8][2] = 59808; f[8][3] = 147224; f[8][4] = 415870; f[8][5] = 1757896; f[8][6] = 1897056; f[8][7] = 4898872; f[8][8] = 7593125; f[16][1] = 776830421; f[16][2] = 290516100; f[16][3] = 746623577; f[16][4] = 293783147; f[16][5] = 33900006; f[16][6] = 735127505; f[16][7] = 565460332; f[16][8] = 428982705; f[16][9] = 472062098; f[16][10] = 161873957; f[16][11] = 117354594; f[16][12] = 515619293; f[16][13] = 578944191; f[16][14] = 312106242; f[16][15] = 569389279; f[16][16] = 391464593; f[32][1] = 261086313; f[32][2] = 584837659; f[32][3] = 683961846; f[32][4] = 468868529; f[32][5] = 211593382; f[32][6] = 736955478; f[32][7] = 229471758; f[32][8] = 157617135; f[32][9] = 398169441; f[32][10] = 360252438; f[32][11] = 629394768; f[32][12] = 264125799; f[32][13] = 647490480; f[32][14] = 342079395; f[32][15] = 391579767; f[32][16] = 225200475; f[32][17] = 486011304; f[32][18] = 513156108; f[32][19] = 628771752; f[32][20] = 132906648; f[32][21] = 142138221; f[32][22] = 20119449; f[32][23] = 444199674; f[32][24] = 195188679; f[32][25] = 387329805; f[32][26] = 44684703; f[32][27] = 651912135; f[32][28] = 737154512; f[32][29] = 612549793; f[32][30] = 519860281; f[32][31] = 186175544; f[32][32] = 212568440; f[64][1] = 240805271; f[64][2] = 239509872; f[64][3] = 581127897; f[64][4] = 6511239; f[64][5] = 156126222; f[64][6] = 509425833; f[64][7] = 672407328; f[64][8] = 366667722; f[64][9] = 459185405; f[64][10] = 509737025; f[64][11] = 554790222; f[64][12] = 165216555; f[64][13] = 703150560; f[64][14] = 74806569; f[64][15] = 398730015; f[64][16] = 383350905; f[64][17] = 506108358; f[64][18] = 51326142; f[64][19] = 298053147; f[64][20] = 104256117; f[64][21] = 391428765; f[64][22] = 374020479; f[64][23] = 206607807; f[64][24] = 87664059; f[64][25] = 275899176; f[64][26] = 56407680; f[64][27] = 551553401; f[64][28] = 448939463; f[64][29] = 582889860; f[64][30] = 129676638; f[64][31] = 226078251; f[64][32] = 135769095; f[64][33] = 61292868; f[64][34] = 578972226; f[64][35] = 190181628; f[64][36] = 390739055; f[64][37] = 184587732; f[64][38] = 446575689; f[64][39] = 732674124; f[64][40] = 232198470; f[64][41] = 676760679; f[64][42] = 352474101; f[64][43] = 611444862; f[64][44] = 575661807; f[64][45] = 628905585; f[64][46] = 320813094; f[64][47] = 522840969; f[64][48] = 469781928; f[64][49] = 156006018; f[64][50] = 554473341; f[64][51] = 239654268; f[64][52] = 643714911; f[64][53] = 433540170; f[64][54] = 199307003; f[64][55] = 496385218; f[64][56] = 291740751; f[64][57] = 67309914; f[64][58] = 370826673; f[64][59] = 202356819; f[64][60] = 279421821; f[64][61] = 421203111; f[64][62] = 63744786; f[64][63] = 520987612; f[64][64] = 550671827; f[128][1] = 482164403; f[128][2] = 768209115; f[128][3] = 462063756; f[128][4] = 154906374; f[128][5] = 36099042; f[128][6] = 341766705; f[128][7] = 678182556; f[128][8] = 621882744; f[128][9] = 478771358; f[128][10] = 231881111; f[128][11] = 175889805; f[128][12] = 243630450; f[128][13] = 168908523; f[128][14] = 671961765; f[128][15] = 55761813; f[128][16] = 652682670; f[128][17] = 773939082; f[128][18] = 517628076; f[128][19] = 756201264; f[128][20] = 124604900; f[128][21] = 750976272; f[128][22] = 498253248; f[128][23] = 676047609; f[128][24] = 137170026; f[128][25] = 705610017; f[128][26] = 495032139; f[128][27] = 561797418; f[128][28] = 703097347; f[128][29] = 500815609; f[128][30] = 95984586; f[128][31] = 739707108; f[128][32] = 265613565; f[128][33] = 387099846; f[128][34] = 777331779; f[128][35] = 594676173; f[128][36] = 591219559; f[128][37] = 407997044; f[128][38] = 208947235; f[128][39] = 93337440; f[128][40] = 478908360; f[128][41] = 685013007; f[128][42] = 487033953; f[128][43] = 671903001; f[128][44] = 39521181; f[128][45] = 738490312; f[128][46] = 33785059; f[128][47] = 465470131; f[128][48] = 310453920; f[128][49] = 54648783; f[128][50] = 346831137; f[128][51] = 427694175; f[128][52] = 474743430; f[128][53] = 705296781; f[128][54] = 435828036; f[128][55] = 429824745; f[128][56] = 663532359; f[128][57] = 261388683; f[128][58] = 244690731; f[128][59] = 533997135; f[128][60] = 596108961; f[128][61] = 506813013; f[128][62] = 371892402; f[128][63] = 590145264; f[128][64] = 104733162; f[128][65] = 143420103; f[128][66] = 654339672; f[128][67] = 700348950; f[128][68] = 685038942; f[128][69] = 578826927; f[128][70] = 286484229; f[128][71] = 501639192; f[128][72] = 434962491; f[128][73] = 299270097; f[128][74] = 27702486; f[128][75] = 335375775; f[128][76] = 111746817; f[128][77] = 565603164; f[128][78] = 294926121; f[128][79] = 676063665; f[128][80] = 735862995; f[128][81] = 710035809; f[128][82] = 437011960; f[128][83] = 668528077; f[128][84] = 138765186; f[128][85] = 508213986; f[128][86] = 615036450; f[128][87] = 353784942; f[128][88] = 624827616; f[128][89] = 343900011; f[128][90] = 241289776; f[128][91] = 52410890; f[128][92] = 72018835; f[128][93] = 352406796; f[128][94] = 415705878; f[128][95] = 4802637; f[128][96] = 376367145; f[128][97] = 65589678; f[128][98] = 333633477; f[128][99] = 341834527; f[128][100] = 303717460; f[128][101] = 282387700; f[128][102] = 42951006; f[128][103] = 254706039; f[128][104] = 423048528; f[128][105] = 526429710; f[128][106] = 68131467; f[128][107] = 669954708; f[128][108] = 12787348; f[128][109] = 500636381; f[128][110] = 317959019; f[128][111] = 479433192; f[128][112] = 657133515; f[128][113] = 416259390; f[128][114] = 610216692; f[128][115] = 340129188; f[128][116] = 44594256; f[128][117] = 257373347; f[128][118] = 138718678; f[128][119] = 530767740; f[128][120] = 292922628; f[128][121] = 37220268; f[128][122] = 605295159; f[128][123] = 480722613; f[128][124] = 458170419; f[128][125] = 30540300; f[128][126] = 487159055; f[128][127] = 232966794; f[128][128] = 149150650; f[256][1] = 412133651; f[256][2] = 386543325; f[256][3] = 139952108; f[256][4] = 289303402; f[256][5] = 102404925; f[256][6] = 317067177; f[256][7] = 396414708; f[256][8] = 80515854; f[256][9] = 663739304; f[256][10] = 317300809; f[256][11] = 228877044; f[256][12] = 493725043; f[256][13] = 715317967; f[256][14] = 490300965; f[256][15] = 315527373; f[256][16] = 743539734; f[256][17] = 488329191; f[256][18] = 553627998; f[256][19] = 533025234; f[256][20] = 242583957; f[256][21] = 706116537; f[256][22] = 614109258; f[256][23] = 645447222; f[256][24] = 523195911; f[256][25] = 492109128; f[256][26] = 722623041; f[256][27] = 111085128; f[256][28] = 766395126; f[256][29] = 654378921; f[256][30] = 691964847; f[256][31] = 496688157; f[256][32] = 399056049; f[256][33] = 654363234; f[256][34] = 102052314; f[256][35] = 191720088; f[256][36] = 473910948; f[256][37] = 259736526; f[256][38] = 332840025; f[256][39] = 388047555; f[256][40] = 665791056; f[256][41] = 627111387; f[256][42] = 139696515; f[256][43] = 441456687; f[256][44] = 443032569; f[256][45] = 283264821; f[256][46] = 771641703; f[256][47] = 452641455; f[256][48] = 511306362; f[256][49] = 117572859; f[256][50] = 127701891; f[256][51] = 721298331; f[256][52] = 176520078; f[256][53] = 357242229; f[256][54] = 611296308; f[256][55] = 696994956; f[256][56] = 405628839; f[256][57] = 429224274; f[256][58] = 465336054; f[256][59] = 695091546; f[256][60] = 689828796; f[256][61] = 574648641; f[256][62] = 351220905; f[256][63] = 507964023; f[256][64] = 675326610; f[256][65] = 517248963; f[256][66] = 453528621; f[256][67] = 220301928; f[256][68] = 494463186; f[256][69] = 681789969; f[256][70] = 339589656; f[256][71] = 44524053; f[256][72] = 417125457; f[256][73] = 339589404; f[256][74] = 747135963; f[256][75] = 341780733; f[256][76] = 734158215; f[256][77] = 396817281; f[256][78] = 21997836; f[256][79] = 5728464; f[256][80] = 147611205; f[256][81] = 456248898; f[256][82] = 714128667; f[256][83] = 377654949; f[256][84] = 3862068; f[256][85] = 128418948; f[256][86] = 589390074; f[256][87] = 304947090; f[256][88] = 11703825; f[256][89] = 228266073; f[256][90] = 127304142; f[256][91] = 429215724; f[256][92] = 361541124; f[256][93] = 521572968; f[256][94] = 468358191; f[256][95] = 341231688; f[256][96] = 65323503; f[256][97] = 613778508; f[256][98] = 15985323; f[256][99] = 291661029; f[256][100] = 410970006; f[256][101] = 591638112; f[256][102] = 349541550; f[256][103] = 89967528; f[256][104] = 224922159; f[256][105] = 361094166; f[256][106] = 584206074; f[256][107] = 640051812; f[256][108] = 324264456; f[256][109] = 652625388; f[256][110] = 693768537; f[256][111] = 11740617; f[256][112] = 309238398; f[256][113] = 211085469; f[256][114] = 194905872; f[256][115] = 639416484; f[256][116] = 110110707; f[256][117] = 296645895; f[256][118] = 748118511; f[256][119] = 131177718; f[256][120] = 511142751; f[256][121] = 775975599; f[256][122] = 421403409; f[256][123] = 475528473; f[256][124] = 434685258; f[256][125] = 1768977; f[256][126] = 80301375; f[256][127] = 708023862; f[256][128] = 569195676; f[256][129] = 56238084; f[256][130] = 632887668; f[256][131] = 88089750; f[256][132] = 631539342; f[256][133] = 396695565; f[256][134] = 38780154; f[256][135] = 695798271; f[256][136] = 469819224; f[256][137] = 439587099; f[256][138] = 69045921; f[256][139] = 682966116; f[256][140] = 112310856; f[256][141] = 64943298; f[256][142] = 534475872; f[256][143] = 40215357; f[256][144] = 389728458; f[256][145] = 286368453; f[256][146] = 736006257; f[256][147] = 501181650; f[256][148] = 54829908; f[256][149] = 603489402; f[256][150] = 338032656; f[256][151] = 512182818; f[256][152] = 627500097; f[256][153] = 462674016; f[256][154] = 3103092; f[256][155] = 157324491; f[256][156] = 43978329; f[256][157] = 596818971; f[256][158] = 259025598; f[256][159] = 9088632; f[256][160] = 91991781; f[256][161] = 577291428; f[256][162] = 211245489; f[256][163] = 429471231; f[256][164] = 142626330; f[256][165] = 172560633; f[256][166] = 510907446; f[256][167] = 444609585; f[256][168] = 758102058; f[256][169] = 375112647; f[256][170] = 744786693; f[256][171] = 276174402; f[256][172] = 19259856; f[256][173] = 233672418; f[256][174] = 745389414; f[256][175] = 225772848; f[256][176] = 23385663; f[256][177] = 324290610; f[256][178] = 519804558; f[256][179] = 120337812; f[256][180] = 402578568; f[256][181] = 360676008; f[256][182] = 450089262; f[256][183] = 551043738; f[256][184] = 337388940; f[256][185] = 512108856; f[256][186] = 28879011; f[256][187] = 690040638; f[256][188] = 106017282; f[256][189] = 558262341; f[256][190] = 99972432; f[256][191] = 608226003; f[256][192] = 612152037; f[256][193] = 42414435; f[256][194] = 776201013; f[256][195] = 39580443; f[256][196] = 518796945; f[256][197] = 494437752; f[256][198] = 583194366; f[256][199] = 723936555; f[256][200] = 415359657; f[256][201] = 309569589; f[256][202] = 751104774; f[256][203] = 166684527; f[256][204] = 249229170; f[256][205] = 353120823; f[256][206] = 130668327; f[256][207] = 753823584; f[256][208] = 580966092; f[256][209] = 561963717; f[256][210] = 543672234; f[256][211] = 393846327; f[256][212] = 586278000; f[256][213] = 327398400; f[256][214] = 278403867; f[256][215] = 156455586; f[256][216] = 363920382; f[256][217] = 190245195; f[256][218] = 290039148; f[256][219] = 547014447; f[256][220] = 466218648; f[256][221] = 146037150; f[256][222] = 585462906; f[256][223] = 666008595; f[256][224] = 691786683; f[256][225] = 374707494; f[256][226] = 622498779; f[256][227] = 231158277; f[256][228] = 685740951; f[256][229] = 115612245; f[256][230] = 681825249; f[256][231] = 545555745; f[256][232] = 551718468; f[256][233] = 277206615; f[256][234] = 640171035; f[256][235] = 757727334; f[256][236] = 195193908; f[256][237] = 658656684; f[256][238] = 457760646; f[256][239] = 225925875; f[256][240] = 505761984; f[256][241] = 18685233; f[256][242] = 506832921; f[256][243] = 112511021; f[256][244] = 396846646; f[256][245] = 290147622; f[256][246] = 113924623; f[256][247] = 669986155; f[256][248] = 336008070; f[256][249] = 63611061; f[256][250] = 238586775; f[256][251] = 119956662; f[256][252] = 616557739; f[256][253] = 772784623; f[256][254] = 334527774; f[256][255] = 410403148; f[256][256] = 51933421; int n, k; cin >> n >> k; cout << f[n][k] << endl; return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:11:04 06/09/2015
// Design Name:
// Module Name: aesmodule
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aesmodule(
output [127:0] out,
output ready,
input [127:0] in,
input decr,
input clk,
input reset
);
wire [3:0] memadd;
wire [127:0] roundkey;
// Main AES Encrypt Block (Encrypts single 128 bit data)
aesmain mainencblock( .out(out), .ready(ready), .memadd(memadd), .in(in), .roundkey(roundkey), .decr(decr), .clk(clk), .reset(reset));
// Memory
keymem keymemory(.dout(roundkey), .add(memadd), .clock(clk), .en(1'b1)); // Always enabled, but use a counter for address that has a clock divided by 2.
endmodule
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//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
RowsGenerator
:Function
Generate rows cache, **this module just support Pipeline mode now !!!**
The lowest color_width-bits of out_data are the first row!
You can configure all fifos by yourself, but fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
Give the first output after rows_width * (rows_depth + 1) cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-18
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module RowsGenerator(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data
);
/*
::description
The width of rows.
::range
2 - 15
*/
parameter[3 : 0] rows_width = 3;
/*
::description
The width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Color's bit wide.
::range
1 - 12
*/
parameter[3: 0] color_width = 8;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter[4 : 0] im_width_bits = 9;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, it works as fifo0's wr_en.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [color_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
The lowest color_width-bits of this are the first row!
*/
output[rows_width * color_width - 1 : 0] out_data;
reg reg_row_wr_en[0 : rows_width];
wire row_wr_en[0 : rows_width];
wire row_rd_en[0 : rows_width - 1];
wire[color_width - 1 : 0] row_din[0 : rows_width - 1];
wire[color_width - 1 : 0] row_dout[0 : rows_width - 1];
wire[im_width_bits - 1 : 0] row_num[0 : rows_width - 1];
wire rst = ~rst_n;
genvar i, j;
generate
assign out_ready = row_wr_en[rows_width];
for (i = 0; i < rows_width; i = i + 1) begin : fifos
assign row_rd_en[i] = row_num[i] == im_width - 1 ? 1 : 0;
if (i == 0) begin
assign row_wr_en[i] = in_enable;
assign row_din[i] = in_data;
end else begin
assign row_din[i] = row_dout[i - 1];
end
//One clock delay from fifo read enable to data out
always @(posedge clk)
reg_row_wr_en[i + 1] <= row_rd_en[i];
assign row_wr_en[i + 1] = reg_row_wr_en[i + 1];
case (color_width)
1 :
/*
::description
Fifo which has 1 width and N depth (0 < N < 4096), used for rows cache which color_width is 1.
You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
*/
Fifo1xWidthRows Fifo(
.clk(clk),
.rst(rst),
.din(row_din[i]),
.wr_en(row_wr_en[i]),
.rd_en(row_rd_en[i]),
.dout(row_dout[i]),
.data_count(row_num[i])
);
2, 3, 4 :
/*
::description
Fifo which has 4 width and N depth (0 < N < 4096), used for rows cache which color_width is 2, 3 and 4.
You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
*/
Fifo4xWidthRows Fifo(
.clk(clk),
.rst(rst),
.din(row_din[i]),
.wr_en(row_wr_en[i]),
.rd_en(row_rd_en[i]),
.dout(row_dout[i]),
.data_count(row_num[i])
);
5, 6, 7, 8 :
/*
::description
Fifo which has 8 width and N depth (0 < N < 4096), used for rows cache which color_width is 5, 6, 7 and 8.
You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
*/
Fifo8xWidthRows Fifo(
.clk(clk),
.rst(rst),
.din(row_din[i]),
.wr_en(row_wr_en[i]),
.rd_en(row_rd_en[i]),
.dout(row_dout[i]),
.data_count(row_num[i])
);
9, 10, 11, 12 :
/*
::description
Fifo which has 12 width and N depth (0 < N < 4096), used for rows cache which color_width is 9, 10, 11 and 12.
You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.
And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
*/
Fifo12xWidthRows Fifo(
.clk(clk),
.rst(rst),
.din(row_din[i]),
.wr_en(row_wr_en[i]),
.rd_en(row_rd_en[i]),
.dout(row_dout[i]),
.data_count(row_num[i])
);
default : /* default */;
endcase
assign out_data[(i + 1) * color_width - 1 : i * color_width] = out_ready ? row_dout[rows_width - 1 - i] : 0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int N; char c[2000000]; int numWays() { if (N == 1) { if (c[0] == * ) return 1; else if (c[0] == 0 ) return 1; else if (c[0] == ? ) return 2; else return 0; } if (c[0] == 2 ) return 0; if (c[N - 1] == 2 ) return 0; for (int i = 0; i < N; i++) { if (c[i] == 0 ) { if (i > 0) { if (c[i - 1] == ? ) c[i - 1] = - ; else if (c[i - 1] == * ) return 0; } if (i + 1 < N) { if (c[i + 1] == ? ) c[i + 1] = - ; else if (c[i + 1] == * ) return 0; } } } for (int i = 0; i < N; i++) { int max = (i > 0) + ((i + 1) < N); if (c[i] == 0 + max) { if (i > 0) { if (c[i - 1] == ? ) c[i - 1] = * ; else if (c[i - 1] != * ) return 0; } if (i + 1 < N) { if (c[i + 1] == ? ) c[i + 1] = * ; else if (c[i + 1] != * ) return 0; } } } for (int i = 1; i + 1 < N; i++) { if (c[i] == 1 ) { int numq = (c[i - 1] == ? ) + (c[i + 1] == ? ); int numm = (c[i - 1] == * ) + (c[i + 1] == * ); int numf = 2 - numm - numq; if (numq == 0) { if (numf != 1) return 0; } else if (numq == 1) { if (numm == 0) { if (c[i - 1] == ? ) c[i - 1] = * ; else if (c[i + 1] == ? ) c[i + 1] = * ; else assert(false); } else if (numm == 1) { if (c[i - 1] == ? ) c[i - 1] = - ; else if (c[i + 1] == ? ) c[i + 1] = - ; else assert(false); } else assert(false); } } } for (int i = N - 2; i > 0; i--) { if (c[i] == 1 ) { int numq = (c[i - 1] == ? ) + (c[i + 1] == ? ); int numm = (c[i - 1] == * ) + (c[i + 1] == * ); int numf = 2 - numm - numq; if (numq == 0) { if (numf != 1) return 0; } else if (numq == 1) { if (numm == 0) { if (c[i - 1] == ? ) c[i - 1] = * ; else if (c[i + 1] == ? ) c[i + 1] = * ; else assert(false); } else if (numm == 1) { if (c[i - 1] == ? ) c[i - 1] = - ; else if (c[i + 1] == ? ) c[i + 1] = - ; else assert(false); } else assert(false); } } } int res = 1; for (int i = 0; i < N; i++) { if (c[i] == ? && (i == 0 || c[i - 1] != 1 )) { res *= 2; if (res >= MOD) res -= MOD; } } return res; } int main() { cin >> c; N = strlen(c); cout << numWays() << n ; }
|
#include <bits/stdc++.h> using namespace std; int A[105][105]; int main() { int n; int ans = 0; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < n; j++) { if (s[j] == C ) { A[i][j] = 1; } else { A[i][j] = 0; } } } for (int i = 0; i < n; i++) { int cnt = 0; for (int j = 0; j < n; j++) { if (A[i][j] == 1) { cnt++; } } ans += (cnt * (cnt - 1)) / 2; } for (int i = 0; i < n; i++) { int cnt = 0; for (int j = 0; j < n; j++) { if (A[j][i] == 1) { cnt++; } } ans += (cnt * (cnt - 1)) / 2; } cout << ans; }
|
//
// Copyright (c) 2001 Stephen Williams <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This program tests the behavior of a simple non-blocking assignment
* with an internal delay. We can check that the value changes at the
* right time and not the wrong time.
*/
module main ;
reg a;
initial begin
a = 0;
if (a !== 0) begin
$display("FAILED -- a at 0 is %b", a);
$finish;
end
a <= #2 1;
if (a !== 0) begin
$display("FAILED -- (0) a should still be 0 but is %b", a);
$finish;
end
#1 if (a !== 0) begin
$display("FAILED -- (1) a should still be 0 but is %b", a);
$finish;
end
#2 if (a !== 1'b1) begin
$display("FAILED -- a should now be 1, but is %b", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, z; int gcd(int n, int m) { return m == 0 ? n : gcd(m, n % m); } int main() { cin >> n >> m >> z; cout << (z / ((long long)n * m / gcd(n, m))); return 0; }
|
/*
SLICEM at the following:
SLICE_XxY*
Where Y any value
x
Always even (ie 100, 102, 104, etc)
In our ROI
x = 6, 8, 10, 12, 14
SRL16E: LOC + BEL
SRLC32E: LOC + BEL
RAM64X1S: LOCs but doesn't BEL
*/
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
/*
//BEL works
my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
*/
/*
//BEL works
//No unknown bits
my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
*/
/*
RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
*/
/*
seg SEG_CLBLM_L_X10Y127
bit 01_23
bit 31_16
bit 31_17
bit 31_46
bit 31_47
seg SEG_CLBLM_L_X10Y100
bit 01_23
bit 31_16
bit 31_17
bit 31_46
bit 31_47
*/
my_RAM64X1D2 #(.LOC("SLICE_X6Y100"))
dut0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X6Y127"))
dut1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y100"))
dut2(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y127"))
dut3(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
/*
my_RAM64M #(.LOC("SLICE_X6Y100"))
my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_RAM64X1S #(.LOC("SLICE_X6Y101"))
my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
my_RAM64X1S_1 #(.LOC("SLICE_X6Y102"))
my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
my_RAM64X2S #(.LOC("SLICE_X6Y103"))
my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
my_RAM64X1D #(.LOC("SLICE_X6Y104"))
my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
my_RAM128X1D #(.LOC("SLICE_X6Y105"))
my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
*/
endmodule
module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) ramb (
.DPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) rama (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule
module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
wire mc31c;
(* LOC=LOC, BEL=BEL *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lut (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule
module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
SRL16E #(
) SRL16E (
.Q(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule
module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64M #(
) RAM64M (
.DOA(dout[0]),
.DOB(dout[1]),
.DOC(dout[2]),
.DOD(dout[3]),
.ADDRA(din[0]),
.ADDRB(din[1]),
.ADDRC(din[2]),
.ADDRD(din[3]),
.DIA(din[4]),
.DIB(din[5]),
.DIC(din[6]),
.DID(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule
module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64X1S #(
) RAM64X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S_1 #(
) RAM64X1S_1 (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X2S #(
) RAM64X2S (
.O0(dout[0]),
.O1(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D0(din[6]),
.D1(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule
module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM64X1D (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule
module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM128X1D #(
.INIT(128'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM128X1D (
.DPO(dout[0]),
.SPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Mod = 1e9 + 7; int n, inv; long long m; long long A[30]; inline int Qpow(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = (long long)ans * a % Mod; b >>= 1; a = (long long)a * a % Mod; } return ans; } inline int C(long long a) { if (a < (n - 1)) return 0; long long res = 1; for (int i = 0; i < n - 1; i++) res = res * ((a - i) % Mod) % Mod; return res * inv % Mod; } inline void Init() { cin >> n >> m; inv = 1; for (int i = 2; i < n; i++) inv = (long long)inv * i % Mod; inv = Qpow(inv, Mod - 2); for (int i = 1; i <= n; i++) cin >> A[i]; } inline void Work() { int res = 0; for (int i = 0; i < (1 << n); i++) { long long a = n + m - 1; int flag = 1; for (int j = 0; j < n; j++) { if ((i >> j) & 1) { flag *= -1; a -= A[j + 1] + 1; } } res = ((long long)res + (long long)flag * C(a) % Mod) % Mod; } cout << (res + Mod) % Mod << endl; } int main() { Init(); Work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Node { int sz, val; Node *left, *right; Node() : left(NULL), right(NULL), sz(0), val(-1) {} ~Node() { delete left; delete right; } }; int A[200000]; void insert(Node*& curr, int i, int x) { if (curr == NULL) curr = new Node(); if (i == -1) curr->val = x; else { if ((1 << i) & A[x]) insert(curr->left, i - 1, x); else insert(curr->right, i - 1, x); } curr->sz += 1; return; } int find(Node* curr) { if (curr == NULL) return 0; if (curr->val > -1) return 1; if (curr->left == NULL) return find(curr->right); if (curr->left->sz == 1) return 1 + find(curr->right); if (curr->right == NULL) return find(curr->left); if (curr->right->sz == 1) return 1 + find(curr->left); return 1 + max(find(curr->left), find(curr->right)); } int main() { int n; cin >> n; Node* root = NULL; for (int i = 0; i < n; ++i) { cin >> A[i]; insert(root, 31, i); } cout << n - find(root); delete root; return 0; }
|
#include <bits/stdc++.h> int main() { int n, temp, count, i, len, len1, j; char c, a[200], b[40]; strcpy(b, qwertyuiopasdfghjkl;zxcvbnm,./ ); while (~scanf( %c , &c)) { getchar(); gets(a); len = strlen(a); len1 = strlen(b); if (c == R ) temp = -1; else temp = 1; for (i = 0; i < len; i++) { for (j = 0; j < len1; j++) { if (a[i] == b[j]) printf( %c , b[j + temp]); } } puts( ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_1_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_1_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv3sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkdlyinv3sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkdlyinv3sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_1_V
|
//======================================================================
//
// test_core.v
// -----------
// A simple test core used during verification of the coretest test
// module. The test core provies a few read and write registers
// that can be tested. Additionally it also provides an 8-bit data
// port directly connected to one of the internal registers.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module test_core(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Programming interface
parameter ADDR_CORE_ID_0 = 8'h00;
parameter ADDR_CORE_ID_1 = 8'h01;
parameter ADDR_CORE_TYPE_0 = 8'h02;
parameter ADDR_CORE_TYPE_1 = 8'h03;
parameter ADDR_RW_REG = 8'h10;
parameter ADDR_DEBUG_REG = 8'h20;
parameter CORE_ID_0 = 32'h74657374; // "test"
parameter CORE_ID_1 = 32'h636f7265; // "core"
parameter CORE_TYPE_0 = 32'h30303030; // "00000"
parameter CORE_TYPE_1 = 32'h30303162; // "001b"
parameter RW_DEFAULT = 32'h11223344;
parameter DEBUG_DEFAULT = 8'h55;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] rw_reg;
reg [31 : 0] rw_new;
reg rw_we;
reg [7 : 0] debug_reg;
reg [7 : 0] debug_new;
reg debug_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg tmp_error;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign error = tmp_error;
assign read_data = tmp_read_data;
assign debug = debug_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin: reg_update
if (!reset_n)
begin
rw_reg <= RW_DEFAULT;
debug_reg <= DEBUG_DEFAULT;
end
else
begin
if (rw_we)
begin
rw_reg <= rw_new;
end
if (debug_we)
begin
debug_reg <= debug_new;
end
end
end // reg_update
//---------------------------------------------------------------
// read_write_logic
//
// Read and write register logic.
//---------------------------------------------------------------
always @*
begin: read_write_logic
// Defafult assignments
rw_new = 32'h00000000;
rw_we = 0;
debug_new = 8'h00;
debug_we = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
// Write operations.
case (address)
ADDR_RW_REG:
begin
rw_new = write_data;
rw_we = 1;
end
ADDR_DEBUG_REG:
begin
debug_new = write_data[7 : 0];
debug_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
else
begin
// Read operations.
case (address)
ADDR_CORE_ID_0:
begin
tmp_read_data = CORE_ID_0;
end
ADDR_CORE_ID_1:
begin
tmp_read_data = CORE_ID_1;
end
ADDR_CORE_TYPE_0:
begin
tmp_read_data = CORE_TYPE_0;
end
ADDR_CORE_TYPE_1:
begin
tmp_read_data = CORE_TYPE_1;
end
ADDR_RW_REG:
begin
tmp_read_data = rw_reg;
end
ADDR_DEBUG_REG:
begin
tmp_read_data = {24'h000000, debug_reg};
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // read_write_logic
endmodule // test_core
//======================================================================
// EOF test_core.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int x; cin >> x; int divisor = 1; int digits; int ans = 0; for (; divisor <= 9; divisor++) { if (x / divisor == 1 && x % divisor == 0) { digits = 1; break; } else if (x / divisor == 11 && x % divisor == 0) { digits = 2; break; } else if (x / divisor == 111 && x % divisor == 0) { digits = 3; break; } else if (x / divisor == 1111 && x % divisor == 0) { digits = 4; break; } } ans = ans + 10 * (divisor - 1); ans = ans + ((digits) * (digits + 1)) / 2; cout << ans << endl; } }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build Wed Nov 18 09:43:45 MST 2015
// Date : Fri Mar 04 11:10:30 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.v
// Design : clk_wiz_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v5_2_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_1
(clk_in1,
clk_out1);
input clk_in1;
output clk_out1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
clk_wiz_1_clk_wiz_1_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule
(* ORIG_REF_NAME = "clk_wiz_1_clk_wiz" *)
module clk_wiz_1_clk_wiz_1_clk_wiz
(clk_in1,
clk_out1);
input clk_in1;
output clk_out1;
wire clk_in1;
wire clk_in1_clk_wiz_1;
wire clk_out1;
wire clk_out1_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfbout_clk_wiz_1;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_1),
.O(clkfbout_buf_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_1),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(32.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(128.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_1),
.CLKFBOUT(clkfbout_clk_wiz_1),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_1),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer
( // Read/USB side
input usbclk,
input bus_reset,
output [15:0] usbdata,
input RD,
output reg have_pkt_rdy,
output reg rx_overrun,
input clear_status,
// Write/DSP side
input rxclk,
input reset, // DSP side reset (used here), do not reset registers
input rxstrobe,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
// Settings, on rxclk also
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input reset_regs, //Only reset registers
output [31:0] debugbus
);
wire [15:0] fifodata, fifodata_8;
reg [15:0] fifodata_16;
wire [11:0] rxfifolevel;
wire rx_full;
wire bypass_hb, want_q;
wire [4:0] bitwidth;
wire [3:0] bitshift;
setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({bypass_hb,want_q,bitwidth,bitshift}));
// USB Read Side of FIFO
always @(negedge usbclk)
have_pkt_rdy <= (rxfifolevel >= 256);
// 257 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= 0;
else if(RD)
read_count <= read_count + 1;
else
read_count <= 0;
// FIFO
wire ch0_in, ch0_out, iq_out;
assign ch0_in = (phase == 1);
fifo_4k_18 rxfifo
( // DSP Write Side
.data ( {ch0_in, phase[0], fifodata} ),
.wrreq (~rx_full & (phase != 0)),
.wrclk ( rxclk ),
.wrfull ( rx_full ),
.wrempty ( ),
.wrusedw ( ),
// USB Read Side
.q ( {ch0_out,iq_out,usbdata} ),
.rdreq ( RD & ~read_count[8] ),
.rdclk ( ~usbclk ),
.rdfull ( ),
.rdempty ( ),
.rdusedw ( rxfifolevel ),
// Async, shared
.aclr ( reset ) );
// DSP Write Side of FIFO
reg [15:0] ch_0_reg;
reg [15:0] ch_1_reg;
reg [15:0] ch_2_reg;
reg [15:0] ch_3_reg;
reg [15:0] ch_4_reg;
reg [15:0] ch_5_reg;
reg [15:0] ch_6_reg;
reg [15:0] ch_7_reg;
always @(posedge rxclk)
if (rxstrobe)
begin
ch_0_reg <= ch_0;
ch_1_reg <= ch_1;
ch_2_reg <= ch_2;
ch_3_reg <= ch_3;
ch_4_reg <= ch_4;
ch_5_reg <= ch_5;
ch_6_reg <= ch_6;
ch_7_reg <= ch_7;
end
reg [3:0] phase;
always @(posedge rxclk)
if(reset)
phase <= 4'd0;
else if(phase == 0)
begin
if(rxstrobe)
phase <= 4'd1;
end
else if(~rx_full)
if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels))
phase <= 4'd0;
else
phase <= phase + 4'd1;
assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
assign fifodata_8 = {round_8(top),round_8(bottom)};
reg [15:0] top,bottom;
function [7:0] round_8;
input [15:0] in_val;
round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
endfunction // round_8
always @*
case(phase)
4'd1 : begin
bottom = ch_0_reg;
top = ch_1_reg;
end
4'd2 : begin
bottom = ch_2_reg;
top = ch_3_reg;
end
4'd3 : begin
bottom = ch_4_reg;
top = ch_5_reg;
end
4'd4 : begin
bottom = ch_6_reg;
top = ch_7_reg;
end
default : begin
top = 16'hFFFF;
bottom = 16'hFFFF;
end
endcase // case(phase)
always @*
case(phase)
4'd1 : fifodata_16 = ch_0_reg;
4'd2 : fifodata_16 = ch_1_reg;
4'd3 : fifodata_16 = ch_2_reg;
4'd4 : fifodata_16 = ch_3_reg;
4'd5 : fifodata_16 = ch_4_reg;
4'd6 : fifodata_16 = ch_5_reg;
4'd7 : fifodata_16 = ch_6_reg;
4'd8 : fifodata_16 = ch_7_reg;
default : fifodata_16 = 16'hFFFF;
endcase // case(phase)
// Detect overrun
reg clear_status_dsp, rx_overrun_dsp;
always @(posedge rxclk)
clear_status_dsp <= clear_status;
always @(negedge usbclk)
rx_overrun <= rx_overrun_dsp;
always @(posedge rxclk)
if(reset)
rx_overrun_dsp <= 1'b0;
else if(rxstrobe & (phase != 0))
rx_overrun_dsp <= 1'b1;
else if(clear_status_dsp)
rx_overrun_dsp <= 1'b0;
// Debug bus
//
// 15:0 rxclk domain => TXA 15:0
// 31:16 usbclk domain => RXA 15:0
assign debugbus[0] = reset;
assign debugbus[1] = reset_regs;
assign debugbus[2] = rxstrobe;
assign debugbus[6:3] = channels;
assign debugbus[7] = rx_full;
assign debugbus[11:8] = phase;
assign debugbus[12] = ch0_in;
assign debugbus[13] = clear_status_dsp;
assign debugbus[14] = rx_overrun_dsp;
assign debugbus[15] = rxclk;
assign debugbus[16] = bus_reset;
assign debugbus[17] = RD;
assign debugbus[18] = have_pkt_rdy;
assign debugbus[19] = rx_overrun;
assign debugbus[20] = read_count[0];
assign debugbus[21] = read_count[8];
assign debugbus[22] = ch0_out;
assign debugbus[23] = iq_out;
assign debugbus[24] = clear_status;
assign debugbus[30:25] = 0;
assign debugbus[31] = usbclk;
endmodule // rx_buffer
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, m, st[N], fn[N], timer, ans[N]; vector<int> adj[N], vec[N]; struct node { long long sum, lazy, sz, one; node() { sum = one = sz = lazy = 0; } } seg[N << 2]; void dfs1(int v, int p = -1) { st[v] = timer++; for (auto u : adj[v]) { if (u == p) continue; dfs1(u, v); } fn[v] = timer; } void build(int id = 1, int b = 0, int e = n) { if (e - b == 1) { seg[id].sz = 1; return; } int mid = (b + e) >> 1, lc = id * 2, rc = lc | 1; build(lc, b, mid); build(rc, mid, e); seg[id].sz = seg[lc].sz + seg[rc].sz; return; } void add(int l, int r, int val, int id = 1, int b = 0, int e = n) { if (l >= e || b >= r) return; if (l <= b && e <= r) { seg[id].one += val; return; } int mid = (b + e) >> 1, lc = id * 2, rc = lc | 1; add(l, r, val, lc, b, mid); add(l, r, val, rc, mid, e); seg[id].sum = ((seg[lc].one) ? seg[lc].sz : seg[lc].sum) + ((seg[rc].one) ? seg[rc].sz : seg[rc].sum); return; } void dfs2(int v, int p = -1) { if (vec[v].size()) vec[v].push_back(v); for (auto u : vec[v]) { int l = st[u], r = fn[u]; add(l, r, 1); } ans[v] = ((seg[1].one) ? n : seg[1].sum); if (ans[v]) ans[v]--; for (auto u : adj[v]) { if (u == p) continue; dfs2(u, v); } for (auto u : vec[v]) { int l = st[u], r = fn[u]; add(l, r, -1); } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < n - 1; i++) { int v, u; cin >> v >> u; v--, u--; adj[v].push_back(u); adj[u].push_back(v); } dfs1(0); build(); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; int l = st[b], r = fn[b]; vec[a].push_back(b); l = st[a], r = fn[a]; vec[b].push_back(a); } dfs2(0); for (int i = 0; i < n; i++) cout << ans[i] << ; cout << n ; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_edb_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_edb_e.v,v 1.1 2006/04/10 15:42:08 wig Exp $
// $Date: 2006/04/10 15:42:08 $
// $Log: inst_edb_e.v,v $
// Revision 1.1 2006/04/10 15:42:08 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_edb_e
//
// No user `defines in this module
module inst_edb_e
//
// Generated module inst_edb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_edb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> int main() { int n, h, arr[1000], c = 0, i; scanf( %d %d , &n, &h); for (i = 0; i < n; i++) { scanf( %d , &arr[i]); if (arr[i] > h) c = c + 2; else c = c + 1; } printf( %d , c); return 0; }
|
// pg_sequencer.v
`timescale 1ns / 1ps
module pg_sequencer
(
input clk,
input sync,
input reset,
input enable,
input start,
output reg running,
output reg [4:0]pgout,
output reg [7:0]ip, // command index pointer
input [15:0]cmd
);
/* command word structure
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | pgout | delay |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*/
wire [4:0]cmd_sig = cmd[12:8];
wire [7:0]cmd_del = cmd[7:0];
wire stop = cmd_del == 0; // stop command
reg [7:0]delay; // delay counter
wire next = delay == 0;
// start/stop
always @(posedge clk or posedge reset)
begin
if (reset) running <= 0;
else if (enable)
begin
if (sync)
begin
if (start) running <= 1;
else if (stop && next) running <= 0;
end
end
else running <= 0;
end
// set index pointer
always @(posedge clk or posedge reset)
begin
if (reset) ip <= 0;
else if (sync)
begin
if (!running) ip <= 0;
else if (next) ip <= ip + 1;
end
end
// command execution
always @(posedge clk or posedge reset)
begin
if (reset)
begin
delay <= 0;
pgout <= 0;
end
else if (sync)
begin
if (!running)
begin
delay <= 0;
pgout <= 0;
end
else if (next)
begin
delay <= cmd_del;
pgout <= cmd_sig;
end
else
begin
delay <= delay - 1;
pgout <= 4'b0000;
end
end
end
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_7_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_7_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_7_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 19; double pw2[8 * N]; struct mynum { double v; int sh; mynum(double _v, int _sh) { v = _v; sh = _sh; } mynum() {} mynum shift(int x) { return mynum(v, sh + x); } friend mynum operator+(mynum a, mynum b) { if (a.sh < b.sh) swap(a, b); if (b.v == 0) return a; if (a.v == 0) return b; b.v *= pw2[b.sh - a.sh + 4 * N]; return mynum(a.v + b.v, a.sh); } }; struct tree { int sh[2 * N]; mynum T[2 * N]; void push(int v) { if (v >= N) { T[v].sh += sh[v]; sh[v] = 0; } else { sh[2 * v] += sh[v]; sh[2 * v + 1] += sh[v]; T[v].sh += sh[v]; sh[v] = 0; } } mynum get(int l, int r, int L = 1, int R = N, int v = 1) { if (r < L || l > R) return mynum(0, 0); else if (l <= L && R <= r) return T[v].shift(sh[v]); else { push(v); return get(l, r, L, (L + R) / 2, 2 * v) + get(l, r, (L + R) / 2 + 1, R, 2 * v + 1); } } inline int getsh(int x) { int L = 1, R = N, v = 1; while (v < N) { push(v); if ((L + R) / 2 >= x) v = 2 * v, R = (L + R) / 2; else v = 2 * v + 1, L = (L + R) / 2 + 1; } return sh[v] + T[v].sh; } void ch(int l, int r, int x, int L = 1, int R = N, int v = 1) { if (r < L || l > R) return; else if (l <= L && R <= r) sh[v] += x; else { push(v); ch(l, r, x, L, (L + R) / 2, 2 * v); ch(l, r, x, (L + R) / 2 + 1, R, 2 * v + 1); T[v] = T[2 * v].shift(sh[2 * v]) + T[2 * v + 1].shift(sh[2 * v + 1]); } } tree() {} void init() { for (int i = N; i < 2 * N; i++) sh[i] = 0, T[i] = mynum(1, 0); for (int i = N - 1; i > 0; i--) sh[i] = 0, T[i] = T[2 * i] + T[2 * i + 1]; } }; tree TL, TR; int main() { pw2[4 * N] = 1; for (int i = 1; i < 4 * N - 10; i++) pw2[4 * N + i] = pw2[4 * N + i - 1] * 2.0, pw2[4 * N - i] = pw2[4 * N - i + 1] / 2.0; int n; scanf( %d , &n); vector<pair<int, int> > V; TL.init(); TR.init(); for (int i = 1; i <= n; i++) { int t; scanf( %d , &t); V.push_back(make_pair(-t, i)); } sort(V.begin(), V.end()); double ans = 0; for (int i = 0; i < V.size(); i++) { int v = -V[i].first; int p = V[i].second; mynum a = TL.get(1, p); int sa = TL.getsh(p); mynum b = TR.get(p, n); int sb = TR.getsh(p); a = a.shift(-sa); b = b.shift(-sb); assert(a.v == a.v); assert(b.v == b.v); assert(v == v); int tp = a.sh + b.sh; double res = v * a.v * b.v * pw2[4 * N + tp]; assert(pw2[4 * N + tp] == pw2[4 * N + tp]); assert(res == res); ans += res; TL.ch(1, p, -1); TR.ch(p, n, -1); } ans /= 2 * (double)n * (double)n; printf( %.10lf n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int n, m, i, j, k, l, a, b, sz[2], v1[2][5005]; string s; bool used[5005]; int main() { ios_base ::sync_with_stdio(); cin.tie(0); cin >> s; n = s.size(); if (n == 1) { cout << s; return 0; } int pw = 1; while (pw * 2 <= n) pw *= 2, k++; a = 0; b = 1; v1[a][0] = 0; sz[a] = 1; for (l = 0; l < n - (1 << k) + 1; l++) { char res = z ; int v, mask; for (i = 0; i < sz[a]; i++) { int v = v1[a][i], mask = ((1 << k) - 1) ^ (v - l); used[v] = 0; for (j = mask; j > 0; j = mask & (j - 1)) res = min(res, s[v + j]); res = min(res, s[v]); } for (i = 0; i < sz[a]; i++) { int v = v1[a][i], mask = ((1 << k) - 1) ^ (v - l); for (j = mask; j >= 0; j = mask & (j - 1)) { if (!used[v + j + 1] && s[v + j] == res) v1[b][sz[b]++] = v + j + 1, used[v + j + 1] = true; if (j == 0) break; } } cout << res; sz[a] = 0; b = a; a ^= 1; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:46:53 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="rgb_565[15:0],rgb_888[23:0]" */;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; long long child[N], w[N], dp[N][65][3], ans[N][2]; void pre(int n) { for (int i = 0; i < n; i++) { dp[i][0][0] = w[i]; dp[i][0][2] = w[i]; dp[i][0][1] = child[i]; } for (int j = 1; j < 65; j++) { for (int i = 0; i < n; i++) { dp[i][j][1] = dp[dp[i][j - 1][1]][j - 1][1]; dp[i][j][0] = dp[i][j - 1][0] + dp[dp[i][j - 1][1]][j - 1][0]; dp[i][j][2] = min(dp[i][j - 1][2], dp[dp[i][j - 1][1]][j - 1][2]); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; long long k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> child[i]; for (int i = 0; i < n; i++) cin >> w[i]; pre(n); int pt; for (int i = 0; i < n; i++) { pt = i; ans[i][1] = 1000000007ULL; for (long long j = 0; (1LL << j) <= k; j++) { if ((1LL << j) & k) { ans[i][0] += dp[pt][j][0]; ans[i][1] = min(ans[i][1], dp[pt][j][2]); pt = dp[pt][j][1]; } } } for (int i = 0; i < n; i++) cout << ans[i][0] << << ans[i][1] << n ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dpMem_dc.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Synchronous dual port memory with dual clocks
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input wrClk;
input rdClk;
input [FIFO_WIDTH-1:0] dataIn;
output [FIFO_WIDTH-1:0] dataOut;
input writeEn;
input readEn;
input [ADDR_WIDTH-1:0] addrIn;
input [ADDR_WIDTH-1:0] addrOut;
wire wrClk;
wire rdClk;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire writeEn;
wire readEn;
wire [ADDR_WIDTH-1:0] addrIn;
wire [ADDR_WIDTH-1:0] addrOut;
reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
// synchronous read. Introduces one clock cycle delay
always @(posedge rdClk) begin
dataOut <= buffer[addrOut];
end
// synchronous write
always @(posedge wrClk) begin
if (writeEn == 1'b1)
buffer[addrIn] <= dataIn;
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Multiplexer for Carry Logic with General Output
// /___/ /\ Filename : MUXCY.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXCY (O, CI, DI, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input CI, DI, S;
reg O_out;
always @(CI or DI or S)
if (S)
O_out = CI;
else
O_out = DI;
assign O = O_out;
`ifdef XIL_TIMING
specify
(CI => O) = (0:0:0, 0:0:0);
(DI => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
module test();
localparam [7:0] dly1 = 4;
wire [7:0] dly2 = 3;
reg [7:0] dly3 = 2;
reg i;
wire [6:1] o;
nmos #(dly1, dly2, dly3) buf1(o[1], i, 1'b1);
nmos #(dly2, dly3, dly1) buf2(o[2], i, 1'b1);
nmos #(dly3, dly1, dly2) buf3(o[3], i, 1'b1);
nmos #(dly2-1, dly2-2, dly2-3) buf4(o[4], i, 1'b1);
nmos #(dly3+1, dly3+2, dly3+3) buf5(o[5], i, 1'b1);
nmos #(4, 3, 2) buf6(o[6], i, 1'b1);
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1'b1;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'b1, 1'b1, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bx, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
i = 1'b0;
#0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
i = 1'bx;
#0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'bx)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
i = 1'bz;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bz, 1'bx, 1'bz)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bz)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int p = 1; int diagjump = n + 1; for (int i = 1; i <= n; i++) { p = i; for (int j = 1; j <= n; j++) { cout << p << ; if (p == n * j) p++; else p += diagjump; } cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_2_V
`define SKY130_FD_SC_LS__DECAPHE_2_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_2_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,fma ) #pragma GCC optimize( unroll-loops ) using namespace std; long long MOD = 998244353; double eps = 1e-12; void solve() { long long n, k; cin >> n >> k; if (n == 1 && k == 10) { cout << -1 << n ; return; } if (k == 10) { cout << 1; for (int i = 1; i <= n - 1; i++) { cout << 0; } } else { for (int i = 1; i <= n; i++) { cout << k; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jun 27 05:23:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.5 2006/07/04 09:54:10 wig Exp $
// $Date: 2006/07/04 09:54:10 $
// $Log: ent_ba.v,v $
// Revision 1.5 2006/07/04 09:54:10 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:30 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: rx_stream.ejava,v $
// Rev: $Revision: 1.1.4.1 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RX_STREAM
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: The RX_LL module receives data from the Aurora Channel,
// converts it to a simple streaming format. This module expects
// all data to be carried in a single, infinite frame, and it
// expects the data data in lanes to be all valid or all invalid
//
// This module supports 2 4-byte lane designs.
//
//
`timescale 1 ns / 10 ps
module RX_STREAM
(
// LocalLink PDU Interface
RX_D,
RX_SRC_RDY_N,
// Global Logic Interface
START_RX,
// Aurora Lane Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
output [0:31] RX_D;
output RX_SRC_RDY_N;
// Global Logic Interface
input START_RX;
// Aurora Lane Interface
input [0:1] RX_PAD;
input [0:31] RX_PE_DATA;
input [0:1] RX_PE_DATA_V;
input [0:1] RX_SCP;
input [0:1] RX_ECP;
// System Interface
input USER_CLK;
//************************Register Declarations********************
reg infinite_frame_started_r;
//***********************Main Body of Code*************************
//Don't start presenting data until the infinite frame starts
always @(posedge USER_CLK)
if(!START_RX)
infinite_frame_started_r <= `DLY 1'b0;
else if(RX_SCP > 2'd0)
infinite_frame_started_r <= `DLY 1'b1;
assign RX_D = RX_PE_DATA;
assign RX_SRC_RDY_N = !(RX_PE_DATA_V[0] && infinite_frame_started_r);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Jul 4 08:52:39 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_b.v,v $
// Revision 1.2 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
`ifdef exclude_inst_ba
`else
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
`endif
`ifdef exclude_inst_bb
`else
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
`endif
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, sum = 0, i, j, ara[100000], mid, low, high; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &j); sum += j; ara[i] = sum; } scanf( %d , &m); for (i = 0; i < m; i++) { scanf( %d , &k); low = 0; high = n - 1; for (j = 0;; j++) { mid = (high + low) / 2; if (ara[mid] == k) { printf( %d n , mid + 1); break; } else if (ara[mid] > k) high = mid; else if (ara[mid] < k) low = mid + 1; if (high == low) { printf( %d n , low + 1); break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, i, n; int edges[int(2e5 + 1)][2], weights[int(2e5 + 1)], freq[int(2e5 + 1)]; cin >> n; for (i = 1; i <= n; i++) freq[i] = 0; for (i = 0; i < n; i++) { weights[i] = -1; cin >> edges[i][0] >> edges[i][1]; freq[edges[i][0]]++; freq[edges[i][1]]++; } int maxindex = 1, k = 0; for (i = 1; i <= n; i++) if (freq[i] > freq[maxindex]) maxindex = i; for (i = 0; i < n; i++) if (edges[i][0] == maxindex or edges[i][1] == maxindex) weights[i] = k++; for (i = 0; i < n; i++) if (weights[i] == -1) weights[i] = k++; for (i = 0; i < n - 1; i++) cout << weights[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e3 + 40; int f[maxn][maxn]; int dp[maxn]; char s[maxn]; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); scanf( %s , s + 1); f[n][n + 1] = f[n + 1][n] = f[n + 1][n + 1] = 0; for (int i = n; i >= 1; i--) for (int j = n; j >= 1; j--) { if (s[i] == s[j]) { f[i][j] = f[i + 1][j + 1] + 1; } else { f[i][j] = 0; } } int ans = 0; for (int i = 1; i <= n; i++) { dp[i] = n - i + 1; for (int j = 1; j < i; j++) { int len = f[i][j]; if (i + len - 1 >= n || s[i + len] <= s[j + len]) continue; dp[i] = max(dp[i], dp[j] + n - i + 1 - len); } ans = max(ans, dp[i]); } printf( %d n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_PP_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_PP_V
|
// `define DEBUG
module spdif_dai #(
parameter MAX_CLK_PER_HALFBIT_LOG2 = 5 // 32 max
)(
input wire clk,
input wire rst,
input wire [(MAX_CLK_PER_HALFBIT_LOG2-1):0] clk_per_halfbit,
input wire signal_i,
output wire [23:0] data_o,
output wire ack_o,
output wire locked_o,
output wire lrck_o,
output wire [191:0] udata_o,
output wire [191:0] cdata_o);
// read async signal through chained ffs to avoid meta stable
wire buffed_signal;
parameter BUF_LEN = 2;
reg [(BUF_LEN-1):0] buf_ff;
always @(posedge clk)
buf_ff <= {buf_ff[(BUF_LEN-2):0], signal_i};
assign buffed_signal = buf_ff[BUF_LEN-1];
parameter HIST_LEN = 2;
reg [(HIST_LEN-1):0] lvl_history_ff;
always @(posedge clk)
lvl_history_ff <= {lvl_history_ff[(HIST_LEN-2):0], buffed_signal};
reg lvl_probe_ff;
always @(posedge clk)
if(lvl_history_ff[(HIST_LEN-1):(HIST_LEN-2)] == 2'b00)
lvl_probe_ff <= 0;
else if (lvl_history_ff[(HIST_LEN-1):(HIST_LEN-2)] == 2'b11)
lvl_probe_ff <= 1;
wire lvl_probe = lvl_probe_ff;
reg last_lvl;
always @(posedge clk)
last_lvl <= lvl_probe;
reg [7:0] subbit_hist_ff;
reg subbit_ready_ff;
reg signed [MAX_CLK_PER_HALFBIT_LOG2:0] pulse_duration;
always @(posedge clk) begin
subbit_ready_ff <= 0;
if(rst || last_lvl != lvl_probe) begin
pulse_duration <= 0;
end else if(pulse_duration == clk_per_halfbit/2 - 1) begin
pulse_duration <= -clk_per_halfbit + clk_per_halfbit/2;
subbit_hist_ff <= {subbit_hist_ff[6:0], last_lvl};
subbit_ready_ff <= 1;
end else
pulse_duration <= pulse_duration + 1;
end
wire subbit_ready = subbit_ready_ff;
wire [7:0] synccode = subbit_hist_ff;
wire subbit_counter_rst;
reg [5:0] subbit_counter;
parameter SUBBIT_COUNTER_UNLOCKED = 6'h3f;
always @(posedge clk) begin
if(subbit_counter_rst)
subbit_counter <= 0;
else if(subbit_ready && subbit_counter != SUBBIT_COUNTER_UNLOCKED)
subbit_counter <= subbit_counter + 1;
end
wire fullbit_signal = (subbit_counter[0] == 1'b0);
reg fullbit_signal_prev;
always @(posedge clk) begin
fullbit_signal_prev <= fullbit_signal;
end
wire fullbit_ready = fullbit_signal && !fullbit_signal_prev;
reg bmcdecode_bit_reg;
always @(subbit_hist_ff[1:0]) begin
case(subbit_hist_ff[1:0])
2'b10, 2'b01:
bmcdecode_bit_reg = 1;
2'b11, 2'b00:
bmcdecode_bit_reg = 0;
endcase
end
reg [23:0] bit_hist_ff;
always @(posedge clk) begin
if(fullbit_ready) begin
bit_hist_ff <= {bmcdecode_bit_reg, bit_hist_ff[23:1]};
end
end
// sync using synccode
parameter SYNCCODE_B1 = 8'b00010111;
parameter SYNCCODE_W1 = 8'b00011011;
parameter SYNCCODE_M1 = 8'b00011101;
parameter SYNCCODE_B2 = ~SYNCCODE_B1;
parameter SYNCCODE_W2 = ~SYNCCODE_W1;
parameter SYNCCODE_M2 = ~SYNCCODE_M1;
reg startframe_ff;
reg subbit_counter_rst_ff;
reg lrck_ff;
always @(posedge clk) begin
startframe_ff <= 0;
subbit_counter_rst_ff <= 0;
if(rst) begin
subbit_counter_rst_ff <= 1;
end else if(subbit_ready) begin
case(synccode)
SYNCCODE_B1, SYNCCODE_B2: begin
startframe_ff <= 1;
lrck_ff <= 0;
subbit_counter_rst_ff <= 1;
end
SYNCCODE_W1, SYNCCODE_W2: begin
lrck_ff <= 1;
subbit_counter_rst_ff <= 1;
end
SYNCCODE_M1, SYNCCODE_M2: begin
lrck_ff <= 0;
subbit_counter_rst_ff <= 1;
end
// default: begin end
endcase
end
end
assign subbit_counter_rst = subbit_counter_rst_ff;
// output wire locked status / lrck
reg [5:0] unlock_tolerance_counter;
parameter UNLOCK_TOLERANCE = 48;
always @(posedge clk) begin
if(subbit_counter != SUBBIT_COUNTER_UNLOCKED)
unlock_tolerance_counter <= 0;
else if (unlock_tolerance_counter != UNLOCK_TOLERANCE)
unlock_tolerance_counter <= unlock_tolerance_counter + 1;
end
assign locked_o = (unlock_tolerance_counter != UNLOCK_TOLERANCE);
assign lrck_o = lrck_ff;
// output wire data
wire audiodata_ready = (subbit_counter == 24*2) && subbit_ready; // subbit_ready is for 1clk pulse width and pipeline wait
reg [23:0] data_ff;
reg ack_ff;
always @(posedge clk) begin
if(audiodata_ready) begin
`ifdef DEBUG
$display("spdif_dai: lr %d recv %h", lrck_o, bit_hist_ff[23:0]);
`endif
data_ff <= bit_hist_ff[23:0];
ack_ff <= locked_o; // only ack if locked
end else
ack_ff <= 0;
end
assign data_o = data_ff;
assign ack_o = ack_ff;
// output wire {u,c}data
wire extradata_ready = (subbit_counter == (24+4)*2) && subbit_ready; // subbit_ready is for 1clk pulse width and pipeline wait
reg [191:0] udata_shiftreg;
reg [191:0] cdata_shiftreg;
always @(posedge clk) begin
if(rst) begin
udata_shiftreg <= 0;
cdata_shiftreg <= 0;
end else if(extradata_ready) begin
udata_shiftreg <= {udata_shiftreg[190:0], bit_hist_ff[22]};
cdata_shiftreg <= {cdata_shiftreg[190:0], bit_hist_ff[21]};
end
end
reg [191:0] udata_ff;
reg [191:0] cdata_ff;
always @(posedge clk) begin
if(startframe_ff) begin
udata_ff <= udata_shiftreg;
cdata_ff <= cdata_shiftreg;
end
end
assign udata_o = udata_ff;
assign cdata_o = cdata_ff;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[120000]; int main() { cin >> n >> k; for (int i = 0; i < n * 2; i++) a[i] = i; for (int i = 0; i < k; i++) { int now = i * 2; swap(a[now], a[now + 1]); } k = n - k; for (int i = 0; i < n * 2; i++) { printf( %d , a[i] + 1); } puts( ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; struct line { int x, l; } c[105]; bool cmp(line a, line b) { return a.x < b.x; } int f[105][105][2]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &c[i].x, &c[i].l); sort(c + 1, c + n + 1, cmp); c[0].x = -1e9; int ans = 0; for (int i = 0; i <= n; i++) for (int j = 0; j <= i; j++) for (int p1 = 0; p1 <= 1; p1++) { ans = max(ans, f[i][j][p1]); int t = c[j].x + p1 * c[j].l, mx = -1e9, id = 0, y = 0; for (int k = i + 1; k <= n; k++) for (int p2 = 0; p2 <= 1; p2++) { int o = c[k].x + p2 * c[k].l; if (o > mx) mx = o, id = k, y = p2; f[k][id][y] = max(f[k][id][y], f[i][j][p1] + min(o - t, c[k].l) + mx - o); } } printf( %d , ans); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_SYMBOL_V
`define SKY130_FD_SC_HD__DFBBP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; int main(void) { int n, m, a, b; cin >> n >> m >> a >> b; int ans = 1000000000; for (int i = 0; i <= n / m + 1; i++) { ans = min(ans, i * b + max(n - m * i, 0) * a); } cout << ans << n ; return 0; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gl_vrt_all.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gl_vrt1(c12 ,sctag_in ,sctag_out ,c7 );
output [1:0] sctag_out ;
output [7:0] c7 ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt2(c7 ,sctag_out ,sctag_in ,c12 );
output [7:0] c7 ;
output [1:0] sctag_out ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt3(c7 ,sctag_out ,sctag_in ,c12 );
output [7:0] c7 ;
output [1:0] sctag_out ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt_all(jbus_c12 ,cmp_c12 ,cmp_sctag_out ,cmp_sctag_in
,ddr_sctag_in ,ddr_sctag_out ,jbus_sctag_in ,jbus_sctag_out ,
gclk_jbus ,gclk_cmp ,gclk_ddr ,ddr_c12 );
output [1:0] cmp_sctag_out ;
output [1:0] ddr_sctag_out ;
output [1:0] jbus_sctag_out ;
output [7:0] gclk_jbus ;
output [7:0] gclk_cmp ;
output [7:0] gclk_ddr ;
input [1:0] cmp_sctag_in ;
input [1:0] ddr_sctag_in ;
input [1:0] jbus_sctag_in ;
input jbus_c12 ;
input cmp_c12 ;
input ddr_c12 ;
bw_clk_gl_vrt1 xcmp (
.sctag_in ({cmp_sctag_in } ),
.sctag_out ({cmp_sctag_out } ),
.c7 ({gclk_cmp } ),
.c12 (cmp_c12 ) );
bw_clk_gl_vrt2 x0 (
.c7 ({gclk_ddr } ),
.sctag_out ({ddr_sctag_out } ),
.sctag_in ({ddr_sctag_in } ),
.c12 (ddr_c12 ) );
bw_clk_gl_vrt3 x1 (
.c7 ({gclk_jbus } ),
.sctag_out ({jbus_sctag_out } ),
.sctag_in ({jbus_sctag_in } ),
.c12 (jbus_c12 ) );
endmodule
|
/////////////////////////////////////////////////////////////////////
//// Author: Zhangfeifei ////
//// ////
//// Advance Test Technology Laboratory, ////
//// Institute of Computing Technology, ////
//// Chinese Academy of Sciences ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: or ////
//// Tel: +86-10-6256 5533 ext. 5673 ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2005-2006 Zhangfeifei ////
//// ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2005.12.3 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: register file of ucore processor ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "ucore_defines.v"
`define BLOCK_RAM
module regfile
(
clk_i,rst_i, //sys signal
enc,portc,dinc, // Write signal,reg address to write ,its data and byte selection
ena,porta,douta,//read porta
enb,portb,doutb //read portb
);
//the regfile,it act as the precesser's inter register bank and
//it's coprocesser0's register bank
//that is,0~31 are it's internal register bank and 32~63 are coprocesser's register bank
//so the bit 5 of the reg addr in is the general register sel signal,when it's 1,sellect the
//coprosser's register bank, when '0',select the general register bank
input clk_i;
input rst_i;
// Write signal;reg address to write,its data and byte selection
input enc;
input [5:0] portc;
input [31:0] dinc;
//porta
input ena;
input [5:0] porta;
output [31:0] douta;
//portb
input enb;
input [5:0] portb;
output [31:0] doutb;
`ifndef BLOCK_RAM
//porta
//input ena;
//input [5:0] porta;
//output reg [31:0] douta;
//portb
//input enb;
//input [5:0] portb;
//output reg [31:0] doutb;
// The register bank
reg [63:0] mem[31:0];
always @(posedge clk_i or posedge rst_i)
begin
if(rst_i)
begin:INITIAL_SECTION
integer i;
for(i=0;i<32;i=i+1) mem[i] <= 32'b0;
end
else begin
douta <= ena?mem[porta]:32'b0;
doutb <= enb?mem[portb]:32'b0;
if (enc && portc != 0)
begin
mem[portc] <= dinc;
end
end
end
`else
wire [31 : 0] tempa, tempb;
wire collision_a, collision_b;
reg collision_a_reged, collision_b_reged;
reg [31 : 0] dinc_reged;
wire enc_inter;
assign enc_inter = enc & portc != 0;
assign collision_a = (porta == portc) && ena && enc_inter;
assign collision_b = (portb == portc) && enb && enc_inter;
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
collision_a_reged <= 1'b0;
collision_b_reged <= 1'b0;
dinc_reged <= 32'b0;
end
else begin
collision_a_reged <= collision_a;
collision_b_reged <= collision_b;
dinc_reged <= dinc;
end
end
assign douta = collision_a_reged ? dinc_reged : tempa;
assign doutb = collision_b_reged ? dinc_reged : tempb;
RAMB16_S36_S36 ram0
(
.DOA(tempa),
.DOB(),
.DOPA(),
.DOPB(),
.ADDRA({3'b0,porta}),
.ADDRB({3'b0,portc}),
.CLKA(clk_i),
.CLKB(clk_i),
.DIA(32'b0),
.DIB(dinc),
.DIPA(4'b0),
.DIPB(4'b0),
.ENA(ena & ~collision_a),
.ENB(enc_inter),
.SSRA(rst_i),
.SSRB(rst_i),
.WEA(1'b0),
.WEB(1'b1)
);
RAMB16_S36_S36 ram1
(
.DOA(tempb),
.DOB(),
.DOPA(),
.DOPB(),
.ADDRA({3'b0,portb}),
.ADDRB({3'b0,portc}),
.CLKA(clk_i),
.CLKB(clk_i),
.DIA(32'b0),
.DIB(dinc),
.DIPA(4'b0),
.DIPB(4'b0),
.ENA(enb && ~collision_b),
.ENB(enc_inter),
.SSRA(rst_i),
.SSRB(rst_i),
.WEA(1'b0),
.WEB(1'b1)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; unsigned int logceil(long long first) { return first ? 8 * sizeof(long long) - __builtin_clzll(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; class DAlmostAll { public: int N; vector<vector<int>> E; vector<int> S; vector<pair<std::pair<int, int>, int>> Ans; int size(int u, int p) { S[u] = 1; for (int v : E[u]) if (v != p) S[u] += size(v, u); return S[u]; } void fill(int u, int p, int& cnt, int par, long long mul) { int mine = cnt; long long val = (cnt - par) * mul; val = min(1000000LL, val); Ans.push_back({{u + 1, p + 1}, val}); cnt++; for (int v : E[u]) if (v != p) { fill(v, u, cnt, mine, mul); } } int centroid(int u, int p) { int m = N - S[u]; for (int v : E[u]) if (v != p) m = max(m, S[v]); if (2 * m <= N) return u; for (int v : E[u]) if (v != p && 2 * S[v] > N) return centroid(v, u); return -1; } void solve(istream& cin, ostream& cout) { cin >> N; E.resize(N); for (int i = 0; i < N - 1; ++i) { int u, v; cin >> u >> v; --u; --v; E[u].push_back(v); E[v].push_back(u); } S.assign(N, 0); size(0, -1); int ctr = centroid(0, -1); long long mul = 1; int M = E[ctr].size(); size(ctr, -1); vector2<bool> B(M + 1, N + 1, false); B[0][0] = true; for (int i = 0; i < M; ++i) { for (int j = 0; j <= N; ++j) { if (B[i][j]) { B[i + 1][j] = true; B[i + 1][j + S[E[ctr][i]]] = true; } } } for (int i = 0; i <= N; ++i) { if (B[M][i] && (i + 1) * (N - i - 1) + i >= 2 * N * N / 9) { vector<bool> Left(M, false); int first = i; for (int j = M - 1; j >= 0; --j) { if (!B[j][first]) { Left[j] = true; first -= S[E[ctr][j]]; } } int c1 = 1, c2 = 1; for (int j = 0; j < M; ++j) { if (Left[j]) { fill(E[ctr][j], ctr, c1, 0, 1); } else { fill(E[ctr][j], ctr, c2, 0, i + 1); } } for (auto a : Ans) { cout << a << n ; } break; } } } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); DAlmostAll solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
|
#include <bits/stdc++.h> int main(void) { long n; long sum = 0; int i; int call = 0; scanf( %li , &n); while (n != 1) { call = 0; for (i = 2; i <= (long)sqrt((double)n); i++) if (!(n % i)) { call = 1; break; } if (call) { sum += n; n /= i; } else { sum += n; n = 1; } } printf( %li , sum + 1); return 0; }
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#include <bits/stdc++.h> using namespace std; const double EPS = 1e-10; const double PI = acos(-1.0); double tick() { static clock_t oldtick; clock_t newtick = clock(); double diff = 1.0 * (newtick - oldtick) / CLOCKS_PER_SEC; oldtick = newtick; return diff; } template <typename T> T mod(T a, T b) { return (a < b ? a : a % b); } long long mulmod(long long a, long long b, long long m) { long long q = (long long)(((long double)a * (long double)b) / (long double)m); long long r = a * b - q * m; if (r > m) r %= m; if (r < 0) r += m; return r; } template <typename T> T expo(T e, T n) { T x = 1, p = e; while (n) { if (n & 1) x = x * p; p = p * p; n >>= 1; } return x; } template <typename T> T power(T e, T n, T m) { T x = 1, p = e; while (n) { if (n & 1) x = mod(x * p, m); p = mod(p * p, m); n >>= 1; } return x; } template <typename T> T powerL(T e, T n, T m) { T x = 1, p = e; while (n) { if (n & 1) x = mulmod(x, p, m); p = mulmod(p, p, m); n >>= 1; } return x; } template <typename T> T InverseEuler(T a, T m) { return (a == 1 ? 1 : power(a, m - 2, m)); } template <typename T> T gcd(T a, T b) { return __gcd(a, b); } template <typename T> T lcm(T a, T b) { return (a * (b / gcd(a, b))); } int a[55][55]; int ans[55]; bool v[55][55]; int main() { int n; scanf( %d , &n); for (__typeof(1) i = 1; i <= n; ++i) { for (__typeof(1) j = 1; j <= n; ++j) { scanf( %d , &a[i][j]); v[i][j] = false; } } int first = 1, pos; int reqd = n - 1; for (__typeof(1) m = 1; m <= n - 1; ++m) { pos = -1; for (__typeof(1) i = 1; i <= n; ++i) { int count = 0; for (__typeof(1) j = 1; j <= n; ++j) { if (a[i][j] == first && v[i][j] == false) { count++; } } if (count == reqd) { pos = i; ans[pos] = first; first++; reqd--; for (__typeof(1) k = 1; k <= n; ++k) { v[pos][k] = true; } for (__typeof(1) k = 1; k <= n; ++k) { v[k][pos] = true; } break; } } if (pos == -1) break; } for (__typeof(1) i = 1; i <= n; ++i) { if (ans[i] == 0) { ans[i] = first; first++; } } for (__typeof(1) i = 1; i <= n; ++i) printf( %d , ans[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 10, mod = 1e9 + 7; long long n, x; long long f[N]; void solve() { scanf( %lld , &n); long long s1 = 0, s2 = 0, ans = 0; for (long long i = 1; i <= n; i++) { scanf( %lld , &x); if (x == 1) s1++; else s2++; } f[0] = 1, f[1] = 1; for (long long i = 2; i <= s1; i++) f[i] = (f[i - 1] + (i - 1) * f[i - 2]) % mod; ans = f[s1]; for (long long i = s1 + 1; i <= n; i++) ans = ans * i % mod; printf( %lld , ans); } signed main() { solve(); }
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/* Author : Prakhar Rai */ #include<bits/stdc++.h> #define ll long long #define ld long double #define LB(x,num) lower_bound(x.begin(),x.end(),num) - x.begin() #define UB(x,num) upper_bound(x.begin(),x.end(),num) - x.begin() #define BS(x,num) binary_search(x.begin(),x.end(),num) #define pb push_back #define mp make_pair #define fs first #define sc second #define vci vector<int> #define vcll vector<ll> #define vcd vector<long double> #define line(x) sort(x.begin(),x.end()) #define all(x) x.begin(),x.end() #define newl n #define vc vector #define loop(i,a,b) for(int i = a; i < b; i++) #define lol(i,a,b) for(ll i = a; i < b; i++) #define lod(i,a,b) for(ld i = 0; i < b; i++) #define mod 1000000007 #define read(v,n) lol(i,0,n) {ll x; cin >> x; v.pb(x);} #define run(a,x) for(auto x : a) #define yes YES #define no NO ll cnt; using namespace std; // ll dp[10000000]; // memset(dp, -1, sizeof(dp)); void solve() { ll n; cin >> n; vcll v; read(v, n + 2); sort(all(v)); ll sum = 0; lol(i, 0, n) { sum += v[i]; } if (sum == v[n]) { lol(i, 0, n) { cout << v[i] << ; } cout << newl; return; } sum += v[n]; lol(i, 0, n + 1) { if (sum - v[i] == v[n + 1]) { lol(j, 0, n + 1) { if (i == j) { continue; } else { cout << v[j] << ; } } cout << newl; return; } } cout << -1 << newl; return; } // FILE WITH TEST CASE void init() { #ifndef ONLINE_JUDGGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif } int main() { // init(); ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) solve(); } /* This is my journey and i shall endure the work to reach the top .*/
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#include <bits/stdc++.h> using namespace std; string s; int k; set<pair<string, int> > st; pair<string, int> tmp; int main() { cin >> s >> k; for (int i = 0; i < (int)s.length(); i++) { string q = ; q += s[i]; st.insert(make_pair(q, i)); } while (k > 1 && (int)st.size() > 0) { tmp = *st.begin(); st.erase(st.begin()); if (tmp.second + 1 < (int)s.length()) { tmp.second++; tmp.first += s[tmp.second]; st.insert(tmp); } k--; } if ((int)st.size() > 0) { tmp = *st.begin(); cout << tmp.first << endl; return 0; } cout << No such line. << endl; return 0; }
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(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export cequiv.
(**
This chapter presents our formalization of Nuprl's type system.
We will first explain how induction-recursion can be used to
define the type system in an intuitive way.
We will then explain why such a simple definition cannot be achieved
in Coq either by pure mutual induction(using the [Inductive] construct)
or by pure mutual recursion(using the [Fixpoint] construct).
As mentioned above,
this problem is well known, and we are just adapting it to our context with a slightly different explanation.
In one sentence, the problem is that the intuitive definition the evidence of typehood of an [NTerm]
is an inductive one,
but equality can be best understood as function that is structurally recursive on the evidence of typehood.
As a proof of concept, we show how to use induction-recursion to define the entire predicative
hierarchy of universes of Nuprl in the first universe of Agda's predicative hierarchy.
The use of induction-recursion to define shallow embeddings of hierarchies
of Martin Lof universes have been
often described in the literature %\cite{Dybjer:2000, McBride:2011}%.
However, since we have a deep embedding, we have to use parametrized induction-recursion
and our definitions are parametrized over (pairs of) [NTerm].
This deep approach is required for our goals of extracting an independent,
correct by construction proof assistant.
Also for Nuprl, we have to simultaneously
define the equality of types and equality of members in types,
unlike other works where just typehood and membership are defined simultaneously.
Note that two terms that are not related by [cequiv] can represent the same type.
For example, $\lambda x.((x+1)-1) =_{\mathbb{N} \rightarrow \mathbb{N}} \lambda x.x$
and $ \lambda x.x =_{\mathbb{N} \rightarrow \mathbb{N}} \lambda x.((x+1)-1)$ are equal
equality types, but the two terms are not related by [cequiv].
On the other hand, types that have the same PER are not always equal. For example,
as we will see later, the equality types
$0 =_{\mathbb{N}} 0$ and $1 =_{\mathbb{N}} 1$ are not equal types.
Hence, the equality of types in a Nuprl universe is non-trivial and our
the inductive part defines the pairs of [NTerm]s that represent equal types,
instead of just defining the [NTerm]s that denote types.
Although the inductive-recursive definition is easier to understand and
would enable a predicative formalization of all of Nuprl,
Agda does not have a tactic language,
which we heavily depend on to automate many otherwise tedious parts of proofs.
So we had to accept the lack of induction-recursion in Coq and we
finally settled on using Allen's trick to define the type system of Nuprl in Coq.
At first, this purely inductive definition in section %\ref{sec:type:ind}% might seem overly complicated.
However, it can be understood as applying the generalized recipe of %\cite{Capretta:2004}%
to the inductive-recursive definition.
One might want to revisit Fig. %\ref{fig:metatheories}% for a summary our deep embeddings.
*)
(*
\begin{figure}
\centering
\input{finalPicTikz.tex}
\caption{The left hand side summarizes our predicative embeddings. For completeness,
we also pictorially depict Werner's set theoretic
semantics\cite{Werner97setsin} on the right hand side.
}
\label{figure:embeddings}
\end{figure}
*)
(** * An Inductive Recursive Definition of Nuprl's Type System
%\label{sec:type:indrec}%
Just for this section, we will pretend that all our definitions
so far are in Agda. Given the theoretical slimilarity between
Coq and Agda%\footnote{\url{http://wiki.portal.chalmers.se/agda/pmwiki.php?n=Main.AgdaVsCoq}}%,
and the fact that all our definitions are predicative,
we think that it should be fairly straightforward to convert our
definitions to Agda. In fact, all the definitions so far can be defined
in [Set], the first predicate universe in both Coq and Agda.
We will first show the construction of just one universe of Nuprl
in Agda and then define the whole hierarchy of universes.
We only define the following 3 representative types to illustrate the idea:
- the integer type
- dependent functions
- partial types
- W types
Our Agda definition is just intended as a proof of concept. It illustrates the
elegance and the consistency strength of induction-recursion. As mentioned before,
we have defined all the types of Nuprl in Coq because the powerful
tactic machinery of Coq is critical for automating our tedious proofs.
We will assume that we had the following definitions( among others )
in Agda instead of Coq.
[[
Definition subst (t : NTerm) (v : NVar) (u : NTerm) : NTerm :=
lsubst t [(v,u)].
Definition mk_lam (v : NVar) (b : NTerm) : NTerm :=
oterm (Can NLambda) [bterm [v] b].
Definition mk_apply (f a : NTerm) : NTerm :=
oterm (NCan NApply) [bterm [] f , bterm [] a].
Definition mk_int (z : Z ) := oterm (Can (Nint z)) [].
Definition mk_Int := oterm (Can NInt) [].
Definition mk_Uni n := oterm (Can (NUni n)) [].
Definition mk_Function (T1 : NTerm) (v : NVar) (T2 : NTerm) :=
oterm (Can NFunction) [bterm [] T1, bterm [v] T2].
Definition mk_W (T1 : NTerm) (v : NVar) (T2 : NTerm) :=
oterm (Can NW) [bterm [] T1, bterm [v] T2].
]]
*)
(*
A straightforward way to define a single universe will be to define the following
by mutual induction.
- equalType : [NTerm -> NTerm -> Set]
- equalInType : [ {T1 T2 : NTerm} -> (ev: equalType T1 T2) -> (t1 t2: NTerm) -> Set]
The idea is that [equalType T1 T2] asserts that [T1] and [T2] denote
equal types and given an evidence [ev] that [T1] and [T2] denote equal types,
[equalInType ev t1 t2] are equal terms in the type denoted by [T1] and [T2].
Note that the first two arguments of equalInType are implicit.
*)
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 29; const double EPS = 1e-9; const char *crop[3] = { Carrots , Kiwis , Grapes }; int m, n, nw, nq; int main() { scanf( %d%d%d%d , &m, &n, &nw, &nq); set<int> waste[40000]; for (int i = (0); i < (nw); ++i) { int x, y; scanf( %d%d , &y, &x); x--, y--; waste[y].insert(x); } int hd[40000]; for (int i = 0, tmp = 0; i < m; i++) { hd[i] = tmp; tmp = (tmp + (n - waste[i].size())) % 3; } for (int i = (0); i < (nq); ++i) { int x, y; scanf( %d%d , &y, &x); x--, y--; if (waste[y].count(x) == 1) { puts( Waste ); } else { int tmp = distance(waste[y].begin(), waste[y].lower_bound(x)); tmp = x - tmp; tmp = (hd[y] + tmp) % 3; puts(crop[tmp]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105; int n, a[maxn], vis[maxn]; int gcd(int a, int b) { while (b) { int c = a % b; a = b; b = c; } return a; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int flag = 0; vector<int> ans; for (int i = 1; i <= n; i++) { if (vis[i]) continue; int now = i; int cnt = 0; while (!vis[now]) { vis[now] = i; now = a[now]; cnt++; } if (now != i) return puts( -1 ), 0; if (cnt % 2 == 0) cnt /= 2; ans.push_back(cnt); } long long A = ans[0]; for (int i = 1; i < ans.size(); i++) A = A * ans[i] / gcd(A, ans[i]); cout << A << endl; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Master Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:11:05 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_mast(clk, rst,
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
mast_go, mast_we, mast_adr, mast_sel, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait,
pt_sel, mast_pt_in, mast_pt_out
);
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// INTERNAL DMA INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [3:0] mast_sel; // Select lines for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg mast_cyc, mast_stb;
reg mast_we_r;
reg [3:0] mast_be;
reg [31:0] mast_dout;
wire [31:0] mast_din_sel;
////////////////////////////////////////////////////////////////////
//
// Pass-Through Interface
//
assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
pt_sel ? mast_pt_in :
{mast_din_sel, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
assign mast_din_sel =
(mast_sel=='b0001 || mast_sel=='b0010 || mast_sel=='b0100 || mast_sel=='b1000)?
{mast_din[7:0],mast_din[7:0],mast_din[7:0],mast_din[7:0]}:
(mast_sel=='b0011 || mast_sel=='b1100)?
{mast_din[15:0],mast_din[15:0]}:mast_din;
assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
////////////////////////////////////////////////////////////////////
//
// DMA Engine Interface
//
always @(posedge clk)
if (wb_ack_i) begin
// Capture read data according to the select mask
case (mast_sel)
'b0001: mast_dout <= wb_data_i[7:0];
'b0010: mast_dout <= wb_data_i[15:8];
'b0100: mast_dout <= wb_data_i[23:16];
'b1000: mast_dout <= wb_data_i[31:24];
'b0011: mast_dout <= wb_data_i[15:0];
'b1100: mast_dout <= wb_data_i[31:16];
'b1111: mast_dout <= wb_data_i;
endcase
end
always @(posedge clk)
mast_be <= #1 mast_sel;
always @(posedge clk)
mast_we_r <= #1 mast_we;
always @(posedge clk)
mast_cyc <= #1 mast_go;
always @(posedge clk)
mast_stb <= #1 mast_go & !mast_wait;
assign mast_drdy = wb_ack_i;
assign mast_err = wb_err_i;
endmodule
|
#include <bits/stdc++.h> const int kInf = 0x3f3f3f3f; int len, n; int msk[200010]; int mem[21][1 << 20]; int f[200010], s[200010]; int conv(char *s) { int res = 0; for (int i = 0; i < len; i++) res = (res << 1) + (s[i] - 0 ); return res; } int g(int i, int j) { int p = msk[i], q = msk[j]; for (int i = len; i >= 0; i--) if ((p & ((1 << i) - 1)) == (q >> (len - i))) return i; assert(0); } inline void upd(int &x, int y) { if (y < x) x = y; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { static char ts[22]; scanf( %s , ts); len = strlen(ts); msk[i] = conv(ts); } for (int i = 2; i <= n; i++) s[i] = s[i - 1] + g(i - 1, i); memset(mem, 0x3f, sizeof(mem)); mem[0][0] = 0; for (int i = 1; i <= n; i++) { f[i] = kInf; if (i < n) { for (int l = 0; l <= len; l++) { int tmp = mem[l][msk[i + 1] >> (len - l)]; if (tmp != kInf) upd(f[i], tmp + i * len - s[i] - l); } for (int l = 0; l <= len; l++) upd(mem[l][msk[i] & ((1 << l) - 1)], f[i] + s[i + 1] - i * len); } else { f[i] = mem[0][0] + i * len - s[i]; } } printf( %d n , f[n]); }
|
module ComWithCC3200(
input CC3200_SPI_CLK,
input CC3200_SPI_CS,
output reg CC3200_SPI_DIN,
input CC3200_SPI_DOUT,
input Envelop,
output reg [7:0] Line_Num,
output reg Enable,
output reg [1:0] Zoom,
output reg [5:0] Gain,
input [7:0] Trans_Data,
output reg [8:0] Trans_Addr
);
reg [15:0] Config_Data_Shift;
reg [3:0] SPI_Counter;
reg [7:0] Shift_Data;
//write
always @(posedge CC3200_SPI_CLK or negedge CC3200_SPI_CS )
begin
if(~CC3200_SPI_CS)
begin
//Enable <= Config_Data_Shift[7];
Line_Num <= Config_Data_Shift[7:0];
Zoom <= Config_Data_Shift[15:14];
Gain <= Config_Data_Shift[13:8];
end
else begin
if(Trans_Addr == 9'd1 ) begin // wr
Config_Data_Shift[15:8] <={Config_Data_Shift[14:8],CC3200_SPI_DOUT};
end
else if(Trans_Addr == 9'd2 ) begin //wr
Config_Data_Shift[7:0] <={Config_Data_Shift[6:0],CC3200_SPI_DOUT} ;
end
end
end
//read
always @(negedge CC3200_SPI_CLK or negedge CC3200_SPI_CS ) begin
if(~CC3200_SPI_CS) begin
SPI_Counter <= 8'd0;
Shift_Data <=Trans_Data;
end
else begin
if(~Envelop) begin //rd
SPI_Counter <= SPI_Counter + 1'b1;
CC3200_SPI_DIN <= Shift_Data[7];
Shift_Data <= Shift_Data <<1;
end
end
end
always @(posedge CC3200_SPI_CS or posedge Envelop) begin //cs 8 bit once
if(Envelop) begin
Trans_Addr <= 9'd0;
end
else begin
Trans_Addr <= Trans_Addr + 1'b1;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_vb_e
//
// Generated
// by: wig
// on: Wed Jul 19 05:44:57 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_vb_e.v,v 1.3 2006/07/19 07:35:16 wig Exp $
// $Date: 2006/07/19 07:35:16 $
// $Log: inst_vb_e.v,v $
// Revision 1.3 2006/07/19 07:35:16 wig
// Updated testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
udc: Verilog HEAD HOOK inst_bc_i
//
//
// Start of Generated Module rtl of inst_vb_e
//
// No user `defines in this module
module inst_vb_e
//
// Generated Module inst_bc_i
//
(
);
udc: Verilog PARA HOOK inst_bc_i
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
udc: Verilog BODY HOOK inst_bc_i
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_vb_e
//
udc: Verilog FOOT HOOK two lines inst_bc_i
second line inst_bc_i, config here inst_vb_e_rtl_conf and description verilog udc
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_BLACKBOX_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a;
reg [31:0] b;
wire [2:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
// verilator lint_off IMPLICIT
not #(0.108) NT0 (nt0, a[0]);
and #1 AN0 (an0, a[0], b[0]);
nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
or OR0 (or0, a[0], b[0]);
nor NR0 (nr0, a[0], b[0], b[2]);
xor (xo0, a[0], b[0]);
xnor (xn0, a[0], b[0], b[2]);
// verilator lint_on IMPLICIT
parameter BITS=32;
wire [BITS-1:0] ba;
buf BARRAY [BITS-1:0] (ba, a);
`ifdef verilator
specify
specparam CDS_LIBNAME = "foobar";
(nt0 *> nt0) = (0, 0);
endspecify
specify
// delay parameters
specparam
a$A1$Y = 1.0,
b$A0$Z = 1.0;
// path delays
(A1 *> Q) = (a$A1$Y, a$A1$Y);
(A0 *> Q) = (b$A0$Y, a$A0$Z);
endspecify
`endif
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 32'h18f6b034;
b <= 32'h834bf892;
end
if (cyc==2) begin
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf !== 3'b100) $stop;
if (nt0 !== 1'b1) $stop;
if (an0 !== 1'b0) $stop;
if (nd0 !== 1'b1) $stop;
if (or0 !== 1'b0) $stop;
if (nr0 !== 1'b1) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b1) $stop;
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (bf !== 3'b111) $stop;
if (nt0 !== 1'b0) $stop;
if (an0 !== 1'b1) $stop;
if (nd0 !== 1'b0) $stop;
if (or0 !== 1'b1) $stop;
if (nr0 !== 1'b0) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b0) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int x = 0; while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x; } const int maxn = (1 << 21) + 3; const int INF = 0x3f3f3f3f; struct segtree { int n; int tag[maxn], mmin[maxn]; int ul, ur, uv; void update(int o, int l, int r) { if (ul <= l && ur >= r) { tag[o] = max(tag[o], uv); mmin[o] = max(mmin[o], uv); return; } int mid = (l + r) / 2; if (ul <= mid) update(o * 2, l, mid); if (ur > mid) update(o * 2 + 1, mid + 1, r); mmin[o] = max(min(mmin[o * 2], mmin[o * 2 + 1]), tag[o]); } void modify(int l, int r, int v) { if (l > r) return; ul = l, ur = r, uv = v; update(1, 1, n); } int p, x; int query2(int o, int l, int r) { if (max(tag[o], mmin[o]) >= x) return n + 1; if (l == r) return l; int mid = (l + r) / 2; if (mmin[o * 2] < x) return query2(o * 2, l, mid); else return query2(o * 2 + 1, mid + 1, r); } int query(int o, int l, int r) { if (max(tag[o], mmin[o]) >= x) return n + 1; if (l == r) return l; int mid = (l + r) / 2; if (p > mid) return query(o * 2 + 1, mid + 1, r); else { int ans = query(o * 2, l, mid); if (ans != n + 1) return ans; else return query2(o * 2 + 1, mid + 1, r); } } int query(int p, int x) { if (p > n) return n + 1; this->p = p, this->x = x; return query(1, 1, n); } } t; struct edge { int l, r; bool operator<(const edge& rhs) const { return r < rhs.r; } } e[maxn]; struct query { int id, x, y; bool operator<(const query& rhs) const { return y < rhs.y; } } q[maxn]; int ans[maxn]; void write(int x) { if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(int x) { write(x); putchar( n ); } int main() { int n = t.n = read(), k = read(); for (int i = 1; i <= k; i++) e[i].l = read(), e[i].r = read(); sort(e + 1, e + k + 1); int m = read(); for (int i = 1; i <= m; i++) q[i].id = i, q[i].x = read(), q[i].y = read(); sort(q + 1, q + m + 1); int now = 1; for (int i = 1; i <= m; i++) { while (now <= k && e[now].r <= q[i].y) { t.modify(e[now].l + 1, e[now].r, e[now].l); now++; } ans[q[i].id] = t.query(q[i].x + 1, q[i].x) - 1; } for (int i = 1; i <= m; i++) writeln(ans[i]); }
|
#include <bits/stdc++.h> using namespace std; priority_queue<int, vector<int>, less<int> > num; int main() { int n, x; cin >> n; for (int i = 1; i <= n; i++) { cin >> x; num.push(x); } cout << ((num.top()) xor (x)) << n ; }
|
#include <bits/stdc++.h> using namespace std; double EPS = 1e-9; int INF = 2000000000; long long INFF = 8000000000000000000LL; double PI = acos(-1); string IntToString(int a) { char x[100]; sprintf(x, %d , a); string s = x; return s; } int StringToInt(string a) { char x[100]; strcpy(x, a.c_str()); int res; sscanf(x, %d , &res); return res; } int spaces = 0; char c[5]; int main() { while (scanf( %c , &c[0]) != EOF && c[0] != n ) { scanf( %c%c , &c[1], &c[2]); if (c[2] == > ) { spaces += 2; for (int(i) = (1); (i) <= (spaces - 2); (i)++) printf( ); for (int(i) = (0); (i) <= (2); (i)++) printf( %c , c[i]); puts( ); } else { scanf( %c , &c[3]); spaces -= 2; for (int(i) = (1); (i) <= (spaces); (i)++) printf( ); for (int(i) = (0); (i) <= (3); (i)++) printf( %c , c[i]); puts( ); } } return 0; }
|
#include <bits/stdc++.h> namespace std { template <typename A, typename B> inline string to_string(pair<A, B> p); template <typename A, typename B, typename C> inline string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> inline string to_string(tuple<A, B, C, D> p); inline string to_string(const string& s) { return + s + ; } inline string to_string(const char* s) { return to_string((string)s); } inline string to_string(bool b) { return (b ? true : false ); } inline string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> inline string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> inline string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> inline string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> inline string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> inline string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } } // namespace std inline void debug_out() { std::cerr << std::endl; } template <typename Head, typename... Tail> inline void debug_out(Head H, Tail... T) { std::cerr << << std::to_string(H); debug_out(T...); } using namespace std; int main() { int n, m; scanf( %d%d , &n, &m); vector<vector<int>> e(n); for (int i = 0; i < m; i++) { int v, u; scanf( %d%d , &v, &u); v--; u--; e[v].push_back(u); e[u].push_back(v); } vector<pair<int, int>> color(n); vector<int> b(n); for (int i = 0; i < n; i++) { scanf( %d , &color[i].first); color[i].first--; color[i].second = i; b[i] = color[i].first; } sort((color).begin(), (color).end()); bool good = true; vector<int> use(n); for (int i = 0; i < n; i++) { int v = color[i].second; int tgt = color[i].first; vector<int> mask(tgt + 1); for (auto u : e[v]) { if (use[u]) { assert(b[u] <= tgt); mask[b[u]] = 1; } } for (int j = 0; j < tgt; j++) { if (mask[j] == 0) { good = false; } } if (mask[tgt]) { good = false; } use[v] = 1; } if (!good) { puts( -1 ); return 0; } for (auto x : color) { cout << x.second + 1 << ; } cout << endl; return 0; }
|
//manages all the stuff needed to read and write to the flash ROM
module flash_manager(
clock, reset,
dots,
writemode,
wdata,
dowrite,
raddr,
frdata,
doread,
busy,
flash_data,
flash_address,
flash_ce_b,
flash_oe_b,
flash_we_b,
flash_reset_b,
flash_sts,
flash_byte_b,
fsmstate);
input reset, clock; //clock and reset
output [639:0] dots; //outputs to dot-matrix to help debug flash, not necessary
input writemode; //if true then we're in write mode, else we're in read mode
input [15:0] wdata; //data to be written
input dowrite; //putting this high tells the manager the data it has is new, write it
input [22:0] raddr; //address to read from
output[15:0] frdata; //data being read
reg[15:0] rdata;
input doread; //putting this high tells the manager to perform a read on the current address
output busy; //and an output to tell folks we're still working on the last thing
reg busy;
inout [15:0] flash_data; //direct passthrough from labkit to low-level modules (flash_int and test_fsm)
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b;
output flash_reset_b, flash_byte_b;
input flash_sts;
wire flash_busy; //except these, which are internal to the interface
wire[15:0] fwdata;
wire[15:0] frdata;
wire[22:0] address;
wire [1:0] op;
reg [1:0] mode;
wire fsm_busy;
reg[2:0] state; //210
output[11:0] fsmstate;
wire [7:0] fsmstateinv;
assign fsmstate = {state,flash_busy,fsm_busy,fsmstateinv[4:0],mode}; //for debugging only
//this guy takes care of /some/ of flash's tantrums
flash_int flash(reset, clock, op, address, fwdata, frdata, flash_busy, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b);
//and this guy takes care of the rest of its tantrums
test_fsm fsm (reset, clock, op, address, fwdata, frdata, flash_busy, dots, mode, fsm_busy, wdata, raddr, fsmstateinv);
parameter MODE_IDLE = 0;
parameter MODE_INIT = 1;
parameter MODE_WRITE = 2;
parameter MODE_READ = 3;
parameter HOME = 3'd0;
parameter MEM_INIT = 3'd1;
parameter MEM_WAIT = 3'd2;
parameter WRITE_READY= 3'd3;
parameter WRITE_WAIT = 3'd4;
parameter READ_READY = 3'd5;
parameter READ_WAIT = 3'd6;
always @ (posedge clock)
if(reset)
begin
busy <= 1;
state <= HOME;
mode <= MODE_IDLE;
end
else begin
case(state)
HOME://0 //we always start here
if(!fsm_busy)
begin
busy <= 0;
if(writemode)
begin
busy <= 1;
state <= MEM_INIT;
end
else
begin
busy <= 1;
state <= READ_READY;
end
end
else
mode <= MODE_IDLE;
MEM_INIT://1 //begin wiping the memory
begin
busy <= 1;
mode <= MODE_INIT;
if(fsm_busy) //to give the fsm a chance to raise its busy signal
state <= MEM_WAIT;
end
MEM_WAIT://2 //finished wiping
if(!fsm_busy)
begin
busy <= 0;
state<= WRITE_READY;
end
else
mode <= MODE_IDLE;
WRITE_READY://3 //waiting for data to write to flash
if(dowrite)
begin
busy <= 1;
mode <= MODE_WRITE;
end
else if(busy)
state <= WRITE_WAIT;
else if(!writemode)
state <= READ_READY;
WRITE_WAIT://4 //waiting for flash to finish writing
if(!fsm_busy)
begin
busy <= 0;
state <= WRITE_READY;
end
else
mode <= MODE_IDLE;
READ_READY://5 //ready to read data
if(doread)
begin
busy <= 1;
mode <= MODE_READ;
if(busy) //lets the fsm raise its busy level
state <= READ_WAIT;
end
else
busy <= 0;
READ_WAIT://6 //waiting for flash to give the data up
if(!fsm_busy)
begin
busy <= 0;
state <= READ_READY;
end
else
mode <= MODE_IDLE;
default: begin //should never happen...
state <= 3'd7;
end
endcase
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_fdiv_32ns_32ns_32_16
#(parameter
ID = 2,
NUM_STAGE = 16,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_fdiv_14_no_dsp_32 feedforward_ap_fdiv_14_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string proc(int a, int b) { if (a * 2 > b) return noob ; if (a * 5 > b) return random ; if (a * 10 > b) return average ; if (a * 100 > b) return hardcore ; return pro ; } int main() { int i, n, x; string s; map<string, int> score; cin >> n; while (n--) { cin >> s >> x; if (score.find(s) == score.end()) score[s] = 0; score[s] = max(score[s], x); } vector<int> list; for (typeof(score.begin()) it = score.begin(); it != score.end(); it++) list.push_back(it->second); sort(list.rbegin(), list.rend()); cout << ((int)score.size()) << endl; for (typeof(score.begin()) it = score.begin(); it != score.end(); it++) { for (i = 0; i < (int)(((int)list.size())); i++) if (list[i] == it->second) break; cout << it->first << << proc(i, ((int)list.size())) << endl; } return 0; }
|
// bsg_fsb_node_level_shift_fsb_domain
//
// This module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink - level shifting cell must be in the same power doamin as the
// signal's destination
//
// This is 1 of 4 modules that shift all the signals between the FSB and
// a node. Each of the modules has a different strategy about which power
// domain the level-shifters should be in:
//
// 1) bsg_fsb_node_level_shift_all_sink
// -- All level shifters in same power domain as the input pin
// 2) bsg_fsb_node_level_shift_all_source
// -- All level shifters in same power domain as the output pin
// * 3) bsg_fsb_node_level_shift_fsb_domain
// -- All level shifters in same power domain as the fsb module
// 4) bsg_fsb_node_level_shift_node_domain
// -- All level shifters in same power domain as the node module
//
`include "bsg_defines.v"
module bsg_fsb_node_level_shift_fsb_domain #(parameter `BSG_INV_PARAM(ring_width_p ))
(
input en_ls_i,
input clk_i,
input reset_i,
output clk_o,
output reset_o,
//----- ATTACHED TO FSB -----//
output fsb_v_i_o,
output [ring_width_p-1:0] fsb_data_i_o,
input fsb_yumi_o_i,
input fsb_v_o_i,
input [ring_width_p-1:0] fsb_data_o_i,
output fsb_ready_i_o,
//----- ATTACHED TO NODE -----//
output node_v_i_o,
output [ring_width_p-1:0] node_data_i_o,
input node_ready_o_i,
input node_v_o_i,
input [ring_width_p-1:0] node_data_o_i,
output node_yumi_i_o
);
// Level Shift Clock
bsg_level_shift_up_down_source #(.width_p(1)) clk_ls_inst
(
.v0_en_i(1'b1),
.v0_data_i(clk_i),
.v1_data_o(clk_o)
);
// Level Shift Reset
bsg_level_shift_up_down_source #(.width_p(1)) reset_ls_inst
(
.v0_en_i(1'b1),
.v0_data_i(reset_i),
.v1_data_o(reset_o)
);
// NODE v_o --> FSB v_i
bsg_level_shift_up_down_sink #(.width_p(1)) n2f_v_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_v_o_i),
.v1_data_o(fsb_v_i_o)
);
// NODE data_o --> FSB data_i
bsg_level_shift_up_down_sink #(.width_p(ring_width_p)) n2f_data_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_data_o_i),
.v1_data_o(fsb_data_i_o)
);
// FSB yumi_o --> NODE yumi_i
bsg_level_shift_up_down_source #(.width_p(1)) f2n_yumi_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_yumi_o_i),
.v1_data_o(node_yumi_i_o)
);
// FSB v_o --> NODE v_i
bsg_level_shift_up_down_source #(.width_p(1)) f2n_v_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_v_o_i),
.v1_data_o(node_v_i_o)
);
// FSB data_o --> NODE data_i
bsg_level_shift_up_down_source #(.width_p(ring_width_p)) f2n_data_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_data_o_i),
.v1_data_o(node_data_i_o)
);
// NODE ready_o --> FSB ready_i
bsg_level_shift_up_down_sink #(.width_p(1)) n2f_ready_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_ready_o_i),
.v1_data_o(fsb_ready_i_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb_node_level_shift_fsb_domain)
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int mod = 1e9 + 7; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == w || s[i] == m ) { cout << 0; return 0; } } int a, b = 1, c = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == s[i - 1] && (s[i] == n || s[i] == u )) { a = (b + c) % mod; } else a = b; c = b; b = a; } cout << a; }
|
#include <bits/stdc++.h> const long long RXD = 1e9 + 7; const long long N = 1e5 + 1000; using namespace std; long long C[N][110], a[N], s[N][110], n, m, l, r, K; long long read() { long long x = 0, f = 1, c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x * f; } int main() { C[0][0] = 1; for (long long i = 1; i <= 100100; i++) for (long long j = 0; j <= i && j <= 105; j++) C[i][j] = (j == 0) ? 1 : (C[i - 1][j] + C[i - 1][j - 1]) % RXD; n = read(); m = read(); for (long long i = 1; i <= n; i++) a[i] = read(); for (long long i = 1; i <= m; i++) { l = read(); r = read(); K = read(); for (long long i = 0; i <= K; i++) s[l][i] = (s[l][i] + C[K][K - i]) % RXD; for (long long i = 0; i <= K; i++) s[r + 1][i] = (s[r + 1][i] - C[K + r + 1 - l][K - i] + RXD) % RXD; } for (long long i = 1; i <= n; i++) for (long long j = 101; j; j--) s[i + 1][j - 1] = ((s[i + 1][j - 1] + s[i][j]) % RXD + s[i][j - 1]) % RXD; for (long long i = 1; i <= n; i++) printf( %d , ((a[i] + s[i][0]) % RXD + RXD) % RXD); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; void read(long long &x) { x = 0; char ch = getchar(); long long pd = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) { pd = -pd; } ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= pd; } long long gcd(long long x, long long y) { return !x ? y : gcd(y % x, x); } long long l, n, m, aa[10010]; long long a[N], b[N]; long long ans, lcm, x, y, bg; long long mul(long long a, long long b, long long P) { long long s = 0; for (; b; b >>= 1, a = (a + a) % P) if (b & 1) s = (s + a) % P; return s; } long long exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return a; } long long gd = exgcd(b, a % b, y, x); y -= a / b * x; return gd; } long long excrt() { ans = a[1], lcm = b[1], x, y; for (long long i = 2; i <= l; i++) { long long B = b[i], C = (a[i] - ans % B + B) % B; long long d = exgcd(lcm, B, x, y); if (C % d) return -1; B = B / d; C = C / d; x = (x + B) % B; x = mul(x, C, B); ans += x * lcm; lcm *= B; ans %= lcm; } return ans == 0 ? lcm : ans; } signed main() { scanf( %lld%lld%lld , &n, &m, &l); if (l > m) { puts( NO ); return 0; } for (register long long i = 1; i <= l; ++i) { scanf( %lld , &aa[i]); b[i] = aa[i]; } for (register long long i = 1; i <= l; ++i) { a[i] = (1 - i); while (a[i] < aa[i]) { a[i] += aa[i]; } a[i] %= aa[i]; } long long yy = excrt(); if (yy == -1) { puts( NO ); return 0; } if (yy + l - 1 > m) { puts( NO ); return 0; } if (lcm > n) { puts( NO ); return 0; } for (register long long i = 1; i <= l; ++i) { if (gcd(lcm, yy + i - 1) != aa[i]) { puts( NO ); return 0; } } puts( YES ); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= 0;
else
x[9:0] <= {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char a[26], b[26], c[26], d[26]; scanf( %s , a); scanf( %s , b); int i = 0, m = 0, n = 0, k, q, w, j = 0, flag = 0, t = 0; while (a[i] != 0 ) { if (a[i] == | ) m = i; i++; } q = m; w = i - m - 1; n = i; while (b[j] != 0 ) { j++; } i = 0; for (i = 0; i < q; i++) c[i] = a[i]; for (i = 0; i < w; i++) d[i] = a[q + i + 1]; i = 0; while (j > 0) { if (q < w) { c[q++] = b[i++]; j--; } else if (q >= w) { d[w++] = b[i++]; j--; } } if (q == w) { for (i = 0; i < q; i++) printf( %c , c[i]); printf( | ); for (i = 0; i < w; i++) printf( %c , d[i]); } else { printf( Impossible ); } return 0; }
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [18:0] c;
// Output of stage 2
wire [18:0] cx;
// Output of stage 3
wire [5:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [5:0] b;
reg [5:0] r_b;
reg [18:0] e;
reg [18:0] r_e;
// 2nd stage
reg [18:0] r_c;
reg [18:0] rr_e;
reg [5:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [18:0] r_qx;
reg [5:0] rb;
reg clk,reset;
reg [18:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 18'b000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000001000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000010000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b001000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 18'b000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
import "DPI-C" context function int init_socket();
import "DPI-C" context function void close_socket();
import "DPI-C" context function void senduart(input bit[7:0] in);
import "DPI-C" context function bit[8:0] recuart();
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
init_socket();
end
final begin
close_socket();
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_buf[8] && ~cs)
uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
senduart(bus_wr_val[7:0]);
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
if (bus_addr[3:0] == 4'b1100) begin
inter<=1'b1;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= (uart_buf[8] ? 32'b10 : 32'b0);
end
end
end
bus_ack <= cs;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 500; int n, ret, cnt; char a[maxn][maxn]; int arr[maxn][maxn]; pair<int, int> par[maxn][maxn]; multiset<pair<int, int> > s; pair<int, int> root(pair<int, int> c) { if (par[c.first][c.second].first < 0) return c; return par[c.first][c.second] = root(par[c.first][c.second]); } void merge(pair<int, int> A, pair<int, int> B) { if ((A = root(A)) == (B = root(B))) return; if (par[A.first][A.second].first < par[B.first][B.second].first) swap(A, B); par[B.first][B.second].first += par[A.first][A.second].first; par[A.first][A.second] = B; } void add(pair<int, int> A) { A = root(A); if (arr[A.first][A.second] == 0) ret += -par[A.first][A.second].first; arr[A.first][A.second]++; } void Add(pair<int, int> A) { int i = A.first, j = A.second; if (a[i][j] == X ) ret++; if (a[i][j] != X ) add({i, j}); if (i - 1 >= 0 && a[i - 1][j] != X ) add({i - 1, j}); if (i + 1 < n && a[i + 1][j] != X ) add({i + 1, j}); if (j - 1 >= 0 && a[i][j - 1] != X ) add({i, j - 1}); if (j + 1 < n && a[i][j + 1] != X ) add({i, j + 1}); } void rem(pair<int, int> A) { A = root(A); arr[A.first][A.second]--; if (arr[A.first][A.second] == 0) ret -= -par[A.first][A.second].first; } void Rem(pair<int, int> A) { int i = A.first, j = A.second; if (a[i][j] == X ) ret--; if (a[i][j] != X ) rem({i, j}); if (i - 1 >= 0 && a[i - 1][j] != X ) rem({i - 1, j}); if (i + 1 < n && a[i + 1][j] != X ) rem({i + 1, j}); if (j - 1 >= 0 && a[i][j - 1] != X ) rem({i, j - 1}); if (j + 1 < n && a[i][j + 1] != X ) rem({i, j + 1}); } int main() { ios_base::sync_with_stdio(false); int K; cin >> n >> K; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; for (int i = 0; i < maxn; i++) for (int j = 0; j < maxn; j++) par[i][j] = {-1, -1}; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (a[i][j] == . ) { if (i + 1 < n && a[i + 1][j] == . ) merge({i, j}, {i + 1, j}); if (j + 1 < n && a[i][j + 1] == . ) merge({i, j}, {i, j + 1}); } int ans = 0; for (int i = K - 1; i < n; i++) { memset(arr, 0, sizeof arr); ret = 0; for (int j = i - K + 1; j <= i; j++) for (int k = 0; k < K; k++) { Add({j, k}); } ans = max(ans, ret); for (int j = K; j < n; j++) { for (int k = i - K + 1; k <= i; k++) Add({k, j}); for (int k = i - K + 1; k <= i; k++) Rem({k, j - K}); ans = max(ans, ret); } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_BLACKBOX_V
`define SKY130_FD_SC_MS__A221O_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_BLACKBOX_V
|
//--------------------------------------------------------------------------------
// spi_slave.v
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// spi_slave
//
//--------------------------------------------------------------------------------
//
// 01/22/2011 - Ian Davis - Added meta data generator.
//
`timescale 1ns/100ps
module spi_slave (
// system signals
input wire clk,
input wire rst,
//
input wire send,
input wire [31:0] send_data,
input wire [3:0] send_valid,
input wire [31:0] dataIn,
output wire [39:0] cmd,
output wire execute,
output wire busy,
// SPI signals
input wire spi_cs_n,
input wire spi_sclk,
input wire spi_mosi,
output wire spi_miso
);
// TODO: recode SPI into SPI clock synchronous code, use CDC for data bytes
// reg [7:0] spi_cnt;
// reg [7:0] spi_byte;
//
// always @ (posedge spi_sclk, posedge spi_cs_n)
// if (spi_cs_n) spi_cnt <= 0;
// else spi_cnt <= spi_cnt + 'b1;
//
// always @ (posedge spi_sclk)
// spi_byte <= {spi_byte[6:0], spi_mosi};
//
// Registers...
//
reg query_id;
reg query_metadata;
reg query_dataIn;
reg dly_execute;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
//
// Synchronize inputs...
//
full_synchronizer spi_sclk_sync (clk, rst, spi_sclk, sync_sclk);
full_synchronizer spi_cs_n_sync (clk, rst, spi_cs_n, sync_cs_n);
//
// Instantaite the meta data generator...
//
wire [7:0] meta_data;
meta_handler meta_handler(
// system signals
.clock (clk),
.extReset (rst),
//
.query_metadata (query_metadata),
.xmit_idle (!busy && !send && byteDone),
.writeMeta (writeMeta),
.meta_data (meta_data)
);
//
// Instantiate the heavy lifters...
//
spi_receiver spi_receiver(
// system signals
.clk (clk),
.rst (rst),
// SPI signals
.spi_sclk (sync_sclk),
.spi_mosi (spi_mosi),
.spi_cs_n (sync_cs_n),
//
.transmitting (busy),
.opcode (opcode),
.opdata (opdata),
.execute (execute)
);
spi_transmitter spi_transmitter(
// system signals
.clk (clk),
.rst (rst),
// SPI signals
.spi_sclk (sync_sclk),
.spi_cs_n (sync_cs_n),
.spi_miso (spi_miso),
//
.send (send),
.send_data (send_data),
.send_valid (send_valid),
.writeMeta (writeMeta),
.meta_data (meta_data),
.query_id (query_id),
.query_dataIn (query_dataIn),
.dataIn (dataIn),
.busy (busy),
.byteDone (byteDone)
);
//
// Process special SPI commands not handled by core decoder...
//
always @(posedge clk)
begin
dly_execute <= execute;
if (!dly_execute && execute) begin
query_id <= (opcode == 8'h02);
query_metadata <= (opcode == 8'h04);
query_dataIn <= (opcode == 8'h06);
end else begin
query_id <= 1'b0;
query_metadata <= 1'b0;
query_dataIn <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_PP_SYMBOL_V
`define SKY130_FD_SC_LP__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long long inf = 2e18; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; int add(int a, int b) { int res = (a + b) % mod; if (res < 0) res += mod; return res; } int mult(int a, int b) { int res = (a * 1LL * b) % mod; if (res < mod) res += mod; return res; } int power(int a, int b) { int res = 1; while (b) { if ((b % 2) == 1) res = mult(res, a); a = mult(a, a); b /= 2; } return res; } template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string &s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(char c) { return to_string(string(1, c)); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void dbg() { cout << endl; } template <typename Head, typename... Tail> void dbg(Head H, Tail... T) { cout << << to_string(H); dbg(T...); } void solve() { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } vector<int> dp(1 << 22, 0); for (int i = 0; i < n; i++) { dp[v[i]] = v[i]; } for (int mask = 1; mask < (1 << 22); mask++) { for (int i = 0; i < 22; i++) { if (mask & (1 << i)) { dp[mask] = max(dp[mask], dp[mask ^ (1 << i)]); } } } for (int i = 0; i < n; i++) { int no = ((1 << 22) - 1) & (~v[i]); if (dp[no]) { cout << dp[no] << ; } else { cout << -1 ; } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(10); int t = 1; for (int i = 1; i <= t; i++) { solve(); } }
|
//`include ".\src\image_capture_manager_S00_AXI.v"
`timescale 1 ns / 1 ps
module image_capture_manager #
(
// Users to add parameters here
parameter integer START_IMAGE_CAPTURE_COMMAND = 1,
parameter integer STOP_IMAGE_CAPTURE_COMMAND = 2,
parameter integer RESET_IMAGE_CAPTURE_COMMAND = 3,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output reg image_capture_enabled = 0,
output reg clear_memory = 0,
output reg reset,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
//localparam RESET_CYCLES = 16;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] register_read;
reg [C_S00_AXI_DATA_WIDTH - 1 : 0] register_write;
reg [1:0] register_operation;
reg [7:0] register_number;
//reg [7:0] reset_counter;
// Instantiation of Axi Bus Interface S00_AXI
axi_slave_impl # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.NUMBER_OF_REGISTERS(4)
) image_capture_manager_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.register_read(register_read),
.register_write(register_write),
.register_number(register_number),
.register_operation(register_operation)
);
// Add user logic here
always @(posedge s00_axi_aclk)
begin
if(~s00_axi_aresetn)
begin
clear_memory <= 0;
image_capture_enabled <= 0;
register_operation <= 0;
register_write <= 0;
register_number <= 0;
reset <= 1;
//reset_counter <= 0;
end
else
begin
if(s00_axi_wstrb[0] && s00_axi_wvalid)
begin
if(s00_axi_wdata == START_IMAGE_CAPTURE_COMMAND)
begin
clear_memory <= 0;
image_capture_enabled <= 1;
end
else if(s00_axi_wdata == STOP_IMAGE_CAPTURE_COMMAND)
begin
clear_memory <= 1;
image_capture_enabled <= 0;
end
else if(s00_axi_wdata == RESET_IMAGE_CAPTURE_COMMAND)
begin
reset <= 0;
//reset_counter <= reset_counter + 1;
//if(reset_counter ==
end
end
else
clear_memory <= 0;
end
end
// User logic ends
endmodule
|
module SevenSegment(
output reg [6:0] display,
output reg [3:0] digit,
input wire [15:0] nums,
input wire rst,
input wire clk
);
reg [15:0] clk_divider;
reg [3:0] display_num;
always @ (posedge clk, posedge rst) begin
if (rst) begin
clk_divider <= 15'b0;
end else begin
clk_divider <= clk_divider + 15'b1;
end
end
always @ (posedge clk_divider[15], posedge rst) begin
if (rst) begin
display_num <= 4'b0000;
digit <= 4'b1111;
end else begin
case (digit)
4'b1110 : begin
display_num <= nums[7:4];
digit <= 4'b1101;
end
4'b1101 : begin
display_num <= nums[11:8];
digit <= 4'b1011;
end
4'b1011 : begin
display_num <= nums[15:12];
digit <= 4'b0111;
end
4'b0111 : begin
display_num <= nums[3:0];
digit <= 4'b1110;
end
default : begin
display_num <= nums[3:0];
digit <= 4'b1110;
end
endcase
end
end
always @ (*) begin
case (display_num)
0 : display = 7'b1000000; //0000
1 : display = 7'b1111001; //0001
2 : display = 7'b0100100; //0010
3 : display = 7'b0110000; //0011
4 : display = 7'b0011001; //0100
5 : display = 7'b0010010; //0101
6 : display = 7'b0000010; //0110
7 : display = 7'b1111000; //0111
8 : display = 7'b0000000; //1000
9 : display = 7'b0010000; //1001
default : display = 7'b1111111;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)2e9; const long long mod = 1000000007; int dx[] = {1, -1, 0, 0}, dy[] = {0, 0, 1, -1}; long long powmod(long long a, long long p) { long long ans = 1; a %= mod; while (p) { if (p & 1) ans *= a; p /= 2; a *= a; ans %= mod; a %= mod; } return ans; } long long mdinv(long long a) { return powmod(a, mod - 2); } const int N = 5e5 + 10; vector<int> adj[N]; vector<int> pre[N]; vector<int> suf[N]; int d[N]; vector<pair<int, int> > nb[N]; int f[2 * N]; void dfs1(int i, int p) { d[i] = 0; for (int v : adj[i]) { if (v != p) { dfs1(v, i), d[i] = max(d[i], 1 + d[v]); } } } void evaluate(vector<pair<int, int> >& v); void go(vector<pair<int, int> >& v, vector<pair<int, int> >& v2); void dfs2(int i, int p, int parDep) { vector<int>& pr = pre[i]; for (int v : adj[i]) { if (v != p) { pr.push_back(d[v] + 1); } else pr.push_back(parDep + 1); } vector<int> lst(pr); vector<int>& sf = suf[i]; sf = pr; for (int i = 1; i < (int)(pr.size()); i++) pr[i] = max(pr[i - 1], pr[i]); for (int i = (int)(pr.size()) - 2; i >= 0; i--) sf[i] = max(sf[i], sf[i + 1]); for (int first = 0; first < (int)(adj[i].size()); first++) { int v = adj[i][first]; if (v == p) continue; int mx = 0; if (first) mx = max(mx, pr[first - 1]); if (first + 1 < (int)(pr.size())) mx = max(mx, sf[first + 1]); dfs2(v, i, mx); } for (int first : lst) nb[i].push_back({first, 1}); vector<pair<int, int> >& v = nb[i]; sort((v).begin(), (v).end()); int ind = 0; for (int i = 1; i < (int)(v.size()); i++) { if (v[ind].first == v[i].first) { v[ind].second += v[i].second; } else { ind++; v[ind] = v[i]; } } v.resize(ind + 1); evaluate(nb[i]); for (int v : adj[i]) { if (v != p) { go(nb[i], nb[v]); } } } vector<pair<int, int> > tmp; void evaluate(vector<pair<int, int> >& v) { tmp = v; for (int i = (int)(tmp.size()) - 1; i >= 0; i--) { if (i != (int)(tmp.size()) - 1) tmp[i].second = tmp[i].second + tmp[i + 1].second; int dep = tmp[i].first; f[2 * dep] = max(f[2 * dep], tmp[i].second); int greater = tmp[i].second - v[i].second; f[2 * dep + 1] = max(f[2 * dep + 1], greater + 1); f[2 * dep - 1] = max(f[2 * dep - 1], tmp[i].second); } } void go(vector<pair<int, int> >& v1, vector<pair<int, int> >& v2) { tmp.clear(); for (auto i : v1) tmp.push_back(i); for (auto i : v2) tmp.push_back(i); sort((tmp).begin(), (tmp).end()); int ind = 0; for (int i = 1; i < (int)(tmp.size()); i++) { if (tmp[ind].first == tmp[i].first) { tmp[ind].second += tmp[i].second; } else { ind++; tmp[ind] = tmp[i]; } } tmp.resize(ind + 1); for (int i = (int)(tmp.size()) - 1; i >= 0; i--) { if (i != (int)(tmp.size()) - 1) tmp[i].second = tmp[i].second + tmp[i + 1].second; int dep = tmp[i].first; f[2 * dep] = max(f[2 * dep], tmp[i].second - 2); } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (int i = 0; i < (int)2 * N; i++) f[i] = 1; int n; cin >> n; int a, b; int mxd = 0; for (int i = 0; i < (int)n - 1; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } for (int i = 1; i <= n; i++) mxd = max(mxd, (int)(adj[i].size())); dfs1(1, 0); dfs2(1, 0, -1); for (int i = N - 3; i >= 0; i -= 2) f[i] = max(f[i], f[i + 2]); for (int i = N - 4; i >= 0; i -= 2) f[i] = max(f[i], f[i + 2]); f[1] = mxd + 1; for (int i = 1; i <= n; i++) cout << f[i] << ; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Tue Sep 16 21:34:47 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_0
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_0_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0_clk_wiz_0_clk_wiz
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.375000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(120.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(6),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; int main() { stack<int> q; string str; cin >> str; int open = 0, count = 0, rcount = 0; for (int i = 0; i < str.length(); ++i) { if (str[i] == ( ) open++; else if (str[i] == ) ) { if (open != 0) open--; else count--; } if (str[i] == # ) { count += open - 1; open = 0; rcount++; } if (count < 0) { cout << -1; return 0; } } if (open > 0) { cout << -1; return 0; } for (int i = 0; i < rcount - 1; i++) cout << 1 ; cout << count + 1; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKBUFLP_BEHAVIORAL_PP_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkbuflp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char arr[100][100]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> arr[i][j]; if (arr[i][j] == - ) { arr[i][j] = - ; } else { if (i % 2 == 0 && j % 2 == 0) { arr[i][j] = B ; } else if (i % 2 == 0 && j % 2 != 0) { arr[i][j] = W ; } else if (i % 2 != 0 && j % 2 == 0) { arr[i][j] = W ; } else if (i % 2 != 0 && j % 2 != 0) { arr[i][j] = B ; } } cout << arr[i][j]; } cout << endl; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:50:34 03/11/2015
// Design Name:
// Module Name: delay_line
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_line #(
parameter DELAY = 0,
parameter WIDTH = 8
)(
input ce,
input rst,
input clk,
input [WIDTH - 1:0] in,
output [WIDTH - 1:0] out
);
wire [WIDTH - 1:0] chain [DELAY:0];
assign chain[0] = in;
assign out = chain[DELAY];
generate
genvar i;
for(i = 0; i < DELAY; i = i + 1)
latch #(
.WIDTH(WIDTH)
)
lat (
.ce(ce),
.rst(rst),
.clk(clk),
.in(chain[i]),
.out(chain[i + 1])
);
endgenerate
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module Altera_UP_Audio_Bit_Counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [4:0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long mint = 0x7fffffff; const long long linf = 1000000000000000000LL; const long long mod = 1000000007LL; const double eps = 1e-3; const int N = 1000020; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } long long qpow(long long a, long long b, long long m) { long long ans = 1; while (b > 0) { if (b & 1) { ans = ans * a % m; } a = a * a % m; b >>= 1; } return ans; } int main(void) { for (int _ = read(); _ > 0; _--) { int n = read(); long long p = read(); vector<long long> k(n); long long b = 0; for (int i = 0; i < n; i++) k[i] = read(); sort(k.begin(), k.end(), greater<long long>()); long long q = 1; bool f = false; if (p == 1) { printf( %d n , n % 2 == 1 ? 1 : 0); continue; } long long now = k[0]; b = 1; int i = 1; for (; i < n; i++) { if (b == 0) now = k[i]; else while (now > k[i] && !f) { if (b >= n) { f = true; break; } b = b * p; now--; } if (f) { break; } else { if (b > 0) b--; else b++; } } long long ans = b % mod * qpow(p, now, mod) % mod; for (; i < n; i++) ans = (ans + (mod - 1) * qpow(p, k[i], mod) % mod) % mod; printf( %lld n , ans); } return 0; }
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//CLOCKS_PER_SEC using namespace std; #include<bits/stdc++.h> #define sqr(x) 1ll*(x)*(x) //#define sort stable_sort #define ll long long #define mk make_pair #define pb push_back #define in insert #define mtr(x,y,z) mk(mk(x,y),z) #define fi first #define se second #define lch(x) ((x)<<1) #define rch(x) (((x)<<1)|1) #define all(x) (x).begin(),(x).end() #define titose CLOCKS_PER_SEC #define fpi(x) freopen(x, r ,stdin); #define fpo(x) freopen(x, w ,stdout); #define fprio fpi( in.txt );fpo( out.txt ); #define fast ios_base::sync_with_stdio(false); inline void read(int &x){int v=0,f=1;char c=getchar();while (!isdigit(c)&&c!= - ) c=getchar();if (c== - ) f=-1; else v=(c&15);while (isdigit(c=getchar())) v=(v<<1)+(v<<3)+(c&15);x=v*f;} inline void read(ll &x){ll v=0ll,f=1ll;char c=getchar();while (!isdigit(c)&&c!= - ) c=getchar();if (c== - ) f=-1; else v=(c&15);while (isdigit(c=getchar())) v=(v<<1)+(v<<3)+(c&15);x=v*f;} inline void readc(char &x){char c;while (((c=getchar())== )||c== n );x=c;} #define pii pair<int,int> #define pll pair<ll,ll> #define vi vector<int> #define vl vector<ll> #define si set<int> //#define sl set<ll> #define mii map<int,int> #define mll map<ll,ll> #define msi map<string,int> #define msl map<string,ll> #define piii pair<int,pii > #define piipi pair<pii,int> #define plll pair<ll,pll > #define pllpl pair<pll,ll> #define pqi priority_queue<int> #define pql priority_queue<ll> #define npqi priority_queue<int,vector<int>,greater<int> > #define npql priority_queue<ll,vector<ll>,greater<ll> > #define forup(i,a,b) for ((i)=(a);(i)<=(b);(i)++) #define fordo(i,a,b) for ((i)=(a);(i)>=(b);(i)--) #define rep(i,x) forup ((i),1,(x)) #define repd(i,x) fordo ((i),(x),1) #define rep0(i,x) forup ((i),0,((int)(x))-1) #define rep0d(i,x) fordo ((i),((int)(x))-1,0) #define itr iterator #define fe(itcalc,c) for(__typeof((c).begin()) itcalc=(c).begin();itcalc!=(c).end();itcalc++) #define NO {cout<< NO ;return 0;} #define YES {cout<< YES ;return 0;} #define y0 y000000000000000000000000000 #define y1 y111111111111111111111111111 #define j0 j000000000000000000000000000 #define j1 j111111111111111111111111111 #define cl0(a) memset((a),(0),(sizeof((a)))) #define clz(a) memset((a),(0x16),(sizeof((a)))) #define clf(a) memset((a),(-(0x16)),(sizeof((a)))) #define inf 0x3bbbbbbb #define lnf 0x2bbbbbbbbbbbbbbbll //#define sqrt divi #define p2(i) (1ll<<(i)) #define readi read #define readll read /*************************************************/ int n,m,i,j,s=0,t=2001,px[1005],py[1005],dis[2005],inq[2005]; map<pair<int,int>,int> mp; struct edg { int y;ll z; }ee[1000005]; vector<int> e[2005];int tot; ll sum; void add(int x,int y,ll z) { // cerr<<x<< <<y<< <<z<<endl; tot++; e[x].pb(tot+tot-2);e[y].pb(tot+tot-1); ee[tot+tot-2]=(edg){y,z};ee[tot+tot-1]=(edg){x,0}; } bool bfs(int s,int t) { queue<int> qx;qx.push(s); clz(dis);dis[s]=0; while(!qx.empty()){ int x=qx.front();qx.pop();inq[x]=0; fe(it,e[x])if(ee[*it].z){ if(dis[ee[*it].y]>dis[x]+1){ dis[ee[*it].y]=dis[x]+1; if(!inq[ee[*it].y]){ qx.push(ee[*it].y); inq[ee[*it].y]=1; } } } } return dis[t]<dis[t+1]; } ll dfs(int x,int tt,ll flw) { if(x==tt||flw==0)return flw; ll res=0; fe(it,e[x])if(ee[*it].z&&dis[ee[*it].y]==dis[x]+1){ ll t=dfs(ee[*it].y,tt,min(ee[*it].z,flw)); res+=t;flw-=t;ee[*it].z-=t;ee[(*it)^1].z+=t; if(!flw)break; } if(flw) dis[x]=-1; return res; } ll dinic(int s,int t) { ll ans=0; while(bfs(s,t)){ ans+=dfs(s,t,lnf); } return ans; } int main() { read(n); rep(i,n){ int z;read(py[i]);read(px[i]);read(z); sum+=z; add(i,i+n,z);mp[mk(px[i],py[i])]=i; } rep(i,n){ int a=abs(px[i]&1),b=abs(py[i]&1); if(a==0){ if(b==1){ add(s,i,lnf); if(mp.count(mk(px[i],py[i]-1))){ add(i+n,mp[mk(px[i],py[i]-1)],lnf); } if(mp.count(mk(px[i],py[i]+1))){ add(i+n,mp[mk(px[i],py[i]+1)],lnf); } } else{ if(mp.count(mk(px[i]-1,py[i]))){ add(i+n,mp[mk(px[i]-1,py[i])],lnf); } if(mp.count(mk(px[i]+1,py[i]))){ add(i+n,mp[mk(px[i]+1,py[i])],lnf); } } } if(a==1){ if(b==0){ if(mp.count(mk(px[i],py[i]-1))){ add(i+n,mp[mk(px[i],py[i]-1)],lnf); } if(mp.count(mk(px[i],py[i]+1))){ add(i+n,mp[mk(px[i],py[i]+1)],lnf); } } else{ add(i+n,t,lnf); } } } cout<<sum-dinic(s,t)<<endl; return 0; }
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#include <iostream> #include <algorithm> using namespace std; int INF = 2e9; int pre[200001]; struct node{ int l, r, max, min; } segtree[800001]; void build(int ind, int l, int r){ if (l == r){ segtree[ind] = (node){l, r, pre[l], pre[l]}; } else { build(2*ind, l, (l+r)/2); build(2*ind+1, (l+r)/2+1, r); segtree[ind] = (node){l, r, max(segtree[2*ind].max, segtree[2*ind+1].max), min(segtree[2*ind].min, segtree[2*ind+1].min)}; } } int find_min(int ind, int l, int r){ if (segtree[ind].l >= l && segtree[ind].r <= r) return segtree[ind].min; if (segtree[ind].r < l || segtree[ind].l > r) return INF; return min(find_min(ind*2, l, r), find_min(ind*2+1,l,r)); } int find_max(int ind, int l, int r){ if (segtree[ind].l >= l && segtree[ind].r <= r) return segtree[ind].max; if (segtree[ind].r < l || segtree[ind].l > r) return -INF; return max(find_max(ind*2, l, r), find_max(ind*2+1,l,r)); } int main(){ int t; cin >> t; for (int i=0;i<t;i++){ int n,m; string s; cin >> n >> m; cin >> s; pre[0] = 0; for (int j=0;j<n;j++){ if (s[j] == + ) pre[j+1] = pre[j] + 1; else pre[j+1] = pre[j] - 1; } build(1, 0, n); for (int j=0;j<m;j++){ int l,r; cin >> l >> r; int M = find_max(1, 0, l-1), m = find_min(1, 0, l-1); //cout << M << << m << endl; int subsum = pre[r] - pre[l-1]; M = max(M, find_max(1, r+1, n) - subsum); m = min(m, find_min(1, r+1, n) - subsum); cout << M-m+1 << endl; } } }
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// VGA¿ØÖÆÄ£¿é ¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
module VGA_Control
(
input clk,
input rst,
input [7:0]snake,
input [7:0]apple_x,
input [7:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
);
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 7'b0000_000;
localparam HEAD = 7'b0000_001;
localparam BODY = 7'b0000_010;
localparam WALL = 7'b0000_011;
localparam HEAD_COLOR = 12'b0000_1111_0000;
localparam BODY_COLOR = 12'b0000_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or posedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin //¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; long long mod = 1000 * 1000 * 1000 + 7; struct suffix_array { vector<int> sa; vector<int> lcp; vector<vector<int>> st; vector<int> log2; vector<int> c; string str; int n; void sort_pairs(vector<pair<pair<int, int>, int>>& a) { vector<int> beg(n + 20); for (int i = 0; i < n; i++) { beg[a[i].first.second + 1]++; } for (int i = 0; i < beg.size() - 1; i++) { beg[i + 1] += beg[i]; } vector<pair<pair<int, int>, int>> sorted(n); for (int i = 0; i < n; i++) { sorted[beg[a[i].first.second]] = a[i]; beg[a[i].first.second]++; } beg.assign(beg.size(), 0); for (int i = 0; i < n; i++) { beg[sorted[i].first.first + 1]++; } for (int i = 0; i < beg.size() - 1; i++) { beg[i + 1] += beg[i]; } for (int i = 0; i < n; i++) { a[beg[sorted[i].first.first]] = sorted[i]; beg[sorted[i].first.first]++; } } suffix_array(string s) { s += $ ; n = s.length(); str = s; c.assign(n, 0); for (int i = 0; i < n; i++) { if (s[i] >= 0 && s[i] <= 9 ) { c[i] = (int)(s[i] - 0 + 1); } else { c[i] = 0; } } vector<pair<pair<int, int>, int>> pairs(n); for (int j = 0; (1 << (j - 1)) < n; j++) { for (int i = 0; i < n; i++) { pairs[i] = {{c[i], c[(i + (1 << j)) % n]}, i}; } sort_pairs(pairs); int cc = 0; c[pairs[0].second] = cc; for (int i = 1; i < n; i++) { if (pairs[i].first != pairs[i - 1].first) cc++; c[pairs[i].second] = cc; } } sa.assign(n, 0); for (int i = 0; i < n; i++) { sa[c[i]] = i; } lcp.assign(n, 0); int k = 0; for (int i = 0; i < n; i++) { int a = i; if (c[i] == n - 1) { k = 0; continue; } int b = sa[c[i] + 1]; if (k > 0) k--; while (max(a + k, b + k) < n && s[a + k] == s[b + k]) { k++; } lcp[c[i]] = k; } log2.assign(n + 1, 0); log2[1] = 0; for (int i = 2; i <= n; i++) { log2[i] = log2[i / 2] + 1; } st.assign(log2[n] + 1, vector<int>(n)); for (int i = 0; i < n; i++) { st[0][i] = lcp[i]; } for (int j = 1; j < st.size(); j++) { for (int i = 0; i + (1 << j) <= n; i++) { st[j][i] = min(st[j - 1][i], st[j - 1][i + (1 << (j - 1))]); } } } int compare(int i, int len_i, int j, int len_j) { if (i == j && len_i == len_j) return 0; int pos_i = i; int pos_j = j; i = c[i]; j = c[j]; if (i > j) swap(i, j); j--; int l = log2[j - i + 1]; int lcp_ans = min(st[l][i], st[l][j - (1 << l) + 1]); int len = min(len_i, len_j); lcp_ans = min(lcp_ans, len); if (lcp_ans == len) { if (len_i == len_j) { return 0; } else if (len_i > len_j) { return 1; } else { return -1; } } else if (str[pos_i + lcp_ans] > str[pos_j + lcp_ans]) { return 1; } else { return -1; } } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; string s; cin >> s; suffix_array sa(s); vector<vector<int>> dp(n + 1, vector<int>(n + 1)); vector<vector<int>> sums(n + 1, vector<int>(n + 1)); dp[0][0] = 1; dp[1][1] = 1; sums[0].assign(n + 1, 1); for (int i = 1; i <= n; i++) { sums[1][i] = 1; } for (int i = 2; i <= n; i++) { for (int j = 1; j <= i; j++) { if (s[i - j] == 0 ) { dp[i][j] = 0; sums[i][j] = sums[i][j - 1]; continue; } if (j <= i - j && sa.compare(i - j, j, i - j - j, j) > 0) { dp[i][j] += dp[i - j][j]; dp[i][j] %= mod; } dp[i][j] += sums[i - j][j - 1]; dp[i][j] %= mod; } for (int j = 1; j <= n; j++) { sums[i][j] = sums[i][j - 1] + dp[i][j]; sums[i][j] %= mod; } } long long ans = 0; for (int i = 0; i <= n; i++) { ans += dp[n][i]; ans %= mod; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int n; vector<pair<long long, long long> > a; set<int> extr; set<int>::iterator it; vector<int> e; int f[300005]; long long mnx = 999999999999999999, mny = 999999999999999999, mxx = -999999999999999999, mxy = -999999999999999999; int main() { cin >> n; a.reserve(n); for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; a.push_back({x, y}); } long long m = 0; for (int i = 0; i < n; i++) { if (a[i].first <= a[m].first) { m = i; mnx = a[m].first; } } extr.insert(m); f[m] = 1; m = 0; for (int i = 0; i < n; i++) { if (a[i].second <= a[m].second) { m = i; mny = a[m].second; } } extr.insert(m); f[m] = 1; m = 0; for (int i = 0; i < n; i++) { if (a[i].first >= a[m].first) { m = i; mxx = a[m].first; } } extr.insert(m); f[m] = 1; m = 0; for (int i = 0; i < n; i++) { if (a[i].second >= a[m].second) { m = i; mxy = a[m].second; } } extr.insert(m); f[m] = 1; for (it = extr.begin(); it != extr.end(); it++) { e.push_back(*it); } long long p = -999999999999999999; for (int i = 0; i < e.size(); i++) { for (int j = i + 1; j < e.size(); j++) { for (int k = 0; k < n; k++) { if (k == e[i] || k == e[j]) continue; long long minx = min(a[e[i]].first, min(a[e[j]].first, a[k].first)); long long maxx = max(a[e[i]].first, max(a[e[j]].first, a[k].first)); long long miny = min(a[e[i]].second, min(a[e[j]].second, a[k].second)); long long maxy = max(a[e[i]].second, max(a[e[j]].second, a[k].second)); if (p < ((maxx - minx) + (maxy - miny)) * 2) { p = ((maxx - minx) + (maxy - miny)) * 2; } } } } cout << p << ; for (int i = 0; i < n - 3; i++) cout << ((mxx - mnx) + (mxy - mny)) * 2 << ; }
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