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#include <bits/stdc++.h> using namespace std; int father[18000010], nRow, nCol; bool col[3010][3010 * 2]; int movex[] = {1, 1, 1, 0, 0, -1, -1, -1}; int movey[] = {-1, 0, 1, 1, -1, -1, 0, 1}; int Find(int p, int *father) { if (father[p] != p) father[p] = Find(father[p], father); return father[p]; } void read() { scanf( %d %d , &nRow, &nCol); nCol *= 2; for (int i = 1; i <= nRow * nCol; ++i) father[i] = i; } bool check(int x1, int y1, int x2, int y2) { static int fa[18000010], e[3010][2]; col[x1][y1] = col[x2][y2] = 1; int tot = 0; int pa = Find((x1 - 1) * nCol + y1, father), pb = Find((x2 - 1) * nCol + y2, father); fa[Find(pa, father)] = father[pa], fa[Find(pb, father)] = father[pb]; for (int j = 0, x, y; j < 8; ++j) { x = x1 + movex[j], y = y1 + movey[j]; if (y == 0) y = nCol; if (y == nCol + 1) y = 1; if (x >= 1 && x <= nRow && y >= 1 && y <= nCol && col[x][y]) { int p = Find((x - 1) * nCol + y, father); fa[p] = p, ++tot, e[tot][0] = p, e[tot][1] = pa; } x = x2 + movex[j], y = y2 + movey[j]; if (y == 0) y = nCol; if (y == nCol + 1) y = 1; if (x >= 1 && x <= nRow && y >= 1 && y <= nCol && col[x][y]) { int p = Find((x - 1) * nCol + y, father); fa[p] = p, ++tot, e[tot][0] = p, e[tot][1] = pb; } } for (int i = 1; i <= tot; ++i) fa[Find(e[i][0], fa)] = Find(e[i][1], fa); col[x1][y1] = col[x2][y2] = 0; return Find(pa, fa) != Find(pb, fa); } void print() { for (int i = 1; i <= nRow; ++i, printf( n )) for (int j = 1; j <= nCol / 2; ++j) printf( %d , col[i][j]); printf( n ); } void work(int a, int b) { int pa = Find((a - 1) * nCol + b, father); for (int j = 0; j < 8; ++j) { int x = a + movex[j], y = b + movey[j]; if (x < 1 || x > nRow) continue; if (y == 0) y = nCol; if (y == nCol + 1) y = 1; if (x >= 1 && x <= nRow && y >= 1 && y <= nCol && col[x][y]) father[Find((x - 1) * nCol + y, father)] = Find(pa, father); } } void Query() { int cnt = 0, m; scanf( %d , &m); for (int i = 1, a, b; i <= m; ++i) { scanf( %d %d , &a, &b); if (check(a, b, a, b + nCol / 2)) col[a][b] = 1, col[a][b + nCol / 2] = 1, ++cnt, work(a, b), work(a, b + nCol / 2); } printf( %d n , cnt); } int main() { read(); Query(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long INF = 1e12; vector<long long> ans[200010]; signed main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) ans[i].push_back(-1); ans[0][0] = a[0]; long long sz = 1; for (long long i = 1; i < n; i++) { long long l = -1, r = sz; while (r - l > 1) { long long mid = (l + r) / 2; long long tmp = ans[mid][ans[mid].size() - 1]; if (tmp > a[i]) { l = mid; } else { r = mid; } } if (r == sz) { ans[r][0] = a[i]; sz++; } else { ans[r].push_back(a[i]); } } for (long long i = 0; i < sz; i++) { for (long long ii = 0; ii < ans[i].size(); ii++) { if (ii) cout << ; cout << ans[i][ii]; } cout << endl; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:45:15 04/19/2015
// Design Name:
// Module Name: exponent_finder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module exponent_finder(
input clk,
input [63:0] boundary,
input input_enable,
input [8:0] base,
output reg [7:0] exponent,
output reg ready
);
reg [7:0] next_exponent;
reg next_ready;
reg [10:0] temp_product;
reg [10:0] next_temp_product;
initial begin
next_ready = 0;
next_exponent = 0;
next_temp_product = 1;
end
always @(posedge clk) begin
ready <= next_ready;
exponent <= next_exponent;
temp_product <= next_temp_product;
end
always @(*) begin
if (input_enable) begin
if (temp_product < boundary) begin
next_temp_product = temp_product * base;
next_ready = 0;
next_exponent = exponent + 1;
end else begin
next_temp_product = temp_product;
next_ready = 1;
next_exponent = exponent;
end
end else begin
if (ready) begin
next_ready = 1;
next_exponent = exponent;
next_temp_product = 1;
end else begin
next_temp_product = 1;
next_ready = 0;
next_exponent = 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long x, sum; while (~scanf( %lld , &x)) { if (x < 0) x = -x; if (x == 2) printf( 3 n ); else if (x == 0) printf( 0 n ); else { for (long long i = 1; i <= x; i++) { sum = i * (i + 1) / 2; if (sum == x || (sum > x && ((sum - x) % 2 == 0))) { printf( %d n , i); break; } } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n; cin >> n; int A[12]; int B[12]; for (int i = 0; i < 10; i++) A[i] = true; for (int i = 0; i < 10; i++) B[i] = false; for (int i = 0; i < n; i++) { char x; int c; cin >> x >> c; for (int j = 0; j < 10; j++) { if (x == & ) { A[j] &= (c % 2); B[j] &= (c % 2); } if (x == | ) { A[j] |= (c % 2); B[j] |= (c % 2); } if (x == ^ ) { A[j] ^= (c % 2); B[j] ^= (c % 2); } c /= 2; } } int AAA = 0; int BBB = 0; for (int i = 0; i < 10; i++) { int a_ = 0, b_ = 0; for (int a = 0; a < 2; a++) { for (int b = 0; b < 2; b++) { int AA = (((true | a) ^ b)); int BB = (((false | a) ^ b)); if (AA == A[i] && BB == B[i]) { a_ = a; b_ = b; } } } AAA += a_ * (1ll << i); BBB += b_ * (1ll << i); } cout << 2 << n ; cout << | << AAA << n ; cout << ^ << BBB << n ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1010, M = 200200; int i, j, k, n, m, ch, now, q; int a[N][N], ans[M]; struct cc { int x, y; } A[M]; struct dd { int l, r, s, t, q; } Q[M]; void R(int &x) { x = 0; ch = getchar(); while (ch < 0 || 9 < ch) ch = getchar(); while ( 0 <= ch && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); } bool cmp(const dd &a, const dd &b) { return a.r < b.r; } void work() { now++; int x = A[now].x, y = A[now].y; a[x][y] = a[y][x] = now; for (int i = 1; i <= n; i++) a[x][i] = a[y][i] = max(a[x][i], a[y][i]); } int main() { R(n); R(m); R(q); for (i = 1; i <= m; i++) R(A[i].x), R(A[i].y); for (i = 1; i <= q; i++) { R(Q[i].l); R(Q[i].r); R(Q[i].s); R(Q[i].t); Q[i].q = i; } sort(Q + 1, Q + q + 1, cmp); now = 0; for (i = 1; i <= q; i++) { while (now < Q[i].r) work(); if (a[Q[i].t][Q[i].s] >= Q[i].l) ans[Q[i].q] = 1; } for (i = 1; i <= q; i++) { if (ans[i]) puts( Yes ); else puts( No ); } }
|
`timescale 1ns / 1ps
// @input
// clk_src: clock source
// switch_power: electric power
// switch_en: pause switch
// sum_count: time limit
// count_start_flag: start signal
// @output
// count_end_flag: end signal
// count: counting of timer
module timer
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
( input [31:0]clk_src,
input switch_power,
input switch_en,
input [(WIDTH-1):0]sum_count,
input count_start_flag,
output reg count_end_flag,
output [(WIDTH-1):0] count
);
reg init_flag;
wire real_clk;
wire [(WIDTH-1):0] sum_count_mode;
reg [(WIDTH-1):0] count_mode;
reg [(WIDTH-1):0] reverse_count;
// if change TIME_SCORE, you can change simulate time step
assign sum_count_mode = sum_count * TIME_SCORE;
assign count = count_mode / TIME_SCORE;
initial begin
count_end_flag <= 0;
init_flag <= 1;
reverse_count <= 0;
count_mode <= 0;
end
//information: count has a second delay
assign real_clk = (switch_power & count_start_flag & !init_flag) ? clk_src[CLK_CH] : clk_src[0];
always @(posedge real_clk) begin
if (switch_power & count_start_flag) begin
if(init_flag) begin
reverse_count = 0;
count_mode = sum_count_mode;
// when fisrt enter this module, start to initiate
init_flag = 0;
end else if (switch_en) begin
//add time score
if (sum_count_mode >= reverse_count) begin
count_mode = sum_count_mode - reverse_count;
reverse_count = reverse_count + 1;
end else begin
count_end_flag = 1;
end
end
end else begin
count_end_flag <= 0;
reverse_count <= 0;
count_mode <= 0;
// when leave this module, reset init_flag to 1,
// making next time enter this module, all var of this module can be reset
init_flag <= 1;
end
end
endmodule
|
#include <bits/stdc++.h> const int N = 50005; char s[N]; int main() { scanf( %s , s); int i, j, n = strlen(s); for (j = 1; j <= n / 2; j++) { int t = 0, cnt = 0; for (i = 0; i + j < n; i++) { s[t++] = s[i]; if (s[i] == s[i + j]) cnt++; else cnt = 0; if (cnt == j) { t -= j; cnt = 0; } } for (; i < n; i++) s[t++] = s[i]; n = t; } s[n] = 0; puts(s); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module ad_pnmon (
// adc interface
adc_clk,
adc_valid_in,
adc_data_in,
adc_data_pn,
// pn out of sync and error
adc_pn_oos,
adc_pn_err);
// parameters
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adc interface
input adc_clk;
input adc_valid_in;
input [DW:0] adc_data_in;
input [DW:0] adc_data_pn;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg adc_valid_d = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg adc_pn_oos = 'd0;
reg [ 3:0] adc_pn_oos_count = 'd0;
// internal signals
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// make sure data is not 0, sequence will fail.
assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn oos and counters (16 to clear and set).
always @(posedge adc_clk) begin
adc_valid_d <= adc_valid_in;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
adc_pn_oos <= ~adc_pn_oos;
end
if (adc_pn_update_s == 1'b1) begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
end else begin
adc_pn_oos_count <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type1_block1
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type1_block1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En28
output signed [17:0] Out1; // sfix18_En10
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10
// <S46>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type1_block1
|
#include <bits/stdc++.h> using namespace std; long long q, x, y; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> q; while (q--) { cin >> x >> y; if (x - y > 1) cout << YES << n ; else cout << NO << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct compare { bool operator()(const pair<int, int>& a, const pair<int, int>& b) { return true; } }; int main() { cin.tie(0); ios_base::sync_with_stdio(0); int t; cin >> t; while (t--) { int n, x, y; cin >> n >> x >> y; vector<int> ans; for (int i = 1; i <= 50; i++) { ans.clear(); if ((x - y) % i != 0) continue; for (int j = x; j <= y; j += i) ans.push_back(j); if (ans.back() != y || ans.size() > n) continue; int j = x - i; while (ans.size() < n && j >= 1) { ans.push_back(j); j -= i; } j = y + i; while (ans.size() < n) { ans.push_back(j); j += i; } break; } for (auto ai : ans) cout << ai << ; cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_TB_V
`define SKY130_FD_SC_LP__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_TB_V
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; ll a[200009],n,p; bool vis[200009][2]; pair <ll,ll> g[200009]; int main() { ios::sync_with_stdio(0); int t; cin>>t; while(t--) { cin>>n>>p; ll ans=0; for(int i=1;i<=n;i++) { cin>>a[i]; vis[i][0]=vis[i][1]=0; g[i]=make_pair(a[i],i); } vis[1][0]=vis[n][1]=1; sort(g+1,g+n+1); for(int i=1;i<=n;i++) { int w=g[i].second; if(a[w]>p)break; int l,r; l=r=w; while(!vis[l][0]&&(a[l-1]%a[w]==0))l--; while(!vis[r][1]&&(a[r+1]%a[w]==0))r++; ans+=(r-l)*a[w]; if(l!=r){vis[l][1]=vis[r][0]=1;} for(int h=l+1;h<r;h++)vis[h][0]=vis[h][1]=1; } for(int i=1;i<=n;i++)if(!vis[i][1])ans+=p; cout<<ans<<endl; } return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
SB_CARRY carry (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.CO(CO[i])
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(AA[i]),
.I2(BB[i]),
.I3(C[i]),
.O(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule
|
`timescale 1ns / 1ps
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
module mmc3_eth_core(
input wire RESET_N,
// clocks from PLL clock buffers
input wire BUS_CLK, CLK125TX, CLK125TX90, CLK125RX,
input wire PLL_LOCKED,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS,
input wire fifo_empty,
input wire fifo_full,
input wire FIFO_NEXT,
output wire FIFO_WRITE,
output wire [31:0] FIFO_DATA,
output wire [7:0] GPIO
);
/* ------- MODULE ADREESSES ------- */
localparam GPIO_BASEADDR = 32'h1000;
localparam GPIO_HIGHADDR = 32'h101f;
/* ------- USER MODULES ------- */
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO)
);
reg [31:0] datasource;
reg fifo_write;
assign FIFO_WRITE = fifo_write;
reg [31:0] fifo_data_out;
assign FIFO_DATA = fifo_data_out;
/* ------- Main FSM ------- */
always@ (posedge BUS_CLK)
begin
// FIFO handshake
if(FIFO_NEXT) begin
if(!fifo_full) begin
fifo_data_out <= datasource;
datasource <= datasource + 1;
fifo_write <= 1'b1;
end
else
fifo_write <= 1'b0;
end
else begin
datasource <= 'd0;
fifo_write <= 1'b0;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v1_9_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk,
output sys_clk_o
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
// IBUFG #
// (
// .IBUF_LOW_PWR ("FALSE")
// )
// u_ibufg_sys_clk_o
// (
// .I (sys_clk_i),
// .O (sys_clk_o)
// );
assign sys_clk_o = sys_clk_i;
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
assign sys_clk_o = sys_clk_ibufg;
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
assign sys_clk_o = sys_clk_ibufg;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct keycompare { bool operator()(const pair<long long, long long>& v, const long long& k) { return (v.first < k); } bool operator()(const long long& k, const pair<long long, long long>& v) { return (k < v.first); } }; long long mod1 = 998244353, mod2 = 1000000007, limit = 9223372036854775807; long double pi = 3.1415926535897932; long long modpow(long long x, long long n, long long m) { if (x > m) { x %= m; } if (n == 0) return 1 % m; long long u = modpow(x, n / 2, m); u = (u * u) % m; if (n % 2 == 1) u = (u * x) % m; return u; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } bool isprime(long long n) { if (n == 2) return true; for (long long i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } long long power(long long x, long long n) { long long x_n = 1; for (long long i = 0; i < n; i++) { x_n *= x; } return x_n; } long double arr[100005]; int n; long double l; long double time1(long double mid) { long double last = 1; long double timer = 0; for (int i = 1; i <= n + 1; i++) { if (arr[i] < mid) { timer += (arr[i] - arr[i - 1]) / last; } else { timer += (mid - arr[i - 1]) / last; break; } last++; } return timer; } long double time2(long double mid) { long double last = 1; long double timer = 0; for (int i = n; i >= 0; i--) { if (arr[i] > mid) { timer += (arr[i + 1] - arr[i]) / last; } else { timer += (arr[i + 1] - mid) / last; break; } last++; } return timer; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { cin >> n >> l; arr[0] = 0; arr[n + 1] = l; for (int i = 1; i <= n; i++) { cin >> arr[i]; } long double left = 0, right = l; while (abs(left - right) > 1e-9) { long double mid = (left + right) / 2; if (time1(mid) < time2(mid)) { left = mid; } else { right = mid; } } cout << setprecision(15) << time1(left) << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_TB_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_nsr.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hd__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
|
// file: design_1_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
// CLK_OUT2____50.000______0.000______50.0______151.636_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________100____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_1_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_1_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_1_0;
wire clkfbout_buf_design_1_clk_wiz_1_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (20),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_1_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_design_1_clk_wiz_1_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_design_1_clk_wiz_1_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_1_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_1_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_1_0),
.I (clkfbout_design_1_clk_wiz_1_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_1_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_design_1_clk_wiz_1_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; if (t % 2 == 0) { cout << Mahmoud << endl; } else { cout << Ehab << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_nr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > al, dist; int n, m; bool done[5000]; vector<int> bfs(const vector<vector<int> >& al, int s) { queue<int> q; vector<int> dist(al.size(), INT_MAX); dist[s] = 0; q.push(s); while (!q.empty()) { int i = q.front(); q.pop(); for (int j : al[i]) if (dist[j] == INT_MAX) { dist[j] = dist[i] + 1; q.push(j); } } return dist; } int main() { ios::sync_with_stdio(0); cin >> n >> m; int r = n; al.resize(n); dist.resize(n); int i, j; for (int c = 0; c < m; c++) { cin >> i >> j; i--; j--; al[i].push_back(j); } for (int s = 0; s < n; s++) dist[s] = bfs(al, s); for (int i = 0; i < n; i++) if (!done[i]) { vector<int> comp{i}; done[i] = 1; bool outgo = 0; for (int j = 0; j < n; j++) if (dist[i][j] != INT_MAX && i != j) { if (dist[j][i] != INT_MAX) { comp.push_back(j); done[j] = 1; } else outgo = 1; } if (!outgo && comp.size() > 1) { int m = INT_MAX; for (int c = 0; c < comp.size(); c++) for (int d = 0; d < comp.size(); d++) if (c != d) m = min(m, dist[comp[c]][comp[d]] + dist[comp[d]][comp[c]]); r += 998 * m + 1; } } cout << r << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_16_V
`define SKY130_FD_SC_LP__CLKINVLP_16_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_16_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll M = 1000000007; const ll M1 = 998244353; using vl = vector<ll>; using pll = pair<ll, ll>; ll power(ll x, ll y) { if (y == 0) return 1; ll res = power(x, y / 2); res = (res * res); if (y & 1) res = (res * x); return res; } ll powermod(ll x, ll y, ll mod) { if (y == 0) return 1; ll res = powermod(x, y / 2, mod); res = (res * res) % mod; if (y & 1) res = (res * x) % mod; return res; } ll findxor(ll a) { switch (a & 3) { case 0: return a; case 1: return 1; case 2: return a + 1; case 3: return 0; } return -1; } int n; vector<int> visi; vector<string> gr; void dfs(int node, vector<int> &rec_visit) { visi[node] = 1; rec_visit.push_back(node); for (int con_node = 0; con_node < n; con_node++) { if (visi[con_node] || gr[node][con_node] == 0 ) continue; dfs(con_node, rec_visit); } } void solve() { cin >> n; int ans[n]; for (int i = 0; i < n; i++) cin >> ans[i]; gr.resize(n); visi.resize(n, 0); for (int i = 0; i < n; i++) cin >> gr[i]; for (int i = 0; i < n; i++) { if (visi[i]) continue; vector<int> rec_visit; dfs(i, rec_visit); vector<int> val; for (int j = 0; j < rec_visit.size(); j++) val.push_back(ans[rec_visit[j]]); sort(val.begin(), val.end()); sort(rec_visit.begin(), rec_visit.end()); for (int j = 0; j < rec_visit.size(); j++) ans[rec_visit[j]] = val[j]; } for (int i = 0; i < n; i++) cout << ans[i] << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
`include "constants.vh"
module ram_sync_2r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_2r1w
module ram_sync_2r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_2r2w
module ram_sync_4r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule // ram_sync_4r1w
module ram_sync_4r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_4r2w
module ram_sync_6r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
input [BRAM_ADDR_WIDTH-1:0] raddr5,
input [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_6r2w
|
//Jan.7.2005 Register File on Xilinx
// using two dual port ram
module ram32x32_xilinx (
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb);
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
input [4:0] rdaddress_b;
input wren;
input clock;
output [31:0] qa;
output [31:0] qb;
ram32x32 ram1(//write port /read porta
.addra(wraddress),
.addrb(rdaddress_a),
.clka(clock),
.clkb(clock),
.dina(data),
.dinb(32'h0000_0000),
.douta(),
.doutb(qa),
.wea(wren),
.web(1'b0)); // synthesis black_box
ram32x32 ram2(//write port /read portb
.addra(wraddress),
.addrb(rdaddress_b),
.clka(clock),
.clkb(clock),
.dina(data),
.dinb(32'h0000_0000),
.douta(),
.doutb(qb),
.wea(wren),
.web(1'b0)); // synthesis black_box
/* There is no specific 3port RAM on Xilinx.
Following description is unavailable because of too many Slices required. Jan.7.2005
.
reg [31:0] regfile [0:31];
reg [4:0] addr_a,addr_b,w_addr;
reg [31:0] data_port;
integer i;
always @(posedge clock) begin
addr_a<=rdaddress_a;
addr_b<=rdaddress_b;
end
always @ (posedge clock) begin
if (sync_reset) for (i=0;i<32;i=i+1) regfile[i]<=0;
else if (wren) regfile[wraddress] <=data;
end
assign qa=regfile[addr_a];
assign qb=regfile[addr_b];
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_SYMBOL_V
`define SKY130_FD_SC_HVL__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_SYMBOL_V
|
module test();
// function with no lifetime, return-type, or port-list
function f0;
blah0;
endfunction
// empty port-list
function f1();
blah1;
endfunction
// non-empty portlist
function f2(stuff2);
blah2;
endfunction
// test that ": function_identifier" remains unscathed
function f3;
endfunction : f3
// return type
function void f4;
blah4;
endfunction
// return type with empty port-list.
function void f5();
int i;
begin
blah4;
end
endfunction
// return type, non-empty portlist
// also check that a stale auto-comment gets removed
function void f6(stuff,
that,
spans,
lines);
blah5;
endfunction // fX
// test lifetime keywords 'automatic' and 'static'
function automatic f7();
endfunction
// test a crazy-long function declaration
function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
endfunction
// port-list that doesn't start on the same line as the function declaration
function automatic void f9
(int a,
int b);
endfunction
// mismatched keyword
function f10;
endtask
// make sure previous screw-up doesn't affect future functions
function f11;
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 20; int pos[maxn]; int n, m; long long k, ans[maxn]; int val[maxn]; struct query { int l, r, id; } Q[maxn]; long long now = 0; long long M[maxn]; bool cmp(query a, query b) { if (pos[a.l] == pos[b.l]) return a.r < b.r; return pos[a.l] < pos[b.l]; } void add(int x) { now += M[val[x] ^ k]; M[val[x]]++; } void del(int x) { M[val[x]]--; now -= M[val[x] ^ k]; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) { long long temp; scanf( %I64d , &temp); val[i] = val[i - 1] ^ temp; } int block = sqrt(n); for (int i = 1; i <= n; i++) pos[i] = i / block; for (int i = 1; i <= m; i++) { scanf( %d%d , &Q[i].l, &Q[i].r); Q[i].id = i; } sort(Q + 1, Q + m + 1, cmp); M[0] = 1; for (int i = 1, L = 1, R = 0; i <= m; i++) { for (; R < Q[i].r; R++) add(R + 1); for (; R > Q[i].r; R--) del(R); for (; L < Q[i].l; L++) del(L - 1); for (; L > Q[i].l; L--) add(L - 2); ans[Q[i].id] = now; } for (int i = 1; i <= m; i++) printf( %I64d n , ans[i]); }
|
module tenv_usb_decoder #(parameter PACKET_MAXSIZE=64);
//IFACE
wire dplus;
wire dminus;
reg start=0;
integer mode=0;
localparam MODE_PACKET=0,
MODE_NOREPLY=1,
MODE_WAKEUP=2;
reg speed=1;
reg[7:0] pid=0;
reg[(PACKET_MAXSIZE*8)+15:0] data=0;
integer pack_size=0;
integer bit_time=10;
localparam PIDOUT=8'b1110_0001;
localparam PIDIN=8'b0110_1001;
localparam PIDSOF=8'b1010_0101;
localparam PIDSETUP=8'b0010_110;
localparam PIDDATA0=8'b1100_0011;
localparam PIDDATA1=8'b0100_1011;
localparam PIDACK=8'b1101_0010;
localparam PIDNAK=8'b0101_1010;
localparam PIDSTALL=8'b0001_1110;
localparam PIDPRE=8'b0011_1100;
//LOCAL
localparam block_name="tenv_usb_decoder";
integer loop;
reg[15:0] crc;
reg[7:0] sync=8'b10000000;
reg dplus_prev=1;
integer count_ones=0;
integer i=0,j=0;
initial forever
begin
wait(start);
//CHECK IDLE
if(dplus!==speed | dplus!==~dminus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid bus idle state.");
$finish;
end
dplus_prev= dplus;
if(mode==MODE_PACKET)
fork
//INTERPACKET DELAY: required < 6.5 BIT TIME
// checked < 4 BIT TIME
begin:TIMEOUT
j=0;
while(dplus_prev==dplus)
begin
#bit_time;
j=j+1;
if(j==4)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - timeout.");
$finish;
end
end
end
begin:DECODE
wait(dplus!==dplus_prev);
disable TIMEOUT;
//SYNC
#(bit_time/4);
i=0;
repeat(8)
begin
if(dplus!==~dminus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid diff lines state.");
$finish;
end
if((dplus==dplus_prev?1'b1:1'b0)!==sync[i])
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid SYNC.");
$finish;
end
i=i+1;
dplus_prev= dplus;
#bit_time;
end
//PID
i=0;
count_ones=1;
while((dplus!==0 | dminus!==0) & i!= 8)
begin
pid[i]= dplus_prev==dplus ? 1'b1 : 1'b0;
i= i+1;
if(dplus_prev==dplus)
count_ones= count_ones+1;
else
count_ones= 0;
if(dplus!==~dminus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid diff lines state.");
$finish;
end
dplus_prev=dplus;
#bit_time;
end
if(pid[3:0]!==~pid[7:4])
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid PID.");
$finish;
end
//DATA
i=0;
while((dplus!==0 | dminus!==0))
begin
if(count_ones!==6)
begin
data[i]= dplus_prev==dplus ? 1'b1 : 1'b0;
i= i+1;
end
if(dplus_prev==dplus)
count_ones= count_ones+1;
else
count_ones= 0;
if(count_ones==7 & dplus_prev==dplus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid bit stuffing.");
$finish;
end
if(dplus!==~dminus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid diff lines state.");
$finish;
end
dplus_prev=dplus;
#bit_time;
end
//EOP
#bit_time;
if(dplus!==0 | dminus!==0)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid EOP SE0.");
$finish;
end
#bit_time;
if(dplus!==speed | dminus!==~speed)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid EOP IDLE.");
$finish;
end
#bit_time;
//CRC
crc=16'hffff;
if(pid==PIDDATA0 | pid==PIDDATA1)
begin
j=0;
while(j!=i)
begin
crc= (crc[15]^data[j]) ? {crc[14:0],1'b0}^16'h8005 :
{crc[14:0],1'b0};
j= j+1;
end
i= i-16;
if(crc!==16'h800D)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid CRC16.");
$finish;
end
end
else
if(pid==PIDSETUP | pid==PIDIN | pid==PIDOUT | pid==PIDSOF)
begin
j=0;
while(j!=i)
begin
crc[4:0]= (crc[4]^data[j]) ? {crc[3:0],1'b0}^5'b00101 :
{crc[3:0],1'b0};
j= j+1;
end
i= i-5;
if(crc!==5'b01100)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid CRC5.");
$finish;
end
end
//CHECK BYTES QUANTITY
if(i[2:0]!==0)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid quantity of bytes.");
$finish;
end
pack_size=i;
end
join
else if(mode==MODE_WAKEUP)
begin
//WAKEUP: required 1-15ms
// checked 1-5ms
j=0;
while({dplus,dminus}!=={~speed,speed})
begin
#bit_time;
j=j+1;
if(j==5)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - timeout.");
$finish;
end
end
j=0;
while({dplus,dminus}=={~speed,speed})
begin
#1000;
j=j+1;
if(j>=5000)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid wakeup.");
$finish;
end
end
if(j<1000)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - invalid wakeup.");
$finish;
end
end
else if(mode==MODE_NOREPLY)
begin
j=0;
while(dplus_prev==dplus & j!=18)
begin
#bit_time;
j=j+1;
end
if(dplus_prev!==dplus)
begin
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$display("Error - bus is active.");
$finish;
end
end
start=0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long maxn = 3e6; const long long mod = 1e9 + 7; const long double PI = acos((long double)-1); long long pw(long long a, long long b, long long md = mod) { long long res = 1; while (b) { if (b & 1) { res = (a * res) % md; } a = (a * a) % md; b >>= 1; } return (res); } string s[4]; bool hor(int x, int y) { if (x < 1 or x > 2) return (0); int cnt = 0; if (s[x][y] == o ) return (0); if (s[x][y] == . ) cnt++; if (s[x - 1][y] == o ) return (0); if (s[x - 1][y] == . ) cnt++; if (s[x + 1][y] == o ) return (0); if (s[x + 1][y] == . ) cnt++; return (cnt < 2); } bool ver(int x, int y) { if (y < 1 or y > 2) return (0); int cnt = 0; if (s[x][y] == o ) return (0); if (s[x][y] == . ) cnt++; if (s[x][y - 1] == o ) return (0); if (s[x][y - 1] == . ) cnt++; if (s[x][y + 1] == o ) return (0); if (s[x][y + 1] == . ) cnt++; return (cnt < 2); } bool dia(int x, int y) { int cnt = 0; if (x < 1 or x > 2) return (0); if (y < 1 or y > 2) return (0); if (s[x][y] == o ) return (0); if (s[x][y] == . ) cnt++; if (s[x - 1][y - 1] == o ) return (0); if (s[x - 1][y - 1] == . ) cnt++; if (s[x + 1][y + 1] == o ) return (0); if (s[x + 1][y + 1] == . ) cnt++; return (cnt < 2); } bool diag(int x, int y) { int cnt = 0; if (x < 1 or x > 2) return (0); if (y < 1 or y > 2) return (0); if (s[x][y] == o ) return (0); if (s[x][y] == . ) cnt++; if (s[x - 1][y + 1] == o ) return (0); if (s[x - 1][y + 1] == . ) cnt++; if (s[x + 1][y - 1] == o ) return (0); if (s[x + 1][y - 1] == . ) cnt++; return (cnt < 2); } bool chk(int x, int y) { if (ver(x, y)) return (1); if (hor(x, y)) return (1); if (dia(x, y)) return (1); if (diag(x, y)) return (1); return (0); } int32_t main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); for (int i = 0; i < 4; i++) cin >> s[i]; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) if (chk(i, j)) cout << YES , exit(0); cout << NO ; return (0); }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-10; const long long MOD = 1000000007ll; const long long mod1 = 1000000009ll; const long long mod2 = 1100000009ll; int INF = (int)1e9 + 5; long long INFINF = (long long)1e18; int main() { int n; scanf( %d , &n); int a, b, diff; diff = INF; a = -1; b = -1; for (int i = 1; i <= n; i++) { if (n % i == 0) { int a_t, b_t; a_t = i; b_t = n / i; if (abs(a_t - b_t) < diff) { diff = abs(a_t - b_t); a = min(a_t, b_t); b = max(a_t, b_t); } } } printf( %d , a); printf( %d n , b); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V
|
module add_5stage (
input ck,
input [63:0] i_a, i_b,
input [6:0] i_htId,
input i_vld,
output [63:0] o_res,
output [6:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t1_res;
wire [6:0] c_t1_htId;
wire c_t1_vld;
reg [63:0] r_t2_res, r_t3_res, r_t4_res, r_t5_res, r_t6_res;
reg [6:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_res <= c_t1_res;
r_t2_htId <= c_t1_htId;
r_t2_vld <= c_t1_vld;
r_t3_res <= r_t2_res;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t4_res <= r_t3_res;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t5_res <= r_t4_res;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t6_res <= r_t5_res;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
end
// Inputs
assign c_t1_res = i_a + i_b;
assign c_t1_htId = i_htId;
assign c_t1_vld = i_vld;
// Outputs
assign o_res = r_t6_res;
assign o_htId = r_t6_htId;
assign o_vld = r_t6_vld;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int add(int a, int b) { return (a + b) % MOD; } int sub(int a, int b) { return add(a, MOD - b); } int mul(int a, int b) { return ((long long)a * b) % MOD; } int inv(int a) { int b = 1; for (int i = 0; (1 << i) <= MOD - 2; i++) { if ((1 << i) & (MOD - 2)) b = mul(b, a); a = mul(a, a); } return b; } const int MAXN = 1e5 + 10; vector<int> e[MAXN]; int val[MAXN], sz[MAXN], parent[MAXN]; map<int, int> dist[MAXN]; int A[MAXN], B[MAXN], total; bool active[MAXN]; vector<int> in[MAXN], out[MAXN]; int calc_sz(int i, int p) { sz[i] = 1; for (int j : e[i]) { if (!active[j] || j == p) continue; sz[i] += calc_sz(j, i); } return sz[i]; } int find_centroid(int i, int p, int n) { for (int j : e[i]) { if (!active[j] || j == p) continue; if (sz[j] > n / 2) return find_centroid(j, i, n); } return i; } void calc_dist(int i, int p, int r, int d) { dist[i][r] = d; for (int j : e[i]) { if (!active[j] || j == p) continue; calc_dist(j, i, r, d + 1); } } int build_centroid(int i) { i = find_centroid(i, -1, calc_sz(i, -1)); calc_dist(i, -1, i, 0); active[i] = false; for (int j : e[i]) { if (!active[j]) continue; parent[build_centroid(j)] = i; } return i; } void update(int i, int k) { int v = mul(val[i], MOD + k); for (int p = i; p != -1; p = parent[p]) { total = sub(total, mul(A[p], B[p])); A[p] = add(A[p], mul(v, dist[i][p])); if (parent[p] != -1) A[p] = sub(A[p], mul(v, dist[i][parent[p]])); B[p] = add(B[p], v); total = add(total, mul(A[p], B[p])); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; int t = 1; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; in[l].push_back(i); out[r].push_back(i); val[i] = inv(r - l + 1); t = mul(t, r - l + 1); active[i] = true; } for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; x--; y--; e[x].push_back(y); e[y].push_back(x); } parent[build_centroid(0)] = -1; int sol = 0; for (int color = 0; color < MAXN; color++) { for (int i : in[color]) update(i, 1); sol = add(sol, total); for (int i : out[color]) update(i, -1); } cout << mul(sol, t); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_drv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// _____________________________________________________________________________
//
// bw_io_dtl_drv -- DTL Driver.
// _____________________________________________________________________________
//
module bw_io_dtl_drv (/*AUTOARG*/
// Outputs
pad,
// Inouts
vddo,
// Inputs
cbu, cbd, sel_data_n, pad_up, pad_dn_l, pad_dn25_l, por, bsr_up, bsr_dn_l,
bsr_dn25_l
);
output pad;
input [8:1] cbu;
input [8:1] cbd;
input sel_data_n;
input pad_up;
input pad_dn_l;
input pad_dn25_l;
input por;
input bsr_up;
input bsr_dn_l;
input bsr_dn25_l;
inout vddo;
reg /*4value*/ pad_reg;
always @(por or sel_data_n or pad_up or pad_dn_l or pad_dn25_l or bsr_up or bsr_dn_l or bsr_dn25_l) begin
casez ({por, sel_data_n, pad_up, pad_dn_l,pad_dn25_l, bsr_up, bsr_dn_l, bsr_dn25_l})
8'b1???????: pad_reg = 1'b1; // normal path (pad) reset
8'b00001???: pad_reg = 1'b0; // normal path (pad) write 0, 50 ohms
8'b00000???: pad_reg = 1'b0; // normal path (pad) write 0, 25 ohms
8'b00011???: pad_reg = 1'bz; // normal path (pad) hi-Z
8'b00111???: pad_reg = 1'b1; // normal path (pad) write 1
8'b01???001: pad_reg = 1'b0; // boundary scan (bsr) write 0, 50 ohms
8'b01???000: pad_reg = 1'b0; // boundary scan (bsr) write 0, 25 ohms
8'b01???011: pad_reg = 1'bz; // boundary scan (bsr) hi-Z
8'b01???111: pad_reg = 1'b1; // boundary scan (bsr) write 1
default: pad_reg = 1'bx; // all other cases illegal and not defined
endcase
end
assign (pull1, strong0) #1 pad = pad_reg;
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_hdmi_tx_alt (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// vdma interface
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
vdma_sop,
vdma_eop,
vdma_empty,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awid,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bid,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arid,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rid,
s_axi_rlast,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
input vdma_sop;
input vdma_eop;
input [ 3:0] vdma_empty;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
input [ 0:0] s_axi_awlock;
input [ 3:0] s_axi_awcache;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
input s_axi_wlast;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
input [ 0:0] s_axi_arlock;
input [ 3:0] s_axi_arcache;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
// internal signals
wire vdma_fsync;
// defaults
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
// hdmi tx lite version
axi_hdmi_tx #(
.PCORE_ID (PCORE_ID),
.PCORE_Cr_Cb_N (PCORE_Cr_Cb_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC))
i_hdmi_tx (
.hdmi_clk (hdmi_clk),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.m_axis_mm2s_clk (vdma_clk),
.m_axis_mm2s_fsync (vdma_fsync),
.m_axis_mm2s_fsync_ret (vdma_fsync),
.m_axis_mm2s_tvalid (vdma_valid),
.m_axis_mm2s_tdata (vdma_data),
.m_axis_mm2s_tkeep (8'hff),
.m_axis_mm2s_tlast (vdma_eop),
.m_axis_mm2s_tready (vdma_ready),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long int fast_expo(long long int x, long long int p) { if (p == 0) return 1; else if (p % 2 == 0) { long long int t = fast_expo(x, p / 2) % 1000000007; return (t * t) % 1000000007; } else return (x * (fast_expo(x, p - 1)) % 1000000007) % 1000000007; } long long int aft_bunk[501][501]; long long int dp[501][501]; vector<long long int> vect[501]; long long int solve(long long int day, long long int bunk) { if (day == -1 && bunk >= 0) return 0; if (day < 0 || bunk < 0) return INT_MAX; if (dp[day][bunk] != -1) return dp[day][bunk]; long long int ans = INT_MAX; for (long long int i = 0; i <= vect[day].size(); ++i) { long long int temp = solve(day - 1, bunk - i) + aft_bunk[day][i]; if (ans > temp) ans = temp; } return dp[day][bunk] = ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int n, m, k; cin >> n >> m >> k; char tempo; for (long long int i = 0; i < n; ++i) { for (long long int j = 1; j <= m; ++j) { cin >> tempo; if (tempo == 1 ) { vect[i].push_back(j); } } } for (long long int i = 0; i < n; ++i) { for (long long int j = 0; j < 501; ++j) { aft_bunk[i][j] = INT_MAX; } } long long int temp; for (long long int i = 0; i < n; ++i) { for (long long int j = 0; j < vect[i].size(); ++j) { long long int ptr1 = 0, ptr2 = vect[i].size() - 1 - j; for (long long int ptr1 = 0; ptr1 <= j; ptr1++, ptr2++) { temp = vect[i][ptr2] - vect[i][ptr1] + 1; if (temp < aft_bunk[i][j]) aft_bunk[i][j] = temp; } } aft_bunk[i][vect[i].size()] = 0; } for (long long int i = 0; i < 501; ++i) { for (long long int j = 0; j < 501; ++j) dp[i][j] = -1; } cout << solve(n - 1, k); return 0; }
|
#include <bits/stdc++.h> using namespace std; int z[100005], cnt[100005]; char s[100005]; void solve() { int n, t, L, R; n = strlen(s), L = R = 0; z[0] = n; for (int i = 1; i < n; i++) { if (R < i) { L = R = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L, R--; } else { t = i - L; if (z[t] + i - 1 < R) z[i] = z[t]; else { L = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L, R--; } } } int ret = 0; for (int i = (n)-1; i >= (0); i--) { if (z[i] + i >= n) ++ret; ++cnt[z[i]]; } for (int i = (n)-1; i >= (0); i--) cnt[i] += cnt[i + 1]; printf( %d n , ret); for (int i = (n)-1; i >= (0); i--) if (z[i] + i >= n) printf( %d %d n , n - i, cnt[n - i]); } int main() { scanf( %s , s); solve(); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of IO60DRV1
//
// Generated
// by: wig
// on: Wed Mar 7 06:35:27 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: io60drv1.v,v 1.1 2007/03/08 09:32:07 wig Exp $
// $Date: 2007/03/08 09:32:07 $
// $Log: io60drv1.v,v $
// Revision 1.1 2007/03/08 09:32:07 wig
// Import missing file ...
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./03/03 17:24:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of IO60DRV1
//
// No user `defines in this module
module IO60DRV1
//
// Generated Module pad_data9
//
(
pad // From TopLevel Boundary
);
// Generated Module In/Outputs:
inout pad;
// Generated Wires:
wire pad;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of IO60DRV1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int MOD = 1e9 + 7; const long long INF64 = 1e18; const long double EPS = 1e-7; mt19937 myrand(time(NULL)); const int N = 100 * 1000 + 13; int n, ac, d; pair<int, int> a[N]; long double t[N]; bool read() { if (scanf( %d%d%d , &n, &ac, &d) != 3) return 0; for (int i = 0; i < (n); i++) scanf( %d%d , &a[i].first, &a[i].second); return 1; } void solve() { for (int i = 0; i < (n); i++) { long double cur = a[i].second * 1.0 / ac; t[i] = a[i].first; if (cur * cur * ac / 2 > d - EPS) t[i] += sqrtl(d * 2.0 / ac); else t[i] += cur + (d - cur * cur * ac / 2) / a[i].second; if (i && t[i] < t[i - 1]) t[i] = t[i - 1]; printf( %.10f n , (double)t[i]); } } int main() { while (read()) solve(); return 0; }
|
//
// Copyright (c) 2015 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "rca110_defs.v"
module rca110_memory(i_clk, i_rst, mm_adr, mm_we, mm_idat, mm_odat);
input i_clk;
input i_rst;
input [11:0] mm_adr;
input mm_we;
output reg [23:0] mm_idat;
input [23:0] mm_odat;
reg [24:0] m_memory [4095:0];
integer i;
always @(posedge i_clk) begin
if(i_rst) begin
mm_idat <= 0;
for(i = 0; i < 4095; i = i + 1)
m_memory[i] = 0;
m_memory[64] = {9'b011010000, 3'b010, 12'b000000000010}; // STP
m_memory[65] = {9'o400, 15'h0};
m_memory[66] = {12'b0, 12'b100000000000};
end
else begin
if(mm_we)
m_memory[mm_adr] <= mm_odat;
else
mm_idat <= m_memory[mm_adr];
end
end
endmodule // rca110_memory
module rca110(i_clk, i_rst,
mm_adr, mm_we, mm_idat, mm_odat);
input i_clk;
input i_rst;
output reg [11:0] mm_adr;
output reg mm_we;
input [23:0] mm_idat;
output reg [23:0] mm_odat;
// Instruction decode
reg [23:0] r_inst;
wire [8:0] w_inst_OP;
wire [2:0] w_inst_T;
wire [10:0] w_inst_Y;
assign w_inst_OP = r_inst[23:15];
assign w_inst_T = r_inst[14:12];
assign w_inst_Y = r_inst[11:0];
// Registers
reg [23:0] r_L;
reg [23:0] r_R;
reg [11:0] r_PC;
reg [7:0] r_JR;
reg [7:0] r_JS;
reg [11:0] r_XR [6:0];
integer i;
wire w_do_Y_offset;
reg [11:0] w_Y_wrap;
// assign w_Y_wrap = (|w_inst_T & w_do_Y_offset) ?
// w_inst_Y - m_XR[w_inst_T-1] : w_inst_Y;
assign w_do_Y_offset = (w_inst_OP == 9'o400) ? 1'b0 : 1'b1;
wire [23:0] w_store1_data;
assign w_store1_data = (w_inst_OP == `RCA110_OP_STZ) ? 24'h00 :
(w_inst_OP == `RCA110_OP_STL) ? r_L :
(w_inst_OP == `RCA110_OP_STR) ? r_R : 24'h00;
reg [2:0] r_state;
reg [2:0] r_state_next;
localparam SFETCH1 = 3'b000; // Fetch I
localparam SFETCH2 = 3'b001; // Decode
localparam SEXEC1 = 3'b010; // Execute single operations
localparam SEXEC2 = 3'b011; // Memory Writeback
// Index register update
always @(posedge i_clk) begin
if(i_rst) begin
for(i = 0; i < 7; i = i + 1)
r_XR[i] <= 0;
end
else begin
if(mm_we && (mm_adr >= 12'o0001 && mm_adr <= 12'o0007)) begin
$display("r_XR[%d] <= %h", mm_adr, mm_odat);
r_XR[mm_adr[2:0] - 1] = mm_odat;
end
end
end
always @(posedge i_clk) begin
if(i_rst) begin
mm_adr <= 0;
mm_we <= 0;
mm_odat <= 0;
r_L <= 0;
r_R <= 0;
r_PC <= 64;
r_JR <= 0;
r_JS <= 0;
r_state <= SFETCH1;
r_state_next <= SFETCH1;
r_inst <= 0;
end
else begin
case(r_state)
SFETCH1:
begin
mm_adr <= r_PC;
mm_we <= 0;
mm_odat <= 0;
r_state <= SFETCH2;
r_PC = r_PC+1;
end
SFETCH2:
begin
r_inst <= mm_idat;
r_state <= SEXEC1;
if(|mm_idat[14:12])
w_Y_wrap <= mm_idat[11:0] - r_XR[mm_idat[14:12]-1];
else
w_Y_wrap <= mm_idat[11:0];
end
SEXEC1:
begin
r_state = SFETCH1;
case(w_inst_OP)
// Load & Store
`RCA110_OP_STP:
begin
mm_adr <= w_Y_wrap;
mm_we <= 1'b1;
mm_odat[11:0] <= ~(r_PC-1);
mm_odat[23:12] <= 0;
end
`RCA110_OP_LDZ:
begin
r_L <= 0;
end
`RCA110_OP_LDL,
`RCA110_OP_LDR,
`RCA110_OP_LDB,
`RCA110_OP_ADD,
`RCA110_OP_LDA:
begin
mm_adr <= w_Y_wrap;
mm_we <= 0;
r_state = SEXEC2;
r_state_next = SEXEC2; // Used as flag
end
`RCA110_OP_STZ,
`RCA110_OP_STL,
`RCA110_OP_STR:
begin
mm_adr <= w_Y_wrap;
mm_odat <= w_store1_data;
mm_we <= 1;
r_state <= SFETCH1;
end
`RCA110_OP_STB:
begin
mm_adr <= w_Y_wrap;
mm_odat <= r_R;
mm_we <= 1;
r_state <= SEXEC2;
end
`RCA110_OP_STA:
// First fetch than save since it only affects bit 11:0
begin
mm_adr <= w_Y_wrap;
r_state <= SEXEC2;
end
endcase // case (w_inst_OP)
end // case: SEXEC1
SEXEC2:
begin
case(w_inst_OP)
`RCA110_OP_LDL:
begin
r_L <= mm_idat;
end
`RCA110_OP_LDR:
begin
r_R <= mm_idat;
end
`RCA110_OP_LDB:
begin
if(r_state_next == SEXEC2) begin
r_R <= mm_idat;
mm_adr <= w_Y_wrap+1;
r_state_next <= SFETCH1;
end
else begin
r_L <= mm_idat;
r_state <= SFETCH1;
end
end // case: `RCA110_OP_LDB
`RCA110_OP_LDA:
begin
r_L[11:0] <= mm_idat[11:0];
r_state <= SFETCH1;
end
`RCA110_OP_STB:
begin
mm_adr <= w_Y_wrap+1;
mm_odat <= r_L;
r_state <= SFETCH1;
end
`RCA110_OP_STA:
begin
mm_adr <= w_Y_wrap;
mm_odat[23:12] <= mm_idat[23:12];
mm_odat[11:0] <= r_L[11:0];
mm_we <= 1;
end
`RCA110_OP_ADD,
`RCA110_OP_ADR:
begin
r_L = r_L + mm_idat;
mm_odat <= r_L + mm_idat;
mm_we <= 1'b1;
mm_adr <= w_Y_wrap;
end
endcase // case (w_inst_OP)
end
endcase // case (r_state)
end
end
endmodule // rca110
module tb;
reg clk = 0;
reg rst = 1;
wire [11:0] mm_adr;
wire mm_we;
wire [23:0] mm_idat;
wire [23:0] mm_odat;
rca110_memory mem(clk, rst, mm_adr, mm_we, mm_idat, mm_odat);
rca110 cpu(clk, rst,
mm_adr, mm_we, mm_idat, mm_odat);
always #10 clk = ~clk;
always @(posedge clk) begin
rst <= 0;
end
initial begin
$dumpfile("rca110.vcd");
$dumpvars(0, mem);
$dumpvars(0, cpu);
#500 $finish();
end
endmodule // tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:45:59 02/22/2015
// Design Name:
// Module Name: Allign
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Allign(
input [1:0] idle_NormaliseProd,
input [35:0] cout_NormaliseProd,
input [35:0] zout_NormaliseProd,
input [31:0] sout_NormaliseProd,
input [1:0] modeout_NormaliseProd,
input operationout_NormaliseProd,
input NatLogFlagout_NormaliseProd,
input [49:0] productout_NormaliseProd,
input [7:0] InsTag_NormaliseProd,
input clock,
output reg [1:0] idle_Allign,
output reg [35:0] cout_Allign,
output reg [35:0] zout_Allign,
output reg [31:0] sout_Allign,
output reg [1:0] modeout_Allign,
output reg operationout_Allign,
output reg NatLogFlagout_Allign,
output reg [7:0] difference_Allign,
output reg [7:0] InsTag_Allign
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_NormaliseProd[35];
assign z_exponent = zout_NormaliseProd[34:27];
assign z_mantissa = {zout_NormaliseProd[26:0]};
assign c_sign = cout_NormaliseProd[35];
assign c_exponent = cout_NormaliseProd[34:27] - 127;
assign c_mantissa = {cout_NormaliseProd[26:0]};
always @ (posedge clock)
begin
InsTag_Allign <= InsTag_NormaliseProd;
idle_Allign <= idle_NormaliseProd;
modeout_Allign <= modeout_NormaliseProd;
operationout_Allign <= operationout_NormaliseProd;
NatLogFlagout_Allign <= NatLogFlagout_NormaliseProd;
if (idle_NormaliseProd == no_idle || idle_NormaliseProd == allign_idle) begin
if ($signed(z_exponent) > $signed(c_exponent)) begin
difference_Allign <= z_exponent - c_exponent;
end
else if ($signed(z_exponent) <= $signed(c_exponent)) begin
difference_Allign <= c_exponent - z_exponent;
end
// Most of the special cases will never occur except the case where one input is zero.
// The HCORDIC module will not receive NaN and inf at input stage.
//if c is NaN or z is NaN return NaN
if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin
sout_Allign[31] <= 1;
sout_Allign[30:23] <= 255;
sout_Allign[22] <= 1;
sout_Allign[21:0] <= 0;
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
//if c is inf return inf
end else if (c_exponent == 128) begin
sout_Allign[31] <= c_sign;
sout_Allign[30:23] <= 255;
sout_Allign[22:0] <= 0;
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
//if z is inf return inf
end else if (z_exponent == 128) begin
sout_Allign[31] <= z_sign;
sout_Allign[30:23] <= 255;
sout_Allign[22:0] <= 0;
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
//if c is zero return z
end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin
sout_Allign[31] <= c_sign & z_sign;
sout_Allign[30:23] <= z_exponent[7:0] + 127;
sout_Allign[22:0] <= z_mantissa[26:3];
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
//if c is zero return z
end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin
sout_Allign[31] <= z_sign;
sout_Allign[30:23] <= z_exponent[7:0] + 127;
sout_Allign[22:0] <= z_mantissa[26:3];
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
//if z is zero return c
end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin
sout_Allign[31] <= c_sign;
sout_Allign[30:23] <= c_exponent[7:0] + 127;
sout_Allign[22:0] <= c_mantissa[26:3];
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
idle_Allign <= put_idle;
end else begin
sout_Allign <= sout_NormaliseProd;
//Denormalised Number
if ($signed(c_exponent) == -127) begin
cout_Allign[34:27] <= -126;
cout_Allign[35] <= c_sign;
cout_Allign[26:0] <= c_mantissa;
end else begin
cout_Allign[34:27] <= c_exponent + 127;
cout_Allign[35] <= c_sign;
cout_Allign[26] <= 1;
cout_Allign[25:0] <= c_mantissa[25:0];
end
//Denormalised Number
if ($signed(z_exponent) == -127) begin
zout_Allign[35] <= z_sign;
zout_Allign[34:27] <= -126;
zout_Allign[26:0] <= z_mantissa;
end else begin
zout_Allign[35] <= z_sign;
zout_Allign[34:27] <= z_exponent + 127;
zout_Allign[25:0] <= z_mantissa[25:0];
zout_Allign[26] <= 1;
end
end
end
else begin
sout_Allign <= sout_NormaliseProd;
zout_Allign <= zout_NormaliseProd;
cout_Allign <= cout_NormaliseProd;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { return (a > b ? a = b, true : false); } template <class T> bool uax(T &a, T b) { return (a < b ? a = b, true : false); } int const X = 8; int const L = 26; int const N = 41; long long const INF = 3e18 + 41; int x, k, n, q; int c[N]; int p[N], w[N]; long long d[(1 << X)][(1 << X)][L]; long long ans; bool bit(int m, int i) { return (m & (1 << i)); } int xorbit(int m, int i) { return (m ^ (1 << i)); } int qbit(int m) { int res = 0; while (m) { res += (m & 1); m /= 2; } return res; } int dx[(1 << X)][(1 << X)]; unordered_map<int, int> a; vector<pair<int, long long>> e[(1 << X)][L]; void build() { for (int i = 0; i < (1 << X); ++i) for (int j = 0; j < (1 << X); ++j) for (int o = 0; o < L; ++o) d[i][j][o] = INF; memset(dx, 255, sizeof(dx)); for (int i = 0; i < (1 << k); ++i) { if (!bit(i, 0)) { int m0 = i; int m1 = (m0 >> 1); uin(d[m0][m1][0], 0ll); } else { int m0 = i; for (int j = 1; j < k + 1; ++j) { if (bit(m0, j)) continue; int m1 = xorbit(m0, j); m1 = xorbit(m1, 0); m1 >>= 1; if (uin(d[m0][m1][0], (long long)c[j - 1])) dx[m0][m1] = j; } } } for (int o = 1; o < L; ++o) { for (int t = 0; t < (1 << k); ++t) { if (qbit(t) != x) continue; for (int i = 0; i < (1 << k); ++i) { if (qbit(i) != x) continue; for (int j = 0; j < (1 << k); ++j) { if (qbit(j) != x) continue; uin(d[i][j][o], d[i][t][o - 1] + d[t][j][o - 1]); } } } } for (int o = 0; o < L; ++o) { for (int i = 0; i < (1 << X); ++i) for (int j = 0; j < (1 << X); ++j) if (d[i][j][o] < INF) { if (qbit(i) != x) continue; e[i][o].push_back(make_pair(j, d[i][j][o])); } } } long long f[(1 << X)], nf[(1 << X)]; void solve() { int p1 = 0; int x0 = 0; for (int i = 0; i < (1 << X); ++i) f[i] = INF; f[(1 << x) - 1] = 0; while (x0 < n - x) { while (p1 < q && x0 > p[p1]) ++p1; int s; for (int i = L - 1; i >= 0; --i) { s = i; if (x0 + (1 << i) + k - 1 > n - 1) continue; if (p1 != q && x0 + (1 << i) + k - 1 >= p[p1]) continue; break; } for (int i = 0; i < (1 << k); ++i) nf[i] = INF; for (int i = 0; i < (1 << k); ++i) { if (f[i] == INF) continue; for (pair<int, long long> p : e[i][s]) { long long v = f[i] + p.second; if (s == 0 && dx[i][p.first] != -1 && a.find(x0 + dx[i][p.first]) != a.end()) { v += a[x0 + dx[i][p.first]]; } uin(nf[p.first], v); } } memcpy(f, nf, sizeof(f)); x0 += (1 << s); } ans = f[(1 << x) - 1]; } int main() { scanf( %d %d %d %d , &x, &k, &n, &q); for (int i = 0; i < k; ++i) scanf( %d , &c[i]); for (int i = 0; i < q; ++i) { scanf( %d %d , &p[i], &w[i]); --p[i]; a[p[i]] = w[i]; } for (int i = 0; i < q; ++i) for (int j = i + 1; j < q; ++j) if (p[j] < p[i]) { swap(p[j], p[i]); swap(w[j], w[i]); } build(); solve(); printf( %I64d n , ans); return 0; }
|
module spi_engine_execution (
input clk,
input resetn,
output reg active,
output cmd_ready,
input cmd_valid,
input [15:0] cmd,
input sdo_data_valid,
output reg sdo_data_ready,
input [7:0] sdo_data,
input sdi_data_ready,
output reg sdi_data_valid,
output [7:0] sdi_data,
input sync_ready,
output reg sync_valid,
output [7:0] sync,
output reg sclk,
output sdo,
output reg sdo_t,
input sdi,
output reg [NUM_CS-1:0] cs,
output reg three_wire
);
parameter NUM_CS = 1;
parameter DEFAULT_SPI_CFG = 0;
parameter DEFAULT_CLK_DIV = 0;
localparam CMD_TRANSFER = 2'b00;
localparam CMD_CHIPSELECT = 2'b01;
localparam CMD_WRITE = 2'b10;
localparam CMD_MISC = 2'b11;
localparam MISC_SYNC = 1'b0;
localparam MISC_SLEEP = 1'b1;
localparam REG_CLK_DIV = 1'b0;
localparam REG_CONFIG = 1'b1;
reg idle;
reg [7:0] clk_div_counter = 'h00;
reg [7:0] clk_div_counter_next = 'h00;
reg clk_div_last;
reg [11:0] counter = 'h00;
wire [7:0] sleep_counter = counter[11:4];
wire [1:0] cs_sleep_counter = counter[5:4];
wire [2:0] cs_sleep_counter2 = counter[6:4];
wire [2:0] bit_counter = counter[3:1];
wire [7:0] transfer_counter = counter[11:4];
wire ntx_rx = counter[0];
reg trigger = 1'b0;
reg trigger_next = 1'b0;
reg wait_for_io = 1'b0;
reg transfer_active = 1'b0;
wire last_bit;
wire first_bit;
reg last_transfer;
wire end_of_word;
assign first_bit = bit_counter == 'h0;
assign last_bit = bit_counter == 'h7;
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
reg [15:0] cmd_d1;
reg cpha = DEFAULT_SPI_CFG[0];
reg cpol = DEFAULT_SPI_CFG[1];
reg [7:0] clk_div = DEFAULT_CLK_DIV;
wire sdo_enabled = cmd_d1[8];
wire sdi_enabled = cmd_d1[9];
reg [8:0] data_shift = 'h0;
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
wire exec_cmd = cmd_ready && cmd_valid;
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
assign cmd_ready = idle;
always @(posedge clk) begin
if (cmd_ready)
cmd_d1 <= cmd;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else begin
if (exec_cmd == 1'b1)
active <= 1'b1;
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
active <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cpha <= DEFAULT_SPI_CFG[0];
cpol <= DEFAULT_SPI_CFG[1];
three_wire <= DEFAULT_SPI_CFG[2];
clk_div <= DEFAULT_CLK_DIV;
end else if (exec_write_cmd == 1'b1) begin
if (cmd[8] == REG_CONFIG) begin
cpha <= cmd[0];
cpol <= cmd[1];
three_wire <= cmd[2];
end else if (cmd[8] == REG_CLK_DIV) begin
clk_div <= cmd[7:0];
end
end
end
always @(posedge clk) begin
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
clk_div_counter == 'h01) || clk_div == 'h00)
clk_div_last <= 1'b1;
else
clk_div_last <= 1'b0;
end
always @(posedge clk) begin
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
clk_div_counter <= clk_div;
trigger <= 1'b1;
end else begin
clk_div_counter <= clk_div_counter - 1'b1;
trigger <= 1'b0;
end
end
wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
wire trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
wire sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
always @(posedge clk) begin
if (idle == 1'b1)
counter <= 'h00;
else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
counter <= counter + (transfer_active ? 'h1 : 'h10);
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle <= 1'b1;
end else begin
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
idle <= 1'b0;
end else begin
case (inst_d1)
CMD_TRANSFER: begin
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
idle <= 1'b1;
end
CMD_CHIPSELECT: begin
if (cs_sleep_counter_compare2)
idle <= 1'b1;
end
CMD_MISC: begin
case (cmd_d1[8])
MISC_SLEEP: begin
if (sleep_counter_compare)
idle <= 1'b1;
end
MISC_SYNC: begin
if (sync_ready)
idle <= 1'b1;
end
endcase
end
endcase
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
cs <= cmd_d1[NUM_CS-1:0];
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
sync_valid <= 1'b0;
end else begin
if (exec_sync_cmd == 1'b1) begin
sync_valid <= 1'b1;
end else if (sync_ready == 1'b1) begin
sync_valid <= 1'b0;
end
end
end
assign sync = cmd_d1[7:0];
always @(posedge clk) begin
if (resetn == 1'b0)
sdo_data_ready <= 1'b0;
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
transfer_active == 1'b1)
sdo_data_ready <= 1'b1;
else if (sdo_data_valid == 1'b1)
sdo_data_ready <= 1'b0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
sdi_data_valid <= 1'b0;
else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
transfer_active == 1'b1)
sdi_data_valid <= 1'b1;
else if (sdi_data_ready == 1'b1)
sdi_data_valid <= 1'b0;
end
wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
always @(posedge clk) begin
if (idle == 1'b1) begin
last_transfer <= 1'b0;
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
if (transfer_counter == cmd_d1[7:0])
last_transfer <= 1'b1;
else
last_transfer <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
transfer_active <= 1'b0;
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
if (io_ready2 == 1'b0)
wait_for_io <= 1'b1;
end
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
begin
sdo_t <= ~sdo_enabled;
end else begin
sdo_t <= 1'b1;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
if (first_bit == 1'b1)
data_shift[8:1] <= sdo_data;
else
data_shift[8:1] <= data_shift[7:0];
end
end
assign sdo = data_shift[8];
assign sdi_data = data_shift[7:0];
always @(posedge clk) begin
if (trigger_rx == 1'b1) begin
data_shift[0] <= sdi;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1) begin
sclk <= cpol ^ cpha ^ ntx_rx;
end else begin
sclk <= cpol;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Primary Global Buffer for Driving Clocks or Long Lines
// /___/ /\ Filename : BUFGP.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFGP (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int a[maxn], vis[maxn]; int main() { int n, p, flag = 0, mark = 0, tot = 0, Min = 1e9 + 7, cur, Max = -1e9 - 7, Maxcur; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] == 0) vis[i] = 1, mark = 1; else if (a[i] < 0) { flag++; if (a[i] < Min) cur = i; Min = min(Min, a[i]); if (a[i] > Max) Maxcur = i; Max = max(Max, a[i]); } } if (flag % 2) vis[Maxcur] = 1, mark = 1; for (int i = 1; i <= n; i++) if (vis[i]) { p = i; break; } for (int i = p + 1; i <= n; i++) if (vis[i]) printf( 1 %d %d n , p, i), p = i, tot++; if (tot != n - 1 && mark) printf( 2 %d n , p); for (int i = 1; i <= n; i++) if (!vis[i]) { p = i; break; } for (int i = p + 1; i <= n; i++) if (!vis[i]) printf( 1 %d %d n , p, i), p = i; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.v
// Design : system_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module system_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int T[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int W[24]; bool ok(int n) { bool l = false; for (int i = 0; i < 12; i++) { bool f = true; for (int j = 0; j < n; j++) { if (T[i + j] != W[j]) { if ((i + j) % 12 == 1 && W[j] == 29 && !l) { l = true; continue; } else f = false; } } if (f == true) return true; } return false; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &W[i]); if (ok(n)) printf( YES n ); else printf( NO n ); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:30 06/09/2015
// Design Name: game_text_top
// Module Name: D:/OnGoingProject/Curriculum/ISE/Proj_x/proj_test/test_game_text_top.v
// Project Name: proj_test
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: game_text_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_game_text_top;
// Inputs
reg clk;
reg reset;
reg [1:0] btn;
// Outputs
wire hsync;
wire vsync;
wire [2:0] rgb;
// Instantiate the Unit Under Test (UUT)
game_text_top uut (
.clk(clk),
.reset(reset),
.btn(btn),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
btn = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever #10 clk=~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using lint = long long; using ulint = unsigned long long; const int N = 1500 + 1; int a[N]; int bit[N]; int back[N]; int lsb(int x) { return x & -x; } int query(int r) { int res = 0; for (; r > 0; r -= lsb(r)) { res = max(res, bit[r]); } return res; } void update(int r, int k, int id) { for (; r < N; r += lsb(r)) { if (k > bit[r]) { bit[r] = k; back[r] = id; } } } int main(void) { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] += a[i - 1]; } map<int, vector<pair<int, int>>> sums; for (int l = 1; l <= n; l++) { for (int r = l; r <= n; r++) { sums[a[r] - a[l - 1]].emplace_back(l, r); } } int best = -1, best_sum = -1; for (auto &sum : sums) { fill(begin(bit), end(bit), 0); auto &vec = sum.second; for (int i = 0; i < vec.size(); i++) { auto [l, r] = vec[i]; update(r, query(l - 1) + 1, i); } if (query(n) > best) { best = query(n); best_sum = sum.first; } } cout << best << n ; fill(begin(bit), end(bit), 0); fill(begin(back), end(back), -1); auto &vec = sums[best_sum]; for (int i = 0; i < vec.size(); i++) { auto [l, r] = vec[i]; int k = query(l - 1) + 1; update(r, k, i); if (k == best) { l = n + 1; for (int j = r; j >= 0; j--) { if (best > 0 && bit[j] == best && vec[back[j]].second < l) { cout << vec[back[j]].first << << vec[back[j]].second << n ; best--; l = vec[back[j]].first; } } break; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a; cin >> a; vector<long long> x; for (long long i = 0; i < a; i++) { long long b; cin >> b; x.push_back(b); } bool done[101] = {false}; sort(x.begin(), x.end()); long long counter = 0; long long ans = 0; while (counter != a) { long long num = 0; for (long long i = 0; i < a; i++) { if (x[i] >= num && !done[i]) { num++; counter++; done[i] = true; } } ans++; } cout << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_1_V
`define SKY130_FD_SC_LS__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_1_V
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module InterruptLogicTest;
reg clk;
reg rst_x;
reg r_irq_x;
reg r_nmi_x;
wire [ 7:0] w_mc2il_data;
wire [15:0] w_il2mc_addr;
wire w_il2mc_read;
wire [ 7:0] w_il2rf_data;
wire w_il2rf_set_pcl;
wire w_il2rf_set_pch;
wire w_il2rf_pushed;
MC6502InterruptLogic dut(
.clk (clk ),
.rst_x (rst_x ),
.i_irq_x (r_irq_x ),
.i_nmi_x (r_nmi_x ),
.mc2il_data (w_mc2il_data ),
.mc2il_brk (1'b0 ),
.il2mc_addr (w_il2mc_addr ),
.il2mc_read (w_il2mc_read ),
.rf2il_s (8'h00 ),
.rf2il_psr (8'h00 ),
.rf2il_pc (16'h0000 ),
.il2rf_data (w_il2rf_data ),
.il2rf_set_pcl(w_il2rf_set_pcl),
.il2rf_set_pch(w_il2rf_set_pch),
.il2rf_pushed (w_il2rf_pushed ));
always #1 clk = !clk;
assign w_mc2il_data = 8'h89;
always @ (posedge clk) begin
if (rst_x & w_il2mc_read & w_il2rf_set_pcl) begin
$display("load pcl: $%04x", w_il2mc_addr);
end
if (rst_x & w_il2rf_set_pcl) begin
$display("set pcl: $%02x", w_il2rf_data);
end
if (rst_x & w_il2mc_read & w_il2rf_set_pch) begin
$display("load pch: $%04x", w_il2mc_addr);
end
if (rst_x & w_il2rf_set_pch) begin
$display("set pch: $%02x", w_il2rf_data);
end
end
initial begin
$dumpfile("InterruptLogic.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b0;
r_irq_x <= 1'b1;
r_nmi_x <= 1'b1;
#2
rst_x <= 1'b1;
#10
// IRQ and NMI implementation is not correct, but just check the outgoing
// addresses for now.
r_irq_x <= 1'b0;
#2
r_irq_x <= 1'b1;
#10
r_nmi_x <= 1'b0;
#2
r_nmi_x <= 1'b1;
#10
$finish;
end
endmodule // InterruptLogicTest
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } int main() { int k; cin >> k; long long a; while (k--) { cin >> a; long long g = gcd(a + 1, a * 4); long long l = (a + 1) * a * 4 / g; cout << l / (a + 1) + 1 << ; } return 0; }
|
/**
# Rx8b10b Receiver/Decoder #
Takes in an unaligned serial bit stream, aligns to comma symbols in the data,
and decodes the 8b10b encoded data.
## Bit Alignment ##
Bit alignment here is extremely naive: it aligns to the latest detected bit edge
in the bitstream.
## Word Alignment ##
Word alignment is done by aligning to either of the "fill words" selected by the
parameter section. Compared to the bit alignment section, it looks two bit
periods earlier in the bitstream. This allows it to align to a comma value where
the first transition is two bit periods in.
## Decoding ##
Decoding is relatively simple: use look-up tables of known 6b/5b codes and 4b/3b
codes to get the 8 bit word. If the code word doesn't show up, then we know we
have an error.
## Possible Future Improvements ##
Bit alignment has very little noise immunity. It can be improved by decreasing
response to edges after an initial lock, and by using an integrate & dump filter
for the bit to be shifted into the byte alignment section.
Better error detection could be achieved by tracking running disparity, then
determining if the code word is valid given that disparity state.
*/
module Rx8b10b #(
parameter FILL_WORD_RD0 = 10'b0011111010, ///< Send when no data present & RD=-1
parameter FILL_WORD_RD1 = 10'b1100000101, ///< Send when no data present & RD=1
parameter FILL_WORD_FLIP = 1'b1, ///< Flip status of Running Disparity when using fill word
parameter CLK_RATE = 8, ///< Number of clocks per data bit
parameter LOG2_DEPTH = 4 ///< log2(depth of FIFO buffer). Must be an integer.
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input rxEnable, ///< Set to start/enable receiver
input rx, ///< Receive line
input readStrobe, ///< Read data from receive FIFO
output dataPresent, ///< FIFO has data still in it
output halfFull, ///< FIFO halfway full
output full, ///< FIFO is completely full. Don't write to it.
output errorDetect, ///< Error detected. Does not latch.
output [7:0] dataOut ///< Data received
);
parameter integer CLK_COUNT_WIDTH = $clog2(CLK_RATE-1);
localparam CLK_COUNT_INIT = CLK_RATE-1;
localparam CLK_COUNT_CAPTURE = (CLK_RATE>>1);
localparam RX_DELAY_LEN = CLK_RATE*2;
wire rxClk;
reg [RX_DELAY_LEN-1:0] rxDelay;
reg [CLK_COUNT_WIDTH-1:0] rxClkCount;
reg [7:0] decodedData;
reg [1:10] shiftData;
reg [3:0] inCounter;
reg shiftDone;
reg locked;
reg writeStrobe;
reg rxD1;
reg error5b6b;
reg error3b4b;
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo
(
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(writeStrobe), ///< Write strobe (1 clk)
.read(readStrobe), ///< Read strobe (1 clk)
.dataIn(decodedData), ///< [WIDTH-1:0] Data to write
// Outputs
.dataOut(dataOut), ///< [WIDTH-1:0] Data from FIFO
.dataPresent(dataPresent), ///< Data is present in FIFO
.halfFull(halfFull), ///< FIFO is half full
.full(full) ///< FIFO is full
);
end
else begin
assign dataOut = decodedData;
end
initial begin
rxDelay = 'd0;
rxD1 = 1'b0;
rxClkCount = 'd0;
shiftData = 'd0;
inCounter = 'd0;
shiftDone = 1'b0;
locked = 1'b0;
end
// Bit alignment
assign rxClk = (rxClkCount == CLK_COUNT_CAPTURE);
always @(posedge clk) begin
rxD1 <= rx;
if ((rx ^ rxD1) || (rxClkCount == 'd0)) begin
rxClkCount <= CLK_COUNT_INIT;
end
else begin
rxClkCount <= rxClkCount - 2'd1;
end
end
// Word alignment
always @(posedge clk) begin
// Delay serial data to look for "comma value" earlier in bitstream
rxDelay <= (rxDelay << 1) | rx;
// Input shift register
if (rxClk) begin
shiftData <= {shiftData[2:10], rxDelay[RX_DELAY_LEN-1]};
end
// Bit counter
if (rxEnable && ~locked
&& ((shiftData == FILL_WORD_RD1) || (shiftData == FILL_WORD_RD0)))
begin
inCounter <= 'd0;
shiftDone <= 1'b0;
locked <= 1'b1;
end
else if (rxEnable && locked && rxClk) begin
inCounter <= inCounter + 2'd1;
shiftDone <= 1'b0;
end
else if ((inCounter == 'd10)
&& !((shiftData == FILL_WORD_RD1) || (shiftData == FILL_WORD_RD0)))
begin
inCounter <= 'd0;
shiftDone <= 1'b1;
end
else if (inCounter == 'd10) begin
inCounter <= 'd0;
end
else if (~rxEnable) begin
inCounter <= 'd0;
shiftDone <= 1'b0;
locked <= 1'b0;
end
else begin
inCounter <= inCounter;
shiftDone <= 1'b0;
end
end
// Word Decoder
assign errorDetect = error5b6b | error3b4b;
always @(posedge clk) begin
if (rst) begin
error5b6b <= 1'b0;
error3b4b <= 1'b0;
decodedData <= 'd0;
writeStrobe <= 1'b0;
end
else begin
if (shiftDone) begin
writeStrobe <= 1'b1;
error5b6b <= 1'b0;
error3b4b <= 1'b0;
case (shiftData[1:6])
6'b100111 : decodedData[4:0] <= 5'b00000;
6'b011000 : decodedData[4:0] <= 5'b00000;
6'b011101 : decodedData[4:0] <= 5'b00001;
6'b100010 : decodedData[4:0] <= 5'b00001;
6'b101101 : decodedData[4:0] <= 5'b00010;
6'b010010 : decodedData[4:0] <= 5'b00010;
6'b110001 : decodedData[4:0] <= 5'b00011;
6'b110101 : decodedData[4:0] <= 5'b00100;
6'b001010 : decodedData[4:0] <= 5'b00100;
6'b101001 : decodedData[4:0] <= 5'b00101;
6'b011001 : decodedData[4:0] <= 5'b00110;
6'b111000 : decodedData[4:0] <= 5'b00111;
6'b000111 : decodedData[4:0] <= 5'b00111;
6'b111001 : decodedData[4:0] <= 5'b01000;
6'b000110 : decodedData[4:0] <= 5'b01000;
6'b100101 : decodedData[4:0] <= 5'b01001;
6'b010101 : decodedData[4:0] <= 5'b01010;
6'b110100 : decodedData[4:0] <= 5'b01011;
6'b001101 : decodedData[4:0] <= 5'b01100;
6'b101100 : decodedData[4:0] <= 5'b01101;
6'b011100 : decodedData[4:0] <= 5'b01110;
6'b010111 : decodedData[4:0] <= 5'b01111;
6'b101000 : decodedData[4:0] <= 5'b01111;
6'b011011 : decodedData[4:0] <= 5'b10000;
6'b100100 : decodedData[4:0] <= 5'b10000;
6'b100011 : decodedData[4:0] <= 5'b10001;
6'b010011 : decodedData[4:0] <= 5'b10010;
6'b110010 : decodedData[4:0] <= 5'b10011;
6'b001011 : decodedData[4:0] <= 5'b10100;
6'b101010 : decodedData[4:0] <= 5'b10101;
6'b011010 : decodedData[4:0] <= 5'b10110;
6'b111010 : decodedData[4:0] <= 5'b10111;
6'b000101 : decodedData[4:0] <= 5'b10111;
6'b110011 : decodedData[4:0] <= 5'b11000;
6'b001100 : decodedData[4:0] <= 5'b11000;
6'b100110 : decodedData[4:0] <= 5'b11001;
6'b010110 : decodedData[4:0] <= 5'b11010;
6'b110110 : decodedData[4:0] <= 5'b11011;
6'b001001 : decodedData[4:0] <= 5'b11011;
6'b001110 : decodedData[4:0] <= 5'b11100;
6'b101110 : decodedData[4:0] <= 5'b11101;
6'b010001 : decodedData[4:0] <= 5'b11101;
6'b011110 : decodedData[4:0] <= 5'b11110;
6'b100001 : decodedData[4:0] <= 5'b11110;
6'b101011 : decodedData[4:0] <= 5'b11111;
6'b010100 : decodedData[4:0] <= 5'b11111;
default : begin decodedData[4:0] <= 5'b00000; error5b6b <= 1'b1; end
endcase
case (shiftData[7:10])
4'b1011 : decodedData[7:5] <= 3'b000;
4'b0100 : decodedData[7:5] <= 3'b000;
4'b1001 : decodedData[7:5] <= 3'b001;
4'b0101 : decodedData[7:5] <= 3'b010;
4'b1100 : decodedData[7:5] <= 3'b011;
4'b0011 : decodedData[7:5] <= 3'b011;
4'b1101 : decodedData[7:5] <= 3'b100;
4'b0010 : decodedData[7:5] <= 3'b100;
4'b1010 : decodedData[7:5] <= 3'b101;
4'b0110 : decodedData[7:5] <= 3'b110;
4'b0111 : decodedData[7:5] <= 3'b111;
4'b1110 : decodedData[7:5] <= 3'b111;
4'b1000 : decodedData[7:5] <= 3'b111;
4'b0001 : decodedData[7:5] <= 3'b111;
default : begin decodedData[7:5] <= 3'b000; error3b4b <= 1'b1; end
endcase
end
else begin
writeStrobe <= 1'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char BUF[500010]; int n, m; int up[500010], down[500010], L[500010], R[500010]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %s , &BUF); for (int j = 0; j < m; ++j) switch (BUF[j]) { case 1 : if (j & 1) R[i] = 1; else L[i] = 1; if (i & 1) down[j] = 1; else up[j] = 1; break; case 2 : if (j & 1) R[i] = 1; else L[i] = 1; if (i & 1) up[j] = 1; else down[j] = 1; break; case 3 : if (j & 1) L[i] = 1; else R[i] = 1; if (i & 1) up[j] = 1; else down[j] = 1; break; case 4 : if (j & 1) L[i] = 1; else R[i] = 1; if (i & 1) down[j] = 1; else up[j] = 1; break; } } int ans = 1; for (int i = 0; i < n; ++i) ans = (ans * (2 - L[i] - R[i])) % 1000003; for (int i = 0; i < m; ++i) ans = (ans * (2 - up[i] - down[i])) % 1000003; printf( %d n , ans); return 0; }
|
module top;
reg passed;
reg signed[95:0] m_one, m_two, zero, one, two;
// Both argument positive.
reg signed[95:0] rem;
wire signed[95:0] wrem = one % two;
// First argument negative.
reg signed[95:0] rem1n;
wire signed[95:0] wrem1n = m_one % two;
// Second argument negative.
reg signed[95:0] rem2n;
wire signed[95:0] wrem2n = one % m_two;
// Both arguments negative.
reg signed[95:0] rembn;
wire signed[95:0] wrembn = m_one % m_two;
// Divide by zero.
reg signed[95:0] remd0;
wire signed[95:0] wremd0 = one % zero;
initial begin
passed = 1'b1;
m_one = 96'hffffffffffffffffffffffff;
m_two = 96'hfffffffffffffffffffffffe;
zero = 96'h000000000000000000000000;
one = 96'h000000000000000000000001;
two = 96'h000000000000000000000002;
#1;
// Both positive.
if (wrem !== 96'h000000000000000000000001) begin
$display("Failed: CA remainder, expected 96'h00...01, got %h",
wrem);
passed = 1'b0;
end
rem = one % two;
if (rem !== 96'h000000000000000000000001) begin
$display("Failed: remainder, expected 96'h00...01, got %h",
rem);
passed = 1'b0;
end
// First negative.
if (wrem1n !== 96'hffffffffffffffffffffffff) begin
$display("Failed: CA remainder (1n), expected 96'hff...ff, got %h",
wrem1n);
passed = 1'b0;
end
rem1n = m_one % two;
if (rem1n !== 96'hffffffffffffffffffffffff) begin
$display("Failed: remainder (1n), expected 96'hff...ff, got %h",
rem1n);
passed = 1'b0;
end
// Second negative.
if (wrem2n !== 96'h000000000000000000000001) begin
$display("Failed: CA remainder (2n), expected 96'h00...01, got %h",
wrem2n);
passed = 1'b0;
end
rem2n = one % m_two;
if (rem2n !== 96'h000000000000000000000001) begin
$display("Failed: remainder (2n), expected 96'h00...01, got %h",
rem2n);
passed = 1'b0;
end
// Both negative.
if (wrembn !== 96'hffffffffffffffffffffffff) begin
$display("Failed: CA remainder (bn), expected 96'hff...ff, got %h",
wrembn);
passed = 1'b0;
end
rembn = m_one % m_two;
if (rembn !== 96'hffffffffffffffffffffffff) begin
$display("Failed: remainder (bn), expected 96'hff...ff, got %h",
rembn);
passed = 1'b0;
end
// Divide by zero.
if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: CA remainder (d0), expected 96'hxx...xx, got %h",
wremd0);
passed = 1'b0;
end
remd0 = one % zero;
if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: remainder (d0), expected 96'hxx...xx, got %h",
remd0);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops ) using namespace std; const long long N = 2e5 + 36; const long long M = 1e3 + 36; const long long INF = 2e9 + 7; const long long MOD = 987654323; const int X[8] = {1, 1, -1, -1, 2, 2, -2, -2}; const int Y[8] = {2, -2, 2, -2, 1, -1, 1, -1}; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, ans = 0; cin >> n; string s, t; cin >> s >> t; for (int i(0); i < (n >> 1); ++i) { if (t[i] == t[n - i - 1]) { if (s[i] == s[n - i - 1]) { continue; } else { ans += 1; continue; } } else { if (s[i] == s[n - i - 1]) { if (t[i] == s[i] || t[n - i - 1] == s[i]) { ans += 1; continue; } else { ans += 2; continue; } } else { if (s[i] != t[i] && s[i] != t[n - i - 1] && s[n - i - 1] != t[i] && s[n - i - 1] != t[n - i - 1]) { ans += 2; continue; } if (min(t[i], t[n - i - 1]) == min(s[i], s[n - i - 1]) && max(t[i], t[n - i - 1]) == max(s[i], s[n - i - 1])) { continue; } else { ans += 1; continue; } } } } if (n % 2 == 1) { if (s[(n >> 1)] != t[(n >> 1)]) ans++; } cout << ans << n ; return 0; }
|
`timescale 1ns/1ns
module usb_ctrl // usb control endpoint transfer
(input c, // bus clock
input rst,
output token_start,
output ack_start,
input tx_sie_done,
input [ 6:0] addr,
input [63:0] d,
output [18:0] token,
output [7:0] txd,
output txdv,
input [7:0] rxd,
input rxdv,
input start,
output done);
localparam ST_IDLE = 4'h0;
localparam ST_TX_SETUP = 4'h1;
localparam ST_TX_SETUP_WAIT = 4'h2;
localparam ST_TX_DATA_PID = 4'h3;
localparam ST_TX_DATA = 4'h4;
localparam ST_TX_DATA_WAIT = 4'h5;
localparam ST_TX_DATA_ACK_WAIT = 4'h6;
localparam ST_TX_IN = 4'h7;
localparam ST_TX_IN_WAIT = 4'h8;
localparam ST_RX_PID = 4'h9;
localparam ST_RX_DATA = 4'ha;
localparam ST_RX_NAK = 4'hb;
localparam ST_TX_ACK = 4'hc;
localparam ST_TX_ACK_WAIT = 4'hd;
localparam ST_SUCCESS = 4'he;
localparam ST_ERROR = 4'hf;
`include "usb_pids.v"
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(rst), .en(1'b1), .d(next_state), .q(state));
wire [18:0] token_setup = { 4'b0, addr, PID_SETUP };
wire [18:0] token_in = { 4'b0, addr, PID_IN };
wire [1:0] token_sel;
gmux #(.DWIDTH(19), .SELWIDTH(2)) token_gmux
(.d({19'hx, 19'hx, token_in, token_setup }),
.sel(token_sel), .z(token));
wire [2:0] cnt;
r #(3) cnt_r
(.c(c), .rst(state == ST_TX_DATA_PID), .en(1'b1), .d(cnt + 1'b1), .q(cnt));
localparam NAK_TIMEOUT = 11'h3ff; // this seems to be what linux does
wire nak_timer_rst;
wire [10:0] nak_timer;
r #(11) nak_timer_r
(.c(c), .rst(nak_timer_rst), .en(1'b1), .d(nak_timer+1'b1), .q(nak_timer));
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_TX_SETUP , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_TX_SETUP: ctrl = { ST_TX_SETUP_WAIT , 5'b00000 };
ST_TX_SETUP_WAIT:
if (tx_sie_done) ctrl = { ST_TX_DATA_PID , 5'b00000 };
else ctrl = { ST_TX_SETUP_WAIT , 5'b00000 };
ST_TX_DATA_PID: ctrl = { ST_TX_DATA , 5'b00001 };
ST_TX_DATA:
if (cnt == 3'd7) ctrl = { ST_TX_DATA_WAIT , 5'b00001 };
else ctrl = { ST_TX_DATA , 5'b00001 };
ST_TX_DATA_WAIT:
if (tx_sie_done) ctrl = { ST_TX_DATA_ACK_WAIT , 5'b00000 };
else ctrl = { ST_TX_DATA_WAIT , 5'b00000 };
ST_TX_DATA_ACK_WAIT: // TODO: timeout
if (rxdv & rxd == PID_ACK) ctrl = { ST_TX_IN , 5'b00000 };
else ctrl = { ST_TX_DATA_ACK_WAIT , 5'b00000 };
ST_TX_IN: ctrl = { ST_TX_IN_WAIT , 5'b00010 };
ST_TX_IN_WAIT:
if (tx_sie_done) ctrl = { ST_RX_PID , 5'b00010 };
else ctrl = { ST_TX_IN_WAIT , 5'b00010 };
ST_RX_PID: // TODO: timeout
if (rxdv)
if (rxd == PID_DATA1) ctrl = { ST_RX_DATA , 5'b00000 };
else if (rxd == PID_NAK) ctrl = { ST_RX_NAK , 5'b01000 };
else ctrl = { ST_ERROR , 5'b00000 };
else ctrl = { ST_RX_PID , 5'b00000 };
ST_RX_NAK:
if (nak_timer == NAK_TIMEOUT) ctrl = { ST_TX_IN , 5'b00000 };
else ctrl = { ST_RX_NAK , 5'b00000 };
ST_RX_DATA:
if (~rxdv) ctrl = { ST_TX_ACK , 5'b00000 };
else ctrl = { ST_RX_DATA , 5'b00000 };
ST_TX_ACK: ctrl = { ST_TX_ACK_WAIT , 5'b00000 };
ST_TX_ACK_WAIT:
if (tx_sie_done) ctrl = { ST_SUCCESS , 5'b00000 };
else ctrl = { ST_TX_ACK_WAIT , 5'b00000 };
ST_SUCCESS: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_IDLE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign token_start = state == ST_TX_SETUP |
state == ST_TX_IN ;
assign ack_start = state == ST_TX_ACK;
assign token_sel = ctrl[2:1];
assign nak_timer_rst = ctrl[3];
assign done = state == ST_ERROR | state == ST_SUCCESS; // todo: distinguish...
wire [63:0] shift;
r #(64) shift_r
(.c(c), .rst(1'b0), .en(state == ST_IDLE | state == ST_TX_DATA),
.d(state == ST_IDLE ? d : { 8'h0, shift[63:8] }), .q(shift));
assign txdv = ctrl[0];
assign txd = state == ST_TX_DATA_PID ? PID_DATA0 : shift[7:0];
endmodule
|
//
// Author: Pawel Szostek ()
// Date: 01.08.2011
`timescale 1ns/1ps
module dummy_v( input [7:0] in, output reg [7:0] out);
assign out = {in[7], 7'b1111111}; //there is no equivalent to vhdl's `others'
endmodule
module stimulus (output reg [7:0] a);
parameter S = 20000;
int unsigned j,i;
initial begin
for(i=0; i<S; i=i+1) begin
#10;
a[7] <= inject();
a[6] <= inject();
a[5] <= inject();
a[4] <= inject();
a[3] <= inject();
a[2] <= inject();
a[1] <= inject();
a[0] <= inject();
end
end
function inject();
reg ret;
reg unsigned [3:0] temp;
temp[3:0] = $random % 16;
begin
if(temp >= 10)
ret = 1'b1;
else if(temp >= 4)
ret = 1'b0;
else if(temp >= 2)
ret = 1'bx;
else
ret = 1'b0;
inject = ret;
end
endfunction
endmodule
module main;
wire [7:0] i,o;
wire [7:0] veri;
dummy dummy_vhdl(i,o);
dummy_v dummy_verilog(i, veri);
stimulus stim(i);
always @(i) begin
#1;
if(o != veri) begin
$display("ERROR!");
$display("VERILOG: ", veri);
$display("VHDL: ", o);
$stop;
end
end
initial begin
#12000;
#10;
$display("PASSED");
//stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; const int maxn = 1e5 + 10; const int mod = 1e9 + 7; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); ll pwr(ll a, ll pw) { ll ret = 1; while (pw > 0) { if (pw & 1) { ret = ret * a % mod; } a = a * a % mod; pw >>= 1; } return ret; } ll modinv(ll a) { return pwr(a, mod - 2); } int main() { ios_base::sync_with_stdio(false), cin.tie(0); int n; cin >> n; vector<ll> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } vector<vector<ll> > prob_win(n, vector<ll>(n)); for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { prob_win[i][j] = v[i] * modinv(v[i] + v[j]) % mod; prob_win[j][i] = v[j] * modinv(v[i] + v[j]) % mod; } } vector<vector<ll> > win_msk(n, vector<ll>(1 << n, 1ll)); for (int i = 0; i < n; i++) { for (int msk = 0; msk < 1 << n; msk++) { for (int bit = 0; bit < n; bit++) { if (msk >> bit & 1) { win_msk[i][msk] = win_msk[i][msk] * prob_win[i][bit] % mod; } } } } ll ans = 0; vector<ll> dp_prob(1 << n, 1ll); for (int msk = 1; msk < 1 << n; msk++) { ll num_winners = __builtin_popcount(msk); for (int bit = 0; bit < n; bit++) { if (msk >> bit & 1) { dp_prob[msk] = dp_prob[msk] * win_msk[bit][(1 << n) - 1 - msk] % mod; } } for (int sub_winners = (msk - 1) & msk; sub_winners > 0; sub_winners = (sub_winners - 1) & msk) { int sub_losers = msk ^ sub_winners; ll p = dp_prob[sub_winners]; for (int bit = 0; bit < n; bit++) { if (sub_losers >> bit & 1) { p = p * win_msk[bit][(1 << n) - 1 - msk] % mod; } } dp_prob[msk] = (dp_prob[msk] - p + mod) % mod; } ans = (ans + dp_prob[msk] * num_winners % mod) % mod; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) #pragma GCC optimize( omit-frame-pointer ) #pragma GCC optimize( unroll-loops ) using namespace std; template <class T> void debug(vector<T> vec) { for (int i = 0; i < vec.size(); i++) cerr << vec[i] << ; cerr << n ; } template <class T> void debug(vector<vector<T> > vec) { for (int i = 0; i < vec.size(); i++) { for (int ii = 0; ii < vec[i].size(); ii++) cerr << vec[i][ii] << ; cerr << n ; } } void solve() { int T; int i; cin >> T; for (int i = 0; i < T; i++) { int n; string s; cin >> n; cin >> s; if (s.size() == 1) { cout << YES << n ; continue; } else if (s.size() == 2) { if (abs(s[0] - s[1]) > 2 || abs(s[0] - s[1]) == 1) cout << NO << n ; else cout << YES << n ; continue; } int x; bool possible = true; for (int x = 0; x < n / 2; x++) { if (abs(s[x] - s[n - x - 1]) > 2 || abs(s[x] - s[n - x - 1]) == 1) { possible = false; cout << NO << n ; break; } } if (possible == true) cout << YES << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); ; cin.tie(NULL); int testcases = 1; while (testcases-- != 0) { solve(); } }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Include definition of the control signals
`include "control.h"
// Non-synthesizable behavioral RTL model for the instruction memory
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Data output read from the data memory
output [0:127] data_out;
// ===============================================================
// Input signals
// Data input stored into the data memory
input [0:127] data_in;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input [0:31] mem_ctrl_addr;
// Clock signal
input clk;
// Control signals for the data memory
input [0:1] dm_ctrl_sig;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:127] data_out; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [127:0] data_mem [255:0]; // Store the data here
// Store instruction address in the instruction memory
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",data_mem);
end
// A change in the instruction address activates this...
always @(posedge clk)
begin
/**
* Check the control signal and implement the appropriate
* function
*/
case(dm_ctrl_sig)
`memwld:
begin
// Read the data from the memory
data_out<=data_mem[mem_ctrl_addr];
end
`memwst:
begin
// Write the data to the memory
data_mem[mem_ctrl_addr]<=data_in;
$display("Value written to data mem",data_mem[mem_ctrl_addr],"#");
end
`memnop:
begin
data_out<=128'd0;
end
default:
begin
data_out<=128'd0;
end
endcase
end
endmodule
|
module SmallBsf_tb ();
parameter K0_SHIFT = 6; ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 6; ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16; ///< Width of data path
parameter CLAMP = 1; ///< Set to 1 to clamp the accumulators
parameter FREQ_RATE = ;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] dataIn;
wire signed [WIDTH-1:0] dataOut;
integer i;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
#2 rst = 1'b0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $random();
end
$stop();
end
always #1 clk = ~clk;
SmallBsf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataIn), ///< [WIDTH-1:0] Filter input
.dataOut(dataOut) ///< [WIDTH-1:0] Filter output
);
endmodule
|
#include <bits/stdc++.h> using ll = long long; int main() { std::ios_base::sync_with_stdio(0); std::cin.tie(0); std::string s; std::cin >> s; int n = s.length(); std::vector<std::set<int>> adj(26); for (int i = 0; i < n; ++i) { int d = s[i] - a ; adj[d].insert(i); } int q; std::cin >> q; while (q--) { int op; std::cin >> op; if (op == 1) { int pos; char c; std::cin >> pos >> c; --pos; int d = s[pos] - a ; s[pos] = c; adj[d].erase(pos); adj[c - a ].insert(pos); } else { int l, r; std::cin >> l >> r; --l, --r; int ans = 0; for (int i = 0; i < 26; ++i) { if (adj[i].empty()) { continue; } auto it = adj[i].lower_bound(l); if (it == adj[i].end()) { continue; } int index = *it; if (index <= r) { ++ans; } } std::cout << ans << n ; } } }
|
#include <bits/stdc++.h> struct oficinas { int valor; int sig; }; int v[200002], vaux[200002]; int buscar(int buscado); int main() { int n, q, type, x, y, i, A, B, aux; scanf( %d %d , &n, &q); for (i = 1; i <= n; i++) { v[i] = i; vaux[i] = i + 1; } for (i = 0; i < q; i++) { scanf( %d %d %d , &type, &x, &y); switch (type) { case 1: v[buscar(x)] = buscar(y); break; case 2: while (x < y) { v[buscar(x)] = buscar(y); aux = vaux[x]; vaux[x] = vaux[y]; x = aux; } break; case 3: printf( %s n , buscar(x) == buscar(y) ? YES : NO ); break; } } return 0; } int buscar(int buscado) { return v[buscado] = v[buscado] == buscado ? buscado : buscar(v[buscado]); }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for the "cached" lsu
// Latency = 2
// Capacity = 1
//
// Description:
//
// This is essentially a streaming unit where threads can enter out of order
// It is organized as a direct mapped cache where there are N cache lines
// Each cache line is CACHESIZE bytes long
//
// By default, the values of N=8 and CACHESIZE=1024 bytes
//
// Feel free to change the parameters as determined by the data access patterns
//
// Note that this is a read only cache so one has to guarantee that data isn't
// going to get overwritten by some store within the kernel. The start signal
// is brought into this LSU to "flush" the cache once the kernel is started
//
// You'll notice that there are many similarities to the streaming unit including
// a FIFO size. Well, think of a cache as a FIFO where it can be accessed in any
// order :-)
//
// Note2: It is slightly different from other lsu's in that it needs a kernel start
// signal that tells it to invalidate it's contents
//
module lsu_read_cache
(
clk, reset, flush, o_stall, i_valid, i_stall, i_nop, o_valid, o_readdata,
o_active, //Debugging signal
i_address, avm_address, avm_burstcount, avm_read,
avm_readdata, avm_waitrequest, avm_byteenable, avm_readdatavalid,
// profile
req_cache_hit_count
);
/*************
* Parameters *
*************/
parameter AWIDTH=32;
parameter WIDTH_BYTES=32;
parameter MWIDTH_BYTES=32;
parameter ALIGNMENT_ABITS=6;
parameter BURSTCOUNT_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=1;
parameter REQUESTED_SIZE=1024;
parameter ACL_BUFFER_ALIGNMENT=128;
parameter ACL_PROFILE=0;
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam MBYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam BYTE_SELECT_BITS=$clog2(WIDTH_BYTES);
localparam MAXBURSTCOUNT=2**(BURSTCOUNT_WIDTH-1);
localparam CACHESIZE=ACL_BUFFER_ALIGNMENT/MWIDTH_BYTES > 1 ? ACL_BUFFER_ALIGNMENT : MWIDTH_BYTES*2 ;
localparam FIFO_DEPTH= CACHESIZE/MWIDTH_BYTES;
localparam FIFO_DEPTH_LOG2=$clog2(FIFO_DEPTH);
localparam CACHE_ADDRBITS=MBYTE_SELECT_BITS+FIFO_DEPTH_LOG2;
localparam N=( (REQUESTED_SIZE+CACHESIZE-1) / CACHESIZE) ;
localparam LOG2N=$clog2(N);
localparam LOG2N_P=(LOG2N == 0)? 1 : LOG2N;
/********
* Ports *
********/
// Standard globals
input clk;
input reset;
input flush;
// Upstream pipeline interface
output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;
// Downstream pipeline interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
// ACL PROFILE
output req_cache_hit_count;
/***************
* Architecture *
***************/
wire stall_out;
wire prefetch_new_block;
reg [AWIDTH-1:0] reg_i_address;
reg reg_i_valid;
reg reg_i_nop;
reg [N-1:0] cache_valid;
wire cache_available;
reg cache_available_d1;
wire [MWIDTH-1:0] cache_data;
wire [WIDTH-1:0] extracted_cache_data;
wire [LOG2N_P-1:0] in_cache, in_cache_unreg;
generate
if(N==1) begin : GEN_N_IS_1
assign in_cache = 1'b0;
assign in_cache_unreg = 1'b0;
end
else begin : GEN_N_GREATER_THAN_1
assign in_cache = reg_i_address[CACHE_ADDRBITS+LOG2N-1:CACHE_ADDRBITS];
assign in_cache_unreg = i_address[CACHE_ADDRBITS+LOG2N-1:CACHE_ADDRBITS];
end
if(ACL_PROFILE) begin: GEN_ACL_PROFILE
reg R_thread_valid;
assign req_cache_hit_count = R_thread_valid && cache_valid[in_cache];
always@(posedge clk) begin
R_thread_valid <= i_valid & !i_nop & !stall_out;
end
end
endgenerate
assign o_stall = stall_out;
assign prefetch_new_block = reg_i_valid && !reg_i_nop && !cache_valid[in_cache];
wire stall_out_from_output_reg;
assign stall_out = reg_i_valid && !reg_i_nop && (prefetch_new_block || !cache_available || !cache_available_d1) || reg_i_valid && stall_out_from_output_reg;
reg output_reg_valid;
reg [WIDTH-1:0] output_reg;
assign stall_out_from_output_reg = output_reg_valid && i_stall;
integer i;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
cache_valid <= {N{1'b0}};
reg_i_address <=0;
reg_i_valid <= 1'b0;
reg_i_nop <= 1'b0;
output_reg_valid <= 1'b0;
output_reg <= 0;
cache_available_d1 <= 1'b0;
end
else
begin
cache_available_d1 <= cache_available;
if (flush)
begin
cache_valid <= {N{1'b0}};
$display("Flushing Cache\n");
end
else if (prefetch_new_block)
begin
$display("%m is Prefetching a cache block for address {%x} in line%d\n", reg_i_address, in_cache);
cache_valid[in_cache] <= 1'b1;
end
if (!stall_out)
begin
reg_i_valid <= i_valid;
reg_i_address <= i_address;
reg_i_nop <= i_nop;
end
if (!stall_out_from_output_reg)
begin
output_reg <= extracted_cache_data;
output_reg_valid <= reg_i_valid && !stall_out;
end
end
end
wire prefetch_active;
lsu_prefetch_block #(
.DATAWIDTH( MWIDTH ),
.MAXBURSTCOUNT( MAXBURSTCOUNT ),
.BURSTCOUNTWIDTH( BURSTCOUNT_WIDTH ),
.BYTEENABLEWIDTH( MWIDTH_BYTES ),
.ADDRESSWIDTH( AWIDTH ),
.FIFODEPTH( FIFO_DEPTH ),
.FIFODEPTH_LOG2( FIFO_DEPTH_LOG2 ),
.FIFOUSEMEMORY( 1 ),
.N(N),
.LOG2N(LOG2N)
) read_master (
.clk(clk),
.reset(reset),
.o_active(prefetch_active),
.control_fixed_location( 1'b0 ),
.control_read_base( {reg_i_address[AWIDTH-1:CACHE_ADDRBITS],{CACHE_ADDRBITS{1'b0}}} ),
.control_read_length( CACHESIZE ),
.control_go( prefetch_new_block ),
.cache_line_to_write_to( in_cache ),
.control_done(),
.control_early_done(),
.cache_line_to_read_from( in_cache_unreg ),
.user_buffer_address( i_address[MBYTE_SELECT_BITS+FIFO_DEPTH_LOG2-1:MBYTE_SELECT_BITS] ),
.user_buffer_data( cache_data ),
.user_data_available( cache_available ),
.read_reg_enable(~stall_out),
.master_address( avm_address ),
.master_read( avm_read ),
.master_byteenable( avm_byteenable ),
.master_readdata( avm_readdata ),
.master_readdatavalid( avm_readdatavalid ),
.master_burstcount( avm_burstcount ),
.master_waitrequest( avm_waitrequest )
);
// Our RAM holds cache lines in chunks of MWIDTH (256 bits) so we need
// to extract the relevant bits with a mux for the user data
//
generate
if(MBYTE_SELECT_BITS != BYTE_SELECT_BITS)
begin
assign extracted_cache_data = cache_data[reg_i_address[MBYTE_SELECT_BITS-1:BYTE_SELECT_BITS] * WIDTH +: WIDTH];
end
else
begin
assign extracted_cache_data = cache_data;
end
endgenerate
assign o_readdata = output_reg;
assign o_valid = output_reg_valid;
assign o_active = reg_i_valid | prefetch_active;
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Thu Mar 31 18:01:07 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(AXI_En,
En,
FrameSize,
M_AXIS_tdata,
M_AXIS_tlast,
M_AXIS_tready,
M_AXIS_tstrb,
M_AXIS_tvalid,
S_AXIS_tdata,
S_AXIS_tlast,
S_AXIS_tready,
S_AXIS_tstrb,
S_AXIS_tvalid,
m_axis_aclk,
m_axis_aresetn);
input AXI_En;
input En;
input [7:0]FrameSize;
output [31:0]M_AXIS_tdata;
output M_AXIS_tlast;
input M_AXIS_tready;
output [3:0]M_AXIS_tstrb;
output M_AXIS_tvalid;
input [31:0]S_AXIS_tdata;
input S_AXIS_tlast;
output S_AXIS_tready;
input [3:0]S_AXIS_tstrb;
input S_AXIS_tvalid;
input m_axis_aclk;
input m_axis_aresetn;
wire AXI_En;
wire En;
wire [7:0]FrameSize;
wire [31:0]M_AXIS_tdata;
wire M_AXIS_tlast;
wire M_AXIS_tready;
wire [3:0]M_AXIS_tstrb;
wire M_AXIS_tvalid;
wire [31:0]S_AXIS_tdata;
wire S_AXIS_tlast;
wire S_AXIS_tready;
wire [3:0]S_AXIS_tstrb;
wire S_AXIS_tvalid;
wire m_axis_aclk;
wire m_axis_aresetn;
design_1 design_1_i
(.AXI_En(AXI_En),
.En(En),
.FrameSize(FrameSize),
.M_AXIS_tdata(M_AXIS_tdata),
.M_AXIS_tlast(M_AXIS_tlast),
.M_AXIS_tready(M_AXIS_tready),
.M_AXIS_tstrb(M_AXIS_tstrb),
.M_AXIS_tvalid(M_AXIS_tvalid),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tstrb(S_AXIS_tstrb),
.S_AXIS_tvalid(S_AXIS_tvalid),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn));
endmodule
|
module DCM_BUFG (input I, input RST_N, output O);
wire CLKFB_IN;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
wire RST_P;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign RST_P = !RST_N;
assign O = CLKFB_IN;
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(I),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_P),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
defparam DCM_ADV_INST.CLK_FEEDBACK = "1X";
defparam DCM_ADV_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_ADV_INST.CLKFX_DIVIDE = 1;
defparam DCM_ADV_INST.CLKFX_MULTIPLY = 4;
defparam DCM_ADV_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_ADV_INST.CLKIN_PERIOD = 8.000;
defparam DCM_ADV_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_ADV_INST.DCM_AUTOCALIBRATION = "TRUE";
defparam DCM_ADV_INST.DCM_PERFORMANCE_MODE = "MAX_SPEED";
defparam DCM_ADV_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_ADV_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_ADV_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_ADV_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_ADV_INST.FACTORY_JF = 16'hF0F0;
defparam DCM_ADV_INST.PHASE_SHIFT = 0;
defparam DCM_ADV_INST.STARTUP_WAIT = "FALSE";
defparam DCM_ADV_INST.SIM_DEVICE = "VIRTEX5";
endmodule
|
#include <iostream> #include <algorithm> #include <vector> #include <utility> using namespace std; int main() { int task; cin>>task; while(task--) { int n; cin>>n; int a[n]; int ans=n+n-1; for(int i=0;i<n;i++) { cin>>a[i]; if(i>=2) { if(a[i-1]>a[i]&&a[i-1]>a[i-2]) ans++; else if(a[i-1]<a[i]&&a[i-1]<a[i-2]) ans++; } } //cout<<ans<<endl; for(int i=0;i<n-3;i++) { if(a[i+1]>a[i]&&a[i+1]>a[i+3]&&a[i+2]<a[i]&&a[i+2]<a[i+3]) ans++; else if(a[i+1]<a[i]&&a[i+1]<a[i+3]&&a[i+2]>a[i]&&a[i+2]>a[i+3]) ans++; } cout<<ans<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, i, ans, a[1001]; int main() { cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 2; i < n; i++) if ((a[i] > a[i - 1] && a[i] > a[i + 1]) || (a[i] < a[i - 1] && a[i] < a[i + 1])) ans++; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int cnt[5]; int main() { int n, t; cin >> n; memset(cnt, 0, sizeof(0)); for (int i = 0; i < n; i++) { cin >> t; cnt[t]++; } bool flag = true; int ret = 0; int minN = min(cnt[1], cnt[2]); cnt[3] += minN; cnt[1] -= minN; cnt[2] -= minN; ret += minN; if (cnt[1] != 0) { while (cnt[1] >= 3) { cnt[3]++; ret += 2; cnt[1] -= 3; } if (cnt[1] == 1) { if (cnt[3] > 0) { cnt[4] + 1; cnt[3]--; cnt[1] = 0; ret += 1; } else if (cnt[4] >= 2) { cnt[4] -= 2; cnt[3] += 3; cnt[1] = 0; ret += 2; } else flag = false; } else if (cnt[1] == 2) { if (cnt[4] > 0) { cnt[4] -= 1; cnt[3] += 2; ret += 2; cnt[1] = 0; } else if (cnt[3] >= 2) { cnt[3] -= 2; cnt[4] += 2; cnt[1] = 0; ret += 2; } else flag = false; } } else { while (cnt[2] >= 3) { cnt[2] -= 3; ret += 2; cnt[3] += 2; } if (cnt[2] == 1) { if (cnt[4] > 0) { cnt[4]--; cnt[3] += 1; cnt[2] = 0; ret++; } else if (cnt[3] > 1) { cnt[4] += 2; cnt[3] -= 2; cnt[2] = 0; ret += 2; } else flag = false; } else if (cnt[2] == 2) { cnt[2] = 0; cnt[4]++; ret += 2; } } if (flag) cout << ret << endl; else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long a, b; cin >> a >> b; if (b / 2 >= a) cout << (b % (b / 2 + 1)); else cout << b % a; cout << n ; return; } signed main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); srand(time(NULL)); long long t = 1; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, m, k, i, j, v, bor[100005][27], a[100005], b[100005]; string s; void dfs(int v) { int q = 0; int u = 0; int t = 0; for (int i = 1; i < 27; i++) { if (bor[v][i] > 0) { q = 1; dfs(bor[v][i]); if (a[bor[v][i]] == 0) u = 1; if (b[bor[v][i]] == 0) t = 1; } } if (q == 0) { a[v] = 0; b[v] = 1; } if (u == 1) a[v] = 1; if (t == 1) b[v] = 1; } int main() { cin >> n >> m; k = 1; for (i = 1; i <= n; i++) { cin >> s; v = 1; for (j = 0; j < s.length(); j++) { int to = s[j] - 96; if (bor[v][to] > 0) v = bor[v][to]; else { k++; bor[v][to] = k; v = k; } } } dfs(1); if (a[1] == 1 && b[1] == 1) cout << First ; else if (a[1] == 1 && b[1] == 0 && (m % 2 == 1)) cout << First ; else cout << Second ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<int> vec(n + 1, 0); vector<pair<int, pair<int, int>>> arr; for (int i = 0; i < m; i++) { int si, di, ci; scanf( %d %d %d , &si, &di, &ci); arr.push_back(make_pair(di, make_pair(si, ci))); } bool is_possible = true; for (int i = 1; i <= n; i++) { bool exam_time = false; for (int j = 0; j < m; j++) { if (arr[j].first == i) { exam_time = true; if (arr[j].second.second != 0) { is_possible = false; } else { vec[i] = m + 1; } break; } } if (exam_time) continue; int best = -1, mini = (int)1e9; for (int j = 0; j < m; j++) { if (arr[j].first > i && arr[j].second.first <= i && arr[j].second.second != 0) { if (arr[j].first < mini) { mini = arr[j].first; best = j; } } } if (best != -1) { vec[i] = best + 1; arr[best].second.second--; } } if (is_possible) { for (int i = 1; i <= n; i++) { printf( %d , vec[i]); } } else { printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int a, b, c, d; cin >> a >> b >> c >> d; if (a * d < c * b) { int g = gcd(b * c - a * d, b * c); cout << ((b * c - a * d) / g) << / << (b * c / g) << endl; } else { int g = gcd(a * d - b * c, a * d); cout << ((a * d - b * c) / g) << / << (a * d / g) << endl; } return 0; }
|
(* CHAPTER VI: SIMILARITY OF RELATIONS *)
Require Export Chap5.
Definition heterogeneous_relation {X} {Y} := X -> Y -> Prop.
(* The relation in stdlib is what we called 'homogeneous relation',
because the domain and the converse domain has the same logic type. *)
Definition homogenenous_relation {X} := X -> X -> Prop.
Definition homogenenous_relation' := relation.
Definition field {X} (R : relation X) (x : X) := domain R x \/ converse_domain R x.
(* We may define two relations P and Q as “similar,” or as having
“likeness,” when
there is a (1)one-one relation S
(2)whose domain is the field of P and
(3)whose converse domain is the field of Q
, and which is such that,
(4)if one term(a) has the relation P to another(b), the correlate of
the one(S a) has the relation Q to the correlate of the other(S b), and
(* forall a b, P a b -> Q (S a) (S b) *)
(5)vice versa.
(* forall a b, Q (S a) (S b) -> P a b *)
*)
Inductive similar {X} (P : relation X) (Q : relation X) : Prop :=
| similar_intro : (exists S : relation X,
one_one S /\
(forall x, field P x <-> domain S x) /\
(forall x, field Q x <-> converse_domain S x) /\
(forall x y z w, P x y -> S x z -> S y w -> Q z w) /\
(forall x y z w, Q z w -> S x z -> S y w -> P x y)) ->
similar P Q.
(* This theorem is not mentioned on the book but I want to prove it *)
Theorem one_one_converse_one_one :
forall {X} (P : relation X), one_one P ->
one_one (converse P).
Proof.
intros.
inversion H. unfold many_one in H0. unfold one_many in H1.
unfold one_one. unfold many_one. unfold one_many.
split; intros; inversion H2; inversion H3; subst.
apply H1 with y x y' in H4; assumption.
apply H0 with y x x' in H7; assumption.
Qed.
(*
A relation S is said to be a “correlator” or an “ordinal correlator”
of two relations P and Q if S is one-one, has the field of Q for its
converse domain, and is such that P is the relative product of S and Q
and the converse of S.
*)
Inductive correlator {X} (P Q : relation X) : relation X -> Prop :=
| correlator_intro :
forall (S : relation X),
one_one S ->
(forall x, field P x <-> domain S x) ->
(forall x, field Q x <-> converse_domain S x) ->
(forall x y, relative_product (relative_product S Q) (converse S) x y -> P x y) ->
correlator P Q S.
(* Two relations P and Q are said to be “similar,” or to have
“likeness,” when there is at least one correlator of P and Q.
*)
Inductive similar' {X} (P Q : relation X) : Prop :=
| similar'_intro : (exists S, correlator P Q S) -> similar' P Q.
(* NOTE: this defintion is taken from Russel's book
Principles of Mathematics rather than Introduction to Mathematical Philosophy
===============================================================================
Two relations P, Q are like when there is a one-one relation S such
that the domain of S is the field of P, and Q = S̆PS.
** I don't know about this notation 'S̆PS', but I guess
it's the relative product of the converse of S, P, and S.
*)
(* Proving these two definition are equivalent *)
Theorem similar_eqv1 :
forall {X} (P Q : relation X), similar P Q -> similar' P Q.
Proof.
intros.
inversion H as [HS].
inversion HS as [S SProps].
inversion SProps as [HS11 SProps'].
inversion SProps' as [HSdomain SProps''].
inversion SProps'' as [HScdomain SProps'''].
inversion SProps''' as [HSPQ HSQP].
clear SProps SProps' SProps'' SProps''' HS.
constructor. exists S.
constructor; try assumption.
(*
Inductive relative_product
{X} (R: relation X) (S: relation X) : relation X :=
| rp0 : forall x y, forall z, R x y -> S y z -> relative_product R S x z.
*)
intros x y Himp.
inversion Himp.
inversion H0.
inversion H1.
subst.
rename y1 into z.
rename y0 into w.
clear H0 H1.
specialize HSPQ with x y z w.
specialize HSQP with x y z w.
apply HSQP; assumption.
Qed.
Theorem similar_eqv2 :
forall {X} (P Q : relation X), similar' P Q -> similar P Q.
Proof.
intros.
inversion H as [HExCorrelator].
inversion HExCorrelator as [S Hcorrelator]. clear HExCorrelator.
inversion Hcorrelator as [S' HS11 HSdomain HScodomain HSrp]. subst. clear Hcorrelator.
constructor. exists S.
repeat (split; try assumption; try intros; try specialize HSrp with x y);
try (apply HSrp; apply rp0 with w; [ apply rp0 with z; assumption |
apply cv0; assumption ]).
rename H0 into HP.
rename H1 into HSx.
rename H2 into HSy.
pose proof HScodomain as HScodomain'.
specialize HScodomain with z.
specialize HScodomain' with w.
inversion HScodomain.
inversion HScodomain'.
clear H0 H2.
assert (Qz : converse_domain S z).
apply converse_domain_intro with x. assumption.
assert (Qw : converse_domain S w).
apply converse_domain_intro with y. assumption.
apply H1 in Qz.
apply H3 in Qw.
(*
assert (relative_product (relative_product S Q) (converse S) x y).
apply rp0 with w; try apply cv0; try assumption.
apply rp0 with z; try assumption.
*)
(*
TODO: Sorry for my insufficient intelligence. I couldn't solve this :(
*)
admit.
Qed.
(* This thorem does not always hold *)
Theorem prop_similar :
forall {X} (R S : relation X) (P : relation X -> Prop),
similar R S -> P R -> P S.
Proof.
intros.
inversion H.
inversion H1.
inversion H2.
inversion H4.
inversion H6.
inversion H8.
inversion H3.
unfold many_one in H11.
unfold one_many in H12.
clear H1 H2 H3 H4 H6 H8.
unfold relation in x.
unfold relation in P.
(*
TODO: Sorry again for my insufficient intelligence.
*)
admit.
(*
UPDATE: This theorem doesn't always hold!!
A counterexample:
* P : fun R x => R x 1.
* R : fun x y => y = 1.
* S : fun z w => w = 2.
* T : fun x z => z = x + 1.
=> R S are similar, because T is one-one, and TST^-1 -> P.
=> P R holds, but P S does not hold.
Qed.
*)
Qed.
(* Let me just prove something specific~ *)
Theorem aliorelative_similar :
forall {X} (R S : relation X),
similar R S -> aliorelative R -> aliorelative S.
Proof.
intros.
inversion H.
unfold aliorelative in H0.
inversion H1. inversion H2. inversion H4. inversion H6. inversion H8.
clear H1 H2 H4 H6 H8.
unfold aliorelative.
intro.
rename x into T.
rename x0 into a.
inversion H3.
unfold many_one in H1.
unfold one_many in H2.
assert (x : X). intuition.
specialize H0 with x.
specialize H1 with x a a.
specialize H2 with x a a.
assert (T x a).
specialize H5 with x.
inversion H5.
unfold field in H4.
(* I'm just an idiot.. ignore me. *)
admit. admit.
(*
apply H10 with x x a a in H4.
apply H0 in H4. contradiction.
intro.
*)
Qed.
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; vector<vector<int>> v; vector<int> cur; if ((n * m) % k == 0) { int div = (n * m) / k; for (int i = 0; i < n; i++) { if (!(i & 1)) { for (int j = 0; j < m; j++) { cur.push_back(i + 1); cur.push_back(j + 1); if (cur.size() >= div * 2) { vector<int> add = cur; v.push_back(add); cur.clear(); } } } else { for (int j = m - 1; j >= 0; j--) { if (cur.size() <= div * 2) { cur.push_back(i + 1); cur.push_back(j + 1); } if (cur.size() >= div * 2) { vector<int> add = cur; v.push_back(add); cur.clear(); } } } } } else { int div = ((n * m) - 2) / (k - 1); int count = 0; int flag = 0; for (int i = 0; i < n; i++) { if (!(i & 1)) { for (int j = 0; j < m; j++) { if (count == k - 1 && flag == 0) { div = (n * m - (k - 1) * (div)); flag = 1; } cur.push_back(i + 1); cur.push_back(j + 1); if (cur.size() >= div * 2) { vector<int> add = cur; v.push_back(add); cur.clear(); count++; } } } else { for (int j = m - 1; j >= 0; j--) { if (count == k - 1 && flag == 0) { div = (n * m - (k - 1) * (div)); flag = 1; } if (cur.size() <= div * 2) { cur.push_back(i + 1); cur.push_back(j + 1); } if (cur.size() >= div * 2) { vector<int> add = cur; v.push_back(add); cur.clear(); count++; } } } } } for (int i = 0; i < v.size(); i++) { int s = v[i].size(); s /= 2; cout << s << ; for (int j = 0; j < v[i].size(); j++) { cout << v[i][j] << ; } cout << endl; } return 0; }
|
// Register File module
`timescale 1ns / 1ps
module regfile (
clk,
rst,
wen,
//lhb_llb_sec_control,
//jr_rf,
//jr_raddr,
//jal_write_reg,
//jal_pc_val,
raddr1,
raddr2,
waddr,
wdata,
rdata1,
rdata2
);
parameter DSIZE=16;
parameter NREG=16;
localparam RSIZE=4;
input clk;
input rst;
input wen;
//input lhb_llb_sec_control;
//input jr_rf;
//input jal_write_reg;
//input [DSIZE-1:0] jal_pc_val;
//input [RSIZE-1:0] jr_raddr;
input [RSIZE-1:0] raddr1;
input [RSIZE-1:0] raddr2;
input [RSIZE-1:0] waddr;
input [DSIZE-1:0] wdata;
output [DSIZE-1:0] rdata1;
output [DSIZE-1:0] rdata2;
reg [DSIZE-1:0] regdata [0:NREG-1];
reg wen_temp;
// assign RData2 = RegFile[RAddr2];
//assign wen = wen_temp;
always@(posedge clk)
begin
if(rst)
begin
//wen_temp <= 0;
regdata[0] <=0;
regdata[1] <=0;
regdata[2] <=0;
regdata[3] <=0;
regdata[4] <=0;
regdata[5] <=0;
regdata[6] <=0;
regdata[7] <=0;
regdata[8] <=0;
regdata[9] <=0;
regdata[10] <=0;
regdata[11] <=0;
regdata[12] <=0;
regdata[13] <=0;
regdata[14] <=0;
regdata[15] <=0;
end
/*else if(jal_write_reg == 1)
regdata[15] = jal_pc_val;*/
else
regdata[waddr] <= ((wen == 1) && (waddr != 0)) ? wdata : regdata[waddr];
end
//assign rdata1 = jr_rf? regdata[jr_raddr]:(((wen) && (waddr == raddr1) && (waddr != 0)) ? wdata : regdata[raddr1]);
//added support for load immediate, new control added
//assign rdata2 = (lhb_llb_sec_control)?(regdata[waddr]) :(((wen) && (waddr == raddr2) && (waddr != 0)) ? wdata : regdata[raddr2]);
assign rdata1 = ((wen===1) && (waddr == raddr1) && (waddr != 0))? wdata : regdata[raddr1];
assign rdata2 = ((wen===1) && (waddr == raddr2) && (waddr != 0)) ? wdata : regdata[raddr2];
endmodule
|
module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
wire rst = ~rst_n;
wire fclk;
wire pllLock;
wire pllFeedbackClk;
PLL_BASE#(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.0),
.CLKIN_PERIOD ("20"),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_PHASE (0.0),
.CLK_FEEDBACK ("CLKFBOUT"),
//.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
PLL_BASE_inst(
.CLKFBOUT (pllFeedbackClk),
.CLKOUT0 (fclk),
.LOCKED (pllLock),
.CLKFBIN (pllFeedbackClk),
.CLKIN (clk),
.RST (rst)
);
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
wire [22:0] addr;
wire rw;
wire [31:0] data_in, data_out;
wire busy;
wire in_valid, out_valid;
//sdram_clk_gen clkram_clk_gen (
// .clk_in(clk),
// .clk_out(fclk)
// );
sdram sdram (
.clk(fclk),
.rst(rst),
.sdram_clk(sdram_clk),
.sdram_cle(sdram_cle),
.sdram_cs(sdram_cs),
.sdram_cas(sdram_cas),
.sdram_ras(sdram_ras),
.sdram_we(sdram_we),
.sdram_dqm(sdram_dqm),
.sdram_ba(sdram_ba),
.sdram_a(sdram_a),
.sdram_dq(sdram_dq),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid)
);
ram_test ram_test (
.clk(fclk),
.rst(rst),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid),
.leds(led)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int dat[100000 + 10]; int vis[100000 + 10]; int dfs(int x) { vis[x] = 1; if (vis[dat[x]] == 0) return dfs(dat[x]) + 1; return 1; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> dat[i + 1]; } vector<long long> g; for (int i = 1; i <= n; i++) { if (vis[i] == 0) { g.push_back(dfs(i)); } } sort(g.begin(), g.end()); reverse(g.begin(), g.end()); if (g.size() == 0) { cout << 0 << endl; } else if (g.size() == 1) { cout << g[0] * g[0] << endl; } else { long long total = (g[0] + g[1]) * (g[0] + g[1]); for (int i = 2; i < g.size(); i++) { total += g[i] * g[i]; } cout << total << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18, N = 1e6, mod = 1e9 + 7; const long double PI = acos(-1), eps = -1e9; inline void read(long long &a) { char c; bool neg = 0; c = getchar(); a = 0; if (c == - ) { neg = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { a = (a << 3) + (a << 1) + (c - 0 ); c = getchar(); } if (neg) a *= -1; } long long a[N]; void solve() { long long n; read(n); long long sum = 0, cur = 0; for (long long i = 1; i <= n; i++) { long long x; read(x); if (a[x] != 0) { cur -= a[x]; } a[x] = i; cur += a[x]; sum += cur; } sum -= n; sum *= 2; sum += n; cout << setprecision(20) << (long double)sum / ((long double)n * n); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv5sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
|
#include <bits/stdc++.h> using namespace std; void er() { cout << NO << endl; exit(0); } int main() { int n; cin >> n; int a[n + 1]; int o = 0; int um = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] != 0) o++; um = um + a[i]; } if (o < 1) er(); if (um != 0) { cout << YES << endl; cout << 1 << endl; cout << 1 << << n << endl; return 0; } cout << YES << endl; cout << 2 << endl; for (int i = 1; i <= n; i++) { if (a[i] != 0) { cout << 1 << << i << endl; cout << i + 1 << << n << endl; break; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_4_V
`define SKY130_FD_SC_MS__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_4_V
|
#include <bits/stdc++.h> void dfs(int64_t node, int64_t from, const std::vector<std::vector<int64_t> > &g, std::vector<bool> &visited, int64_t &count, bool &cycle, bool &self) { if (visited[node]) { return; } visited[node] = 1; ++count; for (int64_t p = 0; p < g[node].size(); p++) { int64_t u = g[node][p]; if (u == from) { continue; } else if (u == node) { self = true; } else if (visited[u]) { cycle = true; } else { dfs(u, node, g, visited, count, cycle, self); } } return; } int main() { const int64_t MOD = 1000000007; int64_t n; scanf( %lld , &n); std::vector<std::vector<int64_t> > g(2 * n); for (int64_t p = 0; p < n; p++) { int64_t x, y; scanf( %lld %lld , &x, &y); --x; --y; g[x].push_back(y); g[y].push_back(x); } std::vector<bool> visited(2 * n, false); int64_t total(1); for (int64_t p = 0; p < 2 * n; p++) { if (visited[p]) { continue; } int64_t count(0); bool cycle(false), self(false); dfs(p, -1, g, visited, count, cycle, self); if (self) { count = 1; } else if (cycle) { count = 2; } total *= count; total %= MOD; } printf( %lld n , total); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_TB_V
`define SKY130_FD_SC_HD__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = int(500 * 1000 + 7); long long n, k; vector<pair<long long, long long> > adj[N]; long long dp[N][2]; void dfs(int v, int p = -1) { vector<long long> x; long long curr = 0; for (auto it : adj[v]) { long long to = it.first; long long w = it.second; if (to == p) continue; dfs(to, v); curr += dp[to][0]; x.push_back(dp[to][1] + w - dp[to][0]); } sort(x.begin(), x.end(), greater<long long>()); for (long long i = 0; i < min((long long)x.size(), k); i++) { if (x[i] > 0) curr += x[i]; } dp[v][0] = dp[v][1] = curr; if (k <= (long long)x.size() && x[k - 1] > 0) dp[v][1] -= x[k - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long q; cin >> q; while (q--) { cin >> n >> k; for (long long i = 0; i < n; i++) adj[i].clear(); for (long long i = 0; i < n - 1; i++) { long long u, v, w; cin >> u >> v >> w; u--; v--; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } dfs(0, -1); cout << dp[0][0] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[51][51]; long long combinatorics(long long n, long long k) { double res = 1; for (long long i = 1; i <= k; ++i) res = res * (n - k + i) / i; return (long long)(res + 0.01); } int main() { long long n, m, i, j, numOneRow[51] = {0}, numZeroRow[51] = {0}, numOneColumn[51] = {0}, numZeroColumn[51] = {0}, x, y; long long c; cin >> n >> m; c = m * n; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == 0) { numZeroRow[i]++, numZeroColumn[j]++; } else { numOneRow[i]++, numOneColumn[j]++; } } } for (i = 0; i < n; i++) { j = 2; x = numOneRow[i], y = numZeroRow[i]; while (x >= j) { c += combinatorics(x, j); j++; } j = 2; while (y >= j) { c += combinatorics(y, j); j++; } } for (j = 0; j < m; j++) { i = 2; x = numOneColumn[j], y = numZeroColumn[j]; while (x >= i) { c += combinatorics(x, i); i++; } i = 2; while (y >= i) { c += combinatorics(y, i); i++; } } cout << c << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; inline void rd(int &x) { int k; int m = 0; x = 0; for (;;) { k = getchar(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { k = getchar(); if (k < 0 || k > 9 ) { break; } x = x * 10 + k - 0 ; } if (m) { x = -x; } } inline void rd(char &c) { int i; for (;;) { i = getchar(); if (i != && i != n && i != r && i != t && i != EOF) { break; } } c = i; } inline int rd(char c[]) { int i; int sz = 0; for (;;) { i = getchar(); if (i != && i != n && i != r && i != t && i != EOF) { break; } } c[sz++] = i; for (;;) { i = getchar(); if (i == || i == n || i == r || i == t || i == EOF) { break; } c[sz++] = i; } c[sz] = 0 ; return sz; } inline void wt_L(char a) { putchar(a); } inline void wt_L(int x) { int s = 0; int m = 0; char f[10]; if (x < 0) { m = 1; x = -x; } while (x) { f[s++] = x % 10; x /= 10; } if (!s) { f[s++] = 0; } if (m) { putchar( - ); } while (s--) { putchar(f[s] + 0 ); } } template <class S, class T> inline S chmin(S &a, T b) { if (a > b) { a = b; } return a; } int N; char S[300002]; int sz; int lis[300002]; int main() { int i, m; int k; int mn; int y; int f; int cnt; int res; int res1; int res2; int ini; rd(N); rd(S); k = mn = 0; for (i = (0); i < (N); i++) { if (S[i] == ( ) { k++; } else { k--; } chmin(mn, k); } if (k) { wt_L(0); wt_L( n ); wt_L(1); wt_L( ); wt_L(1); wt_L( n ); return 0; } k = 0; res = res1 = res2 = 0; for (i = (0); i < (N); i++) { if (S[i] == ( ) { k++; } else { k--; } if (k == mn) { res++; lis[sz++] = i; } } ini = res; for (m = (0); m < (sz); m++) { k = 0; if (m == sz - 1) { y = lis[0] + N; } else { y = lis[m + 1]; } f = -1; for (i = (lis[m] + 1); i < (y); i++) { if (S[i % N] == ( ) { k++; } else { k--; } if (k < 2) { f = -1; cnt = 0; } if (k == 2 && f == -1) { f = i; } if (k == 2) { cnt++; } if (k == 2 && ini + cnt > res) { res = ini + cnt; res1 = f % N; res2 = (i + 1) % N; } } } for (m = (0); m < (sz); m++) { k = 0; if (m == sz - 1) { y = lis[0] + N; } else { y = lis[m + 1]; } cnt = 0; for (i = (lis[m] + 1); i < (y); i++) { if (S[i % N] == ( ) { k++; } else { k--; } if (k == 1) { cnt++; } } if (cnt > res) { res = cnt; res1 = (lis[m] + 1) % N; res2 = y % N; } } wt_L(res); wt_L( n ); wt_L(res1 + 1); wt_L( ); wt_L(res2 + 1); wt_L( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> di[100003]; struct trie { trie *zero, *one; int val; trie() { zero = one = NULL; val = 100003; } } * root[100003]; void add(trie *cur, int a) { int i, ck; for (i = 20; i >= 0; i--) { ck = (1 << i & a); if (ck == 0) { cur->val = min(cur->val, a); if (cur->zero == NULL) cur->zero = new trie(); cur = cur->zero; cur->val = min(cur->val, a); } else { cur->val = min(cur->val, a); if (cur->one == NULL) cur->one = new trie(); cur = cur->one; cur->val = min(cur->val, a); } } } int query(trie *cur, int a, int lim) { int i, ck, ans; for (i = 20; i >= 0; i--) { ck = (1 << i & a); if (ck == 0) { if (cur->one != NULL && cur->one->val + a <= lim) cur = cur->one; else if (cur->zero != NULL) cur = cur->zero; ans = cur->val; } else { if (cur->zero != NULL && cur->zero->val + a <= lim) cur = cur->zero; else if (cur->one != NULL) cur = cur->one; ans = cur->val; } } return ans; } void pre() { for (int i = 1; i < 100003; i++) { for (int j = i; j < 100003; j += i) di[j].push_back(i); root[i] = new trie(); } } int main() { pre(); int q, a, k, s, v, ty; scanf( %d , &q); while (q--) { scanf( %d , &ty); if (ty == 1) { scanf( %d , &a); for (int x : di[a]) { add(root[x], a); } } else { scanf( %d %d %d , &v, &k, &s); if (root[k]->val + v > s || root[k]->val == 0 || v % k) printf( -1 n ); else printf( %d n , query(root[k], v, s)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[101]; bool f = 1; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) f = 0; } if (f) puts( EASY ); else puts( HARD ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O211A_FUNCTIONAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_FUNCTIONAL_PP_V
|
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