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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int main() { string s; cin >> s; map<int, int> cnt; for (int i = 0; i < s.size(); ++i) { cnt[s[i] - 0 ]++; } cnt[1]--; cnt[6]--; cnt[8]--; cnt[9]--; string ans = ; for (int i = 1; i <= 9; ++i) { for (int j = 0; j < cnt[i]; ++j) ans += (char)( 0 + i); } int powr = 1; int su = 0; for (int i = 0; i < ans.size(); ++i) { su = su * 10 + (ans[i] - 0 ); su %= 7; } vector<int> perm = {1, 6, 8, 9}; do { int n = su * 10000 + perm[0] * 1000 + perm[1] * 100 + perm[2] * 10 + perm[3]; if (n % 7 == 0) { cout << ans; for (int x : perm) cout << x; for (int i = 0; i < cnt[0]; ++i) cout << 0; return 0; } } while (next_permutation(perm.begin(), perm.end())); return 0; }
|
`timescale 1ns / 1ps
//this code was generated by cReComp
module sensor_ctl(
input [0:0] clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
input [0:0] SPI_DI_a,
output [0:0] SPI_SS_a,
output [0:0] SPI_CK_a,
output [0:0] SPI_DO_a
);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32_x = 5,
SND_DATA_32_y = 6,
SND_DATA_32_z = 7;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
reg [15:0] accel_x_reg;
reg [15:0] accel_y_reg;
reg [15:0] accel_z_reg;
wire arm_rd_en_a;
////fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
//MPU_gyro_controller MPU_gyro_controller(
// .clk(clk),
// .reset(rst_32),
//
// .gyro_x(gyro_x),
// .gyro_y(gyro_y),
// .gyro_z(gyro_z),
//
// .SPI_SS_g(SPI_SS_g), //Sleve select
// .SPI_CK_g(SPI_CK_g), //SCLK
// .SPI_DO_g(SPI_DO_g), //Master out Sleve in
// .SPI_DI_g(SPI_DI_g), //Master in Slave out
//
// .arm_read_enable_g(arm_rd_en_g) //finish sensing accel_xyz
//);
MPU_accel_controller MPU_accel_controller(
.clk(clk),
.reset(rst_32),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.SPI_SS_a(SPI_SS_a), //Sleve select
.SPI_CK_a(SPI_CK_a), //SCLK
.SPI_DO_a(SPI_DO_a), //Master out Sleve in
.SPI_DI_a(SPI_DI_a), //Master in Slave out
.arm_read_enable_a(arm_rd_en_a) //finish sensing accel_xyz
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(1) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: if(arm_rd_en_a) state_32 <= READY_SND_32;
// POSE_32: if(1) state_32 <= READY_SND_32;
READY_SND_32: if(data_full_32 == 0) state_32 <= SND_DATA_32_x;
// READY_SND_32: if(1) state_32 <= SND_DATA_32_x;
SND_DATA_32_x: state_32 <= SND_DATA_32_y;
SND_DATA_32_y: state_32 <= SND_DATA_32_z;
SND_DATA_32_z: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 > READY_SND_32);
assign snd_data_32 = (state_32 == SND_DATA_32_x)? accel_x_reg:
(state_32 == SND_DATA_32_y)? accel_y_reg:
(state_32 == SND_DATA_32_z)? accel_z_reg:0;
always @(posedge clk) begin
if (rst_32) begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
end
else
case (state_32)
INIT_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
end
READY_RCV_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
end
POSE_32: begin
accel_x_reg <= accel_x;
accel_y_reg <= accel_y;
accel_z_reg <= accel_z;
end
endcase
end
endmodule
|
// Ken Eguro
// Alpha version - 2/11/09
// Version 1.0 - 1/4/10
// Version 1.0.1 - 5/7/10
// Version 1.1 - 8/1/11
`timescale 1ns / 1ps
`default_nettype none
module fifo36Wrapper(
input wire writeClk,
input wire [35:0] writeData,
input wire writeEnable,
output wire full,
input wire readClk,
output wire [35:0] readData,
input wire readEnable,
output wire empty,
input wire reset
);
//This is straight from the Virtex 5 HDL Design Guide
FIFO18_36 #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
.DO_REG(1), // Enable output register (0 or 1)
// Must be 1 if EN_SYN = "FALSE"
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
// or Synchronous ("TRUE")
.FIRST_WORD_FALL_THROUGH("TRUE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO18_inst (
.ALMOSTEMPTY(), // 1-bit almost empty output flag
.ALMOSTFULL(), // 1-bit almost full output flag
.DO(readData[31:0]), // 32-bit data output
.DOP(readData[35:32]), // 4-bit parity data output
.EMPTY(empty), // 1-bit empty output flag
.FULL(full), // 1-bit full output flag
.RDCOUNT(), // 9-bit read count output
.RDERR(), // 1-bit read error output
.WRCOUNT(), // 9-bit write count output
.WRERR(), // 1-bit write error
.DI(writeData[31:0]), // 32-bit data input
.DIP(writeData[35:32]), // 4-bit parity input
.RDCLK(readClk), // 1-bit read clock input
.RDEN(readEnable), // 1-bit read enable input
.RST(reset), // 1-bit reset input
.WRCLK(writeClk), // 1-bit write clock input
.WREN(writeEnable) // 1-bit write enable input
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int const bound = 2e6 + 2, N = 5e5 + 2; long long OO = 1e18; double eps = 1e-6; int oo = 1e9, mod = oo + 7; pair<int, int> can[101]; bool cmp(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a.first.first != b.first.first) return a.first.first > b.first.first; return a.first.second < b.first.second; } int main() { int n, m, k, a; cin >> n >> k >> m >> a; for (int(i) = 0; (i) < (a); (i)++) { int g; cin >> g; g--; can[g].first++; can[g].second = i; } for (int(i) = 0; (i) < (n); (i)++) { pair<pair<int, int>, int> tmp[101]; for (int(j) = 0; (j) < (n); (j)++) tmp[j] = {can[j], j}; int sv = tmp[i].first.second; tmp[i].first.first += m - a; if (m - a) tmp[i].first.second = m; sort(tmp, tmp + n, cmp); bool no = 1; for (int(j) = 0; (j) < (k); (j)++) { if (tmp[j].first.first && tmp[j].second == i) { no = 0; break; } } if (no) { cout << 3 << ; continue; } int to = -1, rem = m - a; for (int(j) = 0; (j) < (n); (j)++) if (tmp[j].second == i) { tmp[j].first.first -= m - a; tmp[j].first.second = sv; } sort(tmp, tmp + n, cmp); for (int(j) = 0; (j) < (n); (j)++) { if (to != -1) { if (rem < to - tmp[j].first.first + 1) break; rem -= to - tmp[j].first.first + 1; tmp[j].first.first += to - tmp[j].first.first + 1; tmp[j].first.second = m; } if (tmp[j].second == i) to = tmp[j].first.first; } sort(tmp, tmp + n, cmp); no = 1; for (int(j) = 0; (j) < (k); (j)++) if (tmp[j].first.first && tmp[j].second == i) no = 0; if (no) cout << 2 << ; else cout << 1 << ; } return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 15:18:53 03/06/2015
// Design Name: SAM Coupé clone
// Module Name: ps2_keyb
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_keyb(
input wire clk,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [8:0] rows,
output wire [7:0] cols,
output wire rst_out_n,
output wire nmi_out_n,
output wire mrst_out_n,
output wire [1:0] user_toggles,
//---------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire regaddr_changed,
input wire [7:0] din,
output wire [7:0] keymap_dout,
output wire oe_n_keymap,
output wire [7:0] scancode_dout,
output wire oe_n_scancode,
output reg [7:0] kbstatus_dout,
output wire oe_n_kbstatus
);
parameter SCANCODE = 8'h04;
parameter KBSTATUS = 8'h05;
parameter KEYMAP = 8'h07;
wire master_reset, user_reset, user_nmi;
assign mrst_out_n = ~master_reset;
assign rst_out_n = ~user_reset;
assign nmi_out_n = ~user_nmi;
assign oe_n_keymap = ~(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1);
assign oe_n_scancode = ~(zxuno_addr == SCANCODE && zxuno_regrd == 1'b1);
assign oe_n_kbstatus = ~(zxuno_addr == KBSTATUS && zxuno_regrd == 1'b1);
wire [7:0] kbcode;
wire ps2busy;
wire kberror;
wire nueva_tecla;
wire extended;
wire released;
assign scancode_dout = kbcode;
wire teclado_limpio;
/*
| BSY | x | x | x | ERR | RLS | EXT | PEN |
*/
reg reading_kbstatus = 1'b0;
always @(posedge clk) begin
kbstatus_dout[7:1] <= {ps2busy, 3'b000, kberror, released, extended};
if (nueva_tecla == 1'b1)
kbstatus_dout[0] <= 1'b1;
if (oe_n_kbstatus == 1'b0)
reading_kbstatus <= 1'b1;
else if (reading_kbstatus == 1'b1) begin
kbstatus_dout[0] <= 1'b0;
reading_kbstatus <= 1'b0;
end
end
ps2_port lectura_de_teclado (
.clk(clk),
.enable_rcv(~ps2busy),
.kb_or_mouse(1'b0),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(nueva_tecla),
.scancode(kbcode),
.released(released),
.extended(extended)
);
scancode_to_sam traductor (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scan(kbcode),
.extended(extended),
.released(released),
.kbclean(teclado_limpio),
.sam_row(rows),
.sam_col(cols),
.master_reset(master_reset),
.user_reset(user_reset),
.user_nmi(user_nmi),
.user_toggles(user_toggles),
.din(din),
.dout(keymap_dout),
.cpuwrite(zxuno_addr == KEYMAP && zxuno_regwr == 1'b1),
.cpuread(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1),
.rewind(regaddr_changed == 1'b1 && zxuno_addr == KEYMAP)
);
keyboard_pressed_status comprueba_teclado_limpio (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scancode(kbcode),
.extended(extended),
.released(released),
.kbclean(teclado_limpio)
);
ps2_host_to_kb escritura_a_teclado (
.clk(clk),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.data(din),
.dataload(zxuno_addr == SCANCODE && zxuno_regwr== 1'b1),
.ps2busy(ps2busy),
.ps2error(kberror)
);
endmodule
|
module microfono
(
input reset,
output ledres,
input clk,
output mclk,
output reg micLRSel,
input micData,
output ampPWM,
output ampSD,
input rd,wr,
output empty,
output full,
output reg done
);
wire [7:0] dout;
wire [7:0] dout1;
wire mclk1;
wire mclk2;
assign mclk3=mclk2;
assign mclk2=mclk1;
assign mclk=mclk1;
reg [7:0] sregt1;
reg [7:0] sregt;
fifo fi(.reset(reset),.din(sregt1),.dout(dout),.clock(done),.rd(rd),.wr(wr),.empty(empty),.full(full));
pwm pw(.ampSD(ampSD), .reset(reset),.mclk(mclk2),.ampPWM(ampPWM),.clk(clk),.dout(dout1));
div_freq df(.clk(clk), .reset(reset),.clkout(mclk1),.led(ledres));
reg [7:0] count;
assign dout1=dout;
initial micLRSel <= 0;
initial count <= 0;
initial sregt <= 0;
initial sregt1 <= 0;
always @(posedge mclk)
begin
if (reset)
begin
sregt<=0;
end
else
begin
if(count<=7)
begin
sregt<= {sregt[7:0],micData};
count<=count+1;
done<=0;
end
else
begin
count<=0;
done<=1;
sregt1<=sregt;
end
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: coffee.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module coffee (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/coffee.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/coffee.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coffee_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_TB_V
`define SKY130_FD_SC_LP__A31O_TB_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_TB_V
|
#include <bits/stdc++.h> using namespace std; int n; char a[440000], b[440000]; int cnta = 0, cntb = 0; int df[440000] = {0}; int czl[440000], czr[440000]; int zz1 = 0, zz2 = 0; int ab[440000] = {0}, ba[440000] = {0}; int ans = 0; int main() { cin >> n; cin >> a >> b; for (int i = 0; i < n; i++) { if (a[i] == a ) { cnta++; if (a[i] != b[i]) ab[++zz1] = i + 1; } if (b[i] == a ) { cntb++; if (a[i] != b[i]) ba[++zz2] = i + 1; } } if ((zz1 + zz2) % 2 == 1) { cout << -1 << endl; return 0; } while (zz1 || zz2) { if (zz2 % 2 == 1) { zz2++; ans++; czl[ans] = ab[zz1], czr[ans] = ab[zz1]; ba[zz2] = ab[zz1]; zz1--; } if (zz1) { ans++; czl[ans] = ab[zz1], czr[ans] = ab[zz1 - 1]; zz1 -= 2; } else { ans++; czl[ans] = ba[zz2], czr[ans] = ba[zz2 - 1]; zz2 -= 2; } } cout << ans << endl; for (int i = 1; i <= ans; i++) cout << czl[i] << << czr[i] << endl; return 0; }
|
`timescale 1ns/1ns
module top;
wire q;
reg a, b;
initial begin
// $dumpfile("test.lx2"); // Need to also use the -lxt2 flags on exe.
// $dumpvars(0, top);
// Initial value should be X is 1.
#1 a = 1'b1; // Should be X is 1.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1'b0; // Correct: 1.
#1 if (q !== 1'b1) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1'b1; // Should be X is 1.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1'bx; // Should be X is 1.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1'b1; // Should be X is 1.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1'bx; b = 1'b1; // Correct: X.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 b = 1'b0; // Correct: 1.
#1 if (q !== 1'b1) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 b = 1'b1; // Correct: X, but following #1 delay is missing.
#1 if (q !== 1'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
$display("PASSED");
$finish;
end
nand dut (q, a, b);
// nand dut (q, b, a); // This also produces incorrect results.
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, unsigned long long y, unsigned long long m) { if (y == 0) return 1; long long p = power(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, pi, k; cin >> n >> pi >> k; long long arr[n], x, ans = 0; map<long long, long long> m; for (long long i = 0; i < n; i++) { cin >> x; arr[i] = (power(x, 4, pi) - k * x) % pi; arr[i] += pi, arr[i] %= pi; } for (long long i = n - 1; i >= 0; i--) { ans += m[arr[i]]; m[arr[i]]++; } cout << ans; return 0; }
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_jesd_align_1 (
// jesd interface
rx_clk,
rx_sof,
rx_eof,
rx_ferr,
rx_fdata,
// aligned data
rx_err,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [ 3:0] rx_eof;
input [ 3:0] rx_ferr;
input [31:0] rx_fdata;
// aligned data
output rx_err;
output [31:0] rx_data;
reg rx_err = 'd0;
reg [31:0] rx_data = 'd0;
wire rx_err_s;
// error conditions- sof & eof are the same - 1 byte per frame!
assign rx_err_s = ((rx_sof == rx_eof) && (rx_ferr == 4'd0)) ? 1'b0 : 1'b1;
// 1 bytes per frame - so only 1 combination
always @(posedge rx_clk) begin
case (rx_sof)
4'b1111: begin
rx_err <= rx_err_s;
rx_data <= rx_fdata;
end
default: begin
rx_err <= 1'b1;
rx_data <= 32'hffff;
end
endcase
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMS32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMS32 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output O,
input ADR0,
input ADR1,
input ADR2,
input ADR3,
input ADR4,
input CLK,
input I,
input WE
);
reg [31:0] mem;
wire [4:0] ADR_dly, ADR_in;
wire I_dly, CLK_dly, WE_dly;
wire I_in, CLK_in, WE_in;
localparam MODULE_NAME = "RAMS32";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
always @(posedge CLK_in)
if (WE_in == 1'b1)
mem[ADR_in] <= #100 I_in;
assign O = mem[ADR_in];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {ADR4, ADR3, ADR2, ADR1, ADR0};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
assign WE_in = WE_dly;
assign I_in = I_dly;
assign ADR_in = ADR_dly;
specify
(ADR0 => O) = (0:0:0, 0:0:0);
(ADR1 => O) = (0:0:0, 0:0:0);
(ADR2 => O) = (0:0:0, 0:0:0);
(ADR3 => O) = (0:0:0, 0:0:0);
(ADR4 => O) = (0:0:0, 0:0:0);
(CLK => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK &&& WE, 0:0:0, notifier);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int T; cin >> T; while (T--) { int n; cin >> n; cout << n / 2 << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int oo = 1e9 + 9; const long long inf = 1e18 + 18; const int max6 = 1e6 + 6; const int modx = 1e9 + 7; const int mody = 997; const int base = 137; int n, m; int cnt[max6], a[max6], tmp[max6]; int f[3][1005][1005]; int b[3][1005][1005]; int Pow(int a, int b) { if (b == 0) return 1; int half = Pow(a, b / 2); int res = 1ll * half * half % m; if (b % 2) res = 1ll * res * a % m; return res; } void update(int id, int j, int u) { if (id == 1) { for (; u > 0; u -= u & (-u)) b[id][j][u]++; } else { for (; u <= n; u += u & (-u)) b[id][j][u]++; } } int get(int id, int j, int u) { int res = 0; if (id == 1) { for (; u <= n; u += u & (-u)) res = res + b[id][j][u]; } else { for (; u > 0; u -= u & (-u)) res = res + b[id][j][u]; } return res; } int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) { int u = a[i] % m; if (cnt[u]) { cout << 0; return 0; } cnt[u]++; } int res = 1; for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) res = 1ll * res * abs(a[i] - a[j]) % m; cout << res; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long a[n]; for (int i = 0; i < n; ++i) { a[i] = i + 1; } long long ans = 0; long long i = 1, j = 1, k = 2; for (int q = 0; q < n - 2; ++q) { ans += i * a[j] * a[k]; j = (j + 1) % (n); k = (k + 1) % (n); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 3e5 + 100; int t, T, n, k; int A[maxn]; int B[maxn]; int main() { ios::sync_with_stdio(false); cin >> T; while (T--) { cin >> n; int sum = 0; for (int i = 1; i <= n; i++) { cin >> A[i]; sum += A[i]; B[i] = A[i]; } if (sum % n) { cout << -1 << endl; continue; } sum /= n; int cnt = 0; for (int i = 2; i <= n; i++) { int d = (A[i] + i - 1) / i * i - A[i]; if (d <= A[1]) { A[i] += d; A[1] -= d; cnt++; } int x = A[i] / i * i; A[1] += x; A[i] -= x; } int ok = 1; for (int i = n; i > 1; i--) { if (A[i] > sum) ok = 0; A[1] -= (sum - A[i]); if (A[1] < 0) ok = 0; if (!ok) break; } if (!ok) { cout << -1 << endl; continue; } if (ok) { cout << 2 * (n - 1) + cnt << endl; for (int i = 2; i <= n; i++) { int d = (B[i] + i - 1) / i * i - B[i]; if (d <= B[1]) { B[i] += d; B[1] -= d; cout << 1 << << i << << d << endl; } int x = B[i] / i * i; B[1] += x; B[i] -= x; cout << i << << 1 << << x / i << endl; } for (int i = n; i > 1; i--) { int x = sum - B[i]; B[1] -= x; B[i] += x; cout << 1 << << i << << x << endl; } } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_TB_V
`define SKY130_FD_SC_MS__HA_TB_V
/**
* ha: Half adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ha.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_TB_V
|
#include<bits/stdc++.h> using namespace std ; # define all(v) (v).begin() , (v).end() # define allrev(v) (v).rbegin() , (v).rend() # define allcomp(v) (v).begin() , (v).end() , comp # define ll long long # define line cout << n ; # define fast ios_base :: sync_with_stdio ( false ) ; cin.tie ( 0 ) ; # define pii pair < int , int > # define pll pair < ll , ll > # define F first # define S second const int mod = 998244353 ; const int dx[] = { -1 , 0 , 1 , 0 , -1 , -1 , 1 , 1 } ; const int dy[] = { 0 , 1 , 0 , -1 , -1 , 1 , -1 , 1 } ; ll mod_pow ( ll a , ll b ) { if ( b == 0 ) return 1 ; if ( b == 1 ) return a%mod ; if ( b == 2 ) { return ((a%mod) * (a%mod))%mod ; } return (mod_pow ( mod_pow ( a , b>>1 ) , 2 ) * mod_pow ( a , b&1 ))%mod ; } void solve ( int test_case ) { int n ; cin >> n ; int bak = n ; int nr = 0 ; if ( n <= 2 ) nr = 1 ; else { n -= 2 ; ll a = 1 , b = 1 ; while ( n -- ) { b += a ; a = b - a ; a %= mod ; b %= mod ; } nr = b ; } ll f = 1 ; for ( int i = 1 ; i <= bak ; i ++ ) f <<= 1 , f %= mod ; // cout << nr : << nr << and dr : << f ; line ; f = mod_pow ( f , mod - 2 ) ; ll ans = nr * f ; ans %= mod ; cout << ans ; line ; } int main() {fast int t = 1 ; // cin >> t ; for ( int i = 1 ; i <= t ; i ++ ) { solve ( i ) ; } return 0 ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3B_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, m; cin >> n >> m; vector<int> v[n + 1]; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; v[a].push_back(b); } int cnt[n + 1]; for (int o = 1; o <= n; o++) { for (int i = 0; i < (int)v[o].size(); i++) { if (o < v[o][i]) v[o][i] -= o; else v[o][i] = n - (o - v[o][i]); } sort(v[o].begin(), v[o].end()); if (!v[o].empty()) cnt[o] = ((v[o].size() - 1) * n + v[o][0]); else cnt[o] = 0; } for (int o = 1; o <= n; o++) { int res = cnt[o]; int mv = 0; for (int i = o + 1;; i++) { mv++; if (i == n + 1) i = 1; if (i == o) break; res = max(res, (cnt[i] != 0) * (cnt[i] + mv)); } cout << res << ; } cout << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Sep 25 09:53:03 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.2 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_a_e.v,v $
// Revision 1.2 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.93 2006/09/25 08:24:10 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No user `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
port_a, // wire `s_def of signal to port_b
port_a_2, // wire `s_def_2 from port to signal
port_a_3, // wire port splice
port_a_4, // wire port splice 4
port_a_5, // wire port splice 4
port_a_6, // wire `s_def_6 (which is a slice!) to port_b
port_a_7 // wire_7 only define
);
// Generated Module Outputs:
output [10:0] port_a;
output [10:0] port_a_2;
output [10:0] port_a_3;
output [`p_def_4f:`p_def_4t] port_a_4;
output [`s_def_5h:0] port_a_5;
output [10:0] port_a_6;
output [12:0] port_a_7;
// Generated Wires:
wire [10:0] port_a;
wire [10:0] port_a_2;
wire [10:0] port_a_3;
wire [`p_def_4f:`p_def_4t] port_a_4;
wire [`s_def_5h:0] port_a_5;
wire [10:0] port_a_6;
wire [12:0] port_a_7;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/* testcase */
/**
generate this input file:
$ cat t.in
$
expected output in t.out:
$ cat t.out
# x =
# x =
# x =
0
Icarus Verilog output in t.out:
$ cat t.out
# x =
# x =
# x =
0
0
*/
module testbench;
parameter WIDTH = 33;
reg clk;
reg [WIDTH-1:0] in;
reg [WIDTH-1:0] test_val1;
reg [WIDTH-1:0] test_val2;
reg [WIDTH-1:0] test_val3;
integer infile, outfile, count;
initial begin
clk = 0;
in = 0;
test_val1 = 1 << 30;
test_val2 = 1 << 31;
test_val3 = 1 << 32;
infile = $fopen("ivltests/pr2029336.in", "r");
outfile = $fopen("work/pr2029336.out", "w");
$fwrite(outfile, "# x = %d\n", test_val1); // $fwrite() seems to be ok...
$fwrite(outfile, "# x = %d\n", test_val2); // $fwrite() seems to be ok...
$fwrite(outfile, "# x = %d\n", test_val3); // $fwrite() seems to be ok...
end
always @(negedge clk) begin
$fwrite(outfile, "%d\n", in);
count = $fscanf(infile, "%d\n", in); // $fscanf() seems buggy...
if (count != 1) begin
$fclose(infile);
$fclose(outfile);
$finish;
end
end
always #1
clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 400000 + 5; int n, m, tr[N << 2][3], q; set<int> ssp[N][2]; void modify(int x, int who, int v, int l = 1, int r = n, int k = 1) { if (l == r) { if (ssp[l][who].count(v)) ssp[l][who].erase(v); else ssp[l][who].insert(v); tr[k][0] = ssp[l][0].empty() ? 0x3f3f3f3f : *ssp[l][0].begin(); tr[k][1] = ssp[l][1].empty() ? 0 : *ssp[l][1].rbegin(); tr[k][2] = tr[k][1] >= tr[k][0]; return; } int mid = (l + r) >> 1; if (x <= mid) modify(x, who, v, l, mid, k << 1); else modify(x, who, v, mid + 1, r, k << 1 | 1); tr[k][1] = max(tr[k << 1][1], tr[k << 1 | 1][1]); tr[k][0] = min(tr[k << 1][0], tr[k << 1 | 1][0]); tr[k][2] = (tr[k << 1 | 1][1] >= tr[k << 1][0]) | tr[k << 1][2] | tr[k << 1 | 1][2]; } void build(int l = 1, int r = n, int k = 1) { tr[k][0] = 0x3f3f3f3f, tr[k][1] = tr[k][2] = 0; if (l == r) return; int mid = (l + r) >> 1; build(l, mid, k << 1), build(mid + 1, r, k << 1 | 1); } int main() { scanf( %d%d%d , &n, &m, &q); n <<= 1, m <<= 1, build(); while (q--) { int x, y; scanf( %d%d , &x, &y); if (x & 1) { modify(x, 0, y); } else { --x, --y; modify(x, 1, y); } printf( %s n , !tr[1][2] ? YES : NO ); } return 0; }
|
module visualizacion (
input clk,
input ECHO,
input orden,
output trigg,
output [3:0] anodo,
output [6:0] seg
);
wire [7:0] d;
wire [7:0] distancia;
wire [1:0] mostrar;
wire [3:0] digito;
wire [3:0] anodo;
wire [6:0] seg;
wire [3:0] centenas;
wire [3:0] decenas;
wire [3:0] unidades;
divisorfrecdisp divisorfrecdisp0 (
.clk ( clk ),
.CLKOUTseg ( CLKOUTseg )
);
/////////////////////////////////////////////
anteconmutador anteconmutador0 (
.clk ( clk ),
.d ( d ),
.DONE ( DONE ),
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.D ( D ),
.U ( U )
);
/////////////////////////////////////////////
conmutacion conmutacion0 (
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.D ( D ),
.U ( U ),
.CLKOUTseg ( CLKOUTseg ),
.mostrar ( mostrar ),
.digito ( digito )
);
/////////////////////////////////////////////
display display (
.mostrar ( mostrar ),
.digito ( digito ),
.anodo ( anodo ),
.seg ( seg )
);/*
/////////////////////////////////////////////
pulsodisplay pulsodisplay (
.DONE ( DONE ),
.d ( d ),
.CLKOUTseg ( CLKOUTseg ), // Esto Toca Cambiarlo
.pulse ( pulse ),
.distancia ( distancia )
);*/
/////////////////////////////////////////////
bloqueultrasonido bloqueultrasonido (
.d ( d ),
.trigg ( trigg ),
.DONE ( DONE ),
.clk ( clk ),
.orden ( orden ),
.ECHO ( ECHO )
);
endmodule
|
`timescale 1ns / 1ps
module spi #(
parameter clk_divisor=8 // SCLK shall be this many
// times slower than CLK;
// can only be an even number.
)
(
input clk, // Processor clock
input rst, // Processor reset
input [7:0] data_in, // Data to be transferred
output reg[7:0] data_out, // Received data
input ready_send, // Initialize transfer
output busy, // Transaction is in progress
input miso, // Master in slave out
output mosi, // Master out slave in
output sclk, // SPI clock
output ss // Slave select
);
reg[ 3:0] sctr;
reg[ 7:0] data_in_reg;
reg[31:0] ctr;
assign ss = sctr == 0;
assign sclk = !sctr[0] || ss;
assign mosi = data_in_reg[sctr >> 1];
assign busy = !ss;
always @(posedge clk) begin
if (rst) begin
sctr <= 0;
ctr <= 0;
data_out <= 0;
end else if (ready_send && !sctr) begin
data_in_reg <= data_in;
sctr <= 15;
ctr <= 0;
end else if (sctr && ctr + 1 == clk_divisor >> 1) begin
ctr <= 0;
if (sctr[0])
data_out[sctr >> 1] <= miso;
sctr <= sctr - 1;
end else if (sctr) begin
ctr <= ctr + 1;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v4_0_ddr_phy_ocd_edge
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
|
/**
* ff_d.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module ff_d #(parameter WIDTH=8) (
input wire [WIDTH - 1 : 0] D, /* data input */
input wire en, /* enable */
input wire clk, /* clock */
input wire res, /* synchronous active high reset */
output wire [WIDTH - 1 : 0] Q /* output */
);
reg [WIDTH - 1 : 0] storage;
assign Q = storage;
always @(posedge clk) begin
if(res) /* handle synchronous reset */
storage <= {WIDTH{1'b0}};
else if(en) /* handle save data */
storage <= D;
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module conbus_arb5(
input sys_clk,
input sys_rst,
input [4:0] req,
output [2:0] gnt
);
reg [2:0] state;
reg [2:0] next_state;
assign gnt = state;
always @(posedge sys_clk) begin
if(sys_rst)
state <= 3'd0;
else
state <= next_state;
end
always @(*) begin
next_state = state;
case(state)
3'd0: begin
if(~req[0]) begin
if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
end
end
3'd1: begin
if(~req[1]) begin
if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
end
end
3'd2: begin
if(~req[2]) begin
if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
end
end
3'd3: begin
if(~req[3]) begin
if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
end
end
3'd4: begin
if(~req[4]) begin
if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[3 * 100001]; int main() { int n; long long s = 0; cin >> n; for (int i = 1; i <= n; ++i) { cin >> v[i]; } sort(v + 1, v + n + 1); for (int i = 1; i <= n / 2; ++i) { s += (v[i] + v[n - i + 1]) * (v[i] + v[n - i + 1]); } cout << s; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/16/2017 04:17:39 PM
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_tb();
reg CLOCK_50;
reg rst;
wire[7:0] o_sel;
wire[7:0] o_seg;
//integer file_output;
initial begin
//file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
# $stop;
end
top top1(
.clk(CLOCK_50),
.rst(rst),
.o_seg(o_seg),
.o_sel(o_sel)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:23:37 11/08/2015
// Design Name:
// Module Name: Integradorv2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Integradorv2(
input [15:0] a,
input [15:0] dt,
input enable,
input rst,
input clk,
output reg [31:0] v,
output reg busy
);
wire ready;
reg en;
reg [31:0] pv;
reg [31:0] vd;
reg [31:0] pvd;
reg [31:0] varI;
wire [31:0] varS;
reg rest;
initial rest <= 1'b1;
initial v = 32'h0000;
booth_mult Multi(.clk(clk),.rst(rest), .en(en),.A(dt),.B(varI),.busy(ready),.R(varS));
//--------------------------------Module states
localparam
reset = 5'd0,
ini = 5'd1,
mulv = 5'd2,
check_1 = 5'd3,
afterv = 5'd4,
end_state= 5'd5;
// State Machine Regs
reg[4:0] state;
reg[4:0] next_state;
initial state = 0;
initial next_state = 0;
always @(posedge clk)begin
if(rst) state <= reset;
else state <= next_state;
end
always @(*)begin
case(state)
reset: begin
v <= 32'd0;
pv <= 32'd0;
busy <= 1'd1;
en <= 1'd0;
varI <= 32'd0;
rest <= 1'd1;
next_state <= ini;
end
ini: begin
busy <= 1'd0;
v <= vd;
pv <= pvd;
en <= 1'd0;
varI <= 1'd0;
rest <= 1'd1;
if (!enable) next_state <= ini;
else next_state <= mulv;
end
mulv: begin
v <= vd;
pv <= pvd;
busy <= 1'd1;
en <= 1'b1;
rest <=1'b0;
varI <= a;
next_state <= check_1;
end
check_1: begin
v <= vd;
busy <= 1'd1;
en <= 1'b0;
rest <= 1'b0;
varI <= a;
if (!ready) begin
next_state <= afterv;
pv <= v + varS;
end
else begin
pv <= pvd;
next_state <= check_1;
end
end
afterv: begin
v <= vd;
pv <= pvd;
busy <= 1'd1;
varI <= a;
rest <= 1'b1;
en <= 1'd0;
next_state <= end_state;
end
end_state:begin
pv <= pvd;
en <= 1'd0;
rest <=1'b1;
varI <= a;
v <= pv;
busy <= 1'd0;
if (!enable) next_state <= end_state;
else next_state <= ini;
end
default: begin
pv <= pvd;
en <= 1'd0;
rest <= 1'b1;
varI <= a;
v <= vd;
busy <= 1'd0;
next_state <= ini;
end
endcase
end
always @(negedge clk)begin
pvd <= pv;
vd <= v;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool visited[2000]; vector<int> G[2000]; vector<int> parent; int dfs(int u) { if (visited[u]) { return 0; } visited[u] = true; int ans = 0; for (int i = 0; i < G[u].size(); i++) { ans = max(ans, dfs(G[u][i])); } return ans + 1; } int ans(int n) { int a = 0; for (int i = 0; i < parent.size(); i++) { a = max(a, dfs(parent[i])); } return a; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { visited[i] = false; int u; scanf( %d , &u); if (u != -1) { u--; G[u].push_back(i); } else { parent.push_back(i); } } printf( %d n , ans(n)); }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); int n = a * c - b * c; if (n % b > 0) printf( %d n , n / b + 1); else printf( %d n , n / b); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_8_V
`define SKY130_FD_SC_MS__NAND2_8_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_8_V
|
#include <bits/stdc++.h> using namespace std; int n, g[20][20], r, c, k, ans = 0, x, y; bool chk(int a, int b, int c, int d) { int cnt = 0; for (int i = a; i <= a + c; i++) { for (int j = b; j <= b + d; j++) { cnt += g[i][j]; if (cnt >= k) return 1; } } return 0; } int main() { scanf( %d%d%d%d , &r, &c, &n, &k); for (int i = 0; i < n; i++) { scanf( %d%d , &x, &y); g[x][y] = 1; } for (int i = 1; i <= r; i++) { for (int j = 1; j <= c; j++) { for (int e = 0; e + i <= r; e++) { for (int f = 0; f + j <= c; f++) { ans += chk(i, j, e, f); } } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 100; int t, cnt[N]; int mx; int check(int row, int col, int n, int m) { if (row < 0 || row >= n || col < 0 || col >= m) return 0; int i = 0, j = 0, ok = 1; for (; i < n; i++) { for (j = 0; j < m; j++) { if (!cnt[abs(row - i) + abs(col - j)]--) { ok = 0; break; } } if (!ok) break; } if (ok) { cout << n << << m << endl; cout << row + 1 << << col + 1 << endl; return 1; } for (int a = 0; a <= i; a++) for (int b = 0; b < m && (a != i || b <= j); b++) ++cnt[abs(row - a) + abs(col - b)]; return 0; } bool solve(int row, int n, int m, int mxi, int mxj) { if (check(row, mxj - (mx - abs(row - mxi)), n, m)) return 1; return check(row, mxj + (mx - abs(row - mxi)), n, m); } int main() { scanf( %d , &t); for (int i = 0; i < t; ++i) { int v; scanf( %d , &v); ++cnt[v]; mx = max(mx, v); } if (cnt[0] != 1) return puts( -1 ); int a; if (cnt[1] != 4) a = 0; else { a = 1; while (cnt[a + 1] == (a + 1) * 4) a++; } for (int n = 1; n * n <= t; n++) { if (t % n) continue; int m = t / n; if (solve(a, n, m, 0, 0)) return 0; if (solve(a, n, m, 0, m - 1)) return 0; if (solve(a, n, m, n - 1, 0)) return 0; if (solve(a, n, m, n - 1, m - 1)) return 0; if (solve(a, m, n, 0, 0)) return 0; if (solve(a, m, n, 0, n - 1)) return 0; if (solve(a, m, n, m - 1, 0)) return 0; if (solve(a, m, n, m - 1, n - 1)) return 0; } return puts( -1 ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_1_V
`define SKY130_FD_SC_HS__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_1_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 51; int n, x; int res[MAXN]; inline int read() { register int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } inline void calc1(int n) { if (n <= 0) { return; } int x = 31 - __builtin_clz(n); reverse(res + (1 << x + 1) - n - 1, res + n + 1); calc1((1 << x + 1) - n - 2); } inline void solve1() { if (n & 1) { return (void)puts( NO ); } puts( YES ); for (register int i = 1; i <= n; i++) { res[i] = i; } calc1(n); for (register int i = 1; i <= n; i++) { printf( %d , res[i]); } puts( ); } inline void solve2() { if (n == 3 || n == 5 || n == (n & -n)) { return (void)puts( NO ); } puts( YES ); for (register int i = 1; i <= n; i++) { res[i] = i; } if (n & 1) { printf( 3 6 1 5 7 2 4 ); for (register int i = 8; i <= n; i += 2) { swap(res[i], res[i ^ 1]); } for (register int i = 8; i <= n; i++) { printf( %d , res[i]); } } else { for (register int i = 2; i <= n - 3; i += 2) { swap(res[i], res[i + 1]); } swap(res[1], res[n - 1]), swap(res[n], res[n - 2]); for (register int i = 1; i <= n; i++) { printf( %d , res[i]); } } puts( ); } int main() { n = read(), solve1(), solve2(); }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 9223000000000000000; struct DATA { long long v; long long c; long double p; }; long long n, l; DATA data[31]; bool cmp(DATA x, DATA y) { return x.p < y.p; } void init() { scanf( %lld%lld , &n, &l); for (int i = 1; i <= n; i++) { scanf( %lld , &data[i].c); data[i].v = pow(2, i - 1); data[i].p = (long double)data[i].c / data[i].v; } sort(data + 1, data + n + 1, cmp); } long long process(long long left) { long long ans = maxn; if (left == 0) return 0; for (int i = 1; i <= n; i++) { if (data[i].v >= left) ans = min(ans, data[i].c); } int id = -1; for (int i = 1; i <= n; i++) if (data[i].v < left) { id = i; break; } if (id != -1) { long long sum = 0; long long k = left / data[id].v; sum = k * data[id].c + process(left - k * data[id].v); ans = min(ans, sum); } return ans; } int main() { init(); printf( %lld , process(l)); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_PP_V
|
/*
VGA Demo 800x480 at 58Hz
The screen I'm using
http://www.amazon.co.uk/gp/product/B00IR5VRS4?psc=1&redirect=true&ref_=oh_aui_detailpage_o00_s01
http://www.adafruit.com/datasheets/KD50G21-40NT-A1.pdf
if these timings fail, try http://www.adafruit.com/datasheets/AT070TN94.pdf
Pixel Clock (MHz): 30.000
Horizontal (in Pixels)
Active Video: 800
Front Porch: 40
Sync Pulse: 48
Back Porch: 88
Total pixel clock ticks: 976
Vertical (in Lines)
Active Video: 480
Front Porch: 13
Sync Pulse: 3
Back Porch: 32
Total pixel clock ticks: 528
Total pixel clock ticks: 692,640
30,000,000 / 515,328 = 58.215350224 = 58Hz
1 pixel clock = 1/30Mhz = 33ns = 0.033us
*/
module vga_demo
(
CLOCK_PIXEL,
RESET,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// Code
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max)
ver_reg <= 0;
else
ver_reg <= ver_reg + 1;
end else
hor_reg <= hor_reg + 1;
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
else if (hor_reg == 928) // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
/* Generating the vertical sync signal */
if (ver_reg == 493) // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
else if (ver_reg == 496) // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
end
else begin
// Draw a single square.
if (hor_reg >= 100 && hor_reg <= 200 && ver_reg >= 100 && ver_reg <= 200) begin
red <= 0;
green <= 1;
blue <= 0;
end
// top border
else if (ver_reg == 0 ) begin
red <= 0;
green <= 1;
blue <= 0;
end
// bottom border
else if (ver_reg == 478 ) begin // Not quite 480 visable
red <= 0;
green <= 1;
blue <= 0;
end
// left border
else if (hor_reg == 0 ) begin
red <= 1;
green <= 0;
blue <= 0;
end
// right border
else if (hor_reg == 780 ) begin // Not quite 800 visable
red <= 1;
green <= 0;
blue <= 0;
end
else begin
red <= 1;
green <= 1;
blue <= 1;
end
end
end
end
// Send the sync signals to the outputh.
// this doc says pulse is positive http://tinyvga.com/vga-timing/800x600@72Hz
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
endmodule
|
#include <bits/stdc++.h> using namespace std; int fastpow(int a, int b) { int ans = 1; for (; b; b >>= 1, a = a * a) if (b & 1) ans = ans * a; return ans; } int num; int main() { int n; scanf( %d , &n); string a; cin >> a; for (int i = 0; i < a.length(); i++) n += (a[i] - 0 ) * fastpow(10, i); printf( %d , n); return 0; }
|
// megafunction wizard: %RAM: 3-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt3pram
// ============================================================
// File Name: IMG_TRI_BUFFER.v
// Megafunction Name(s):
// alt3pram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module IMG_TRI_BUFFER (
data,
rdaddress_a,
rdaddress_b,
rdclock,
wraddress,
wrclock,
wren,
qa,
qb);
input [7:0] data;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [7:0] qa;
output [7:0] qb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] qa = sub_wire0[7:0];
wire [7:0] qb = sub_wire1[7:0];
alt3pram alt3pram_component (
.outclock (rdclock),
.wren (wren),
.inclock (wrclock),
.data (data),
.rdaddress_a (rdaddress_a),
.wraddress (wraddress),
.rdaddress_b (rdaddress_b),
.qa (sub_wire0),
.qb (sub_wire1)
// synopsys translate_off
,
.aclr (),
.inclocken (),
.outclocken (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
alt3pram_component.indata_aclr = "OFF",
alt3pram_component.indata_reg = "INCLOCK",
alt3pram_component.intended_device_family = "Cyclone III",
alt3pram_component.lpm_type = "alt3pram",
alt3pram_component.outdata_aclr_a = "OFF",
alt3pram_component.outdata_aclr_b = "OFF",
alt3pram_component.outdata_reg_a = "OUTCLOCK",
alt3pram_component.outdata_reg_b = "OUTCLOCK",
alt3pram_component.rdaddress_aclr_a = "OFF",
alt3pram_component.rdaddress_aclr_b = "OFF",
alt3pram_component.rdaddress_reg_a = "OUTCLOCK",
alt3pram_component.rdaddress_reg_b = "OUTCLOCK",
alt3pram_component.rdcontrol_aclr_a = "OFF",
alt3pram_component.rdcontrol_aclr_b = "OFF",
alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",
alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",
alt3pram_component.width = 8,
alt3pram_component.widthad = 11,
alt3pram_component.write_aclr = "OFF",
alt3pram_component.write_reg = "INCLOCK";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGqa NUMERIC "1"
// Retrieval info: PRIVATE: REGqb NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden_a NUMERIC "0"
// Retrieval info: PRIVATE: rden_b NUMERIC "0"
// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"
// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "OUTCLOCK"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "OUTCLOCK"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "11"
// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"
// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: qa 0 0 8 0 OUTPUT NODEFVAL qa[7..0]
// Retrieval info: USED_PORT: qb 0 0 8 0 OUTPUT NODEFVAL qb[7..0]
// Retrieval info: USED_PORT: rdaddress_a 0 0 11 0 INPUT NODEFVAL rdaddress_a[10..0]
// Retrieval info: USED_PORT: rdaddress_b 0 0 11 0 INPUT NODEFVAL rdaddress_b[10..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: qa 0 0 8 0 @qa 0 0 8 0
// Retrieval info: CONNECT: qb 0 0 8 0 @qb 0 0 8 0
// Retrieval info: CONNECT: @wraddress 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @rdaddress_a 0 0 11 0 rdaddress_a 0 0 11 0
// Retrieval info: CONNECT: @rdaddress_b 0 0 11 0 rdaddress_b 0 0 11 0
// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IMG_TRI_BUFFER_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int mxn = 1e5 + 100; int a[mxn], b[mxn], c[mxn]; set<int> mp; void add(int x) { if (c[x] == 0) mp.insert(b[x]); else if (c[x] == 1) mp.erase(b[x]); c[x]++; } void remove(int x) { if (c[x] == 2) mp.insert(b[x]); else if (c[x] == 1) mp.erase(b[x]); c[x]--; } int main() { int n, k, m; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , a + i), b[i - 1] = a[i]; sort(b, b + n), m = unique(b, b + n) - b; for (int i = 1; i <= n; i++) { a[i] = lower_bound(b, b + m, a[i]) - b; add(a[i]); if (i >= k) { if (mp.empty()) puts( Nothing ); else printf( %d n , *mp.rbegin()); remove(a[i - k + 1]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5, maxk = (1 << 20), inf = 1e9; int dp[maxk][2]; int ind[20]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m >> k; string a, b; cin >> a >> b; int c = 0, d = 0; for (int i = 0; i < k; i++) { if (a[i] == 1 ) { c += (1 << i); } if (b[i] == 1 ) { d += (1 << i); } } for (int i = 0; i < maxk; i++) { dp[i][0] = inf; dp[i][1] = -inf; } dp[c][0] = 0; dp[d][1] = 0; int x, y; int c1, d1; for (int i = 0; i < k; i++) { ind[i] = i; } for (int i = 0; i < n; i++) { cin >> x >> y; x--; y--; swap(ind[x], ind[y]); c1 = 0; d1 = 0; for (int j = 0; j < k; j++) { c1 += (1 << ind[j]) * (((1 << j) & c) > 0); d1 += (1 << ind[j]) * (((1 << j) & d) > 0); } if (dp[c1][0] == inf) { dp[c1][0] = i + 1; } dp[d1][1] = i + 1; } int uk = __builtin_popcount(c) + __builtin_popcount(d); int sol = 0; pair<int, int> range = {1, 1}; for (int i = (1 << k) - 1; i > -1; i--) { if (dp[i][1] - dp[i][0] >= m) { if (sol < k + __builtin_popcount(i) * 2 - uk) { sol = k + __builtin_popcount(i) * 2 - uk; range = {dp[i][0] + 1, dp[i][1]}; } } for (int j = 0; j < k; j++) { if (i & (1 << j)) { dp[i ^ (1 << j)][0] = min(dp[i ^ (1 << j)][0], dp[i][0]); dp[i ^ (1 << j)][1] = max(dp[i ^ (1 << j)][1], dp[i][1]); } } } cout << sol << n ; cout << range.first << << range.second << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; int sum1 = 0, sum2 = 0, sum3 = 0; int flag1 = 1, flag2 = 0, flag3 = 0; for (int i = 1; i <= n; i++) { int a; cin >> a; if (flag1) { sum1 += a; flag1 = 0; flag2 = 1; continue; } if (flag2) { sum2 += a; flag2 = 0; flag3 = 1; continue; } if (flag3) { sum3 += a; flag3 = 0; flag1 = 1; continue; } } if (sum1 > sum2 && sum1 > sum3) { cout << chest n ; } else if (sum2 > sum1 && sum2 > sum3) { cout << biceps n ; } else { cout << back n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr[n]; map<long long, int> mp; vector<long long> summer(n); for (int i = 0; i < n; i++) { int m; cin >> m; int tmp; long long sum = 0; for (int j = 0; j < m; j++) { cin >> tmp; arr[i].push_back(tmp); sum += tmp; } summer[i] = sum; for (int j = 0; j < m; j++) { long long key = sum - arr[i][j]; if (mp.find(key) != mp.end()) { if (mp[key] != i) { cout << YES n << i + 1 << << j + 1 << n ; int cur = mp[key]; cout << cur + 1 << ; int check = summer[cur] - key; for (int k = 0; k < arr[cur].size(); k++) { if (arr[cur][k] == check) { cout << k + 1; return 0; } } } } else { mp[key] = i; } } } cout << NO ; }
|
module Sec4(
input A,
input B,
input C,
input AnalogLDir,
input AnalogRDir,
output Len,
output Ldir,
output Ren,
output Rdir
);
wire Z_A;
wire Z_B;
wire Z_C;
wire Ldir_int;
wire Len_int;
wire Rdir_int;
wire Ren_int;
wire Analog_select;
supply0 GND;
assign Analog_select = AnalogLDir & AnalogRDir;
inv invA(.A(A), .Z(Z_A));
inv invB(.A(B), .Z(Z_B));
inv invC(.A(C), .Z(Z_C));
section2_schematic lab2Logic(.A(Z_A),
.B(Z_B),
.C(Z_C),
.Ld(Ldir_int),
.Le(Len_int),
.Rd(Rdir_int),
.Re(Ren_int)
);
mux2 mux_1(.d0(AnalogLDir), .d1(Ldir_int), .s(Analog_select), .y(Ldir));
mux2 mux_2(.d0(GND), .d1(Len_int), .s(Analog_select), .y(Len));
mux2 mux_3(.d0(AnalogRDir), .d1(Rdir_int), .s(Analog_select), .y(Rdir));
mux2 mux_4(.d0(GND), .d1(Ren_int), .s(Analog_select), .y(Ren));
endmodule
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inv (input A,
output Z);
assign Z = ~A;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int l, r; scanf( %d%d , &l, &r); if (l == r && l % 2) printf( %d , l); else printf( %d , 2); }
|
#include <bits/stdc++.h> using namespace std; int S, l[100], r[100], N, w[200]; double a[100], b[100], f[100][100], ans[100]; void init() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d%d , &l[i], &r[i]), w[++S] = l[i], w[++S] = r[i]; } void calc(int p, int L, int R) { int t = 0, bg = 0; memset(f, 0, sizeof(f)), f[0][0] = 1.0 * (R - L) / (r[p] - l[p]); for (int i = 1; i <= N; i++) if (i != p) { double s = r[i] - l[i], x, y; if (r[i] <= L) { bg++; continue; } else if (R <= l[i]) continue; else x = (L - l[i]) / s, y = (R - L) / s; t++; for (int j = t; j >= 0; j--) for (int k = t - j; k >= 0; k--) { f[j][k] *= 1 - x - y; if (j) f[j][k] += f[j - 1][k] * x; if (k) f[j][k] += f[j][k - 1] * y; } } for (int i = 0; i + bg < N; i++) for (int j = 0; i + bg + j < N; j++) ans[i + bg + 1] += f[i][j] / (j + 1), ans[i + bg + j + 2] -= f[i][j] / (j + 1); } void doit() { sort(w + 1, w + S + 1); for (int i = 1; i <= N; i++) { memset(ans, 0, sizeof(ans)); for (int j = 1; j <= S; j++) if ((j == 1 || w[j] != w[j - 1]) && l[i] <= w[j - 1] && w[j] <= r[i]) calc(i, w[j - 1], w[j]); for (int j = 1; j <= N; j++) printf( %.9lf%c , ans[j] += ans[j - 1], j == N ? n : ); } } int main() { init(); doit(); return 0; }
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY serdes watchdog
*/
module eth_phy_10g_rx_watchdog #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_reset_req,
/*
* Monitor inputs
*/
input wire rx_bad_block,
input wire rx_sequence_error,
input wire rx_block_lock,
input wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2(COUNT_125US);
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
reg [3:0] error_count_reg = 0, error_count_next;
reg saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next;
reg [9:0] block_error_count_reg = 0, block_error_count_next;
reg serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next;
assign serdes_rx_reset_req = serdes_rx_reset_req_reg;
always @* begin
error_count_next = error_count_reg;
saw_ctrl_sh_next = saw_ctrl_sh_reg;
block_error_count_next = block_error_count_reg;
serdes_rx_reset_req_next = 1'b0;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin
block_error_count_next = block_error_count_reg + 1;
end
end
if (time_count_reg != 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = COUNT_125US;
if (!saw_ctrl_sh_reg || &block_error_count_reg) begin
error_count_next = error_count_reg + 1;
end else begin
error_count_next = 0;
end
if (&error_count_reg) begin
error_count_next = 0;
serdes_rx_reset_req_next = 1'b1;
end
saw_ctrl_sh_next = 1'b0;
block_error_count_next = 0;
end
end
always @(posedge clk) begin
time_count_reg <= time_count_next;
error_count_reg <= error_count_next;
saw_ctrl_sh_reg <= saw_ctrl_sh_next;
block_error_count_reg <= block_error_count_next;
if (rst) begin
time_count_reg <= COUNT_125US;
error_count_reg <= 0;
saw_ctrl_sh_reg <= 1'b0;
block_error_count_reg <= 0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
serdes_rx_reset_req_reg <= 1'b0;
end else begin
serdes_rx_reset_req_reg <= serdes_rx_reset_req_next;
end
end
endmodule
`resetall
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; double eps = 1e-10; const int maxn = 30005; char s[105][105]; int num[105][105], ans[105]; int main() { ios::sync_with_stdio; cin.tie(0); double a, b, c, d; cin >> a >> b >> c >> d; double l = 0, r = 1e9 + 7; for (int i = 1; i <= 100; i++) { double mid = (l + r) / 2.0; double maxia = max(max((a + mid) * (d + mid), (a + mid) * (d - mid)), max((a - mid) * (d + mid), (a - mid) * (d - mid))); double minia = min(min((a + mid) * (d + mid), (a + mid) * (d - mid)), min((a - mid) * (d + mid), (a - mid) * (d - mid))); double maxib = max(max((b + mid) * (c + mid), (b + mid) * (c - mid)), max((b - mid) * (c + mid), (b - mid) * (c - mid))); double minib = min(min((b + mid) * (c + mid), (b + mid) * (c - mid)), min((b - mid) * (c + mid), (b - mid) * (c - mid))); if (maxia >= minib && maxia <= maxib || minia >= minib && minia <= maxib || maxib >= minia && maxib <= maxia || minib >= minia && minib <= maxia) r = mid; else l = mid; } printf( %.10lf n , l); return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<pair<bool, long double>, string> a[13]; bool comp(pair<pair<bool, long double>, string> a, pair<pair<bool, long double>, string> b) { auto t1 = a.first, t2 = b.first; if (t1.first != t2.first) return t1.first; if (abs(t1.second - t2.second) <= 1e-6) return false; return (t1.second < t2.second) ^ t1.first; } int main() { long double x, y, z; cin >> x >> y >> z; a[1] = {{x < 1, z * log10(y) + (x < 1 ? log10(-log10(x)) : log10(log10(x)))}, x^y^z }; a[2] = {{x < 1, y * log10(z) + (x < 1 ? log10(-log10(x)) : log10(log10(x)))}, x^z^y }; a[3] = {{x < 1, log10(y * z) + (x < 1 ? log10(-log10(x)) : log10(log10(x)))}, (x^y)^z }; a[4] = {{x < 1, log10(y * z) + (x < 1 ? log10(-log10(x)) : log10(log10(x)))}, (x^z)^y }; a[5] = {{y < 1, z * log10(x) + (y < 1 ? log10(-log10(y)) : log10(log10(y)))}, y^x^z }; a[6] = {{y < 1, x * log10(z) + (y < 1 ? log10(-log10(y)) : log10(log10(y)))}, y^z^x }; a[7] = {{y < 1, log10(z * x) + (y < 1 ? log10(-log10(y)) : log10(log10(y)))}, (y^x)^z }; a[8] = {{y < 1, log10(z * x) + (y < 1 ? log10(-log10(y)) : log10(log10(y)))}, (y^z)^x }; a[9] = {{z < 1, y * log10(x) + (z < 1 ? log10(-log10(z)) : log10(log10(z)))}, z^x^y }; a[10] = {{z < 1, x * log10(y) + (z < 1 ? log10(-log10(z)) : log10(log10(z)))}, z^y^x }; a[11] = {{z < 1, log10(y * x) + (z < 1 ? log10(-log10(z)) : log10(log10(z)))}, (z^x)^y }; a[12] = {{z < 1, log10(y * x) + (z < 1 ? log10(-log10(z)) : log10(log10(z)))}, (z^y)^x }; int ind = 1; for (int i = 2; i <= 12; i++) ind = (comp(a[ind], a[i]) ? i : ind); cout << a[ind].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const char *par = () ; const int pm[] = {1, -1}; int n; int mn, res, fir; string s; vector<int> v, w; map<int, int> mp; int init(string s) { v = vector<int>(n); for (int i = 0, pre = 0; i < n; ++i) { v[i] = (pre += pm[strchr(par, s[i]) - par]); mp[v[i]]++; } if (v.back() != 0) return 0; res = mp.begin()->second; mn = mp.begin()->first; for (int i = 0; i < n; ++i) if (v[i] == mn) { fir = (i + 1) % n; return res; } } int count(int l, int r) { int cur = v[(l - 1 + n) % n]; s[l] = ) ; for (int i = l; i != r; i = (i + 1) % n) { cur += pm[strchr(par, s[i]) - par]; if (!--mp[v[i]]) mp.erase(v[i]); mp[cur]++; } int ret = mp.begin()->second; cur = v[(l - 1 + n) % n]; for (int i = l; i != r; i = (i + 1) % n) { cur += pm[strchr(par, s[i]) - par]; if (!--mp[cur]) mp.erase(cur); mp[v[i]]++; } s[l] = ( ; return ret; } int main() { cin >> n >> s; if (!init(s)) { cout << 0 n1 1 n ; return 0; } stack<int> st; int i = fir; w = vector<int>(n); do { if (s[i] == ( ) st.push(i); if (s[i] == ) ) { w[i] = st.top(); w[w[i]] = i; st.pop(); } } while ((i = (i + 1) % n) != fir); int ans[3] = {res}; for (int i = 0; i < n; ++i) if (s[i] == ( && v[i] <= mn + 2) { int ret = count(i, w[i]); if (ret > ans[0]) ans[0] = ret, ans[1] = i, ans[2] = w[i]; } cout << ans[0] << endl << ans[1] + 1 << << ans[2] + 1 << endl; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_broadcast(
dq_data_in,
dm_data_in,
dq_data_out,
dm_data_out
);
parameter NUMBER_OF_DQS_GROUPS = "";
parameter NUMBER_OF_DQ_PER_DQS = "";
parameter AFI_RATIO = "";
parameter MEM_DM_WIDTH = "";
localparam NUMBER_OF_DQ_BITS = NUMBER_OF_DQS_GROUPS * NUMBER_OF_DQ_PER_DQS;
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
input [NUMBER_OF_DQ_PER_DQS * NUMBER_OF_WORDS - 1 : 0] dq_data_in;
input [NUMBER_OF_WORDS - 1 : 0] dm_data_in;
output [NUMBER_OF_DQ_BITS * NUMBER_OF_WORDS - 1 : 0] dq_data_out;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1 : 0] dm_data_out;
genvar gr, wr, dmbit;
generate
for(wr = 0; wr < NUMBER_OF_WORDS; wr = wr + 1)
begin : word
for(gr = 0; gr < NUMBER_OF_DQS_GROUPS; gr = gr + 1)
begin : group
assign dq_data_out[wr * NUMBER_OF_DQ_BITS + (gr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_BITS + gr * NUMBER_OF_DQ_PER_DQS] =
dq_data_in[(wr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_PER_DQS];
end
for(dmbit = 0; dmbit < MEM_DM_WIDTH; dmbit = dmbit + 1)
begin : data_mask_bit
assign dm_data_out[wr * MEM_DM_WIDTH + dmbit] = dm_data_in[wr];
end
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@dm_data_in NUMBER_OF_DQS_GROUPS == MEM_DM_WIDTH) else
$error("%t, [DATA BROADCAST ASSERT] NUMBER_OF_DQS_GROUPS and MEM_DM_WIDTH mismatch, NUMBER_OF_DQS_GROUPS = %d, MEM_DM_WIDTH = %d", $time, NUMBER_OF_DQS_GROUPS, MEM_DM_WIDTH);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, mod = 1e9 + 7; const long long inf = 1e18; long long tn[20], fv[20]; long long Mul(long long a, long long b, long long md) { long long ans = 0; while (b) { if (b & 1) ans = (ans + a) % md; a = (a + a) % md; b >>= 1; } return ans; } long long Pow(long long a, long long b, long long md) { long long ans = 1; while (b) { if (b & 1) ans = Mul(ans, a, md); a = Mul(a, a, md); b >>= 1; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); tn[0] = fv[0] = 1; for (int i = 1; i < 19; i++) tn[i] = tn[i - 1] * 10, fv[i] = fv[i - 1] * 5; int q; cin >> q; while (q--) { long long x; cin >> x; long long xx = x; int n = 0; while (xx > 0) n++, xx /= 10; long long y = (-tn[17 - n] * x) % (1ll << 17); if (y < 0) y += (1ll << 17); if (y % 5 == 0) y += (1ll << 17); x = tn[17 - n] * x + y; long long ans = 0; if (x % 5 == 2) ans = 1; if (x % 5 == 4) ans = 2; if (x % 5 == 3) ans = 3; for (int i = 2; i <= 17; i++) while (Pow(2, ans, fv[i]) != (x % fv[i])) ans = (ans + 4ll * fv[i - 2]) % (4ll * fv[i - 1]); ans += 4ll * fv[16]; cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, kol = 0; vector<int> a, b; cin >> n; for (i = 0; i < n; i++) { cin >> j; a.push_back(j); b.push_back(j); } sort(b.begin(), b.end()); for (i = 0; i < n; i++) if (a[i] != b[i]) kol++; if (kol == 0 || kol == 2) cout << YES ; else cout << NO ; return 0; }
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* PL allocator
*
*
*/
module LAG_pl_allocator (req, output_port, // PL request, for which port?
pl_new, pl_new_valid, // newly allocated PL ids
pl_allocated, // which PLs were allocated on this cycle?
pl_alloc_status, // which PLs are free?
clk, rst_n);
parameter buf_len=4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter dynamic_priority_pl_alloc = 0;
parameter plalloc_unrestricted = 0;
parameter alloc_stages = 1;
parameter plselect_bydestinationnode = 0;
parameter plselect_leastfullbuffer = 0;
parameter plselect_arbstateupdate = 0;
parameter plselect_usepacketmask = 0;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
// input pl_priority_t pl_sel_priority [np-1:0][nv-1:0][nv-1:0];
output [np-1:0][nv-1:0] pl_allocated;
input [np-1:0][nv-1:0] pl_alloc_status;
input clk, rst_n;
generate
LAG_pl_unrestricted_allocator
#(.np(np), .nv(nv), .xs(xs), .ys(ys), .buf_len(buf_len),
.alloc_stages(alloc_stages),
.dynamic_priority_pl_alloc(dynamic_priority_pl_alloc),
.plselect_bydestinationnode(plselect_bydestinationnode),
.plselect_leastfullbuffer(plselect_leastfullbuffer),
.plselect_arbstateupdate(plselect_arbstateupdate),
.plselect_usepacketmask(plselect_usepacketmask))
unrestricted
(
.req,
.output_port,
.pl_status(pl_alloc_status),
.pl_new,
.pl_new_valid,
.pl_allocated,
.clk, .rst_n
);
endgenerate
endmodule // LAG_pl_allocator
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 21; const long long MOD = 1000000007; int n; long long m; long long C[MAXN][MAXN]; long long g[MAXN], s[MAXN], ten[MAXN], eight[MAXN]; inline void update(long long& x, long long y) { y %= MOD, x += y, x %= MOD; } inline long long P(const long long& x, int y) { if (x < y) return 0; long long res = 1; for (long long i = x; i >= x - y + 1; --i) res = (res * i) % MOD; return res; } inline pair<int, int> get(long long num, int x) { int res4 = 0, res7 = 0; for (int i = 1; i <= x; ++i) num /= 10; for (long long i = num; i > 0; i /= 10) if (i % 10 == 4) res4++; else if (i % 10 == 7) res7++; return pair<int, int>(res4, res7); } inline long long F(const long long& num, int x, int a, int b) { pair<int, int> p = get(num, x); a -= p.first, b -= p.second; if (a < 0 || b < 0 || a + b > x) return 0; return (((C[x][a] * C[x - a][b]) % MOD) * eight[x - a - b]) % MOD; } inline long long G(long long num, int x, int a, int b) { long long res = 0; for (; num + ten[x] <= m; num += ten[x]) update(res, F(num, x, a, b)); if (x > 0) { if (num <= m) update(res, G(num, x - 1, a, b)); } else update(res, F(num, x, a, b)); return res; } inline void preProcess() { ten[0] = eight[0] = 1; for (int i = 1; i < MAXN; ++i) ten[i] = ten[i - 1] * 10, eight[i] = eight[i - 1] * 8; while (ten[n] <= m) n++; C[0][0] = 1; for (int i = 1; i < MAXN; ++i) { C[i][0] = C[i][i] = 1; for (int j = 1; j < i; ++j) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % MOD; } for (int i = 0; i <= n; ++i) for (int j = 0; j <= i; ++j) update(g[i], G(0, n - 1, j, i - j)); g[0]--; } inline long long dp(int s, int x, int y, int z) { if (y < 0 || z < 0) return 0; if (x == s) return (y == 0) ? 1 : 0; long long res = 0; for (int i = 0; i <= y; ++i) { long long k = (C[y][i] * P(g[x], i)) % MOD; update(res, k * dp(s, x + 1, y - i, z - i * x)); } return res; } int main() { scanf( %I64d n , &m); preProcess(); long long res = 0; for (int s = 1; s <= n; ++s) update(res, g[s] * dp(s, 0, 6, s - 1)); printf( %I64d n , res); fclose(stdin); fclose(stdout); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_SYMBOL_V
`define SKY130_FD_SC_HD__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, k, res = 1; long long a[100005]; long long b[100005]; long long d = 1, ans; int main() { cin >> n >> k; for (int i = 0; i < k; i++) d *= 10; for (int i = 0; i < n / k; i++) cin >> a[i]; for (int i = 0; i < n / k; i++) cin >> b[i]; for (int i = 0; i < n / k; i++) { ans = (d - 1) / a[i] + 1; if (b[i] == 0) ans -= ((d / 10) - 1) / a[i] + 1; else ans -= ((b[i] + 1) * (d / 10) - 1) / a[i] - ((b[i]) * (d / 10) - 1) / a[i]; res = (res * ans) % (1000000007); } cout << res; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A311O_PP_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_PP_BLACKBOX_V
|
module top;
parameter parm = 1;
parameter name0_s = 1; // signal
wire [1:0] out;
/***********
* Check signals
***********/
// Check signal/parameter name issues.
wire name0_s;
// Check signal/genvar name issues.
genvar name0_v;
generate
for (name0_v = 0; name0_v < 2; name0_v = name0_v + 1) begin
assign out[name0_v] = name0_v;
end
endgenerate
wire name0_v;
// Check signal/task name issues.
task name1_st;
$display("FAILED in task name1_st");
endtask
wire name1_st;
// Check signal/function name issues.
function name2_sf;
input in;
name2_sf = in;
endfunction
wire name2_sf;
// Check signal/module instance name issues.
test name3_si(out[0]);
wire name3_si;
// Check signal/named block name issues.
initial begin: name4_sb
$display("FAILED in name4_sb");
end
wire name4_sb;
// Check signal/named event name issues.
event name5_se;
wire name5_se;
// Check signal/generate loop name issues.
genvar i;
generate
for (i = 0; i < 2 ; i = i + 1) begin: name6_sgl
assign out[i] = i;
end
endgenerate
wire name6_sgl;
// Check signal/generate if name issues.
generate
if (parm == 1) begin: name7_sgi
assign out[1] = 1;
end
endgenerate
wire name7_sgi;
// Check signal/generate case name issues.
generate
case (parm)
1: begin: name8_sgc
assign out[1] = 1;
end
default: begin: name8_sgc
assign out[1] = 0;
end
endcase
endgenerate
wire name8_sgc;
// Check signal/generate block name issues.
generate
begin: name9_sgb
assign out[0] = 0;
end
endgenerate
wire name9_sgb;
initial $display("FAILED");
endmodule
module test(out);
output out;
reg out = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; int n, l; int a[maxn], b[maxn]; bool check(int d, int x, int y) { int i = x + 1, j = y + 1; i %= n; j %= n; while (i != x && j != y) { if ((a[i] - b[j] + l) % l == d) { i++; i %= n; j++; j %= n; } else { return false; } } return true; } int main() { cin >> n >> l; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; bool flag = false; for (int i = 0; i < n && !flag; i++) { for (int j = 0; j < n && !flag; j++) { int d = (a[i] - b[j] + l) % l; if (check(d, i, j)) { flag = true; } } } if (flag) cout << YES << endl; else cout << NO << endl; return 0; }
|
// niosii_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [17:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [17:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
niosii_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1025; long long p[MAX_N]; int main() { long long s, n, sum = 0; scanf( %lld%lld , &n, &s); for (int i = 1; i <= n; ++i) scanf( %lld , &p[i]), sum += p[i]; sort(p + 1, p + 1 + n); if (sum < s) { printf( -1 n ); return 0; } else { long long tmp = 0; for (int i = 1; i <= n; ++i) { tmp += p[i] - p[1]; } if (tmp >= s) { printf( %lld n , p[1]); return 0; } else { tmp = s - tmp; long long k = (tmp - 1) / n + 1; printf( %lld n , p[1] - k); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int main() { long long k, d, t; scanf( %lld %lld %lld , &k, &d, &t); if (k % d == 0) { printf( %.10lf n , (double)t); return 0; } t *= 2; long long period = (k / d + 1) * d; long long periodPoints = 2 * k + period - k; long long nPeriods = t / periodPoints; long long timeSpent = nPeriods * periodPoints; long long rest = t - timeSpent; if (rest == 0) { printf( %.10lf n , (double)nPeriods * period); return 0; } if (2 * k >= rest) { printf( %.10lf n , (double)nPeriods * period + rest / 2.0); return 0; } printf( %.10lf n , (double)nPeriods * period + rest - k); }
|
#include <bits/stdc++.h> using namespace std; int num[200000]; long long cnt[200000] = {0}; long long dp[200000] = {0}; long long sum[200000] = {0}; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> num[i]; cnt[num[i]]++; } long long ans = 0; for (int i = 1; i < 200000; ++i) { if (i > 1) { dp[i] = max(dp[i - 2] + cnt[i] * i, dp[i - 1]); } else { dp[i] = cnt[i] * i; } ans = max(ans, dp[i]); } cout << ans << endl; return 0; }
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module datapath (
input clk,
input reset,
input stall,
output [31:0] fetch_addr,
output fetch_request,
input fetch_data_valid,
output [31:0] dmem_addr,
output [31:0] dmem_write_data,
output [3:0] dmem_write_mask,
output dmem_request,
output dmem_request_type,
input dmem_data_valid,
input [31:0] request_data,
output [31:0] ptbr,
output vm_enable,
output flush_tlb
);
reg [31:0] inst;
reg [31:0] pc;
wire [1:0] next_pc_sel;
wire [2:0] wb_sel;
wire rf_wr_en;
wire interrupt;
wire [31:0] evec;
wire branch_taken;
wire [31:0] branch_target;
wire jump_taken;
wire [31:0] jump_target;
reg [31:0] fetch_pc;
always @ (*) begin
if (stall)
fetch_pc = pc;
else if (interrupt)
fetch_pc = evec;
else if (jump_taken)
fetch_pc = jump_target;
else if (branch_taken)
fetch_pc = branch_target;
else
fetch_pc = pc + 4;
end
assign fetch_addr = fetch_pc;
assign fetch_request = !reset;
always @ (posedge clk) begin
/* PC */
if (reset)
pc <= `PC_START;
else
pc <= fetch_pc;
end
always @ (posedge clk) begin
/* Instruction */
if (reset)
inst <= `INSTR_NOP;
else if (fetch_data_valid)
inst <= request_data;
end
/* DECODE and EXECUTE */
wire [4:0] ex_rs1;
wire [4:0] ex_rs2;
wire [4:0] ex_wd;
wire cp_enable;
wire [1:0] pcr_cmd;
decode d(.inst(inst),
.rs1(ex_rs1), .rs2(ex_rs2), .wd(ex_wd),
.wb_sel(wb_sel), .rf_wr_en(rf_wr_en),
.memory_request(dmem_request), .memory_request_type(dmem_request_type),
.pcr_enable(cp_enable), .pcr_cmd(pcr_cmd));
wire [31:0] rf_rd1;
wire [31:0] rf_rd2;
reg [31:0] rf_wdata;
regfile rf(.clk(clk), .reset(reset), .rd1(rf_rd1), .rd2(rf_rd2), .rs1(ex_rs1),
.rs2(ex_rs2), .wd(ex_wd), .w_data(rf_wdata), .w_enable(rf_wr_en),
.stall(stall));
wire [4:0] alu_sel;
wire [1:0] mul_sel;
wire [31:0] alu_op1;
wire [31:0] alu_op2;
alu_dec ad(.alu_sel(alu_sel), .mul_sel(mul_sel),
.op1(alu_op1), .op2(alu_op2),
.rs1(rf_rd1), .rs2(rf_rd2), .inst(inst));
wire [31:0] multiplier_result;
wire [31:0] alu_out;
wire alu_equal;
wire alu_less;
multiplier mul(.multiplier_result(multiplier_result),
.op1(alu_op1), .op2(alu_op2), .mul_sel(mul_sel));
alu alu(.alu_out(alu_out),
.op1(alu_op1), .op2(alu_op2), .multiplier_result(multiplier_result), .alu_sel(alu_sel));
branch_jump bj(.branch_taken(branch_taken), .branch_target(branch_target),
.jump(jump_taken), .jump_target(jump_target),
.inst(inst), .pc(pc), .rd1(rf_rd1), .alu_out(alu_out));
/* MEMORY and WRITEBACK */
wire [31:0] mem_data;
reg [31:0] load_data;
always @ (posedge clk) begin
if (reset)
load_data <= 32'b0;
else if (dmem_data_valid)
load_data <= request_data;
end
data_memory m(.inst(inst), .data(rf_rd2), .addr(alu_out),
.memory_addr(dmem_addr),
.write_data(dmem_write_data), .write_mask(dmem_write_mask),
.load_data(load_data), .output_data(mem_data));
wire [31:0] pcr_data;
control_processor cp(.clk(clk), .reset(reset), .stall(stall),
.inst(inst), .pc(pc),
.enable(cp_enable),
.pcr_write_data({1'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1),
.pcr(ex_rs1), .cmd(pcr_cmd), .pcr_data(pcr_data),
.interrupt(interrupt), .evec(evec),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
always @ (*) begin
case (wb_sel)
`WB_ALU: rf_wdata = alu_out;
`WB_MEM: rf_wdata = mem_data;
`WB_PC4: rf_wdata = pc + 4;
`WB_PCR: rf_wdata = pcr_data;
default: rf_wdata = 32'b0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
module Controlador_Gato(
clk,
reset_all,
reset_game,
cuadro,
vertical,
horizontal,
cruzada,
state,
boton_arriba_reg, boton_abajo_reg, boton_izq_reg, boton_der_reg, boton_elige_reg,
turno_p1_wire, turno_p2_wire,
win_game_wire, //Gana Jugador 2
loss_game_wire, //Gana Jugador 1
tie_game_wire, //Juego empatado
c1_out_registro,
c2_out_registro,
c3_out_registro,
c4_out_registro,
c5_out_registro,
c6_out_registro,
c7_out_registro,
c8_out_registro,
c9_out_registro
);
input clk, reset_all, reset_game;
output [2:0] state;
output [3:0] cuadro;
output [1:0] vertical, horizontal, cruzada;
output turno_p1_wire, turno_p2_wire;
output win_game_wire, loss_game_wire, tie_game_wire;
wire p1_mm_wire, p2_mm_wire;
wire p1_tie_wire, p1_loss_wire, p1_win_wire;
wire p2_tie_wire, p2_loss_wire, p2_win_wire;
wire verifica_status_wire;
//reg boton_arriba_reg, boton_abajo_reg, boton_izq_reg, boton_der_reg, boton_elige_reg;
input boton_arriba_reg, boton_abajo_reg, boton_izq_reg, boton_der_reg, boton_elige_reg;
wire [1:0]
c1_in_registro,
c2_in_registro,
c3_in_registro,
c4_in_registro,
c5_in_registro,
c6_in_registro,
c7_in_registro,
c8_in_registro,
c9_in_registro;
output [1:0]
c1_out_registro,
c2_out_registro,
c3_out_registro,
c4_out_registro,
c5_out_registro,
c6_out_registro,
c7_out_registro,
c8_out_registro,
c9_out_registro;
Gato_FSM maquina (
.clk (clk),
.reset (reset_all),
.state (state),
.p1_mm (p1_mm_wire),
.p2_mm (p2_mm_wire),
.p1_tie (p1_tie_wire),
.p1_loss (p1_loss_wire),
.p1_win (p1_win_wire),
.p2_tie (p2_tie_wire),
.p2_loss (p2_loss_wire),
.p2_win (p2_win_wire),
.verifica_status (verifica_status_wire),
.turno_p1 (turno_p1_wire),
.turno_p2 (turno_p2_wire),
.win_game (win_game_wire),
.loss_game (loss_game_wire),
.tie_game (tie_game_wire)
);
Selector_Casillas selector (
.clk (clk),
.boton_arriba (boton_arriba_reg),
.boton_abajo (boton_abajo_reg),
.boton_izq (boton_izq_reg),
.boton_der (boton_der_reg),
.boton_elige (boton_elige_reg),
.turno_p1 (turno_p1_wire),
.turno_p2 (turno_p2_wire),
.guarda_c1 (c1_in_registro),
.guarda_c2 (c2_in_registro),
.guarda_c3 (c3_in_registro),
.guarda_c4 (c4_in_registro),
.guarda_c5 (c5_in_registro),
.guarda_c6 (c6_in_registro),
.guarda_c7 (c7_in_registro),
.guarda_c8 (c8_in_registro),
.guarda_c9 (c9_in_registro),
.p1_mm (p1_mm_wire),
.p2_mm (p2_mm_wire),
.cuadro (cuadro)
);
Registro_Juego registro (
.clk (clk),
.reset_in (reset_all),
.c1_clear_in (reset_all),
.c2_clear_in (reset_all),
.c3_clear_in (reset_all),
.c4_clear_in (reset_all),
.c5_clear_in (reset_all),
.c6_clear_in (reset_all),
.c7_clear_in (reset_all),
.c8_clear_in (reset_all),
.c9_clear_in (reset_all),
.c1_in (c1_in_registro),
.c2_in (c2_in_registro),
.c3_in (c3_in_registro),
.c4_in (c4_in_registro),
.c5_in (c5_in_registro),
.c6_in (c6_in_registro),
.c7_in (c7_in_registro),
.c8_in (c8_in_registro),
.c9_in (c9_in_registro),
.c1_out (c1_out_registro),
.c2_out (c2_out_registro),
.c3_out (c3_out_registro),
.c4_out (c4_out_registro),
.c5_out (c5_out_registro),
.c6_out (c6_out_registro),
.c7_out (c7_out_registro),
.c8_out (c8_out_registro),
.c9_out (c9_out_registro)
);
Verificador_gato verificador (
.verifica_status (verifica_status_wire),
.p1_tie (p1_tie_wire),
.p1_loss (p1_loss_wire),
.p1_win (p1_win_wire),
.p2_tie (p2_tie_wire),
.p2_loss (p2_loss_wire),
.p2_win (p2_win_wire),
.linea_horizontal (horizontal),
.linea_vertical (vertical),
.linea_cruzada (cruzada),
.reg_c1 (c1_out_registro),
.reg_c2 (c2_out_registro),
.reg_c3 (c3_out_registro),
.reg_c4 (c4_out_registro),
.reg_c5 (c5_out_registro),
.reg_c6 (c6_out_registro),
.reg_c7 (c7_out_registro),
.reg_c8 (c8_out_registro),
.reg_c9 (c9_out_registro)
);
endmodule
|
`timescale 1ps/1ps
module sim_fsusb_foot
(inout dp,
inout dm);
localparam HALFBIT = 41667;
localparam BIT = 83333;
reg vp_noise_inject;
reg vm_noise_inject;
reg vm_noise, vp_noise;
integer delay_amount;
initial begin
vp_noise = 1'b0;
vp_noise_inject = 1'b0;
#1_200_000_000;
forever begin
vp_noise = ~vp_noise;
vp_noise_inject = 1'b0;
#232238251;
vp_noise_inject = 1'b1;
#;
end
end
initial begin
vm_noise = 1'b0;
vm_noise_inject = 1'b0;
#1_300_000_000;
forever begin
vm_noise = ~vm_noise;
vm_noise_inject = 1'b0;
#158983124;
vm_noise_inject = 1'b1;
#832389;
vm_noise_inject = 1'b0;
end
end
reg oe = 1'b0;
reg vp = 1'b1;
reg vm = 1'b0;
assign dp = vp_noise_inject ? vp_noise : (oe ? vp : 1'bz);
assign dm = vm_noise_inject ? vm_noise : (oe ? vm : 1'bz);
integer i;
wire [7:0] sync = 8'b1101_0101;
reg decoded, prev_state, save_bit;
integer byte_count, bit_count, num_rx_ones;
reg [7:0] rx_byte;
reg [7:0] rx_pkt[63:0];
`include "usb_pids.v"
`include "usb_defs.v"
integer tx_num_ones = 0;
/*
task tx_sync;
integer bit_cnt;
begin
vp = 1'b1;
vm = 1'b0;
oe = 1'b1;
#BIT;
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
vp = sync[bit_cnt];
vm = ~sync[bit_cnt];
#BIT;
end
tx_nrzi = 1'b1;
tx_prev_bit = 1'b1;
tx_num_ones = 1'b1;
end
endtask
*/
task tx_byte;
input [7:0] byte;
integer bit_cnt;
reg bit;
begin
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
bit = byte[bit_cnt]; // save some typing
if (bit) begin
tx_num_ones = tx_num_ones + 1'b1;
if (tx_num_ones >= 7) begin
// bit stuffing... throw a bit-flip in there
//nrzi = ~nrzi;
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
#BIT; // to send a "1" we just leave the lines the same
end else begin
// to send a "0" we toggle the lines
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
end
end
endtask
task tx_32bits_be;
input [31:0] bits;
begin
tx_byte(bits[31:24]);
tx_byte(bits[23:16]);
tx_byte(bits[15:8]);
tx_byte(bits[7:0]);
end
endtask
task tx_eop;
begin
vp = 1'b0;
vm = 1'b0;
#BIT;
#BIT;
vp = 1'b1;
#BIT;
oe = 1'b0;
end
endtask
task tx_warmup;
begin
oe = 1'b1;
vp = 1'b1;
vm = 1'b0;
#BIT;
end
endtask
task rx_data0;
integer len;
begin
len = byte_count - 3;
$display("%t rx data0 len %d ", $time, len);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
tx_byte(PID_ACK);
tx_eop();
end
endtask
integer rx_in_cnt = 0;
task rx_in;
begin
$display("%t rx IN", $time);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
if (rx_in_cnt == 0) begin
$display("%t sending NAK", $time);
tx_byte(PID_NAK);
end else if (rx_in_cnt == 5) begin
$display("not transmitting anything in response to this IN request...");
end else begin
if (rx_pkt[1] == 8'h91) begin
$display("%t received IN pkt on EP1", $time);
tx_byte(PID_DATA1); // TODO: toggle data0 / data1
tx_foot_pkt();
/*
for (i = 0; i < 64; i = i + 1) begin
//$display("%t tx 0x%02h", $time, 64-i);
tx_byte(64-i);
end
*/
end else if (rx_pkt[1] == 8'h00 | rx_pkt[1] == 8'h01 | rx_pkt[1] == USB_DEV_ADDR) begin
$display("%t responding to IN pkt on EP0", $time);
tx_byte(PID_DATA1);
// for now, always just a zero-length packet
tx_byte(0);
tx_byte(0);
end else begin
$display("%t unhandled IN request!", $time);
for (i = 0; i < 64; i = i + 1) begin
$display("rx %d = 0x%02h", $time, rx_pkt[i]);
//$display("%t tx 0x%02h", $time, 64-i);
//tx_byte(64-i);
end
end
end
tx_eop();
rx_in_cnt = rx_in_cnt + 1;
end
endtask
task tx_foot_pkt;
begin
tx_32bits_be(32'h0000abcd);
tx_32bits_be(32'h12345678);
tx_32bits_be(32'h01000200); // 0
tx_32bits_be(32'h03000400); // 2
tx_32bits_be(32'h05000600); // 4
tx_32bits_be(32'h07000800); // 6
tx_32bits_be(32'h09000a00); // 8
tx_32bits_be(32'h0b000c00); // 10
tx_32bits_be(32'h0d000e00); // 12
tx_32bits_be(32'h0f001000); // 14
tx_32bits_be(32'h00000000);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
end
endtask
initial begin
oe = 1'b0;
vp = 1'b0;
vm = 1'b0;
//$printtimescale;
// wait for USB reset
wait(~dp && ~dm);
$display("%t usb reset start", $time);
wait(dp && ~dm);
$display("%t usb reset end", $time); // todo: time reset pulse length
wait(~dp && ~dm);
$display("%t usb reset2 start", $time);
wait(dp && ~dm);
$display("%t usb reset2 end", $time); // todo: time reset pulse length
forever begin
num_rx_ones = 0;
bit_count = 0;
byte_count = 0;
rx_byte = 8'h0;
prev_state = 1;
decoded = 0;
save_bit = 1; // this is set to 0 when we get a stuffed bit
wait(~dp);
//$display("%t fsusb pkt start", $time);
#41667; // shift to the middle of a bit period
for (i = 0; i < 8; i = i + 1) begin
//$display("%t sync bit", $time);
if (dp != ~dm) begin
$display("illegal usb state at %t", $time);
//#1000 $finish();
end
if (sync[i] != dm) begin
$display("sync fail at %t", $time);
//#1000 $finish();
end
#83333; // skip over a full bit
end
//$display("%t sync OK", $time);
// decode the NRZI data
while (~(dp == 0 & dm == 0)) begin
if (dp != ~dm) begin
$display("%t illegal usb state", $time);
//#1000 $finish();
end
if (prev_state != dm) begin
decoded = 0;
prev_state = dm;
if (num_rx_ones == 6) begin
$display("%t stuffed bit detected", $time);
save_bit = 0; // it's a stuffed bit; ignore it
end
else
save_bit = 1;
num_rx_ones = 0;
//$display("%t rx flip @ %d", $time, bit_count);
end else begin
decoded = 1;
num_rx_ones = num_rx_ones + 1;
save_bit = 1; // ones are never stuffed
if (num_rx_ones > 6) begin
$display("%t received more than 6 ones in a row.", $time);
//#100000 $finish();
end
//$display("%t rx same @ %d", $time, bit_count);
end
if (save_bit) begin
rx_byte = { decoded, rx_byte[7:1] };
bit_count = bit_count + 1;
end
if (bit_count == 8) begin
rx_pkt[byte_count] = rx_byte;
if (byte_count == 0) begin
case (rx_byte)
PID_SOF: $display("%t SOF", $time);
PID_SETUP: $display("%t SETUP", $time);
PID_DATA0: $display("%t DATA0", $time);
PID_IN : $display("%t IN", $time);
PID_ACK : $display("%t ACK", $time);
default: begin
$display("%t ERROR: rx unknown PID (0x%02h)", $time, rx_byte);
//$finish();
end
endcase
end
else
$display("%t rx 0x%02h", $time, rx_byte);
byte_count = byte_count + 1;
bit_count = 0;
end
#83333; // skip over a full bit
end
if (num_rx_ones == 6) begin
$display("%t expected to see bit-stuffing right before SE0", $time);
//#100000 $finish();
end
if (bit_count != 0) begin
$display("%t SE0 seen at non-byte boundary", $time);
//#5000 $finish();
end
//$display("%t found SE0", $time);
#83333;
if (dp != 0 | dm != 0) begin
$display("%t SE0 state wasn't two bits long", $time);
//#1000 $finish();
end
#83333;
if (dp != 1 | dm != 0) begin
$display("%t didn't finish EOP with J state", $time);
//#1000 $finish();
end
#83.333;
$display("%t packet RX complete", $time);
case (rx_pkt[0])
PID_SOF: ;
PID_SETUP: ;
PID_DATA0: rx_data0();
PID_IN: rx_in();
PID_ACK: ;
default: begin
$display("%t unknown rx PID (0x%02h)", $time, rx_pkt[0]);
//$finish();
end
endcase
//if (rx_pkt[0] == PID_DATA0)
// rx_data0();
end
end
endmodule
|
#include <bits/stdc++.h> clock_t t = clock(); namespace my_std { using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> inline T rnd(T l, T r) { return uniform_int_distribution<T>(l, r)(rng); } template <typename T> inline bool chkmax(T& x, T y) { return x < y ? x = y, 1 : 0; } template <typename T> inline bool chkmin(T& x, T y) { return x > y ? x = y, 1 : 0; } template <typename T> inline void read(T& t) { t = 0; char f = 0, ch = getchar(); double d = 0.1; while (ch > 9 || ch < 0 ) f |= (ch == - ), ch = getchar(); while (ch <= 9 && ch >= 0 ) t = t * 10 + ch - 48, ch = getchar(); if (ch == . ) { ch = getchar(); while (ch <= 9 && ch >= 0 ) t += d * (ch ^ 48), d *= 0.1, ch = getchar(); } t = (f ? -t : t); } template <typename T, typename... Args> inline void read(T& t, Args&... args) { read(t); read(args...); } char __sr[1 << 21], __z[20]; int __C = -1, __zz = 0; inline void Ot() { fwrite(__sr, 1, __C + 1, stdout), __C = -1; } inline void print(register int x) { if (__C > 1 << 20) Ot(); if (x < 0) __sr[++__C] = - , x = -x; while (__z[++__zz] = x % 10 + 48, x /= 10) ; while (__sr[++__C] = __z[__zz], --__zz) ; __sr[++__C] = n ; } void file() {} inline void chktime() {} long long ksm(long long x, int y) { long long ret = 1; for (; y; y >>= 1, x = x * x) if (y & 1) ret = ret * x; return ret; } } // namespace my_std using namespace my_std; int n; int ans[10][333][10] = { {{2}, {3, 1, 2, 3}, {3, 1, 2, 3}}, {{4}, {3, 1, 2, 3}, {3, 1, 2, 4}, {3, 1, 3, 4}, {3, 2, 3, 4}}, {{6}, {3, 5, 4, 2}, {3, 3, 1, 5}, {4, 4, 5, 2, 3}, {4, 4, 3, 2, 1}, {3, 4, 2, 1}, {3, 3, 1, 5}}, {{9}, {4, 1, 5, 2, 4}, {4, 1, 6, 3, 4}, {4, 2, 6, 3, 5}, {3, 1, 2, 6}, {3, 2, 3, 4}, {3, 1, 5, 3}, {3, 1, 2, 3}, {3, 4, 5, 6}, {3, 4, 5, 6}}}; int L[333][2], R[333][2]; int Ans[333 * 333][10], cnt; void addcir(int s, int l) { for (int i = (1); i <= (ans[s][0][0]); i++) { assert(ans[s][i][0]); ++cnt; for (int j = (0); j <= (ans[s][i][0]); j++) Ans[cnt][j] = ans[s][i][j] + (!!j) * l; } } void solve(int l, int r) { int s = r - l + 1; if (s <= 6) return addcir(s - 3, l); int x, y, c; if (s & 1) { x = 3, y = (s - 3) >> 1, c = 1; ++l; L[1][0] = l, L[1][1] = l + 1; L[2][0] = l, L[2][1] = l + 2; L[3][0] = l + 1, L[3][1] = l + 2; for (int i = (1); i <= (y); i++) for (int k = (0); k <= (1); k++) R[i][k] = l + 3 + 2 * (i - 1) + k; --l; addcir(0, l); } else { x = 2, y = (s - 4) >> 1, c = 2; ++l; for (int i = (1); i <= (x); i++) for (int k = (0); k <= (1); k++) L[i][k] = l + 2 * (i - 1) + k; for (int i = (1); i <= (y); i++) for (int k = (0); k <= (1); k++) R[i][k] = l + 4 + 2 * (i - 1) + k; --l; addcir(1, l); } for (int i = (1); i <= (x); i++) for (int j = (1); j <= (y); j++) for (int k = (1); k <= (c); k++) ++cnt, Ans[cnt][0] = 4, Ans[cnt][1] = L[i][0], Ans[cnt][2] = R[j][0], Ans[cnt][3] = L[i][1], Ans[cnt][4] = R[j][1]; solve(l + ((s & 1) ? 3 : 4), r); } int main() { file(); read(n); solve(0, n - 1); printf( %d n , cnt); for (int i = (1); i <= (cnt); i++) { for (int j = (0); j <= (Ans[i][0]); j++) printf( %d , Ans[i][j]); puts( ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_1_V
`define SKY130_FD_SC_MS__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; int a[m], b[k], c[105] = {0}; for (int i = 0; i < m; i++) { cin >> a[i]; } for (int i = 0; i < k; i++) { cin >> b[i]; } for (int i = 0; i < m; i++) { c[a[i]] = 1; } for (int i = 0; i < k; i++) { if (c[b[i]] == 0) c[b[i]] = 2; } for (int i = 1; i <= n; i++) { cout << c[i] << ; } return 0; }
|
module top;
parameter le0 = 1'b0 <-> 1'b0; // 1'b1
parameter le1 = 1'b0 <-> 1'b1; // 1'b0
parameter le2 = 1'b0 <-> 1'bz; // 1'bx
parameter le3 = 1'b0 <-> 1'bx; // 1'bx
parameter le4 = 1'b1 <-> 1'b0; // 1'b0
parameter le5 = 1'b1 <-> 1'b1; // 1'b1
parameter le6 = 1'b1 <-> 1'bz; // 1'bx
parameter le7 = 1'b1 <-> 1'bx; // 1'bx
parameter le8 = 1'bz <-> 1'b0; // 1'bx
parameter le9 = 1'bz <-> 1'b1; // 1'bx
parameter lea = 1'bz <-> 1'bz; // 1'bx
parameter leb = 1'bz <-> 1'bx; // 1'bx
parameter lec = 1'bx <-> 1'b0; // 1'bx
parameter led = 1'bx <-> 1'b1; // 1'bx
parameter lee = 1'bx <-> 1'bz; // 1'bx
parameter lef = 1'bx <-> 1'bx; // 1'bx
parameter [1:0] lew = 4'b0110 <-> 4'b1001; // 2'b01
parameter [1:0] lews = $signed(4'b0110 <-> 4'b1001); // 2'b11
parameter ler0 = 0.0 <-> 1'b0; // 1'b1
parameter ler1 = 1'b0 <-> 2.0; // 1'b0
parameter ler2 = 2.0 <-> 1'bx; // 1'bx
parameter ler3 = -5.0 <-> 2.0; // 1'b1
reg pass;
initial begin
pass = 1'b1;
if (le0 !== 1'b1) begin
$display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", le0);
pass = 1'b0;
end
if (le1 !== 1'b0) begin
$display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", le1);
pass = 1'b0;
end
if (le2 !== 1'bx) begin
$display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", le2);
pass = 1'b0;
end
if (le3 !== 1'bx) begin
$display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", le3);
pass = 1'b0;
end
if (le4 !== 1'b0) begin
$display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", le4);
pass = 1'b0;
end
if (le5 !== 1'b1) begin
$display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", le5);
pass = 1'b0;
end
if (le6 !== 1'bx) begin
$display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", le6);
pass = 1'b0;
end
if (le7 !== 1'bx) begin
$display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", le7);
pass = 1'b0;
end
if (le8 !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", le8);
pass = 1'b0;
end
if (le9 !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", le9);
pass = 1'b0;
end
if (lea !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", lea);
pass = 1'b0;
end
if (leb !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", leb);
pass = 1'b0;
end
if (lec !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", lec);
pass = 1'b0;
end
if (led !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", led);
pass = 1'b0;
end
if (lee !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", lee);
pass = 1'b0;
end
if (lef !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", lef);
pass = 1'b0;
end
if (ler0 !== 1'b1) begin
$display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0);
pass = 1'b0;
end
if (ler1 !== 1'b0) begin
$display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b1", ler1);
pass = 1'b0;
end
if (ler2 !== 1'bx) begin
$display("FAILED: 2.0 <-> 1'bx returned %b not 1'b1", ler2);
pass = 1'b0;
end
if (ler3 !== 1'b1) begin
$display("FAILED: -5.0 <-> 2.0 returned %b not 1'b1", ler3);
pass = 1'b0;
end
if (lew !== 2'b01) begin
$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew);
pass = 1'b0;
end
if (lews !== 2'b11) begin
$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
/**
* sregsbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire ASYNC_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (set , ASYNC_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, set, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( ASYNC_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( ASYNC === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { s = s * 10 + ch - 0 ; ch = getchar(); } return s * w; } int n; int a[N]; void solve() { n = read(); int sum = 0; for (int i = 1; i <= n; i++) a[i] = read(), sum += a[i]; for (int i = 2; i * i <= sum; i++) { if (sum % i == 0) { printf( %d n , n); for (int i = 1; i <= n; i++) printf( %d , i); puts( ); return; } } printf( %d n , n - 1); bool ok = 0; for (int i = 1; i <= n; i++) { if (!ok && a[i] % 2 == 1) { ok = 1; continue; } printf( %d , i); } puts( ); } int main() { int T = read(); while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<double, double> p[100100]; double dt[100100]; double db[100100]; double da[100100]; int main() { double ax, ay, bx, by, tx, ty; int n; cin >> ax >> ay >> bx >> by >> tx >> ty; cin >> n; double ans = 0; scanf( %lf %lf , &p[0].first, &p[0].second); ans += sqrt((p[0].first - tx) * (p[0].first - tx) + (p[0].second - ty) * (p[0].second - ty)); dt[0] = ans; for (int i = 1; i < n; i++) { scanf( %lf %lf , &p[i].first, &p[i].second); dt[i] = sqrt((p[i].first - tx) * (p[i].first - tx) + (p[i].second - ty) * (p[i].second - ty)); ans += dt[i]; } ans *= 2; for (int i = 0; i < n; i++) { da[i] = sqrt((p[i].first - ax) * (p[i].first - ax) + (p[i].second - ay) * (p[i].second - ay)); db[i] = sqrt((p[i].first - bx) * (p[i].first - bx) + (p[i].second - by) * (p[i].second - by)); } double p1, p2, p3, p4; double Da = 1.7976931348623158e+308, Db = 1.7976931348623158e+308; int indexofa = -1; int indexofb = -1; for (int i = 0; i < n; i++) { if (da[i] - dt[i] < Da) { Da = da[i] - dt[i]; indexofa = i; } } for (int i = 0; i < n; i++) { if (db[i] - dt[i] < Db && i != indexofa) { Db = db[i] - dt[i]; indexofb = i; } } p1 = Da + Db; Da = 1.7976931348623158e+308, Db = 1.7976931348623158e+308; indexofa = -1; indexofb = -1; for (int i = 0; i < n; i++) { if (db[i] - dt[i] < Db) { Db = db[i] - dt[i]; indexofb = i; } } for (int i = 0; i < n; i++) { if (da[i] - dt[i] < Da && i != indexofb) { Da = da[i] - dt[i]; indexofa = i; } } p2 = Da + Db; Db = 1.7976931348623158e+308; indexofb = -1; for (int i = 0; i < n; i++) { if (db[i] - dt[i] < Db) { Db = db[i] - dt[i]; indexofb = i; } } p3 = Db; Da = 1.7976931348623158e+308; indexofa = -1; for (int i = 0; i < n; i++) { if (da[i] - dt[i] < Da) { Da = da[i] - dt[i]; indexofa = i; } } p4 = Da; printf( %.12lf , min(min(p1, p2), min(p3, p4)) + ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long double a[100009][2]; long double maxi(long double a, long double b) { if (a > b) return a; else return b; } bool solve(long double mid, int n, long double p) { long double req = 0; for (int i = 0; i < n; i++) { req += maxi(0.00, mid * a[i][0] - a[i][1]); } if (req > mid * p) return false; else return true; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long double n, p, sum = 0, count = 0, m, flag = 0, ans = 0, k; cin >> n >> p; long double l = 0, r = 1e10; for (int i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1]; } while (flag < 1000) { long double m = (l + r) / 2; if (solve(m, n, p)) ans = m, l = m; else r = m; flag++; } if (ans >= 1e10) { cout << -1; return 0; } cout << setprecision(8) << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> tmp; vector<vector<int>> sol[4]; int lov[7][7]; int hero(string s) { if (s == Troll ) return 0; if (s == Dracul ) return 1; if (s == Anka ) return 2; if (s == Snowy ) return 3; if (s == Hexadecimal ) return 4; if (s == Chapay ) return 5; else return 6; } void rec(int i, int a, int b, int c) { if (i == 7) { int z[] = {a, b, c}; sort(z, z + 3); if (z[2] == 5 && z[1] == 1 && z[0] == 1) sol[0].push_back(tmp); if (z[2] == 4 && z[1] == 2 && z[0] == 1) sol[1].push_back(tmp); if (z[2] == 3 && z[1] == 3 && z[0] == 1) sol[2].push_back(tmp); if (z[2] == 3 && z[1] == 2 && z[0] == 2) sol[3].push_back(tmp); return; } tmp.push_back(1); rec(i + 1, a + 1, b, c); tmp.pop_back(); tmp.push_back(2); rec(i + 1, a, b + 1, c); tmp.pop_back(); tmp.push_back(3); rec(i + 1, a, b, c + 1); tmp.pop_back(); } int main() { rec(0, 0, 0, 0); int arr[4][3]; pair<int, int> exp[3]; int mini = 1e9, maxi = 0; set<int> minI; arr[0][0] = 5, arr[0][1] = 1, arr[0][2] = 1; arr[1][0] = 4, arr[1][1] = 2, arr[1][2] = 1; arr[2][0] = 3, arr[2][1] = 3, arr[2][2] = 1; arr[3][0] = 3, arr[3][1] = 2, arr[3][2] = 2; int n; cin >> n; for (int i = 0; i < n; i++) { string s, tmp, s2; cin >> s >> tmp >> s2; int x = hero(s), y = hero(s2); lov[x][y] = 1; } for (int i = 0; i < 3; i++) { cin >> exp[i].second; exp[i].first = i; } for (int i = 0; i < 4; i++) { int a = 0; do { int ans[3] = {}; for (int j = 0; j < 3; j++) ans[j] = exp[j].second / arr[i][j]; sort(ans, ans + 3); if (ans[2] - ans[0] < mini) minI.clear(); if (ans[2] - ans[0] <= mini) minI.insert(i); mini = min(ans[2] - ans[0], mini); a++; } while (next_permutation(exp, exp + 3)); } for (set<int>::iterator it = minI.begin(); it != minI.end(); it++) { for (int i = 0; i < sol[*it].size(); i++) { int tmpA = 0; for (int x = 0; x < 7; x++) { for (int y = 0; y < 7; y++) { if (x != y && sol[*it][i][x] == sol[*it][i][y] && lov[x][y]) tmpA++; } } maxi = max(tmpA, maxi); } } cout << mini << << maxi << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long f = n * (n - 1) * (n - 2) * (n - 3) * (n - 4); cout << (f / 120) * ((n * n) - (4 * n) + 37) / 42; return 0; }
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#include <bits/stdc++.h> using namespace std; int arr[30001]; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> arr[i]; } int dp1 = arr[1]; int dp2 = 0; bool fail = 0; for (int i = 2; i < n; i++) { arr[i] = arr[i] - dp2; if (arr[i] < 0) { fail = 1; break; } if (arr[i] > dp1) { arr[i] = arr[i] - dp1; dp2 = dp2 + arr[i]; } else { dp1 = arr[i]; } } if (dp2 > arr[n]) { fail = 1; } if (fail) { cout << NO << n ; } else { cout << YES << n ; } } }
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// This module generate enable and two-bit selector for verifying a 2-to-4 decoder
module stimulus #(parameter M = 8, T = 10) (
output reg [1:0] sel,
output reg en
);
bit [2:0] i;
initial begin
sel = 0;
en = 1'bx;
#T;
sel = 1;
#T;
sel = 2;
#T;
sel = 3;
#T;
sel = 2'bxx;
#T;
en = 0;
#T;
en = 1;
#T;
en = 1'bx;
#T;
for (i = 0; i < M; i=i+1) begin
#T;
{sel, en} = i;
end
end
endmodule
// This module always checks that y complies with a decoding operation
module check (input [1:0] sel, input en, input [0:3] y);
always @(sel, en, y) begin
if (en == 0) begin
#1;
if (y !== 4'b0000) begin
$display("ERROR");
$finish;
end
else if (en == 1) begin
#1;
case (sel)
0: if (y !== 4'b1000) begin
$display("ERROR");
$finish;
end
1: if (y !== 4'b0100) begin
$display("ERROR");
$finish;
end
2: if (y !== 4'b0010) begin
$display("ERROR");
$finish;
end
3: if (y !== 4'b0001) begin
$display("ERROR");
$finish;
end
default: if (y !== 4'b0000) begin
$display("ERROR");
$finish;
end
endcase
end // else
else begin
if (y !== 4'b0000) begin
$display("ERROR");
$finish;
end
end
end // if
end
endmodule
module test;
parameter M = 8;
parameter T = 10;
parameter S = 4*M*T + 40;
wire [1:0] sel;
wire en;
wire [0:3] y;
stimulus #(M, T) stim (.sel(sel), .en(en) );
dec2to4 duv (.sel(sel), .en(en), .y(y) );
check check (.sel(sel), .en(en), .y(y) );
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; char IO; inline long long rd() { long long res = 0, f = 1; while (IO = getchar(), IO < 48 || IO > 57) if (IO == - ) f = 0; do res = (res << 3) + (res << 1) + (IO ^ 48); while (IO = getchar(), IO >= 48 && IO <= 57); if (f) return res; return -res; } const long long P = 1e9 + 7, M = 1e5 + 5; long long fac[M], pw[M], inv[M]; char str[M]; long long Pow(long long a, long long b) { long long res = 1; for (; b; b >>= 1, a = a * a % P) if (b & 1) res = res * a % P; return res; } void init() { fac[0] = pw[0] = 1; for (long long i = 1, iend = M - 5; i <= iend; ++i) { fac[i] = fac[i - 1] * i % P; pw[i] = pw[i - 1] * 10 % P; } inv[M - 5] = Pow(fac[M - 5], P - 2); for (long long i = M - 5, iend = 1; i >= iend; --i) inv[i - 1] = inv[i] * i % P; } long long C(long long n, long long m) { if (n < 0 || m < 0 || n < m) return 0; return fac[n] * inv[m] % P * inv[n - m] % P; } int main() { init(); long long n = rd(), m = rd(), s = 0, ans = 0; scanf( %s , str + 1); for (long long i = n, iend = 1; i >= iend; --i) { ans = (ans + (s + C(i - 1, m) * pw[n - i]) * (str[i] - 0 ) % P) % P; s = (s + C(i - 2, m - 1) * pw[n - i] % P); } cout << ans << endl; }
|
//
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// force3.17A - Template 1 - force reg_lvalue = constant.
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
#50 ;
if(val2 !== 4'b1010)
$display("FAILED");
else
$display("PASSED");
end
initial
begin
#20;
force val2 = 4'b1010;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, l, ans = 0, sign = 1, count = 0; string s; getline(cin, s); l = s.size(); vector<int> v; for (i = 0; i < l; i++) { if (s[i] == ? ) { v.push_back(sign); sign == 1 ? count++ : count--; } else if (s[i] == + ) sign = 1; else if (s[i] == - ) sign = -1; else if (s[i] != && s[i] != = ) { ans = 10 * ans + s[i] - 0 ; } } int remain = ans - count; vector<int> v1(v.size(), 1); for (i = 0; i < v.size(); i++) { if (v[i] == 1 && remain > 0) { int old = v1[i]; v1[i] = min(ans, v1[i] + remain); remain -= (v1[i] - old); } else if (v[i] == -1 && remain < 0) { int old = v1[i]; v1[i] = min(ans, v1[i] - remain); remain += (v1[i] - old); } } if (remain != 0) { printf( Impossible n ); return 0; } printf( Possible n ); for (i = 0; i < v.size(); i++) { if (i == 0) { printf( %d , v1[i]); } else { printf( %c %d , v[i] == 1 ? + : - , v1[i]); } } printf( = %d n , ans); return 0; }
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// vg93 interface
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
// #1F - vg93 command/state reg {0,0} - not here!
// #3F - vg93 track register {0,1} - not here!
// #5F - vg93 sector register {1,0} - not here!
// #7F - vg93 data register {1,1} - not here!
// #FF - output "system" reg/input (DRQ+IRQ) reg
// output: d6 - FM/MFM - NOT USED ANYWHERE! -> skipped
// d4 - disk side - inverted out
// d3 - head load - for HRDY pin of vg93
// d2 - /RESET for vg93 - must be zero at system reset
// d1:d0 - disk drive select - to the 74138
// input: d7 - /INTRQ - resynced at CPU clock
// d6 - /DRQ - .....................
//
// current limitations:
// 1. read clock regenerator is made of simple counter, as in pentagon128
// 1. write precompensation is based only on SL/SR/TR43 signals
`include "../include/tune.v"
module vg93(
input zclk, // Z80 cpu clock
input rst_n,
input fclk, // fpga 28 MHz clock
output vg_clk,
output reg vg_res_n,
input [7:0] din, // data input from CPU
output intrq,drq, // output signals for the read #FF (not here)
input vg_wrFF, // when TRDOS port #FF written - positive strobe
output reg vg_hrdy,
output wire vg_rclk,
output wire vg_rawr,
output reg [1:0] vg_a, // disk drive selection
output reg vg_wrd,
output reg vg_side,
input step, // step signal from VG93
input vg_sl,vg_sr,vg_tr43,
input rdat_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd
);
localparam WRDELAY_OUTER_LEFT = 4'd4;
localparam WRDELAY_OUTER_RIGHT = 4'd11;
localparam WRDELAY_INNER_LEFT = 4'd0; // minimal delay is for maximum shift left
localparam WRDELAY_INNER_RIGHT = 4'd14; // maximal delay is for maximum shift right
localparam WRDELAY_STANDARD = 4'd7; // no-shift
reg [2:0] vgclk_div7;
wire vgclk_strobe7;
reg [1:0] vgclk_div4;
reg [2:0] step_pulse;
reg [2:0] drq_pulse;
wire step_pospulse;
wire drq_pospulse;
reg turbo_state;
reg [1:0] intrq_sync;
reg [1:0] drq_sync;
reg [1:0] sl_sync,sr_sync,tr43_sync;
reg [2:0] wd_sync;
wire sl,sr,tr43,wd;
reg [3:0] wrdelay_cnt;
wire delay_end;
reg [3:0] wrwidth_cnt;
wire wrwidth_ena;
// reg [4:0] rdat_sync;
// reg rdat_edge1, rdat_edge2;
// wire rdat;
// reg [3:0] rwidth_cnt;
// wire rwidth_ena;
// reg [5:0] rclk_cnt;
// wire rclk_strobe;
// VG93 clocking and turbo-mode
always @(posedge fclk)
begin
step_pulse[2:0] <= { step_pulse[1:0], step};
drq_pulse[2:0] <= { drq_pulse[1:0], vg_drq};
end
assign step_pospulse = ( step_pulse[1] & (~step_pulse[2]) );
assign drq_pospulse = ( drq_pulse[1] & ( ~drq_pulse[2]) );
always @(posedge fclk,negedge rst_n)
begin
if( !rst_n )
turbo_state <= 1'b0;
else
begin
if( drq_pospulse )
turbo_state <= 1'b0;
else if( step_pospulse )
turbo_state <= 1'b1;
end
end
assign vgclk_strobe7 = (vgclk_div7[2:1] == 2'b11); // 28/7=4MHz freq strobe
always @(posedge fclk)
begin
if( vgclk_strobe7 )
vgclk_div7 <= 3'd0;
else
vgclk_div7 <= vgclk_div7 + 3'd1;
end
always @(posedge fclk)
begin
if( vgclk_strobe7 )
begin
vgclk_div4[0] <= ~vgclk_div4[1];
if( turbo_state )
vgclk_div4[1] <= ~vgclk_div4[1];
else
vgclk_div4[1] <= vgclk_div4[0];
end
end
assign vg_clk = vgclk_div4[1];
// input/output for TR-DOS port #FF
always @(posedge zclk, negedge rst_n) // CHANGE IF GO TO THE positive/negative strobes instead of zclk!
begin
if( !rst_n )
vg_res_n <= 1'b0;
else if( vg_wrFF )
{ vg_side, vg_hrdy, vg_res_n, vg_a } <= { (~din[4]),din[3],din[2],din[1:0] };
end
always @(posedge zclk)
begin
intrq_sync[1:0] <= {intrq_sync[0],vg_irq};
drq_sync[1:0] <= {drq_sync[0],vg_drq};
end
assign intrq = intrq_sync[1];
assign drq = drq_sync[1];
// write precompensation
// delay times are as in WRDELAY_* parameters, vg_wrd width is always 7 clocks
always @(posedge fclk)
begin
sl_sync[1:0] <= { sl_sync[0], vg_sl };
sr_sync[1:0] <= { sr_sync[0], vg_sr };
tr43_sync[1:0] <= { tr43_sync[0], vg_tr43 };
wd_sync[2:0] <= { wd_sync[1:0], vg_wd };
end
assign sl = sl_sync[1]; // just state signals
assign sr = sr_sync[1]; //
assign tr43 = tr43_sync[1]; //
assign wd = wd_sync[1] & (~wd_sync[2]); // strobe: beginning of vg_wd
// make delay
always @(posedge fclk)
begin
if( wd )
case( {sl, tr43, sr} )
3'b100: // shift left, outer tracks
wrdelay_cnt <= WRDELAY_OUTER_LEFT;
3'b001: // shift right, outer tracks
wrdelay_cnt <= WRDELAY_OUTER_RIGHT;
3'b110: // shift left, inner tracks
wrdelay_cnt <= WRDELAY_INNER_LEFT;
3'b011: // shift right, inner tracks
wrdelay_cnt <= WRDELAY_INNER_RIGHT;
default: // no shift
wrdelay_cnt <= WRDELAY_STANDARD;
endcase
else if( !delay_end )
wrdelay_cnt <= wrdelay_cnt - 4'd1;
end
assign delay_end = (wrdelay_cnt==4'd0);
// make vg_wdr impulse after a delay
always @(posedge fclk)
if( wrwidth_ena )
begin
if( wd )
wrwidth_cnt <= 4'd0;
else
wrwidth_cnt <= wrwidth_cnt + 4'd1;
end
assign wrwidth_ena = wd | ( delay_end & (~wrwidth_cnt[3]) );
always @(posedge fclk)
vg_wrd <= | wrwidth_cnt[2:0]; // only 7 clocks is the lendth of vg_wrd
/* fapch_counter dpll
(
.fclk (fclk ),
.rdat_n (rdat_n ),
.vg_rclk(vg_rclk),
.vg_rawr(vg_rawr)
);
*/
fapch_zek dpll
(
.fclk (fclk ),
.rdat_n (rdat_n ),
.vg_rclk(vg_rclk),
.vg_rawr(vg_rawr)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void swap(int &a, int &b) { int temp; temp = a; a = b; b = temp; } void printarr(int a[], int n) { for (int i = 0; i < 2 * n; i++) cout << a[i] << ; cout << endl; } int main() { long long int n, k, v; cin >> n; int a[2 * n], i, j, count = 0; for (i = 0; i < 2 * n; i++) cin >> a[i]; for (i = 0; i < 2 * n; i += 2) { if (a[i] != a[i + 1]) { j = a[i]; for (k = i + 1; k < 2 * n; k++) { if (j == a[k]) { v = k; while (v > i + 1) { count++; swap(a[v], a[v - 1]); v--; } } } } } cout << count; return 0; }
|
#include <bits/stdc++.h> using namespace std; void fastIO() { ios_base::sync_with_stdio(false); cout.setf(ios::fixed); cout.precision(10); cout.tie(nullptr); cin.tie(nullptr); } template <class T> T power(T N, T P) { return (P == 0) ? 1 : N * power(N, P - 1); } template <class T> T GCD(T A, T B) { return (A % B == 0) ? B : GCD(B, A % B); } const int MOD = 1e9 + 7; const int MX = 2e5 + 5; const double delta = 1e-9; const long long INF = 1e18; const long double PI = acos((long double)-1); void setIn(string s) { freopen(s.c_str(), r , stdin); } void setOut(string s) { freopen(s.c_str(), w , stdout); } bool sort_rev(int a, int b) { return a > b; } bool sort_(pair<string, int> &p1, pair<string, int> &p2) { if (p1.first == p2.first) return p1.second < p2.second; return p1.first < p2.first; } bool func(pair<int, int> a, pair<int, int> b) { return a.first > b.first; } int main() { fastIO(); int t = 1; cin >> t; while (t--) { int n; cin >> n; pair<int, int> ara[n + 1]; for (int i = 0; i < n; i++) { cin >> ara[i].first; } for (int i = 0; i < n; i++) cin >> ara[i].second; sort(ara, ara + n, func); long long aa = 0, bb = 0; for (int i = 0; i < n; i++) { long long canB = bb + ara[i].second; long long canA = max(aa, (long long)ara[i].first); if (canA <= canB) aa = canA; else bb = canB; } cout << max(aa, bb) << n ; } return 0; }
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of blocking procedural assignment.
module top;
reg array1[2:1];
reg array2[1:0];
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
`endif
integer index;
reg failed;
initial begin
failed = 0;
array1[1] = 1'b0;
array1[2] = 1'b0;
array1[0] = 1'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
array1[1] = 1'b0;
array1[2] = 1'b0;
array1[3] = 1'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
array2[0] = 1'b0;
array2[1] = 1'b0;
array2['bx] = 1'b1;
$display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1;
index = 0;
array1[1] = 1'b0;
array1[2] = 1'b0;
array1[index] = 1'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
index = 3;
array1[1] = 1'b0;
array1[2] = 1'b0;
array1[index] = 1'b1;
$display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
index = 'bx;
array2[0] = 1'b0;
array2[1] = 1'b0;
array2[index] = 1'b1;
$display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1;
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
array3[0] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array3[1] = 0.0;
array3[2] = 0.0;
array3[3] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array4[0] = 0.0;
array4[1] = 0.0;
array4['bx] = 1.0;
$display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
index = 0;
array3[1] = 0.0;
array3[2] = 0.0;
array3[index] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = 3;
array3[1] = 0.0;
array3[2] = 0.0;
array3[index] = 1.0;
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = 'bx;
array4[0] = 0.0;
array4[1] = 0.0;
array4[index] = 1.0;
$display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000006; const long long MOD = 1000000007; struct Query { int a, t, x, id; } query[MAXN]; map<int, int> cnt; int n, ans[MAXN], qcnt; void solve(int l, int r) { ; if (l != r - 1) { int mid = (l + r) >> 1; solve(l, mid); solve(mid, r); cnt.clear(); int lp = l, rp = mid; while (rp < r) { if (lp == mid || query[lp].t > query[rp].t) { if (query[rp].a == 3) { ; ans[query[rp].id] += cnt[query[rp].x]; } rp++; } else { if (query[lp].a == 1) { cnt[query[lp].x]++; } else if (query[lp].a == 2) { cnt[query[lp].x]--; } lp++; } }; sort(query + l, query + r, [&](Query q1, Query q2) { return q1.t < q2.t; }); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int i = 0; i < n; i++) { int a, t, x; cin >> a >> t >> x; query[i] = {a, t, x, qcnt}; ; if (a == 3) { qcnt++; } } solve(0, n); for (int i = 0; i < qcnt; i++) { cout << ans[i] << n ; } return 0; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:33:50 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/8-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } unsigned int countBits(unsigned int n) { unsigned int count = 0; while (n) { count++; n >>= 1; } return count; } bool isPerfectSquare(long double x) { long double sr = sqrt(x); return ((sr - floor(sr)) == 0); } int subArraySum(int arr[], int n) { int curr_sum = arr[0], start = 0, i, count = 0, len; len = 0; for (i = 1; i <= n; i++) { len++; while (curr_sum > len && start < i - 1) { curr_sum = curr_sum - arr[start]; start++; len++; } if (curr_sum == len) { count++; } if (i < n && i > 0) { curr_sum = curr_sum + arr[i]; } } return count; } void printDigit(int N, vector<long long int>& arr) { int i = 0; int j, r; while (N != 0) { r = N % 10; arr.push_back(r); i++; N = N / 10; } } void solver(vector<long long int> arr, long long int start, long long int& count, long long int a1) { long long int sum = 0; for (long long int i = start + 1; i < arr.size() - 1; i++) { sum += arr[i]; if (sum == a1) count++; } } bool checkDivisibility(long long int n, int digit) { if (digit == 0) return true; return (digit != 0 && n % digit == 0); } bool allDigitsDivide(long long int n) { long long int temp = n; while (temp > 0) { int digit = temp % 10; if (!(checkDivisibility(n, digit))) return false; temp /= 10; } return true; } bool isPrime(int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool isPowerOfTwo(unsigned long long x) { return x && (!(x & (x - 1))); } int nextPrime(int N) { if (N <= 1) return 2; int prime = N; bool found = false; while (!found) { prime++; if (isPrime(prime)) found = true; } return prime; } bool sortcol(const vector<long long int>& v1, const vector<long long int>& v2) { return v1[0] < v2[0]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int b = 0, q, c, x, y, start = 0, end = 0, count = 0, neg = 0, pos = 0, count1 = 0, a1 = 0, b1 = 0, c1 = 0, x1, y1, n1, m, ans = 0, sum = 0, k; long long int n; string s1, s2( ), s3( ); bool check2 = false, check3 = false; long long int x3, x2, y3, y2; int curr1 = 0, curr = 0; vector<int> arr(130, 0); vector<int> arr1; stack<char> s; long long int vb; bool check1 = false, check4 = false; vector<double> arrv; unordered_map<long long int, long long int> map1; unordered_map<long long int, long long int> map2; long long int a, l = 0, d = 0, u = 0, v, g, sub; cin >> s1; n = s1.length(); for (int i = 0; i < n; i++) { arr[s1[i]]++; } for (int i = 0; i < arr.size(); i++) { if (arr[i] % 2 != 0) count++; } if (count == 0 || count == 1) cout << First ; else if (count % 2 != 0) cout << First ; else cout << Second ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e6, mod = 1e9 + 7, inf = 1e10; long long int a[N], dp[N]; int main() { long long int n, mn = 0, mx = -1, ans_1 = 0, ans_2 = 0, cnt, clk, clr; cin >> n; for (long long int i = 1; i * i * i <= n; i++) { if (n % i == 0) { for (long long int j = 1; j * j <= (n / i); j++) { long long int k = n / (i * j); if (i * j * k == n) { cnt = (i + 1) * (j + 2) * (k + 2); if (mn == 0) mn = cnt; mn = min(mn, cnt); mx = max(mx, cnt); clk = (i + 2) * (j + 1) * (k + 2); mn = min(mn, clk); mx = max(mx, clk); clr = (i + 2) * (j + 2) * (k + 1); mn = min(mn, clr); mx = max(mx, clr); } } } } ans_1 = mn - n; ans_2 = mx - n; cout << ans_1 << ; return cout << (ans_2), 0; }
|
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