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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200050; int len; char a[maxn]; int main() { while (scanf( %d , &len) != EOF) { scanf( %s , a); int ans = 0; for (int i = 0; i < len; i++) if (a[i] == < ) ans++; else break; for (int i = len - 1; i >= 0; i--) if (a[i] == > ) ans++; else break; printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, n, m, t, l; cin >> t; while (t--) { string s, p, q = abacaba , r; cin >> n >> s; int cnt = 0, cntt = 0; p = s; r = s; for (i = 0; i < n; i++) { int c = 0; for (j = i, k = 0; j < i + 7 && j < n; j++) { if (q[k] == s[j]) { k++; c++; } else { k = 0; break; } } if (c == 7) cnt++; if (s[i] == ? ) cntt++; } if (cnt > 1) cout << No << endl; else if (cntt == 0 && cnt == 0) cout << No << endl; else { int ans = 0; if (cnt == 0) { for (i = 0; i + 6 < n; i++) { bool f = 1; s = p; for (j = 0; j < i; j++) { if (s[j] == ? ) s[j] = x ; } for (j = 0; j < 7; j++) { if (s[j + i] != q[j] && s[j + i] != ? ) { f = 0; break; } else if (s[j + i] == ? ) s[j + i] = q[j]; } if (f == 0) continue; int con = 0; if (f == 1) { for (l = 0; l + 6 < n; l++) { int ok = 1; for (j = 0; j < 7; j++) { if (s[j + l] != q[j]) { ok = 0; break; } } con += ok; } if (con == 1) { cout << Yes << endl; for (i = 0; i < n; i++) if (s[i] == ? ) s[i] = x ; cout << s << endl; ans = 1; break; } else continue; } } if (ans == 0) cout << No << endl; } else if (cnt == 1) { for (i = 0; i < n; i++) { if (s[i] == ? ) s[i] = x ; } cout << Yes << endl; cout << s << endl; } else cout << No << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_1_V
`define SKY130_FD_SC_HDLL__NOR3B_1_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_1 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_1 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_1_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T checkmin(T &a, T b) { return (a < b) ? a : a = b; } template <class T> inline T checkmax(T &a, T b) { return (a > b) ? a : a = b; } template <class T> T GCD(T a, T b) { if (a < 0) return GCD(-a, b); if (b < 0) return GCD(a, -b); return (a == 0) ? b : GCD(b % a, a); } template <class T> T LCM(T a, T b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return (a == 0 || b == 0) ? 0 : a / GCD(a, b) * b; } template <class T> inline T sqr(T X) { return X * X; } namespace Poor { const int MaxiN = 105; const long long Infinity = 2000000000000000000LL; int N, M; long long K; int C[MaxiN][MaxiN]; int Weight[MaxiN + MaxiN]; pair<int, int> List[MaxiN + MaxiN]; char St[MaxiN + MaxiN]; inline void Inc(long long &a, long long b) { a += b; if (a > Infinity) a = Infinity; } long long DP() { map<int, long long> Now, Suc; Now.clear(); Now[0] = 1; for (int i = 0; i < N + M - 1; ++i) { for (typeof(Now.begin()) it = Now.begin(); it != Now.end(); ++it) { if (St[i] != ) ) Inc(Suc[it->first + 1], it->second); if (St[i] != ( && it->first > 0) Inc(Suc[it->first - 1], it->second); } Now = Suc; Suc.clear(); } return Now[0]; } void Run() { cin >> N >> M >> K; for (int i = 0; i < N; ++i) for (int j = 0; j < M; ++j) cin >> C[i][j]; fill(Weight, Weight + N + M - 1, INT_MAX); for (int i = 0; i < N; ++i) for (int j = 0; j < M; ++j) checkmin(Weight[i + j], C[i][j]); for (int i = 0; i < N + M - 1; ++i) List[i] = make_pair(Weight[i], i); sort(List, List + N + M - 1); fill(St, St + N + M - 1, ? ); for (int i = 0; i < N + M - 1; ++i) { int p = List[i].second; St[p] = ( ; long long dp = DP(); if (dp < K) { K -= dp; St[p] = ) ; } } for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) putchar(St[i + j]); puts( ); } } } // namespace Poor int main() { Poor::Run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<bitset<7>> score; vector<bitset<7>> bvec(10); map<unsigned long, int> bmap; bool flag = false; long long ans = 0; vector<string> anss; int ccc = 0; int ans_tab[2001][10][2001]; bool valid(vector<bitset<7>>& s, int cur, int dig, int cnt) { if (ans_tab[cur][dig][cnt] != -1) return ans_tab[cur][dig][cnt]; ccc++; bool vld = (score[cur] & bvec[dig]).to_ulong() == score[cur].to_ulong(); if (vld) { int x = __builtin_popcount((char)(score[cur] ^ bvec[dig]).to_ulong()); if (cnt - x >= 0) { if (cur == n - 1 && cnt - x == 0) { flag = true; return ans_tab[cur][dig][cnt] = true; } else { for (int j = 9; j >= 0; j--) { if (ans_tab[cur][dig][cnt] = valid(s, cur + 1, j, cnt - x)) { return true; } } } } else { return ans_tab[cur][dig][cnt] = false; } } return ans_tab[cur][dig][cnt] = false; } void solve() { memset(ans_tab, -1, sizeof(ans_tab)); cin >> n >> k; string in; for (int i = 0; i < n; ++i) { cin >> in; score.emplace_back(in); } bvec = {bitset<7>( 1110111 ), bitset<7>( 0010010 ), bitset<7>( 1011101 ), bitset<7>( 1011011 ), bitset<7>( 0111010 ), bitset<7>( 1101011 ), bitset<7>( 1101111 ), bitset<7>( 1010010 ), bitset<7>( 1111111 ), bitset<7>( 1111011 )}; for (int i = 0; i < (int)bvec.size(); ++i) { bmap[bvec[i].to_ulong()] = i; } string test = ; test = ; int cc = k; for (int j = 9; j >= 0; --j) { valid(score, 0, j, cc); } if (flag) { for (int i = 0; i < n; ++i) { for (int j = 9; j >= 0; --j) { bool vld = (score[i] & bvec[j]).to_ulong() >= score[i].to_ulong(); if (vld) { int x = __builtin_popcount((char)(score[i] ^ bvec[j]).to_ulong()); if (cc - x >= 0) { if (ans_tab[i][j][cc]) { test += to_string(j); cc -= x; break; } } } } } cout << test << endl; } else cout << -1 << endl; } int main() { solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_1_V
`define SKY130_FD_SC_HVL__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_1_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9, MOD = INF + 7; long long gcd(long long a, long long b) { return (b ? gcd(b, a % b) : a); } long long power(long long a, long long b) { return (!b ? 1 : power(a, b / 2) * power(a, b / 2) * (b % 2 ? a : 1)); } long long mod(long long a) { return (a % MOD + MOD) % MOD; } const long long N = 1e6 + 20; vector<long long> g[N]; long long mark[N]; vector<pair<long long, pair<long long, long long> > > ans; bool dfs(long long v, long long par = 0) { mark[v] = 1; long long tmp = 0; for (long long u : g[v]) { if (u == par || mark[u] == 2) continue; if (mark[u] == 0 && dfs(u, v)) continue; if (tmp == 0) tmp = u; else ans.push_back(make_pair(v, make_pair(u, tmp))), tmp = 0; } mark[v] = 2; if (tmp != 0 && par != 0) ans.push_back(make_pair(v, make_pair(tmp, par))); return tmp; } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, m; cin >> n >> m; for (long long i = 0; i < m; i++) { long long x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } for (long long i = 1; i <= n; i++) if (mark[i] == 0) dfs(i); cout << ans.size() << n ; for (auto p : ans) cout << p.second.first << << p.first << << p.second.second << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_TB_V
`define SKY130_FD_SC_MS__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ms__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_PP_SYMBOL_V
`define SKY130_FD_SC_LP__ISOBUFSRC_PP_SYMBOL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_src_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input eot,
input en,
input [C_DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
input fifo_ready,
output fifo_valid,
output [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
reg valid = 1'b0;
wire ready;
reg [C_DATA_WIDTH-1:0] buffer = 'h00;
reg buffer_sync = 1'b0;
reg needs_sync = 1'b0;
wire has_sync = ~needs_sync | buffer_sync;
wire sync_valid = valid & has_sync;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (ready && valid && buffer_sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
valid <= 1'b0;
overflow <= 1'b0;
end else begin
if (enable) begin
if (en) begin
buffer <= din;
buffer_sync <= sync;
valid <= 1'b1;
end else if (ready) begin
valid <= 1'b0;
end
overflow <= en & valid & ~ready;
end else begin
if (ready)
valid <= 1'b0;
overflow <= en;
end
end
end
assign sync_id_ret = sync_id;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(buffer),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
);
endmodule
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#include <bits/stdc++.h> using namespace std; void ex() { cout << NO n ; exit(0); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<pair<bool, int> > q(2 * n); for (int i = 0; i < 2 * n; ++i) { char t; cin >> t; if (t == + ) { q[i] = {true, -1}; } else { int x; cin >> x; q[i] = {false, x}; } } reverse(q.begin(), q.end()); vector<int> w, e; for (int i = 0; i < 2 * n; ++i) { if (q[i].first) { if (!e.empty()) { w.push_back(e.back()); e.pop_back(); } else { ex(); } } else { if (!e.empty() and e.back() < q[i].second) { ex(); } e.push_back(q[i].second); } } if (!e.empty()) { ex(); } cout << YES n ; for (int i = n - 1; i > -1; --i) { cout << w[i] << ; } cout << n ; }
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#include <bits/stdc++.h> using namespace std; map<char, int> m; char letters[30]; int numbers[30]; int mystring[30]; int ceiling(int top, int bottom) { return (top + bottom - 1) / bottom; } int main() { string s; int n; cin >> s >> n; for (int i = 0; i < (int)s.length(); i++) m[s[i]]++; int numChar = 0; for (map<char, int>::iterator it = m.begin(); it != m.end(); ++it) { letters[numChar] = it->first; numbers[numChar] = it->second; numChar++; } if (numChar > n) { cout << -1 << endl; return 0; } for (int i = 0; i < numChar; i++) mystring[i] = 1; for (int i = numChar; i < n; i++) { int needMost = -1, needMostIndex = -1; for (int j = 0; j < numChar; j++) { if (ceiling(numbers[j], mystring[j]) > needMost) { needMost = ceiling(numbers[j], mystring[j]); needMostIndex = j; } } mystring[needMostIndex]++; } int needMost = -1; for (int j = 0; j < numChar; j++) { if (ceiling(numbers[j], mystring[j]) > needMost) { needMost = ceiling(numbers[j], mystring[j]); } } cout << needMost << endl; for (int i = 0; i < numChar; i++) for (int j = 0; j < mystring[i]; j++) cout << letters[i]; cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; class flow { private: int n; vector<int> head, d, cur; vector<tuple<int, ll, int>> edge; bool bfs(int s, int t) { d.assign(n, -1); queue<int> que; que.push(s); d[s] = 0; while (!que.empty()) { int u = que.front(); que.pop(); for (int i = head[u]; i != -1; i = get<2>(edge[i])) { int v = get<0>(edge[i]); if (get<1>(edge[i]) && d[v] == -1) { d[v] = d[u] + 1; if (v == t) { return true; } que.push(v); } } } return false; } ll dfs(int u, int t, ll f) { if (u == t) { return f; } ll res = f; for (int &i = cur[u]; i != -1 && res; i = get<2>(edge[i])) { int v = get<0>(edge[i]); ll &c = get<1>(edge[i]); if (d[v] == d[u] + 1 && c) { ll aug = dfs(v, t, min(res, c)); res -= aug; c -= aug; get<1>(edge[i ^ 1]) += aug; } } return f - res; } public: flow(int _n) { n = _n; head.assign(n, -1); } void insert_edge(int u, int v, ll c) { edge.emplace_back(v, c, head[u]); head[u] = edge.size() - 1; edge.emplace_back(u, 0, head[v]); head[v] = edge.size() - 1; } ll max_flow(int s, int t) { ll flow = 0; while (bfs(s, t)) { cur = head; flow += dfs(s, t, 1e18); } return flow; } }; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<vector<int>> dis(n, vector<int>(n, 1e9)); for (int i = 0; i < n; ++i) { dis[i][i] = 0; } for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; --u; --v; dis[u][v] = 1; dis[v][u] = 1; } for (int k = 0; k < n; ++k) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { dis[i][j] = min(dis[i][j], dis[i][k] + dis[k][j]); } } } int s, b, k; cin >> s >> b >> k; vector<tuple<int, int, int, int>> ship; vector<vector<pair<int, int>>> base(n); for (int i = 0; i < s; ++i) { int x, a, f, p; cin >> x >> a >> f >> p; --x; ship.emplace_back(x, a, f, p); } for (int i = 0; i < b; ++i) { int x, d, g; cin >> x >> d >> g; --x; base[x].emplace_back(d, g); } for (int i = 0; i < n; ++i) { sort(base[i].begin(), base[i].end()); for (int j = 1; j < base[i].size(); ++j) { base[i][j].second = max(base[i][j].second, base[i][j - 1].second); } } vector<ll> gain(s); for (int i = 0; i < s; ++i) { int x = get<0>(ship[i]); int a = get<1>(ship[i]); int f = get<2>(ship[i]); int p = get<3>(ship[i]); gain[i] = -1e14; for (int j = 0; j < n; ++j) { if (dis[x][j] <= f && !base[j].empty() && a >= base[j][0].first) { gain[i] = max(gain[i], 1ll * (--upper_bound(base[j].begin(), base[j].end(), make_pair(a, (int)1e9))) ->second - p); } } } vector<bool> used(s); vector<pair<int, int>> rel; for (int i = 0; i < k; ++i) { int x, y; cin >> x >> y; --x; --y; used[x] = true; used[y] = true; rel.emplace_back(x, y); } int cnt = 0; ll ans = 0; vector<int> id(s, -1); for (int i = 0; i < s; ++i) { if (used[i]) { id[i] = cnt++; } else if (gain[i] > 0) { ans += gain[i]; } } flow G(cnt + 2); int S = cnt; int T = cnt + 1; for (int i = 0; i < s; ++i) { if (used[i]) { if (gain[i] > 0) { G.insert_edge(S, id[i], gain[i]); ans += gain[i]; } else if (gain[i] < 0) { G.insert_edge(id[i], T, -gain[i]); } } } for (int i = 0; i < k; ++i) { G.insert_edge(id[rel[i].first], id[rel[i].second], 1e18); } ans -= G.max_flow(S, T); cout << ans << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; const int MX = (int)1e6 + 17; const int MOD = (int)1e9 + 7; const long long oo = (long long)1e18 + 7; const int INF = (int)999999999; const int N = (int)1e5 + 17; const int di[4] = {-1, 0, 1, 0}; const int dj[4] = {0, 1, 0, -1}; inline long long IN() { long long x = 0, ch = getchar(), f = 1; while (!isdigit(ch) && (ch != - ) && (ch != EOF)) ch = getchar(); if (ch == - ) { f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } inline void OUT(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) OUT(x / 10), putchar(x % 10 + 0 ); else putchar(x + 0 ); } int n, mx; int a[N], t[N * 4]; void build(int v, int tl, int tr) { if (tl == tr) t[v] = a[tl]; else { int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); t[v] = max(t[v * 2], t[v * 2 + 1]); } } int get(int l, int r, int v, int tl, int tr) { if (l <= tl && tr <= r) return t[v]; if (tr < l || tl > r) return 0; int tm = (tl + tr) / 2; return max(get(l, r, v * 2, tl, tm), get(l, r, v * 2 + 1, tm + 1, tr)); } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; build(1, 1, n); for (int i = 1; i <= n; i++) { if (i < n) { int x = get(i + 1, n, 1, 1, n); if (x < a[i]) cout << 0 << ; else cout << x - a[i] + 1 << ; } else cout << 0 << ; } return 0; }
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`timescale 1ns / 1ps
module Pruebas_Controlador_Gato;
// Inputs
reg clk;
reg reset_all;
reg reset_game;
reg boton_arriba_reg;
reg boton_abajo_reg;
reg boton_izq_reg;
reg boton_der_reg;
reg boton_elige_reg;
// Outputs
wire [3:0] cuadro;
wire [3:0] circulo;
wire [3:0] equis;
wire [1:0] vertical;
wire [1:0] horizontal;
wire [1:0] cruzada;
wire [2:0] state;
wire turno_p1_wire;
wire turno_p2_wire;
wire win_game;
wire loss_game;
wire tie_game;
// Instantiate the Unit Under Test (UUT)
Controlador_Gato uut (
.clk(clk),
.reset_all(reset_all),
.reset_game(reset_game),
.cuadro(cuadro),
.circulo(circulo),
.equis(equis),
.vertical(vertical),
.horizontal(horizontal),
.cruzada(cruzada),
.state(state),
.boton_arriba_reg(boton_arriba_reg),
.boton_abajo_reg(boton_abajo_reg),
.boton_izq_reg(boton_izq_reg),
.boton_der_reg(boton_der_reg),
.boton_elige_reg(boton_elige_reg),
.turno_p1_wire(turno_p1_wire),
.turno_p2_wire(turno_p2_wire),
.win_game(win_game),
.loss_game(loss_game),
.tie_game(tie_game)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset_all = 0;
reset_game = 0;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 1;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 1;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 1;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = 5000 + 10, MOD = 1000000007; vector<pair<int, int> > lis[MAXN * 2]; pair<int, int> p[MAXN]; int n, f[MAXN], cnt; bool b[MAXN]; int dis(const pair<int, int> &a, const pair<int, int> &b) { return abs(a.first - b.first) + abs(a.second - b.second); } int getf(int first) { if (first == f[first]) return first; int fx = f[first]; f[first] = getf(f[first]); b[first] ^= b[fx]; return f[first]; } bool Merge(int first, int second) { int fx = getf(first), fy = getf(second); if (fx == fy) return b[first] ^ b[second]; f[fx] = fy; b[fx] = b[first] ^ b[second] ^ 1; --cnt; return true; } int Pow(int a, int b) { int d = 1; for (; b; d = (b & 1) ? (long long)d * a % MOD : d, a = (long long)a * a % MOD, b /= 2) ; return d; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d%d , &p[i].first, &p[i].second); for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) lis[dis(p[i], p[j])].push_back(make_pair(i, j)); cnt = n; for (int i = 1; i <= n; ++i) f[i] = i, b[i] = 0; for (int i = MAXN * 2 - 1; i >= 1; --i) { bool flag = true; int sum = cnt; for (vector<pair<int, int> >::iterator it = lis[i].begin(); it != lis[i].end(); ++it) if (!Merge(it->first, it->second)) { flag = false; break; } if (!flag) { cout << i << endl; cout << Pow(2, sum) << endl; exit(0); } } cout << 0 << endl << 2 << endl; fclose(stdin); fclose(stdout); return 0; }
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#include <bits/stdc++.h> using namespace std; long long read() { char x = getchar(); long long ans = 0, flag = 1; while (!isdigit(x)) if (x == - ) flag = -1, x = getchar(); else x = getchar(); while (isdigit(x)) ans = ans * 10 + x - 0 , x = getchar(); return ans * flag; } long long n, a[200005], ans, las; map<long long, long long> mp; signed main() { cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 1; i <= n; i++) a[i] += a[i - 1]; mp[0] = 0; las = 0; for (long long i = 1; i <= n; i++) { if (mp.find(a[i]) != mp.end()) { if (mp[a[i]] >= las) { ans -= (mp[a[i]] - las + 1) * ((n - i + 1)); las = mp[a[i]] + 1; } } mp[a[i]] = i; } cout << ans + n * (n + 1) / 2; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &out, const vector<T> &v) { out << { ; for (const T &a : v) out << a << , ; out << } ; return out; } template <typename S, typename T> ostream &operator<<(ostream &out, const pair<S, T> &p) { out << ( << p.first << , << p.second << ) ; return out; } const int dx[] = {0, 0, -1, 1}; const int dy[] = {-1, 1, 0, 0}; long long fpw(long long a, long long b, long long p) { long long r = 1; while (b) { if (b & 1) r = r * a % p; a = a * a % p; b /= 2; } return (long long)r; } bool check(long long p, long long d, long long a) { a %= p; if (!a) return 1; if (fpw(a, p - 1, p) != 1) return 0; if ((a = fpw(a, d, p)) == 1) return 1; while (a != 1) { if (a == p - 1) return 1; a = a * a % p; } return 0; } vector<long long> primes; bool prime(long long p) { if (p < 4) return p > 1; if (!(p & 1)) return 0; if (p <= 2000000000) { long long d = p - 1; while (!(d & 1)) d /= 2; return check(p, d, 2) && check(p, d, 325) && check(p, d, 9375) && check(p, d, 28178) && check(p, d, 450775) && check(p, d, 9780504) && check(p, d, 1795265022); } else { for (long long first : primes) { if (first * first > p) return 1; if (p % first == 0) return 0; } return 1; } } long long n; vector<long long> D; vector<long long> R, Q; void apply(long long d) { int i = ((int)(D).size()) - 1; int j = ((int)(D).size()) - 1; while (n / d != D[i]) --i; while (i >= 0) { while (D[j] > D[i] * d) --j; if (D[j] == D[i] * d) Q[j] += R[i]; --i; } } int main() { ios_base::sync_with_stdio(0); for (int i = (2); i < (1000010); ++i) if (prime(i)) primes.push_back(i); cin >> n; for (long long d = 1; d * d <= n; ++d) if (n % d == 0) { D.push_back(d); if (d * d != n) D.push_back(n / d); } sort(D.begin(), D.end()); R.resize(((int)(D).size())); Q.resize(((int)(D).size())); R[0] = 1; for (long long p : primes) { long long pk = p; bool once = 0; while (pk + 1 <= n) { if (n % (pk + 1) == 0) { once = 1; apply(pk + 1); } pk *= p; } if (once) for (int i = (0); i < (((int)(D).size())); ++i) { R[i] += Q[i]; Q[i] = 0; } } for (long long d : D) if (d - 1 > primes.back() && prime(d - 1)) { for (int i = (0); i < (((int)(D).size())); ++i) Q[i] = 0; apply(d); for (int i = (0); i < (((int)(D).size())); ++i) R[i] += Q[i]; } cout << R.back() << endl; return 0; }
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; namespace Xrocks {} using namespace Xrocks; namespace Xrocks { class in { } user_input; class out { } output; in& operator>>(in& X, int& Y) { scanf( %d , &Y); return X; } in& operator>>(in& X, char* Y) { scanf( %s , Y); return X; } in& operator>>(in& X, float& Y) { scanf( %f , &Y); return X; } in& operator>>(in& X, double& Y) { scanf( %lf , &Y); return X; } in& operator>>(in& X, char& C) { scanf( %c , &C); return X; } in& operator>>(in& X, string& Y) { cin >> Y; return X; } in& operator>>(in& X, long long& Y) { scanf( %lld , &Y); return X; } template <typename T> in& operator>>(in& X, vector<T>& Y) { for (auto& x : Y) user_input >> x; return X; } template <typename T> out& operator<<(out& X, const T& Y) { cout << Y; return X; } template <typename T> out& operator<<(out& X, vector<T>& Y) { for (auto& x : Y) output << x << ; return X; } out& operator<<(out& X, const int& Y) { printf( %d , Y); return X; } out& operator<<(out& X, const char& C) { printf( %c , C); return X; } out& operator<<(out& X, const string& Y) { printf( %s , Y.c_str()); return X; } out& operator<<(out& X, const long long& Y) { printf( %lld , Y); return X; } out& operator<<(out& X, const float& Y) { printf( %f , Y); return X; } out& operator<<(out& X, const double& Y) { printf( %lf , Y); return X; } out& operator<<(out& X, const char Y[]) { printf( %s , Y); return X; } template <typename T> T max(T A) { return A; } template <typename T, typename... args> T max(T A, T B, args... S) { return max(A > B ? A : B, S...); } template <typename T> T min(T A) { return A; } template <typename T, typename... args> T min(T A, T B, args... S) { return min(A < B ? A : B, S...); } template <typename T> void vectorize(int y, vector<T>& A) { A.resize(y); } template <typename T, typename... args> void vectorize(int y, vector<T>& A, args&&... S) { A.resize(y); vectorize(y, S...); } long long fast(long long a, long long b, long long pr) { if (b == 0) return 1 % pr; long long ans = 1 % pr; while (b) { if (b & 1) ans = (ans * a) % pr; b >>= 1; a = (a * a) % pr; } return ans; } int readInt() { int n = 0; int ch = getchar_unlocked(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar_unlocked(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar_unlocked(); n = n * sign; return n; } long long readLong() { long long n = 0; int ch = getchar_unlocked(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar_unlocked(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar_unlocked(); n = n * sign; return n; } long long readBin() { long long n = 0; int ch = getchar_unlocked(); int sign = 1; while (ch < 0 || ch > 1 ) { if (ch == - ) sign = -1; ch = getchar_unlocked(); } while (ch >= 0 && ch <= 1 ) n = (n << 1) + (ch - 0 ), ch = getchar_unlocked(); return n; } long long inv_(long long val, long long pr = static_cast<long long>(1000000007)) { return fast(val, pr - 2, pr); } } // namespace Xrocks class solve { public: solve() { set<int> Buy, Sell, Mid; int n; user_input >> n; Buy.insert(-1); Sell.insert(1e9); char action[10]; int num; int B1 = 0, B2 = 0; long long ans = 1; for (int i = 0; i < n; i++) { scanf( %s%d , action, &num); if (action[1] == D ) { B1 = *Buy.rbegin(); B2 = *Sell.begin(); if (B1 < num && B2 > num) { Mid.insert(num); } else if (B1 > num) { Buy.insert(num); } else Sell.insert(num); } else { if (Mid.find(num) != Mid.end()) { set<int>::iterator it = Mid.find(num); ++it; while (it != Mid.end()) { Sell.insert(*it); ++it; } set<int>::iterator it2 = Mid.begin(); while (*it2 < num) { Buy.insert(*it2); ++it2; } Mid.clear(); ans = (ans * 2) % static_cast<long long>(1000000007); } else if (num == (*Buy.rbegin())) { Buy.erase(num); Sell.insert(Mid.begin(), Mid.end()); Mid.clear(); } else if (num == (*Sell.begin())) { Sell.erase(Sell.begin()); Buy.insert(Mid.begin(), Mid.end()); Mid.clear(); } else { output << 0; return; } } } if (Mid.size()) ans = (ans * (Mid.size() + 1)) % static_cast<long long>(1000000007); output << ans; } }; int32_t main() { int t = 1, i = 1; if (0 || 0) scanf( %d , &t); while (t--) { if (0) printf( Case #%d: , i++); new solve; } output << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 7; const int MOD = (int)1e9 + 7; const long long INF = (long long)1e18 + 7; vector<vector<long long>> a; long long col[N], row[N], trow[N], tcol[N]; long long res; int m, n; long long getrow() { long long ma = trow[1]; long long pos = 1; for (int i = 2; i <= m; i++) if (trow[i] > ma) { ma = trow[i]; pos = i; } trow[pos] = 0; for (int i = 1; i <= n; i++) tcol[i] -= a[pos][i]; return max(0ll, ma); } long long getcol() { long long ma = tcol[1]; long long pos = 1; for (int i = 2; i <= n; i++) if (tcol[i] > ma) { ma = tcol[i]; pos = i; } tcol[pos] = 0; for (int i = 1; i <= m; i++) trow[i] -= a[i][pos]; return max(0ll, ma); } void sett() { for (int i = 1; i <= m; i++) trow[i] = row[i]; for (int i = 1; i <= n; i++) tcol[i] = col[i]; } void proces(int st, int nd, int rd, int th) { long long ma = 0; sett(); if (st) ma += getcol(); else ma += getrow(); if (nd) ma += getcol(); else ma += getrow(); if (rd) ma += getcol(); else ma += getrow(); if (th) ma += getcol(); else ma += getrow(); res = max(res, ma); } int main() { cin >> m >> n; a.resize(m + 1); for (int i = 1; i <= m; i++) { a[i].push_back(0); long long t; for (int j = 1; j <= n; j++) { cin >> t; a[i].push_back(t); } } for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) row[i] += a[i][j]; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) col[i] += a[j][i]; for (int a1 = 0; a1 <= 1; a1++) for (int a2 = 0; a2 <= 1; a2++) for (int a3 = 0; a3 <= 1; a3++) for (int a4 = 0; a4 <= 1; a4++) proces(a1, a2, a3, a4); cout << res; }
|
/*
Teak synthesiser for the Balsa language
Copyright (C) 2007-2010 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Andrew Bardsley <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
/*
nand2-mapping.v : Teak tech mapping for a technology with only a 2-input NAND gate called nand2
*/
module tkg_nand2 (output o, input i0, i1);
NAND2 I0 (o, i0, i1);
endmodule
module tkg_buff (output o, input i);
BUFF I0 (o, i);
endmodule
module tkg_mutex (input ar, br, output ag, bg);
MUTEX I0 (ar, br, ag, bg);
endmodule
// tkg_{and,or,nand,nor}[23] : 2/3 input AND/OR/NAND/NOR gates
module tkg_and2 (output o, input i0, i1);
wire na01;
nand2 I0 (na01, i0, i1);
inv I1 (o, na01);
endmodule
module tkg_and3 (output o, input i0, i1, i2);
wire a01;
and2 I0 (a01, i0, i1);
and2 I1 (o, a01, i2);
endmodule
module tkg_or2 (output o, input i0, i1);
wire n0, n1;
inv I0 (n0, i0);
inv I1 (n1, i1);
nand2 I2 (o, n0, n1);
endmodule
module tkg_or3 (output o, input i0, i1, i2);
wire o01;
or2 I0 (o01, i0, i1);
or2 I1 (o, o01, i2);
endmodule
// module tkg_nand2 (output o, input i0, i1);
// endmodule
module tkg_nand3 (output o, input i0, i1, i2);
wire a01;
and2 I0 (a01, i0, i1);
nand2 I1 (o, a01, i2);
endmodule
module tkg_nor2 (output o, input i0, i1);
wire no;
or2 I0 (no, i0, i1);
inv I1 (o, no);
endmodule
module tkg_nor3 (output o, input i0, i1, i2);
wire o01;
or2 I0 (o01, i0, i1);
nor2 I1 (o, o01, i2);
endmodule
// tkg_c[23] : 2/3 input symmetric C-elements
module tkg_c2 (output o, input i0, i1);
ao222 I0 (o, i0, i1, i0, o, i1, o);
endmodule
module tkg_c3 (output o, input i0, i1, i2);
wire c01;
c2 I0 (c01, i0, i1);
c2 I1 (o, c01, i2);
endmodule
// tkg_c2r1 : 2 input symmetric C-element with active high reset
module tkg_c2r1 (output o, input i0, i1, r);
wire c01, nr;
inv I0 (nr, r);
ao222 I1 (c01, i0, i1, i0, o, i1, o);
and2 I2 (o, c01, nr);
endmodule
// tkg_c1u1 : asymmetric C-element with one 'symmetric' and one 'up' input
module tkg_c1u1 (output o, input s0, u0);
ao22 I0 (o, s0, u0, s0, o);
endmodule
// tkg_ao22 : AND-OR-22. o = i0&i1 | i2&i3
module tkg_ao22 (output o, input i0, i1, i2, i3);
wire na01, na23;
nand2 I0 (na01, i0, i1);
nand2 I1 (na23, i2, i3);
nand2 I2 (o, na01, na23);
endmodule
// tkg_ao222 : AND-OR-222. o = i0&i1 | i2&i3 | i4&i5
module tkg_ao222 (output o, input i0, i1, i2, i3, i4, i5);
wire na01, na23, na45;
nand2 I0 (na01, i0, i1);
nand2 I1 (na23, i2, i3);
nand2 I2 (na45, i4, i5);
nand3 I3 (o, na01, na23, na45);
endmodule
// tkg_gnd : logic 0 connection
module tkg_gnd (output o);
/*
wire no;
and2 I0 (o, o, no);
inv I1 (no, o);
*/
GND I0 (o);
endmodule
// tkg_inv : inverter
module tkg_inv (output o, input i);
nand2 I0 (o, i, i);
endmodule
// tkg_buff : non-inverting logical buffer
// module tkg_buff (output o, input i);
// endmodule
// tkg_mutex : mutual exclusion element. ag&bg is never true.
// module tkg_mutex (input ar, br, output ag, bg);
// endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; static inline int Rint() { struct X { int dig[256]; X() { for (int i = 0 ; i <= 9 ; ++i) dig[i] = 1; dig[ - ] = 1; } }; static X fuck; int s = 1, v = 0, c; for (; !fuck.dig[c = getchar()];) ; if (c == - ) s = 0; else if (fuck.dig[c]) v = c ^ 48; for (; fuck.dig[c = getchar()]; v = v * 10 + (c ^ 48)) ; return s ? v : -v; } template <typename T> static inline void cmax(T& a, const T& b) { if (b > a) a = b; } template <typename T> static inline void cmin(T& a, const T& b) { if (b < a) a = b; } struct Pt { int x, y; }; int cmp_x_min(const Pt& a, const Pt& b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } Pt data[100005]; int main() { int n = Rint(), m = Rint(); for (int i = 0; i < m; ++i) data[i].x = Rint(), data[i].y = Rint(); sort(data, data + m, cmp_x_min); vector<int> last; last.push_back(1); last.push_back(1); int row = 0; for (int now = 0; now < m;) { int j = now + 1; while (j < m && data[j].x == data[now].x) ++j; if (last.size() && data[now].x > row + 1) { vector<int> next; next.push_back(last.front()), next.push_back(n); last.swap(next); row = row + 1; } const int size = ((int)(last).size()); vector<int> next; for (int k = now, pos = 0; k <= j; ++k) { int r = k == j ? n : data[k].y - 1; int l = k == now ? 1 : data[k - 1].y + 1; if (l > r) continue; while (pos < size && last[pos + 1] < l) pos += 2; if (pos < size) { if (last[pos] > r) continue; if (last[pos] <= l) { next.push_back(l); next.push_back(r); } else if (last[pos] <= r) { next.push_back(last[pos]); next.push_back(r); } } } last.swap(next); row = data[now].x; now = j; } if (last.size() && data[m - 1].x < n) { vector<int> next; next.push_back(last.front()), next.push_back(n); last.swap(next); row = row + 1; } if (last.size()) { const int size = ((int)(last).size()); if (last[size - 2] <= n && last[size - 1] >= n) { printf( %d n , 2 * n - 2); return 0; } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 1e5 + 10; long long len, ans, val[26], s[mx]; char str[mx]; map<pair<long long, char>, long long> dp; int main() { for (int i = 0; i < 26; i++) scanf( %I64d , &val[i]); scanf( %s , str); len = strlen(str); s[0] = val[str[0] - a ]; for (int i = 1; i < len; i++) s[i] = s[i - 1] + val[str[i] - a ]; for (int i = 0; i < len; i++) { ans += dp[make_pair(s[i - 1], str[i])]; dp[make_pair(s[i], str[i])]++; } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_TB_V
`define SKY130_FD_SC_LP__ISO0P_TB_V
/**
* iso0p: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg KAPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 SLEEP = 1'b1;
#200 VGND = 1'b1;
#220 VNB = 1'b1;
#240 VPB = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 SLEEP = 1'b0;
#320 VGND = 1'b0;
#340 VNB = 1'b0;
#360 VPB = 1'b0;
#380 VPB = 1'b1;
#400 VNB = 1'b1;
#420 VGND = 1'b1;
#440 SLEEP = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPB = 1'bx;
#520 VNB = 1'bx;
#540 VGND = 1'bx;
#560 SLEEP = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__iso0p dut (.A(A), .SLEEP(SLEEP), .KAPWR(KAPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_TB_V
|
#include <bits/stdc++.h> using namespace std; using i64 = long long; const int N = 2e5 + 5; struct Nod { i64 sum; int max_pos, max_pos2; }; Nod pom[N * 4]; int v[N]; int n, q, update_pos, update_val, current_pos; i64 query_sum, peak_sum; static void pom_build(int nod, int l, int r) { if (l == r) { pom[nod] = {v[l], l, n + 1}; return; } int med = (l + r) / 2; pom_build(2 * nod, l, med); pom_build(2 * nod + 1, med + 1, r); pom[nod].sum = pom[2 * nod].sum + pom[2 * nod + 1].sum; if (v[pom[2 * nod].max_pos] > v[pom[2 * nod + 1].max_pos]) { pom[nod].max_pos = pom[2 * nod].max_pos; pom[nod].max_pos2 = v[pom[2 * nod].max_pos2] > v[pom[2 * nod + 1].max_pos] ? pom[2 * n].max_pos2 : pom[2 * nod + 1].max_pos; } else { pom[nod].max_pos = pom[2 * nod + 1].max_pos; pom[nod].max_pos2 = pom[2 * nod + 1].max_pos2; } } static void internal_update(int nod, int l, int r) { if (l == r) { pom[nod].sum = update_val; return; } int med = (l + r) / 2; if (update_pos <= med) internal_update(2 * nod, l, med); else internal_update(2 * nod + 1, med + 1, r); pom[nod].sum = pom[2 * nod].sum + pom[2 * nod + 1].sum; if (v[pom[2 * nod].max_pos] > v[pom[2 * nod + 1].max_pos]) { pom[nod].max_pos = pom[2 * nod].max_pos; pom[nod].max_pos2 = v[pom[2 * nod].max_pos2] > v[pom[2 * nod + 1].max_pos] ? pom[2 * n].max_pos2 : pom[2 * nod + 1].max_pos; } else { pom[nod].max_pos = pom[2 * nod + 1].max_pos; pom[nod].max_pos2 = pom[2 * nod + 1].max_pos2; } } static int find_peak(int nod, int l, int r) { if (l == r) return l; if (v[pom[1].max_pos] == 0) return n >= 2 ? 2 : -1; int med = (l + r) / 2; if (current_pos < med && (pom[2 * nod].max_pos != current_pos ? v[pom[2 * nod].max_pos] : v[pom[2 * nod].max_pos2]) >= query_sum) return find_peak(2 * nod, l, med); else if (current_pos < r && (pom[2 * nod + 1].max_pos != current_pos ? v[pom[2 * nod + 1].max_pos] : v[pom[2 * nod + 1].max_pos2]) >= query_sum) { peak_sum += pom[2 * nod].sum; return find_peak(2 * nod + 1, med + 1, r); } else return -1; } static void update(int pos, int val) { update_val = val; update_pos = pos; v[pos] = val; internal_update(1, 1, n); } static int query() { int pos = 0; peak_sum = 0; query_sum = 0; current_pos = 0; while ((pos = find_peak(1, 1, n)) != -1) { query_sum = peak_sum + v[pos]; if (peak_sum == v[pos]) return pos; current_pos = pos; peak_sum = 0; } return -1; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int pos, val; cin >> n >> q; for (int i = 1; i <= n; ++i) cin >> v[i]; pom_build(1, 1, n); while (q--) { cin >> pos >> val; update(pos, val); cout << query() << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_2_V
`define SKY130_FD_SC_HVL__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_2_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
// Async set, enable
module \$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
// Async set & reset
module \$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
// Async set, reset & enable
module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R), .S(S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
module \$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
module \$_DFFSR_NPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_301x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_301x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [300:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [300:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [300:0] sub_wire4;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
wire [300:0] q = sub_wire4[300:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.wrempty (sub_wire3),
.q (sub_wire4)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 301,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "301"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "301"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "301"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 301 0 INPUT NODEFVAL data[300..0]
// Retrieval info: USED_PORT: q 0 0 301 0 OUTPUT NODEFVAL q[300..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 301 0 data 0 0 301 0
// Retrieval info: CONNECT: q 0 0 301 0 @q 0 0 301 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
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// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.1up/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/11/05 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> v; string s; int n; int main() { cin >> n >> s; v.push_back(s); for (int i = 0; i < n; i++) { string s1 = s; if (s[i] != 0) { int kl = 10 - (s[i] - 48); for (int j = 0; j < n; j++) { int zn = s[j] - 48 + kl; zn %= 10; s1[j] = zn + 48; } } string s2 = ; for (int j = i; j < n; j++) s2 += s1[j]; for (int j = 0; j < i; j++) s2 += s1[j]; v.push_back(s2); } sort(v.begin(), v.end()); cout << v[0] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 1, M = 1e9 + 7; int n, dp[N][1 << 3][2]; char s[3][N]; int calc(int r, int msk, bool f) { if (r == n) return f; int &res = dp[r][msk][f]; if (res != -1) return res; int nmsk = msk; for (int i = 0; i < 3; ++i) if (s[i][r] != . ) nmsk |= (1 << i); res = 0; if (nmsk == 0) { if (r + 1 != n && s[0][r + 1] == . && s[1][r + 1] == . && s[2][r + 1] == . ) { if (r + 2 != n && (s[0][r + 2] == O || s[1][r + 2] == O || s[2][r + 2] == O )) res = (res + calc(r + 2, 0, true)) % M; else if (r != 0 && (s[0][r - 1] == O || s[1][r - 1] == O || s[2][r - 1] == O )) res = (res + calc(r + 2, 0, true)) % M; else res = (res + calc(r + 2, 0, f)) % M; } if (r + 1 != n && s[0][r + 1] == . ) { if ((r + 2 != n && s[0][r + 2] == O ) || (r != 0 && s[0][r - 1] == O )) res = (res + calc(r + 1, 1 << 0, true)) % M; else if ((s[1][r + 1] == O && s[2][r + 1] == O ) || (r != 0 && s[1][r - 1] == O && s[2][r - 1] == O )) res = (res + calc(r + 1, 1 << 0, true)) % M; else res = (res + calc(r + 1, 1 << 0, f)) % M; } if (r + 1 != n && s[2][r + 1] == . ) { if ((r + 2 != n && s[2][r + 2] == O ) || (r != 0 && s[2][r - 1] == O )) res = (res + calc(r + 1, 1 << 2, true)) % M; else if ((s[0][r + 1] == O && s[1][r + 1] == O ) || (r != 0 && s[0][r - 1] == O && s[1][r - 1] == O )) res = (res + calc(r + 1, 1 << 2, true)) % M; else res = (res + calc(r + 1, 1 << 2, f)) % M; } } else if (nmsk == 1) { if ((r + 1 != n && s[1][r + 1] == O && s[2][r + 1] == O ) || (r != 0 && s[1][r - 1] == O && s[2][r - 1] == O )) res = (res + calc(r + 1, 0, true)) % M; else if (s[0][r] == O ) res = (res + calc(r + 1, 0, true)) % M; else res = (res + calc(r + 1, 0, f)) % M; if (r + 1 != n && s[1][r + 1] == . && s[2][r + 1] == . ) { if (r + 2 != n && (s[1][r + 2] == O || s[2][r + 2] == O )) res = (res + calc(r + 1, (1 << 1) | (1 << 2), true)) % M; else if (r != 0 && (s[1][r - 1] == O || s[2][r - 1] == O )) res = (res + calc(r + 1, (1 << 1) | (1 << 2), true)) % M; else if (s[0][r] == O && s[0][r + 1] == O ) res = (res + calc(r + 1, (1 << 1) | (1 << 2), true)) % M; else res = (res + calc(r + 1, (1 << 1) | (1 << 2), f)) % M; } } else if (nmsk == 2) { if (r + 1 != n && s[0][r + 1] == . && s[2][r + 1] == . ) { if (r + 2 != n && (s[0][r + 2] == O || s[2][r + 2] == O )) res = (res + calc(r + 1, (1 << 0) | (1 << 2), true)) % M; else if (r != 0 && (s[0][r - 1] == O || s[2][r - 1] == O )) res = (res + calc(r + 1, (1 << 0) | (1 << 2), true)) % M; else if (s[1][r] == O && s[1][r + 1] == O ) res = (res + calc(r + 1, (1 << 0) | (1 << 2), true)) % M; else res = (res + calc(r + 1, (1 << 0) | (1 << 2), f)) % M; } } else if (nmsk == 3) { if (r + 1 != n && s[2][r + 1] == . ) { if ((r + 2 != n && s[2][r + 2] == O ) || (r != 0 && s[2][r - 1] == O )) res = (res + calc(r + 1, 1 << 2, true)) % M; else if (s[1][r] == O && s[1][r + 1] == O ) res = (res + calc(r + 1, 1 << 2, true)) % M; else res = (res + calc(r + 1, 1 << 2, f)) % M; } } else if (nmsk == 4) { if ((r + 1 != n && s[0][r + 1] == O && s[1][r + 1] == O ) || (r != 0 && s[0][r - 1] == O && s[1][r - 1] == O )) res = (res + calc(r + 1, 0, true)) % M; else if (s[2][r] == O ) res = (res + calc(r + 1, 0, true)) % M; else res = (res + calc(r + 1, 0, f)) % M; if (r + 1 != n && s[0][r + 1] == . && s[1][r + 1] == . ) { if (r + 2 != n && (s[0][r + 2] == O || s[1][r + 2] == O )) res = (res + calc(r + 1, (1 << 0) | (1 << 1), true)) % M; else if (r != 0 && (s[0][r - 1] == O || s[1][r - 1] == O )) res = (res + calc(r + 1, (1 << 0) | (1 << 1), true)) % M; else if (s[2][r] == O && s[2][r + 1] == O ) res = (res + calc(r + 1, (1 << 0) | (1 << 1), true)) % M; else res = (res + calc(r + 1, (1 << 0) | (1 << 1), f)) % M; } } else if (nmsk == 5) { if (r + 1 != n && s[1][r + 1] == . ) { if ((r + 2 != n && s[1][r + 2] == O ) || (r != 0 && s[1][r - 1] == O )) res = (res + calc(r + 1, 1 << 1, true)) % M; else if ((s[0][r] == O && s[0][r + 1] == O ) || (s[2][r] == O && s[2][r + 1] == O )) res = (res + calc(r + 1, 1 << 1, true)) % M; else res = (res + calc(r + 1, 1 << 1, f)) % M; } } else if (nmsk == 6) { if (r + 1 != n && s[0][r + 1] == . ) { if ((r + 2 != n && s[0][r + 2] == O ) || (r != 0 && s[0][r - 1] == O )) res = (res + calc(r + 1, 1 << 0, true)) % M; else if (s[1][r] == O && s[1][r + 1] == O ) res = (res + calc(r + 1, 1 << 0, true)) % M; else res = (res + calc(r + 1, 1 << 0, f)) % M; } } else res = (res + calc(r + 1, 0, f)) % M; return res; } int main() { scanf( %d , &n); for (int i = 0; i < 3; ++i) scanf( %s , s[i]); memset(dp, -1, sizeof dp); printf( %d n , calc(0, 0, false)); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); map<string, long long> m; long long n; cin >> n; for (long long i = 0; i < n; i++) { long long x; string y; cin >> x >> y; sort(y.begin(), y.end()); if (m[y] == 0) m[y] = x; else m[y] = min(m[y], x); } long long ans = INT_MAX; for (auto it = m.begin(); it != m.end(); it++) { for (auto i = m.begin(); i != m.end(); i++) { if (i == it) continue; string s1 = it->first; string s2 = i->first; set<char> s; for (long long p = 0; p < s1.size(); p++) s.insert(s1[p]); for (long long q = 0; q < s2.size(); q++) s.insert(s2[q]); if (s.size() == 3) ans = min(ans, m[s1] + m[s2]); } } if (m[ ABC ] > 0) ans = min(ans, m[ ABC ]); if (m[ A ] > 0 && m[ B ] > 0 && m[ C ] > 0) ans = min(ans, m[ A ] + m[ B ] + m[ C ]); if (ans != INT_MAX) cout << ans << endl; else cout << -1 << endl; }
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#include <bits/stdc++.h> using namespace std; namespace input { const int InputBufferSize = (1 << 24) + 5; char buffer[InputBufferSize], *s, *eof; inline void init() { assert(stdin != NULL); s = buffer; eof = s + fread(buffer, 1, InputBufferSize, stdin); } inline bool read(int& x) { x = 0; int flag = 1; while (!isdigit(*s) && *s != - ) s++; if (eof <= s) return false; if (*s == - ) flag = -1, s++; while (isdigit(*s)) x = x * 10 + *s++ - 0 ; x *= flag; return true; } inline bool read(char* str) { *str = 0; while (isspace(*s)) s++; if (eof < s) return false; while (!isspace(*s)) *str = 0, *str = *s, str++, s++; *str = 0; return true; } } // namespace input using namespace input; int const p = 1e9 + 7; int pr[305], cnt, a[400005], tmp[65], id[305], c[305], tree[1600005], tag[1600005]; long long b[400005], tree2[1600005], tag2[1600005]; bool flag[305]; long long res(int x) { memset(tmp, 0, sizeof(tmp)); long long res = 0; for (int i = 0; i <= 6; i++) while (!(x % pr[i])) x /= pr[i], res |= (1ll << i); if (x != 1) res |= (1ll << id[x]); return res; } int pw(int x, int y) { int res = 1; while (y) { if (y & 1) res = 1ll * res * x % p; x = 1ll * x * x % p; y >>= 1; } return res; } void build(int l, int r, int x) { if (l == r) { tree[x] = a[l]; tag[x] = 1; return; } int mid = (l + r) >> 1; build(l, mid, x * 2), build(mid + 1, r, x * 2 + 1); tree[x] = 1ll * tree[x * 2] * tree[x * 2 + 1] % p; tag[x] = 1; } void build2(int l, int r, int x) { if (l == r) { tree2[x] = b[l]; return; } int mid = (l + r) >> 1; build2(l, mid, x * 2), build2(mid + 1, r, x * 2 + 1); tree2[x] = (tree2[x * 2] | tree2[x * 2 + 1]); } void pushdown(int l, int r, int x) { if (tag[x] == 1) return; tree[x] = 1ll * tree[x] * pw(tag[x], r - l + 1) % p; if (l != r) tag[x * 2] = 1ll * tag[x * 2] * tag[x] % p, tag[x * 2 + 1] = 1ll * tag[x * 2 + 1] * tag[x] % p; tag[x] = 1; } void modify(int l, int r, int x, int a, int b, int c) { if (l >= a && r <= b) { tag[x] = 1ll * tag[x] * c % p; return; } int mid = (l + r) >> 1; if (a <= mid) modify(l, mid, x * 2, a, b, c); if (b > mid) modify(mid + 1, r, x * 2 + 1, a, b, c); pushdown(l, mid, x * 2), pushdown(mid + 1, r, x * 2 + 1); tree[x] = 1ll * tree[x * 2] * tree[x * 2 + 1] % p; } void pushdown2(int l, int r, int x) { if (!tag2[x]) return; tree2[x] |= tag2[x]; if (l != r) tag2[x * 2] |= tag2[x], tag2[x * 2 + 1] |= tag2[x]; tag2[x] = 0; } void modify2(int l, int r, int x, int a, int b, long long c) { if (l >= a && r <= b) { tag2[x] = (tag2[x] | c); return; } int mid = (l + r) >> 1; if (a <= mid) modify2(l, mid, x * 2, a, b, c); if (b > mid) modify2(mid + 1, r, x * 2 + 1, a, b, c); pushdown2(l, mid, x * 2), pushdown2(mid + 1, r, x * 2 + 1); tree2[x] = (tree2[x * 2] | tree2[x * 2 + 1]); } int ask(int l, int r, int x, int a, int b) { pushdown(l, r, x); if (l >= a && r <= b) return tree[x]; int mid = (l + r) >> 1, res = 1; if (a <= mid) res = ask(l, mid, x * 2, a, b); if (b > mid) res = 1ll * res * ask(mid + 1, r, x * 2 + 1, a, b) % p; return res; } long long ask2(int l, int r, int x, int a, int b) { pushdown2(l, r, x); if (l >= a && r <= b) return tree2[x]; int mid = (l + r) >> 1; long long res = 0; if (a <= mid) res = ask2(l, mid, x * 2, a, b); if (b > mid) res = (res | ask2(mid + 1, r, x * 2 + 1, a, b)); return res; } char op[15]; int main() { for (int i = 2; i <= 300; i++) { if (!flag[i]) pr[cnt] = i, id[i] = cnt, c[cnt] = 1ll * (i - 1) * pw(i, p - 2) % p, cnt++; for (int j = i * 2; j <= 300; j += i) flag[j] = 1; } init(); int n, q, l, r, x; long long y; read(n), read(q); for (int i = 1; i <= n; i++) { read(a[i]); b[i] = res(a[i]); } build(1, n, 1), build2(1, n, 1); while (q--) { read(op); if (op[0] == M ) { read(l), read(r), read(x); y = res(x); modify(1, n, 1, l, r, x), modify2(1, n, 1, l, r, y); } else { read(l), read(r); x = ask(1, n, 1, l, r), y = ask2(1, n, 1, l, r); for (int j = 0; j <= 61; j++) if (y & (1ll << j)) x = 1ll * x * c[j] % p; printf( %d n , x); } } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; const int NAX = 2e5 + 5, MOD = 1000000007; struct Solution { Solution() {} void solveCase() { set<string> ss; for (size_t i = 0; i <= 100; i += 4) { auto I = to_string(i); ss.insert(I); if (i < 10) { I = 0 + I; ss.insert(I); } } string str; cin >> str; char prev = 0 ; ll res = 0; ; for (size_t i = 0; i < str.size(); i++) { string curr = ; curr += str[i]; if (ss.count(curr)) res++; if (i > 0) { curr = prev + curr; if (ss.count(curr)) res += i; }; prev = str[i]; } cout << res << n ; } }; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; Solution mySolver; for (int i = 1; i <= t; ++i) { mySolver.solveCase(); } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 20:55:11 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
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`include "mio_regmap.vh"
module mio_if (/*AUTOARG*/
// Outputs
access_out, packet_out, wait_out, rx_wait_out, tx_access_out,
tx_packet_out,
// Inputs
clk, nreset, amode, emode, lsbfirst, datasize, ctrlmode, dstaddr,
wait_in, access_in, packet_in, rx_access_in, rx_packet_in,
tx_wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter AW = 32; // address width
parameter PW = 104; // emesh packet width
parameter MPW = 128; // mio packet width (> PW)
// reset, clk, config
input clk; // main core clock
input nreset; // async active low reset
input amode; // auto address mode
input emode; // emesh mode
input lsbfirst; // lsbfirst transfer
input [7:0] datasize; // datasize
input [4:0] ctrlmode; // emesh ctrlmode
input [AW-1:0] dstaddr; // destination address for amode
// core interface
output access_out; // pass through
output [PW-1:0] packet_out; // packet for core from rx
input wait_in; // pass through
input access_in; // pass through
input [PW-1:0] packet_in; // packet for tx from core
output wait_out; // pass through
// datapath interface (fifo)
input rx_access_in; // pass through
input [MPW-1:0] rx_packet_in; // packet from rx fifo
output rx_wait_out; // pass through
output tx_access_out; // pass through
output [MPW-1:0] tx_packet_out; // packet to tx fifo
input tx_wait_in; // pass through
//#####################################################################
//# BODY
//#####################################################################
wire [4:0] ctrlmode_out;
wire [AW-1:0] data_out;
wire [1:0] datamode_out;
wire [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire write_out;
wire [1:0] datamode;
wire [3:0] addr_stride;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
wire [1:0] datamode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
wire write_in; // From pe2 of packet2emesh.v
// End of automatics
/*AUTOINPUT*/
// pass throughs
assign rx_wait_out = wait_in;
assign access_out = rx_access_in;
assign tx_access_out = access_in;
assign wait_out = tx_wait_in;
// adapter for PW-->MPW width (MPW>=PW)
// shift up data on msbfirst shift
assign tx_packet_out[MPW-1:0] = (~lsbfirst & emode ) ? {packet_in[PW-1:0],{(MPW-PW-8){1'b0}}} :
(~lsbfirst ) ? {packet_in[PW-1:0],{(MPW-PW){1'b0}}} :
packet_in[PW-1:0];
//#################################################
// TRANSACTION FOR CORE (FROM RX)
//#################################################
// parse packet
packet2emesh #(.AW(AW),
.PW(PW))
pe2 (.packet_in (rx_packet_in[PW-1:0]),
/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]));
// datamode
assign datamode[1:0] = (datasize[3:0]==4'd1) ? 2'b00 :
(datasize[3:0]==4'd2) ? 2'b01 :
(datasize[3:0]==4'd4) ? 2'b10 :
2'b11;
//#################################################
// TRANSACTION FOR CORE (FROM RX)
//#################################################
// write only for amode (streaming data)
assign write_out = amode ? 1'b1 :
write_in;
// translate datasize to datamode
assign datamode_out[1:0] = amode ? datamode[1:0] :
datamode_in[1:0];
// ctrlmode from register in amode
assign ctrlmode_out[4:0] = amode ? ctrlmode[4:0] :
ctrlmode_in[4:0];
// address from
assign dstaddr_out[AW-1:0] = amode ? dstaddr[AW-1:0] :
dstaddr_in[AW-1:0];
// data in first 64 bits for amode
assign data_out[AW-1:0] = amode ? rx_packet_in[31:0] :
data_in[AW-1:0];
assign srcaddr_out[AW-1:0] = amode ? rx_packet_in[63:32] :
srcaddr_in[AW-1:0];
//Construct outgoing packet
emesh2packet #(.AW(AW),
.PW(PW))
e2p (/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.write_out (write_out),
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
endmodule // mio_if
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_1_V
`define SKY130_FD_SC_MS__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_1_V
|
// HeaderTrailer.v
//
// Author Beat Meier PSI
// Date Nov 10 2014
//
module HeaderTrailer
(
input Sdat,
input CLK,
input Trailer_OLD_NEW_0_1,
output reg TBM_HEADER,
output reg ROC_HEADER,
output reg TBM_TRAILER,
output reg gate,
output sdo
);
reg start;
reg [4:0]delay;
wire veto = delay != 0;
reg [14:0]shift;
// --- shift register (shift <- Sdat)
always @(posedge CLK) shift <= {shift[13:0], Sdat};
wire [8:0]leader = shift[11:3]; // 9 bit leader (011111111)
wire [2:0]id = shift[3:1]; // 3 bit header id (1 CLK cycle delayed)
assign sdo = shift[14]; // serial data output
// --- 9 bit start marker detector 011111111
always @(posedge CLK) start <= (leader == 9'b011111111) && !veto;
// --- veto counter to skip TBM header/trailer data
always @(posedge CLK)
begin
if (TBM_HEADER || TBM_TRAILER) delay <= 22;
else if (veto) delay <= delay - 1;
end
// --- header/trailer type separation
always @(posedge CLK)
begin
TBM_HEADER <= start && (id == 3'b100);
TBM_TRAILER <= start && (id == {2'b11, ~Trailer_OLD_NEW_0_1});
ROC_HEADER <= start && !id[2];
end
// --- data gate
always @(posedge CLK)
begin
if (TBM_HEADER) gate <= 1;
else if (TBM_TRAILER) gate <= 0;
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : timer.v
-- DESCRIPTION : ^C}
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "timer.h"
/********** W
[ **********/
module timer (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire rw, // Read / Write
input wire [`TimerAddrBus] addr, // AhX
input wire [`WordDataBus] wr_data, // «Ýf[^
output reg [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_, // fB
/********** èÝ **********/
output reg irq // èÝvi§äWX^ 1j
);
/********** §äWc^ **********/
// §äWX^ 0 : Rg[
reg mode; // [hrbg
reg start; // X^[grbg
// §äWX^ 2 : ¹l
reg [`WordDataBus] expr_val; // ¹l
// §äWX^ 3 : JE^
reg [`WordDataBus] counter; // JE^
/********** ¹tO **********/
wire expr_flag = ((start == `ENABLE) && (counter == expr_val)) ?
`ENABLE : `DISABLE;
/********** ^C}§ä **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
start <= #1 `DISABLE;
mode <= #1 `TIMER_MODE_ONE_SHOT;
irq <= #1 `DISABLE;
expr_val <= #1 `WORD_DATA_W'h0;
counter <= #1 `WORD_DATA_W'h0;
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* ÇÝoµANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`TIMER_ADDR_CTRL : begin // §äWX^ 0
rd_data <= #1 {{`WORD_DATA_W-2{1'b0}}, mode, start};
end
`TIMER_ADDR_INTR : begin // §äWX^ 1
rd_data <= #1 {{`WORD_DATA_W-1{1'b0}}, irq};
end
`TIMER_ADDR_EXPR : begin // §äWX^ 2
rd_data <= #1 expr_val;
end
`TIMER_ADDR_COUNTER : begin // §äWX^ 3
rd_data <= #1 counter;
end
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* «ÝANZX */
// §äWX^ 0
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_CTRL)) begin
start <= #1 wr_data[`TimerStartLoc];
mode <= #1 wr_data[`TimerModeLoc];
end else if ((expr_flag == `ENABLE) &&
(mode == `TIMER_MODE_ONE_SHOT)) begin
start <= #1 `DISABLE;
end
// §äWX^ 1
if (expr_flag == `ENABLE) begin
irq <= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_INTR)) begin
irq <= #1 wr_data[`TimerIrqLoc];
end
// §äWX^ 2
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_EXPR)) begin
expr_val <= #1 wr_data;
end
// §äWX^ 3
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_COUNTER)) begin
counter <= #1 wr_data;
end else if (expr_flag == `ENABLE) begin
counter <= #1 `WORD_DATA_W'h0;
end else if (start == `ENABLE) begin
counter <= #1 counter + 1'd1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int64_t read() { bool b = 0; int64_t n = 0; char c = getchar(); for (; !(( 0 ) <= (c) && (c) <= ( 9 )); c = getchar()) b = (c == - ); for (; (( 0 ) <= (c) && (c) <= ( 9 )); c = getchar()) n = 10 * n + (c - 0 ); if (b) n = -n; return n; } const int64_t N = 1e5 + 10; int64_t _log[2 * N], ss[2 * N][20], bl[N][20]; vector<int64_t> adj[N]; int64_t h[N], first[N]; vector<int64_t> et; int64_t V[N]; int64_t n, q; int64_t tin[N], tout[N], t = -1; int64_t stlen, sth; int64_t lp[N]; int64_t st[2 * N]; void calc(int64_t i, int64_t k) { st[i] = st[i << 1] + st[i << 1 | 1] + lp[i] * k; } void app(int64_t i, int64_t vv, int64_t k) { st[i] += vv * k; if (i < stlen) lp[i] += vv; } void build(int64_t l, int64_t r) { int64_t k = 2; for (l += stlen, r += stlen - 1; l > 1; k <<= 1) { l >>= 1, r >>= 1; for (int64_t i = r; i >= l; --i) calc(i, k); } } void push(int64_t l, int64_t r) { int64_t s = sth, k = 1 << (sth - 1); for (l += stlen, r += stlen - 1; s > 0; --s, k >>= 1) for (int64_t i = l >> s; i <= r >> s; ++i) if (lp[i] != 0) { app(i << 1, lp[i], k); app(i << 1 | 1, lp[i], k); lp[i] = 0; } } void add(int64_t l, int64_t r, int64_t vv) { push(l, l + 1), push(r - 1, r); int64_t l0 = l, r0 = r, k = 1; for (l += stlen, r += stlen; l < r; l >>= 1, r >>= 1, k <<= 1) { if (l & 1) app(l++, vv, k); if (r & 1) app(--r, vv, k); } build(l0, l0 + 1), build(r0 - 1, r0); } int64_t query(int64_t l, int64_t r) { int64_t l0 = l, r0 = r; push(l, l + 1), push(r - 1, r); int64_t res = 0; for (l += stlen, r += stlen; l < r; l >>= 1, r >>= 1) { if (l & 1) res += st[l++]; if (r & 1) res += st[--r]; } l = l0, r = r0; return res; } void _clog() { for (int64_t i = 2; i < 2 * N; ++i) _log[i] = _log[i >> 1] + 1; } void clca() { int64_t n = et.size(); for (int64_t i = 0; (i) < (n); ++(i)) ss[i][0] = et[i]; for (int64_t k = 1; (1 << k) <= n; ++k) for (int64_t i = 0; i + (1 << k) <= n; ++i) { int64_t j = i + (1 << (k - 1)); if (h[ss[i][k - 1]] < h[ss[j][k - 1]]) ss[i][k] = ss[i][k - 1]; else ss[i][k] = ss[j][k - 1]; } } int64_t lca(int64_t l, int64_t r) { l = first[l], r = first[r]; if (r < l) swap(l, r); int64_t k = _log[r - l + 1]; int64_t a = ss[l][k], b = ss[r - (1 << k) + 1][k]; if (h[a] < h[b]) return a; else return b; } void pdfs(int64_t v, int64_t p) { first[v] = int64_t((et).size()); tin[v] = ++t; et.push_back(v); bl[v][0] = p; for (int64_t i = 0; (i) < (19); ++(i)) bl[v][i + 1] = bl[bl[v][i]][i]; for (int64_t c : adj[v]) { if (c == p) continue; h[c] = h[v] + 1; pdfs(c, v); et.push_back(v); } tout[v] = t; } int64_t rlca(int64_t root, int64_t l, int64_t r) { return lca(l, root) ^ lca(r, root) ^ lca(l, r); } int64_t up(int64_t v, int64_t first) { for (int64_t i = 19; first && i >= 0; --i) if ((1 << i) <= first) v = bl[v][i], first -= (1 << i); return v; } int64_t qsub(int64_t v) { return query(tin[v], tout[v] + 1); } void msub(int64_t v, int64_t vv) { add(tin[v], tout[v] + 1, vv); } int main() { ; n = read(), q = read(), stlen = n; sth = 8 * 4 - __builtin_clz(stlen); ; for (int64_t i = 0; (i) < (n); ++(i)) V[i] = read(); int64_t a, b; for (int64_t i = 0; (i) < (n - 1); ++(i)) { a = read() - 1, b = read() - 1; adj[a].push_back(b); adj[b].push_back(a); } _log[1] = 0; _clog(); pdfs(0, 0); clca(); ; for (int64_t i = 0; (i) < (n); ++(i)) ; ; ; ; for (int64_t i = 0; (i) < (n); ++(i)) ; ; ; for (int64_t i = 0; (i) < (n); ++(i)) st[stlen + tin[i]] = V[i]; build(0, n); int64_t op, root = 0; while (q--) { op = read(); if (op == 1) { root = read() - 1; } else if (op == 2) { int64_t v = rlca(root, read() - 1, read() - 1); int64_t vv = read(); if (root == v) { msub(0, vv); } else if (lca(v, root) == v) { ; msub(0, vv), msub(up(root, h[root] - h[v] - 1), -vv); } else { msub(v, vv); } } else { int64_t v = read() - 1; ; assert(op == 3); if (root == v) { printf( %lld n , qsub(0)); } else if (lca(v, root) == v) { ; ; printf( %lld n , qsub(0) - qsub(up(root, h[root] - h[v] - 1))); } else { printf( %lld n , qsub(v)); } }; for (int64_t i = 0; (i) < (n); ++(i)) ; ; ; } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty (1'b0),
.in_error (1'b0),
.in_channel (1'b0),
.in_csr_address (1'b0),
.in_csr_read (1'b0),
.in_csr_write (1'b0),
.in_csr_writedata (32'b0),
.out_csr_address (1'b0),
.out_csr_read (1'b0),
.out_csr_write (1'b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty (1'b0),
.in_error (1'b0),
.in_channel (1'b0),
.in_csr_address (1'b0),
.in_csr_read (1'b0),
.in_csr_write (1'b0),
.in_csr_writedata (32'b0),
.out_csr_address (1'b0),
.out_csr_read (1'b0),
.out_csr_write (1'b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int const maxn = 100 * 1000 + 5; int a[maxn]; int b[maxn]; int main() { int t; cin >> t; int n, f1, fm1; for (int i = 0; i < t; i++) { f1 = maxn; fm1 = maxn; cin >> n; for (int j = 0; j < n; j++) { cin >> a[j]; if (a[j] == 1 && f1 == maxn) f1 = j; if (a[j] == -1 && fm1 == maxn) fm1 = j; } bool check = true; for (int j = 0; j < n; j++) { cin >> b[j]; } for (int j = n - 1; j >= 0; j--) { if (j > 0) { if (a[j] < b[j] && f1 >= j) check = false; if (a[j] > b[j] && fm1 >= j) check = false; } else { if (a[j] != b[j]) check = false; } if (!check) break; } if (check) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; queue<int> q1, q2, q3, q4, q5, q6; int main() { int n, x, ans = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); if (x == 4) q1.push(i); else if (x == 8) q2.push(i); else if (x == 15) q3.push(i); else if (x == 16) q4.push(i); else if (x == 23) q5.push(i); else q6.push(i); } if (q1.empty() || q2.empty() || q3.empty() || q4.empty() || q5.empty() || q6.empty()) { printf( %d n , n - ans); return 0; } while (1) { if (q2.front() > q1.front()) { if (q3.front() > q2.front()) { if (q4.front() > q3.front()) { if (q5.front() > q4.front()) { if (q6.front() > q5.front()) { ans += 6; q1.pop(); q2.pop(); q3.pop(); q4.pop(); q5.pop(); q6.pop(); } else q6.pop(); } else q5.pop(); } else q4.pop(); } else q3.pop(); } else q2.pop(); if (q1.empty() || q2.empty() || q3.empty() || q4.empty() || q5.empty() || q6.empty()) break; } printf( %d n , n - ans); return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Video_In_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23;
parameter ODW = 15;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[15:11] = r[ 9: 5];
assign converted_data[10: 5] = g[ 9: 4];
assign converted_data[ 4: 0] = b[ 9: 5];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______167.017____114.212
// CLK_OUT2____25.000______0.000______50.0______191.696____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (16),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
endmodule
|
// Bus selector/mux
// select between two buses
// depending on which input port
// was last active
// To be used after an arbitrer
module selector_r1_2ph (/*AUTOARG*/
// Outputs
dataout,
// Inputs
r1, a1, r2, a2, datain1, datain2, rstn
);
parameter WIDTH = 8;
input r1;
input a1;
input r2;
input a2;
input [WIDTH-1:0 ]datain1;
input [WIDTH-1:0] datain2;
output [WIDTH-1:0] dataout;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire port1_active;
wire port2_active;
wire muxsel;
wire rstn;
wire [WIDTH-1:0] dataout;
assign port1_active = r1 ^a1;
assign port2_active = r2 ^a2;
rs_ff U_RS(
.set(port2_active),
.reset(port1_active),
.q(muxsel),
.qn(),
.async_rst_neg(rstn)
);
assign dataout = muxsel ? datain2 : datain1;
endmodule // selector_r1_2ph
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
`timescale 1ns / 1ps
//
// PDP-11 datapath.
//
module datapath (
input wire clk, // External clock signal
input wire reset // External active high reset signal
);
// Control.
wire [2:0] ctl_reg_src, ctl_reg_dst; // src/dst reg numbers
wire [1:0] ctl_alu_input; // alu source from src or x, dst or y
wire [9:0] ctl_alu_op; // alu operation code
wire [2:0] ctl_mem_addr; // memory address src/dst/src+x/dst+y/x/y/z
wire ctl_mem_byte; // memory byte mode
wire ctl_reg_input; // write to regfile from mem out
wire ctl_reg_we; // register file write enable
wire ctl_x_we; // x register write
wire ctl_y_we; // y register write
wire ctl_z_we; // z register write
wire ctl_psw_we; // psw register write
wire ctl_mem_we; // memory write
wire ctl_ir_we; // instruction register write
// Output of ALU
wire [15:0] alu_out;
// Output of RAM
wire [15:0] mem_out;
// Output of register file: source and destination registers
wire [15:0] src, dst;
// Input of register file: from memory or from ALU
wire [15:0] reg_input = ctl_reg_input ? mem_out : alu_out;
// Register file.
// On reset, PC is cleared.
regfile regfile (
.sela (ctl_reg_src),
.selb (ctl_reg_dst),
.we (ctl_reg_we),
.clk (clk),
.reset (reset),
.w (reg_input),
.a (src),
.b (dst)
);
// Registers X, Y - hold data from memory.
// Used for source and destination indirect addressing modes.
reg [15:0] x, y;
always @(posedge clk) begin
if (ctl_x_we == 1) begin
x <= mem_out;
$display ("%4d-%1d) X := %o", $time, cycount, mem_out);
end
if (ctl_y_we == 1) begin
y <= mem_out;
$display ("%4d-%1d) Y := %o", $time, cycount, mem_out);
end
end
// Data buses on input of ALU
wire [15:0] alu_ina = ctl_alu_input[0] ? x : src;
wire [15:0] alu_inb = ctl_alu_input[1] ? y : dst;
// Resulting state
wire [7:0] alu_state;
// Register PSW - hold ALU state
reg [7:0] psw;
always @(posedge clk) begin
if (ctl_psw_we == 1) begin
psw <= alu_state;
$display ("%4d-%1d) PSW := %02o", $time, cycount, alu_state);
end
end
// ALU
alu alu (
.op (ctl_alu_op),
.a (alu_ina),
.b (alu_inb),
.ps_in (psw),
.d (alu_out),
.ps_out (alu_state)
);
// Memory address
wire [15:0] mem_addr =
(ctl_mem_addr == 3'd0) ? src : // src
(ctl_mem_addr == 3'd1) ? src + x : // src + X
(ctl_mem_addr == 3'd2) ? dst : // dst
(ctl_mem_addr == 3'd3) ? dst + y : // dst + Y
(ctl_mem_addr == 3'd4) ? x : // X
(ctl_mem_addr == 3'd5) ? y : // Y
z; // Z
// Register Z - hold memory address
reg [15:0] z;
always @(posedge clk) begin
if (ctl_z_we == 1) begin
z <= mem_addr;
$display ("%4d-%1d) Z := %o", $time, cycount, mem_addr);
end
end
// RAM
memory ram (
.addr (mem_addr),
.we (ctl_mem_we),
.clk (clk),
.bytew (ctl_mem_byte),
.d_in (alu_out),
.d_out (mem_out)
);
// Instruction register.
reg [15:0] ir;
always @(posedge clk) begin
if (ctl_ir_we == 1 && ! reset) begin
ir <= mem_out;
$c ("extern void trace_fetch (unsigned cycount, unsigned mem_addr, unsigned mem_out);");
$c ("trace_fetch (", cycount, ",", mem_addr, ",", mem_out, ");");
//$display (" reg_src %o - src %o", ctl_reg_src, src);
//$display (" reg_dst %o - dst %o", ctl_reg_dst, dst);
end
end
// Cycle counter. Changed on negative clk edge.
// On reset, TC is cleared.
reg [2:0] cycount;
wire [2:0] cycount_next;
always @(posedge clk) begin
//$display ("%4d-%1d) cycount := %0d", $time, cycount, reset ? 0 : cycount_next);
cycount <= reset ? 0 : cycount_next;
end
// Control unit
control control (
.cmd (ir),
.cycle (cycount),
.cnext (cycount_next),
.reg_from_mem (ctl_reg_input),
.reg_src (ctl_reg_src),
.reg_dst (ctl_reg_dst),
.reg_we (ctl_reg_we),
.mem_addr (ctl_mem_addr),
.mem_byte (ctl_mem_byte),
.x_we (ctl_x_we),
.y_we (ctl_y_we),
.z_we (ctl_z_we),
.alu_input (ctl_alu_input),
.alu_op (ctl_alu_op),
.psw_we (ctl_psw_we),
.mem_we (ctl_mem_we),
.ir_we (ctl_ir_we)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } void XsliferX() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); } long long f_p(long long x, int y) { if (y == 0) return 1; else if (y % 2 == 0) return f_p(x * x, y / 2); else return x * f_p(x * x, y / 2); } long long l_p(long long n) { n = n | (n >> 1); n = n | (n >> 2); n = n | (n >> 4); n = n | (n >> 8); return (n + 1) >> 1; } int dp[5005]; int a[5005]; int n; int L[5005], R[5005]; bool vis[5005]; int solve(int idx) { int x = 0; int lft = L[a[idx]], rit = R[a[idx]]; if (idx == n) return 0; if (dp[idx] != -1) return dp[idx]; for (int i = L[a[idx]]; i <= R[a[idx]]; i++) { if (lft > L[a[i]]) lft = L[a[i]]; if (rit < R[a[i]]) rit = R[a[i]]; } bool v[5005] = {0}; if (idx == lft) { int xo = 0; for (int i = lft; i <= rit; i++) { if (!v[a[i]]) { xo ^= a[i]; v[a[i]] = 1; } vis[a[i]] = 1; } x = max(x, solve(rit + 1) + xo); for (int i = lft; i < rit; i++) { vis[a[i]] = 0; } } vis[a[idx]] = 1; x = max(x, solve(idx + 1)); vis[a[idx]] = 0; return dp[idx] = x; } int main() { memset(dp, -1, sizeof dp); cin >> n; for (int i = 0; i < n; i++) cin >> a[i], R[a[i]] = i; memset(L, -1, sizeof L); for (int i = 0; i < n; i++) if (L[a[i]] == -1) L[a[i]] = i; cout << solve(0) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_SYMBOL_V
/**
* lpflow_inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso1n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_SYMBOL_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Nov 03 20:56:59 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/half_band_FIR_stub.v
// Design : half_band_FIR
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.2" *)
module half_band_FIR(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [23:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_BLACKBOX_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int nmax = 110; char s[nmax]; bool pal(int n) { int i; for (i = 0; i <= (n - 1) / 2; i++) if (abs(s[i] - s[n - i - 1]) > 2 || abs(s[i] - s[n - i - 1]) == 1) return 0; return 1; } int main() { int t, n, i; cin >> t; for (i = 1; i <= t; i++) { cin >> n >> s; if (pal(n) == 1) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MAXN = 23; int parseInt() { int d; scanf( %d , &d); ; return d; } int n; int a[MAXN], b[MAXN]; vector<pair<int, int> > v; map<int, int> rang; int main() { cin >> n; for (int i = 0; i < n; ++i) { a[i] = parseInt(); v.push_back(make_pair(a[i], i)); } sort(v.begin(), v.end()); for (int i = 0; i < n; ++i) { rang[v[i].first] = i; b[i] = v[i].first; } int rng; for (int i = 0; i < n; ++i) { rng = rang[a[i]]; rng = (rng + 1) % n; cout << b[rng] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int T, n; long long W; pair<long long, int> w[N]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); for (cin >> T; T--;) { vector<int> id; cin >> n >> W; long long x = W; for (int i = 1; i <= n; ++i) cin >> w[i].first, w[i].second = i; sort(w + 1, w + n + 1, greater<pair<int, int> >()); for (int i = 1; i <= n; ++i) if (w[i].first <= x) x -= w[i].first, id.push_back(w[i].second); if (W - x < (W + 1) / 2) cout << -1 n ; else { cout << id.size() << n ; for (int i : id) cout << i << ; cout << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool ps[1111111]; const int mod = 1e9 + 7; int main() { int p, k, c = 0; long long ans = 1; scanf( %d%d , &p, &k); for (int i = 0; i < p; ++i) { if (ps[i]) continue; c++; long long b = i; while (!ps[b]) ps[b] = 1, b = (b * k) % p; } if (k != 1) c--; while (c--) ans = (ans * p) % mod; printf( %d n , int(ans)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1E3 + 5; int n; struct line { int x, y, w, num; line(int a = 0, int b = 0, int c = 0, int d = 0) : x(a), y(b), w(c), num(d) {} bool operator<(const line& A) const { return w > A.w; } } a[maxn], b[maxn]; vector<line> ans; inline bool inter(line x, line y) { int l1 = min(x.x, x.y), r1 = max(x.x, x.y); int l2 = min(y.x, y.y), r2 = max(y.x, y.y); return (l1 < l2 && l2 < r1 && r1 < r2) || (l2 < l1 && l1 < r2 && r2 < r1); } inline int dis(line A, int x) { int l = min(A.x, A.y), r = max(A.x, A.y); if (l <= x && x <= r) return n - (r - l); return r - l; } inline void solve(int x, int y) { vector<line> wait; for (int i = 1; i <= n - 3; ++i) if (inter(a[i], line(x, y))) wait.push_back(line(a[i].x, a[i].y, dis(a[i], x), i)); if (wait.size() == 0) return; sort(wait.begin(), wait.end()); for (int i = 0; i < wait.size() - 1; ++i) { ans.push_back(wait[i]); int p = wait[i].num; if (wait[i].x == wait[i + 1].x) { a[p].x = wait[i + 1].y; a[p].y = x; } else if (wait[i].y == wait[i + 1].x) { a[p].y = wait[i + 1].y; a[p].x = x; } else if (wait[i].x == wait[i + 1].y) { a[p].x = wait[i + 1].x; a[p].y = x; } else { a[p].y = wait[i + 1].x; a[p].x = x; } } ans.push_back(wait[wait.size() - 1]); int p = wait[wait.size() - 1].num; a[p].x = x, a[p].y = y; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n - 3; ++i) cin >> a[i].x >> a[i].y; for (int i = 1; i <= n - 3; ++i) cin >> b[i].x >> b[i].y; random_shuffle(b + 1, b + n - 3 + 1); for (int i = 1; i <= n - 3; ++i) solve(b[i].x, b[i].y); cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) cout << ans[i].x << << ans[i].y << n ; return 0; }
|
`timescale 1 ns / 1 ps
module axis_ram_writer #
(
parameter integer ADDR_WIDTH = 20,
parameter integer AXI_ID_WIDTH = 6,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXIS_TDATA_WIDTH = 64
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [AXI_ADDR_WIDTH-1:0] cfg_data,
output wire [ADDR_WIDTH-1:0] sts_data,
// Master side
output wire [AXI_ID_WIDTH-1:0] m_axi_awid, // AXI master: Write address ID
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, // AXI master: Write address
output wire [3:0] m_axi_awlen, // AXI master: Write burst length
output wire [2:0] m_axi_awsize, // AXI master: Write burst size
output wire [1:0] m_axi_awburst, // AXI master: Write burst type
output wire [3:0] m_axi_awcache, // AXI master: Write memory type
output wire m_axi_awvalid, // AXI master: Write address valid
input wire m_axi_awready, // AXI master: Write address ready
output wire [AXI_ID_WIDTH-1:0] m_axi_wid, // AXI master: Write data ID
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, // AXI master: Write data
output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, // AXI master: Write strobes
output wire m_axi_wlast, // AXI master: Write last
output wire m_axi_wvalid, // AXI master: Write valid
input wire m_axi_wready, // AXI master: Write ready
output wire m_axi_bready, // AXI master: Write response ready
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);
reg int_awvalid_reg, int_awvalid_next;
reg int_wvalid_reg, int_wvalid_next;
reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
wire int_full_wire, int_empty_wire, int_rden_wire;
wire int_wlast_wire, int_tready_wire;
wire [71:0] int_wdata_wire;
assign int_tready_wire = ~int_full_wire;
assign int_wlast_wire = &int_addr_reg[3:0];
assign int_rden_wire = m_axi_wready & int_wvalid_reg;
FIFO36E1 #(
.FIRST_WORD_FALL_THROUGH("TRUE"),
.ALMOST_EMPTY_OFFSET(13'hf),
.DATA_WIDTH(72),
.FIFO_MODE("FIFO36_72")
) fifo_0 (
.FULL(int_full_wire),
.ALMOSTEMPTY(int_empty_wire),
.RST(~aresetn),
.WRCLK(aclk),
.WREN(int_tready_wire & s_axis_tvalid),
.DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
.RDCLK(aclk),
.RDEN(m_axi_wready & int_wvalid_reg),
.DO(int_wdata_wire)
);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
end
else
begin
int_awvalid_reg <= int_awvalid_next;
int_wvalid_reg <= int_wvalid_next;
int_addr_reg <= int_addr_next;
int_wid_reg <= int_wid_next;
end
end
always @*
begin
int_awvalid_next = int_awvalid_reg;
int_wvalid_next = int_wvalid_reg;
int_addr_next = int_addr_reg;
int_wid_next = int_wid_reg;
if(~int_empty_wire & ~int_awvalid_reg & ~int_wvalid_reg)
begin
int_awvalid_next = 1'b1;
int_wvalid_next = 1'b1;
end
if(m_axi_awready & int_awvalid_reg)
begin
int_awvalid_next = 1'b0;
end
if(int_rden_wire)
begin
int_addr_next = int_addr_reg + 1'b1;
end
if(m_axi_wready & int_wlast_wire)
begin
int_wid_next = int_wid_reg + 1'b1;
if(int_empty_wire)
begin
int_wvalid_next = 1'b0;
end
else
begin
int_awvalid_next = 1'b1;
end
end
end
assign sts_data = int_addr_reg;
assign m_axi_awid = int_wid_reg;
assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
assign m_axi_awcache = 4'b0011;
assign m_axi_awvalid = int_awvalid_reg;
assign m_axi_wid = int_wid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wlast = int_wlast_wire;
assign m_axi_wvalid = int_wvalid_reg;
assign m_axi_bready = 1'b1;
assign s_axis_tready = int_tready_wire;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSHOLD_BLACKBOX_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold (
X ,
RESET
);
inout X ;
input RESET;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1E18; const int MAXN = 2000; int l[MAXN]; int r[MAXN]; int a[MAXN]; long long dp[MAXN]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; bool poss = true; long long extra = 0; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i] >> a[i]; if (i && l[i] > r[i - 1]) extra = 0; long long bullets = extra + a[i]; if (bullets > (long long)(r[i] - l[i] + 1) * k) { poss = false; } extra = max(0LL, bullets - (long long)(r[i] - l[i]) * k); } if (!poss) { cout << -1 n ; return 0; } dp[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; i--) { dp[i] = INF; extra = 0; long long totalUsed = 0; for (int j = i; j < n; j++) { totalUsed += a[j]; long long bullets = extra + a[j]; if (bullets > (long long)(r[j] - l[j] + 1) * k) break; extra = bullets % k; if (j < n - 1) { long long last = max(0LL, bullets - (long long)(r[j] - l[j]) * k); if (r[j] < l[j + 1] || !last) { if (extra) dp[i] = min(dp[i], totalUsed + (k - extra) + dp[j + 1]); else dp[i] = min(dp[i], totalUsed + dp[j + 1]); } } else { dp[i] = min(dp[i], totalUsed); } } } cout << dp[0] << n ; return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_arbiter (clock, reset, enable, reqs, priorities, gnts, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 2;
parameter priority_width = 1;
parameter min_cks = 1;
parameter max_cks = 0;
parameter one_cycle_gnt_check = 1;
parameter priority_check = 0;
parameter arbitration_rule = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] reqs;
input [width-1 : 0] gnts;
input [(width*priority_width)-1 : 0] priorities;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ARBITER";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_arbiter_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_arbiter
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <typename A, size_t N, typename T> void Fill(A (&array)[N], const T& val) { fill((T*)array, (T*)(array + N), val); } const int inf = INT_MAX / 2; const long long int INF = LLONG_MAX / 2; vector<int> g[100010]; int main() { int n, m; scanf( %d%d , &n, &m); vector<pair<long long int, long long int> > check(m); for (int i = (0); i < (m); i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; g[x].push_back(y); g[y].push_back(x); check[i] = {x, y}; } int ans[100010] = {}; int idx = 0; for (int st = (1); st < (4); st++) { while (idx < n && ans[idx]) idx++; if (idx == n) { printf( -1 n ); return 0; } ans[idx] = st; bool used[100010] = {}; used[idx] = 1; for (int nxt : g[idx]) { used[nxt] = 1; } for (int i = (0); i < (n); i++) if (!used[i]) { if (ans[i] && ans[i] != st) { printf( -1 n ); return 0; } ans[i] = st; } } bool f = 1; int cnt[4] = {}; for (int i = (0); i < (n); i++) { if (ans[i] == 0) f = 0; cnt[ans[i]]++; } for (int i = (0); i < (m); i++) { if (ans[check[i].first] == ans[check[i].second]) f = 0; } if (m != cnt[1] * cnt[2] + cnt[2] * cnt[3] + cnt[3] * cnt[1]) f = 0; if (f) for (int i = (0); i < (n); i++) printf( %d n , ans[i]); else printf( -1 n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_PP_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*
*
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "bmu.v"
module bmutb;
// Modify the number of bits in the ouput bus to be 2
wire [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
reg cx0, cx1;
bmu bmu1 (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
initial
begin
cx0=0; cx1=0;
#10;
cx0=0; cx1=1;
#10;
cx0=1; cx1=0;
#10;
cx0=1; cx1=1;
#10;
cx0=0; cx1=0;
#10;
end
initial
begin
$shm_open("bmu.shm");
$shm_probe("AC");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long INFL = 1e18 + 123; const double PI = atan2(0, -1); mt19937 tw(960172); long long rnd(long long x, long long y) { static uniform_int_distribution<long long> d; return d(tw) % (y - x + 1) + x; } bool check(string s) { string tmp = s; reverse(tmp.begin(), tmp.end()); return tmp != s; } void solve() { string s; cin >> s; int ans = 0; for (int i = 0; i < ((int)(s).size()); ++i) { string cur = ; for (int j = i; j < ((int)(s).size()); ++j) { cur += s[j]; if (check(cur)) { ans = max(ans, j - i + 1); } } } cout << ans << n ; } int main() { cerr << fixed << setprecision(15); cout << fixed << setprecision(15); ios::sync_with_stdio(false); int tests = 1; for (int it = 1; it <= tests; ++it) { solve(); } return 0; }
|
/*
* Copyright (c) 2002 Michael Ruff (mruff @chiaro.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module top;
reg \bot.r ;
bot bot();
initial begin
#1;
\bot.r = 1;
#1;
$display("\\bot.r == %b", \bot.r );
$display("bot.r == %b", bot.r );
if (\bot.r !== 1) begin
$display("FAILED -- \\bot.r !== 1");
$finish;
end
if (bot.r !== 0) begin
$display("FAILED -- bot.r !== 0");
$finish;
end
$display("PASSED");
end
endmodule // top
module bot;
reg r;
initial begin
r = 0;
end
endmodule
|
#include<iostream> #include<cstdio> #include<unordered_map> using namespace std; const int N=105; const int MOD=1000000007; int n,q; int c[N]; int b[N]; int sb[N],sc[N]; int l,r; int solve(int x) { static int f[N][N*N],g[N][N*N]; f[0][0]=g[0][0]=1; for(int i=1;i<=n;i++) { for(int j=0;j<max(i*x+sb[i-1],0);j++) f[i][j]=0; for(int j=max(i*x+sb[i-1],0);j<=sc[i];j++) f[i][j]=((long long)g[i-1][j-max(j-sc[i-1],0)]-(j-min(c[i],j)-1>=0?g[i-1][j-min(c[i],j)-1]:0)+MOD)%MOD; g[i][0]=f[i][0]; for(int j=1;j<=sc[i];j++) g[i][j]=(g[i][j-1]+f[i][j])%MOD; } int ans=0; for(int j=0;j<=sc[n];j++) ans=(ans+f[n][j])%MOD; return ans; } unordered_map<int,int>res; int main() { scanf( %d ,&n); for(int i=1;i<=n;i++) scanf( %d ,&c[i]); for(int i=1;i<n;i++) scanf( %d ,&b[i]); for(int i=1;i<n;i++) sb[i]=sb[i-1]+b[i]; for(int i=1;i<n;i++) sb[i]+=sb[i-1]; for(int i=1;i<=n;i++) sc[i]=sc[i-1]+c[i]; r=(sc[n]-sb[n-1])/n; for(int i=1;i<n;i++) r=min(r,(sc[i]-sb[i-1])/i); l=-sb[n-1]/n; for(int i=1;i<n;i++) l=min(l,sb[i-1]/i); for(int i=l;i<=r;i++) res[i]=solve(i); int pw=1; for(int i=1;i<=n;i++) pw=1LL*pw*(c[i]+1)%MOD; scanf( %d ,&q); while(q--) { int x; scanf( %d ,&x); if(x<l) printf( %d n ,pw); else if(x>r) printf( %d n ,0); else printf( %d n ,res[x]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int p[100001], w[100001]; vector<pair<int, int>> e[100001]; long long ans[100001], sum; int root(int x) { while (x != p[x]) x = p[x] = p[p[x]]; return x; } void pre(int x, int from) { sum += w[x]; for (auto c : e[x]) if (c.first != from) pre(c.first, x); } int gao(int x, int from, int t) { int cnt = w[x]; for (auto c : e[x]) { if (c.first == from) continue; cnt += gao(c.first, x, c.second); } e[x].clear(); ans[t] = cnt * (sum - cnt) * 2; return cnt; } int main() { int n; scanf( %d , &n); map<int, vector<pair<pair<int, int>, int>>> u; for (int i = 1; i <= n; i++) w[p[i] = i] = 1; for (int i = 1; i != n; i++) { int x, y, c; scanf( %d%d%d , &x, &y, &c); u[c].push_back({{x, y}, i}); } for (auto& r : u) { vector<int> v; for (auto c : r.second) { int x = root(c.first.first); int y = root(c.first.second); int t = c.second; e[x].push_back({y, t}); e[y].push_back({x, t}); v.push_back(x); v.push_back(y); } sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); for (auto x : v) if (!e[x].empty()) { pre(x, sum = 0); gao(x, 0, 0); } for (auto c : r.second) { int x = root(c.first.first); int y = root(c.first.second); if (w[x] < w[y]) w[p[x] = y] += w[x]; else w[p[y] = x] += w[y]; } } long long tmp = *max_element(ans + 1, ans + n); printf( %I64d %d n , tmp, count(ans + 1, ans + n, tmp)); for (int i = 1; i != n; i++) if (ans[i] == tmp) printf( %d , i); }
|
/* Ragul's FPGA Experiments 2020
* Tested with the EG4S20BG256 FPGA
* Learning to generate VGA signalz
*
* http://tinyvga.com/vga-timing/640x480@60Hz
* https://www.youtube.com/watch?v=4enWoVHCykI
* https://www.fpga4fun.com/PongGame.html
*
* ATTRIBUTE IF YOU END UP USING ANY OF MY WORK
*/
module top(
input wire CLK_24M,
input wire USR_BTN,
output wire [2:0]VGA_RGB,
output wire HSYNC,
output wire VSYNC
);
reg enVcnt;
reg [10:0] hzcount;
reg [10:0] vtcount;
reg RED;
reg BLU;
reg GRN;
initial begin
enVcnt <= 0;
hzcount <= 0;
vtcount <= 0;
end
always @(posedge CLK_24M) begin
if (hzcount < 799) begin
hzcount <= hzcount + 1'b1;
enVcnt <= 0;
end
else begin
hzcount <= 0;
enVcnt <= 1;
end
if (enVcnt == 1'b1) begin
if (vtcount < 524) begin
vtcount <= vtcount + 1'b1;
end
else begin
vtcount <= 0;
end
end
if (hzcount < 639 && vtcount < 479) begin
RED <= vtcount[(hzcount >> 6) % 11];
end
else begin
RED <= 0;
GRN <= 0;
BLU <= 0;
end
end
assign VGA_RGB[0] = RED;
assign VGA_RGB[1] = GRN;
assign VGA_RGB[2] = BLU;
assign HSYNC = (hzcount > 655 && hzcount < 751) ? 1'b1 : 1'b0;
assign VSYNC = (vtcount > 489 && vtcount < 491) ? 1'b1 : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops,no-stack-protector,unsafe-math-optimizations ) #pragma GCC target( avx ) inline int read_char() { static char buf[1 << 16], *ptr = buf, *end_ptr = buf; if (ptr == end_ptr) { int len = fread(buf, 1, sizeof(buf), stdin); if (len <= 0) return EOF; ptr = buf; end_ptr = buf + len; } return *ptr++; } inline int read_int() { int ch; bool sg = 0; do { ch = read_char(); if (ch == - ) sg = 1; } while (ch < 0 || ch > 9 ); int x = ch - 0 ; while (true) { ch = read_char(); if (ch < 0 || ch > 9 ) break; x = x * 10 + ch - 0 ; } return (sg ? -x : x); } float __attribute__((aligned(64))) a[100005]; int n, m, ans, t, l, r; float x; int main() { n = read_int(); m = read_int(); for (int i = 1; i <= n; i++) a[i] = read_int(); for (int i = 1; i <= m; i++) { t = read_int(); l = read_int(); r = read_int(); x = read_int(); if (t == 1) { for (int j = l; j <= r; j++) if (a[j] > x) a[j] -= x; } else { ans = 0; for (int j = l; j <= r; j++) ans += (a[j] == x); printf( %d n , ans); } } }
|
module top;
reg [31:0] in1, in2;
reg [4:0] addr3;
reg [31:0] data3;
reg chksignal;
reg [31:0] in, address;
wire [5:0] opcode, funct;
wire [31:0] pc, inst;
wire [4:0] rs, rt, rd;
wire [15:0] addr;
wire [31:0] result, Rs, Rt, out, extendaddr, newpc;
clkGen CLK(clk);
PC pc1(pc,in,clk);
instMem IM(inst,pc,clk);
Splitter SP(inst,opcode,rs,rt,rd,funct,addr);
ALU al(opcode,funct,in1,in2,result,rw,clk);
RegisterFile RF(rw,rs,rt,Rs,Rt,addr3,data3,clk);
dataMem DM(opcode,Rt,address,clk,out);
signExtend SE(addr,extendaddr);
PC_ALU alpc(newpc,pc,extendaddr,chksignal);
always @(*)
begin
if(opcode==6'b000000)
begin
if(funct==6'b100000||funct==6'b100010||funct==6'b100100||funct==6'b100101)
begin
in1=Rs;
in2=Rt;
addr3=rd;
data3=result;
chksignal=1'b0;
in=newpc;
end
end
if(opcode==6'b100011)
begin
in1=Rs;
in2=extendaddr;
address=result;
addr3=rt;
data3=out;
chksignal=1'b0;
in=newpc;
end
if(opcode==6'b101011)
begin
in1=Rs;
in2=extendaddr;
address=result;
chksignal=1'b0;
in=newpc;
end
if(opcode==6'b000100)
begin
in1=Rs;
in2=Rt;
if(result==32'h00000000)
begin
chksignal=1'b1;
in=newpc;
end
end
end
//always @(posedge clk)
//begin
// in1 <= in1 + 1'b1;
// in <= in + 1'b1;
// in2 <= in2 - 1'b1;
//end
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, top);
end
initial begin
//in=6'b000000;
//in1=32'h00000000;
//in2=32'hFF00F0;
$monitor("pc = %5d inst=0x%h in1 = %5d in2 = %5d result = %5d time=%5d clk = %5d",pc,inst,in1,in2,result,$time,clk);
#10
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_2_V
`define SKY130_FD_SC_HS__XOR3_2_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:36:03 09/06/2013
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter(div_clk,rst,time_value,contando, terminado);
input div_clk;
input rst;
input contando;
input [3:0] time_value;
output reg terminado;
reg [3:0] contador;
always @(posedge div_clk or posedge rst)
begin
if(rst)
begin
contador <= 0;
terminado <= 0;
end
else
if(contando)
begin
if(contador == time_value)
begin
contador <= 0;
terminado <= 1;
end
else
begin
terminado <= 0;
contador <= contador + 1;
end
end
else
terminado <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_1_V
`define SKY130_FD_SC_HD__O32A_1_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_4_V
`define SKY130_FD_SC_LP__DFSTP_4_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_4 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_4 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_4_V
|
#include <bits/stdc++.h> using namespace std; long long int a[100005]; int main() { long long int n, b, k; cin >> k >> b >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } long long int ans = 0; if (b == 0) { for (int i = 0; i < n;) { long long int now = a[i]; long long int cnt = 0; while (i < n && a[i] == now) { i++; cnt++; } if (now == 0) { ans += (cnt * (cnt + 1) / 2); } } cout << ans << endl; return 0; } if (b == k - 1) b = 0; long long int ans2 = 0; if (b == 0) { for (int i = 0; i < n;) { long long int now = a[i]; long long int cnt = 0; while (i < n && a[i] == now) { i++; cnt++; } if (now == 0) { ans2 += (cnt * (cnt + 1) / 2); } } } map<long long int, long long int> mp; mp[0]++; for (int i = 0; i < n; i++) { if (i > 0) a[i] += a[i - 1]; long long int mod = a[i] % (k - 1); long long int need = (mod - b + k + k - 2) % (k - 1); if (mp.find(need) != mp.end()) { ans += mp[need]; } mp[mod]++; } cout << ans - ans2 << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_b2g #(
parameter DATA_WIDTH = 8) (
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout);
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
integer i;
begin
b2g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH-1; i > 0; i = i -1) begin
b2g[i-1] = b[i] ^ b[i-1];
end
end
endfunction
assign dout = b2g(din);
endmodule
|
#include <bits/stdc++.h> long long p = 1e9 + 7, x; using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> x; while (cin >> x) cout << ((((x + 4) / 4) % p) * (((x + 6) / 4) % p)) % p << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, len, ct; int a[maxn], tot[maxn], cur[maxn]; long long ans; void solve() { for (int i = 1; i <= n; i++) tot[i] = cur[i] = 0; for (int i = 1; i <= n; i++) tot[a[i]]++; int r = 1; for (int i = 1; i <= (n - 1) / 2; i++) { while (r <= (n - 1) / 2 && (cur[a[r]] + 1) * 2 <= tot[a[r]]) { cur[a[r]]++; r++; } ans += r - i + 1; if (a[i] != a[n - i + 1]) break; tot[a[i]] -= 2; cur[a[i]]--; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), tot[a[i]]++; int val = 0; for (int i = 1; i <= n; i++) if (tot[i] & 1) { if (val) { puts( 0 ); return 0; } val = i; } while (1 + len <= n && n - len >= 1 && a[1 + len] == a[n - len]) len++; if (len == n) { printf( %lld n , 1LL * n * (n + 1) / 2); return 0; } int l = n / 2, r = n / 2 + 1 + (n & 1); while (l - ct >= 1 && r + ct <= n && a[l - ct] == a[r + ct]) ct++; for (int i = 1; i <= n; i++) cur[i] = 0; for (int i = len + 1; i <= l - ct; i++) cur[a[i]]++; bool bad = false; for (int i = r + ct; i <= n - len; i++) { if (!cur[a[i]]) { bad = true; break; } cur[a[i]]--; } if (!bad) ans = 2LL * (len + 1) * (ct + 1); solve(); reverse(a + 1, a + 1 + n); solve(); ans -= len + 1; printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module gpu(
input wire clr,
input wire clka,
input wire clkb,
input wire ena,
input wire wea,
input wire [12:0] addra,
input wire [15:0] dina,
output wire [15:0] douta,
output wire [2:0] vgaRed,
output wire [2:0] vgaGreen,
output wire [2:1] vgaBlue,
output wire Hsync,
output wire Vsync
);
reg [23:0] BlinkCount;
wire cBlink;
assign cBlink = BlinkCount[23];
/* vgabase_1024x768 SyncGen*/
wire pl0_xsync, pl0_ysync, pl0_vidon;
wire [11:0] pl0_xpos, pl0_ypos;
vgabase Pipeline0(.clk(clkb), .clr(clr),
.hsync(pl0_xsync), .vsync(pl0_ysync),
.hc(pl0_xpos), .vc(pl0_ypos), .vidon(pl0_vidon)
);
/* vgamem_128x48 CharMemoryAccess */
wire [7:0] fontcolor;
wire [7:0] backcolor;
wire [6:0] char;
wire Blink;
wire pl1_xsync, pl1_ysync, pl1_vidon;
wire [11:0] pl1_xpos, pl1_ypos;
vgamem Pipeline1( .clr(clr), .clka(clka), .clkb(clkb),
.ena(ena), .wea(wea), .addra(addra), .dina(dina), .douta(douta),
.char(char), .fontcolor(fontcolor), .backcolor(backcolor), .Blink(Blink),
.xsync(pl0_xsync), .ysync(pl0_ysync),
.xpos(pl0_xpos), .ypos(pl0_ypos), .valid(pl0_vidon),
.hsync(pl1_xsync), .vsync(pl1_ysync),
.hc(pl1_xpos), .vc(pl1_ypos), .vidon(pl1_vidon)
);
/* vgachar_128x48 CharFontGen*/
vgachar Pipeline2(.clk(clkb), .clr(clr), .cBlink(cBlink),
.char(char), .fontcolor(fontcolor), .backcolor(backcolor), .Blink(Blink),
.xsync(pl1_xsync), .ysync(pl1_ysync),
.xpos(pl1_xpos), .ypos(pl1_ypos), .valid(pl1_vidon),
.hsync(Hsync), .vsync(Vsync),
.vgaRed(vgaRed), .vgaGreen(vgaGreen), .vgaBlue(vgaBlue)
);
always @(posedge clkb or posedge clr) begin
if(clr == 1)
BlinkCount <= 0;
else
BlinkCount <= BlinkCount + 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5; int m; int num[MAXN + 10]; int tree[4 * MAXN + 10]; int prop[4 * MAXN + 10]; void upd(int cn, int b, int e, int l, int r, int x, int p = 0) { if (l <= b && e <= r) { tree[cn] += x + p; prop[cn] += x + p; return; } if (r < b || l > e) { tree[cn] += p; prop[cn] += p; return; } p += prop[cn]; prop[cn] = 0; int m = (b + e) / 2; upd(2 * cn, b, m, l, r, x, p); upd(2 * cn + 1, m + 1, e, l, r, x, p); tree[cn] = min(tree[2 * cn], tree[2 * cn + 1]); } void upd(int i, int x) { upd(1, 1, m, i, m, x); } int get(int cn, int b, int e, int l, int r, int p = 0) { if (l <= b && e <= r) return tree[cn] + p; if (r < b || l > e) return 1e9; int m = (b + e) / 2; int L = get(2 * cn, b, m, l, r, p + prop[cn]); int R = get(2 * cn + 1, m + 1, e, l, r, p + prop[cn]); return min(L, R); } bool oka(int j) { if (j == 0) return 0 < get(1, 1, m, m, m); return get(1, 1, m, j, m) < get(1, 1, m, m, m); } int solve() { int lo = 0, hi = m - 1; while (hi - lo > 1) { int m = (lo + hi) / 2; if (oka(m)) lo = m; else hi = m - 1; } if (oka(hi)) return num[hi + 1]; if (oka(lo)) return num[lo + 1]; return -1; } int main() { scanf( %d , &m); for (int i = 1; i <= m; i++) { int ps, tp; scanf( %d%d , &ps, &tp); if (tp == 0) upd(ps, -1); else { int x; scanf( %d , &x); num[ps] = x; upd(ps, +1); } printf( %d n , solve()); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_TB_V
`define SKY130_FD_SC_HD__PROBE_P_TB_V
/**
* probe_p: Virtual voltage probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__probe_p.v"
module top();
// Inputs are registered
reg A;
reg VGND;
reg VNB;
reg VPB;
reg VPWR;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__probe_p dut (.A(A), .VGND(VGND), .VNB(VNB), .VPB(VPB), .VPWR(VPWR), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_TB_V
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
reg cm0_a;
reg cm0_b;
reg mut0_r1;
reg mut0_r2;
cmuller U_CM0(.z(cm0_z),
.a(cm0_a),
.b(cm0_b),
.rstn(rst_async_)
);
mutex U_MUTEX0(
.g1(mut0_g1),
.g2(mut0_g2),
.r1(mut0_r1),
.r2(mut0_r2)
);
// Dump all nets to a vcd file called tb.vcd
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
cm0_a <= 0;
cm0_b <= 0;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
// Muller C-Element
#10;
cm0_a <= 0;
cm0_b <= 0;
#10;
cm0_a <= 1;
cm0_b <= 0;
#10;
cm0_a <= 1;
cm0_b <= 1;
#10;
cm0_a <= 1;
cm0_b <= 0;
#10;
cm0_a <= 0;
cm0_b <= 0;
#10;
// Mutex
mut0_r1 <= 1'b1;
mut0_r2 <= 1'b0;
#10;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b0;
#10;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b1;
#10;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b0;
#10;
mut0_r1 <= 1'b1;
mut0_r2 <= 1'b1;
#10;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b1;
#10;
mut0_r1 <= 1'b0;
mut0_r2 <= 1'b0;
#10;
$display("-I- Done !");
$finish;
end
endmodule // tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_TB_V
`define SKY130_FD_SC_LS__HA_TB_V
/**
* ha: Half adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ha.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hdll__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hdll__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int p1, p2, p3, p4, a, b; cin >> p1 >> p2 >> p3 >> p4 >> a >> b; int m = min(min(min(p1, p2), p3), p4); cout << max(0, min(b + 1, m) - a) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> int size(T& a) { return (int)a.size(); } template <typename T> T sqr(T a) { return a * a; } int offset; int f[1000000 * 4 + 10]; int start[27]; int getmask(int l, int r) { int res = 0; for (l += offset, r += offset; l <= r; l /= 2, r /= 2) { if (l % 2 == 1) { res |= f[l++]; } if (r % 2 == 0) { res |= f[r--]; } } return res; } vector<int> pos[27]; int ans[10000]; map<int, int> num; int cnt[27][10000]; int g[10000]; int main() { string s; cin >> s; s += (char)( z + 1); offset = 1; while (offset < size(s)) offset *= 2; memset((f), (0), sizeof(f)); for (int i = offset; i < offset + size(s); ++i) { f[i] = 1 << (s[i - offset] - a ); } for (int i = offset - 1; i >= 1; --i) { f[i] = f[2 * i] | f[2 * i + 1]; } for (int i = 0; i < size(s); ++i) { pos[s[i] - a ].push_back(i); } int q; cin >> q; for (int i = 0; i < q; ++i) { string e; cin >> e; int mask = 0; for (int j = 0; j < e.length(); ++j) { mask |= 1 << (e[j] - a ); } g[i] = mask; num[mask] = i; } for (int i = 0; i < size(s) - 1; ++i) { for (int b = 0; b < 27; ++b) { if (s[i] - a == b) continue; while (start[b] < pos[b].size() && pos[b][start[b]] < i) { ++start[b]; } if (start[b] < pos[b].size() && pos[b][start[b]] >= i) { int m = getmask(i, pos[b][start[b]] - 1); if (i > 0 && (m & (1 << (s[i - 1] - a ))) != 0) continue; if (!num.count(m)) continue; cnt[b][num[m]]++; } } } for (int i = 0; i < q; ++i) { int res = 0; for (int b = 0; b < 27; ++b) if ((g[i] & (1 << b)) == 0) { res += cnt[b][num[g[i]]]; } cout << res << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353, maxn = 1e6, MAXN = 1 << 21; int jc[2222222], injc[2222222], n, a, b, s[2222222], t[2222222], l, r, pw[2222222], sz, rev[2222222], cnt; int S[2222222], T[2222222], G[2222222], w[2][2222222], cur, gg[2222222]; long long c[2222222]; int binpow(int a, int t) { int res = 1, p = a; for (int i = t; i; i >>= 1) { if (i & 1) res = (long long)res * p % mod; p = (long long)p * p % mod; } return res; } int C(int n, int k) { if (n < k) return 0; return ((long long)jc[n] * injc[k] % mod) * injc[n - k] % mod; } void Init() { jc[0] = injc[0] = 1; for (int i = 1; i <= maxn; i++) { jc[i] = (long long)jc[i - 1] * i % mod; } injc[maxn] = binpow(jc[maxn], mod - 2); for (int i = maxn - 1; i >= 0; i--) injc[i] = (long long)injc[i + 1] * (i + 1) % mod; w[0][0] = 1; cur = binpow(3, (mod - 1) / MAXN); for (int i = 1; i <= MAXN; i++) w[0][i] = (long long)w[0][i - 1] * cur % mod; w[1][0] = 1; cur = binpow(3, mod - 1 - (mod - 1) / MAXN); for (int i = 1; i <= MAXN; i++) w[1][i] = (long long)w[1][i - 1] * cur % mod; } void ntt(int d[], int flag) { for (int i = 0; i < sz; i++) c[i] = (long long)d[i]; for (int i = 0; i < sz; i++) { if (rev[i] > i) swap(c[i], c[rev[i]]); } for (int i = 2; i <= sz; i <<= 1) { int p = i >> 1, fu = MAXN / i; for (int j = 0; j < p; j++) { gg[j] = w[flag][j * fu]; } for (int j = 0; j < sz; j += i) { for (int k = j; k < j + p; k++) { long long tmp1 = c[k]; long long tmp2 = c[k + p] % mod * gg[k - j]; c[k] = tmp1 + tmp2; c[k + p] = tmp1 - tmp2; } } } for (int j = 0; j < sz; j++) c[j] %= mod; if (flag) { int wn = binpow(sz, mod - 2); for (int i = 0; i < sz; i++) { c[i] = c[i] * wn % mod; } } for (int i = 0; i < sz; i++) d[i] = c[i]; } void doit() { if (sz <= 64) { for (int i = 0; i < sz; i++) G[i] = 0; for (int i = 0; i < sz; i++) { for (int j = 0; j < sz - i; j++) { G[i + j] = ((long long)S[i] * T[j] + G[i + j]) % mod; } } for (int i = 0; i < sz; i++) S[i] = G[i]; return; } rev[0] = 0; for (int i = 1; i < sz; i++) { rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (cnt - 1)); } ntt(S, 0); ntt(T, 0); for (int i = 0; i < sz; i++) S[i] = (long long)S[i] * T[i] % mod; ntt(S, 1); } void solve(int n) { if (n == 1) { s[1] = 1; return; } if (!n) { s[0] = 1; return; } if (n & 1) { solve(n - 1); t[0] = (long long)s[0] * (n - 1) % mod; for (int i = 1; i <= n; i++) t[i] = ((long long)s[i] * (n - 1) + s[i - 1]) % mod; for (int i = 1; i <= n; i++) s[i] = t[i]; } else { solve(n >> 1); pw[0] = 1; sz = 1; cnt = 0; while (sz <= n) { sz *= 2; cnt++; } int c = (n >> 1); for (int i = 1; i <= c; i++) pw[i] = (long long)pw[i - 1] * c % mod; for (int i = 0; i < sz; i++) S[i] = T[i] = 0; for (int i = 0; i <= c; i++) S[i] = (long long)s[i] * jc[i] % mod; for (int i = 0; i <= c; i++) T[i] = (long long)pw[i] * injc[i] % mod; reverse(T, T + c + 1); doit(); for (int j = 0; j < sz; j++) T[j] = 0; for (int j = c; j <= n; j++) T[j - c] = (long long)S[j] * injc[j - c] % mod; for (int j = 0; j < sz; j++) S[j] = s[j]; doit(); for (int j = 0; j <= n; j++) s[j] = S[j]; } } int main() { cin >> n >> a >> b; Init(); n--; if (!n) { if (!(a + b - 2)) cout << C(a + b - 2, a - 1) << endl; else cout << 0 << endl; return 0; } solve(n); cout << ((long long)s[a + b - 2] * C(a + b - 2, a - 1) % mod + mod) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct segtree { int size = 1; vector<pair<int, int>> v; vector<pair<int, int>> lazy; void init(int n) { while (n > size) { size *= 2; } v.assign(size * 2, {0, -1}); lazy.assign(size * 2, {0, -1}); } void prop(int x, int lx, int rx) { if (rx - lx == 1) return; if (lazy[x] == make_pair(0, -1)) return; v[x * 2 + 1] = lazy[x]; v[x * 2 + 2] = lazy[x]; lazy[x * 2 + 1] = lazy[x]; lazy[x * 2 + 2] = lazy[x]; lazy[x] = {0, -1}; } void update(int l, int r, pair<int, int> val, int x, int lx, int rx) { prop(x, lx, rx); if (rx <= l || lx >= r) { return; } if (lx >= l && rx <= r) { v[x] = val; lazy[x] = val; return; } int m = (lx + rx) / 2; update(l, r, val, x * 2 + 1, lx, m); update(l, r, val, x * 2 + 2, m, rx); v[x] = max(v[x * 2 + 1], v[x * 2 + 2]); } void update(int l, int r, pair<int, int> val) { update(l, r + 1, val, 0, 0, size); } pair<int, int> get(int l, int r, int x, int lx, int rx) { prop(x, lx, rx); if (rx <= l || lx >= r) { return {0, -1}; } if (lx >= l && rx <= r) { return v[x]; } int m = (lx + rx) / 2; pair<int, int> m1 = get(l, r, x * 2 + 1, lx, m); pair<int, int> m2 = get(l, r, x * 2 + 2, m, rx); return max(m1, m2); } pair<int, int> get(int l, int r) { return get(l, r + 1, 0, 0, size); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; set<int> s; vector<vector<pair<int, int>>> v(n); vector<tuple<int, int, int>> actions; for (int i = 0; i < m; i++) { int j, l, r; cin >> j >> l >> r; j--; actions.push_back({j, l, r}); s.insert(l); s.insert(r); v[j].push_back(make_pair(l, r)); } auto s1 = s.begin(); auto s2 = s.begin(); if (s2 != s.end()) s2++; map<int, int> mapa; int ctr = 0; mapa[*s1] = ctr; ctr++; while (s2 != s.end()) { if ((*s1) != (*s2)) { mapa[*s2] = ctr; ctr++; } s1++; s2++; } segtree prev; prev.init(2 * m + 2); vector<int> before(n, -1); for (int i = 0; i < n; i++) { pair<int, int> mx = {0, -1}; for (auto x : v[i]) { int a = mapa[x.first]; int b = mapa[x.second]; mx = max(mx, prev.get(a, b)); } mx.first++; before[i] = mx.second; mx.second = i; for (auto x : v[i]) { int a = mapa[x.first]; int b = mapa[x.second]; prev.update(a, b, mx); } } vector<int> ok(n, false); int lastmx = prev.get(0, 2 * m + 1).second; while (lastmx >= 0) { ok[lastmx] = true; lastmx = before[lastmx]; } vector<int> res; int resnum = 0; for (int i = 0; i < n; i++) { if (!ok[i]) { res.push_back(i); resnum++; } } cout << resnum << n ; for (auto w : res) cout << w + 1 << ; }
|
//
// K580VI53 timer implementation
//
// Copyright (c) 2016 Sorgelig
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// altera message_off 10240
`default_nettype none
module k580vi53
(
// CPU bus
input reset,
input clk_sys,
input [1:0] addr,
input [7:0] din,
output [7:0] dout,
input wr,
input rd,
// Timer signals
input [2:0] clk_timer,
input [2:0] gate,
output [2:0] out,
output [2:0] sound_active
);
wire [7:0] dout0;
wire [7:0] dout1;
wire [7:0] dout2;
assign dout = dout0 & dout1 & dout2;
timer t0(reset, clk_sys, clk_timer[0], din, dout0, wr && (addr == 3) && (din[7:6] == 0), wr && (addr == 0), rd && (addr == 0), gate[0], out[0], sound_active[0]);
timer t1(reset, clk_sys, clk_timer[1], din, dout1, wr && (addr == 3) && (din[7:6] == 1), wr && (addr == 1), rd && (addr == 1), gate[1], out[1], sound_active[1]);
timer t2(reset, clk_sys, clk_timer[2], din, dout2, wr && (addr == 3) && (din[7:6] == 2), wr && (addr == 2), rd && (addr == 2), gate[2], out[2], sound_active[2]);
endmodule
module timer
(
input reset,
input clk_sys,
input clk_timer,
input [7:0] din,
output [7:0] dout,
input wr_cw,
input wr,
input rd,
input gate,
output reg out,
output reg sound_active
);
reg [7:0] q;
reg [7:0] cw;
reg [15:0] counter;
reg [15:0] ld_count;
reg [7:0] load;
reg pause;
reg stop1;
assign dout = q;
always @(posedge clk_sys) begin
reg [15:0] l_counter;
reg msbw, msbr; // according to Siemens doc, read and write have indepenent msb flag.
reg latched;
reg old_wr_cw, old_wr, old_rd;
old_wr_cw <= wr_cw;
old_wr <= wr;
old_rd <= rd;
if(!old_wr_cw && wr_cw) begin
msbw <=0;
msbr <=0;
if(!din[5:4]) begin
if(!latched) begin
latched <=1;
l_counter <= counter;
end
end else begin
cw <= din;
latched <=0;
stop1 <=1;
pause<=1;
end
end
if(!old_wr && wr) begin
case(cw[5:4])
1: begin // high speed mode
ld_count[7:0] <= check(din);
ld_count[15:8] <= 0;
stop1 <=0;
load <=load + 1'd1;
pause <=0;
end
2: begin // low precision mode
ld_count[7:0] <= 0;
ld_count[15:8] <= check(din);
stop1 <=0;
load <=load + 1'd1;
pause <=0;
end
default: begin // full mode
if(msbw) ld_count[15:8] <= check(din);
else ld_count[7:0] <= check(din);
msbw <= ~msbw;
pause <= ~msbw;
if(msbw) begin
stop1 <=0;
load <=load + 1'd1;
end
end
endcase
end
if(!old_rd && rd) begin
casex({latched, msbr, cw[5:4]})
4'b0X01: q <=counter[7:0];
4'b0X10: q <=counter[15:8];
4'b0011: q <=counter[7:0];
4'b0111: q <=counter[15:8];
4'b1X01: begin q <=l_counter[7:0]; latched <=0; end
4'b1X10: begin q <=l_counter[15:8]; latched <=0; end
4'b1011: q <=l_counter[7:0];
4'b1111: begin q <=l_counter[15:8]; latched <=0; end
endcase
msbr <= ~msbr;
end
if(!rd || reset) q <= 255;
if(reset) begin
stop1 <=1;
ld_count <=0;
cw <= 0;
end
end
function [15:0] minus1;
input [15:0] value;
begin
if(!cw[0]) minus1 = value-1'd1;
else begin
minus1 = value;
if(!minus1[3:0]) begin
minus1[3:0] = 9;
if(!minus1[7:4]) begin
minus1[7:4] = 9;
if(!minus1[11:8]) begin
minus1[11:8] = 9;
if(!minus1[15:12]) begin
minus1[15:12] = 9;
end else minus1[15:12] = minus1[15:12]-1'd1;
end else minus1[11:8] = minus1[11:8]-1'd1;
end else minus1[7:4] = minus1[7:4]-1'd1;
end else minus1[3:0] = minus1[3:0]-1'd1;
end
end
endfunction
function [7:0] check;
input [7:0] value;
begin
if(!cw[0]) check = value;
else begin
check[3:0] = (value[3:0]>9) ? 4'd9 : value[3:0];
check[7:4] = (value[7:4]>9) ? 4'd9 : value[7:4];
end;
end
endfunction
reg stop2;
wire stop = stop1 | stop2;
//
// With bugs implemented:
//
// M0,M1,M4,M5 - counter doesn't stop at the end but wrap around instead.
//
// M1,M5 - setting of Control Word doesn't reset counter.
// Counter continue to count old value after ccounter register is set.
//
always @(posedge clk_sys) begin
reg [7:0] old_load;
reg old_gate;
reg start, count_en, m3state;
reg [7:0] stop_delay;
reg old_clk;
// cannot treat it as clock enable because timer clock
// can be fed from output of other timer
old_clk <= clk_timer;
if(old_clk & ~clk_timer) begin
stop2 <= stop1;
old_load <= load;
old_gate <= gate;
start <= stop;
// Assume sound is generated by mode 3 and mode 0(DAC emulation).
sound_active <= (!cw[3:1] || (cw[2:1] == 2'b11)) && !stop;
casex(cw[3:1])
3'b000: if(stop) begin out <=0; count_en <=0; end
else begin
if(start || (old_load != load)) begin
counter <= ld_count;
out <=0;
count_en <=1;
end else if(!pause && gate) begin
counter <= minus1(counter);
if(counter == 1) begin
out <=1;
count_en <=0;
end
end
end
3'b001: if(stop) begin out <=1; count_en <=0; end
else begin
if(!old_gate & gate) begin
counter <= ld_count;
out <=0;
count_en <=1;
end else begin
counter <= minus1(counter);
if((counter == 1) && count_en) begin
out <=1;
count_en <=0;
end
end
end
3'bX10: if(stop || !gate) out <=1;
else begin
if(start || (!old_gate & gate) || (counter <= 1)) begin
counter <=ld_count;
out <=1;
end else begin
counter <= minus1(counter);
if(counter == 2) out <=0;
end
end
3'bX11: if(stop || !gate) begin out <=1; m3state <=1; end
else begin
if(start || (!old_gate & gate) || (counter <= 2)) begin
counter <=ld_count;
out <= m3state;
m3state <= ~m3state;
end else begin
counter <= !counter[0] ? minus1(minus1(counter)) : out ? minus1(counter) : minus1(minus1(minus1(counter)));
end
end
3'b100: if(stop) begin out <=1; count_en <=0; end
else begin
out <=1;
if(start) begin
counter <=ld_count;
count_en <=1;
end else if(gate) begin
counter <= minus1(counter);
if((counter == 1) && count_en) begin
out <=0;
count_en <=0;
end
end
end
3'b101: if(stop) begin out <=1; count_en <=0; end
else begin
out <=1;
if(!old_gate & gate) begin
counter <=ld_count;
out <=1;
count_en <=1;
end else begin
counter <= minus1(counter);
if((counter == 1) && count_en) begin
out <=0;
count_en <=0;
end
end
end
endcase
end
end
endmodule
|
`define bsg_mem_3r1w_sync_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem0 \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r0_v_i ) \
,.r_addr_i( r0_addr_i ) \
,.r_data_o( r0_data_o ) \
); \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem1 \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r1_v_i ) \
,.r_addr_i( r1_addr_i ) \
,.r_data_o( r1_data_o ) \
); \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem2 \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r2_v_i ) \
,.r_addr_i( r2_addr_i ) \
,.r_data_o( r2_data_o ) \
); \
end
module bsg_mem_3r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
// NOTE: unused
, parameter substitute_3r1w_p = 0
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [width_p-1:0] r2_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_3r1w_sync_macro(32,66) else
// no hardened version found
begin : notmacro
initial if (substitute_3r1w_p != 0) $warning("substitute_3r1w_p will have no effect");
bsg_mem_3r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p), .harden_p(harden_p))
synth
(.*);
end // block: notmacro
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
assert (~(r2_addr_i == w_addr_i && w_v_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w_sync)
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; char s[200000], c[200000]; cin >> s; int x = k / 2, r = k / 2; if (k == n) { cout << s; return 0; } for (int i = 0, j = 0; i < n; ++i) { if (s[i] == ( ) { if (x > 0) c[j++] = ( ; --x; } else { if (r > 0) c[j++] = ) ; --r; } } cout << c << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: cpci_clock_checker.v
// Project: UNET (NF2 User Network FPGA)
// Description:
// Checks that the core clock and PCI clock are
// operating at about the right frequencies.
// We have seen funny clock behavior on Rev 1 NF2, so this
// is an attempt to investigate further.
//
// Limitation: it only checks relative frequencies, not
// absolute.
//
///////////////////////////////////////////////////////////////////////////////
// synthesis translate_off
/************************************
* This is the testbench - the actual RTL is further down.
* Uncomment this to simulate just this file.
module tb ();
reg reset, n_clk, p_clk;
cpci_clock_checker cc (
.error (error),
.clk_chk_p_max ('d3333333),
.clk_chk_n_exp ('d6250000),
.reset (reset),
.shift_amount(4'd3),
.p_clk (p_clk),
.n_clk (n_clk)
);
always #15 p_clk = ~p_clk;
always #8 n_clk = ~n_clk;
initial begin
n_clk = 0;
p_clk = 0;
reset =1;
#200 reset = 0;
// $monitor("st: %d ", cc.state);
wait (cc.state == 3); #100;
$display("%t Error is %d. n_count is %d p_count is %d",
$time, error, cc.n_count, cc.p_count);
if (error == 0) $display("(That was good - error should be 0");
else begin $display ("BAD - error should be 0"); $finish; end
wait (cc.state == 0);
#100000 begin end
force n_clk = 0;
$display($time,"Stopping n_clk");
# release n_clk;
wait (cc.state == 3); #100 begin end
$display("%t Error is %d. n_count is %d p_count is %d",
$time, error, cc.n_count, cc.p_count);
if (error == 1) $display("(That was good - error should be 1");
else begin $display ("BAD - error should be 1"); $finish; end
#100 $finish;
end
// always @(posedge p_clk)
// if (($time > 1000) && (cc.p_count[19:0] == 'h0)) $display($time, "p_cnt: %d", cc.p_count);
endmodule
**********************************************************/
// synthesis translate_on
module cpci_clock_checker
(
output error,
output reg [31:0] n_clk_count,
input [31:0] clk_chk_p_max, // MAX value for PCI counter
input [31:0] clk_chk_n_exp, // Expected value of n_clk counter.
input [3:0] shift_amount, // see below
input reset, // pci clock reset
input p_clk, //nominally 33MHz
input n_clk //nominally 62.5 MHz
);
// shift_amount indicates how much to left shift (increase)
// the allowable deviation. Range is 0-15. So a bigger value
// on shift_amount means that we can have more deviation without
// signaling an error.
// create the min and max values. Use flops to make timing easier.
reg [31:0] min_exp_count;
reg [31:0] max_exp_count;
always @(posedge p_clk) begin
min_exp_count <= clk_chk_n_exp - (1<<shift_amount);
max_exp_count <= clk_chk_n_exp + (1<<shift_amount);
end
reg [31:0] p_count;
reg [31:0] n_count;
parameter START = 0, COUNT = 1, WAIT1 = 2, CHECK = 3;
reg [1:0] state, state_nxt;
reg go, go_nxt, stop, stop_nxt;
reg saw_error;
always @* begin
//defaults
state_nxt = state;
saw_error = 0;
go_nxt = 0;
stop_nxt = 0;
case (state)
START: begin
go_nxt = 1;
state_nxt = COUNT;
end
COUNT: begin //wait for count to end
if (p_count == clk_chk_p_max) begin
stop_nxt = 1;
state_nxt = WAIT1;
end
end
WAIT1: begin // Just wait a bit for asynchrony to resolve.
if (p_count == (clk_chk_p_max + 2))
state_nxt = CHECK;
end
CHECK: begin
if ((n_count < min_exp_count) ||
(n_count > max_exp_count))
saw_error = 1;
state_nxt = START;
end
default: state_nxt = START;
endcase
end
//=============================================================
//
// drive error signal for a while whenever we see saw_error - this
// drives the LED so needs to be on for a while.
reg [15:0] error_cnt;
always @(posedge p_clk)
if (reset)
error_cnt <= 0;
else
if (saw_error) error_cnt <= 10000;
else if (error_cnt > 0)
error_cnt <= error_cnt - 1;
assign error = (error_cnt != 0);
always @(posedge p_clk) begin
go <= go_nxt;
stop <= stop_nxt;
state <= reset ? START : state_nxt;
end
always @(posedge p_clk)
if (reset || go) p_count <= 0;
else p_count <= p_count + 1;
//=================================================================
// N clock (faster than PCI clock)
reg go_n, reset_n, stop_n, run_n;
always @(posedge n_clk) begin
go_n <= go;
reset_n <= reset;
stop_n <= stop;
end
always @(posedge n_clk)
if (reset_n || stop_n) run_n <= 0;
else if (go_n) run_n <= 1;
always @(posedge n_clk)
if (reset_n || go_n) n_count <= 0;
else if (run_n) n_count <= n_count + 1;
// N-clk_count preserves the last value of n_count
always @(posedge n_clk)
if (reset_n ) n_clk_count <= 'h0;
else if (stop_n) n_clk_count <= n_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<bool> hero(n); vector<long long> v(n); vector<int> pos_num(n); for (int i = 0; i < m; i++) { int s, h; cin >> s >> h; hero[--s] = 1; pos_num[s] = i; v[s] = h; } for (int i = 0; i < n; i++) { int x; cin >> x; if (!hero[i]) v[i] = x; } for (int cell = 0; cell < n; cell++) { vector<int> order; vector<long long> v_; vector<bool> hero_; for (bool x : hero) hero_.push_back(x); for (long long x : v) v_.push_back(x); for (int dum = 0; dum < m; dum++) { vector<bool> can(n); for (int i = 0; i < n; i++) if (hero_[i]) { int inc = i <= cell ? 1 : -1; long long sum = 0; int idx = i; bool ok = 1; while (1) { if (idx == i || !hero_[idx]) sum += v_[idx]; if (sum < 0) ok = 0; if (idx == cell) break; idx += inc; } if (ok) can[i] = 1; } int idx = -1; for (int i = 0; i < cell + 1; i++) { if (can[i]) { idx = i; break; } } for (int i = n - 1; i >= cell; i--) if (can[i]) { idx = i; break; } if (idx == -1) break; int inc = idx <= cell ? 1 : -1; order.push_back(pos_num[idx]); hero_[idx] = 0; while (1) { v_[idx] = 0; if (idx == cell) break; idx += inc; } } if (order.size() == m) { cout << cell + 1 << n ; for (int i = 0; i < m; i++) { if (i) cout << ; cout << order[i] + 1; } cout << n ; return 0; } } cout << -1 << n ; }
|
module primogen_bench;
reg clk = 0;
wire rst;
reg go = 0;
reg [31:0] clk_count = 0;
reg [31:0] res_count = 0;
reg overflow = 0;
wire [15:0] gen_res;
wire gen_ready;
wire gen_error;
por pos_inst(
.clk(clk),
.rst(rst));
primogen gen(
.clk(clk),
.go(go),
.rst(rst),
.res(gen_res),
.ready(gen_ready),
.error(gen_error));
always #1 clk = !clk;
always @(posedge clk)
clk_count = clk_count + 1;
initial begin
wait(!rst);
while (clk_count < 20000) begin
// Ask for next prime
@(negedge clk) go = 1;
@(posedge clk) @(negedge clk) go = 0;
// Wait until prime is computed
@(posedge gen_ready);
if (gen_error)
overflow = 1;
if (!overflow)
res_count = res_count + 1;
end
$display("primogen_bench SUCCEEDED: Computed %0d primes in %0d cycles, last prime is %d, %soverflow", res_count, clk_count, gen_res, overflow ? "" : "no ");
$finish;
end
// initial
// $monitor("%t: go = %b, ready = %b, error = %b, res = %h", $time, go, gen_ready, gen_error, gen_res);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A21BOI_FUNCTIONAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_FUNCTIONAL_V
|
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