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// Trying to simulate how an automatic naive (non-pipelined) translation
// of _IDIVMOD could work.
module idivmodhw(input clk,
input reset,
input rq,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] div_out,
output [31:0] div_mod,
output ack);
reg [31:0] div_mod;
reg [31:0] div_out;
reg ack;
reg signed [31:0] ndividend;
reg signed [31:0] ndivisor;
reg signed [31:0] nq;
reg signed [31:0] nbit;
reg signed [15:0] np;
reg [3:0] state;
parameter S_IDLE = 0;
parameter S_LOOP0 = 1;
parameter S_POSTLOOP0 = 2;
parameter S_LOOP1 = 3;
parameter S_POSTLOOP1 = 4;
always @(posedge clk)
if(!reset) begin
ack <= 0;
div_out <= 0;
div_mod <= 0;
ndividend <= 0;
ndivisor <= 0;
nbit <= 0;
state <= S_IDLE;
nq <= 0;
np <= 0;
end else begin // if (!reset)
case(state)
S_IDLE: if (rq) begin
nq <= 0;
np <= 32'hffffffff;
ndividend <= dividend;
ndivisor <= divisor;
nbit <= 1;
state <= S_LOOP0;
ack <= 0;
end
S_LOOP0: if (ndivisor < ndividend) begin
ndivisor <= ndivisor << 1;
np <= np + 1;
nbit <= nbit << 1;
end else state <= S_POSTLOOP0;
S_POSTLOOP0: begin
nbit <= nbit >> 1;
ndivisor <= ndivisor >> 1;
state <= S_LOOP1;
end
S_LOOP1: if (np >= 0) begin
if (ndividend >= ndivisor) begin
nq <= nq + nbit;
ndividend <= ndividend - ndivisor;
end
ndivisor <= ndivisor >> 1;
np <= np - 1;
nbit <= nbit >> 1;
end else state <= S_POSTLOOP1;
S_POSTLOOP1: begin
if (dividend == divisor) begin
div_out <= nq + 1;
div_mod <= 0;
end else begin
div_out <= nq;
div_mod <= ndividend;
end
ack <= 1;
state <= S_IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int func(vector<vector<long long int>> &d, vector<int> &v, int i, int k) { if (d[k][i - 1] != 0) return d[k][i - 1]; if (k && (i + v[i - 1] <= d[0].size())) { d[k][i - 1] = -1; long long int y = func(d, v, i + v[i - 1], 1 - k); if (y != -1) y += v[i - 1]; return d[k][i - 1] = y; } else if (k) return d[k][i - 1] = v[i - 1]; else if (i - v[i - 1] > 0) { d[k][i - 1] = -1; long long int y = func(d, v, i - v[i - 1], 1 - k); if (y != -1) y += v[i - 1]; return d[k][i - 1] = y; } else return d[k][i - 1] = v[i - 1]; } int main() { long long int n, x, y, k = 1; cin >> n; vector<int> v; v.push_back(0); for (int i = 0; i < n - 1; i++) { cin >> x; v.push_back(x); } vector<vector<long long int>> d(2, vector<long long int>(n, 0)); for (int i = 1; i < n; i++) { y = 0; v[0] = i; d[1][0] = d[0][0] = -1; y = func(d, v, v[0] + 1, 0); if (y != -1) y += i; cout << y << endl; } return 0; }
|
// ICNBC functions
// Copyright (c) 2014 Dominic Spill, Tariq Bashir
// This file is part of Unambiguous Encapsulation
// License: GPL v2
//
`timescale 1ns/1ps
module icnbc
#(parameter N = 3,
parameter depth=1024,
parameter width=N, //same as N
parameter addr_sz=$clog2(depth)
)
(input clk,
input rst, //positive reset
input [N-1:0] n,
input [N/2-1:0] min_ld,
input start,
output reg [3:0] codes [N-1:0]
);
localparam [2:0]
IDLE = 0,
CALC_LD = 1,
CLOCK_CALC_LD = 2,
FIND_CODE = 3,
RD_MEM = 4,
OUTPUT_CODES = 5,
CLOCK_OUTPUT_CODES = 6,
DONE = 7;
reg [2:0] state, nxt_state;
reg [3:0] counterl[N-1:0], nxt_counterl[N-1:0], counterh[N-1:0], nxt_counterh[N-1:0];
reg [addr_sz-1:0] codelength, nxt_codelength;
reg [addr_sz-1:0] count, nxt_count;
//sequential block
always @(posedge clk)
if(rst)
begin
state <= #1 IDLE;
counterl <= #1 0;
codelength <= #1 0;
count <= #1 0;
counterh <= #1 0;
end
else
begin
state <= #1 nxt_state;
counterl <= #1 nxt_counterl;
counterh <= #1 nxt_counterh;
codelength <= #1 nxt_codelength;
count <= #1 nxt_count;
end
reg [3:0] summation [N-1:0];
reg [3:0] candidate [N-1:0];
reg wr_en, rd_en;
reg [width-1:0] d_in;
reg [addr_sz-1:0] wr_addr;
reg [width-1:0] d_out;
reg [addr_sz-1:0] rd_addr, r_addr;
reg [width-1:0] code_array[0:depth-1];
//memory
always @(posedge clk)
begin
if (wr_en)
begin
code_array[wr_addr] <= #1 d_in;
end
else if (rd_en)
begin
d_out <= #1 code_array[rd_addr];
end
end // always @ (posedge clk)
//Finite STATE MACHINE
always@*
begin
//defaults
nxt_state = state;
nxt_counterl = counterl;
nxt_counterh = counterh;
nxt_count = count;
nxt_codelength = codelength;
case(state)
IDLE:
begin
if(start)
begin
wr_addr = 0;
wr_en = 1;
d_in = 0;
nxt_codelength = 1;
nxt_state = CALC_LD;
end
end
CALC_LD:
begin
wr_en = 0;
if( (counterh == 1 ) || (codelength == depth -1) )
nxt_state = OUTPUT_CODES;
else
begin
if(counterl == 2**N-1)
nxt_counterh = counterh + 1;
summation = sum(counterl, counterh); //function call
if( summation >= min_ld )
begin
//LD[counterl] = counterl;
candidate = counterl;
nxt_counterl = counterl + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_counterl = counterl + 1;
nxt_state = CLOCK_CALC_LD;
end
end // else: !if( (counterh == 1 ) || (codelength == depth -1) )
end // case: CALC_LD
CLOCK_CALC_LD:
begin
nxt_state = CALC_LD;
end
FIND_CODE:
begin
if(count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_state = RD_MEM;
end
else if(count == codelength)
begin
wr_en = 1;
d_in = candidate;
wr_addr = codelength;
nxt_codelength = codelength + 1;
nxt_count = 0;
nxt_state = CALC_LD;
end
end //FIND_CODE
RD_MEM:
begin
rd_en = 0;
summation = sum(d_out ^ candidate);
if (summation >= min_ld)
begin
nxt_count = count + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_count = 0;
nxt_state = CALC_LD;
end
end
OUTPUT_CODES:
begin
if( count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_count = count + 1;
nxt_state = CLOCK_OUTPUT_CODES;
end
else
nxt_state = DONE;
end // case: OUTPUT_CODE
CLOCK_OUTPUT_CODES:
begin
rd_en = 0;
codes = d_out;
nxt_state = OUTPUT_CODES;
end
DONE:
begin
$display($time,": Done \n");
$finish;
end
endcase // case (state)
end // always@ *
function [N-1:0] sum(
input [3:0] input_vector_a [N-1:0],
input [3:0] input_vector_b [N-1:0]
);
integer k;
reg [N-1:0] temp;
begin
temp = 0;
for(k=0; k < N; k=k+1)
begin
temp = temp + input_vector[k][3:0];
end
sum = temp;
end
endfunction // sum
endmodule // lcbbc
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long input() { long long x = 0, f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= ch == - , ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return f ? -x : x; } const int N = 107; string s[N]; map<string, int> p; int vis[N]; string res; int main() { int n = input(), m = input(); for (int i = 1; i <= n; i++) { cin >> s[i]; if (p[s[i]]) res += s[i], vis[i] = vis[p[s[i]]] = 1; else reverse(s[i].begin(), s[i].end()), p[s[i]] = i; } string ser = res; reverse(ser.begin(), ser.end()); for (int i = 1; i <= n; i++) { if (vis[i]) continue; int flag = 1; for (int j = 0; j < m / 2; j++) { if (s[i][j] != s[i][m - j - 1]) { flag = 0; break; } } if (flag == 1) { res += s[i]; break; } } res += ser; cout << res.length() << endl; cout << res << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x * f; } long long n, m, a[N], op, x, y, z; struct SegmentTree { long long l, r, sum, maxn; } tree[N << 2]; void pushup(int k) { tree[k].sum = tree[k << 1].sum + tree[k << 1 | 1].sum; tree[k].maxn = max(tree[k << 1].maxn, tree[k << 1 | 1].maxn); } void build(int k, int l, int r) { tree[k].l = l, tree[k].r = r; if (l == r) { tree[k].sum = tree[k].maxn = a[l]; return; } int mid = (l + r) / 2; build(k << 1, l, mid), build(k << 1 | 1, mid + 1, r); pushup(k); } void changemod(int k, int ql, int qr, long long mod) { if (tree[k].maxn < mod) return; if (ql <= tree[k].l && tree[k].r <= qr && tree[k].l == tree[k].r) { tree[k].sum %= mod, tree[k].maxn %= mod; return; } int mid = (tree[k].l + tree[k].r) / 2; if (ql <= mid) changemod(k << 1, ql, qr, mod); if (mid < qr) changemod(k << 1 | 1, ql, qr, mod); pushup(k); } void modify(int k, int q, long long v) { if (tree[k].l > q || q > tree[k].r) return; if (tree[k].l == tree[k].r) { tree[k].sum = tree[k].maxn = v; return; } int mid = (tree[k].l + tree[k].r) / 2; if (q <= mid) modify(k << 1, q, v); else modify(k << 1 | 1, q, v); pushup(k); } long long query(int k, int ql, int qr) { long long res = 0; if (ql <= tree[k].l && tree[k].r <= qr) return tree[k].sum; int mid = (tree[k].l + tree[k].r) / 2; if (ql <= mid) res += query(k << 1, ql, qr); if (mid < qr) res += query(k << 1 | 1, ql, qr); return res; } int main() { n = read(), m = read(); for (int i = 1; i <= n; i++) a[i] = read(); build(1, 1, n); while (m--) { op = read(); if (op == 1) { x = read(), y = read(); printf( %lld n , query(1, x, y)); } if (op == 2) { x = read(), y = read(), z = read(); changemod(1, x, y, z); } if (op == 3) { x = read(), y = read(); modify(1, x, y); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &f) { f = 0; _T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { fu = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } int main() { for (int i = 1; i <= 35; i++) printf( l ); for (int i = 1; i <= 36; i++) printf( dsut0r ); printf( luu ); for (int i = 1; i <= 35; i++) printf( l ); for (int i = 1; i <= 36; i++) printf( usdt0r ); for (int i = 1; i <= 36; i++) printf( le ); printf( ddd ); for (int i = 1; i <= 35; i++) printf( 0r ); printf( 0uu ); for (int i = 1; i <= 33; i++) { printf( r10ltldr01lt0utd10ut ); printf( uur01ltlldr10ltr10lt0utd10ut ); printf( lrr01ltl10rtl1rt ); printf( rrelelu10dtu10dtddlr10ltu10dtu ); printf( r10ltldr01lt0utd10ut ); printf( uur01ltlldr10ltr10lt0utd10ut ); printf( lrr01ltl10rtl1rt ); printf( l10rtd10utl10rtd10ut ); printf( uereuerererelueueledeleue ); printf( lddd10utuuur10ltd10utd10utl0rt ); printf( r10ltl01rtl1rt ); printf( rdu10dt0ut ); printf( r10ltl01rtl1rt ); printf( ru0utd10ut ); printf( r10ltl01rtl1rt ); printf( reueuerededeldeleuuu ); } printf( ddddr ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e6, N2 = 5e3, delta = 46639, mod = 1e9 + 7, oo = 1e16; const long double PI = 3.141592653589793; int main() { long long int n, cnt1 = 1, cnt2 = 1, mx = 0; string s; cin >> n >> s; for (long long int i = 0; i < n; i++) { for (long long int j = i; j < n; j++) { string t = s; long long int cnt = 0, trn = 0, ans = 0; swap(t[i], t[j]); for (long long int k = 0; k < n; k++) { if (t[k] == ( ) cnt++; else { if (cnt <= 0) trn++; else cnt--; } } for (long long int k = n - 1; k >= 0; k--) { if (cnt == 0 && trn == 0) ans++; if (t[k] == ( ) cnt--, trn--; else cnt++, trn++; } mx = max(mx, ans); if (mx == ans) cnt1 = i + 1, cnt2 = j + 1; } } cout << mx << n << cnt1 << << cnt2; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:17 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb565_to_rgb888_0_0 -prefix
// system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_1_0_stub.v
// Design : system_rgb565_to_rgb888_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="rgb_565[15:0],rgb_888[23:0]" */;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_BLACKBOX_V
`define SKY130_FD_SC_LS__FAHCIN_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc1_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc1_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug749
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
genvar g;
for (g=1; g<3; ++g) begin : gblk
sub2 #(.IN(g)) u ();
//sub #(.IN(g)) u2 ();
end
sub1 #(.IN(0)) u ();
always @ (posedge clk) begin
if (t.u.IN != 0) $stop;
if (t.u.FLAVOR != 1) $stop;
//if (t.u2.IN != 0) $stop; // This should be not found
if (t.gblk[1].u.IN != 1) $stop;
if (t.gblk[2].u.IN != 2) $stop;
if (t.gblk[1].u.FLAVOR != 2) $stop;
if (t.gblk[2].u.FLAVOR != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub1 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 1;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
module sub2 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 2;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
|
module GrayToBinary_tb ();
//////////////////////////////////////////////////////////////////////////////
// Module Parameters & Signals
//////////////////////////////////////////////////////////////////////////////
parameter WIDTH = 32;
// Inputs
reg clk; ///< System clock
reg rst; ///< System reset, active high & synchronous
reg inStrobe; ///< Data input strobe
reg [WIDTH-1:0] dataIn; ///< Gray-coded data
// Outputs
wire outStrobe; ///< Data output strobe
wire [WIDTH-1:0] dataOut; ///< Binary data
//////////////////////////////////////////////////////////////////////////////
// Testbench Parameters & Signals
//////////////////////////////////////////////////////////////////////////////
reg [WIDTH-1:0] gray;
reg [WIDTH-1:0] binaryActual;
reg [WIDTH-1:0] binaryTest;
reg pass;
integer numBits; // Number of bits in input word. May be different from WIDTH
integer i;
integer seed = 1245;
//////////////////////////////////////////////////////////////////////////////
// Functions & Tasks
//////////////////////////////////////////////////////////////////////////////
function [WIDTH-1:0] GrayEncode (
input [WIDTH-1:0] binary
);
begin
GrayEncode = binary ^ (binary >> 1);
end
endfunction
task TestGrayCode (
input [WIDTH-1:0] grayIn,
output [WIDTH-1:0] binaryOut
);
begin
@(posedge clk)
inStrobe = 1'b1;
dataIn = grayIn;
@(posedge clk)
inStrobe = 1'b0;
wait(outStrobe)
binaryOut = dataOut;
end
endtask
//////////////////////////////////////////////////////////////////////////////
// Main Code
//////////////////////////////////////////////////////////////////////////////
always #1 clk = ~clk;
initial begin
clk = 1'b0;
rst = 1'b1;
inStrobe = 1'b0;
dataIn = 'd0;
pass = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
// Test with random vector set
for (i=0; i<2**10; i=i+1) begin
binaryActual = $random();
numBits = $dist_uniform(seed, 3, WIDTH);
// Zero out unused bits
binaryActual = binaryActual >> (WIDTH-numBits);
gray = GrayEncode(binaryActual);
// Clear out unused bits
gray = gray << (WIDTH-numBits);
gray = gray >> (WIDTH-numBits);
TestGrayCode(gray, binaryTest);
if (binaryTest != binaryActual) begin
$display("FAIL: Actual = %08h, UUT = %08h", binaryActual, binaryTest);
pass = 1'b0;
end
end
if (pass) begin
$display("PASS");
end
else begin
$display("FAIL");
end
$stop();
end
//////////////////////////////////////////////////////////////////////////////
// Unit Under Test
//////////////////////////////////////////////////////////////////////////////
GrayToBinary #(
.WIDTH(WIDTH) ///< Data width
)
uut (
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< System reset, active high & synchronous
.inStrobe(inStrobe), ///< Data input strobe
.dataIn(dataIn), ///< [WIDTH-1:0] Gray-coded data
// Outputs
.outStrobe(outStrobe), ///< Data output strobe
.dataOut(dataOut) ///< [WIDTH-1:0] Binary data
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_TB_V
`define SKY130_FD_SC_HDLL__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hdll__sdfrtn dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_TB_V
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Low-latency RAM-based FIFO. Uses a low-latency register-based FIFO to
// mask the latency of the RAM-based FIFO.
//
// This FIFO uses additional area beyond the FIFO capacity and
// counters in order to compensate for the latency in a normal RAM FIFO.
//
//===----------------------------------------------------------------------===//
module acl_ll_ram_fifo
#(
parameter integer DATA_WIDTH = 32, // >0
parameter integer DEPTH = 32 // >3
)
(
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_out,
output logic empty,
output logic full
);
localparam SEL_RAM = 0;
localparam SEL_LL = 1;
// Three FIFOs:
// 1. data - RAM FIFO (normal latency)
// 2. data - LL REG FIFO
// 3. selector - LL REG FIFO
//
// Selector determines which of the two data FIFOs to select the current
// output from.
//
// TODO Implementation note:
// It's probably possible to use a more compact storage mechanism than
// a FIFO for the selector because the sequence of selector values
// should be highly compressible (e.g. long sequences of SEL_RAM). The
// selector FIFO can probably be replaced with a small number of counters.
// A future enhancement.
logic [DATA_WIDTH-1:0] ram_data_in, ram_data_out;
logic ram_valid_in, ram_valid_out, ram_stall_in, ram_stall_out;
logic [DATA_WIDTH-1:0] ll_data_in, ll_data_out;
logic ll_valid_in, ll_valid_out, ll_stall_in, ll_stall_out;
logic sel_data_in, sel_data_out;
logic sel_valid_in, sel_valid_out, sel_stall_in, sel_stall_out;
// Top-level outputs.
assign data_out = sel_data_out == SEL_LL ? ll_data_out : ram_data_out;
assign valid_out = sel_valid_out; // the required ll_valid_out/ram_valid_out must also be asserted
assign stall_out = sel_stall_out;
// RAM FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH - 3),
.IMPL("ram")
)
ram_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ram_data_in),
.data_out(ram_data_out),
.valid_in(ram_valid_in),
.valid_out(ram_valid_out),
.stall_in(ram_stall_in),
.stall_out(ram_stall_out)
);
assign ram_data_in = data_in;
assign ram_valid_in = valid_in & ll_stall_out; // only write to RAM FIFO if LL FIFO is stalled
assign ram_stall_in = (sel_data_out != SEL_RAM) | stall_in;
// Low-latency FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(3),
.IMPL("ll_reg")
)
ll_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ll_data_in),
.data_out(ll_data_out),
.valid_in(ll_valid_in),
.valid_out(ll_valid_out),
.stall_in(ll_stall_in),
.stall_out(ll_stall_out)
);
assign ll_data_in = data_in;
assign ll_valid_in = valid_in & ~ll_stall_out; // write to LL FIFO if it is not stalled
assign ll_stall_in = (sel_data_out != SEL_LL) | stall_in;
// Selector FIFO.
acl_data_fifo #(
.DATA_WIDTH(1),
.DEPTH(DEPTH),
.IMPL("ll_reg")
)
sel_fifo (
.clock(clock),
.resetn(resetn),
.data_in(sel_data_in),
.data_out(sel_data_out),
.valid_in(sel_valid_in),
.valid_out(sel_valid_out),
.stall_in(sel_stall_in),
.stall_out(sel_stall_out),
.empty(empty),
.full(full)
);
assign sel_data_in = ll_valid_in ? SEL_LL : SEL_RAM;
assign sel_valid_in = valid_in;
assign sel_stall_in = stall_in;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input [8:0] dac_address_ext,
input play,
input reset,
input palmode,
output sdout,
output mclk_out,
output lrck_out,
output sclk_out,
output DAC_STATUS
);
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
`ifdef MK2
`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`endif
`ifdef MK3
dac_buf snes_dac_buf (
.clock(clkin),
.wren(~we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [10 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(dac_address), // Bus [8 : 0]
.q(dac_data)); // Bus [31 : 0]
`endif
reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
wire mclk = cnt[2]; // mclk = clk/8
wire lrck = cnt[8]; // lrck = mclk/64
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] mclk_sreg;
reg [2:0] lrck_sreg;
reg [1:0] sclk_sreg;
assign mclk_out = ~mclk_sreg[2];
assign lrck_out = lrck_sreg[2];
assign sclk_out = sclk_sreg[1];
wire lrck_rising = ({lrck_sreg[0],lrck} == 2'b01);
wire lrck_falling = ({lrck_sreg[0],lrck} == 2'b10);
wire sclk_rising = ({sclk_sreg[0],sclk} == 2'b01);
wire sclk_falling = ({sclk_sreg[0],sclk} == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b00;
sclk_sreg = 2'b00;
mclk_sreg = 2'b00;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 1232 = 44100 * 16
21281370 / 709379 * 23520 = 44100 * 16
*/
reg [19:0] phaseacc = 0;
wire [14:0] phasemul = (palmode ? 23520 : 1232);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
reg [3:0] subcount = 0;
reg int_strobe = 0, comb_strobe = 0;
always @(posedge clkin) begin
int_strobe <= 0;
comb_strobe <= 0;
if(reset) begin
dac_address_r <= dac_address_ext;
phaseacc <= 0;
subcount <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv + phasemul;
subcount <= subcount + 1;
int_strobe <= 1;
if (subcount == 0) begin
comb_strobe <= 1;
dac_address_r <= dac_address_r + play_r;
end
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
parameter ST0_IDLE = 10'b1000000000;
parameter ST1_COMB1 = 10'b0000000001;
parameter ST2_COMB2 = 10'b0000000010;
parameter ST3_COMB3 = 10'b0000000100;
parameter ST4_INT1 = 10'b0000010000;
parameter ST5_INT2 = 10'b0000100000;
parameter ST6_INT3 = 10'b0001000000;
reg [63:0] ci[2:0], co[2:0], io[2:0];
reg [9:0] cicstate = 10'h200;
wire [63:0] bufi = {{16{dac_data[31]}}, dac_data[31:16], {16{dac_data[15]}}, dac_data[15:0]};
always @(posedge clkin) begin
if(reset) begin
cicstate <= ST0_IDLE;
{ci[2], ci[1], ci[0]} <= 192'h0;
{co[2], co[1], co[0]} <= 192'h0;
{io[2], io[1], io[0]} <= 192'h0;
end else if(int_strobe) begin
if(comb_strobe) cicstate <= ST1_COMB1;
else cicstate <= ST4_INT1;
end else begin
case(cicstate)
/****** COMB STAGES ******/
ST1_COMB1: begin
cicstate <= ST2_COMB2;
ci[0] <= bufi;
co[0][63:32] <= bufi[63:32] - ci[0][63:32];
co[0][31:0] <= bufi[31:0] - ci[0][31:0];
end
ST2_COMB2: begin
cicstate <= ST3_COMB3;
ci[1] <= co[0];
co[1][63:32] <= co[0][63:32] - ci[1][63:32];
co[1][31:0] <= co[0][31:0] - ci[1][31:0];
end
ST3_COMB3: begin
cicstate <= ST4_INT1;
ci[2] <= co[1];
co[2][63:32] <= co[1][63:32] - ci[2][63:32];
co[2][31:0] <= co[1][31:0] - ci[2][31:0];
end
/****** INTEGRATOR STAGES ******/
ST4_INT1: begin
io[0][63:32] <= co[2][63:32] + io[0][63:32];
io[0][31:0] <= co[2][31:0] + io[0][31:0];
cicstate <= ST5_INT2;
end
ST5_INT2: begin
io[1][63:32] <= io[0][63:32] + io[1][63:32];
io[1][31:0] <= io[0][31:0] + io[1][31:0];
cicstate <= ST6_INT3;
end
ST6_INT3: begin
io[2][63:32] <= io[1][63:32] + io[2][63:32];
io[2][31:0] <= io[1][31:0] + io[2][31:0];
cicstate <= ST0_IDLE;
end
default: begin
cicstate <= ST0_IDLE;
end
endcase
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
mclk_sreg <= {mclk_sreg[1:0], mclk};
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? io[2][59:44] : io[2][27:12];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t, n, m, u, v, cnt = 0; long long head[400005], depth[200005], visited[200005]; vector<long long> ve[5]; struct edge { long long next; long long to; } e[400005]; queue<long long> q; inline void add_edge(long long u, long long v) { cnt++; e[cnt].to = v; e[cnt].next = head[u]; head[u] = cnt; } inline void bfs() { q.push(1); depth[1] = 0; visited[1] = 1; while (!q.empty()) { long long now = q.front(); for (long long i = head[now]; i; i = e[i].next) { if (visited[e[i].to] == 0) { depth[e[i].to] = depth[now] + 1; q.push(e[i].to); visited[e[i].to] = 1; } } visited[now] = 1; q.pop(); } } signed main() { cin >> t; while (t--) { cin >> n >> m; cnt = 0; for (long long i = 0; i <= 1; i++) ve[i].clear(); for (long long i = 1; i <= n; i++) visited[i] = 0; for (long long i = 1; i <= 2 * n; i++) head[i] = e[i].next = e[i].to = 0; for (long long i = 1; i <= m; i++) { cin >> u >> v; add_edge(u, v); add_edge(v, u); } bfs(); for (long long i = 1; i <= n; i++) ve[depth[i] % 2].push_back(i); if (ve[0].size() <= ve[1].size()) { cout << ve[0].size() << endl; for (long long i = 0; i < ve[0].size(); i++) cout << ve[0][i] << ; cout << endl; } else { cout << ve[1].size() << endl; for (long long i = 0; i < ve[1].size(); i++) cout << ve[1][i] << ; cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int const nMax = 40000; map<pair<int, int>, int> Q; int main() { int n; int ans = 0; scanf( %d , &n); pair<int, int> a; for (int i = 0; i < n; i++) { scanf( %d%d , &a.first, &a.second); if (Q.find(a) == Q.end()) { Q[a] = 1; } else { Q[a] = Q[a] + 1; } if (Q[a] > ans) ans = Q[a]; } printf( %d n , ans); return 0; }
|
////////////////////////////////////////////////////////////////////////////////
//
// PS2-to-Kempston Mouse
// (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
////////////////////////////////////////////////////////////////////////////////
module mouse
(
input clk_sys,
input reset,
input [24:0] ps2_mouse,
input [2:0] addr,
output sel,
output [7:0] dout
);
assign dout = data;
assign sel = port_sel;
reg [1:0] button;
reg mbutton;
reg [11:0] dx;
reg [11:0] dy;
wire [11:0] newdx = dx + {{4{ps2_mouse[4]}},ps2_mouse[15:8]};
wire [11:0] newdy = dy + {{4{ps2_mouse[5]}},ps2_mouse[23:16]};
reg [1:0] swap;
reg [7:0] data;
reg port_sel;
always @* begin
port_sel = 1;
casex(addr)
3'b011: data = dx[7:0];
3'b111: data = dy[7:0];
3'bX10: data = ~{5'b00000,mbutton, button[swap[1]], button[~swap[1]]} ;
default: {port_sel,data} = 8'hFF;
endcase
end
always @(posedge clk_sys) begin
reg old_status;
old_status <= ps2_mouse[24];
if(reset) begin
dx <= 128; // dx != dy for better mouse detection
dy <= 0;
button <= 0;
swap <= 0;
end else begin
if(old_status != ps2_mouse[24]) begin
if(!swap) swap <= ps2_mouse[1:0];
{mbutton,button} <= ps2_mouse[2:0];
dx <= |newdx[11:8] ? {8{~ps2_mouse[4]}} : newdx;
dy <= |newdy[11:8] ? {8{~ps2_mouse[5]}} : newdy;
end
end
end
endmodule
|
#include <bits/stdc++.h> const int inf = 1e5 + 10; using namespace std; int main() { int to[5][5]; int a[5]; memset(a, 0, sizeof(a)); memset(to, 0, sizeof(to)); ios::sync_with_stdio(0); int n; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == 0 ) a[0]++; else if (s[i] == 1 ) a[1]++; else if (s[i] == 2 ) a[2]++; } n /= 3; for (int i = 1; i <= 2; i++) { for (int j = 0; j < i; j++) { if (a[j] < a[i] && a[i] > n && a[j] < n) { to[i][j] = min(n - a[j], a[i] - n); int p = a[i]; int q = a[j]; a[i] -= min(n - q, p - n); a[j] += min(n - q, p - n); } else if (a[j] > a[i] && a[i] < n && a[j] > n) { int p = a[i]; int q = a[j]; to[j][i] = min(n - p, q - n); a[j] -= min(n - p, q - n); a[i] += min(n - p, q - n); } } } for (int i = 0; i < 2; i++) { for (int j = 2; j > i; j--) { int v = 3 * n - 1; while (to[i][j] && v >= 0) { if (s[v] - 0 == i) { s[v] = 0 + j; to[i][j]--; } v--; } } } for (int i = 1; i <= 2; i++) { for (int j = 0; j < i; j++) { int v = 0; while (to[i][j] && v < 3 * n) { if (s[v] - 0 == i) { s[v] = 0 + j; to[i][j]--; } v++; } } } cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; static int N, K, M, G, U[500003], V[500003], W[500003], fa[500003], sup[500003], dep[500003]; static bool spe[500003]; static vector<pair<bool, int>> edge[500003]; static long long ans; int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void dfs(int u, int f) { dep[u] = dep[sup[u] = f] + 1; for (auto v : edge[u]) if (v.second != f) { spe[v.second] = v.first; dfs(v.second, u); } } int main() { scanf( %d%d%d , &N, &K, &M); for (int i = 1; i <= N; i++) fa[i] = i; for (int i = 0, x, y; i < K; i++) { scanf( %d%d , &x, &y); edge[x].push_back(make_pair(true, y)); edge[y].push_back(make_pair(true, x)); fa[find(x)] = find(y); } for (int i = 0; i < M; i++) { scanf( %d%d%d , &U[G], &V[G], &W[G]); int u = find(U[G]), v = find(V[G]); if (u != v) { edge[U[G]].push_back(make_pair(false, V[G])); edge[V[G]].push_back(make_pair(false, U[G])); fa[u] = v; } else G++; } dfs(1, 0); for (int i = 1; i <= N; i++) fa[i] = i; for (int i = 0; i < G; i++) { int u = find(U[i]), v = find(V[i]); while (u != v) { if (dep[u] < dep[v]) swap(u, v); ans += spe[u] ? W[i] : 0; u = fa[u] = find(sup[u]); } } for (int i = 1; i <= N; i++) for (auto v : edge[i]) if (v.first && find(v.second) != find(i)) return puts( -1 ), 0; printf( %lld n , ans); return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_double (
clock,
resetn,
dataa,
datab,
result,
enable);
input enable;
input clock, resetn;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
// Latency 14
acl_fp_custom_add_core_double core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.HIGH_LATENCY = 1;
defparam core.ROUNDING_MODE = 0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23.09.2016 08:48:06
// Design Name:
// Module Name: linescanner_image_capture_unit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module linescanner_image_capture_unit(
input wire enable,
input wire[7:0] data,
output reg rst_cvc,
output reg rst_cds,
output reg sample,
input wire end_adc,
input wire lval,
input wire pixel_clock,
input wire main_clock_source,
output wire main_clock,
input wire n_reset,
output reg load_pulse,
output wire[7:0] pixel_data,
output wire pixel_captured);
assign main_clock = main_clock_source;
assign pixel_captured = lval ? pixel_clock : 0;
assign pixel_data = data;
localparam
SM1_SEND_FE_OF_RST_CVC = 0,
SM1_SEND_FE_OF_RST_CDS = 1,
SM1_SEND_RE_OF_SAMPLE = 2,
SM1_SEND_FE_OF_SAMPLE = 3,
SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS = 4,
SM1_WAIT_NUM_CLOCKS = 5;
reg[2:0] sm1_state, sm1_state_to_go_to_after_waiting;
reg[5:0] sm1_num_clocks_to_wait, sm1_clock_count;
always @ (posedge pixel_clock or negedge n_reset) begin
if(!n_reset) begin
rst_cvc <= 1'b1;
rst_cds <= 1'b1;
sample <= 1'b0;
sm1_state <= SM1_SEND_FE_OF_RST_CVC;
sm1_state_to_go_to_after_waiting <= 0;
sm1_num_clocks_to_wait <= 0;
sm1_clock_count <= 0;
end
else
case (sm1_state)
SM1_SEND_FE_OF_RST_CVC:
if(enable) begin
rst_cvc <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_FE_OF_RST_CDS;
sm1_num_clocks_to_wait <= 48;
end
SM1_SEND_FE_OF_RST_CDS:
begin
rst_cds <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_RE_OF_SAMPLE;
sm1_num_clocks_to_wait <= 7;
end
SM1_SEND_RE_OF_SAMPLE:
begin
if(end_adc) begin
sample <= 1'b1;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_FE_OF_SAMPLE;
sm1_num_clocks_to_wait <= 48;
end
end
SM1_SEND_FE_OF_SAMPLE:
begin
sample <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS;
sm1_num_clocks_to_wait <= 6;
end
SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS:
begin
rst_cvc <= 1'b1;
rst_cds <= 1'b1;
sm1_state <= SM1_SEND_FE_OF_RST_CVC;
end
SM1_WAIT_NUM_CLOCKS:
if(sm1_clock_count < sm1_num_clocks_to_wait)
sm1_clock_count <= sm1_clock_count + 1;
else begin
sm1_clock_count <= 0;
sm1_state <= sm1_state_to_go_to_after_waiting;
end
endcase
end
localparam
SM2_WAIT_FOR_RE_OF_END_ADC = 0,
SM2_WAIT_FOR_FE_OF_LVAL = 1,
SM2_SEND_RE_OF_LOAD_PULSE = 2,
SM2_SEND_FE_OF_LOAD_PULSE = 3,
SM2_WAIT_FOR_FE_OF_END_ADC = 4,
SM2_WAIT_NUM_CLOCKS = 5;
reg[2:0] sm2_state, sm2_state_to_go_to_after_waiting;
reg[1:0] sm2_clock_count;
always @ (posedge pixel_clock or negedge n_reset) begin
if(!n_reset) begin
load_pulse <= 1'b0;
sm2_state <= 0;
sm2_state_to_go_to_after_waiting <= 0;
sm2_clock_count <= 0;
end
else
case(sm2_state)
SM2_WAIT_FOR_RE_OF_END_ADC:
if(end_adc) begin
if(!lval) begin
sm2_state <= SM2_WAIT_NUM_CLOCKS;
sm2_state_to_go_to_after_waiting <= SM2_SEND_RE_OF_LOAD_PULSE;
end
else
sm2_state <= SM2_WAIT_FOR_FE_OF_LVAL;
end
SM2_WAIT_FOR_FE_OF_LVAL:
if(!lval) begin
sm2_state <= SM2_WAIT_NUM_CLOCKS;
sm2_state_to_go_to_after_waiting <= SM2_SEND_RE_OF_LOAD_PULSE;
end
SM2_SEND_RE_OF_LOAD_PULSE:
begin
load_pulse <= 1'b1;
sm2_state <= SM2_SEND_FE_OF_LOAD_PULSE;
end
SM2_SEND_FE_OF_LOAD_PULSE:
begin
load_pulse <= 1'b0;
sm2_state <= SM2_WAIT_FOR_FE_OF_END_ADC;
end
SM2_WAIT_FOR_FE_OF_END_ADC:
if(!end_adc)
sm2_state <= SM2_WAIT_FOR_RE_OF_END_ADC;
SM2_WAIT_NUM_CLOCKS:
if(sm2_clock_count < 3)
sm2_clock_count <= sm2_clock_count + 1;
else begin
sm2_clock_count <= 0;
sm2_state <= sm2_state_to_go_to_after_waiting;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_8_V
`define SKY130_FD_SC_MS__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, ns[10005] = {}; cin >> n; for (int i = 0; i < n; i++) { cin >> a; ns[a]++; } int ans = 0; for (int i = 0; i < 10000; i++) { int j = i + 1; while (ns[i] > 1) { for (; j < 10000 && ns[j] != 0; j++) ; ns[j]++; ns[i]--; ans += j - i; } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_TB_V
`define SKY130_FD_SC_HVL__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_TB_V
|
//----------------------------------------------------------------------------
//--By Kyle Williams, 11/20/2012-----------------------------------------------------
//--MODULE DESCRIPTION---------------------------------------------------------------
//----------------Simple single Port Ram used to store data--------------------------
//----------------reset is not required ram can be filled with useless data----------
//Instead of using a case statement it would be quicker to act on multiple data at once
//SHOULD BE MADE ABUNDANTLY CLEAR ANY BANK THAT IS ONLY PARTIALLY FILLED WILL BE DROPPED
///ie 1011xxxx will be dropped since it is not fully displaying a word
module Encryption
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 8,
parameter MEM_DEPTH = 64
)(
//------------Input Ports------------
input clk,
input rst,
input ena,
input[DATA_WIDTH-1:0] key,
input[DATA_WIDTH-1:0] data_in,
//------------Output Ports-----------
output reg finished,
output reg mem_wr_ena,
output reg[ADDR_WIDTH-1:0] memIn_addr,
output reg[ADDR_WIDTH-1:0] memOut_addr,
output reg[DATA_WIDTH-1:0] data_out
);
parameter shift = DATA_WIDTH/2;//swap by nibbles instead of shift by address since Range must be bounded by constant expressions.
// ------------- Regs/ wires -----------
//internal memory for encryption
//store address then data in a memory module instead of seperate busses to keep design tidy and easier to follow
parameter MEM_WIDTH = ADDR_WIDTH+DATA_WIDTH;
reg [MEM_WIDTH-1:0] mem [0:8];
reg start;//need to be used to make sure initial statements are correct
reg done;//needs to know when data becomes irrelevant and can stop hardware
always@(posedge clk)
begin:Main_Module
case(rst)
1'b0:
if(ena==1'b1 && start==1'b0)begin
start <= 1'b1;
done <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem_wr_ena <= 1'b0;
end else
if(ena==1'b1) begin:Encryption
begin:Stage_FetchData
if(data_in!=={DATA_WIDTH{1'bx}})begin//bad practice but good assumption
mem[0] <= {memIn_addr-1,data_in};//decrement address since process happens one clock cycle in the future
memIn_addr <= memIn_addr+1;//increment m ram address
end else begin
done <= 1'b1;
mem[0] <= {MEM_WIDTH{1'b0}};
end
end
begin:Stage0_Stage4_Stage7_AddRoundKey//XOR with pin append address to the end
mem[1] <= |mem[0]==1'b0 ? mem[0] : {mem[0][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[0][DATA_WIDTH-1:0] ^ key};
mem[5] <= |mem[4]==1'b0 ? mem[4] : {mem[4][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[4][DATA_WIDTH-1:0] ^ key};
mem[8] <= |mem[7]==1'b0 ? mem[7] : {mem[7][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[7][DATA_WIDTH-1:0] ^ key};
end
begin:Stage1_Stage5_SubBytes//Replace each byte according to loopup table
//Due to complexity and time constraint instead use 2's compliment
mem[2] <= |mem[1]==1'b0 ? mem[1] : {mem[1][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[1][DATA_WIDTH-1:0]+1'b1};
mem[6] <= |mem[5]==1'b0 ? mem[5] : {mem[5][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[5][DATA_WIDTH-1:0]+1'b1};
end
begin:Stage2_Stage6_ShiftRows
mem[3] <= |mem[2]==1'b0 ? mem[2] : {mem[2][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[2][DATA_WIDTH-1-shift-1:0],mem[2][DATA_WIDTH-1:DATA_WIDTH-1-shift]};//<<mem[2][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
mem[7] <= |mem[6]==1'b0 ? mem[6] : {mem[6][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[6][DATA_WIDTH-1-shift-1:0],mem[6][DATA_WIDTH-1:DATA_WIDTH-1-shift]};//<<mem[6][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage3_MixColumns//multMatrix by a set amount...this section is not implimented correctly
//due to time constraints data data by address
mem[4] <= |mem[3]==1'b0 ? mem[3] : {mem[3][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[3][DATA_WIDTH-1:0]+mem[3][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage8_Push_Data//if Performing Bitwise & on all bits doesn't return 0 or 1 then no more data needs to be processed
//placing & infront of a signal performs the AND operator on all bits
if(mem[8]!=={MEM_WIDTH{1'b0}})begin
mem_wr_ena <= 1'b1;
memOut_addr <= mem[8][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH];
data_out <= mem[8][DATA_WIDTH-1:0];
end
else if (done==1'b1) begin
finished <= 1'b1;
start <=1'b0;
done <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
$display("Encryption Completed");
end
end
end
1'b1:
begin:Reset
start <=1'b0;
done <= 1'b0;
finished <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem[0] <= {MEM_WIDTH{1'b0}};
mem[1] <= {MEM_WIDTH{1'b0}};
mem[2] <= {MEM_WIDTH{1'b0}};
mem[3] <= {MEM_WIDTH{1'b0}};
mem[4] <= {MEM_WIDTH{1'b0}};
mem[5] <= {MEM_WIDTH{1'b0}};
mem[6] <= {MEM_WIDTH{1'b0}};
mem[7] <= {MEM_WIDTH{1'b0}};
mem[8] <= {MEM_WIDTH{1'b0}};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int destroy(list<int> row) { int totalDestroyed = 0, lastDestroyed = -1; int combo = 1; while (lastDestroyed != 0) { lastDestroyed = 0; combo = 1; list<int>::iterator it = row.begin(); list<int>::iterator prev = it++; for (; it != row.end(); ++it) { if (*prev == *it) { combo++; } else { if (combo >= 3) { it = row.erase(prev, it); lastDestroyed += combo; } prev = it; combo = 1; } } totalDestroyed += lastDestroyed; } totalDestroyed += (combo >= 3 ? combo : 0); return totalDestroyed > 0 ? totalDestroyed - 1 : 0; } int main() { int N, K, X; cin >> N >> K >> X; list<int> row; int ball; for (int i = 0; i < N; ++i) { cin >> ball; row.push_back(ball); } int maxDestroyed = 0; for (list<int>::iterator it = row.begin(); it != row.end(); ++it) { it = row.insert(it, X); int destroyed = destroy(row); maxDestroyed = max(maxDestroyed, destroyed); it = row.erase(it); } cout << maxDestroyed; }
|
//
// Copyright (c) 1999 Thomas Coonan ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol, but the general scheme
// should be reusable for other types of CRCs with some fiddling.
//
// This CRC code works for a specific type of network protocol, and it
// must do certain byte swappings, etc. You may need to play with it
// for your protocol. Also, make sure the polynomials are what you
// really want. This is obviously, not synthesizable - I just used this
// in a testbench at one point.
//
// These tasks are crude and rely on some global parameters. They should
// also read from a file, yada yada yada. It is probably better to do this
// with a PLI call, but here it is anyway..
//
// The test case includes a golden DOCSIS (Cable Modem) test message that
// was captured in a lab.
//
// tom coonan, 1999.
//
module test_gencrc;
// *** Buffer for the Golden Message ***
reg [7:0] test_packet[0:54];
// *** Global parameter block for the CRC32 calculator.
//
parameter CRC32_POLY = 32'h04C11DB7;
reg [ 7:0] crc32_packet[0:255];
integer crc32_length;
reg [31:0] crc32_result;
// *** Global parameter block for the CRC16 calculator.
//
parameter CRC16_POLY = 16'h1020;
reg [ 7:0] crc16_packet[0:255];
integer crc16_length;
reg [15:0] crc16_result;
`define TEST_GENCRC
`ifdef TEST_GENCRC
// Call the main test task and then quit.
//
initial begin
main_test;
$finish;
end
`endif
// ****************************************************************
// *
// * GOLDEN MESSAGE
// *
// * The golden message is a DOCSIS frame that was captured off
// * the Broadcom reference design. It is a MAP message. It
// * includes a HCS (crc 16) and a CRC32.
// *
// *
// ****************************************************************
//
task initialize_test_packet;
begin
test_packet[00] = 8'hC2; // FC. HCS coverage starts here.
test_packet[01] = 8'h00; // MACPARAM
test_packet[02] = 8'h00; // MAC LEN
test_packet[03] = 8'h30; // MAC LEN. HCS Coverage includes this byte and ends here.
test_packet[04] = 8'hF2; // CRC16 (also known as HCS)
test_packet[05] = 8'hCF; // CRC16 cont..
test_packet[06] = 8'h01; // Start of the IEEE payload. CRC32 covererage starts here. This is the DA field
test_packet[07] = 8'hE0; // DA field cont..
test_packet[08] = 8'h2F; // DA field cont..
test_packet[09] = 8'h00; // DA field cont..
test_packet[10] = 8'h00; // DA field cont..
test_packet[11] = 8'h01; // DA field cont..
test_packet[12] = 8'h00; // SA field
test_packet[13] = 8'h80; // SA field cont..
test_packet[14] = 8'h42; // SA field cont..
test_packet[15] = 8'h42; // SA field cont..
test_packet[16] = 8'h20; // SA field cont..
test_packet[17] = 8'h9E; // SA field cont..
test_packet[18] = 8'h00; // IEEE LEN field
test_packet[19] = 8'h1E; // IEEE LEN field cont.
test_packet[20] = 8'h00; // LLC field.
test_packet[21] = 8'h00; // LLC field cont...
test_packet[22] = 8'h03; // LLC field cont...
test_packet[23] = 8'h01; // LLC field cont...
test_packet[24] = 8'h03; // LLC field cont... This is also the TYPE, which indicates MAP.
test_packet[25] = 8'h00; // LLC field cont...
test_packet[26] = 8'h01; // Start of MAP message payload.
test_packet[27] = 8'h01; // MAP message payload..
test_packet[28] = 8'h02; // MAP message payload..
test_packet[29] = 8'h00; // MAP message payload..
test_packet[30] = 8'h00; // MAP message payload..
test_packet[31] = 8'h18; // MAP message payload..
test_packet[32] = 8'hAA; // MAP message payload..
test_packet[33] = 8'h58; // MAP message payload..
test_packet[34] = 8'h00; // MAP message payload..
test_packet[35] = 8'h18; // MAP message payload..
test_packet[36] = 8'hA8; // MAP message payload..
test_packet[37] = 8'hA0; // MAP message payload..
test_packet[38] = 8'h02; // MAP message payload..
test_packet[39] = 8'h03; // MAP message payload..
test_packet[40] = 8'h03; // MAP message payload..
test_packet[41] = 8'h08; // MAP message payload..
test_packet[42] = 8'hFF; // MAP message payload..
test_packet[43] = 8'hFC; // MAP message payload..
test_packet[44] = 8'h40; // MAP message payload..
test_packet[45] = 8'h00; // MAP message payload..
test_packet[46] = 8'h00; // MAP message payload..
test_packet[47] = 8'h01; // MAP message payload..
test_packet[48] = 8'hC0; // MAP message payload..
test_packet[49] = 8'h14; // Last byte of MAP payload, last byte covered by CRC32.
test_packet[50] = 8'hDD; // CRC32 Starts here
test_packet[51] = 8'hBF; // CRC32 cont..
test_packet[52] = 8'hC1; // CRC32 cont..
test_packet[53] = 8'h2E; // Last byte of CRC32, last byte of DOCSIS.
end
endtask
// *************************************************************************
// *
// * Main test task.
// *
// * Use our primary "golden packet". Copy into the generic global
// * variables that the low-level 'gencrc16' and 'gencrc32' tasks use.
// * Comare against the expected values and report SUCCESS or FAILURE.
// *
// *************************************************************************
//
task main_test;
integer i, j;
integer num_errors;
reg [15:0] crc16_expected;
reg [31:0] crc32_expected;
begin
num_errors = 0;
// Initialize the Golden Message!
//
initialize_test_packet;
// **** TEST CRC16
//
//
// Copy golden test_packet into the main crc16 buffer..
for (i=0; i<4; i=i+1) begin
crc16_packet[i] = test_packet[i];
end
crc16_expected = {test_packet[4], test_packet[5]};
crc16_length = 4; // Must tell test function the length
gencrc16; // Call main test function
if (crc16_result !== crc16_expected)
begin
num_errors = num_errors + 1;
$display ("FAILED - Actual crc16_result = %h, Expected = %h",
crc16_result, crc16_expected);
end
// **** TEST CRC16
//
j = 0;
for (i=6; i<50; i=i+1) begin
crc32_packet[j] = test_packet[i];
j = j + 1;
end
crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]};
crc32_length = 44;
gencrc32;
if (crc32_result !== crc32_expected)
begin
$display ("FAILED - Actual crc32_result = %h, Expected = %h",
crc32_result, crc32_expected);
num_errors = num_errors + 1;
end
if(num_errors == 0)
$display("PASSED");
end
endtask
// ****************************************************************
// *
// * Main working CRC tasks are: gencrc16, gencrc32.
// *
// * These tasks rely on some globals (see front of program).
// *
// ****************************************************************
// Generate a (DOCSIS) CRC16.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter CRC16_POLY = 16'h1020;
// reg [ 7:0] crc16_packet[0:255];
// integer crc16_length;
//
// Globals modified:
// reg [15:0] crc16_result;
//
task gencrc16;
integer byte, bit;
reg msb;
reg [7:0] current_byte;
reg [15:0] temp;
begin
crc16_result = 16'hffff;
for (byte = 0; byte < crc16_length; byte = byte + 1) begin
current_byte = crc16_packet[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc16_result[15];
crc16_result = crc16_result << 1;
if (msb != current_byte[bit]) begin
crc16_result = crc16_result ^ CRC16_POLY;
crc16_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 2 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 16; bit = bit + 1)
temp[15-bit] = crc16_result[bit];
// Swap and Complement:
crc16_result = ~{temp[7:0], temp[15:8]};
end
endtask
// Generate a (DOCSIS) CRC32.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter CRC32_POLY = 32'h04C11DB7;
// reg [ 7:0] crc32_packet[0:255];
// integer crc32_length;
//
// Globals modified:
// reg [31:0] crc32_result;
//
task gencrc32;
integer byte, bit;
reg msb;
reg [7:0] current_byte;
reg [31:0] temp;
begin
crc32_result = 32'hffffffff;
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
current_byte = crc32_packet[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_byte[bit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 32; bit = bit + 1)
temp[31-bit] = crc32_result[bit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program demonstrates a tricky aspect of the Verilog syntax.
* The problem is with the repeat statement. In fact, there is a
* question as to whether it is a repeat statement at all, or an
* event statement with a repeat modifier. These are the possibilities:
*
* procedural_timing_control_statement ::=
* delay_or_event_control statement_or_null
*
* delay_or_event_control ::=
* event_control
* | repeat ( expression ) event_control
*
* If this interpretation is used, then ``repeat (5) @(posedge clk)''
* should be taken as a delay_or_event_control and the thread will
* block until the 5th clk posedge.
*
* loop_statement ::=
* repeat ( expression ) statement
*
* If *this* interpretation is used, then ``repeat (5)'' is the loop
* head is used and the statement in the example is executed 5 times.
*
* These two interpretations both appear to be perfectly valid. However,
* real tools use the loop_statement, so the standard must be considered
* broken and this interpretation used.
*/
module main;
reg clk = 1;
always #5 clk = ~clk;
initial #1
repeat (5) @(posedge clk) begin
if ($time !== 10) begin
$display("FAILED -- $time = %t", $time);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2021 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module testbench(
/*AUTOARG*/
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
logic third_clk; // Additional dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
other_clk = val;
endfunction;
export "DPI-C" function set_third_clk;
function void set_third_clk(bit val);
third_clk = val;
endfunction;
bit even_other = 1;
import "DPI-C" context function void toggle_other_clk(bit val);
always @(posedge clk) begin
even_other <= ~even_other;
toggle_other_clk(even_other);
end
bit even_third = 1;
import "DPI-C" context function void toggle_third_clk(bit val);
always @(posedge other_clk) begin
even_third <= ~even_third;
toggle_third_clk(even_third);
end
int n = 0;
always @(posedge third_clk) begin
$display("t=%d n=%d", $time, n);
if ($time != (8*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
n += 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int TESTS, k, a, n, b, c, d, m, x, i, y, z; cin >> TESTS; while (TESTS--) { cin >> n; cin >> s; long long int ans = n; for (long long int i = 0; i <= n - 1; i++) { if (s[i] == 1 ) { a = max(i + 1, n - i); ans = max(ans, 2 * a); } } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int sz = 317; int t[100002], a[100002]; int l[100002], r[100002]; long long sum[2][100002]; long long ans[100002]; struct node { int b, r, i; }; bool cmp(node a, node b) { if (a.b != b.b) return a.b < b.b; return a.r < b.r; } int n, k, q; long long res = 0; node block[100002]; int val[3][100002]; int dp[300006]; void add1(int i) { res += dp[val[1][i]]; dp[val[0][i]]++; } void del1(int i) { dp[val[0][i]]--; res -= dp[val[1][i]]; } void add2(int i) { res += dp[val[2][i]]; dp[val[0][i]]++; } void del2(int i) { dp[val[0][i]]--; res -= dp[val[2][i]]; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &t[i]), t[i]--; vector<long long> v; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum[0][i] = sum[0][i - 1]; sum[1][i] = sum[1][i - 1]; sum[t[i]][i] += a[i]; v.emplace_back(sum[0][i] - sum[1][i]); v.emplace_back(sum[0][i] - sum[1][i] - k); v.emplace_back(sum[0][i] - sum[1][i] + k); } v.emplace_back(0); v.emplace_back(-k); v.emplace_back(+k); sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); for (int i = 0; i <= n; i++) { val[0][i] = lower_bound(v.begin(), v.end(), sum[0][i] - sum[1][i]) - v.begin() + 1; val[1][i] = lower_bound(v.begin(), v.end(), sum[0][i] - sum[1][i] - k) - v.begin() + 1; val[2][i] = lower_bound(v.begin(), v.end(), sum[0][i] - sum[1][i] + k) - v.begin() + 1; } scanf( %d , &q); for (int i = 1; i <= q; i++) { scanf( %d%d , &l[i], &r[i]); l[i]--; block[i] = {l[i] / sz, r[i], i}; } sort(block + 1, block + 1 + q, cmp); int curl = 0, curr = 0; dp[val[0][0]]++; for (int i = 1; i <= q; i++) { int idx = block[i].i; int ll = l[idx], rr = r[idx]; while (curl < ll) del2(curl++); while (curl > ll) add2(--curl); while (curr < rr) add1(++curr); while (curr > rr) del1(curr--); ans[idx] = res; } for (int i = 1; i <= q; i++) printf( %lld n , ans[i]); }
|
#include <bits/stdc++.h> template <typename element_type> std::vector<element_type> read_vector(int size); using namespace std; int main() { int particles; string direction; while (cin >> particles >> direction) { vector<int> start = read_vector<int>(particles); int best = -1; for (int i = 1; i < particles; i++) if (direction[i - 1] == R && direction[i] == L ) if (best == -1 || (start[i] - start[i - 1]) / 2 < best) best = (start[i] - start[i - 1]) / 2; cout << best << n ; } } template <typename element_type> std::vector<element_type> read_vector(int size) { std::vector<element_type> ret(size); for (int i = 0; i < size; i++) std::cin >> ret[i]; return ret; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int gi() { int x = 0, c = getchar(); bool f = 0; for (; !isdigit(c); c = getchar()) if (c == - ) f = 1; for (; isdigit(c); c = getchar()) x = x * 10 + (c & 15); return f ? -x : x; } const int N = 300005; const int mod = 998244353; int a[N]; int qpow(int a, int b) { int t = 1; while (b) { if (b & 1) t = 1ll * t * a % mod; a = 1ll * a * a % mod; b >>= 1; } return t; } bool cmp(const int &a, const int &b) { return a < b; } int main() { int n = gi(); for (int i = 1; i <= (n << 1); ++i) a[i] = gi(); sort(a + 1, a + (n << 1) + 1, cmp); int fac = 1; for (int i = 1; i <= n; ++i) fac = 1ll * fac * i % mod; int faci = qpow(fac, mod - 2); for (int i = n + 1; i <= (n << 1); ++i) fac = 1ll * fac * i % mod; int ans = 0; for (int i = 1; i <= n; ++i) { ans += a[n + i] - a[i]; if (ans >= mod) ans -= mod; } printf( %d n , 1ll * fac * faci % mod * faci % mod * ans % mod); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:05:37 11/06/2013
// Design Name:
// Module Name: sound_selector
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sound_selector(
input clock,
input lrck,
input reset,
input[1:0] sound_code,
output reg [15:0] left_data,
output reg [15:0] right_data
);
reg [3:0] temp_addra;
wire [3:0] addra;
wire [31:0] douta;
initial
begin
temp_addra <= 4'b0;
end
assign addra = temp_addra;
always @ (posedge lrck or posedge reset)
begin
if(reset)
begin
temp_addra <= 4'b0;
end
else
begin
temp_addra <= temp_addra + 1;
end
end
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
left_data <= 16'b0;
right_data <= 16'b0;
end
else
begin
left_data <= douta[31:16];
right_data <= douta[15:0];
end
end
sounds_mem sounds_bank (
.clka(clock), // input clka
.addra(addra), // input [3 : 0] addra
.douta(douta) // output [31 : 0] douta
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; char seat[10][1005]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int mark = 2000; int flag; for (int i = 0; i < n; i++) { cin >> seat[0][i] >> seat[1][i] >> seat[2][i] >> seat[3][i] >> seat[4][i]; if (seat[0][i] == O && seat[1][i] == O ) { mark = i; flag = 0; } if (seat[3][i] == O && seat[4][i] == O ) { mark = i; flag = 3; } } if (mark == 2000) cout << NO << endl; else { seat[flag][mark] = + ; seat[flag + 1][mark] = + ; cout << YES << endl; for (int i = 0; i < n; i++) { cout << seat[0][i] << seat[1][i] << seat[2][i] << seat[3][i] << seat[4][i] << endl; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const long long N = (long long)2e6 + 222; const long long INF = (long long)1e18; const double eps = (double)1e-6; long long n, m, l, r, used[N]; vector<long long> g[N]; set<long long> s; long long cnt = 0; void dfs(long long x) { used[x] = 1; s.erase(x); cnt++; long long pr = 0; for (auto to : g[x]) { while (s.upper_bound(pr) != s.end() && (*s.upper_bound(pr)) < to) { long long k = (*s.upper_bound(pr)); if (!used[k]) dfs(k); } pr = to; } } void solve() { cin >> n >> m; for (long long i = 1; i <= m; ++i) { cin >> l >> r; g[l].push_back(r); g[r].push_back(l); } for (long long i = 1; i <= n; ++i) s.insert(i); long long ans = 0; for (long long i = 1; i <= n; ++i) sort(g[i].begin(), g[i].end()); for (long long i = 1; i <= n; ++i) g[i].push_back(n + 1); for (long long i = 1; i <= n; ++i) { if (!used[i]) { ans++; dfs(i); } } cout << ans - 1; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> long long size(const T& x) { return x.size(); } #pragma GCC optimize( Ofast ) template <class T> T smod(T a, T b) { return (a % b + b) % b; } long long pw(long long a, long long b) { long long res = 1; while (b > 0) { if (b % 2) res = (res * a) % 1000000007; b /= 2; a = a * a % 1000000007; } return res; } void solve() { long long n; cin >> n; string S; cin >> S; long long cntk = 0; for (long long i = (0); i < (n); ++i) cntk += (S[i] == ? ); vector<long long> A(n); A[0] = (S[0] == a ); for (long long i = (1); i < (n); ++i) A[i] = A[i - 1] + (S[i] == a ); vector<long long> C(n); C[n - 1] = (S[n - 1] == c ); for (long long i = (n - 2); i > -1; --i) C[i] = C[i + 1] + (S[i] == c ); vector<long long> KL(n); KL[0] = (S[0] == ? ); for (long long i = (1); i < (n); ++i) KL[i] = KL[i - 1] + (S[i] == ? ); vector<long long> KR(n); KR[n - 1] = (S[n - 1] == ? ); for (long long i = (n - 2); i > -1; --i) KR[i] = KR[i + 1] + (S[i] == ? ); long long ans = 0; for (long long i = (1); i < (n - 1); ++i) { if (S[i] == a || S[i] == c ) continue; long long cnta = A[i - 1]; long long cntc = C[i + 1]; long long cntkl = KL[i - 1]; long long cntkr = KR[i + 1]; long long isk = (S[i] == ? ); ans = (ans + cnta * cntc * pw(3, cntk - isk)) % 1000000007; ans = (ans + cnta * cntkr * pw(3, cntk - 1 - isk)) % 1000000007; ans = (ans + cntkl * cntc * pw(3, cntk - 1 - isk)) % 1000000007; ans = (ans + cntkl * cntkr * pw(3, cntk - 2 - isk)) % 1000000007; } cout << ans << endl; } int main() { cin.sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); solve(); return 0; }
|
module wb_stream_reader_cfg
#(parameter WB_AW = 32,
parameter WB_DW = 32)
(
input wb_clk_i,
input wb_rst_i,
//Wishbone IF
input [4:0] wb_adr_i,
input [WB_DW-1:0] wb_dat_i,
input [WB_DW/8-1:0] wb_sel_i,
input wb_we_i ,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output [WB_DW-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
//Application IF
output reg irq,
input busy,
output reg enable,
input [WB_DW-1:0] tx_cnt,
output reg [WB_AW-1:0] start_adr,
output reg [WB_AW-1:0] buf_size,
output reg [WB_AW-1:0] burst_size);
reg busy_r;
always @(posedge wb_clk_i)
if (wb_rst_i)
busy_r <= 0;
else
busy_r <= busy;
// Read
assign wb_dat_o = wb_adr_i[4:2] == 0 ? {{(WB_DW-2){1'b0}}, irq, busy} :
wb_adr_i[4:2] == 1 ? start_adr :
wb_adr_i[4:2] == 2 ? buf_size :
wb_adr_i[4:2] == 3 ? burst_size :
wb_adr_i[4:2] == 4 ? tx_cnt*4 :
0;
always @(posedge wb_clk_i) begin
// Ack generation
if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
//Read/Write logic
enable <= 0;
if (wb_stb_i & wb_cyc_i & wb_we_i & wb_ack_o) begin
case (wb_adr_i[4:2])
0 : begin
if (wb_dat_i[0]) enable <= 1;
if (wb_dat_i[1]) irq <= 0;
end
1 : start_adr <= wb_dat_i;
2 : buf_size <= wb_dat_i;
3 : burst_size <= wb_dat_i;
default : ;
endcase
end
// irq logic, signal on falling edge of busy
if (!busy & busy_r)
irq <= 1;
if (wb_rst_i) begin
wb_ack_o <= 0;
enable <= 1'b0;
start_adr <= 0;
buf_size <= 0;
burst_size <= 0;
irq <= 0;
end
end
assign wb_err_o = 0;
endmodule
|
// CREDIT:
// John Loomis (http://www.johnloomis.org/)
// http://www.johnloomis.org/digitallab/ps2lab1/ps2lab1.html
module keyboard(keyboard_clk, keyboard_data, clock50, reset, read, scan_ready, scan_code);
input keyboard_clk;
input keyboard_data;
input clock50; // 50 Mhz system clock
input reset;
input read;
output scan_ready;
output [7:0] scan_code;
reg ready_set;
reg [7:0] scan_code;
reg scan_ready;
reg read_char;
reg clock; // 25 Mhz internal clock
reg [3:0] incnt;
reg [8:0] shiftin;
reg [7:0] filter;
reg keyboard_clk_filtered;
// scan_ready is set to 1 when scan_code is available.
// user should set read to 1 and then to 0 to clear scan_ready
always @ (posedge ready_set or posedge read)
if (read == 1) scan_ready <= 0;
else scan_ready <= 1;
// divide-by-two 50MHz to 25MHz
always @(posedge clock50)
clock <= ~clock;
// This process filters the raw clock signal coming from the keyboard
// using an eight-bit shift register and two AND gates
always @(posedge clock)
begin
filter <= {keyboard_clk, filter[7:1]};
if (filter==8'b1111_1111) keyboard_clk_filtered <= 1;
else if (filter==8'b0000_0000) keyboard_clk_filtered <= 0;
end
// This process reads in serial data coming from the terminal
always @(posedge keyboard_clk_filtered)
begin
if (reset==1)
begin
incnt <= 4'b0000;
read_char <= 0;
end
else if (keyboard_data==0 && read_char==0)
begin
read_char <= 1;
ready_set <= 0;
end
else
begin
// shift in next 8 data bits to assemble a scan code
if (read_char == 1)
begin
if (incnt < 9)
begin
incnt <= incnt + 1'b1;
shiftin = { keyboard_data, shiftin[8:1]};
ready_set <= 0;
end
else
begin
incnt <= 0;
scan_code <= shiftin[7:0];
read_char <= 0;
ready_set <= 1;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:54 03/02/2016
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(zero, aluRes, input1, input2, aluCtr);
output zero;
output [31:0] aluRes;
input [31:0] input1;
input [31:0] input2;
input [3:0] aluCtr;
reg zero;
reg [31:0] aluRes;
always @ (input1 or input2 or aluCtr)
begin
if(aluCtr == 4'b0010) //+
aluRes = input1 + input2;
else if(aluCtr == 4'b0110) //-
begin
aluRes = input1 - input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0000) //&
begin
aluRes = input1 & input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0001) //|
begin
aluRes = input1 | input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0111) //slt
begin
if(input1 < input2)
begin
zero = 0;
aluRes = 1;
end
else
begin
zero = 1;
aluRes = 0;
end
end
else if(aluCtr == 4'b1100) //NOR
begin
aluRes = ~(input1 | input2);
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
end
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_wb_master
*/
module test_axis_wb_master_8_32;
// Parameters
parameter IMPLICIT_FRAMING = 0;
parameter COUNT_SIZE = 16;
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH/8);
parameter READ_REQ = 8'hA1;
parameter WRITE_REQ = 8'hA2;
parameter READ_RESP = 8'hA3;
parameter WRITE_RESP = 8'hA4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
wb_dat_i,
wb_ack_i,
wb_err_i
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
wb_adr_o,
wb_dat_o,
wb_we_o,
wb_sel_o,
wb_stb_o,
wb_cyc_o,
busy
);
// dump file
$dumpfile("test_axis_wb_master_8_32.lxt");
$dumpvars(0, test_axis_wb_master_8_32);
end
axis_wb_master #(
.IMPLICIT_FRAMING(IMPLICIT_FRAMING),
.COUNT_SIZE(COUNT_SIZE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH),
.READ_REQ(READ_REQ),
.WRITE_REQ(WRITE_REQ),
.READ_RESP(READ_RESP),
.WRITE_RESP(WRITE_RESP)
)
UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/BUFH.v,v 1.3 2008/11/11 21:41:06 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / H Clock Buffer
// /___/ /\ Filename : BUFH.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 09//9/08 - Change to use BUFHCE according to yaml.
// 11/11/08 - Change to not use BUFHCE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFH (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; int a[m]; for (int i = 0; i < m; ++i) a[i] = 1e7; for (int i = 0; i < n; ++i) { int r, c; cin >> r >> c; a[r - 1] = min(a[r - 1], c); } int ans = 0; for (int i = 0; i < m; ++i) ans += a[i]; cout << min(ans, k) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s18kapwr.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s18kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
|
(* techmap_celltype = "$_NOT_" *)
module _90_lut_not (A, Y);
input A;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b01)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_OR_" *)
module _90_lut_or (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_AND_" *)
module _90_lut_and (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1000)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_XOR_" *)
module _90_lut_xor (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b0110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_MUX_" *)
module _90_lut_mux (A, B, S, Y);
input A, B, S;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {S, B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
// A 1010 1010
// B 1100 1100
// S 1111 0000
.LUT(8'b 1100_1010)
) lut (
.A(AA),
.Y(Y)
);
endmodule
|
// Filename: channel_tb1.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module connecting transmit to receive. This uses a clock of
// sufficent period to ensure that the parity gen can keep up.
`timescale 1ns/100ps
module channel_tb1();
reg enable; // Enable for counter
reg clear; // Clear for counter
reg clk_en; // Clock enable
wire clk; // Wire connecting clock to counter and both regs
wire[9:0] data; // Bus connecting transmit and receive modules
wire[8:0] data_out; // Data output of receive
wire data_valid; // Output of comparator from receive module
// Transmit module containing counter and parity gen.
transmit DUT1(enable, clear, clk, data);
// Receive module containing reg, parity gen, and comparator
receive DUT2(clk, data, data_out, data_valid);
// Clock feeding counter and both regs, period set to 100
clk #(100) DUT3(clk_en, clk);
// Using similar inputs as ctr_tb.v
initial begin
enable = 0;
clear = 0;
clk_en = 1;
#10 clear = 1;
#40 clear = 0;
#50 enable = 1;
#400 enable = 0;
#100 enable = 1;
#500 clear = 1;
#60 clear = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void mini(T& a, T b) { a = min(a, b); } template <class T> void maxi(T& a, T b) { a = max(a, b); } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { return out << a.first << << a.second; } template <class T> ostream& operator<<(ostream& out, vector<T> a) { for (auto& i : a) out << i << ; return out; } template <class T> ostream& operator<<(ostream& out, set<T> a) { for (auto& i : a) out << i << ; return out; } template <class T> ostream& operator<<(ostream& out, multiset<T> a) { for (auto& i : a) out << i << ; return out; } template <class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template <class T1, class T2> ostream& operator<<(ostream& out, unordered_map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template <class T> ostream& operator<<(ostream& out, queue<T> a) { while (!a.empty()) { cout << a.front() << ; a.pop(); } return out; } template <class T> ostream& operator<<(ostream& out, deque<T> a) { while (!a.empty()) { cout << a.front() << ; a.pop_front(); } return out; } template <class T> ostream& operator<<(ostream& out, priority_queue<T> a) { while (!a.empty()) { cout << a.top() << n ; a.pop(); } return out; } template <class T> void out(T a) { cout << a << endl; } template <class T1, class T2> void out(T1 a, T2 b) { cout << a << << b << endl; } template <class T1, class T2, class T3> void out(T1 a, T2 b, T3 c) { cout << a << << b << << c << endl; } void out() { cout << OK << endl; } template <class T> void sort(vector<T>& a) { sort(a.begin(), a.end()); } template <class T> void uniq(vector<T>& a) { sort(a); a.erase(unique(a.begin(), a.end()), a.end()); } template <class T> vector<T> set_int(vector<T> a, vector<T> b) { sort(a); sort(b); vector<T> res; set_intersection(a.begin(), a.end(), b.begin(), b.end(), back_inserter(res)); return res; } istream& operator>>(istream& in, __int128& a) { int64_t b; cin >> b; a = b; return in; } ostream& operator<<(ostream& out, const __int128 a) { unsigned __int128 b = a < 0 ? -a : a; char buf[128]; char* c = end(buf); do { --c; *c = 0123456789 [b % 10]; b /= 10; } while (b); if (a < 0) { --c; *c = - ; } int len = end(buf) - c; out.rdbuf()->sputn(c, len); return out; } const int N = 1e5 + 5; const int inf = 1e9; vector<int> dp, pr; vector<bool> used; vector<int> a[N]; void Solve() { int n, k; cin >> n >> k; int h = 5 * sqrt(k); int ans = 0; for (int i = 1; i <= k; i++) { int r, c; cin >> r >> c; if (n - r < h) a[c - 1].push_back(n - r); else ans += 3; } dp.resize(h, 0); pr.resize(h, 0); used.resize(h, 0); for (int i = n - 1; i >= 0; i--) { for (int j = 0; j <= h - 1; j++) used[j] = 0; for (int j : a[i]) used[j] = 1; for (int& j : dp) j = inf; int suf = 0; for (int j = h - 1; j >= 0; j--) { if (used[j]) suf += 3; int cur = suf + pr[max(j - 1, 0)]; mini(dp[j], cur); if (j) cur += 2 + j * (j + 1) / 2; mini(dp[0], cur); } for (int j = 0; j <= h - 2; j++) mini(dp[j + 1], dp[j]); swap(dp, pr); } ans += pr[0]; out(ans); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int k, n; bool contain_same; string s[5005], t[5005]; bool check(int x, int y) { swap(s[0][x], s[0][y]); for (int i = 1; i < k; ++i) { int dif = 0; for (int j = 0; j < n; ++j) { if (s[0][j] != s[i][j]) ++dif; } if (dif == 2 || (dif == 0 && contain_same)) continue; swap(s[0][x], s[0][y]); return 0; } return 1; } signed main() { scanf( %d%d , &k, &n); for (int i = 0; i < k; ++i) { cin >> s[i]; t[i] = s[i]; sort(t[i].begin(), t[i].end()); } for (int i = 1; i < k; ++i) if (t[i] != t[i - 1]) return puts( -1 ), 0; int alp[26] = {}; for (auto ch : s[0]) alp[ch - a ]++; for (int i = 0; i < 26; ++i) if (alp[i] > 1) contain_same = 1; int ma_val = 0, ma_id = 0; for (int i = 1; i < k; ++i) { int cnt = 0; for (int j = 0; j < n; ++j) { if (s[0][j] != s[i][j]) ++cnt; } if (cnt > 4) return puts( -1 ), 0; else if (ma_val < cnt) { ma_val = cnt; ma_id = i; } } if (ma_val == 0) { swap(s[0][0], s[0][1]); cout << s[0]; return 0; } if (ma_val == 2) { if (contain_same) { cout << s[0]; return 0; } return puts( -1 ), 0; } vector<int> pos; for (int i = 0; i < n; ++i) if (s[0][i] != s[ma_id][i]) pos.push_back(i); for (auto x : pos) { for (int y = 0; y < n; ++y) { if (x == y) continue; if (check(x, y)) { cout << s[0]; return 0; } } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n == 1) cout << m; else if (n - m > m - 1 && n - m != 0) cout << m + 1; else cout << m - 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool near(long long A, long long B, long long X, long long Y, long long T) { if ((X - Y * T) < 0) return (0); if ((A - B * T) * Y != (X - Y * T) * B) return ((A - B * T) * Y > (X - Y * T) * B); return (B < Y); } int main() { int t1, t2, x1, x2, t0; scanf( %d %d %d %d %d , &t1, &t2, &x1, &x2, &t0); if (t1 == t0 || t2 == t0) { int a1 = x1 * (t1 == t0); int a2 = x2 * (t2 == t0); printf( %d %d n , a1, a2); return (0); } int dmin = t2 - t0; int ret1 = 0, ret2 = x2; for (int i = 1; i <= x1; i++) { long long y = ((long long)(t0 - t1) * i) / (t2 - t0); int y2 = min(y, (long long)x2); for (int j = max(0, y2 - 1); j <= min(x2, y2 + 1); j++) { if (near((long long)t1 * ret1 + (long long)t2 * ret2, ret1 + ret2, (long long)t1 * i + (long long)t2 * j, i + j, t0)) { ret1 = i; ret2 = j; } } } printf( %d %d n , ret1, ret2); return (0); }
|
#include <bits/stdc++.h> using namespace std; unsigned long long int w, v, qt = 0, n; inline unsigned long long int f(unsigned long long int x) { return w * (1 - x) * (1 - x) + v; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> v >> w; char c; while (cin >> c) qt += c == 1 ; unsigned long long int ans = (~0ULL); for (int i = 1; i <= qt; i++) { unsigned long long int tmp = 0; tmp += (i - (n % i)) * f(n / i); tmp += (n % i) * f(n / i + 1); ans = min(ans, tmp); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const long long INF = 1e18; const long long N = 2e5 + 50; const long long MOD = 1e9 + 7; using namespace std; vector<long long> prime, graph[N]; long long n, k, a[N], m, z; long long POWER(long long base, long long expo) { long long ret = 1; while (expo) { if (expo & 1) ret = ret * base; expo >>= 1; base = base * base; } return ret; } void SOE(long long n) { bool isPrime[n + 1]; memset(isPrime, true, sizeof(isPrime)); for (long long p = 2; p <= n; p++) { if (isPrime[p]) { for (long long i = p * p; i <= n; i += p) isPrime[i] = false; } } for (long long i = 2; i <= n; i++) { if (isPrime[i]) prime.push_back(i); } } int main() { long long test_case = 1; cin >> test_case; while (test_case--) { cin >> n >> k >> z; for (long long i = 0; i < n; i++) cin >> a[i]; vector<long long> v; long long ans = 0, m = -1; for (long long i = 0; i < n; i++) { if (m < k) { ans += a[i]; m++; } } for (long long i = 1; i <= k; i++) { for (long long c = 0; c <= z; c++) { long long l = k, sum = 0, j = i, times = 0; while (j < l && times < c) { if (j == i) { j--; sum += a[j]; sum -= a[l]; l--; times++; } if (j < l) { j++; sum += a[j]; sum -= a[l]; l--; } } v.push_back(sum); } } sort(v.begin(), v.end()); long long s = 0; if (v.size() > 0) { s = v[v.size() - 1]; } cout << max(ans, ans + s) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 30; struct Node { int pos, val; bool operator<(const Node& a) const { return val < a.val; } } p[maxn]; int ans[maxn]; int n; int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> p[i].val, p[i].pos = i; sort(p + 1, p + n + 1); for (int i = 2; i <= n; ++i) ans[p[i].pos] = p[i - 1].val; ans[p[1].pos] = p[n].val; for (int i = 1; i <= n; ++i) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = int(1e5) + 500; int n, m, a[N], s, h, mm; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> s; for (int i = 1; i <= n; i++) { cin >> h >> mm; a[++m] = h * 60 + mm; } if (a[1] >= s + 1) { cout << 0 << << 0; exit(0); } for (int i = 2; i <= n; i++) { if (a[i] - a[i - 1] >= s * 2 + 2) { cout << (a[i - 1] + s + 1) / 60 << << (a[i - 1] + s + 1) % 60; exit(0); } } cout << (a[m] + s + 1) / 60 << << (a[m] + s + 1) % 60; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool comp(const pair<int, int> &a, const pair<int, int> &b) { if (a.first > b.first) return true; if (a.first == b.first) return a.second > b.second; return false; } int main() { int n; scanf( %d , &n); vector<pair<int, int> > v; for (int i = 0; i < n; i++) { int k; scanf( %d , &k); int a[100001]; int ok = 1; for (int i = 0; i < k; i++) { scanf( %d , &a[i]); if (i && a[i] > a[i - 1]) ok = 0; } if (ok) v.push_back(make_pair(a[0], a[k - 1])); } sort(v.begin(), v.end(), comp); vector<int> lo, hi; for (auto i : v) { hi.push_back(i.first); lo.push_back(i.second); } long long ans = 0; for (int i = 0; i < v.size(); i++) { int m = upper_bound(hi.rbegin(), hi.rend(), lo[i]) - hi.rbegin(); ans += m; } printf( %lld , ((long long)n * (long long)n) - ans); }
|
#include <bits/stdc++.h> using namespace std; int p[35], d[35], g[35], h[35], w[55], n, a, b, c, s, MOD; bool f[35][35][50005], v[35][35][50005]; int main() { int i, j, k, r = 0, x; scanf( %d%d , &n, &MOD); for (i = 0; i <= 40; i++) { if (i < 10) w[i] = 10 % MOD; else w[i] = 100 % MOD; } for (i = 1; i <= n; i++) { scanf( %d , &x); if (x < 32) { s++; d[s] = x; g[s] = i; } } n = min(n, 31); for (i = 1; i <= n; i++) { f[i][d[i]][d[i] % MOD] = 1; v[i][d[i]][d[i] % MOD] = 1; for (j = 0; j < 32; j++) { for (k = 0; k < MOD; k++) { if (f[i - 1][j][k]) { f[i][j][k] = 1; f[i][j ^ d[i]][(k * w[d[i]] + d[i]) % MOD] = true; v[i][j ^ d[i]][(k * w[d[i]] + d[i]) % MOD] = true; } } } } a = n; if (!f[a][b][c]) { puts( No ); return 0; } while (a) { if (!v[a][b][c]) a--; else { r++; p[r] = g[a]; b ^= d[a]; for (j = 0; j < MOD; j++) { if (f[a - 1][b][j] && (j * w[d[a]] + d[a]) % MOD == c) { c = j; break; } } a--; } } puts( Yes ); printf( %d n , r); for (i = r; i >= 1; i--) printf( %d , p[i]); puts( ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { int a, s, d; cin >> a >> s >> d; if (a > s) swap(a, s); if (a > d) swap(a, d); if (s > d) swap(s, d); if (s == d) { cout << YES << endl; cout << a << << a << << d << endl; } else { cout << NO << endl; } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module doImgProc_lineBuff_val_0_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 9;
parameter MEM_SIZE = 512;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module doImgProc_lineBuff_val_0(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd512;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
doImgProc_lineBuff_val_0_ram doImgProc_lineBuff_val_0_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// Filename: afi_mux.v
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// During calibration, mux_sel = 1, sequencer AFI signals are selected
// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
// ********************************************************************************************************************************
module ddr3_s4_uniphy_p0_afi_mux(
mux_sel,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
seq_mux_address,
seq_mux_bank,
seq_mux_cs_n,
seq_mux_cke,
seq_mux_odt,
seq_mux_ras_n,
seq_mux_cas_n,
seq_mux_we_n,
seq_mux_reset_n,
seq_mux_dqs_en,
seq_mux_wdata,
seq_mux_wdata_valid,
seq_mux_dm,
seq_mux_rdata_en,
mux_seq_rdata,
mux_seq_read_fifo_q,
mux_seq_rdata_valid,
mux_phy_address,
mux_phy_bank,
mux_phy_cs_n,
mux_phy_cke,
mux_phy_odt,
mux_phy_ras_n,
mux_phy_cas_n,
mux_phy_we_n,
mux_phy_reset_n,
mux_phy_dqs_en,
mux_phy_wdata,
mux_phy_wdata_valid,
mux_phy_dm,
mux_phy_rdata_en,
mux_phy_rdata_en_full,
phy_mux_rdata,
phy_mux_read_fifo_q,
phy_mux_rdata_valid
);
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
input mux_sel;
// AFI inputs from the controller
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
input afi_rdata_en;
input afi_rdata_en_full;
output [AFI_DATA_WIDTH-1:0] afi_rdata;
output afi_rdata_valid;
// AFI inputs from the sequencer
input [AFI_ADDRESS_WIDTH-1:0] seq_mux_address;
input [AFI_BANK_WIDTH-1:0] seq_mux_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke;
input [AFI_ODT_WIDTH-1:0] seq_mux_odt;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_reset_n;
input [AFI_DQS_WIDTH-1:0] seq_mux_dqs_en;
input [AFI_DATA_WIDTH-1:0] seq_mux_wdata;
input [AFI_DQS_WIDTH-1:0] seq_mux_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] seq_mux_dm;
input seq_mux_rdata_en;
output [AFI_DATA_WIDTH-1:0] mux_seq_rdata;
output [AFI_DATA_WIDTH-1:0] mux_seq_read_fifo_q;
output mux_seq_rdata_valid;
// Mux output to the rest of the PHY logic
output [AFI_ADDRESS_WIDTH-1:0] mux_phy_address;
output [AFI_BANK_WIDTH-1:0] mux_phy_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] mux_phy_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] mux_phy_cke;
output [AFI_ODT_WIDTH-1:0] mux_phy_odt;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_ras_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_cas_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_we_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_reset_n;
output [AFI_DQS_WIDTH-1:0] mux_phy_dqs_en;
output [AFI_DATA_WIDTH-1:0] mux_phy_wdata;
output [AFI_DQS_WIDTH-1:0] mux_phy_wdata_valid;
output [AFI_DATA_MASK_WIDTH-1:0] mux_phy_dm;
output mux_phy_rdata_en;
output mux_phy_rdata_en_full;
input [AFI_DATA_WIDTH-1:0] phy_mux_rdata;
input [AFI_DATA_WIDTH-1:0] phy_mux_read_fifo_q;
input phy_mux_rdata_valid;
assign afi_rdata = phy_mux_rdata;
assign afi_rdata_valid = mux_sel ? 1'b0 : phy_mux_rdata_valid;
assign mux_seq_rdata = phy_mux_rdata;
assign mux_seq_read_fifo_q = phy_mux_read_fifo_q;
assign mux_seq_rdata_valid = phy_mux_rdata_valid;
assign mux_phy_address = mux_sel ? seq_mux_address : afi_address;
assign mux_phy_bank = mux_sel ? seq_mux_bank : afi_bank;
assign mux_phy_cs_n = mux_sel ? seq_mux_cs_n : afi_cs_n;
assign mux_phy_cke = mux_sel ? seq_mux_cke : afi_cke;
assign mux_phy_odt = mux_sel ? seq_mux_odt : afi_odt;
assign mux_phy_ras_n = mux_sel ? seq_mux_ras_n : afi_ras_n;
assign mux_phy_cas_n = mux_sel ? seq_mux_cas_n : afi_cas_n;
assign mux_phy_we_n = mux_sel ? seq_mux_we_n : afi_we_n;
assign mux_phy_reset_n = mux_sel ? seq_mux_reset_n : afi_rst_n;
assign mux_phy_dqs_en = mux_sel ? seq_mux_dqs_en : afi_dqs_burst;
assign mux_phy_wdata = mux_sel ? seq_mux_wdata : afi_wdata;
assign mux_phy_wdata_valid = mux_sel ? seq_mux_wdata_valid : afi_wdata_valid;
assign mux_phy_dm = mux_sel ? seq_mux_dm : afi_dm;
assign mux_phy_rdata_en = mux_sel ? seq_mux_rdata_en : afi_rdata_en;
assign mux_phy_rdata_en_full = mux_sel ? seq_mux_rdata_en : afi_rdata_en_full;
endmodule
|
`default_nettype none
`define CLKFREQ 25000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_1_V
`define SKY130_FD_SC_HD__DFBBP_1_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog wrapper for dfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<pair<int, pair<int, int> > > E(m); { int cnt = 0; for (int i = 0; i < m; i++) { cin >> E[i].first >> E[i].second.first; E[i].second.second = i; if (E[i].second.first == 1) cnt++; E[i].second.first = 1 - E[i].second.first; } if (cnt != n - 1) { cout << -1 << endl; return 0; } } sort(E.begin(), E.end()); vector<pair<int, int> > res(m); queue<pair<int, int> > que; int latest = 1; for (int i = 0; i < m; i++) { if (E[i].second.first == 0) { res[E[i].second.second] = make_pair(latest, latest + 1); for (int u = 1; u < latest && que.size() < m; u++) que.push(make_pair(u, latest + 1)); latest++; } else { if (que.empty()) { cout << -1 << endl; return 0; } else { auto v = que.front(); que.pop(); res[E[i].second.second] = v; } } } for (int i = 0; i < m; i++) cout << res[i].first << << res[i].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int sub2(long long int n) { return (n + 3 * n * n) / 2; } int main() { long long int t; cin >> t; vector<long long int> ans; while (t--) { long long int k; cin >> k; long long int m = 0; while (k >= 2) { long long int i = floor((sqrt(1 + 24 * k) - 1) / 6.0); k = k - sub2(i); m++; } ans.push_back(m); } for (long long int k = 0; k < ans.size(); k++) cout << ans[k] << endl; return 0; }
|
#include <bits/stdc++.h> #define arr(i,n) for(ll i=0;i<n;i++) #define ARR(i,n) for(ll i=n-1;i>=0;i--) #define f(i,a,b) for(ll i=a;i<b;i++) #define F(i,a,b) for(ll i=b-1;i>=a;i--) #define float double #define PI 3.14159265358979323846 #define pb push_back #define mp make_pair #define vi vector<ll> #define ceil(a) (ll) ceil(a) #define floor(a) (ll) floor(a) #define pow(a,b) (ll) pow(a,b) #define fixed(x) cout<<fixed<<setprecision(6)<<x; #define vpii vector< pair<ll,ll> > #define debug(x) cout<<(#x)<< is <<(x)<<endl #define dbg(x,y) cout<<#x<< = <<x<< and <<#y<< = <<y<<endl #define gcd(a,b) __gcd(a,b) #define lcm(a,b) (a*(b/gcd(a,b))) #define all(v) v.begin(),v.end() #define array(a,n) arr(i,n) cout<<a[i]<< ; #define array2D(a,n,m) arr(i,n) {arr(j,m) cout<<a[i][j]<< ; cout<<endl;} #define IOS ios::sync_with_stdio(0); cin.tie(0); cout.tie(0) typedef long long ll; using namespace std; const ll mod = 1000000000 + 7; void solve() { //code start here ll n; cin>>n; n=2*n; ll a[n]; arr(i,n) cin>>a[i]; sort(a,a+n); ll start=0,end=n-1; arr(i,n) { if(i%2==0) {cout<<a[start]; start++;} else {cout<<a[end]; end--; } cout<< ; } cout<<endl; } int main() { IOS; int t; cin>>t; while(t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 8e3; void run_case(void) { int n; cin >> n; vector<int> x(n); for (int i = 0; i < n; i++) cin >> x[i]; int d = x[1] - x[0]; for (int i = 1; i < n - 1; i++) { if (x[i + 1] - x[i] != d) { cout << x[n - 1] << endl; return; } } cout << x[n - 1] + d << endl; } int main(void) { ios_base ::sync_with_stdio(false); cin.tie(NULL); run_case(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long add(long long a, long long b) { a += b; if (a >= 998244353) { a -= 998244353; } return a; } long long sub(long long a, long long b) { a -= b; if (a < 0) { a += 998244353; } return a; } long long mul(long long a, long long b) { return (a * b) % 998244353; } void add_self(long long& a, long long b) { a = add(a, b); } void sub_self(long long& a, long long b) { a = sub(a, b); } void mul_self(long long& a, long long b) { a = mul(a, b); } const long long MAXN = 200010; long long fpower(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { long long x, y; cin >> x >> y; cout << fpower(2, x + y, 998244353) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_4_V
`define SKY130_FD_SC_LS__O41A_4_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 110; const int memsize = 20000; struct Node { char val; int kill = 0; Node *failed = NULL; Node *pre = NULL; vector<Node *> child; Node() {} Node(char _val, Node *_pre) : val(_val), pre(_pre) {} int find_char(char c) { int i = 0; for (auto it = child.begin(); it != child.end(); it++) { if ((*it)->val == c) break; i++; } return i; } }; Node mem[memsize]; Node *root = mem; Node *pmem = mem; void str_insert(char *s) { int lenS = strlen(s); Node *cur = root; for (int i = 0; i < lenS; i++) { char c = s[i]; if (cur->find_char(c) == cur->child.size()) { Node *a = new (++pmem) Node(s[i], cur); if (i == lenS - 1) a->kill = lenS; (cur->child).push_back(a); cur = a; } else { cur = cur->child[cur->find_char(c)]; if (i == lenS - 1) cur->kill = lenS; } } } void build_fail() { queue<Node *> que; que.push(root); root->failed = root; while (!que.empty()) { Node *cur = que.front(); que.pop(); for (auto it = cur->child.begin(); it != cur->child.end(); it++) { Node *ptr = cur->failed; char c = (*it)->val; while (ptr != root && ptr->find_char(c) == ptr->child.size()) { ptr = ptr->failed; } (*it)->failed = ptr; if (ptr->find_char(c) != ptr->child.size()) { (*it)->failed = ptr->child[ptr->find_char(c)]; } if (cur == root) (*it)->failed = root; if (cur->kill == 0) cur->kill = cur->failed->kill; que.push(*it); } } } int change[N]; int cap[N]; void match(char *name) { int lenN = strlen(name); Node *cur = root; for (int i = 0; i < lenN; i++) { char c = name[i]; while (cur != root && cur->find_char(c) == cur->child.size()) { cur = cur->failed; } if (cur->find_char(c) != cur->child.size()) { cur = cur->child[cur->find_char(c)]; } change[i] = cur->kill; } } int main() { int n; scanf( %d , &n); char s[N]; while (n--) { scanf( %s , s); for (int i = 0; i < strlen(s); i++) { s[i] = tolower(s[i]); } str_insert(s); } build_fail(); char name[N]; scanf( %s , name); memset(change, 0, sizeof(change)); memset(cap, 0, sizeof(change)); for (int i = 0; i < strlen(name); i++) { if (name[i] == toupper(name[i])) cap[i] = 1; name[i] = tolower(name[i]); } char letter; scanf( %c , &letter); match(name); int rc[N]; memset(rc, 0, sizeof(rc)); for (int i = 0; i < strlen(name); i++) { int num = change[i]; while (num--) { rc[i - num] = 1; } } for (int i = 0; i < strlen(name); i++) { if (rc[i] == 1) { if (name[i] == letter) { name[i] = (letter == a ) ? b : a ; } else { name[i] = letter; } } } for (int i = 0; i < strlen(name); i++) { if (cap[i] == 1) { printf( %c , toupper(name[i])); } else { printf( %c , tolower(name[i])); } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; int a[10000], b[10000]; for (int n = 0; n < N; n++) { cout << ? << 0 << << n << endl; cin >> a[n]; } for (int n = 0; n < N; n++) { cout << ? << n << << 0 << endl; cin >> b[n]; } int nm = 0, fa = 0; int ac[10000], bc[10000]; for (int n = 0; n < N; n++) { for (int x = 0; x < N; x++) { ac[x] = a[x] ^ n; } for (int x = 0; x < N; x++) { bc[x] = b[x] ^ ac[0]; } bool p = true; for (int x = 0; x < N; x++) { if (ac[bc[x]] != x) { p = false; } } if (p) { fa = n; nm++; } } cout << ! << endl; cout << nm << endl; fa = fa ^ a[0]; for (int x = 0; x < N; x++) { if (x) cout << ; cout << (fa ^ b[x]); } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int c[110]; int main() { int n, i, x, y, j; cin >> n; for (i = 0; i < n; i++) { cin >> x; for (j = 0; j < x; j++) { cin >> y; c[y]++; if (c[y] == n) { cout << y << ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200000 + 10; int num[maxn], ans; void Solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , num + i); sort(num + 1, num + 1 + n); int nn = unique(num + 1, num + 1 + n) - (num + 1); for (int i = 1; i <= nn; i++) { int j = num[i] << 1; int pos = lower_bound(num + 1, num + 1 + nn, j) - num; while (num[pos - 1] < j && pos <= nn) { ans = max(ans, num[pos - 1] % num[i]); pos = lower_bound(num + pos + 1, num + 1 + nn, j) - num; j += num[i]; } ans = max(ans, num[pos - 1] % num[i]); } printf( %d , ans); } int main() { Solve(); getchar(); getchar(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int a[1005], b[1005]; int x[1005], y[1005]; int main() { int n; while (scanf( %d , &n) != EOF) { memset(x, 0, sizeof(x)); memset(y, 0, sizeof(y)); for (int i = 0; i < n; ++i) { scanf( %d%d , &a[i], &b[i]); x[a[i]]++; y[b[i]]++; } int sum = 0; for (int i = 0; i < n; ++i) { if (x[b[i]]) { if (a[i] != b[i]) { sum += x[b[i]]; x[b[i]] = 0; } else if (y[a[i]] > 1) { sum += x[b[i]]; x[b[i]] = 0; } else if (x[b[i]] > 1) { sum += x[b[i]] - 1; x[b[i]] = 1; } } } printf( %d n , n - sum); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int k[10] = {2, 7, 2, 3, 3, 4, 2, 5, 1, 2}; int main(void) { int n; scanf( %d , &n); int x = n / 10, y = n % 10; printf( %d n , k[x] * k[y]); }
|
#include <bits/stdc++.h> int main() { unsigned short x; std::cin >> x; (x > 1) ? std::cout << x << << x : std::cout << -1; }
|
`timescale 1ns / 1ps
//-----------------------------------------------------
// Design Name : syn_fifo
// File Name : syn_fifo.v
// Function : Synchronous (single clock) FIFO
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module syn_fifo (
clk , // Clock input
rst , // Active high reset
wr_cs , // Write chip select
rd_cs , // Read chipe select
data_in , // Data input
rd_en , // Read enable
wr_en , // Write Enable
data_out , // Data Output
empty , // FIFO empty
full // FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk ;
input rst ;
input wr_cs ;
input rd_cs ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output empty ;
output [DATA_WIDTH-1:0] data_out ;
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] data_out ;
wire [DATA_WIDTH-1:0] data_ram ;
//-----------Variable assignments---------------
assign full = (status_cnt == (RAM_DEPTH-1));
assign empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @ (posedge clk or posedge rst)
begin : WRITE_POINTER
if (rst) begin
wr_pointer <= 0;
end else if (wr_cs && wr_en ) begin
wr_pointer <= wr_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_POINTER
if (rst) begin
rd_pointer <= 0;
end else if (rd_cs && rd_en ) begin
rd_pointer <= rd_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_DATA
if (rst) begin
data_out <= 0;
end else if (rd_cs && rd_en ) begin
data_out <= data_ram;
end
end
always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
if (rst) begin
status_cnt <= 0;
// Read but no write.
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
&& (status_cnt != 0)) begin
status_cnt <= status_cnt - 1;
// Write but no read.
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
&& (status_cnt != RAM_DEPTH)) begin
status_cnt <= status_cnt + 1;
end
end
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
.address_0 (wr_pointer) , // address_0 input
.data_0 (data_in) , // data_0 bi-directional
.cs_0 (wr_cs) , // chip select
.we_0 (wr_en) , // write enable
.oe_0 (1'b0) , // output enable
.address_1 (rd_pointer) , // address_q input
.data_1 (data_ram) , // data_1 bi-directional
.cs_1 (rd_cs) , // chip select
.we_1 (1'b0) , // Read enable
.oe_1 (rd_en) // output enable
);
endmodule
|
/*
Teak synthesiser for the Balsa language
Copyright (C) 2007-2010 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Andrew Bardsley <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
/*
st65-mapping.v : Teak tech mapping for ST 65nm library
*/
/*
HS65_LS_AND2X4 (Z, A, B, C);
HS65_LS_AND3X4 (Z, A, B, C);
HS65_LS_AO222X4 (Z, A, B, C, D, E, F);
HS65_LS_AO22X4 (Z, A, B, C, D);
HS65_LS_BFX2 (Z, A);
HS65_LS_IVX2 (Z, A);
HS65_LS_NAND2X2 (Z, A, B);
HS65_LS_NAND3X2 (Z, A, B, C);
HS65_LS_NOR2X2 (Z, A, B);
HS65_LS_NOR3X1 (Z, A, B, C);
HS65_LS_OR2X4 (Z, A, B);
HS65_LS_OR3X4 (Z, A, B, C);
HS65_LS_PAO2X4 (Z, A, B, P);
HS65_LS_PAO3X4 (Z, A, B, C, P);
*/
// tkg_{and,or,nand,nor}[23] : 2/3 input AND/OR/NAND/NOR gates
module tkg_and2 (output o, input i0, i1);
HS65_LS_AND2X4 I0 (o, i0, i1);
endmodule
module tkg_and3 (output o, input i0, i1, i2);
HS65_LS_AND3X4 I0 (o, i0, i1, i2);
endmodule
module tkg_or2 (output o, input i0, i1);
HS65_LS_OR2X4 I0 (o, i0, i1);
endmodule
module tkg_or3 (output o, input i0, i1, i2);
HS65_LS_OR3X4 I0 (o, i0, i1, i2);
endmodule
module tkg_nand2 (output o, input i0, i1);
HS65_LS_NAND2X2 I0 (o, i0, i1);
endmodule
module tkg_nand3 (output o, input i0, i1, i2);
HS65_LS_NAND3X2 I0 (o, i0, i1, i2);
endmodule
module tkg_nor2 (output o, input i0, i1);
HS65_LS_NOR2X2 I0 (o, i0, i1);
endmodule
module tkg_nor3 (output o, input i0, i1, i2);
HS65_LS_NOR3X1 I0 (o, i0, i1, i2);
endmodule
// tkg_c[23] : 2/3 input symmetric C-elements
module tkg_c2 (output o, input i0, i1);
HS65_LS_PAO2X4 I0 (o, i0, i1, o);
endmodule
module tkg_c3 (output o, input i0, i1, i2);
HS65_LS_PAO3X4 I0 (o, i0, i1, i2, o);
endmodule
// tkg_c2r1 : 2 input symmetric C-element with active high reset
module tkg_c2r1 (output o, input i0, i1, r);
// tkg_FIXME
endmodule
// tkg_c1u1 : asymmetric C-element with one 'symmetric' and one 'up' input
module tkg_c1u1 (output o, input s0, u0);
HS65_LS_AO22X1 I0 (o, s0, u0, s0, o);
endmodule
// tkg_ao22 : AND-OR-22. o = i0&i1 | i2&i3
module tkg_ao22 (output o, input i0, i1, i2, i3);
HS65_LS_AO22X1 I0 (o, i0, i1, i2, i3);
endmodule
// tkg_ao222 : AND-OR-222. o = i0&i1 | i2&i3 | i4&i5
module tkg_ao222 (output o, input i0, i1, i2, i3, i4, i5);
HS65_LS_AO222X2 I0 (o, i0, i1, i2, i3, i4, i5);
endmodule
// tkg_gnd : logic 0 connection
module tkg_gnd (output o);
// tkg_FIXME
HS65_LS_GND I0 (o);
endmodule
// tkg_inv : inverter
module tkg_inv (output o, input i);
HS65_LS_IVX2 I0 (o, i);
endmodule
// tkg_buff : non-inverting logical buffer
module tkg_buff (output o, input i);
HS65_LS_BFX2 I0 (o, i);
endmodule
// tkg_mutex : mutual exclusion element. ag&bg is never true.
module tkg_mutex (input ar, br, output ag, bg);
// tkg_FIXME
MUTEX I0 (ar, br, ag, bg);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool visited[100005] = {0}; vector<int> v[100005]; int color[100005]; int dfs(int s) { int result = 0; visited[s] = 1; for (int i = 0; i < v[s].size(); i++) { if (!visited[v[s][i]]) { if (color[v[s][i]] != color[s]) result += (1 + dfs(v[s][i])); else result += dfs(v[s][i]); } } return result; } int main() { int n; cin >> n; for (int i = 0; i < 100005; i++) visited[i] = 0; for (int i = 2; i <= n; i++) { int a; cin >> a; v[i].push_back(a); v[a].push_back(i); } for (int i = 0; i < n; i++) { cin >> color[i + 1]; } cout << (1 + dfs(1)) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int a1, b1, a2, b2; int main() { scanf( %lld %lld , &a1, &b1); scanf( %lld %lld , &a2, &b2); long long int p, q, ans = 0; p = (a1 * b1); q = (a2 * b2); long long int tp = 0, tq = 0, thp = 0, thq = 0; while ((p % 3) == 0) { p = (p / 3); thp++; } while ((q % 3) == 0) { q = (q / 3); thq++; } while ((p % 2) == 0) { p = (p / 2); tp++; } while ((q % 2) == 0) { q = (q / 2); tq++; } p = (a1 * b1); q = (a2 * b2); long long int x; if (thp > thq) { tp = tp + (thp - thq); ans = ans + (thp - thq); x = (thp - thq); while (x--) { if ((a1 % 3) == 0) a1 = ((a1 / 3) * 2); else b1 = ((b1 / 3) * 2); } } else if (thq > thp) { tq = tq + (thq - thp); ans = ans + (thq - thp); x = (thq - thp); while (x--) { if ((a2 % 3) == 0) a2 = ((a2 / 3) * 2); else b2 = ((b2 / 3) * 2); } } if (tp > tq) { ans = ans + (tp - tq); x = (tp - tq); while (x--) { if ((a1 % 2) == 0) a1 = (a1 / 2); else b1 = (b1 / 2); } } else { ans = ans + (tq - tp); x = (tq - tp); while (x--) { if ((a2 % 2) == 0) a2 = (a2 / 2); else b2 = (b2 / 2); } } if ((a1 * b1) == (a2 * b2)) { printf( %lld n , ans); printf( %lld %lld n , a1, b1); printf( %lld %lld n , a2, b2); } else printf( -1 n ); return 0; }
|
// header_detector.v
module header_detector
(
input clk,
input reset,
input [1:0]din,
output reg davail,
output reg [3:0]dout,
output reg tbm_hdr,
output reg tbm_trl,
output reg roc_hdr
);
reg [4:0]timeout;
wire active = timeout[4];
// --- data path -----------------------------------------------
reg [1:0]d0;
reg [1:0]d1;
reg [1:0]d2;
reg [1:0]d3;
reg [1:0]d4;
reg [1:0]d5;
reg mode1; // header detection mode
reg mode; // data mode
wire [2:0]id = mode1 ? {d1, d0[1]} : {d2[0], d1};
wire [3:0]data = mode ? {d2[0], d1, d0[1]} : {d2, d1};
always @(posedge clk or posedge reset)
begin
if (reset)
begin
{d5, d4, d3, d2, d1, d0} <= 10'h3ff;
dout <= 0;
end
else
begin
{d5, d4, d3, d2, d1, d0} <= {d4, d3, d2, d1, d0, din};
dout <= data;
end
end
// --- leader detection --------------------------------------
wire leader0 = {d5, d4, d3, d2, d1[1]} == 9'b011111111;
wire leader1 = {d5[0], d4, d3, d2, d1} == 9'b011111111;
reg leader;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
leader <= 0;
mode1 <= 0;
end
else
begin
if (active)
begin
if (leader0)
begin
leader <= 1;
mode1 <= 0;
end
else if (leader1)
begin
leader <= 1;
mode1 <= 1;
end
else
begin
leader <= 0;
end
end
end
end
// --- header identification ---------------------------------
always @(posedge clk or posedge reset)
begin
if (reset)
begin
davail <= 0;
tbm_hdr <= 0;
tbm_trl <= 0;
roc_hdr <= 0;
mode <= 0;
timeout <= 0;
end
else
begin // not reset
if (active && leader)
begin
casez (id)
3'b100: // TBM Header
begin
tbm_hdr <= 1;
timeout <= 4;
mode <= mode1;
davail <= 1;
end
3'b110: // TBM Trailer
begin
tbm_trl <= 1;
timeout <= 4;
mode <= mode1;
davail <= 1;
end
3'b0??: // ROC Header
begin
roc_hdr <= 1;
mode <= mode1;
davail <= 1;
end
default: davail <= !davail;
endcase
end // if active & leader
else
begin
tbm_trl <= 0;
tbm_hdr <= 0;
roc_hdr <= 0;
davail <= !davail;
end
if (!active) timeout <= timeout + 5'd1;
end // not reset
end // always
endmodule
|
`include "defines.vh"
module divrem #(
parameter WIDTH_LOG = 4
) (clk, go, rst, num, den, ready, error, quot, rem);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
input [HI:0] num;
input [HI:0] den;
output reg ready;
output reg error;
output reg [HI:0] quot;
output reg [HI:0] rem;
localparam XW = {WIDTH{1'bx}};
localparam X7 = 7'bx;
localparam READY = 2'd0;
localparam SUBTRACT = 2'd1;
localparam ERROR = 2'd2;
reg [1:0] next_state;
reg [HI:0] next_quot;
reg [HI:0] next_rem;
wire next_ready;
wire next_error;
reg [1:0] state;
wire [HI:0] a;
wire [HI:0] sub;
wire [WIDTH_LOG - 1:0] rem_msb;
wire [WIDTH_LOG - 1:0] den_msb;
wire [WIDTH_LOG - 1:0] shift;
// TODO: pipeline this to increase freq?
prio_enc #(.WIDTH_LOG(WIDTH_LOG)) num_pe(.x(a), .msb(rem_msb));
prio_enc #(.WIDTH_LOG(WIDTH_LOG)) den_pe(.x(den), .msb(den_msb));
assign a = state == READY || state == ERROR ? num : rem;
assign shift = rem_msb > den_msb ? (rem_msb - den_msb - 1'b1) : 1'b0;
assign sub = den << shift;
assign next_ready = next_state == READY || next_state == ERROR;
assign next_error = next_state == ERROR;
always @* begin
next_state = state;
next_quot = quot;
next_rem = rem;
case (state)
READY, ERROR:
if (go) begin
if (den == 0) begin
next_state = ERROR;
next_quot = XW;
next_rem = XW;
end else begin
next_state = SUBTRACT;
next_quot = 0;
next_rem = num;
end
end else begin
// Stay in READY and do nothing
end
SUBTRACT:
if (sub <= rem) begin
next_quot = quot + (1'd1 << shift);
next_rem = rem - sub;
end else begin
next_state = READY;
end
endcase
end
always @(posedge clk)
if (rst) begin
// TODO: is it a good practice to explicitly undefine everything?
state <= READY;
quot <= XW;
rem <= XW;
ready <= 1;
error <= 0;
end else begin
state <= next_state;
quot <= next_quot;
rem <= next_rem;
ready <= next_ready;
error <= next_error;
end
`ifdef SIM
reg [HI:0] ready_prev;
reg [HI:0] go_r;
reg [HI:0] go_prev;
reg [HI:0] num_prev;
reg [HI:0] den_prev;
always @(posedge clk) begin
ready_prev <= ready;
go_r <= go;
go_prev <= go_r;
num_prev <= num;
den_prev <= den;
// Precondition: core signals must always be valid
`assert_nox(rst);
`assert_nox(clk);
if (!rst) begin
// Precondition: if 'go' is asserted, other inputs are valid
if (go) begin
`assert_nox(num);
`assert_nox(den);
end
// Precondition: inputs are stable until computation is over
if (!ready) begin
`assert_eq(num, num_prev);
`assert_eq(den, den_prev);
end
// Precondition: 'go' is not re-asserted until computation is finished
// (this won't be a bug but would be ignored and is likely to indicate
// incorrect usage of module).
if (!ready)
`assert(!(go && !go_prev));
// Invariant: priority encoder produces defined results
if (!`isunknown(den))
`assert_nox(den_msb);
if (!`isunknown(rem))
`assert_nox(rem_msb);
// Postcondition: outputs are correct
if (ready && !ready_prev && !error) begin
`assert_lt(rem, den);
`assert_eq(den*quot + rem, num);
end
end
end
`endif
`ifdef SIM
// initial
// $monitor("%t: go=%h, num=%0d, den=%0d, quot=%h, rem=%0d, a=%0d, state=%h, rem_msb=%h, den_msb=%h, sub=%0d, shift=%h, ready=%h", $time, go, num, den, quot, rem, a, state, rem_msb, den_msb, sub, shift, ready);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c; cin >> a >> b >> c; vector<long> v; for (int i = 1; i <= 81; i++) { long long sum = i; for (int j = 2; j <= a; j++) sum *= i; sum *= b; sum += c; if (sum > 0 && sum < 1000000000) { long long cn = sum, cnt = 0; while (cn) { cnt += cn % 10; cn /= 10; } if (cnt == i) v.push_back(sum); } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i] << ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
|
/*
* Check that the initial value can be out of range and that the next()/prev()
* enumeration methods do not change to a defined state.
*/
module top;
reg pass;
enum bit [3:0] {a2 = 1, b2 = 2, c2 = 3, d2 = 4} evar2;
enum reg [3:0] {a4 = 1, b4 = 2, c4 = 3, d4 = 4} evar4;
initial begin
pass = 1'b1;
if (evar2 !== 0) begin
$display("Failed initial/2 value should be 0, got %d", evar2);
pass = 1'b0;
end
if (evar4 !== 4'bx) begin
$display("Failed initial/4 value should be 'bx, got %d", evar4);
pass = 1'b0;
end
evar2 = evar2.next;
if (evar2 !== 0) begin
$display("Failed next/2 of an invalid value should be 0, got %d", evar2);
pass = 1'b0;
end
evar4 = evar4.next;
if (evar4 !== 4'bx) begin
$display("Failed next/4 of an invalid value should be 0, got %d", evar4);
pass = 1'b0;
end
evar2 = evar2.prev;
if (evar2 !== 0) begin
$display("Failed prev/2 of an invalid value should be 0, got %d", evar2);
pass = 1'b0;
end
evar4 = evar4.prev;
if (evar4 !== 4'bx) begin
$display("Failed prev/4 of an invalid value should be 0, got %d", evar4);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_TB_V
`define SKY130_FD_SC_HD__MUX2I_TB_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_hd__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; ++i) { cin >> arr[i]; } for (int j = 0; j < n; ++j) { if (arr[j] == 0) if (j == (n - 1)) cout << EASY << endl; else continue; else { cout << HARD << endl; break; } } return 0; };
|
#include <bits/stdc++.h> using namespace std; char buf[2000]; int dx[4] = {0, 0, -1, 1}; int dy[4] = {-1, 1, 0, 0}; int n, m; pair<int, int> tbl1[1 << 23]; pair<int, int> tbl2[1 << 23]; const int Prime1 = 262139, Prime2 = 40999999; const int Prime3 = 100003, Prime4 = 40999799; const pair<int, int> ZERO = make_pair(0, 0); bool ex(int x, int y) { int t1 = x * Prime1 + y * Prime2; int t2 = x * Prime3 + y * Prime4; t1 = abs(t1); t1 %= ((1 << 23) - 1); t2 = abs(t2); t2 %= ((1 << 23) - 1); while (tbl1[t1] != ZERO && tbl1[t1] != make_pair(x, y)) t1 = (t1 + 1) % (1 << 23); if (tbl1[t1] == make_pair(x, y)) return false; tbl2[t2] = tbl1[t1] = make_pair(x, y); return true; } int main() { cin >> n >> m; vector<string> a; for (int i = (0); i < (n); ++i) { string s; scanf( %s , buf); s = buf; a.push_back(s); } pair<int, int> start; for (int i = (0); i < (n); ++i) { for (int j = (0); j < (m); ++j) if (a[i][j] == S ) start = make_pair(i, j); } queue<pair<int, int> > q; q.push(start); ex(start.first, start.second); int k = 0; while (!q.empty()) { if (k > n * m) { cout << Yes n ; return 0; } pair<int, int> v = q.front(); q.pop(); for (int i = (0); i < (4); ++i) { int x = v.first + dx[i]; int y = v.second + dy[i]; int _x = (x % n + n) % n; int _y = (y % m + m) % m; if (a[_x][_y] != # && ex(x, y)) { k++; q.push(make_pair(x, y)); } } } cout << No n ; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_TB_V
`define SKY130_FD_SC_MS__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_TB_V
|
import env;
concept SQLite
{
mandatory abstract feature Parameters {
//This macro determines if SQLite creates databases with the auto_vacuum flag set by default to OFF (0), FULL (1), or INCREMENTAL (2). The default value is 0 meaning that databases are created with auto-vacuum turned off. In any case the compile-time default may be overridden by the PRAGMA auto_vacuum command.
//<0 or 1 or 2>
int SQLITE_DEFAULT_AUTOVACUUM=0;
//This macro sets the default size of the page-cache for each attached database, in pages. This can be overridden by the PRAGMA cache_size command. The default value is 2000.
//<pages>
int SQLITE_DEFAULT_CACHE_SIZE=2000;
//The default schema-level file format used by SQLite when creating new database files is set by this macro. The file formats are all very similar. The difference between formats 1 and 4 is that format 4 understands descending indices and has a tighter encoding for boolean values.
//SQLite (as of version 3.6.0) can read and write any file format between 1 and 4. But older versions of SQLite might not be able to read formats greater than 1. So that older versions of SQLite will be able to read and write database files created by newer versions of SQLite, the default file format is set to 1 for maximum compatibility.
//The file format for a new database can be set at runtime using the PRAGMA legacy_file_format command.
//<1 or 4>
int SQLITE_DEFAULT_FILE_FORMAT=1;
//This macro determines whether enforcement of foreign key constraints is enabled or disabled by default for new database connections. Each database connection can always turn enforcement of foreign key constraints on and off and run-time using the foreign_keys pragma. Enforcement of foreign key constraints is normally off by default, but if this compile-time parameter is set to 1, enforcement of foreign key constraints will be on by default.
//<0 or 1>
int SQLITE_DEFAULT_FOREIGN_KEYS=0;
//This option sets the size limit on rollback journal files in persistent journal mode. When this compile-time option is omitted there is no upper bound on the size of the rollback journal file. The journal file size limit can be changed at run-time using the journal_size_limit pragma.
//<bytes>
int SQLITE_DEFAULT_JOURNAL_SIZE_LIMIT=0; //0xFFFFFFFF;
//This macro is used to determine whether or not the features enabled and disabled using the SQLITE_CONFIG_MEMSTATUS argument to sqlite3_config() are available by default. The default value is 1 (SQLITE_CONFIG_MEMSTATUS related features enabled).
//<1 or 0>
int SQLITE_DEFAULT_MEMSTATUS=1;
//This macro is used to set the default page-size used when a database is created. The value assigned must be a power of 2. The default value is 1024. The compile-time default may be overridden at runtime by the PRAGMA page_size command.
//<bytes> (power of 2)
int SQLITE_DEFAULT_PAGE_SIZE=1024;
//This macro sets the default size of the page-cache for temporary files created by SQLite to store intermediate results, in pages. It does not affect the page-cache for the temp database, where tables created using CREATE TEMP TABLE are stored. The default value is 500.
//<pages>
int SQLITE_DEFAULT_TEMP_CACHE_SIZE=500;
//This macro sets the default page count for the WAL automatic checkpointing feature. If unspecified, the default page count is 1000.
//<pages>
int SQLITE_DEFAULT_WAL_AUTOCHECKPOINT=1000;
//This macro sets the maximum depth of the LALR(1) stack used by the SQL parser within SQLite. The default value is 100. A typical application will use less than about 20 levels of the stack. Developers whose applications contain SQL statements that need more than 100 LALR(1) stack entries should seriously consider refactoring their SQL as it is likely to be well beyond the ability of any human to comprehend.
//<max_depth>
int YYSTACKDEPTH=100;
}
mandatory abstract feature EnableFeatures
{
feature SQLITE_ENABLE_FTS3_PARENTHESIS;
feature SQLITE_ENABLE_FTS3;
feature SQLITE_ENABLE_COLUMN_METADATA;
feature SQLITE_ENABLE_ATOMIC_WRITE;
feature YYTRACKMAXSTACKDEPTH;
feature SQLITE_SOUNDEX;
feature SQLITE_ENABLE_UNLOCK_NOTIFY;
feature SQLITE_ENABLE_UPDATE_DELETE_LIMIT;
feature SQLITE_ENABLE_STAT2;
feature SQLITE_ENABLE_RTREE;
abstract feature ChooseMemSys
{
someof {
feature SQLITE_ENABLE_MEMSYS3;
feature SQLITE_ENABLE_MEMSYS5;
}
} //ChooseMemSys
feature SQLITE_ENABLE_MEMORY_MANAGEMENT;
feature SQLITE_ENABLE_ICU;
} //EnableFeatures
mandatory abstract feature OperatingCharacteristics
{
//On most systems, the malloc() system call returns a buffer that is aligned to an 8-byte boundary. But on some systems (ex: windows) malloc() returns 4-byte aligned pointer. This compile-time option must be used on systems that return 4-byte aligned pointers from malloc().
mandatory feature SQLITE_4_BYTE_ALIGNED_MALLOC;
//This compile-time option changes the default setting of the secure_delete pragma. When this option is not used, secure_delete defaults to off. When this option is present, secure_delete defaults to on.
//The secure_delete setting causes deleted content to be overwritten with zeros. There is a small performance penalty for this since additional I/O must occur. On the other hand, secure_delete can prevent sensitive information from lingering in unused parts of the database file after it has allegedly been deleted. See the documentation on the secure_delete pragma for additional information.
feature SQLITE_SECURE_DELETE;
//The option causes SQLite to omit its built-in operating system interfaces for Unix, Windows, and OS/2. The resulting library will have no default operating system interface. Applications must use sqlite3_vfs_register() to register an appropriate interface before using SQLite. Applications must also supply implementations for the sqlite3_os_init() and sqlite3_os_end() interfaces. The usual practice is for the supplied sqlite3_os_init() to invoke sqlite3_vfs_register(). SQLite will automatically invoke sqlite3_os_init() when it initializes.
//This option is typically used when building SQLite for an embedded platform with a custom operating system.
//<0 or 1>
int SQLITE_OS_OTHER=0;
//If this option is present, then SQLite will use the isnan() function from the system math library. Without this option (the default behavior) SQLite uses its own internal implementation of isnan(). SQLite uses its own internal isnan() implementation by default because of past problems with system isnan() functions.
feature SQLITE_HAVE_ISNAN;
//If this option is present, then the built-in LIKE operator will be case sensitive. This same effect can be achieved at run-time using the case_sensitive_like pragma.
feature SQLITE_CASE_SENSITIVE_LIKE;
/*
This option controls whether or not code is included in SQLite to enable it to operate safely in a multithreaded environment. The default is SQLITE_THREADSAFE=1 which is safe for use in a multithreaded environment. When compiled with SQLITE_THREADSAFE=0 all mutexing code is omitted and it is unsafe to use SQLite in a multithreaded program. When compiled with SQLITE_THREADSAFE=2, SQLite can be used in a multithreaded program so long as no two threads attempt to use the same database connection at the same time.
To put it another way, SQLITE_THREADSAFE=1 sets the default threading mode to Serialized. SQLITE_THREADSAFE=2 sets the default threading mode to Multi-threaded. And SQLITE_THREADSAFE=0 sets the threading mode to Single-threaded.
The value of SQLITE_THREADSAFE can be determined at run-time using the sqlite3_threadsafe() interface.
When SQLite has been compiled with SQLITE_THREADSAFE=1 or SQLITE_THREADSAFE=2 then the threading mode can be altered at run-time using the sqlite3_config() interface together with one of these verbs:
SQLITE_CONFIG_SINGLETHREAD
SQLITE_CONFIG_MULTITHREAD
SQLITE_CONFIG_SERIALIZED
The SQLITE_OPEN_NOMUTEX and SQLITE_OPEN_FULLMUTEX flags to sqlite3_open_v2() can also be used to adjust the threading mode of individual database connections at run-time.
Note that when SQLite is compiled with SQLITE_THREADSAFE=0, the code to make SQLite threadsafe is omitted from the build. When this occurs, it is impossible to change the threading mode at start-time or run-time.
See the threading mode documentation for additional information on aspects of using SQLite in a multithreaded environment.
<0 or 1 or 2>
*/
int SQLITE_THREADSAFE=1;
/*
This option controls whether temporary files are stored on disk or in memory. The meanings for various settings of this compile-time option are as follows:
SQLITE_TEMP_STORE Meaning
0 Always use temporary files
1 Use files by default but allow the PRAGMA temp_store command to override
2 Use memory by default but allow the PRAGMA temp_store command to override
3 Always use memory
The default setting is 1. Additional information can be found in tempfiles.html.
<0..3>
*/
int SQLITE_TEMP_STORE=1;
} //OperatingCharacteristics
mandatory abstract feature OmitFeatures
{
feature SQLITE_OMIT_ALTERTABLE;
feature SQLITE_OMIT_COMPOUND_SELECT;
feature SQLITE_OMIT_COMPLETE;
feature SQLITE_OMIT_COMPILEOPTION_DIAGS;
feature SQLITE_OMIT_CHECK;
feature SQLITE_OMIT_CAST;
feature SQLITE_OMIT_BUILTIN_TEST;
feature SQLITE_OMIT_BTREECOUNT;
feature SQLITE_OMIT_BLOB_LITERAL;
feature SQLITE_OMIT_BETWEEN_OPTIMIZATION;
feature SQLITE_OMIT_AUTOVACUUM;
feature SQLITE_OMIT_AUTOINIT;
feature SQLITE_OMIT_AUTOMATIC_INDEX;
feature SQLITE_OMIT_AUTOINCREMENT;
feature SQLITE_OMIT_AUTHORIZATION;
feature SQLITE_OMIT_ATTACH;
feature SQLITE_OMIT_ANALYZE;
feature SQLITE_OMIT_LOOKASIDE;
feature SQLITE_OMIT_LOCALTIME;
feature SQLITE_OMIT_LOAD_EXTENSION;
feature SQLITE_OMIT_LIKE_OPTIMIZATION;
feature SQLITE_OMIT_INTEGRITY_CHECK;
feature SQLITE_OMIT_INCRBLOB;
feature SQLITE_OMIT_GET_TABLE;
feature SQLITE_OMIT_FOREIGN_KEY;
feature SQLITE_OMIT_FLOATING_POINT;
feature SQLITE_OMIT_FLAG_PRAGMAS;
feature SQLITE_OMIT_EXPLAIN;
feature SQLITE_OMIT_DISKIO;
feature SQLITE_OMIT_DEPRECATED;
feature SQLITE_OMIT_DECLTYPE;
feature SQLITE_OMIT_DATETIME_FUNCS;
feature SQLITE_OMIT_CONFLICT_CLAUSE;
feature SQLITE_OMIT_TRUNCATE_OPTIMIZATION;
feature SQLITE_OMIT_TRIGGER;
feature SQLITE_OMIT_TRACE;
feature SQLITE_OMIT_TEMPDB;
feature SQLITE_OMIT_TCL_VARIABLE;
feature SQLITE_OMIT_SUBQUERY;
feature SQLITE_OMIT_SHARED_CACHE;
feature SQLITE_OMIT_SCHEMA_VERSION_PRAGMAS;
feature SQLITE_OMIT_SCHEMA_PRAGMAS;
feature SQLITE_OMIT_REINDEX;
feature SQLITE_OMIT_QUICKBALANCE;
feature SQLITE_OMIT_PROGRESS_CALLBACK;
feature SQLITE_OMIT_PRAGMA;
feature SQLITE_OMIT_PAGER_PRAGMAS;
feature SQLITE_OMIT_OR_OPTIMIZATION;
feature SQLITE_OMIT_MEMORYDB;
feature SQLITE_OMIT_XFER_OPT;
feature SQLITE_OMIT_WSD;
feature SQLITE_OMIT_WAL;
feature SQLITE_OMIT_VIRTUALTABLE;
feature SQLITE_OMIT_VIEW;
feature SQLITE_OMIT_VACUUM;
feature SQLITE_OMIT_UTF16;
} //OmitFeatures
mandatory abstract feature DisableFeatures
{
feature SQLITE_DISABLE_DIRSYNC;
feature SQLITE_DISABLE_LFS;
} //DisableFeatures
mandatory abstract feature Debug
{
feature SQLITE_MEMDEBUG;
feature SQLITE_DEBUG;
}
} //SQLite
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long n, a[1005]; map<long long, int> x; int ans; void f(long long a, long long b) { long long cur = a + b; vector<long long> q; q.push_back(a); q.push_back(b); int len = 2; x[a]--; x[b]--; while (x[cur] > 0) { x[cur]--; q.push_back(cur); a = b; b = cur; cur = a + b; len++; } ans = max(len, ans); for (int i = 0; i < q.size(); i++) x[q[i]]++; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; x[a[i]]++; } ans = x[0]; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (a[i] == a[j] && a[i] == 0) continue; f(a[i], a[j]); f(a[j], a[i]); } } cout << ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_1_V
`define SKY130_FD_SC_HS__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfsbp_1 (
CLK ,
D ,
Q ,
Q_N ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfsbp_1 (
CLK ,
D ,
Q ,
Q_N ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_1_V
|
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