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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 09:37:07 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, srst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input srst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, 1, -1, -1}; int dy[] = {1, -1, -1, 1}; long long int n, k, d1, d2, rem; bool _solve(long long int w1, long long int w2, long long int w3) { long long int tar = n / 3; if (w1 < 0 || w2 < 0 || w3 < 0) return false; if (tar >= w1 && tar >= w2 && tar >= w3 && abs(w1 - w2) == d1 && abs(w2 - w3) == d2) return true; return false; } bool solve() { long long int _d1, w1, w2, w3, _d2; for (int i = 0; i < 4; i++) { _d1 = d1 * dx[i]; _d2 = d2 * dy[i]; w1 = (k + 2 * _d1 + _d2) / 3; w2 = w1 - _d1; w3 = w2 - _d2; if (w1 + w2 + w3 != k) continue; if (_solve(w1, w2, w3)) return true; } return false; } int main() { ios_base ::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> k >> d1 >> d2; if (n % 3 == 0) { if (solve()) cout << yes << endl; else cout << no << endl; } else cout << no << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, sav, mn = 1e9; struct point { long long x, y, uz; } p[2005]; string s; int det(point A, point B, point C) { if (A.x * B.y + A.y * C.x + B.x * C.y - A.x * C.y - A.y * B.x - B.y * C.x < 0) return -1; return 1; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i].x >> p[i].y; if (p[i].y < mn) { mn = p[i].y; sav = i; } } cin >> s; p[sav].uz = 1; cout << sav << ; for (int i = 0; i < s.size(); i++) { int crt = 1, j, sgn; while (p[crt].uz) crt++; j = crt + 1; if (s[i] == R ) sgn = 1; else sgn = -1; while (j <= n) { while (j <= n && p[j].uz) j++; if (j > n) break; if (det(p[sav], p[crt], p[j]) == sgn) crt = j; j++; } sav = crt; p[crt].uz = 1; cout << sav << ; } for (int i = 1; i <= n; i++) if (!p[i].uz) cout << i << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e5 + 10; const long long MOD = 1e9 + 17; long long s, t, n, m; long long d[2][maxN]; vector<pair<long long, long long> > g[maxN], h[maxN]; vector<pair<pair<long long, long long>, long long> > edge; long long dp[2][maxN]; void dij0(long long source) { fill(d[0], d[0] + maxN, 1e18 + 10); d[0][source] = 0; dp[0][source] = 1; set<pair<long long, long long> > s; s.insert(make_pair(d[0][source], source)); while (!s.empty()) { long long v = s.begin()->second; s.erase(s.begin()); for (long long i = 0; i < g[v].size(); i++) { long long u = g[v][i].first, w = g[v][i].second; if (d[0][u] > d[0][v] + w) { dp[0][u] = dp[0][v] % MOD; s.erase(make_pair(d[0][u], u)); d[0][u] = d[0][v] + w; s.insert(make_pair(d[0][u], u)); } else if (d[0][u] == d[0][v] + w) dp[0][u] += dp[0][v], dp[0][u] %= MOD; } } } void dij1(long long source) { fill(d[1], d[1] + maxN, 1e18 + 10); d[1][source] = 0; dp[1][source] = 1; set<pair<long long, long long> > s; s.insert(make_pair(d[1][source], source)); while (!s.empty()) { long long v = s.begin()->second; s.erase(s.begin()); for (long long i = 0; i < h[v].size(); i++) { long long u = h[v][i].first, w = h[v][i].second; if (d[1][u] > d[1][v] + w) { dp[1][u] = dp[1][v] % MOD; s.erase(make_pair(d[1][u], u)); d[1][u] = d[1][v] + w; s.insert(make_pair(d[1][u], u)); } else if (d[1][u] == d[1][v] + w) dp[1][u] += dp[1][v], dp[1][u] %= MOD; } } } int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> s >> t; s--; t--; for (long long i = 0; i < m; i++) { long long v, u, w; cin >> v >> u >> w; v--, u--; g[v].push_back(make_pair(u, w)); h[u].push_back(make_pair(v, w)); edge.push_back(make_pair(make_pair(v, u), w)); } dij0(s); dij1(t); for (long long i = 0; i < m; i++) { long long v = edge[i].first.first, u = edge[i].first.second; long long w = edge[i].second; if (d[0][v] + w + d[1][u] == d[0][t]) { if ((dp[0][v] * dp[1][u]) % MOD == dp[0][t]) { cout << YES << n ; continue; } } if (d[0][v] + d[1][u] + 1 < d[0][t]) { cout << CAN << d[0][v] + w + d[1][u] - d[0][t] + 1 << n ; continue; } cout << NO << n ; } return 0; } |
//------------------------------------------- cputop.v ????? -----------------------------------------------------
/***********************************************************************
*** ?????cputop ????????????????cpu???????????
*** ???????????????????????????????
*** ??????????????????????CPU????RTL??
*** ??????????????
************************************************************************/
`include "ram.v"
`include "rom.v"
`include "addr_decode.v"
`include "cpu.v"
`timescale 1ns / 100ps
`define PERIOD 100 // matches clk_gen.v
module cputop;
reg reset_req,clock;
integer test;
reg [(3*8):0] mnemonic; //array that holds 3 8-bit ASCII characters
reg [12:0] PC_addr,IR_addr;
wire [7:0] data;
wire [12:0] addr;
wire rd,wr,halt,ram_sel,rom_sel;
//------------------------ cpu ?????????ROM?RAM?????--------------------------------------
cpu t_cpu (.clk(clock),.reset(reset_req),.halt(halt),.rd(rd),
.wr(wr),.addr(addr),.data(data));
ram t_ram (.addr(addr[9:0]),.read(rd),.write(wr),.ena(ram_sel),.data(data));
rom t_rom (.addr(addr),.read(rd),.ena(rom_sel),.data(data));
addr_decode t_addr_decode (.addr(addr),.ram_sel(ram_sel),.rom_sel(rom_sel));
//--------------------cpu ?????????ROM?RAM???????----------------------------------
initial
begin
clock=1;
//display time in nanoseconds
$timeformat ( -9, 1, " ns", 12);
display_debug_message;
sys_reset;
test1;
$stop;
test2;
$stop;
test3;
$stop;
end
task display_debug_message;
begin
$display("\n**************************************************");
$display("* THE FOLLOWING DEBUG TASK ARE AVAILABLE: *");
$display("* \"test1; \" to load the 1st diagnostic progran. *");
$display("* \"test2; \" to load the 2nd diagnostic program. *");
$display("* \"test3; \" to load the Fibonacci program. *");
$display("*****************************************************\n");
end
endtask
task test1;
begin
test = 0;
disable MONITOR;
$readmemb ("test1.pro", t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test1.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 1;
#14800 ;
sys_reset;
end
endtask
task test2;
begin
test = 0;
disable MONITOR;
$readmemb("test2.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test2.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 2;
#11600;
sys_reset;
end
endtask
task test3;
begin
test = 0;
disable MONITOR;
$readmemb("test3.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test3.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 3;
#94000;
sys_reset;
end
endtask
task sys_reset;
begin
reset_req = 0;
#(`PERIOD*0.7) reset_req = 1;
#(1.5*`PERIOD) reset_req = 0;
end
endtask
always @(test)
begin: MONITOR
case (test)
1: begin //display results when running test 1
$display("\n*** RUNNING CPUtest1 - The Basic CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- ---- ----- ----- ----- ");
while (test == 1)
@(t_cpu.m_adr.pc_addr)//fixed
if ((t_cpu.m_adr.pc_addr%2 == 1)&&(t_cpu.m_adr.fetch == 1))//fixed
begin
# 60 PC_addr <=t_cpu.m_adr.pc_addr -1 ;
IR_addr <=t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr,data );
//HERE DATA HAS BEEN CHANGED T-CPU-M-REGISTER.DATA
end
end
2: begin
$display("\n*** RUNNING CPUtest2 - The Advanced CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- --- ----- ----- ---- ");
while (test == 2)
@(t_cpu.m_adr.pc_addr)
if ((t_cpu.m_adr.pc_addr%2 == 1)
&& (t_cpu.m_adr.fetch == 1))
begin
# 60 PC_addr <= t_cpu.m_adr.pc_addr - 1 ;
IR_addr <= t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr, data );
end
end
3: begin
$display("\n*** RUNNING CPUtest3 - An Executable Program ***");
$display("*** This program should calculate the fibonacci ***");
$display("\n TIME FIBONACCI NUMBER");
$display( " --------- -----------------");
while (test == 3)
begin
wait ( t_cpu.m_alu.opcode == 3'h1) // display Fib. No. at end of program loop
$strobe("%t %d", $time,t_ram.ram[10'h2]);
wait ( t_cpu.m_alu.opcode != 3'h1);
end
end
endcase
end
//-------------------------------------------------------------------------
always @(posedge halt) //STOP when HALT instruction decoded
begin
#500
$display("\n*********************************************");
$display( "** A HALT INSTRUCTION WAS PROCESSED !!! **");
$display( "*********************************************\n");
end
always #(`PERIOD/2) clock=~clock;
always @(t_cpu.m_alu.opcode)
//get an ASCII mnemonic for each opcode
case(t_cpu.m_alu.opcode)
3'b000 : mnemonic ="HLT";
3'h1 : mnemonic = "SKZ";
3'h2 : mnemonic = "ADD";
3'h3 : mnemonic = "AND";
3'h4 : mnemonic = "XOR";
3'h5 : mnemonic = "LDA";
3'h6 : mnemonic = "STO";
3'h7 : mnemonic = "JMP";
default : mnemonic = "???";
endcase
endmodule
//------------------------------------------- cputop.v ????? -----------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); int t; cin >> t; while (t--) { int n; cin >> n; int arr[n + 1]; for (int i = 1; i <= n; i++) cin >> arr[i]; sort(arr + 1, arr + n + 1); int dp[n + 1][405]; for (int i = 0; i <= n; i++) for (int j = 0; j < 405; j++) dp[i][j] = 1000000; for (int j = 0; j < 405; j++) dp[0][j] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j < 405; j++) { dp[i][j] = min(dp[i][j - 1], dp[i - 1][j - 1] + abs(j - arr[i])); } } cout << dp[n][404] << endl; } return 0; } |
#include <algorithm> #include <cassert> #include <cmath> #include <cstdlib> #include <cstring> #include <iomanip> #include <iostream> #include <limits> #include <map> #include <numeric> #include <queue> #include <random> #include <set> #include <stack> #include <unordered_map> #include <unordered_set> #include <vector> using namespace std; using LL = long long; int Rev(int a, int k) { vector<int> x; while (a > 0) { x.push_back((k - a % k) % k); a /= k; } reverse(x.begin(), x.end()); int ans = 0; for (int i : x) ans = ans * k + i; return ans; } int Xor(int a, int b, int k) { vector<int> x; while (a > 0 || b > 0) { x.push_back((a + b) % k); a /= k; b /= k; } reverse(x.begin(), x.end()); int ans = 0; for (int i : x) ans = ans * k + i; return ans; } int main() { ios::sync_with_stdio(false); int times; cin >> times; while (times--) { int n, k; cin >> n >> k; vector<int> x {0, Rev(1, k)}; for (int i = 2; i < n; i += 2) { x.push_back(Xor(i, Rev(i - 1, k), k)); x.push_back(Xor(i, Rev(i + 1, k), k)); } for (int i = 0; i < n; ++i) { cout << x[i] << endl; int r; cin >> r; if (r == 1) break; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_4_V
`define SKY130_FD_SC_HDLL__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_4_V
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int a[5005], ans = 1, max = 0; for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) for (int j = 0; j < n - i; j++) if (a[j] > a[j + 1]) { int t = a[j]; a[j] = a[j + 1]; a[j + 1] = t; } for (int i = n - 1; i >= 0; i--) { if (a[i] == a[i - 1]) ans++; else { if (ans > max) { max = ans; } ans = 1; } } if (max == 0) printf( 1 n ); else printf( %d n , max); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<pair<long long, long long>> v; for (long long i = 0; i < n; i++) { long long a, b; cin >> a >> b; v.push_back(make_pair(a, b)); } if (n & 1) cout << no ; else { int flag = 0; for (long long i = 1; i <= n / 2 - 1; i++) { if ((v[i - 1].first + v[i - 1 + n / 2].first == v[i].first + v[i + n / 2].first) && (v[i - 1].second + v[i - 1 + n / 2].second == v[i].second + v[i + n / 2].second)) { continue; } else { flag++; break; } } if (flag) cout << no ; else cout << yes ; return 0; } } |
#include <bits/stdc++.h> int arr[150]; int temp[150]; int main() { int n, m; std::cin >> n >> m; for (int i = 0; i < n; ++i) { int a, b; std::cin >> a >> b; for (int j = a; j <= b; ++j) arr[j]++; } int cnt = 0; for (int i = 1; i <= m; ++i) { if (!arr[i]) temp[cnt++] = i; } std::cout << cnt << std::endl; for (int i = 0; i < cnt; ++i) { if (!i) std::cout << temp[i]; else std::cout << << temp[i]; } if (cnt) std::cout << std::endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { int a, b, c; scanf( %d%d%d , &a, &b, &c); int temp = 0; if (a == b && b == c) { printf( 0 n ); } else { if (b > a) { temp = b; b = a; a = temp; } if (c > a) { temp = c; c = a; a = temp; } if (b >= c) { printf( %d n , max(2 * (a - c) - 4, 0)); } else { printf( %d n , max(2 * (a - b) - 4, 0)); } } } } |
#include <bits/stdc++.h> using namespace std; const int nax = 2e5 + 10; int first[nax], last[nax], a[nax]; int reach[nax]; int main() { fill_n(first, nax, 1e9); fill_n(last, nax, -1e9); ios::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; for (int i = 0; i < n; i++) { cin >> a[i]; first[a[i]] = min(first[a[i]], i); last[a[i]] = max(last[a[i]], i); reach[i] = i; } for (int v = 0; v < nax; v++) { if (last[v] == -1e9) continue; reach[first[v]] = max(reach[first[v]], last[v]); } int ans = 0, r = 0; map<int, int> count; for (int i = 0; i <= n; i++) { if (i >= r) { int ma = 0, sum = 0; for (auto p : count) { ma = max(ma, p.second); sum += p.second; } ans += sum - ma; count.clear(); } if (i == n) break; count[a[i]]++; r = max(r, reach[i] + 1); } cout << ans << endl; } |
module top;
reg a, pass;
wire x, y, ab;
assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1;
assign y = a;
// We need this since Icarus currently has a bug when forcing from
// an expression (it only uses the value when the force ran).
assign ab = ~a;
tran (x, y);
initial begin
// $monitor ($realtime,, x,y,,a);
pass = 1'b1;
// Check matching values.
#1 if ( x !== 1'bx || y !== 1'bx) begin
$display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b0;
#1 if ( x !== 1'b0 || y !== 1'b0) begin
$display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b1;
#1 if ( x !== 1'b1 || y !== 1'b1) begin
$display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y);
pass = 1'b0;
end
// Check force with opposite values.
#1 force x = ab;
#1 if ( x !== 1'b0 || y !== 1'bx) begin
$display("Failed force value, expected 1'b0, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b0;
#1 if ( x !== 1'b1 || y !== 1'bx) begin
$display("Failed force value, expected 1'b1, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
// Now release.
#1 release x;
#1 if ( x !== 1'b0 || y !== 1'b0) begin
$display("Failed release value, expected 1'b0, 1'b0, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b1;
#1 if ( x !== 1'b1 || y !== 1'b1) begin
$display("Failed release value, expected 1'b1, 1'b1, got %b %b", x, y);
pass = 1'b0;
end
// Now force and release the driving signal.
#1 force a = 1'bx;
#1 if ( x !== 1'bx || y !== 1'bx) begin
$display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
#1 release a;
a = 1'b0;
#1 if ( x !== 1'b0 || y !== 1'b0) begin
$display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y);
pass = 1'b0;
end
// Check that the other driver works.
#1 a = 1'bz;
#1 if ( x !== 1'b1 || y !== 1'b1) begin
$display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, c = 0; cin >> n; int r = n; int cnt = 0; while (r > 0) { int temp = r % 10; if (temp > 0) cnt++; r = r / 10; c++; } cout << cnt << endl; int it, ans; for (int i = 0; i < c; i++) { it = n % 10; ans = it * pow(10, i); if (ans > 0) cout << ans << ; n = n / 10; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long min(long long a, long long b) { return (a < b) ? a : b; } long long max(long long a, long long b) { return (a > b) ? a : b; } long long fp(long long a, long long b) { if (b == 0) return 1; long long x = fp(a, b / 2); x = (x * x) % mod; if (b & 1) x = (x * a) % mod; return x; } const long long N = 2e5 + 5; long long a[N]; long long n; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; long long cnt[60] = {0}; for (long long i = 1; i <= n; i++) { cin >> a[i]; for (long long b = 0; b < 20; b++) { if ((a[i] >> b) & 1) { cnt[b]++; } } } long long ans = 0; for (long long i = 1; i <= n; i++) { long long x = 0; for (long long b = 0; b < 20; b++) { if (cnt[b]) { cnt[b]--; x |= (1ll << b); } } ans += x * x; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int NMAX = 200000 + 5; const int MMAX = 2000 + 5; const int INF = 1000000000; const int BS = 1000000000 + 7; const long long INFLL = 1000000000ll * 1000000000ll; const long double eps = 1e-6; int a[NMAX]; bool is_inverted[4 * NMAX]; bool shouldSetTrue[4 * NMAX]; bool shouldSetFalse[4 * NMAX]; bool shouldInvert[4 * NMAX]; void merge_flags(int parent, int child) { if (shouldSetFalse[parent]) { shouldSetFalse[child] = true; shouldSetTrue[child] = false; shouldInvert[child] = false; return; } if (shouldSetTrue[parent]) { shouldSetFalse[child] = false; shouldSetTrue[child] = true; shouldInvert[child] = false; return; } if (shouldInvert[parent]) { if (shouldSetFalse[child]) { shouldSetFalse[child] = false; shouldSetTrue[child] = true; shouldInvert[child] = false; } else if (shouldSetTrue[child]) { shouldSetFalse[child] = true; shouldSetTrue[child] = false; shouldInvert[child] = false; } else { shouldInvert[child] = !shouldInvert[child]; } } } void pass_down(int v, int tl, int tr) { if (tl == tr) { bool current = is_inverted[v]; if (shouldSetFalse[v]) { current = false; } if (shouldSetTrue[v]) { current = true; } if (shouldInvert[v]) { current = !current; } is_inverted[v] = current; shouldSetFalse[v] = false; shouldSetTrue[v] = false; shouldInvert[v] = false; return; } merge_flags(v, v + v); merge_flags(v, v + v + 1); shouldSetFalse[v] = false; shouldSetTrue[v] = false; shouldInvert[v] = false; } bool get(int v, int tl, int tr, int pos) { pass_down(v, tl, tr); if (tl == tr) { return is_inverted[v]; } int tm = (tl + tr) / 2; if (pos <= tm) { return get(v + v, tl, tm, pos); } else { return get(v + v + 1, tm + 1, tr, pos); } } void set_inverted(int v, int tl, int tr, int l, int r, bool shouldBeTrue, bool shouldBeFalse, bool shouldBeInverted) { if (r < l) return; pass_down(v, tl, tr); if (l == tl && r == tr) { if (shouldBeFalse) { shouldSetFalse[v] = true; } if (shouldBeTrue) { shouldSetTrue[v] = true; } if (shouldBeInverted) { shouldInvert[v] = true; } return; } int tm = (tl + tr) / 2; if (r <= tm) { set_inverted(v + v, tl, tm, l, r, shouldBeTrue, shouldBeFalse, shouldBeInverted); } else if (l >= tm + 1) { set_inverted(v + v + 1, tm + 1, tr, l, r, shouldBeTrue, shouldBeFalse, shouldBeInverted); } else { set_inverted(v + v, tl, tm, l, tm, shouldBeTrue, shouldBeFalse, shouldBeInverted); set_inverted(v + v + 1, tm + 1, tr, tm + 1, r, shouldBeTrue, shouldBeFalse, shouldBeInverted); } } int main(int argc, char** argv) { if (argc > 1 && strcmp(argv[1], seland ) == 0) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } int n, q; scanf( %d %d n , &n, &q); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } scanf( n ); int bias = 100000; for (int i = 0; i < q; i++) { char c; int x; scanf( %c %d n , &c, &x); if (c == < && x <= 0) { x--; set_inverted(1, 0, NMAX - 1, 0, bias + x, true, false, false); set_inverted(1, 0, NMAX - 1, bias - x, 2 * bias, false, true, false); } else if (c == > && x >= 0) { x++; set_inverted(1, 0, NMAX - 1, bias + x, 2 * bias, true, false, false); set_inverted(1, 0, NMAX - 1, 0, bias - x, false, true, false); } else if (c == < && x > 0) { x--; set_inverted(1, 0, NMAX - 1, 0, bias - x - 1, true, false, false); set_inverted(1, 0, NMAX - 1, bias + x + 1, 2 * bias, false, true, false); set_inverted(1, 0, NMAX - 1, bias - x, bias + x, false, false, true); } else if (c == > && x < 0) { x++; set_inverted(1, 0, NMAX - 1, bias - x + 1, 2 * bias, true, false, false); set_inverted(1, 0, NMAX - 1, 0, bias + x - 1, false, true, false); set_inverted(1, 0, NMAX - 1, bias + x, bias - x, false, false, true); } } for (int i = 0; i < n; i++) { bool inverted = get(1, 0, NMAX - 1, a[i] + bias); if (inverted) { printf( %d , -a[i]); } else { printf( %d , a[i]); } } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2005; char mpt[2005][2005]; int dp[maxn][maxn]; int col[maxn]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %s , mpt[i] + 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (mpt[i][j] == L ) { int w = i - 1; if (j - w >= 1) dp[i][j - w] += 1; } else if (mpt[i][j] == R ) { int w = i - 1; if (j + w <= m) dp[i][j + w] += 1; } else if (mpt[i][j] == U && i % 2 == 1) { col[j] += 1; } else if (mpt[i][j] == D ) { continue; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { col[j] += dp[i][j]; } } for (int i = 1; i <= m; i++) printf( %d , col[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long t, n, i, j, flag = 0, temp, nodes, a, b, m, k, sz, sm, res; long long mn, mx; long long l, r; long long x, y, z; long long c, d; t = 1; vector<pair<int, int>> v; string s; char ch; while (t--) { flag = 0; v.clear(); cin >> n; int A = INT_MAX, B = INT_MIN; for (i = 0; i < n; i++) { cin >> a >> b; v.push_back({a, b}); if (a < A) A = a; if (B < b) B = b; } for (i = 0; i < v.size(); i++) { if (v[i].first == A && v[i].second == B) { flag = 1; break; } } if (flag == 1) { cout << i + 1 << endl; continue; } else { cout << -1 ; continue; } } return 0; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: syncfifo_512x32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module syncfifo_512x32 (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> int m, n, a[10][10] = {{0, 1, 2}, {1, 0, 2}, {1, 2, 0}, {2, 1, 0}, {2, 0, 1}, {0, 2, 1}, {0, 1, 2}}; int main() { scanf( %d %d , &n, &m); n %= 6; printf( %d , a[n][m]); return 0; } |
//Listing 9.1
module ps2_rx
(
input wire clk, reset,
input wire ps2d, ps2c, rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule |
#include <bits/stdc++.h> using namespace std; int m, n, q, a[13][110005], id; bitset<4100> s[110005]; inline int read() { int ret = 0, ff = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) ff = -1; ch = getchar(); } while (isdigit(ch)) { ret = (ret << 3) + (ret << 1) + (ch ^ 48); ch = getchar(); } return ret * ff; } signed main() { m = read(), n = read(), q = read(); id = n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) a[i][j] = read(); for (int j = 0; j < (1 << n); j++) if (j & (1 << (i - 1))) s[i][j] = 1; } for (int que = 1; que <= q; que++) { int opt = read(), x = read(), y = read(); if (opt == 1) { s[++id] = s[x] & s[y]; continue; } if (opt == 2) { s[++id] = s[x] | s[y]; continue; } if (opt == 3) { vector<pair<int, int> > v; for (int i = 1; i <= n; i++) v.push_back(make_pair(a[i][y], i)); sort(v.begin(), v.end()); int sum = 0; for (int i = 0; i < n; i++) { sum |= (1 << (v[i].second - 1)); if (s[x][sum]) { printf( %d n , v[i].first); break; } } continue; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int cnt; bool leaf; int nx[26]; node() { leaf = false; cnt = 0; memset(nx, -1, sizeof nx); } }; string s, d; node t[300100]; int ans, sz; vector<string> v; void add(string s) { int cur = 0; for (int i = 0; i < s.size(); i++) { if (t[cur].nx[s[i] - a ] != -1) cur = t[cur].nx[s[i] - a ]; else { t[cur].nx[s[i] - a ] = ++sz; cur = sz; } t[cur].cnt++; } t[cur].leaf = true; } bool check(string s) { int cur = 0; for (int i = 0; i < s.size(); i++) { if (t[cur].nx[s[i] - a ] != -1) cur = t[cur].nx[s[i] - a ]; else return false; } if (t[cur].leaf) return true; return false; } int calc(string s) { int d = -1, cur = 0, mn = -1; for (int i = 0; i < s.size(); i++) { if (t[cur].nx[s[i] - a ] != -1) cur = t[cur].nx[s[i] - a ]; else break; d = i + 1; } if (d == -1) return s.size(); for (int i = 0; i < 26; i++) if (t[cur].nx[i] != -1) return s.size(); cur = 0; for (int i = 0; i < s.size(); i++) { if (t[cur].nx[s[i] - a ] != -1) cur = t[cur].nx[s[i] - a ]; else break; if (t[cur].cnt == 1) { mn = i + 1; break; } } if (mn == -1) return s.size(); return min(s.size(), mn + 1 + s.size() - d); } int main() { while (getline(cin, d)) { s += d; s += # ; ans++; for (int i = 0; i < d.size(); i++) if (!isalpha(d[i])) ans++; } for (int i = 0; i < s.size();) { if (!isalpha(s[i])) i++; else { int j = i + 1; while (true) { if (!isalpha(s[j])) break; j++; } j--; v.push_back(s.substr(i, j - i + 1)); i = j + 1; } } for (auto a : v) { ans += calc(a); if (!check(a)) add(a); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a = (n * (n + 1) / 2); cout << (6 * a) + 1; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_2_ar_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_2_ar_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_W\
IDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_ar_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 52; const int MAX = 1e9 + 5; int n, a[N]; long double dp[N][N][N][N]; int p; long double all, P[N]; long double f(int wh, int ret, int left, int whd) { if (left == 0 && ret) return 0; if (left == 0 && ret == 0) return 1; if (ret < 0) return 0; if (wh > n) return 0; long double &r = dp[wh][ret][left][whd]; if (r != -1) return r; if (wh == whd) return r = f(wh + 1, ret, left, whd); return r = f(wh + 1, ret - a[wh], left - 1, whd) + f(wh + 1, ret, left, whd); } int main() { scanf( %d , &n); P[0] = 1; for (int i = 1; i <= n; i++) P[i] = P[i - 1] * i; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &p); for (int A = 0; A <= N - 1; A++) for (int B = 0; B <= N - 1; B++) for (int C = 0; C <= N - 1; C++) for (int D = 0; D <= N - 1; D++) dp[A][B][C][D] = -1; for (int i = 1; i <= n; i++) { int begin = p - a[i] + 1; int end = p; for (int j = begin; j <= end; j++) { for (int k = 0; k <= n; k++) { long double temp = f(1, j, k, i); all += temp * P[k] / P[n] * P[n - k - 1] * k; } } } for (int i = 0; i <= p; i++) all += f(1, i, n, 0) * n; cout << setprecision(12) << fixed << all << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<int, vector<int> > m; int e; for (int i = 2; i <= n; i++) { cin >> e; m[e].push_back(i); } vector<bool> leaf(n + 1, true); leaf[1] = false; for (int i = 1; i <= n; i++) { if (m.count(i) > 0) { int c = 0; for (auto it = m[i].begin(); it != m[i].end(); it++) { if (m.count(*it) != 1) c++; } if (c < 3) { cout << No n ; return 0; } } } cout << Yes n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_4_V
`define SKY130_FD_SC_HDLL__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_SYMBOL_V
`define SKY130_FD_SC_HS__HA_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; string a = What are you doing at the end of the world? Are you busy? Will you save us? ; string pref = What are you doing while sending ; string suff = ? Are you busy? Will you send ; string last = ? ; long long f[100001]; long long q, n, k, n1, n2, n3, n4; const long long inf = 1e18 + 10; char solution(long long n, long long k) { if (k > f[n]) return . ; if (n == 0) return a[k - 1]; if (k <= n2) return pref[k - 1]; k = k - n2; if (k <= f[n - 1]) return solution(n - 1, k); k = k - f[n - 1]; if (k <= n3) return suff[k - 1]; k = k - n3; if (k <= f[n - 1]) return solution(n - 1, k); k = k - f[n - 1]; if (k <= n4) return last[k - 1]; } int main() { n1 = a.length(); n2 = pref.length(); n3 = suff.length(); n4 = last.length(); f[0] = n1; for (int i = 1; i <= 100000; i++) f[i] = min(inf, n2 + f[i - 1] + n3 + f[i - 1] + n4); cin >> q; while (q > 0) { cin >> n >> k; q = q - 1; cout << solution(n, k); } return 0; } |
#include <bits/stdc++.h> int len; int big; int Dgt[30]; int N; int ans; void tochar(int); int main() { while (scanf( %d , &N) != EOF) { memset(Dgt, 0, sizeof(Dgt)); ans = 0; while (N) { big = -1; tochar(N); for (int i = 0; i < len; i++) { if (Dgt[i] > big) big = Dgt[i]; } N -= big; ans++; } printf( %d n , ans); } } void tochar(int n) { len = 0; while (n) { Dgt[len] = n % 10; n /= 10; len++; } } |
#include <bits/stdc++.h> using namespace std; struct TreeNode { int val; TreeNode* left; TreeNode* right; TreeNode(int x) : val(x), left(NULL), right(NULL) {} }; struct ListNode { int val; ListNode* next; ListNode(int x) : val(x), next(NULL) {} }; int nxt() { int x; cin >> x; return x; } long long nxtLong() { long long x; cin >> x; return x; } string nxtStr() { string x; cin >> x; return x; } char nxtChar() { char x; cin >> x; return x; } double nxtDouble() { double x; cin >> x; return x; } long double nxtLDouble() { long double x; cin >> x; return x; } TreeNode* makeTree(int n) { queue<TreeNode*> tree_nodes; TreeNode* root; if (n) { root = new TreeNode(nxt()); tree_nodes.push(root); } else { return NULL; } while (!tree_nodes.empty()) { TreeNode* node = tree_nodes.front(); tree_nodes.pop(); bool left; cin >> left; if (left) { node->left = new TreeNode(nxt()); tree_nodes.push(node->left); } bool right; cin >> right; if (right) { node->right = new TreeNode(nxt()); tree_nodes.push(node->right); } } return root; } ListNode* makeLinkedList(int n) { ListNode* list = new ListNode(0); ListNode* dummy = list; for (int i = 0; i < n; ++i) { list->next = new ListNode(nxt()); list = list->next; } return dummy->next; } char ans[2000001]; void solve() { int n = nxt(); int len = 0; while (n--) { string s = nxtStr(); int m = nxt(); int l = s.length(); int y = 0; while (m--) { int x = nxt(); x--; len = max(len, x + l); for (int i = max(x, y); i < x + l; ++i) { ans[i] = s[i - x]; } y = x + l; } } for (int i = 0; i < len; ++i) { if (!ans[i]) { cout << a ; } else { cout << ans[i]; } } cout << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(9); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100001]; int getBound(int start, int dir, int size, int k) { int cnt = 0; bool seen[100001]; fill(seen, seen + 100001, false); for (int i = start; i <= size && i > 0; i += dir) { if (!seen[a[i]]) cnt++, seen[a[i]] = true; if (cnt == k) return i; } return -1; } int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; int right = getBound(1, 1, n, k); if (right == -1) cout << -1 << << -1 << endl; else { int left = getBound(right, -1, n, k); cout << left << << right << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e8 + 10; bool ok = 0; int n, maxy, miny, maxx, minx; struct point { int x, y; }; bool cmp(point a, point b) { return a.x < b.x; } point jilu[100050]; int bfy[100050], afy[100050], bfmaxy[100050], bfminy[100050], afminy[100050], afmaxy[100050]; int b1_search(long long tmp) { int l = 0, r = n - 1, m; while (r >= l) { m = (l + r) >> 1; if (jilu[m].x <= tmp) l = m + 1; else r = m - 1; } return r; } int b2_search(long long tmp) { int l = 0, r = n - 1, m; while (r >= l) { m = (r + l) >> 1; if (jilu[m].x >= tmp) r = m - 1; else l = m + 1; } return l; } long long binary_sqrt(long long tmp) { long long ans = sqrt(tmp); while (ans * ans > tmp) { ans--; } while ((ans + 1) * (ans + 1) <= tmp) { ans++; } return ans; } bool check(long long tmp) { long long a = maxy - miny; long long b = maxx - minx; if (tmp >= a * a || tmp >= b * b) { return 1; } int pos; long long ttmp = binary_sqrt(tmp); for (int i = 0; i < n; i++) { if (jilu[i].x < 0) { pos = b1_search(min(jilu[i].x + ttmp, (long long)-jilu[i].x)); long long my = max(bfy[i], afy[pos]); long long mx = max(max(jilu[i].x, -jilu[i].x), max(jilu[pos].x, -jilu[pos].x)); long long yy = max(afmaxy[pos], bfmaxy[i]) - min(afminy[pos], bfminy[i]); if (my * my + mx * mx <= tmp && yy * yy <= tmp) { return 1; } } else { pos = b2_search(max(jilu[i].x - ttmp, (long long)-jilu[i].x)); long long my = max(afy[i], bfy[pos]); long long mx = max(max(jilu[i].x, -jilu[i].x), max(jilu[pos].x, -jilu[pos].x)); long long yy = max(afmaxy[i], bfmaxy[pos]) - min(afminy[i], bfminy[pos]); if (my * my + mx * mx <= tmp && yy * yy <= tmp) { return 1; } } } return 0; } void Binary_search(long long l, long long r) { long long m; while (r > l) { m = l + (r - l) / 2; if (check(m)) r = m; else l = m + 1; } cout << r << endl; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d , &jilu[i].x, &jilu[i].y); } sort(jilu, jilu + n, cmp); bfmaxy[0] = -inf; bfminy[0] = inf; for (int i = 1; i < n; i++) { bfmaxy[i] = max(bfmaxy[i - 1], jilu[i - 1].y); bfminy[i] = min(bfminy[i - 1], jilu[i - 1].y); } afmaxy[n - 1] = -inf; afminy[n - 1] = inf; for (int i = n - 2; i >= 0; i--) { afmaxy[i] = max(afmaxy[i + 1], jilu[i + 1].y); afminy[i] = min(afminy[i + 1], jilu[i + 1].y); } for (int i = 1; i < n; i++) { bfy[i] = max(max(bfy[i - 1], -bfy[i - 1]), max(jilu[i - 1].y, -jilu[i - 1].y)); } for (int i = n - 2; i >= 0; i--) { afy[i] = max(max(afy[i + 1], -afy[i + 1]), max(jilu[i + 1].y, -jilu[i + 1].y)); } maxy = miny = jilu[0].y; maxx = minx = jilu[0].x; for (int i = 0; i < n; i++) { maxy = max(jilu[i].y, maxy); miny = min(jilu[i].y, miny); maxx = max(jilu[i].x, maxx); minx = min(jilu[i].x, minx); } Binary_search(0, 40000000000000000); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX = 100010; long long quick_Mod(long long n) { long long ans = 1; long long x = 2; while (n) { if (n & 1) ans = ans * x % 1000000007; n = n >> 1; x = x * x % 1000000007; } return ans; } void ex_gcd(long long a, long long b, long long &gcd, long long &x, long long &y) { if (b == 0) { gcd = a; y = 0; x = 1; return; } else { ex_gcd(b, a % b, gcd, y, x); y -= x * (a / b); } } long long inverse(long long a) { long long gcd, x, y; ex_gcd(a, 1000000007, gcd, x, y); if (gcd == 1) return (x % 1000000007 + 1000000007) % 1000000007; else return -1; } int main() { char s[MAX]; long long k; scanf( %s , s); scanf( %I64d , &k); long long len = strlen(s); long long ans = 0; for (int i = 0; i < len; i++) { if (s[i] == 0 || s[i] == 5 ) { ans += quick_Mod(i) * inverse(quick_Mod(len) - 1) % 1000000007 * (quick_Mod(k * len) - 1) % 1000000007; } } printf( %I64d n , (ans % 1000000007 + 1000000007) % 1000000007); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_BEHAVIORAL_V |
#include <bits/stdc++.h> int dx[] = {-1, -1, -1, 0, 1, 1, 1, 0}; int dy[] = {-1, 0, 1, 1, 1, 0, -1, -1}; using namespace std; long long power(long long a, long long p, long long M) { long long r = 1; a = a % M; while (p > 0) { if (p % 2) r = (r * a) % M; a = (a * a) % M; p /= 2; } return r; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long n, m; set<long long> e[100005]; stack<long long> cycle, temp; long long vis[505]; bool found; void findCycle(long long x) { temp.push(x); vis[x] = 1; for (auto y : e[x]) { if (vis[y] == 0) findCycle(y); else if (vis[y] == 1) { if (found) return; cycle = temp; cycle.push(y); found = 1; return; } } if (!temp.empty()) temp.pop(); vis[x] = 2; } void fc(long long x) { vis[x] = 1; for (auto y : e[x]) { if (vis[y] == 0) fc(y); else if (vis[y] == 1) { found = 1; return; } } vis[x] = 2; } void solve() { cin >> n >> m; for (long long i = 0; i < m; i++) { long long a, b; scanf( %lld%lld , &a, &b); e[a].insert(b); } for (long long i = 1; i < n + 1; i++) { if (!vis[i]) { findCycle(i); if (found) break; } } if (!found) { cout << YES n ; return; } vector<long long> c; for (long long i = 0; i < 505; i++) vis[i] = 0; while (!cycle.empty()) { c.push_back(cycle.top()); if (vis[cycle.top()]) { break; } vis[cycle.top()] = 1; cycle.pop(); } reverse(c.begin(), c.end()); for (long long i = 0; i < c.size() - 1; i++) { found = 0; e[c[i]].erase(c[i + 1]); for (long long j = 0; j < 505; j++) vis[j] = 0; for (long long j = 1; j < n + 1; j++) { if (!vis[j]) fc(j); if (found) { break; } } if (!found) { cout << YES n ; return; } e[c[i]].insert(c[i + 1]); } cout << NO n ; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int a[200]; map<int, int> Map; int cnt[20]; int main() { for (int i = 0; i <= 11; i++) Map[1 << i] = i; int _; for (scanf( %d , &_); _; _--) { scanf( %d , &n); for (int i = 0; i < 12; i++) cnt[i] = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] > 2048) continue; cnt[Map[a[i]]]++; } for (int i = 0; i <= 10; i++) { cnt[i + 1] += cnt[i] / 2; } if (cnt[11]) puts( YES ); else puts( NO ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long linf = 1e18 + 5; const int mod = (int)1e9 + 7; const int logN = 17; const int inf = 1e9; const int N = 2e5 + 5; int n, a[N], s; vector<pair<long long, long long> > T[N << 2], g[N << 2]; pair<long long, long long> line[N]; long long pre[N]; int P[N << 2]; double intersect(pair<long long, long long> x, pair<long long, long long> y) { return (y.second - x.second) * 1.0 / (x.first - y.first); } void add(vector<pair<long long, long long> > &T, pair<long long, long long> x) { int s = T.size() - 1; while (s > 0 && intersect(T[s], T[s - 1]) >= intersect(T[s], x)) { T.pop_back(); s--; } T.push_back(x); } void init(int k, int bas, int son) { P[k] = 0; if (bas == son) { T[k].clear(); g[k].clear(); T[k].push_back(line[bas]); g[k].push_back(line[bas]); return; } init((k + k), bas, (bas + son >> 1)); init((k + k + 1), (bas + son >> 1) + 1, son); g[k].resize(g[(k + k)].size() + g[(k + k + 1)].size()); merge(g[(k + k)].begin(), g[(k + k)].end(), g[(k + k + 1)].begin(), g[(k + k + 1)].end(), g[k].begin()); for (__typeof(g[k].begin()) it = g[k].begin(); it != g[k].end(); it++) add(T[k], *it); P[k] = 0; } long long query(int k, int bas, int son, int x, int y, long long t) { if (bas > y || son < x) return -linf; if (x <= bas && son <= y) { while (P[k] < T[k].size() - 1 && intersect(T[k][P[k]], T[k][P[k] + 1]) <= t) P[k]++; return T[k][P[k]].first * t + T[k][P[k]].second; } return max(query((k + k), bas, (bas + son >> 1), x, y, t), query((k + k + 1), (bas + son >> 1) + 1, son, x, y, t)); } int main() { scanf( %d , &n); long long ans = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); pre[i] = pre[i - 1] + a[i]; ans += a[i] * (long long)i; } for (int i = 0; i <= n; i++) line[i] = make_pair(i, pre[n] - pre[i]); init(1, 0, n); long long res = -linf; vector<pair<int, int> > look; for (int i = 1; i <= n; i++) look.push_back(make_pair(a[i], i)); sort(look.begin(), look.end()); for (__typeof(look.begin()) it = look.begin(); it != look.end(); it++) { long long left = query(1, 0, n, 0, it->second, it->first); res = max(res, ans + left - (pre[n] - pre[it->second]) - it->second * (long long)it->first); left = query(1, 0, n, it->second + 2, n, it->first); res = max(res, ans + left - (pre[n] - pre[it->second]) - it->second * (long long)it->first); } cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { while (b) { int temp = b; b = a % b; a = temp; } return a; } int main() { int a, b, n, counting = 0, GCD; scanf( %d %d %d , &a, &b, &n); while (1) { counting++; GCD = gcd(a, n); if (n < GCD) break; n = n - GCD; counting++; GCD = gcd(b, n); if (n < GCD) break; n = n - GCD; } printf( %d n , counting % 2); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int MOD = 1e9 + 7; vector<int> v; long long f[301][N]; int a[N]; int main() { for (int i = 1; i <= 300; i++) { f[i][0] = 1; for (int j = 1; j < N; j++) { f[i][j] = f[i][j - 1] * i % MOD; } } int n, x, sum; while (scanf( %d , &n) != EOF) { for (int i = 1; i <= n; i++) { scanf( %d , &x); a[x]++; } for (int i = 100000; i > 1; i--) a[i - 1] += a[i]; long long ans = 1; for (int i = 2; i <= 100000; i++) { if (a[i] == 0) continue; v.clear(); for (int j = 1; j * j <= i; j++) { if (i % j == 0) { v.push_back(j); if (j != i / j) v.push_back(i / j); } } sort(v.begin(), v.end()); int len = v.size(); long long ret1 = 1, ret2 = 1; sum = 0; for (int j = len - 1; j >= 0; j--) { if (a[v[j]] <= sum) continue; ret1 = ret1 * f[j + 1][a[v[j]] - sum] % MOD; sum = a[v[j]]; } sum = 0; for (int j = len - 2; j >= 0; j--) { if (a[v[j]] <= sum) continue; ret2 = ret2 * f[j + 1][a[v[j]] - sum] % MOD; sum = a[v[j]]; } ans = ((ans + ret1 - ret2) % MOD + MOD) % MOD; } printf( %I64d n , ans); } return 0; } |
#include <stdio.h> int main() { int t; scanf( %d , &t); while (t--) { int x, i; scanf( %d , &x); for (i = 1; i * (i + 1) / 2 < x; i++); if (i * (i + 1) / 2 - x != 1) { printf( %d n , i); } else { printf( %d n , i + 1); } } } |
#include <bits/stdc++.h> using namespace std; int modul(int a, int b) { if (a - b < 0) return b - a; return a - b; } int main() { int n, k, st, et, s, e, d, v[103], j, m, stm, etm; cin >> n >> k; st = et = 0; d = 0; for (int i = 1; i <= n; i++) { cin >> v[i]; if (v[i] == 1) et++; else st++; } stm = etm = 0; for (int i = 1; i <= k; i++) { s = st; e = et; j = i; while (j <= n) { if (v[j] == 1) e--; else s--; j += k; } m = modul(s, e); if (m > d) { stm = s; etm = e; d = m; } } cout << d; return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-7; int ary[10005]; int bry[10005]; vector<pair<int, int> > ans; int pivot[31], pid[31]; int pivot2[31], pid2[31]; bool vis[10005]; void solve(int n, int a[]) { for (int i = 0; i < 31; ++i) pid[i] = -1; for (int k = 0; k < n; ++k) { int v = a[k]; for (int i = 31 - 1; i >= 0; --i) { if (pid[i] == -1) continue; if (v & (1 << i)) v ^= pivot[i], ans.push_back(make_pair(k, pid[i])); } if (v == 0) continue; for (int i = 31 - 1; i >= 0; --i) { if (v & (1 << i)) { assert(pid[i] == -1); pivot[i] = v, pid[i] = k; for (int j = 0; j < 31; ++j) if (pid[j] != -1 and i != j and pivot[j] & (1 << i)) pivot[j] ^= pivot[i], ans.push_back(make_pair(pid[j], pid[i])); break; } } } } bool solve3(vector<pair<int, int> > candi); bool solve2(int n, int a[]) { for (int k = 0; k < n; ++k) { if (vis[k]) continue; int v = a[k]; for (int i = 31 - 1; i >= 0; --i) { if (pid[i] == -1) continue; if (v & (1 << i)) v ^= pivot[i], ans.push_back(make_pair(k, pid[i])); } if (v != 0) return false; } vector<pair<int, int> > candi; for (int i = 31 - 1; i >= 0; --i) if (pid[i] != -1) candi.push_back(make_pair(a[pid[i]], pid[i])); return solve3(candi); } bool solve3(vector<pair<int, int> > candi) { vector<pair<int, int> > buf; for (int i = 0; i < 31; ++i) pid2[i] = -1; for (const auto &p : candi) { int k = p.second; int v = p.first; for (int i = 31 - 1; i >= 0; --i) { if (pid2[i] == -1) continue; if (v & (1 << i)) v ^= pivot2[i], buf.push_back(make_pair(k, pid2[i])); } if (v == 0) continue; for (int i = 31 - 1; i >= 0; --i) { if (v & (1 << i)) { assert(pid2[i] == -1); pivot2[i] = v, pid2[i] = k; for (int j = 0; j < 31; ++j) if (pid2[j] != -1 and i != j and pivot2[j] & (1 << i)) pivot2[j] ^= pivot2[i], buf.push_back(make_pair(pid2[j], pid2[i])); break; } } } for (int i = 31 - 1; i >= 0; --i) { int a = pid[i]; int b = pid2[i]; if (a == -1 and b == -1) continue; if (a == -1 and b != -1) return false; else if (a != -1 and b == -1) ans.push_back(make_pair(a, a)); else { int d = pivot[i] ^ pivot2[i]; for (int j = i - 1; j >= 0; --j) if (pid[j] != -1 and d & (1 << j)) d ^= pivot[j], ans.push_back(make_pair(pid[i], pid[j])); if (d != 0) return false; if (a == b) continue; ans.push_back(make_pair(pid[i], b)); ans.push_back(make_pair(b, pid[i])); ans.push_back(make_pair(pid[i], b)); for (int j = 0; j < 31; ++j) if (pid[j] == b) { swap(pid[i], pid[j]); break; } } } reverse((buf).begin(), (buf).end()); for (const auto &p : buf) ans.push_back(p); return true; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &ary[i]); solve(n, ary); for (int i = 0; i < 31; ++i) if (pid[i] != -1) vis[pid[i]] = true; for (int i = 0; i < n; ++i) scanf( %d , &bry[i]); bool posi = solve2(n, bry); if (not posi) printf( -1 ); else { printf( %d n , ((int)(ans).size())); for (const auto &p : ans) printf( %d %d n , p.first + 1, p.second + 1); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 10; const long long inf = 1e15; const int mod = 1e6; void faster() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const long long N = 3000 * 200; int mark[N]; int main() { faster(); int n; cin >> n; int t = 0; vector<int> v[n]; for (int i = 1; i <= n * n; i++) { v[(i + t) % n].push_back(i); if (i % n == 0) t++; } for (int i = 0; i < n; i++) { for (auto c : v[i]) cout << c << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; vector<int> V[500500]; vector<int> SV[500500]; vector<int> MAX1[500500], MAX2[500500], MIN1[500500], MIN2[500500]; vector<pair<int, int>> T; int R[505000]; int main() { cin.sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc; cin >> tc; for (int t = 1; t <= tc; t++) { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { V[i].clear(); SV[i].clear(); } T.clear(); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x; cin >> x; V[i].push_back(x); } T.push_back(make_pair(V[i][0], i)); } sort(T.begin(), T.end()); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { SV[i].push_back(V[T[i].second][j]); } R[T[i].second] = i; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { MAX1[i].push_back(0); MAX2[i].push_back(0); MIN1[i].push_back(0); MIN2[i].push_back(0); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int m1 = i == 0 ? -1 : MAX1[i - 1][j]; int m2 = j == 0 ? -1 : MAX1[i][j - 1]; MAX1[i][j] = max(max(m1, m2), SV[i][j]); } } for (int i = n - 1; i >= 0; i--) { for (int j = m - 1; j >= 0; j--) { int m1 = (i == n - 1) ? -1 : MAX2[i + 1][j]; int m2 = (j == m - 1) ? -1 : MAX2[i][j + 1]; MAX2[i][j] = max(max(m1, m2), SV[i][j]); } } for (int i = 0; i < n; i++) { for (int j = m - 1; j >= 0; j--) { int m1 = i == 0 ? 9999999 : MIN1[i - 1][j]; int m2 = (j == m - 1) ? 9999999 : MIN1[i][j + 1]; MIN1[i][j] = min(min(m1, m2), SV[i][j]); } } for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < m; j++) { int m1 = (i == n - 1) ? 9999999 : MIN2[i + 1][j]; int m2 = (j == 0) ? 9999999 : MIN2[i][j - 1]; MIN2[i][j] = min(min(m1, m2), SV[i][j]); } } int ansx = -1, ansy = -1; for (int i = 0; i < n - 1; i++) { for (int j = 0; j < m - 1; j++) { if (MAX1[i][j] < MIN2[i + 1][j] && MAX2[i + 1][j + 1] < MIN1[i][j + 1]) { ansx = i; ansy = j; break; } } } if (ansx == -1 && ansy == -1) cout << NO n ; else { cout << YES n ; for (int i = 0; i < n; i++) { if (R[i] <= ansx) cout << B ; else cout << R ; } cout << ; cout << ansy + 1; cout << n ; } } } |
module butterfly_4(
clk,
rst,
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input clk;
input rst;
input signed [23:0] i_0;
input signed [23:0] i_1;
input signed [23:0] i_2;
input signed [23:0] i_3;
output reg signed [24:0] o_0;
output reg signed [24:0] o_1;
output reg signed [24:0] o_2;
output reg signed [24:0] o_3;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [24:0] b_0;
wire signed [24:0] b_1;
wire signed [24:0] b_2;
wire signed [24:0] b_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_3;
assign b_1=i_1+i_2;
assign b_2=i_1-i_2;
assign b_3=i_0-i_3;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
begin
o_0<=25'b0;
o_1<=25'b0;
o_2<=25'b0;
o_3<=25'b0;
end
else
begin
o_0<=b_0;
o_1<=b_1;
o_2<=b_2;
o_3<=b_3;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<pair<int, int>> times; for (int i = 0; i < m; i++) { int s, e; cin >> s >> e; times.push_back(make_pair(s, e)); } sort(times.begin(), times.end(), [](pair<int, int> a, pair<int, int> b) { return (a.first == b.first) ? (a.second < b.second) : (a.first < b.first); }); vector<int> ans(n, 0); for (auto t : times) { for (int i = t.first + 1; i <= t.second; i++) { ans[i - 1] = !ans[i - 2]; } } for (auto a : ans) cout << a; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 987654321; const long long int INF = 123456789987654321; int N; vector<int> arr, chk, chk2; bool f(int l, int r) { for (int i = 0; i < min(l, N - r - 1); i++) { if (arr[i] != arr[N - i - 1]) return false; } chk = vector<int>(N, 0); for (int i = min(l, N - r - 1); i <= max(r, N - l - 1); i++) { chk[arr[i]]++; } chk2 = vector<int>(N, 0); int len = max(r, N - l - 1) - min(l, N - r - 1) + 1; if (len < 2 * (r - l + 1)) { for (int i = min(l, N - r - 1); i <= max(r, N - l - 1); i++) { if (i < l || r < i) { chk2[arr[i]]++; if (chk2[arr[i]] > chk[arr[i]] / 2) return false; } } } else { for (int i = min(l, N - r - 1); i < min(l, N - r - 1) + (r - l + 1); i++) { chk2[arr[i]]++; } for (int i = min(l, N - r - 1); i < min(l, N - r - 1) + (r - l + 1); i++) { chk2[arr[N - 1 - i]]--; } for (int i = 0; i < N; i++) { if (chk2[i]) return false; } for (int i = min(l, N - r - 1) + (r - l + 1); i <= max(r, N - l - 1) - (r - l + 1); i++) { if (arr[i] != arr[N - 1 - i]) return false; } } return true; } long long int ans = 0; int main() { scanf( %d , &N); arr.resize(N); chk = vector<int>(N, 0); for (int i = 0; i < N; i++) { scanf( %d , &arr[i]); chk[--arr[i]]++; } if (N == 1) { printf( 1 ); return 0; } int oddcnt = 0; for (int i = 0; i < N; i++) { if (chk[i] % 2) oddcnt++; } if (oddcnt > 1) { printf( 0 ); return 0; } int s = 0, e = N - 1; int idx; while (s <= e) { int m = (s + e) >> 1; if (f(0, m)) { idx = m; e = m - 1; } else s = m + 1; } s = 0, e = N - 1; int idx2; while (s <= e) { int m = (s + e) >> 1; if (f(m, N - 1)) { idx2 = m; s = m + 1; } else e = m - 1; } int len = 0; for (int i = 0; i < N / 2; i++) { if (arr[i] != arr[N - 1 - i]) break; len++; } if (len == N / 2) { printf( %I64d , (long long int)N * (N + 1) / 2); return 0; } long long int ans = len * len; if (idx < N - len) ans += (len + 1) * (N - len - idx); if (len <= idx2) ans += (len + 1) * (idx2 - len + 1); if (idx < N - len && len <= idx2) ans--; printf( %I64d , ans); } |
#include <bits/stdc++.h> using namespace std; int a[4]; int cmp(int x, int y) { return x > y; } int main() { int t; cin >> t; while (t--) { int ans = 0; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3, cmp); if (a[0]) { a[0]--; ans++; } if (a[1]) { a[1]--; ans++; } if (a[2]) { a[2]--; ans++; } if (a[0] && a[1]) { a[0]--, a[1]--; ans++; } if (a[0] && a[2]) { a[0]--, a[2]--; ans++; } if (a[1] && a[2]) { a[1]--, a[2]--; ans++; } if (a[0] && a[1] && a[2]) { ans++; } cout << ans << endl; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule
// Memory Writer
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule
// Memory Reader
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule
// Multi-port memory abstraction
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule
// Dual-Port L1 Memory Implementation
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module memcard #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
inout [3:0] mc_d,
inout mc_cmd,
output mc_clk
);
reg [10:0] clkdiv2x_factor;
reg cmd_tx_enabled;
reg cmd_tx_pending;
reg cmd_rx_enabled;
reg cmd_rx_pending;
reg cmd_rx_started;
reg [7:0] cmd_data;
reg dat_tx_enabled;
reg dat_tx_pending;
reg dat_rx_enabled;
reg dat_rx_pending;
reg dat_rx_started;
reg [31:0] dat_data;
reg [10:0] clkdiv2x_counter;
reg clkdiv2x_ce;
always @(posedge sys_clk) begin
if(sys_rst) begin
clkdiv2x_counter <= 11'd0;
clkdiv2x_ce <= 1'b0;
end else begin
clkdiv2x_counter <= clkdiv2x_counter + 1'b1;
clkdiv2x_ce <= 1'b0;
if(clkdiv2x_counter == clkdiv2x_factor) begin
clkdiv2x_counter <= 11'd0;
clkdiv2x_ce <= 1'b1;
end
end
end
wire clock_active = (~cmd_tx_enabled | cmd_tx_pending)
&(~cmd_rx_enabled | ~cmd_rx_pending)
&(~dat_tx_enabled | dat_tx_pending)
&(~dat_rx_enabled | ~dat_rx_pending);
reg clkdiv;
always @(posedge sys_clk) begin
if(sys_rst)
clkdiv <= 1'b0;
else if(clkdiv2x_ce & clock_active)
clkdiv <= ~clkdiv;
end
reg clkdiv_ce0;
reg clkdiv_ce;
always @(posedge sys_clk) begin
clkdiv_ce0 <= clkdiv2x_ce & clock_active & ~clkdiv;
clkdiv_ce <= clkdiv_ce0;
end
reg mc_cmd_r0;
reg mc_cmd_r1;
reg mc_cmd_r2;
always @(posedge sys_clk) begin
mc_cmd_r0 <= mc_cmd;
mc_cmd_r1 <= mc_cmd_r0;
mc_cmd_r2 <= mc_cmd_r1;
end
reg [3:0] mc_d_r0;
reg [3:0] mc_d_r1;
reg [3:0] mc_d_r2;
always @(posedge sys_clk) begin
mc_d_r0 <= mc_d;
mc_d_r1 <= mc_d_r0;
mc_d_r2 <= mc_d_r1;
end
wire csr_selected = csr_a[13:10] == csr_addr;
reg [2:0] cmd_bitcount;
reg [2:0] dat_bitcount;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
clkdiv2x_factor <= 11'd1023;
cmd_tx_enabled <= 1'b0;
cmd_tx_pending <= 1'b0;
cmd_rx_enabled <= 1'b0;
cmd_rx_pending <= 1'b0;
cmd_rx_started <= 1'b0;
cmd_data <= 8'd0;
dat_tx_enabled <= 1'b0;
dat_tx_pending <= 1'b0;
dat_rx_enabled <= 1'b0;
dat_rx_pending <= 1'b0;
dat_rx_started <= 1'b0;
dat_data <= 32'd0;
cmd_bitcount <= 3'd0;
dat_bitcount <= 3'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[2:0])
3'b000: csr_do <= clkdiv2x_factor;
3'b001: csr_do <= {dat_rx_enabled, dat_tx_enabled, cmd_rx_enabled, cmd_tx_enabled};
3'b010: csr_do <= {dat_rx_pending, dat_tx_pending, cmd_rx_pending, cmd_tx_pending};
3'b011: csr_do <= {dat_rx_started, cmd_rx_started};
3'b100: csr_do <= cmd_data;
3'b101: csr_do <= dat_data;
endcase
if(csr_we) begin
case(csr_a[2:0])
3'b000: clkdiv2x_factor <= csr_di[10:0];
3'b001: {dat_rx_enabled, dat_tx_enabled, cmd_rx_enabled, cmd_tx_enabled} <= csr_di[3:0];
3'b010: begin
if(csr_di[1]) begin
cmd_rx_pending <= 1'b0;
cmd_bitcount <= 3'd0;
end
if(csr_di[3]) begin
dat_rx_pending <= 1'b0;
dat_bitcount <= 3'd0;
end
end
3'b011: begin
if(csr_di[0])
cmd_rx_started <= 1'b0;
if(csr_di[1])
dat_rx_started <= 1'b0;
end
3'b100: begin
cmd_data <= csr_di[7:0];
cmd_tx_pending <= 1'b1;
cmd_bitcount <= 3'd0;
end
3'b101: begin
dat_data <= csr_di;
dat_tx_pending <= 1'b1;
dat_bitcount <= 3'd0;
end
endcase
end
end
if(clkdiv_ce) begin
if(cmd_tx_enabled|cmd_rx_started|~mc_cmd_r2) begin
cmd_data <= {cmd_data[6:0], mc_cmd_r2};
if(cmd_rx_enabled)
cmd_rx_started <= 1'b1;
end
if(cmd_tx_enabled|(cmd_rx_enabled & (cmd_rx_started|~mc_cmd_r2)))
cmd_bitcount <= cmd_bitcount + 3'd1;
if(cmd_bitcount == 3'd7) begin
if(cmd_tx_enabled)
cmd_tx_pending <= 1'b0;
if(cmd_rx_enabled)
cmd_rx_pending <= 1'b1;
end
if(dat_tx_enabled|dat_rx_started)
dat_data <= {dat_data[27:0], mc_d_r2};
if(dat_tx_enabled|dat_rx_started|(mc_d_r2 == 4'h0)) begin
if(dat_rx_enabled)
dat_rx_started <= 1'b1;
end
if(dat_tx_enabled|(dat_rx_enabled & dat_rx_started))
dat_bitcount <= dat_bitcount + 3'd1;
if(dat_bitcount == 3'd7) begin
if(dat_tx_enabled)
dat_tx_pending <= 1'b0;
if(dat_rx_enabled)
dat_rx_pending <= 1'b1;
end
end
end
end
assign mc_cmd = cmd_tx_enabled ? cmd_data[7] : 1'bz;
assign mc_d = dat_tx_enabled ? dat_data[31:28] : 4'bzzzz;
assign mc_clk = clkdiv;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_rows_V_channel1_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_rows_V_channel1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_rows_V_channel1_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_rows_V_channel1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 2e5 + 10; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; inline int read() { static char buf[1000000], *p1 = buf, *p2 = buf; register int x = false; register char ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; register bool sgn = false; while (ch != - && (ch < 0 || ch > 9 )) ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; if (ch == - ) sgn = true, ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; return sgn ? -x : x; } long long fpow(long long a, int b, int mod) { long long res = 1; for (; b > 0; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long h[N][2]; char s[N]; long long base[N]; int cnt[N]; long long calc(int L, int R) { return (h[R][L & 1] - h[L - 1][L & 1] * base[cnt[R] - cnt[L - 1]] % mod + mod) % mod; } int main() { int n, m; cin >> n; scanf( %s , s + 1); cin >> m; base[0] = 1; for (int i = 1; i <= n; i++) { base[i] = base[i - 1] * 998244353 % mod; cnt[i] = cnt[i - 1]; h[i][0] = h[i - 1][0]; h[i][1] = h[i - 1][1]; if (s[i] == 0 ) { cnt[i] = cnt[i - 1] + 1; h[i][0] = (h[i - 1][0] * 998244353 % mod + (i & 1) + 1) % mod; h[i][1] = (h[i - 1][1] * 998244353 % mod + (i & 1 ^ 1) + 1) % mod; } } while (m--) { int x, y, z; cin >> x >> y >> z; if (calc(x, x + z - 1) == calc(y, y + z - 1)) puts( YES ); else puts( NO ); } return 0; } |
//======================================================================
//
// tb_hc_core.v
// -------------
// Testbench for the HC block cipher core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_hc_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter HC_128_BIT_KEY = 0;
parameter HC_256_BIT_KEY = 1;
parameter HC_DECIPHER = 1'b0;
parameter HC_ENCIPHER = 1'b1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_init;
reg tb_next;
wire tb_ready;
reg [255 : 0] tb_iv;
reg [255 : 0] tb_key;
reg tb_keylen;
wire [31 : 0] tb_result;
wire tb_result_valid;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
hc_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.init(tb_init),
.next(tb_next),
.ready(tb_ready),
.iv(tb_iv),
.key(tb_key),
.keylen(tb_keylen),
.result(tb_result),
.result_valid(tb_result_valid)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("init = 0x%01x, next = 0x%01x", dut.init, dut.next);
$display("iv = 0x%032x ", dut.iv);
$display("keylen = 0x%01x, key = 0x%032x ", dut.keylen, dut.key);
$display("");
$display("ready = 0x%01x", dut.ready);
$display("result_valid = 0x%01x, result = 0x%08x", dut.result_valid, dut.result);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_init = 0;
tb_next = 0;
tb_iv = {8{32'h0}};
tb_key = {8{32'h0}};
tb_keylen = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
if (DUMP_WAIT)
begin
dump_dut_state();
end
end
end
endtask // wait_ready
//----------------------------------------------------------------
// wait_valid()
//
// Wait for the result_valid flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing a block and will in fact
// at some point set the flag.
//----------------------------------------------------------------
task wait_valid;
begin
while (!tb_result_valid)
begin
#(CLK_PERIOD);
end
end
endtask // wait_valid
//----------------------------------------------------------------
// hc_core_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : hc_core_test
$display(" -= Testbench for hc core started =-");
$display(" ================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
$display("HC 128 bit key tests");
$display("---------------------");
$display("");
$display("ECB 256 bit key tests");
$display("---------------------");
display_test_result();
$display("");
$display("*** HC core simulation done. ***");
$finish;
end // hc_core_test
endmodule // tb_hc_core
//======================================================================
// EOF tb_hc_core.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[101], ans = 0; cin >> n; bool flag = false; for (int i = 1; i <= n; i += 1) { cin >> a[i]; if (a[i] == 100) flag = true; ans += a[i]; } if (ans % 200 == 100) cout << NO << endl; else { if (ans % 400 == 0) cout << YES << endl; else if (flag) cout << YES << endl; else cout << NO << endl; } return 0; } |
module draw(
input clk,
input en,
input cls_en,
input [15 : 0] I,
input [10 : 0] start_pix,
input [3 : 0] start_nibbles,
output [ADDR_WIDTH - 1 : 0] mem_raddr,
input [DATA_WIDTH - 1 : 0] mem_d,
output busy,
output draw_out,
output col,
output hs_o,
output vs_o
);
localparam ST_IDLE = 0;
localparam ST_DRAW_SCREEN = 1;
localparam ST_DRAW_VRAM = 2;
localparam ST_DRAW_CLS = 3;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 12;
localparam VRAM_DATA_WIDTH = 2;
localparam VRAM_ADDR_WIDTH = 11;
localparam PIPE_LENGTH = 4;
reg [1 : 0] state_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr_pipe [PIPE_LENGTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] mem_d_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] q_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] d_pipe [PIPE_LENGTH - 1 : 0];
reg [PIPE_LENGTH - 1 : 0] we_pipe;
reg [2 : 0] ctr_pix_pipe [PIPE_LENGTH - 1 : 0];
reg [1 : 0] state = ST_IDLE;
reg [ADDR_WIDTH - 1 : 0] _mem_raddr = 0;
reg we = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr = 0;
wire [VRAM_DATA_WIDTH - 1 : 0] q;
reg [VRAM_DATA_WIDTH - 1 : 0] d = 0;
wire [VRAM_ADDR_WIDTH - 1 : 0] raddr, draw_vram_raddr, draw_screen_raddr;
reg [3 : 0] ctr_nib = 0;
reg [3 : 0] nibbles = 0;
reg [2 : 0] ctr_pix = 0;
reg [4 : 0] y = 0;
reg [5 : 0] x = 0, x0 = 0;
wire [4 : 0] y_screen;
wire [5 : 0] x_screen;
wire vs, hs;
wire hs_valid, vs_valid;
reg _col;
reg draw_vram = 0, draw_cls = 0;
reg _draw_out;
reg [PIPE_LENGTH - 1 : 0] pipe_vs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_vs = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] ctr_vram = 0;
assign draw_out = _draw_out;
assign vs_o = pipe_vs[3];
assign hs_o = pipe_hs[3];
assign col = _col;
assign raddr = state == ST_DRAW_VRAM ? draw_vram_raddr : draw_screen_raddr;
assign draw_vram_raddr = { {y} , {x} };
assign draw_screen_raddr = { {y_screen} , {x_screen} };
assign mem_raddr = _mem_raddr;
assign busy = vs | draw_vram
| (state_pipe[1] == ST_DRAW_VRAM);
always @ (posedge clk)
begin
if (pipe_vs_valid[2] & pipe_hs_valid[2])
begin
_draw_out <= q[0];
end
else
begin
_draw_out <= 0;
end
end // always @ (posedge clk)
always @ (vs_valid, hs_valid, hs, vs)
begin
pipe_vs_valid[0] <= vs_valid;
pipe_hs_valid[0] <= hs_valid;
pipe_vs[0] <= vs;
pipe_hs[0] <= hs;
end
always @ (posedge clk)
begin
pipe_vs_valid[PIPE_LENGTH - 1 : 1] <= pipe_vs_valid[PIPE_LENGTH - 2 : 0];
pipe_hs_valid[PIPE_LENGTH - 1 : 1] <= pipe_hs_valid[PIPE_LENGTH - 2 : 0];
pipe_vs[PIPE_LENGTH - 1 : 1] <= pipe_vs[PIPE_LENGTH - 2 : 0];
pipe_hs[PIPE_LENGTH - 1 : 1] <= pipe_hs[PIPE_LENGTH - 2 : 0];
we_pipe[PIPE_LENGTH - 1 : 1] <= we_pipe[PIPE_LENGTH - 2 : 0];
end
always @ (mem_d, state, we, waddr, q, d, ctr_pix)
begin
mem_d_pipe[0] <= mem_d;
state_pipe[0] <= state;
we_pipe[0] <= we;
waddr_pipe[0] <= waddr;
q_pipe[0] <= q;
d_pipe[0] <= d;
ctr_pix_pipe[0] <= ctr_pix;
end
genvar i;
generate
for (i = 1; i < PIPE_LENGTH; i = i + 1)
begin
always @ (posedge clk)
begin
mem_d_pipe[i] <= mem_d_pipe[i - 1];
state_pipe[i] <= state_pipe[i - 1];
waddr_pipe[i] <= waddr_pipe[i - 1];
q_pipe[i] <= q_pipe[i - 1];
d_pipe[i] <= d_pipe[i - 1];
ctr_pix_pipe[i] <= ctr_pix_pipe[i - 1];
end
end
endgenerate
always @ (posedge clk)
begin
case (state)
ST_IDLE:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (cls_en)
begin
state <= ST_DRAW_CLS;
end
else if (en)
begin
state <= ST_DRAW_VRAM;
end
end
ST_DRAW_VRAM:
begin
if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
state <= ST_IDLE;
end
else if (vs)
begin
state <= ST_DRAW_SCREEN;
end
end
ST_DRAW_SCREEN:
begin
if (~vs)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
ST_DRAW_CLS:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (~draw_cls)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
endcase
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (en)
begin
y <= start_pix[10 : 6];
x0 <= start_pix[5 : 0];
x <= start_pix[5 : 0];
nibbles <= start_nibbles;
end
else if (state == ST_DRAW_VRAM)
begin
if (ctr_pix == 0)
begin
y <= y + 1;
x <= x0;
end
else
begin
x <= x + 1;
end
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (state == ST_IDLE)
begin
ctr_pix <= 7;
end
else if (state == ST_DRAW_VRAM)
begin
ctr_pix <= ctr_pix - 1;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (state == ST_DRAW_VRAM)
begin
waddr <= draw_vram_raddr;
end
else
begin
waddr <= ctr_vram;
end
end
always @ (posedge clk)
begin
if (draw_cls)
begin
d <= 0;
end
else if (state_pipe[1] == ST_DRAW_VRAM)
begin
d[0] <= mem_d_pipe[1][ctr_pix_pipe[1]] ^ q[0];
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if ( (state_pipe[2] == ST_IDLE) | draw_cls )
begin
_col <= 0;
end
else if (state_pipe[2] == ST_DRAW_VRAM)
begin
if (q_pipe[1][0] == 1 & d[0] == 0)
begin
_col <= 1; // screen pix set to unset = collision
end
end
end
always @ (posedge clk)
begin
if (state == en)
begin
_mem_raddr <= I;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 1)
begin
_mem_raddr <= _mem_raddr + 1;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (en)
begin
draw_vram <= 1;
end
else if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
draw_vram <= 0;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
ctr_vram <= ctr_vram + draw_cls;
end
always @ (posedge clk)
begin
if (cls_en)
begin
draw_cls <= 1;
end
else if (ctr_vram == ((1 << VRAM_ADDR_WIDTH) - 2))
begin
draw_cls <= 0;
end
end
always @ (posedge clk)
begin
if (en)
begin
ctr_nib <= 0;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 0)
begin
ctr_nib <= ctr_nib + 1;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
we <= (state == ST_DRAW_VRAM) | (draw_cls);
end
dram_2048x2 vram (
.w_clk(clk),
.r_clk(clk),
.w_clk_en(1'b1),
.r_clk_en(1'b1),
.we(we_pipe[1]),
.waddr(waddr_pipe[1]),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
draw_screen draw_screen(
.clk(clk),
.x(x_screen),
.y(y_screen),
.vs(vs),
.vs_valid(vs_valid),
.hs(hs),
.hs_valid(hs_valid)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_2_V
`define SKY130_FD_SC_LS__DLRBN_2_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbn_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbn_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long arr[n]; int i; map<long long, int> mp; for (i = 0; i < n; i++) { int t; cin >> t; mp[t]++; } auto it = mp.begin(); int maxe = 0; while (it != mp.end()) { if (it->second > maxe) maxe = it->second; it++; } cout << n - maxe << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 50 + 5, maxL = (1 << 20) + 10; int N, L; char s[maxn][25]; bool vis[maxL]; long double F[maxL], R[25]; long long dask[maxL]; bool check(int tt, int k) { if (dask[tt] & (1LL << k)) return false; else return true; } long double dfs(int tt, int g) { if (g == 0) return 0.0; if (vis[tt]) return F[tt]; long double ret = 0.0; long double step = L - g + 1; for (int i = 0; i < L; i++) { if ((1 << i) & tt) continue; int nt = (1 << i) | tt; int wq = __builtin_popcountll(dask[nt] ^ dask[tt]); ret += step * R[g] * wq; ret += dfs(nt, g - 1); } vis[tt] = true; F[tt] = ret; return ret; } void Prepare() { memset(dask, 0, sizeof(dask)); for (int i = (1), _i = (N); i <= _i; i++) for (int j = (i + 1), _j = (N); j <= _j; j++) { int same = 0; for (int k = 0; k < L; k++) if (s[i][k] == s[j][k]) same |= (1 << k); dask[same] |= (1LL << j) | (1LL << i); } for (int i = (1 << L) - 1; i; i--) for (int k = 0; k < L; k++) if (i & (1 << k)) dask[i ^ (1 << k)] |= dask[i]; } int main() { for (; scanf( %d , &N) != EOF;) { for (int i = (1), _i = (N); i <= _i; i++) scanf( %s , s[i]); L = strlen(s[1]); int gg = L; R[L] = 1.0 / (long double)L; for (int i = (L - 1), _i = (1); i >= _i; i--) { gg--; R[i] = R[i + 1] / (long double)gg; } memset(vis, 0, sizeof(vis)); long double ans = 0.0; Prepare(); ans = dfs(0, L); ans /= (long double)N; printf( %.15lf n , (double)ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long sz(char *a) { long i = 0; while (*(a + i) != 0 ) i++; return i; } int main() { char *a = (char *)malloc(sizeof(char) * 1000001); char *b = (char *)malloc(sizeof(char) * 1000001); scanf( %1000000s , a); scanf( %1000000s , b); long a_size = sz(a); long b_size = sz(b); long j, i, a_adj, b_adj; for (i = 0; i < a_size; i++) if (a[i] != 0 ) break; a_size -= i; a_adj = i; i = 0; for (i = 0; i < b_size; i++) if (b[i] != 0 ) break; b_size -= i; b_adj = i; if (a_size > b_size) { printf( > n ); return 0; ; } if (b_size > a_size) { printf( < n ); return 0; ; } for (i = a_adj, j = b_adj; i <= a_size + a_adj, j <= b_size + b_adj; i++, j++) { if (a[i] > b[j]) { printf( > n ); return 0; ; } if (a[i] < b[j]) { printf( < n ); return 0; ; } } printf( = n ); free(a); free(b); return 0; ; } |
/* lab2_part2.v - 4-bit to decimal (0..15)
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part3 (SW, HEX0, HEX1, HEX2, HEX3);
input [17:0] SW;
output [0:6] HEX0, HEX1, HEX2, HEX3;
wire z;
wire [3:0] M, A;
assign A[3] = 0;
/*
Binary-to-decimal convertion values
+---+--+---+---++--+---+
|v3 |v2| v1| v0||d1| d0|
+---+--+---+---++--+---+
| 0 |0 | 0 | 0 ||0 | 0 |
+---+--+---+---++--+---+
| 0 |0 | 0 | 1 ||0 | 1 |
+---+--+---+---++--+---+
| 0 |0 | 1 | 0 ||0 | 2 |
+---+--+---+---++--+---+
| 0 |0 | 1 | 1 ||0 | 3 | 0
+---+--+---+---++--+---+ +-----+
| 0 |1 | 0 | 0 ||0 | 4 | 5| |1
+---+--+---+---++--+---+ | 6 |
| 0 |1 | 0 | 1 ||0 | 5 | +-----+
+---+--+---+---++--+---+ 4| |2
| 0 | 1| 1 | 0 ||0 | 6 | | |
+---+--+---+---++--+---+ +-----+
| 0 | 1| 1 | 1 ||0 | 7 | 3
+---+--+---+---++--+---+
| 1 |0 | 0 | 0 ||0 | 8 |
+---+--+---+---++--+---+
| 1 |0 | 0 | 1 ||0 | 9 |
+---+--+---+---++--+---+
| 1 |0 | 1 | 0 ||1 | 0 |
+---+--+---+---++--+---+
| 1 | 0| 1 | 1 ||1 | 1 |
+---+--+---+---++--+---+
| 1 |1 | 0 |0 ||1 | 2 |
+---+--+---+---++--+---+
| 1 | 1| 0 | 1 ||1 | 3 |
| | | | || | |
| 1 | 1| 1 | 0 ||1 | 4 |
+---+--+---+---++--+---+
| 1 |1 | 1 | 1 ||1 | 5 |
+---+--+---+---++--+---+
+------+
==> v3 | |==> m3
==> v2 | |==> m2
==> v1 | |==> m1
==> v0 | |==> m0
| |==> z
+------+
*/
comparator C0 (SW[3:0], z);
circuitA A0 (SW[3:0], A[2:0]);
mux_4bit_2to1 M0 (z, SW[3:0], A, M);
circuitB B0 (z, HEX1);
b2d_7seg S0 (M, HEX0);
endmodule
module b2d_7seg (X, SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
module comparator (V, z);
input [3:0] V;
output z;
assign z = (V[3] & (V[2] | V[1]));
endmodule
module circuitA (V, A);
input [2:0] V;
output [2:0] A;
assign A[0] = V[0];
assign A[1] = ~V[1];
assign A[2] = (V[2] & V[1]);
endmodule
module circuitB (z, SSD);
input z;
output [0:6] SSD;
assign SSD[0] = z;
assign SSD[1:2] = 2'b00;
assign SSD[3:5] = {3{z}};
assign SSD[6] = 1;
endmodule
module mux_4bit_2to1 (s, U, V, M);
// if ~s, send U
input s;
input [3:0] U, V;
output [3:0] M;
assign M = ({4{~s}} & U) | ({4{s}} & V);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(0.0) * 2.0; const double eps = 1e-12; const int step[8][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; template <class T> inline T abs1(T a) { return a < 0 ? -a : a; } template <class T> inline T max1(T a, T b) { return a > b ? a : b; } template <class T> inline T max1(T a, T b, T c) { return max1(max1(a, b), c); } template <class T> inline T max1(T a, T b, T c, T d) { return max1(max1(a, b, c), d); } template <class T> inline T max1(T a, T b, T c, T d, T e) { return max1(max1(a, b, c, d), e); } template <class T> inline T min1(T a, T b) { return a > b ? a : b; } template <class T> inline T min1(T a, T b, T c) { return min1(min1(a, b), c); } template <class T> inline T min1(T a, T b, T c, T d) { return min1(min1(a, b, c), d); } template <class T> inline T min1(T a, T b, T c, T d, T e) { return min1(min1(a, b, c, d), e); } template <class T> inline T lowb(T num) { return num & (-num); } inline int jud(double a, double b) { if (abs(a) < eps && abs(b) < eps) return 0; else if (abs1(a - b) / abs1(a) < eps) return 0; if (a < b) return -1; return 1; } template <typename t> inline int jud(t a, t b) { if (a < b) return -1; if (a == b) return 0; return 1; } template <typename it, typename t1> inline int find(t1 val, it a, int na, bool f_small = 1, bool f_lb = 1) { int be = 0, en = na - 1; if (*a <= *(a + na - 1)) { if (f_lb == 0) while (be < en) { int mid = (be + en + 1) / 2; if (jud(*(a + mid), val) != 1) be = mid; else en = mid - 1; } else while (be < en) { int mid = (be + en) / 2; if (jud(*(a + mid), val) != -1) en = mid; else be = mid + 1; } if (f_small && jud(*(a + be), val) == 1) be--; if (!f_small && jud(*(a + be), val) == -1) be++; } else { if (f_lb) while (be < en) { int mid = (be + en + 1) / 2; if (jud(*(a + mid), val) != -1) be = mid; else en = mid - 1; } else while (be < en) { int mid = (be + en) / 2; if (jud(*(a + mid), val) != 1) en = mid; else be = mid + 1; } if (!f_small && jud(*(a + be), val) == -1) be--; if (f_small && jud(*(a + be), val) == 1) be++; } return be; } inline int bitnum(unsigned int nValue) { return __builtin_popcount(nValue); } inline int bitnum(int nValue) { return __builtin_popcount(nValue); } inline int bitnum(unsigned long long nValue) { return __builtin_popcount(nValue) + __builtin_popcount(nValue >> 32); } inline int bitnum(long long nValue) { return __builtin_popcount(nValue) + __builtin_popcount(nValue >> 32); } inline int bitmaxl(unsigned int a) { if (a) return 0; return 32 - __builtin_clz(a); } inline int bitmaxl(int a) { if (a) return 0; return 32 - __builtin_clz(a); } inline int bitmaxl(unsigned long long a) { int temp = a >> 32; if (temp) return 32 - __builtin_clz(temp) + 32; return bitmaxl(int(a)); } inline int bitmaxl(long long a) { int temp = a >> 32; if (temp) return 32 - __builtin_clz(temp) + 32; return bitmaxl(int(a)); } long long pow(long long n, long long m, long long mod = 0) { if (m < 0) return 0; long long ans = 1; long long k = n; while (m) { if (m & 1) { ans *= k; if (mod) ans %= mod; } k *= k; if (mod) k %= mod; m >>= 1; } return ans; } const int maxn = (1 << 24) + 10; int cnt[maxn], n; int arr[10010]; int main() { ios_base::sync_with_stdio(0); scanf( %d , &n); for (int i = 0; i < n; i++) { char str[10]; scanf( %s , str); int rmask = 0; for (int j = 0; j < 3; j++) rmask |= 1 << (str[j] - a ); rmask = (1 << 24) - 1 - rmask; arr[i] = rmask; cnt[rmask]++; } long long ans = 0; for (int i = 23; i >= 0; i--) { int mask = 1 << 24; mask -= 1 + (1 << i); for (int j = mask; j >= 0; j = (j - 1) & mask) { cnt[j] += cnt[j + (1 << i)]; if (j == 0) break; } } for (int i = (1 << 24) - 1; i >= 0; i--) { ans ^= (n - cnt[i]) * (n - cnt[i]); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937_64 rng(time(0)); const long double eps = 1e-15; #define rep(i, a, b) for(int i = a; i < (b); ++i) #define trav(a, x) for(auto& a : x) #define all(x) x.begin(), x.end() #define sz(x) (int)(x).size() typedef long long ll; typedef pair<int, int> pii; typedef pair<ll,ll> pll; typedef vector<int> vi; const int mn=300+10; const ll mod=1e9+7; ll po(ll a,ll b=mod-2){ ll ans=1; for(;b;b>>=1,a*=a,a%=mod)if(b&1)ans*=a,ans%=mod; return ans; } ll c[mn],b[mn]; ll ans[mn*2]; ll dp[2][10100]; int main() { cin.tie(0); cin.sync_with_stdio(0); int n; cin>>n; for(int i=0;i<n;i++)cin>>c[i]; for(int i=1;i<n;i++)cin>>b[i],b[i]+=b[i-1]; for(int i=1;i<n;i++)b[i]+=b[i-1]; int ma=INT_MAX,mi=INT_MAX,sa=0,si=0; for(int i=0;i<n;i++){ sa+=c[i]; si+=0; ma=min(ll(ma),(sa-b[i])/(i+1)+1); mi=min(ll(mi),(si-b[i])/(i+1)-1); } //cerr<<mi<< <<ma<<endl; for(int m=mi;m<=ma;m++){ memset(dp,0,sizeof(dp)); dp[0][0]=1; for(int i=0;i<n;i++){ ll lim = m*(i+1)+b[i]; //cerr<<lim<<endl; for(int j=1;j<10100;j++)dp[0][j]+=dp[0][j-1],dp[0][j]%=mod; for(int j=0;j<10100;j++){ dp[1][j]=(dp[0][j]-((j>=c[i]+1)?dp[0][j-c[i]-1]:0))%mod; } for(int j=0;j<min(lim,ll(10100));j++)dp[1][j]=0; memcpy(dp[0],dp[1],sizeof(dp[0])); memset(dp[1],0,sizeof(dp[1])); } for(int i=0;i<10100;i++)ans[m-mi]+=dp[0][i],ans[m-mi]%=mod; if(ans[m-mi]<0)ans[m-mi]+=mod; } int q; cin>>q; ll aa=1; for(int i=0;i<n;i++)aa*=c[i]+1,aa%=mod; for(int i=0;i<q;i++){ ll x; cin>>x; if(x<mi){ printf( %lld n ,aa); } else if(x>ma)printf( 0 n ); else printf( %lld n ,ans[x-mi]); } } |
#include <bits/stdc++.h> using namespace std; long long n, k; long long quickpow(long long x, long long y) { long long res = 1; for (; y; y >>= 1, x *= x, x %= 1000003) if (y & 1) res *= x, res %= 1000003; return res; } int main() { scanf( %I64d %I64d , &n, &k); if (n < 62 && k > (1LL << n)) printf( 1 1 n ); else { long long A = 1, t = quickpow(2, n), cnt = n; for (int y = 1; y < 62; y++) cnt += (k - 1) / (1LL << y); if (k < 1000003) { for (long long i = 1; i <= k; i++) A = A * (t - i + 1000003 + 1) % 1000003; A = A * quickpow(quickpow(2, 1000003 - 2), cnt) % 1000003; } else A = 0; long long B = quickpow(quickpow(2, n), k) * quickpow(quickpow(2, 1000003 - 2), cnt) % 1000003; printf( %I64d %I64d n , (B - A + 1000003) % 1000003, B); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/29/2016 09:39:31 PM
// Design Name:
// Module Name: new_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module new_block(
input wire [5:0] block_in,
input wire up_direction,
input wire direction,
input wire [9:0] relative_xpos,
input wire [8:0] relative_ypos,
output reg [5:0] block_out,
output reg write_enable,
output reg new_point
);
always @* begin
if(block_in == GY) begin
new_point = 1;
block_out = B;
write_enable = 1;
end
else if(((relative_xpos % 40) < 20) && (direction == 0)) begin
if(block_in == D) begin
if(up_direction) begin
new_point = 1;
block_out = DY;
write_enable = 1;
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(block_in == J) begin
new_point = 0;
if(up_direction) begin
block_out = B;
write_enable = 1;
end
else begin
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(((relative_xpos % 40) >= 20) && (direction == 1)) begin
if(block_in == D) begin
if(up_direction) begin
new_point = 1;
block_out = DY;
write_enable = 1;
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(block_in == J) begin
new_point = 0;
if(up_direction) begin
block_out = B;
write_enable = 1;
end
else begin
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
localparam A = 1 ;
localparam B = 0 ;
localparam C = 2 ;
localparam D = 3 ;
localparam E = 4 ;
localparam F = 5 ;
localparam G = 6 ;
localparam H = 7 ;
localparam I = 8 ;
localparam J = 9 ;
localparam K = 10 ;
localparam L = 11 ;
localparam M = 12 ;
localparam N = 13 ;
localparam O = 14 ;
localparam P = 15 ;
localparam Q = 16 ;
localparam R = 17 ;
localparam S = 18 ;
localparam T = 19 ;
localparam U = 20 ;
localparam V = 21 ;
localparam W = 22 ;
localparam X = 23 ;
localparam Y = 24 ;
localparam Z = 25 ;
localparam AY = 26 ;
localparam IY = 27 ;
localparam GY = 28 ;
localparam KY = 29 ;
localparam PY = 30 ;
localparam TY = 31 ;
localparam UY = 32 ;
localparam WY = 33 ;
localparam DY = 34 ;
localparam BY = 35 ;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_M_V
`define SKY130_FD_SC_LP__NOR4_M_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_m (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_m (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, M = (1 << 20) + 5; template <typename T> void read(T &x) { bool neg = false; unsigned char c = getchar(); for (; (c ^ 48) > 9; c = getchar()) if (c == - ) neg = true; for (x = 0; (c ^ 48) < 10; c = getchar()) x = (x << 3) + (x << 1) + (c ^ 48); if (neg) x = -x; } struct line { int next, to; } e[N]; int n, m, hd[N], cnt, k, s[25], t[25], f[N], a[M], pop[M]; bool iss[N], ist[N]; void adline(int u, int v) { e[cnt].to = v; e[cnt].next = hd[u]; hd[u] = cnt++; } void dfs(int u) { if (f[u]) return; for (int i = hd[u]; ~i; i = e[i].next) { int v = e[i].to; dfs(v); f[u] |= f[v]; } } int main() { read(n); read(m); for (int i = 0, i_end = n; i < i_end; ++i) hd[i] = -1, iss[i] = ist[i] = true; for (int i = 0, i_end = m; i < i_end; ++i) { int u, v; read(u); read(v); adline(--u, --v); ist[u] = false; iss[v] = false; } for (int i = 0, i_end = n; i < i_end; ++i) if (iss[i]) s[k++] = i; k = 0; for (int i = 0, i_end = n; i < i_end; ++i) if (ist[i]) t[k++] = i; for (int i = 0, i_end = k; i < i_end; ++i) f[t[i]] = 1 << i; for (int i = 0, i_end = k; i < i_end; ++i) dfs(s[i]), a[1 << i] = f[s[i]]; for (int i = 1, i_end = 1 << k; i < i_end; ++i) pop[i] = pop[i ^ (i & -i)] + 1; for (int i = 1, i_end = (1 << k) - 1; i < i_end; ++i) { a[i] = a[i & -i] | a[i ^ (i & -i)]; if (pop[a[i]] <= pop[i]) return puts( NO ), 0; } puts( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; unsigned long long a[n], M; for (int i = 0; i < n; ++i) { cin >> a[i]; } stack<unsigned long long> s; M = *max_element(a, a + n); for (int i = 0; i < n; ++i) { a[i] = (M - a[i]) % 2; if (s.empty() || s.top() != a[i]) s.push(a[i]); else s.pop(); } bool ans2 = false; for (int i = 0; i < n - 1 && !ans2; ++i) { ans2 = ans2 || (a[i] == a[i + 1]); } bool all1 = true, all0 = true; while (!s.empty()) { all0 = all0 && (s.top() == 0); all1 = all1 && (s.top() == 1); s.pop(); } bool ans = all0 || all1; cout << (ans ? YES : NO ) << endl; return 0; } |
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
module io_fifo
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src_clk,
input wire snk_clk,
input wire reset,
// SRC_0
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk_clk, reset, i0)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
// SRC regs
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = 0;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ro0_c_red (ro0_src, ro0_dst, ro0_dat, ro0_redun);
// SNK_0 regs
reg [0:0] ri0_cks_done = `NS_OFF;
reg [0:0] ri0_ack = `NS_OFF;
reg [DSZ-1:0] ri0_ck_dat = 0;
// CHECK regs
reg [DSZ-1:0] r_0_ck_dat = 15;
reg [DSZ-1:0] r_1_ck_dat = 15;
wire [RSZ-1:0] i0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ri0_c_red (i0_src, i0_dst, i0_dat, i0_redun);
//SRC_0
always @(posedge src_clk)
begin
if(! ro0_busy) begin
ro0_busy <= `NS_ON;
if(ro0_dat > 15) begin
ro0_err <= `NS_ON;
end
/*if(ro0_dat < 0) begin
ro0_err <= `NS_ON;
end*/
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
if(ro0_busy) begin
if((! ro0_req) && (! o0_ckd_ack)) begin
ro0_red <= ro0_redun;
ro0_req <= `NS_ON;
end
if(ro0_req && o0_ckd_ack) begin
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
ro0_busy <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
end
//SNK_0
always @(posedge snk_clk)
begin
//rg_dbg_leds[3:3] <= 1;
if(! ri0_cks_done && i0_ckd_req && (! ri0_ack)) begin
if(! rg_dbg_leds[2:2]) begin
if(i0_dat > 15) begin
rg_dbg_leds[2:2] <= `NS_ON;
end
/*if(i0_dat < 0) begin
rg_dbg_leds[2:2] <= `NS_ON;
end*/
end
if(! rg_dbg_leds[0:0] && (i0_src == 0)) begin
if(i0_red != i0_redun) begin
rg_dbg_leds[0:0] <= `NS_ON;
end
else
if((r_0_ck_dat <= 14) && ((r_0_ck_dat + 1) != i0_dat)) begin
rg_dbg_leds[0:0] <= `NS_ON;
rg_dbg_disp0 <= i0_dat[3:0];
rg_dbg_disp1 <= r_0_ck_dat[3:0];
end else begin
r_0_ck_dat <= i0_dat;
end
end
if(! rg_dbg_leds[1:1] && (i0_src == 1)) begin
if(i0_red != i0_redun) begin
rg_dbg_leds[1:1] <= `NS_ON;
end
else
if((r_1_ck_dat <= 14) && ((r_1_ck_dat + 1) != i0_dat)) begin
rg_dbg_leds[1:1] <= `NS_ON;
rg_dbg_disp0 <= i0_dat[3:0];
rg_dbg_disp1 <= r_1_ck_dat[3:0];
end else begin
r_1_ck_dat <= i0_dat;
end
end
ri0_cks_done <= `NS_ON;
ri0_ck_dat <= i0_dat;
end
if(ri0_cks_done && i0_ckd_req && (! ri0_ack)) begin
ri0_cks_done <= `NS_OFF;
ri0_ack <= `NS_ON;
end
if((! i0_ckd_req) && ri0_ack) begin
ri0_ack <= `NS_OFF;
end
end
//SRC_0
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = ri0_ack;
`NS_ASSIGN_OUT_DBG(dbg, rg_dbg)
endmodule
|
/*
* Instruction decoder for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_decode (
input clk,
input rst,
input [7:0] opcode,
input [7:0] modrm,
input rep,
input block,
input exec_st,
input div_exc,
input ld_base,
input div,
input tfl,
output tflm,
output need_modrm,
output need_off,
output need_imm,
output off_size,
output imm_size,
input [2:0] sop_l,
input intr,
input ifl,
output iflm,
output reg inta,
output reg ext_int,
input nmir,
output reg nmia,
input wr_ss,
output iflss,
// to microcode
output [`MICRO_ADDR_WIDTH-1:0] seq_addr,
output [3:0] src,
output [3:0] dst,
output [3:0] base,
output [3:0] index,
output [1:0] seg,
output [2:0] f,
// from microcode
input end_seq
);
// Net declarations
wire [`MICRO_ADDR_WIDTH-1:0] base_addr;
reg [`MICRO_ADDR_WIDTH-1:0] seq;
reg dive;
reg tfle;
reg tfld;
reg ifld;
reg iflssd;
reg old_ext_int;
reg [4:0] div_cnt;
// Module instantiations
zet_opcode_deco opcode_deco (opcode, modrm, rep, sop_l, base_addr, need_modrm,
need_off, need_imm, off_size, imm_size, src, dst,
base, index, seg);
// Assignments
assign seq_addr = (tfle ? `INTT : (dive ? `INTD
: (ext_int ? (rep ? `EINTP : `EINT) : base_addr))) + seq;
assign f = opcode[7] ? modrm[5:3] : opcode[5:3];
assign iflm = ifl & ifld;
assign tflm = tfl & tfld;
assign iflss = !wr_ss & iflssd;
// Behaviour
always @(posedge clk)
ifld <= rst ? 1'b0 : (exec_st ? ifld : ifl);
always @(posedge clk)
tfld <= rst ? 1'b0 : (exec_st ? tfld : tfl);
always @(posedge clk)
if (rst)
iflssd <= 1'b0;
else
begin
if (!exec_st)
iflssd <= 1'b1;
else if (wr_ss)
iflssd <= 1'b0;
end
// seq
always @(posedge clk)
seq <= rst ? `MICRO_ADDR_WIDTH'd0
: block ? seq
: end_seq ? `MICRO_ADDR_WIDTH'd0
: |div_cnt ? seq
: exec_st ? (seq + `MICRO_ADDR_WIDTH'd1) : `MICRO_ADDR_WIDTH'd0;
// div_cnt - divisor counter
always @(posedge clk)
div_cnt <= rst ? 5'd0
: ((div & exec_st) ? (div_cnt==5'd0 ? 5'd18 : div_cnt - 5'd1) : 5'd0);
// dive
always @(posedge clk)
if (rst) dive <= 1'b0;
else dive <= block ? dive
: (div_exc ? 1'b1 : (dive ? !end_seq : 1'b0));
// tfle
always @(posedge clk)
if (rst) tfle <= 1'b0;
else tfle <= block ? tfle
: ((((tflm & !tfle) & iflss) & exec_st & end_seq) ? 1'b1 : (tfle ? !end_seq : 1'b0));
// ext_int
always @(posedge clk)
if (rst) ext_int <= 1'b0;
else ext_int <= block ? ext_int
: ((((nmir | (intr & iflm)) & iflss) & exec_st & end_seq) ? 1'b1
: (ext_int ? !end_seq : 1'b0));
// old_ext_int
always @(posedge clk) old_ext_int <= rst ? 1'b0 : ext_int;
// inta
always @(posedge clk)
inta <= rst ? 1'b0 : (!nmir & (!old_ext_int & ext_int));
// nmia
always @(posedge clk)
nmia <= rst ? 1'b0 : (nmir & (!old_ext_int & ext_int));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c, d, e, f, g; cin >> a >> b >> c >> d >> e >> f; if (a[0] == b[0] || a[0] == b[1] || a[0] == c[0] || a[0] == c[1] || a[0] == d[0] || a[0] == d[1] || a[0] == e[0] || a[0] == e[1] || a[0] == f[0] || a[0] == f[1] || a[1] == b[0] || a[1] == b[1] || a[1] == c[0] || a[1] == c[1] || a[1] == d[0] || a[1] == d[1] || a[1] == e[0] || a[1] == e[1] || a[1] == f[0] || a[1] == f[1]) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int ans, n; vector<pair<int, int> > vec; string s, t; int lcp1[5005][5005]; int lcp2[5005][5005]; void LCP(string &s, string &t, int lcp[5005][5005]) { for (int i = (int)s.size() - 1; i >= 0; i--) { for (int j = (int)t.size() - 1; j >= 0; j--) { if (s[i] == t[j]) { lcp[i][j] = lcp[i + 1][j + 1] + 1; } else { lcp[i][j] = 0; } } } } void solve() { LCP(s, t, lcp1); reverse(s.begin(), s.end()); LCP(s, t, lcp2); for (int ti = 0; ti < t.size();) { int mx1 = 0, mx1_si = -1; int mx2 = 0, mx2_si = -1; for (int si = 0; si < s.size(); si++) { if (mx1 < lcp1[si][ti]) { mx1 = lcp1[si][ti]; mx1_si = si; } if (mx2 < lcp2[si][ti]) { mx2 = lcp2[si][ti]; mx2_si = si; } } if (mx1 == 0 && mx2 == 0) { ans = -1; break; } else if (mx1 >= mx2) { ans++; vec.push_back(pair<int, int>(mx1_si + 1, mx1_si + mx1 - 1 + 1)); ti += mx1; } else { ans++; vec.push_back(pair<int, int>(n - mx2_si, n - (mx2_si + mx2 - 1))); ti += mx2; } } cout << ans << endl; for (int i = 0; i < (ans); i++) { cout << vec[i].first << << vec[i].second << endl; } } int main() { cin >> s; cin >> t; n = (int)s.size(); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_1_V
`define SKY130_FD_SC_HD__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_1_V
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename L> inline bool smax(T &x, L y) { return x < y ? (x = y, true) : false; } template <typename T, typename L> inline bool smin(T &x, L y) { return y < x ? (x = y, true) : false; } constexpr int MAXN = 1e5 + 15; int n; int a[MAXN]; int ttime[MAXN]; stack<int> dq; int mx; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { ttime[i] = 1; while (!dq.empty() && a[i] > a[dq.top()]) { smax(ttime[i], ttime[dq.top()] + 1); dq.pop(); } if (!dq.empty()) { smax(mx, ttime[i]); } else { ttime[i] = 1e6 + 15; } dq.push(i); } return cout << mx << n , false; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 6010; const int mod = 1000000007; int n; long long k[MAXN], k2[MAXN]; int main() { string asd; string asd2; cin >> asd; cin >> asd2; n = ((int)(asd2.size())); long long res = 0; for (int i = 0; i < ((int)(asd.size())); i++) { for (int j = 0; j < ((int)(asd2.size())); j++) { if (asd2[j] == asd[i]) { k2[j] = (k2[j] + k[j - 1] + 1) % mod; } k2[j + 1] = (k2[j + 1] + k2[j]) % mod; } res = (res + k2[n]) % mod; for (int j = 0; j < ((int)(asd2.size())); j++) k[j] = k2[j]; memset(k2, 0, sizeof k2); } cout << res << endl; return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_instance_index = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_ir_width = 2,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_mfg_id = 70,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_action = "",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_n_scan = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_total_length = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_type_id = 34,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y; long long a[300010]; vector<long long> fac, facn; vector<int> facx, facy; vector<pair<int, int> > facv; vector<long long> check; int n; long long sum[300010]; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } void factorize(long long val) { for (long long i = 2; i <= val && i <= 1000000ll; i++) if (val % i == 0) { fac.push_back(i); while (val % i == 0) val /= i; } if (val > 1) { long long q = (long long)(sqrt(val)); if (q * q == val) { fac.push_back(q); return; } for (int i = 1; i <= n; i++) check.push_back(a[i]); check.push_back(x); check.push_back(y); long long g = val; for (int i = 0; i < check.size(); i++) { g = gcd(val, check[i]); if (g != 1 && g != val) { if (g < val / g) { fac.push_back(g); fac.push_back(val / g); } else { fac.push_back(val / g); fac.push_back(g); } return; } } fac.push_back(val); } } int main() { scanf( %d%I64d%I64d , &n, &x, &y); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); factorize(y); if (y % x) { printf( 0 ); return 0; } for (int i = 0; i < fac.size(); i++) facv.push_back(make_pair(0, 0)); long long x1 = x; long long chunhua = y; for (int i = 0; i < fac.size(); i++) { int cnt = 0; while (x1 % fac[i] == 0) { x1 /= fac[i]; cnt++; } facv[i].first = cnt; } for (int i = 0; i < fac.size(); i++) { int cnt = 0; while (chunhua % fac[i] == 0) { chunhua /= fac[i]; cnt++; } facv[i].second = cnt; } for (int i = 0; i < fac.size(); i++) { if (facv[i].first != facv[i].second) { facn.push_back(fac[i]); facx.push_back(facv[i].first); facy.push_back(facv[i].second); } } for (int i = 1; i <= n; i++) { if (a[i] % x) continue; long long val = a[i]; int mask = 0; for (int j = 0; j < facn.size(); j++) { int cnt = 0; while (val % facn[j] == 0) { val /= facn[j]; cnt++; } mask += ((cnt > facx[j]) << j); } sum[mask]++; } for (int i = 0; i < facn.size(); i++) for (int mask = 0; mask < (1 << facn.size()); mask++) if (mask & (1 << i)) sum[mask] += sum[mask - (1 << i)]; long long ans = 0; for (int i = 1; i <= n; i++) { if (y % a[i]) continue; long long val = a[i]; int mask = 0; for (int j = 0; j < facn.size(); j++) { int cnt = 0; while (val % facn[j] == 0) { val /= facn[j]; cnt++; } mask += ((cnt < facy[j]) << j); } ans += sum[(1 << facn.size()) - mask - 1]; } printf( %I64d , ans); } |
//////////////////////////////////////////////////////////////////////
//// ////
//// updateCRC16.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
input rstCRC;
input CRCEn;
input [7:0] dataIn;
input clk;
input rst;
output [15:0] CRCResult;
output ready;
wire rstCRC;
wire CRCEn;
wire [7:0] dataIn;
wire clk;
wire rst;
reg [15:0] CRCResult;
reg ready;
reg doUpdateCRC;
reg [7:0] data;
reg [3:0] i;
always @(posedge clk)
begin
if (rst == 1'b1 || rstCRC == 1'b1) begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
CRCResult <= 16'hffff;
ready <= 1'b1;
end
else
begin
if (doUpdateCRC == 1'b0)
begin
if (CRCEn == 1'b1) begin
doUpdateCRC <= 1'b1;
data <= dataIn;
ready <= 1'b0;
end
end
else begin
i <= i + 1'b1;
if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
end
else begin
CRCResult <= {1'b0, CRCResult[15:1]};
end
data <= {1'b0, data[7:1]};
if (i == 4'h7)
begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
ready <= 1'b1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> graph[5001]; bool subset[5001][5001]; set<pair<int, int>> ans_pairs; vector<int> child_nodes(5001, -1); int total_nodes; void insert_into_answer(int network1, int network2) { if (network1 != 0 && network2 != 0) { ans_pairs.insert({network1, network2}); ans_pairs.insert({network2, network1}); } return; } bool isSubsetSum(vector<int> &set, int n, int sum) { for (int i = 0; i <= set.size(); i++) subset[i][0] = true; for (int j = 1; j <= sum; j++) subset[0][j] = false; for (int i = 1; i <= n; i++) { for (int j = 1; j <= sum; j++) { if (j < set[i - 1]) subset[i][j] = subset[i - 1][j]; if (j >= set[i - 1]) subset[i][j] = subset[i - 1][j] || subset[i - 1][j - set[i - 1]]; } } return subset[n][sum]; } int dfs(int id, int parent) { if (child_nodes[id] != -1) { return child_nodes[id]; } if (graph[id].size() == 0) { return child_nodes[id] = 1; } int temp = 0; for (long long i = 0; i < graph[id].size(); i++) { if (graph[id][i] != parent) { temp += dfs(graph[id][i], id); } } return child_nodes[id] = temp + 1; } void solve(int id, int parent) { insert_into_answer(child_nodes[id] - 1, total_nodes - child_nodes[id]); vector<int> childs_to_adjacent; for (long long i = 0; i < graph[id].size(); i++) { if (graph[id][i] != parent) { childs_to_adjacent.push_back(child_nodes[graph[id][i]]); } } isSubsetSum(childs_to_adjacent, childs_to_adjacent.size(), child_nodes[id]); int child_length = childs_to_adjacent.size(); for (long long i = 1; i < child_nodes[id]; i++) { if (subset[child_length][i]) { insert_into_answer(i, total_nodes - i - 1); } } for (long long i = 0; i < graph[id].size(); i++) { if (graph[id][i] != parent) { solve(graph[id][i], id); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> total_nodes; int x, y; for (long long i = 1; i < total_nodes; i++) { cin >> x >> y; graph[x - 1].push_back(y - 1); graph[y - 1].push_back(x - 1); } int a = dfs(0, -1); solve(0, -1); cout << ans_pairs.size() << endl; for (auto it : ans_pairs) { cout << it.first << << it.second << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T, size_t SZ> void pr(const array<T, SZ>& x); template <class T> void pr(const vector<T>& x); template <class T> void pr(const set<T>& x); template <class T1, class T2> void pr(const map<T1, T2>& x); template <class T> void pr(const T& x) { cout << x; } template <class Arg, class... Args> void pr(const Arg& first, const Args&... rest) { pr(first); pr(rest...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T> void prContain(const T& x) { pr( { ); bool fst = 1; for (auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } template <class T, size_t SZ> void pr(const array<T, SZ>& x) { prContain(x); } template <class T> void pr(const vector<T>& x) { prContain(x); } template <class T> void pr(const set<T>& x) { prContain(x); } template <class T1, class T2> void pr(const map<T1, T2>& x) { prContain(x); } void ps() { pr( n ); } template <class Arg, class... Args> void ps(const Arg& first, const Args&... rest) { pr(first, ); ps(rest...); } template <typename T> int remin(T& a, const T& b) { if (b < a) { a = b; return true; } return false; } template <typename T> int remax(T& a, const T& b) { if (b > a) { a = b; return true; } return false; } int n; int G[5005][5005]; short int nxt[5005][5005]; vector<unsigned short int> H[5005]; void dfs_parent(int from, vector<int>& p, int parent = -1) { for (auto to : H[from]) if (to != parent) { p[to] = from; dfs_parent(to, p, from); } } void dfs(int u, int v, int w, const vector<int>& p) { while (u != v) { int n = p[v]; remax(G[v][n], w); remax(G[n][v], w); v = n; } } void check(int u, int v, int w, const vector<int>& p) { int exp = 1E9; while (u != v) { int n = p[v]; if (G[v][n] == -1) { G[v][n] = 1000000; G[n][v] = 1000000; } remin(exp, G[v][n]); v = n; } if (exp != w) { printf( -1 n ); exit(0); } } int main(int argc, const char** argv) { scanf( %d , &n); vector<pair<int, int>> edges; for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d%d , &u, &v); --u, --v; G[u][v] = -1; G[v][u] = -1; edges.emplace_back(u, v); H[u].push_back(v); H[v].push_back(u); } vector<vector<int>> p(n, vector<int>(n, -1)); for (int u = 0; u < n; ++u) { dfs_parent(u, p[u]); } int q; scanf( %d , &q); vector<pair<pair<int, int>, int>> qu(q); for (int qq = 0; qq < q; ++qq) { int u, v, w; scanf( %d%d%d , &u, &v, &w); --u, --v; qu[qq] = make_pair(pair<int, int>(u, v), w); dfs(u, v, w, p[u]); } for (auto [c, w] : qu) { check(c.first, c.second, w, p[c.first]); } vector<int> ans(n - 1); for (int i = 0; i < n - 1; ++i) { int u = edges[i].first; int v = edges[i].second; int mn = min(u, v); int mx = max(u, v); printf( %d , G[mn][mx] == -1 ? 1000000 : G[mn][mx]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; string s; map<char, int> u; int main() { cin >> s >> s; for (auto x : s) ++u[x]; if (u.size() == 1) return puts( Yes ), 0; for (auto& x : u) if (x.second >= 2) return puts( Yes ), 0; puts( No ); } |
module spiSlave #(
parameter WIDTH = 8
)(
input clk,
input SS,
input SCLK,
input MOSI,
output reg MISO = 0,
input [WIDTH - 1:0] byteTX,
input newTXData,
output reg [WIDTH - 1:0] byteRX = 0,
output reg newSPIData = 0,
output wire busy
);
reg txCaptured = 0;
reg rxCaptured = 1;
reg [1:0] SSShiftReg = 2'b11;
reg [1:0] SCLKShiftReg = 0;
reg [WIDTH - 1:0] byteTXBuffer;
reg [WIDTH - 1:0] byteRXBuffer = 8'b0;
assign busy = !rxCaptured || txCaptured;
always@(posedge clk) begin
newSPIData <= 0 ;
SSShiftReg <= {SSShiftReg[0], SS};
if(SSShiftReg == 2'd0) begin
rxCaptured <= 0;
MISO <= byteTXBuffer[WIDTH-1];
SCLKShiftReg <= {SCLKShiftReg[0], SCLK};
if(SCLKShiftReg == 2'b01)
byteRXBuffer <= {byteRXBuffer[WIDTH-2:0], MOSI};
else if(SCLKShiftReg == 2'b10)
byteTXBuffer <= {byteTXBuffer[WIDTH-2:0], 1'b0};
end
else if(SSShiftReg == 2'b11 && !rxCaptured) begin
txCaptured <= 0;
newSPIData <= 1;
rxCaptured <= 1;
byteRX <= byteRXBuffer;
end
if(newTXData) begin
txCaptured <= 1;
byteTXBuffer <= byteTX;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; int dp[17][1 << 16][2][2]; int main() { ios::sync_with_stdio(0); cin.tie(0); for (int i = 0; i < 17; i++) { for (int j = 0; j < (1 << 16); j++) { for (int k = 0; k < 2; k++) { for (int l = 0; l < 2; l++) { dp[i][j][k][l] = -inf; } } } } int n, k; cin >> n >> k; vector<int> good(1 << n); while (k--) { int x; cin >> x; x--; good[x] = true; } for (int i = 0; i < (1 << n); i += 2) { dp[0][i / 2][good[i]][good[i + 1]] = max(dp[0][i / 2][good[i]][good[i + 1]], good[i] | good[i + 1]); dp[0][i / 2][good[i + 1]][good[i]] = max(dp[0][i / 2][good[i + 1]][good[i]], good[i] | good[i + 1]); } for (int l = 0; l + 1 < n; l++) { int p = (1 << n) / (1 << (l + 1)); for (int i = 0; i < p; i += 2) { for (int u1 = 0; u1 < 2; u1++) { for (int d1 = 0; d1 < 2; d1++) { for (int u2 = 0; u2 < 2; u2++) { for (int d2 = 0; d2 < 2; d2++) { int d = (d1 | d2); if (d) { int u = u1 | u2; int m = 2 + u; dp[l + 1][i / 2][u][d] = max(dp[l + 1][i / 2][u][d], dp[l][i][u1][d1] + dp[l][i + 1][u2][d2] + m); } else { if (u1 & u2) { dp[l + 1][i / 2][1][1] = max(dp[l + 1][i / 2][1][1], dp[l][i][u1][d1] + dp[l][i + 1][u2][d2] + 2); } else if (u1 | u2) { dp[l + 1][i / 2][1][0] = max(dp[l + 1][i / 2][1][0], dp[l][i][u1][d1] + dp[l][i + 1][u2][d2] + 1); dp[l + 1][i / 2][0][1] = max(dp[l + 1][i / 2][0][1], dp[l][i][u1][d1] + dp[l][i + 1][u2][d2] + 2); } else { dp[l + 1][i / 2][0][0] = max(dp[l + 1][i / 2][0][0], dp[l][i][u1][d1] + dp[l][i + 1][u2][d2]); } } } } } } } } int ans = 0; for (int u = 0; u < 2; u++) { for (int d = 0; d < 2; d++) { ans = max(ans, dp[n - 1][0][u][d] + (u | d)); } } cout << ans << endl; return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: sound.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ()
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
//
////////////////////////////////////////////////////////////////////////////////
// Internal Sound generation
assign SOUND = {1'b0, SBS, SOUND_DTOA};
assign DAC_LEFT = {2'b00, ORCH_LEFT, ORCH_LEFT_EXT, 1'b0} + {2'b00, SOUND, 9'h000};
assign DAC_RIGHT = {2'b00, ORCH_RIGHT, ORCH_RIGHT_EXT, 1'b0} + {2'b00, SOUND, 9'h000};
assign AUD_XCK = CLK24MHZ_2;
//Delay LRCLK half cycle
always @(posedge AUD_BCLK)
begin
DACLRCLK <= AUD_DACLRCK;
ADCLRCLK <= AUD_ADCLRCK;
end
always @(negedge AUD_DACLRCK)
begin
LEFT <= DAC_LEFT;
RIGHT <= DAC_RIGHT;
end
always @(negedge AUD_BCLK or negedge RESET_N)
begin
if(!RESET_N)
DAC_STATE <= 6'h00;
else
case (DAC_STATE)
6'h00:
begin
if(!DACLRCLK)
begin
AUD_DACDAT <= LEFT[18];
DAC_STATE <= 6'h01;
end
end
6'h01:
begin
AUD_DACDAT <= LEFT[17];
DAC_STATE <= 6'h02;
end
6'h02:
begin
AUD_DACDAT <= LEFT[16];
DAC_STATE <= 6'h03;
end
6'h03:
begin
AUD_DACDAT <= LEFT[15];
DAC_STATE <= 6'h04;
end
6'h04:
begin
AUD_DACDAT <= LEFT[14];
DAC_STATE <= 6'h05;
end
6'h05:
begin
AUD_DACDAT <= LEFT[13];
DAC_STATE <= 6'h06;
end
6'h06:
begin
AUD_DACDAT <= LEFT[12];
DAC_STATE <= 6'h07;
end
6'h07:
begin
AUD_DACDAT <= LEFT[11];
DAC_STATE <= 6'h08;
end
6'h08:
begin
AUD_DACDAT <= LEFT[10];
DAC_STATE <= 6'h09;
end
6'h09:
begin
AUD_DACDAT <= LEFT[9];
DAC_STATE <= 6'h0A;
end
6'h0A:
begin
AUD_DACDAT <= LEFT[8];
DAC_STATE <= 6'h0B;
end
6'h0B:
begin
AUD_DACDAT <= LEFT[7];
DAC_STATE <= 6'h0C;
end
6'h0C:
begin
AUD_DACDAT <= LEFT[6];
DAC_STATE <= 6'h0D;
end
6'h0D:
begin
AUD_DACDAT <= LEFT[5];
DAC_STATE <= 6'h0E;
end
6'h0E:
begin
AUD_DACDAT <= LEFT[4];
DAC_STATE <= 6'h0F;
end
6'h0F:
begin
AUD_DACDAT <= LEFT[3];
DAC_STATE <= 6'h10;
end
6'h10:
begin
AUD_DACDAT <= LEFT[2];
DAC_STATE <= 6'h11;
end
6'h11:
begin
AUD_DACDAT <= LEFT[1];
DAC_STATE <= 6'h12;
end
6'h12:
begin
AUD_DACDAT <= LEFT[0];
DAC_STATE <= 6'h13;
end
6'h13:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h14;
end
6'h14:
begin
if(DACLRCLK)
begin
AUD_DACDAT <= RIGHT[18];
DAC_STATE <= 6'h15;
end
end
6'h15:
begin
AUD_DACDAT <= RIGHT[17];
DAC_STATE <= 6'h16;
end
6'h16:
begin
AUD_DACDAT <= RIGHT[16];
DAC_STATE <= 6'h17;
end
6'h17:
begin
AUD_DACDAT <= RIGHT[15];
DAC_STATE <= 6'h18;
end
6'h18:
begin
AUD_DACDAT <= RIGHT[14];
DAC_STATE <= 6'h19;
end
6'h19:
begin
AUD_DACDAT <= RIGHT[13];
DAC_STATE <= 6'h1A;
end
6'h1A:
begin
AUD_DACDAT <= RIGHT[12];
DAC_STATE <= 6'h1B;
end
6'h1B:
begin
AUD_DACDAT <= RIGHT[11];
DAC_STATE <= 6'h1C;
end
6'h1C:
begin
AUD_DACDAT <= RIGHT[10];
DAC_STATE <= 6'h1D;
end
6'h1D:
begin
AUD_DACDAT <= RIGHT[9];
DAC_STATE <= 6'h1E;
end
6'h1E:
begin
AUD_DACDAT <= RIGHT[8];
DAC_STATE <= 6'h1F;
end
6'h1F:
begin
AUD_DACDAT <= RIGHT[7];
DAC_STATE <= 6'h20;
end
6'h20:
begin
AUD_DACDAT <= RIGHT[6];
DAC_STATE <= 6'h21;
end
6'h21:
begin
AUD_DACDAT <= RIGHT[5];
DAC_STATE <= 6'h22;
end
6'h22:
begin
AUD_DACDAT <= RIGHT[4];
DAC_STATE <= 6'h23;
end
6'h23:
begin
AUD_DACDAT <= RIGHT[3];
DAC_STATE <= 6'h24;
end
6'h24:
begin
AUD_DACDAT <= RIGHT[2];
DAC_STATE <= 6'h25;
end
6'h25:
begin
AUD_DACDAT <= RIGHT[1];
DAC_STATE <= 6'h26;
end
6'h26:
begin
AUD_DACDAT <= RIGHT[0];
DAC_STATE <= 6'h27;
end
6'h27:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h00;
end
default:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h00;
end
endcase
end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_TB_V
`define SKY130_FD_SC_HS__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__tap dut (.VPWR(VPWR), .VGND(VGND));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, i, ans; int main() { cin >> n; for (int i = 1; i <= n; i += 2) ans += n - i + 1; cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n, a[200003]; vector<int> v; int main() { cin >> n; for (int i = 2; i <= n; i++) cin >> a[i]; v.push_back(n); int j = n; while (j != 1) { v.push_back(a[j]); j = a[j]; } reverse(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) cout << v[i] << ; } |
//======================================================================
//
// blockmem_rw32_r256.v
// --------------------
// Test implementation of a block memory that has different data
// widths on external (api) and internal ports.
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem_rw32_r128(
input wire clk,
input wire api_we,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [04 : 0] internal_addr,
output wire [255 : 0] internal_rd_data
);
//----------------------------------------------------------------
// Regs and memories.
//----------------------------------------------------------------
reg [31 : 0] mem0 [0 : 31];
reg [31 : 0] mem1 [0 : 31];
reg [31 : 0] mem2 [0 : 31];
reg [31 : 0] mem3 [0 : 31];
reg [31 : 0] mem4 [0 : 31];
reg [31 : 0] mem5 [0 : 31];
reg [31 : 0] mem6 [0 : 31];
reg [31 : 0] mem7 [0 : 31];
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] muxed_api_rd_data;
reg [31 : 0] mem0_api_rd_data;
reg [31 : 0] mem1_api_rd_data;
reg [31 : 0] mem2_api_rd_data;
reg [31 : 0] mem3_api_rd_data;
reg [31 : 0] mem4_api_rd_data;
reg [31 : 0] mem5_api_rd_data;
reg [31 : 0] mem6_api_rd_data;
reg [31 : 0] mem7_api_rd_data;
reg [31 : 0] mem0_int_rd_data;
reg [31 : 0] mem1_int_rd_data;
reg [31 : 0] mem2_int_rd_data;
reg [31 : 0] mem3_int_rd_data;
reg [31 : 0] mem4_int_rd_data;
reg [31 : 0] mem5_int_rd_data;
reg [31 : 0] mem6_int_rd_data;
reg [31 : 0] mem7_int_rd_data;
reg mem0_we;
reg mem1_we;
reg mem2_we;
reg mem3_we;
reg mem4_we;
reg mem5_we;
reg mem6_we;
reg mem7_we;
//----------------------------------------------------------------
// Assignmets.
//----------------------------------------------------------------
assign api_rd_data = muxed_api_rd_data;
assign internal_rd_data = {mem7_int_rd_data, mem6_int_rd_data,
mem5_int_rd_data, mem4_int_rd_data,
mem3_int_rd_data, mem2_int_rd_data,
mem1_int_rd_data, mem0_int_rd_data};
//----------------------------------------------------------------
// Reg updates.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update_mem0
if (mem0_we)
mem0[api_addr[7 : 3]] <= api_wr_data;
mem0_api_rd_data <= mem0[api_addr[7 : 3]];
mem0_int_rd_data <= mem0[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem1
if (mem1_we)
mem1[api_addr[7 : 3]] <= api_wr_data;
mem1_api_rd_data <= mem1[api_addr[7 : 3]];
mem1_int_rd_data <= mem1[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem2
if (mem2_we)
mem2[api_addr[7 : 3]] <= api_wr_data;
mem2_api_rd_data <= mem2[api_addr[7 : 3]];
mem2_int_rd_data <= mem2[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem3
if (mem3_we)
mem3[api_addr[7 : 3]] <= api_wr_data;
mem3_api_rd_data <= mem3[api_addr[7 : 3]];
mem3_int_rd_data <= mem3[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem4
if (mem4_we)
mem4[api_addr[7 : 3]] <= api_wr_data;
mem4_api_rd_data <= mem4[api_addr[7 : 3]];
mem4_int_rd_data <= mem4[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem5
if (mem5_we)
mem5[api_addr[7 : 3]] <= api_wr_data;
mem5_api_rd_data <= mem5[api_addr[7 : 3]];
mem5_int_rd_data <= mem5[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem6
if (mem6_we)
mem6[api_addr[7 : 3]] <= api_wr_data;
mem6_api_rd_data <= mem6[api_addr[7 : 3]];
mem6_int_rd_data <= mem6[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem7
if (mem7_we)
mem7[api_addr[7 : 3]] <= api_wr_data;
mem7_api_rd_data <= mem7[api_addr[7 : 3]];
mem7_int_rd_data <= mem7[internal_addr];
end
//----------------------------------------------------------------
// api_mux
//----------------------------------------------------------------
always @*
begin : api_mux
mem0_we = 1'b0;
mem1_we = 1'b0;
mem2_we = 1'b0;
mem3_we = 1'b0;
mem4_we = 1'b0;
mem5_we = 1'b0;
mem6_we = 1'b0;
mem7_we = 1'b0;
case (api_addr[2 : 0])
0:
begin
muxed_api_rd_data = mem0_api_rd_data;
mem0_we = api_we;
end
1:
begin
muxed_api_rd_data = mem1_api_rd_data;
mem1_we = api_we;
end
2:
begin
muxed_api_rd_data = mem2_api_rd_data;
mem2_we = api_we;
end
3:
begin
muxed_api_rd_data = mem3_api_rd_data;
mem3_we = api_we;
end
4:
begin
muxed_api_rd_data = mem4_api_rd_data;
mem4_we = api_we;
end
5:
begin
muxed_api_rd_data = mem5_api_rd_data;
mem5_we = api_we;
end
6:
begin
muxed_api_rd_data = mem6_api_rd_data;
mem6_we = api_we;
end
7:
begin
muxed_api_rd_data = mem7_api_rd_data;
mem7_we = api_we;
end
default:
begin
end
endcase // case (api_addr[1 : 0])
end // api_mux
endmodule // blockmem_rw32_r128
//======================================================================
// eof blockmem_rw32_r128.v
//======================================================================
|
#include <bits/stdc++.h> long long int power(long long int x, long long int b) { long long int p = 1; while (b > 0) { if (b & 1) { p = p * x; p %= 1000000007; } b >>= 1; x *= x; x %= 1000000007; } return p % 1000000007; } using namespace std; struct lex_compare { bool operator()( const pair<long long int, pair<long long int, long long int> > p1, const pair<long long int, pair<long long int, long long int> > p2) { return (p1.first == p2.first) ? p1.second.first < p2.second.first : p1.first > p2.first; } }; long long int n, m, b, mo; long long int dp[2][500 + 1][500 + 1]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int w, m; cin >> w >> m; bool f = 1; map<long long int, long long int> coeff; long long int term = 1; while (m >= term && term <= 10000000000) { long long int x = (term * (m / term) - (w * term) * (m / (w * term))); x /= term; if (x <= 1) { term *= w; } else { if (x != (w - 1)) { f = 0; break; } else { m += (w * term - term); } term *= w; } } if (f) cout << YES << n ; else cout << NO << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int N = 1e6 + 10, M = 1e7 + 10, mod = 1e9 + 7, INF = 0x3f3f3f3f, ha = 137; int n, q; int mx[N], a[N]; int s[M], ls[M], rs[M]; int rt[N]; int cnt; int update(int loc, int pre, int l, int r) { int now = ++cnt; s[now] = s[pre] + 1; ls[now] = ls[pre]; rs[now] = rs[pre]; if (l == r) return now; int mid = l + r >> 1; if (loc <= mid) ls[now] = update(loc, ls[pre], l, mid); else rs[now] = update(loc, rs[pre], mid + 1, r); return now; } int query(int a, int b) { int x = rt[a - 1], y = rt[b]; int ans = 0; int l = 0, r = n; while (l < r) { int mid = l + r >> 1; if (a <= mid) ans += s[rs[y]] - s[rs[x]], x = ls[x], y = ls[y], r = mid; else { l = mid + 1, x = rs[x], y = rs[y]; } } return ans; } int tot; struct dat { int s[N << 2], lazy[N << 2]; void update(int a, int b, int x, int k, int l, int r) { if (a == l && b == r) { s[x] += k; lazy[x] += k; return; } int mid = l + r >> 1, ls = x << 1, rs = x << 1 | 1; if (lazy[x]) { update(l, mid, ls, lazy[x], l, mid); update(mid + 1, r, rs, lazy[x], mid + 1, r); lazy[x] = 0; } if (b <= mid) update(a, b, ls, k, l, mid); else if (a > mid) update(a, b, rs, k, mid + 1, r); else { update(a, mid, ls, k, l, mid); update(mid + 1, b, rs, k, mid + 1, r); } s[x] = max(s[ls], s[rs]); } int query(int k) { int x = 1; int l = 1, r = n; while (l < r) { int mid = l + r >> 1, ls = x << 1, rs = x << 1 | 1; if (lazy[x]) { update(l, mid, ls, lazy[x], l, mid); update(mid + 1, r, rs, lazy[x], mid + 1, r); lazy[x] = 0; } if (s[rs] >= k) x = rs, l = mid + 1; else x = ls, r = mid; } return l; } } tr; int f[N]; int ss; int main() { cin >> n >> q; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); int k = i - a[i]; if (k < 0) { rt[i] = update(a[i] = 0, rt[i - 1], 0, n); continue; } int t = tr.query(k); a[i] = f[t]; if (k == 0) f[++tot] = i, a[i] = i, t = tot; if (k > ss) { a[i] = 0, t = 0; } else ss++; if (min(tot, t)) tr.update(1, min(tot, t), 1, 1, 1, n); rt[i] = update(a[i], rt[i - 1], 0, n); } int l, r; while (q--) { scanf( %d%d , &l, &r); printf( %d n , query(l, n - r)); } return 0; } |
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] reg_value[8:0];
reg led_out;
reg [31:0] reg_status;
reg [31:0] reg_res;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
reg reg_module_caculation_end;
reg reg_modue_caculating_start;
reg reg_module_end;
reg reg_module_start;
convolution_core instance_convolution(.clk(clock_clk),
.reset(reset_reset),
.value0(reg_value[0]),
.value1(reg_value[1]),
.value2(reg_value[2]),
.value3(reg_value[3]),
.value4(reg_value[4]),
.value5(reg_value[5]),
.value6(reg_value[6]),
.value7(reg_value[7]),
.value8(reg_value[8]),
.caculating_start(reg_modue_caculating_start),
.caculating_done(reg_module_caculation_end),
.res_done(reg_module_end),
.ret(reg_res)
);
reg [3:0] reg_current_status, reg_next_status;
parameter IDLE = 4'b0001;
parameter CALCULATING = 4'b0010;
parameter WAITTING = 4'b0100;
parameter FINISH = 4'b1000;
// machine status
always@(posedge clock_clk)
begin
if(reset_reset)
reg_current_status <= IDLE;
else
reg_current_status <= reg_next_status;
end
// machine's next status
always@(reg_current_status or reg_read_done or reg_module_caculation_end or reg_write_done or reset_reset)
begin
if(reset_reset)
reg_next_status = IDLE;
else
begin
case(reg_current_status)
IDLE:reg_next_status = reg_read_done?CALCULATING:IDLE;
CALCULATING:reg_next_status = reg_module_caculation_end?WAITTING:CALCULATING;
WAITTING:reg_next_status = reg_write_done?FINISH:WAITTING;
FINISH: reg_next_status = IDLE;
default: reg_next_status = IDLE;
endcase
end
end
always@(posedge clock_clk) begin
if (reset_reset) begin
led_out <= 1'b0;
end else begin
case(reg_current_status)
IDLE: begin
reg_module_start<= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
end
CALCULATING: begin
led_out <= 1'b1;
reg_module_start <= 1'b1;
reg_modue_caculating_start <= 1'b1;
end
WAITTING:begin
reg_modue_caculating_start <= 1'b0;
reg_module_end <= 1'b1;
end
FINISH:begin
reg_module_start <= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
led_out <= 1'b0;
end
default:begin
end
endcase
end
end
// WRITE LOGIC
//
reg reg_read_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Write <= 1'b1;
reg_value[0] <= 32'h00000000;
reg_value[1] <= 32'h00000000;
reg_value[2] <= 32'h00000000;
reg_value[3] <= 32'h00000000;
reg_value[4] <= 32'h00000000;
reg_value[5] <= 32'h00000000;
reg_value[6] <= 32'h00000000;
reg_value[7] <= 32'h00000000;
reg_value[8] <= 32'h00000000;
reg_read_done <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b0000: reg_value[0] <= avs_s0_writedata;
4'b0001: reg_value[1] <= avs_s0_writedata;
4'b0010: reg_value[2] <= avs_s0_writedata;
4'b0011: reg_value[3] <= avs_s0_writedata;
4'b0100: reg_value[4] <= avs_s0_writedata;
4'b0101: reg_value[5] <= avs_s0_writedata;
4'b0110: reg_value[6] <= avs_s0_writedata;
4'b0111: reg_value[7] <= avs_s0_writedata;
4'b1000:begin
reg_value[8] <= avs_s0_writedata;
reg_read_done <= 1'b1; // read done;
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write && reg_module_start == 1'b0)begin
Reg_Status_Write <= 1'b0;
end else begin
//revert reg_read_done to 0 at here when it's done /
if(reg_module_end) begin
reg_read_done <= 1'b0;
end
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
reg reg_write_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
reg_write_done <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read && reg_module_caculation_end) begin
case (avs_s0_address[3:0])
4'b0000: reg_out <= reg_value[0];
4'b0001: reg_out <= reg_value[1];
4'b0010: reg_out <= reg_value[2];
4'b0011: reg_out <= reg_value[3];
4'b0100: reg_out <= reg_value[4];
4'b0101: reg_out <= reg_value[5];
4'b0110: reg_out <= reg_value[6];
4'b0111: reg_out <= reg_value[7];
4'b1000: reg_out <= reg_value[8];
4'b1001: reg_out <= reg_res;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
if (reg_module_end) begin
reg_write_done <= 1'b0;
end
end
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Sat Mar 15 17:18:29 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.v
// Design : clk_base
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_base
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire clk_100MHz;
wire clk_250MHz;
(* IBUF_LOW_PWR *) wire clk_raw;
wire locked;
clk_baseclk_base_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_250MHz(clk_250MHz),
.clk_raw(clk_raw),
.locked(locked));
endmodule
module clk_baseclk_base_clk_wiz
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_base;
wire clk_250MHz;
wire clk_250MHz_clk_base;
(* IBUF_LOW_PWR *) wire clk_raw;
wire clk_raw_clk_base;
wire clkfbout_buf_clk_base;
wire clkfbout_clk_base;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_base),
.O(clkfbout_buf_clk_base));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_raw),
.O(clk_raw_clk_base));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_100MHz_clk_base),
.O(clk_100MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_250MHz_clk_base),
.O(clk_250MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_base),
.CLKFBOUT(clkfbout_clk_base),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_raw_clk_base),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_100MHz_clk_base),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_250MHz_clk_base),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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