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#include <bits/stdc++.h> const int nMax = 200001; struct Segment { int left; int right; long long sum; long long forced; Segment* lChild; Segment* rChild; }; Segment* initTree(int left, int right, long long forced) { Segment* segment = new Segment; segment->left = left; segment->right = right; segment->forced = forced; if (left == right) { segment->lChild = nullptr; segment->rChild = nullptr; segment->sum = left; segment->forced = left; } else { segment->lChild = initTree(left, (left + right) / 2, forced); segment->rChild = initTree((left + right) / 2 + 1, right, forced); segment->sum = ((segment->rChild == nullptr) ? 0 : segment->rChild->sum) + ((segment->lChild == nullptr) ? 0 : segment->lChild->sum); } return segment; } int customMax(int fd, int sd) { return (fd > sd) ? fd : sd; } int getValue(Segment* root, int item, int value = -1) { if (root->left == root->right) { if (value == -1) value = root->forced; return value; } if (value == -1) if (root->forced != -1) value = root->forced; if (item <= (root->left + root->right) / 2) return getValue(root->lChild, item, value); else return getValue(root->rChild, item, value); } int safeForceCheck(Segment* root, int left, int right, int threshold) { if (left > right) return -1; if (left == right) if (getValue(root, left) >= threshold) return -1; else return left; int result; if (getValue(root, (left + right) / 2) >= threshold) { result = safeForceCheck(root, left, (left + right) / 2 - 1, threshold); } else { result = safeForceCheck(root, (left + right) / 2 + 1, right, threshold); if (result == -1) result = (left + right) / 2; } return result; } void forceToSegment(Segment* root, int left, int right, long long forced, long long was_forced = -1) { if (left < 0) return; if (right < left) return; if ((left == root->left) && (right == root->right)) { root->forced = forced; root->sum = (right - left + 1) * forced; return; } if (was_forced == -1) was_forced = root->forced; if (was_forced != -1) { if (was_forced >= forced) return; root->lChild->forced = was_forced; root->lChild->sum = (root->lChild->right - root->lChild->left + 1) * was_forced; root->rChild->forced = was_forced; root->rChild->sum = (root->rChild->right - root->rChild->left + 1) * was_forced; root->forced = -1; } if (right <= (root->left + root->right) / 2) { forceToSegment(root->lChild, left, right, forced, was_forced); } else if (left > (root->left + root->right) / 2) { forceToSegment(root->rChild, left, right, forced, was_forced); } else { forceToSegment(root->lChild, left, (root->left + root->right) / 2, forced, was_forced); forceToSegment(root->rChild, (root->left + root->right) / 2 + 1, right, forced, was_forced); } root->sum = ((root->rChild == nullptr) ? 0 : root->rChild->sum) + ((root->lChild == nullptr) ? 0 : root->lChild->sum); } int main() { long n; Segment* root; scanf( %ld , &n); std::vector<int> a(n); std::vector<int> used(nMax, -1); int maxA = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); used[a[i]] = i; if (a[i] > maxA) maxA = a[i]; } maxA++; std::vector<long long> downCount(maxA, 0); std::vector<int> rowTail(n, 0); std::vector<std::vector<int> > affective(maxA); downCount[maxA - 1] = ((long long)n * (n + 1)) / 2; for (int i = 1; i < maxA; ++i) for (int j = i; j < maxA; j += i) if (used[j] != -1) affective[i].push_back(used[j]); root = initTree(0, n - 1, -1); for (int i = maxA - 2; i >= 1; i--) { if (affective[i].size() <= 1) { downCount[i] = downCount[i + 1]; } else { std::sort(affective[i].begin(), affective[i].end()); forceToSegment(root, affective[i][1] + 1, safeForceCheck(root, affective[i][1] + 1, n - 1, n), n); forceToSegment(root, affective[i][0] + 1, safeForceCheck(root, affective[i][0] + 1, affective[i][1], affective[i][affective[i].size() - 1]), affective[i][affective[i].size() - 1]); forceToSegment(root, 0, safeForceCheck(root, 0, affective[i][0], affective[i][affective[i].size() - 2]), affective[i][affective[i].size() - 2]); downCount[i] = ((long long)n * (n)) - root->sum; } } long long result = 0LL; for (int i = maxA - 2; i >= 1; i--) { result += (downCount[i + 1] - downCount[i]) * i; } printf( %I64d , result); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {b, d}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
b, c, d,
// Inputs
crc
);
input [31:0] crc;
`ifdef ISOLATE
output reg [31:0] b /* verilator isolate_assignments*/;
`else
output reg [31:0] b;
`endif
output reg [31:0] c;
output reg [31:0] d;
always @* begin
// Note that while c and b depend on crc, b doesn't depend on c.
casez (crc[3:0])
4'b??01: begin
b = {crc[15:0],get_31_16(crc)};
d = c;
end
4'b??00: begin
b = {crc[15:0],~crc[31:16]};
d = {crc[15:0],~c[31:16]};
end
default: begin
set_b_d(crc, c);
end
endcase
end
function [31:16] get_31_16 /* verilator isolate_assignments*/;
input [31:0] t_crc /* verilator isolate_assignments*/;
get_31_16 = t_crc[31:16];
endfunction
task set_b_d;
`ifdef ISOLATE
input [31:0] t_crc /* verilator isolate_assignments*/;
input [31:0] t_c /* verilator isolate_assignments*/;
`else
input [31:0] t_crc;
input [31:0] t_c;
`endif
begin
b = {t_crc[31:16],~t_crc[23:8]};
d = {t_crc[31:16], ~t_c[23:8]};
end
endtask
always @* begin
// Any complicated equation we can't optimize
casez (crc[3:0])
4'b00??: begin
c = {b[29:0],2'b11};
end
4'b01??: begin
c = {b[30:1],2'b01};
end
4'b10??: begin
c = {b[31:2],2'b10};
end
4'b11??: begin
c = {b[31:2],2'b00};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200010], c[200010]; int main() { int n, t, k; scanf( %d%d%d , &n, &t, &k); for (int i = 1; i <= t; i++) scanf( %d , &a[i]); a[0] = (k > n - t ? 2 : 1); for (int i = 0; i <= t; i++) { c[i] = min(a[i], a[i + 1]); k -= a[i] - c[i]; } if (k < 0 || a[0] > 1) { puts( -1 ); return 0; } for (int i = t - 1; i > 0; i--) { int q = min(c[i] - 1, k); k -= q; c[i] -= q; } int id = 1; printf( %d n , n); for (int i = 0; i < t; i++) { for (int j = 0; j < a[i + 1]; j++) printf( %d %d n , id + j % c[i], id + a[i] + j); id += a[i]; } } |
#include <bits/stdc++.h> using namespace std; const int N = 20; const int MOD = (int)1e9 + 7; const int dx[] = {0, -1, 0, 1, 0}; const int dy[] = {0, 0, 1, 0, -1}; struct Matrix { long long mat[N][N]; }; bool blocked[N][N]; int m, n, q; int size; Matrix operator*(const Matrix a, const Matrix b) { Matrix c; for (int i = 0; i < size; ++i) for (int j = 0; j < size; ++j) { c.mat[i][j] = 0; for (int k = 0; k < size; ++k) c.mat[i][j] = (c.mat[i][j] + a.mat[i][k] * b.mat[k][j]) % MOD; } return c; } Matrix power(Matrix a, int p) { Matrix ans; memset(ans.mat, 0, sizeof(ans.mat)); for (int i = 0; i < size; ++i) ans.mat[i][i] = 1; for (; p; p >>= 1) { if (p & 1) ans = ans * a; a = a * a; } return ans; } int getIndex(int x, int y) { return x * n + y; } void update(Matrix &a) { for (int i = 0; i < m; ++i) for (int j = 0; j < n; ++j) { int cur = getIndex(i, j); for (int k = 0; k < size; ++k) a.mat[cur][k] = 0; if (blocked[i][j]) continue; for (int d = 0; d < 5; ++d) { int x = i + dx[d], y = j + dy[d]; if (x < 0 || y < 0 || x >= m || y >= n || blocked[x][y]) continue; a.mat[cur][getIndex(x, y)] = 1; } } } void multiply(Matrix gap, long long ans[]) { int newAns[N]; for (int i = 0; i < size; ++i) { newAns[i] = 0; for (int j = 0; j < size; ++j) newAns[i] = (newAns[i] + ans[j] * gap.mat[i][j]) % MOD; } for (int i = 0; i < size; ++i) ans[i] = newAns[i]; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> m >> n >> q; size = m * n; Matrix a; update(a); long long ans[N]; memset(ans, 0, sizeof(ans)); ans[0] = 1; int lastT = 1; while (q--) { int type, x, y, t; cin >> type >> x >> y >> t; --x; --y; Matrix gap = power(a, t - lastT - 1); multiply(gap, ans); multiply(a, ans); if (type != 1) { blocked[x][y] ^= 1; update(a); } if (type == 1) cout << ans[getIndex(x, y)] << n ; lastT = t; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long x, int p) { long long res = 1; while (p) { if (p & 1) res = (res * x) % 998244353; x = (x * x) % 998244353; p >>= 1; } return res; } int main() { int n, m; cin >> n >> m; vector<long long> d(n), pref(n); for (int i = 0; i < n; i++) cin >> d[i]; sort(d.begin(), d.end()); pref[0] = d[0]; for (int i = 1; i < n; i++) pref[i] = (pref[i - 1] + d[i]) % 998244353; while (m--) { int a, b; cin >> a >> b; int x = lower_bound(d.begin(), d.end(), b) - d.begin(); int big = n - x; if (big < a) { cout << 0 << n ; continue; } long long big_total = (pref[n - 1] - (x > 0 ? pref[x - 1] : 0)) % 998244353; (big_total += 998244353) %= 998244353; long long ans = (big_total * (big - a)) % 998244353; ans = (ans * bigmod(big, 998244353 - 2)) % 998244353; long long tmp = ((x > 0 ? pref[x - 1] : 0) * (big + 1 - a)) % 998244353; tmp = (tmp * bigmod(big + 1, 998244353 - 2)) % 998244353; ans = (ans + tmp) % 998244353; cout << ans << n ; } return 0; } |
`define ADDER_WIDTH 007
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
`timescale 1ns / 1ps
// Name: WcaDspCounter.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaDspCounter(
input clock,
input reset, // Resets the counter.
input bUp, //(1) Counts up, (0) counts down.
input data, //Data value to load.
input load, //(1) loads the data.
output count //Current Count value.
);
parameter MAXBITS = 24;
wire clock, reset, bUp, load;
wire [MAXBITS : 0] data;
wire [MAXBITS : 0] count;
//Implment internal counter.
DspCounter24 ( .clk(clock), .up( bUp), .load( load | reset), .l( data), .q( count) );
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Stratix IV" inclk0_input_frequency=20000 intended_device_family="Stratix IV" lpm_hint="CBX_MODULE_PREFIX=pll_125" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" using_fbmimicbidir_port="OFF" width_clock=10 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 12.1SP1 cbx_altclkbuf 2013:01:31:18:04:58:SJ cbx_altiobuf_bidir 2013:01:31:18:04:58:SJ cbx_altiobuf_in 2013:01:31:18:04:58:SJ cbx_altiobuf_out 2013:01:31:18:04:58:SJ cbx_altpll 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE4_Reference_Router_pll_125_pll_125_ins_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module pll_125_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [9:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] wire_pll1_clk;
wire wire_pll1_fbout;
stratixiv_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({4{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 2,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 5,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "stratixiv_pll";
assign
clk = wire_pll1_clk;
endmodule //pll_125_altpll
//VALID FILE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 00:02:33 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_1_0/RAT_FlagReg_1_0_sim_netlist.v
// Design : RAT_FlagReg_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_FlagReg_1_0,FlagReg,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "FlagReg,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_FlagReg_1_0
(IN_FLAG,
LD,
SET,
CLR,
CLK,
OUT_FLAG);
input IN_FLAG;
input LD;
input SET;
input CLR;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
output OUT_FLAG;
wire CLK;
wire CLR;
wire IN_FLAG;
wire LD;
wire OUT_FLAG;
wire SET;
RAT_FlagReg_1_0_FlagReg U0
(.CLK(CLK),
.CLR(CLR),
.IN_FLAG(IN_FLAG),
.LD(LD),
.OUT_FLAG(OUT_FLAG),
.SET(SET));
endmodule
(* ORIG_REF_NAME = "FlagReg" *)
module RAT_FlagReg_1_0_FlagReg
(OUT_FLAG,
IN_FLAG,
SET,
LD,
CLR,
CLK);
output OUT_FLAG;
input IN_FLAG;
input SET;
input LD;
input CLR;
input CLK;
wire CLK;
wire CLR;
wire IN_FLAG;
wire LD;
wire OUT_FLAG;
wire OUT_FLAG_i_1_n_0;
wire SET;
LUT5 #(
.INIT(32'hACAFACAC))
OUT_FLAG_i_1
(.I0(IN_FLAG),
.I1(SET),
.I2(LD),
.I3(CLR),
.I4(OUT_FLAG),
.O(OUT_FLAG_i_1_n_0));
FDRE OUT_FLAG_reg
(.C(CLK),
.CE(1'b1),
.D(OUT_FLAG_i_1_n_0),
.Q(OUT_FLAG),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class T> using V = vector<T>; template <typename T> using min_priority_queue = priority_queue<T, vector<T>, greater<T> >; long long GCD(long long a, long long b) { return b ? GCD(b, a % b) : a; } long long LCM(long long a, long long b) { return a / GCD(a, b) * b; } long long int pom(long long int a, long long int n, int m) { long long int x = 1; for (a %= m; n; n /= 2) n& 1 ? x = x * a % m : 0, a = a * a % m; return x; } int dx[4] = {-1, 0, 1, 0}; int dy[4] = {0, -1, 0, 1}; int ddx[8] = {-1, 0, 1, 0, 1, 1, -1, -1}; int ddy[8] = {0, -1, 0, 1, 1, -1, 1, -1}; long long int cmp1(pair<pair<long long int, long long int>, long long int> a, pair<pair<long long int, long long int>, long long int> b) { return a.first.second > b.first.second; } long long int cmp2(pair<long long int, long long int> a, pair<long long int, long long int> b) { if (a.second != b.second) return a.second < b.second; else return a.first > b.first; } int main(int argc, char* argv[]) { cin.tie(0); ios::sync_with_stdio(false); long long int T; cin >> T; while (T--) { long long int n; cin >> n; V<long long int> a(n + 1); for (long long int i = 0; i < n; i++) { cin >> a[i]; } long long int ans = 0; bool abc = 0; long long int cnt = 0; for (long long int i = 1; i < n; i++) { if (a[i - 1] == 1 && a[i] == 0) { abc = 1; cnt = 1; } else if (abc == 1 && a[i] == 0) { cnt++; } if (abc == 1 && (a[i] == 0 && a[i + 1] == 1 && i < n - 1)) { ans += cnt; cnt = 0; abc = 0; } } cout << ans << endl; } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// FIFO backed by an off chip ZBT/NoBL SRAM.
//
// This module and its sub-hierarchy implment a FIFO capable of sustaining
// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits.
//
// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz,
// your milage may vary with other clock ratio's especially those where int_clk < ext_clk.
// Testing has also exclusively used a rst signal synchronized to int_clk.
//
// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through",
// though signal naming differs.
//
// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be
// packed into the IO ring.
//
//`define NO_EXT_FIFO
module ext_fifo
#(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
(
input int_clk,
input ext_clk,
input rst,
input [EXT_WIDTH-1:0] RAM_D_pi,
output [EXT_WIDTH-1:0] RAM_D_po,
output RAM_D_poe,
output [RAM_DEPTH-1:0] RAM_A,
output RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output RAM_CE1n,
input [INT_WIDTH-1:0] datain,
input src_rdy_i, // WRITE
output dst_rdy_o, // not FULL
output [INT_WIDTH-1:0] dataout,
output src_rdy_o, // not EMPTY
input dst_rdy_i, // READ
output reg [31:0] debug,
output reg [31:0] debug2
);
wire [EXT_WIDTH-1:0] write_data;
wire [EXT_WIDTH-1:0] read_data;
wire full1, empty1;
wire almost_full2, almost_full2_spread, full2, empty2;
wire [FIFO_DEPTH-1:0] capacity;
wire space_avail;
wire data_avail;
// These next 2 lines here purely because ICARUS is crap at handling generate statements.
// Empirically this has been determined to make simulations work.
wire read_input_fifo = space_avail & ~empty1;
wire write_output_fifo = data_avail;
assign src_rdy_o = ~empty2;
assign dst_rdy_o = ~full1;
`ifdef NO_EXT_FIFO
assign space_avail = ~full2;
assign data_avail = ~empty1;
assign read_data = write_data;
`else
// External FIFO running at ext clock rate and 18 or 36 bit width.
nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH))
nobl_fifo_i1
(
.clk(ext_clk),
.rst(rst),
.RAM_D_pi(RAM_D_pi),
.RAM_D_po(RAM_D_po),
.RAM_D_poe(RAM_D_poe),
.RAM_A(RAM_A),
.RAM_WEn(RAM_WEn),
.RAM_CENn(RAM_CENn),
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
.write_data(write_data),
.write_strobe(~empty1 ),
.space_avail(space_avail),
.read_data(read_data),
.read_strobe(~almost_full2_spread),
.data_avail(data_avail),
.capacity(capacity)
);
`endif // !`ifdef NO_EXT_FIFO
generate
if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1
// FIFO buffers data from UDP engine into external FIFO clock domain.
fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
.rst(rst),
.wr_clk(int_clk),
.rd_clk(ext_clk),
.din(datain), // Bus [35 : 0]
.wr_en(src_rdy_i),
.rd_en(read_input_fifo),
.dout(write_data), // Bus [17 : 0]
.full(full1),
.empty(empty1));
// FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
.rst(rst),
.wr_clk(ext_clk),
.rd_clk(int_clk),
.din(read_data), // Bus [17 : 0]
.wr_en(write_output_fifo),
.rd_en(dst_rdy_i),
.dout(dataout), // Bus [35 : 0]
.full(full2),
.prog_full(almost_full2),
.empty(empty2));
end // block: fifo_g1
else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1
// FIFO buffers data from UDP engine into external FIFO clock domain.
fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 (
.rst(rst),
.wr_clk(int_clk),
.rd_clk(ext_clk),
.din(datain), // Bus [35 : 0]
.wr_en(src_rdy_i),
.rd_en(read_input_fifo),
.dout(write_data), // Bus [35 : 0]
.full(full1),
.empty(empty1));
// FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 (
.rst(rst),
.wr_clk(ext_clk),
.rd_clk(int_clk),
.din(read_data), // Bus [35 : 0]
.wr_en(write_output_fifo),
.rd_en(dst_rdy_i),
.dout(dataout), // Bus [35 : 0]
.full(full2),
.empty(empty2),
.prog_full(almost_full2));
end
endgenerate
refill_randomizer #(.BITS(7))
refill_randomizer_i1 (
.clk(ext_clk),
.rst(rst),
.full_in(almost_full2),
.full_out(almost_full2_spread)
);
// always @ (posedge int_clk)
// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
always @ (posedge ext_clk)
// debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]};
always@ (posedge ext_clk)
// debug2[31:0] <= {write_data[15:0],read_data[15:0]};
debug2[31:0] <= 0;
endmodule // ext_fifo
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
//`#start body` -- edit after this line, do not edit this line
// Your code goes here
//`#end` -- edit above this line, do not edit this line
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
module ToneSequencer(input clk, input key, input nrq1, input nrq2, input nrq3, output [1:0] mux);
reg [1:0] count;
always @(posedge clk)
begin
if (count == 0)
begin
// Key down, start the tone, or continue with the idle state.
count <= key ? 1 : 0;
end
else if ((count == 1 && nrq1) || (count == 2 && nrq2))
begin
// Still key down, continue with the tone, or key up, stop the tone.
count <= key ? 2 : 3;
end
else if (count == 3 && nrq3)
begin
// Key down again or idle.
count <= key ? 1 : 0;
end
end
assign mux = count;
endmodule
//[] END OF FILE
|
#include <bits/stdc++.h> using namespace std; template <class S, class T> pair<S, T> operator+(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first + t.first, s.second + t.second); } template <class S, class T> pair<S, T> operator-(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first - t.first, s.second - t.second); } template <class S, class T> ostream &operator<<(ostream &os, pair<S, T> p) { os << ( << p.first << , << p.second << ) ; return os; } template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return 1; } return 0; } const long long inf = 1000000001; const long long INF = 2e18; const long long MOD = 1000000007; const double pi = 3.14159265358979323846; int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; int dx2[8] = {1, 1, 0, -1, -1, -1, 0, 1}, dy2[8] = {0, 1, 1, 1, 0, -1, -1, -1}; vector<vector<int> > child(5010), parent(5010); vector<int> color(5010, -1); int n, m, s; vector<int> roots, roots2; void dfs1(int now, int col) { color[now] = col; for (long long i = 0; i < (long long)(child[now].size()); i++) { if (color[child[now][i]] < 0) { dfs1(child[now][i], col); } } } void dfs2(int now) { color[now] = -2; if (parent[now].size() == 0) { roots.push_back(now); return; } bool flag = true; for (long long i = 0; i < (long long)(parent[now].size()); i++) { if (color[parent[now][i]] == -1) { dfs2(parent[now][i]); flag = false; } } if (flag) { roots2.push_back(now); } return; } int main() { cin >> n >> m >> s; s--; for (long long i = 0; i < (long long)(m); i++) { int u, v; cin >> u >> v; u--; v--; child[u].push_back(v); parent[v].push_back(u); } dfs1(s, s); int ans = 0; for (long long i = 0; i < (long long)(n); i++) { if (color[i] >= 0) { continue; } roots.clear(); dfs2(i); ans += roots.size(); for (long long j = 0; j < (long long)(roots.size()); j++) { dfs1(roots[j], roots[j]); } } for (long long i = 0; i < (long long)(roots2.size()); i++) { if (color[roots2[i]] < 0) { ans++; dfs1(roots2[i], roots2[i]); } } cout << ans << endl; } |
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; long long fn(long long x, long long rn[]) { if (x == rn[x]) return x; else return rn[x] = fn(rn[x], rn); } bool un(long long x, long long y, long long rn[], long long sz[]) { x = fn(x, rn); y = fn(y, rn); if (x == y) return false; if (sz[x] < sz[y]) swap(x, y); sz[x] += sz[y]; rn[y] = x; return true; } long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long MOD = 998244353; long long mod = 1000000007; long long power(long long x, long long y, long long p) { long long res = 1; x %= p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long inv(long long val, long long MODx = MOD) { return power(val, MODx - 2, MODx); } vector<long long> fac, ifac; void preFac(long long sz) { fac.resize(sz + 1), ifac.resize(sz + 1); fac[0] = 1; for (int i = 1; i <= sz; i++) { fac[i] = (i * fac[i - 1]) % MOD; } ifac[sz] = inv(fac[sz]); for (int i = sz - 1; i >= 0; i--) { ifac[i] = ((i + 1) * ifac[i + 1]) % MOD; } } long long nCr(long long N, long long R) { if (R <= N and R >= 0) { return ((fac[N] * ifac[R]) % MOD * ifac[N - R]) % MOD; } return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; map<long long, long long> pos; long long p[n + 1], q[n + 1]; for (long long i = 1; i <= n; i++) { cin >> p[i]; } for (long long i = 1; i <= n; i++) { cin >> q[i]; pos[q[i]] = i; } long long pt = 1; long long pt_cons = 1; vector<vector<long long>> comp; vector<long long> vec; while (pt <= n) { vec.push_back(p[pt]); pt_cons = max(pt_cons, pos[p[pt]]); if (pt == pt_cons) { comp.push_back(vec); vec.clear(); pt_cons = 1; } pt++; } if (!vec.empty()) { comp.push_back(vec); } if (comp.size() < k) { cout << NO ; return 0; } string ans(n + 1, * ); char x = a ; for (auto u : comp) { for (auto v : u) { ans[v] = x; } x++; if (x == ( z + 1)) { x = z ; } } cout << YES n ; for (long long i = 1; i <= n; i++) { cout << ans[i]; } } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long i = 1, cnt = 0; while (i < k && i < n) { cnt++; i = i * 2; } if (i < n) { cnt += (n - i) / k; if ((n - i) % k) cnt++; } cout << cnt << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int FFTMOD = 119 << 23 | 1; const int INF = (int)1e9 + 23111992; const long long LINF = (long long)1e18 + 23111992; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return val < a ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } inline unsigned long long isqrt(unsigned long long k) { unsigned long long r = sqrt(k) + 1; while (r * r > k) r--; return r; } inline long long icbrt(long long k) { long long r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } inline int sign(long double x) { return x < -EPS ? -1 : x > +EPS; } inline int sign(long double x, long double y) { return sign(x - y); } mt19937 mt(chrono::high_resolution_clock::now().time_since_epoch().count()); inline int mrand() { return abs((int)mt()); } inline int mrand(int k) { return abs((int)mt()) % k; } template <class num_t> struct SegmentTree { struct node_t { num_t max[2]; num_t pref[2]; num_t suff[2]; num_t pref2[2]; num_t suff2[2]; num_t lz; int size; node_t() { lz = 0; size = -1; } }; int n; vector<node_t> st; void init(int n_) { n = n_; st.resize(n << 2); } node_t merge(node_t u, node_t v) { if (u.size == -1) return v; if (v.size == -1) return u; node_t c; for (int i = (0); i < (2); ++i) { c.max[i] = max(u.max[i], v.max[i]); c.pref[i] = u.pref[i]; c.suff[i] = v.suff[i]; c.pref2[i] = u.pref2[i]; c.suff2[i] = v.suff2[i]; } for (int i = (0); i < (2); ++i) { if (u.pref[i] == u.size) { c.pref[i] = u.pref[i] + v.pref[i]; } if (v.suff[i] == v.size) { c.suff[i] = u.suff[i] + v.suff[i]; } if (u.pref[i ^ 1] == u.size) { c.pref2[i] = u.pref[i ^ 1] + v.pref2[i]; } if (v.suff[i ^ 1] == v.size) { c.suff2[i] = u.suff2[i] + v.suff[i ^ 1]; } if (u.pref2[i] == u.size) { chkmax(c.pref2[i], u.pref2[i] + v.pref[i]); } if (v.suff2[i] == v.size) { chkmax(c.suff2[i], u.suff[i] + v.suff2[i]); } } for (int i = (0); i < (2); ++i) { chkmax(c.pref2[i], c.pref[i]); chkmax(c.suff2[i], c.suff[i]); } for (int i = (0); i < (2); ++i) { chkmax(c.max[i], c.pref[i]); chkmax(c.max[i], c.suff[i]); chkmax(c.max[i], c.pref2[i]); chkmax(c.max[i], c.suff2[i]); chkmax(c.max[i], u.suff[i] + v.pref2[i]); chkmax(c.max[i], u.suff2[i] + v.pref[i]); } c.size = u.size + v.size; return c; } void build(int p, int L, int R, vector<int>& a) { if (L == R) { st[p].max[0] = st[p].max[1] = 1; for (int i = (0); i < (2); ++i) { st[p].pref[i] = st[p].pref2[i] = (a[L] == i); st[p].suff[i] = st[p].suff2[i] = (a[R] != i); } st[p].size = 1; return; } build(p << 1, L, L + R >> 1, a); build(p << 1 | 1, (L + R >> 1) + 1, R, a); st[p] = merge(st[p << 1], st[p << 1 | 1]); } void push(int p, int L, int R) { if (st[p].lz) { swap(st[p].max[0], st[p].max[1]); swap(st[p].pref[0], st[p].pref[1]); swap(st[p].suff[0], st[p].suff[1]); swap(st[p].pref2[0], st[p].pref2[1]); swap(st[p].suff2[0], st[p].suff2[1]); if (L < R) { st[p << 1].lz ^= st[p].lz; st[p << 1 | 1].lz ^= st[p].lz; } st[p].lz = 0; } } void upd(int p, int l, int r, int L, int R, num_t val) { push(p, L, R); if (r < L || R < l) return; if (l <= L && R <= r) { st[p].lz = val; push(p, L, R); return; } upd(p << 1, l, r, L, L + R >> 1, val); upd(p << 1 | 1, l, r, (L + R >> 1) + 1, R, val); st[p] = merge(st[p << 1], st[p << 1 | 1]); } node_t query(int p, int l, int r, int L, int R) { push(p, L, R); if (r < L || R < l) return node_t(); if (l <= L && R <= r) { return st[p]; } return merge(query(p << 1, l, r, L, L + R >> 1), query(p << 1 | 1, l, r, (L + R >> 1) + 1, R)); } void upd(int l, int r, num_t val) { upd(1, l, r, 0, n - 1, val); } node_t query(int l, int r) { return query(1, l, r, 0, n - 1); } }; SegmentTree<int> seg; void chemthan() { int n, q; cin >> n >> q; string s; cin >> s; vector<int> a(n); for (int i = (0); i < (n); ++i) a[i] = s[i] == > ; seg.init(n); seg.build(1, 0, n - 1, a); while (q--) { int l, r; cin >> l >> r; l--, r--; seg.upd(l, r, 1); cout << seg.query(l, r).max[0] << n ; } } int main(int argc, char* argv[]) { ios_base::sync_with_stdio(0), cin.tie(0); if (argc > 1) { assert(freopen(argv[1], r , stdin)); } if (argc > 2) { assert(freopen(argv[2], wb , stdout)); } chemthan(); cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> adj1[1000050], adj2[1000050]; bool vis1[1000050], vis2[1000050]; vector<int> ans; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); adj1[u].push_back(v); adj2[v].push_back(u); } for (int i = n; i >= 0; i--) { if (!vis1[i]) { vis1[i] = true; vis2[i] = true; for (auto c : adj1[i]) vis1[c] = true; } } for (int i = 1; i <= n; i++) { if (vis2[i]) { for (auto c : adj2[i]) { if (vis2[c]) vis2[i] = false; } if (vis2[i]) ans.push_back(i); } } printf( %d n , ans.size()); for (auto c : ans) printf( %d , c); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// registerInterface.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Modified by Nathan Larson for the Cloud Car project
//// 10/21/2016
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module registerInterface (
clk,
addr,
dataIn,
writeEn,
dataOut,
myReg0,
myReg1,
myReg2,
myReg3,
myReg4,
myReg5,
myReg6,
myReg7
);
input clk;
input [7:0] addr;
input [7:0] dataIn;
input writeEn;
output [7:0] dataOut;
output [7:0] myReg0;
output [7:0] myReg1;
output [7:0] myReg2;
output [7:0] myReg3;
input [7:0] myReg4;
input [7:0] myReg5;
input [7:0] myReg6;
input [7:0] myReg7;
reg [7:0] dataOut;
reg [7:0] myReg0;
reg [7:0] myReg1;
reg [7:0] myReg2;
reg [7:0] myReg3;
// --- I2C Read
always @(posedge clk) begin
case (addr)
8'h00: dataOut <= myReg0;
8'h01: dataOut <= myReg1;
8'h02: dataOut <= myReg2;
8'h03: dataOut <= myReg3;
8'h04: dataOut <= myReg4;
8'h05: dataOut <= myReg5;
8'h06: dataOut <= myReg6;
8'h07: dataOut <= myReg7;
default: dataOut <= 8'h00;
endcase
end
// --- I2C Write
always @(posedge clk) begin
if (writeEn == 1'b1) begin
case (addr)
8'h00: myReg0 <= dataIn;
8'h01: myReg1 <= dataIn;
8'h02: myReg2 <= dataIn;
8'h03: myReg3 <= dataIn;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int price[100005]; int sum[100005]; vector<int> tempo; int main() { int n, t; scanf( %d , &n); tempo.push_back(0); for (int i = 1; i <= n; i++) { scanf( %d , &t); if (i == 1) { price[i] = 20; sum[i] = 20; tempo.push_back(t); continue; } int fim = i - 1; int ini = (int)(lower_bound(tempo.begin(), tempo.end(), t - 1440 + 1) - tempo.begin()); ini = max(ini - 1, 0); int p = (sum[fim] - sum[ini] >= 120 ? 0 : 120 - (sum[fim] - sum[ini])); ini = (int)(lower_bound(tempo.begin(), tempo.end(), t - 90 + 1) - tempo.begin()); ini = max(ini - 1, 0); int aux = (sum[fim] - sum[ini] >= 50 ? 0 : 50 - (sum[fim] - sum[ini])); price[i] = min(p, min(aux, 20)); sum[i] = sum[i - 1] + price[i]; tempo.push_back(t); } for (int i = 1; i <= n; i++) { printf( %d n , price[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long n, cnt1 = 0, cnt2 = 0, l, r; cin >> n; for (int i = 0; i < n; i++) { cin >> l >> r; cnt1 += l; cnt2 += r; } cout << min(cnt1, n - cnt1) + min(cnt2, n - cnt2); } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const long long N = 4e5; long long fac[N]; long long qpow(long long x, long long y) { long long res = 1; for (; y; y >>= 1, x = x * x % mod) if (y & 1) res = res * x % mod; return res; } long long inv(long long x) { return qpow(x, mod - 2); } long long C(long long x, long long y) { return ((fac[x] * inv(fac[y]) % mod) * inv(fac[x - y])) % mod; } void build() { fac[0] = 1; for (long long i = 1; i < N; i++) fac[i] = fac[i - 1] * i % mod; } long long a[N]; signed main() { ios::sync_with_stdio(0); cin.tie(0); build(); long long n; cin >> n; for (long long i = 0; i < 2 * n; i++) cin >> a[i]; sort(a, a + 2 * n); for (long long i = 0; i < 2 * n; i++) a[i] %= mod; long long ans = 0; for (long long i = 0; i < n; i++) ans = (ans + a[i + n] - a[i] + mod) % mod; cout << ans * C(2 * n, n) % mod << n ; } |
`timescale 1 ps / 1 ps
module ram_r(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
output wire [DATA_WIDTH-1:0] data_fifo_in,
input read_fifo_in,
input start_fifo_in,
input [ADD_WIDTH-1:0] address_fifo_in,
input [DATA_WIDTH-1:0] n_burst_fifo_in,
output wire bussy_fifo_in,
output wire empty_fifo_in,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // derived parameter
parameter MAX_BURST_COUNT_R = 32; // must be a multiple of 2 between 2 and 1024, when bursting is disabled this value must be set to 1
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
wire read_complete;
reg [DATA_WIDTH-1:0] reads_pending;
wire read_burst_end;
reg next_r;
wire too_many_reads_pending;
reg [ADD_WIDTH-1:0] read_address;
reg [DATA_WIDTH-1:0] in_n;
reg [DATA_WIDTH-1:0] in_n_2;
wire fifo_full;
wire fifo_empty;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_in),
.clock(clk),
.data(ram_r_readdata),
.wrreq(read_complete),
.q(data_fifo_in),
.rdreq(read_fifo_in),
.full(fifo_full),
.empty(fifo_empty),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "OFF"; // FIFO latency of 2
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_complete == 1) begin
in_n <= in_n - 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n_2 <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n_2 <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_burst_end == 1) begin
in_n_2 <= in_n_2 - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_in == 1) begin
read_address <= address_fifo_in;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// tracking FIFO
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1; // a burst read was posted, but a word returned
end
end else begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end else begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);// & (header_c > 4);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFO_DEPTH - MAX_BURST_COUNT_R - 4); // make sure there are fewer reads posted than room in the FIFO
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n_2 != 0);// & (header_c > 4);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
assign bussy_fifo_in = in_n != 0;
assign empty_fifo_in = fifo_empty;
assign usedw_fifo_in = fifo_used;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; string to_string(string s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } const int N = 2e3 + 7, M = 1e4, OO = 0x3f3f3f3f; int vis[N][N]; int main() { int TCF = 1; while (TCF--) { int n; scanf( %d , &n); ; vector<pair<int, int>> p; int x, y; for (int i = 0; i < n; ++i) { scanf( %d %d , &x, &y); p.emplace_back(x, y); vis[x + 1000][y + 1000] = 1; } vector<pair<int, int>> mid; int ans = 0; for (int i = (0); i < (n); i++) { for (int j = (i + 1); j < (n); j++) { if (i == j) continue; int mx = p[i].first + p[j].first; int my = p[i].second + p[j].second; if (mx % 2 == 0 && my % 2 == 0) { mx /= 2; my /= 2; if (vis[mx + 1000][my + 1000]) { ans++; } } } } printf( %d n , ans); } } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// testbench for fullchip
module interp_tb();
`include "usrp_tasks.v"
reg clk_120mhz;
reg usbclk;
reg reset;
reg [11:0] adc1_data, adc2_data;
wire [13:0] dac1_data, dac2_data;
wire [5:0] usbctl;
wire [5:0] usbrdy;
wire [15:0] usbdata;
reg WE, RD, OE;
assign usbctl[0] = WE;
assign usbctl[1] = RD;
assign usbctl[2] = OE;
assign usbctl[5:3] = 0;
reg tb_oe;
assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
reg serload, serenable, serclk, serdata;
reg enable_tx, enable_rx;
reg [15:0] usbdatareg;
///////////////////////////////////////////////
// Simulation Control
initial
begin
$dumpfile("interp_tb.vcd");
$dumpvars(0, fc_tb);
end
initial #100000 $finish;
///////////////////////////////////////////////
// Monitors
reg [7:0] counter_interp;
wire [7:0] interp_rate;
assign interp_rate = 32;
initial $monitor(dac1_data);
always @(posedge clk_120mhz)
begin
if(reset | ~enable_tx)
counter_interp <= #1 0;
else if(counter_interp == 0)
counter_interp <= #1 interp_rate - 8'b1;
else
counter_interp <= #1 counter_interp - 8'b1;
end
///////////////////////////////////////////////
// Clock and reset
initial clk_120mhz = 0;
initial usbclk = 0;
always #48 clk_120mhz = ~clk_120mhz;
always #120 usbclk = ~usbclk;
initial reset = 1'b1;
initial #500 reset = 1'b0;
initial enable_tx = 1'b1;
wire [31:0] interp_out, q_interp_out;
wire [31:0] decim_out;
wire [31:0] phase;
cic_interp #(.bitwidth(32),.stages(4))
interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
.strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out));
cic_decim #(.bitwidth(32),.stages(4))
decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
.strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> pair<T1, T2> operator+(pair<T1, T2> a, pair<T1, T2> b) { return make_pair(a.first + b.first, a.second + b.second); } template <typename T1, typename T2> pair<T1, T2> operator-(pair<T1, T2> a, pair<T1, T2> b) { return make_pair(a.first - b.first, a.second - b.second); } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { out << p.first << << p.second; return out; } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.first >> p.second; return in; } template <typename T> ostream& operator<<(ostream& out, vector<T> v) { for (auto a : v) out << a << ; return out; } template <typename T> istream& operator>>(istream& in, vector<T>& v) { for (auto& a : v) in >> a; return in; } template <typename T> ostream& operator<<(ostream& out, multiset<T> S) { for (auto a : S) out << a << ; return out; } template <typename T> ostream& operator<<(ostream& out, set<T> S) { for (auto a : S) out << a << ; return out; } template <typename T> set<T> operator+(set<T> A, set<T> B) { for (auto b : B) A.insert(b); return A; } int main() { string s, t; cin >> s >> t; int i = 0; for (int j = 0; j < t.size(); j++) { if (s[i] == t[j]) i++; } cout << i + 1 << endl; return 0; } |
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dangling_port.v,v 1.1 2001/07/08 03:22:08 sib4 Exp $
// $Log: dangling_port.v,v $
// Revision 1.1 2001/07/08 03:22:08 sib4
// Test for PR#209
//
//
// Test for PR#209, VVP wrong nodangle of dangling port.
module main;
reg retval;
reg a, b;
function f;
input dangle;
begin
f = retval;
end
endfunction
initial
begin
#1 retval <= 1;
#1 a <= f(0);
#1 b <= f(1);
#1 $display("PASSED");
$finish;
end
endmodule
|
//-------------------------------------------------------------------
//-- notas_tb.v
//-- Banco de pruebas para el generador de 8 notas
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module notas_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Salidas de los canales
wire ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7;
//-- Instanciar el componente y establecer el valor del divisor
//-- Se pone un valor bajo para simular (de lo contrario tardaria mucho)
notas #(2, 3, 4, 5, 6, 7, 8, 9)
dut(
.clk(clk),
.ch0(ch0),
.ch1(ch1),
.ch2(ch2),
.ch3(ch3),
.ch4(ch4),
.ch5(ch5),
.ch6(ch6),
.ch7(ch7)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("notas_tb.vcd");
$dumpvars(0, notas_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
module BaudRateGenerator(input [28:0] baudrate, input rst, input clk, output baudclk);
parameter SYS_CLK_RATE = 50000000;
reg [28:0] d;
wire [28:0] dInc = d[28] ? (baudrate) : (baudrate - SYS_CLK_RATE);
always @(posedge clk or posedge rst)
//in case of rst, start couting after T = 1/(baudrate/2)
d <= (rst) ? ((baudrate - SYS_CLK_RATE) >>> 1 ) : d+dInc;
assign baudclk = ~d[28] & ~rst; // this is the BAUD_RATE Hz clock
endmodule
module UART(
// Transmiter part
output tx_busy, // High means UART is transmitting
output reg tx, // UART transmit wire
input wr_i, // Raise to transmit byte
input [7:0] dat_i, // 8-bit data
//Receiver part
input rx,
output rx_busy,
output reg [7:0] rx_reg,
input clk, // System clock, 50 MHz
input rst, // System reset
input [3:0] clk_speed_sel
);
parameter BAUD_RATE = 9600;
parameter BIT_COUNT = 10;
parameter SYS_CLK_RATE = 50000000;
//************************************************
//baudrate selector hw description
reg [28:0] baud_rate;
always @(posedge clk or posedge rst) begin
if (rst) begin
baud_rate <= BAUD_RATE;
end
else begin
case (clk_speed_sel)
4'b1000: baud_rate <= 4800;
4'b0100: baud_rate <= 9600;
4'b0010: baud_rate <= 57600;
4'b0001: baud_rate <= 115200;
endcase
end
end
//************************************************
// UART transmiter description
wire tx_clk;
BaudRateGenerator #(.SYS_CLK_RATE(SYS_CLK_RATE))
txGenerator(.baudrate(baud_rate), .clk(clk), .rst(rst), .baudclk(tx_clk));
reg [3:0] bitcount_tx;
reg [8:0] shifter_tx;
assign tx_busy = | bitcount_tx[3:1];
wire sending = | bitcount_tx;
always @(posedge clk)
begin
if (rst) begin
tx <= 1;
bitcount_tx <= 0;
shifter_tx <= 0;
end
else begin
// just got a new byte
if (wr_i & ~tx_busy)
begin
shifter_tx <= { dat_i, 1'h0 };
bitcount_tx <= (1 + 8 + 1);
end
if (sending & tx_clk) begin
{ shifter_tx, tx } <= { 1'h1, shifter_tx };
bitcount_tx <= bitcount_tx - 1;
end
end
end
//************************************************
// UART receiver description
reg [3:0] bitcount_rx;
reg [7:0] shifter_rx;
wire rx_clk;
BaudRateGenerator #(.SYS_CLK_RATE(SYS_CLK_RATE))
rxGenerator(.baudrate(baud_rate), .clk(clk), .rst(rx_baudrate_rst | rst), .baudclk(rx_clk));
assign rx_busy = | bitcount_rx;
assign rx_baudrate_rst = ~rx_busy;
wire receiving = bitcount_rx > 1;
always @(posedge clk or posedge rst)
begin
if (rst) begin
bitcount_rx <= 0;
shifter_rx <= 0;
end
else begin
if (~rx_busy & ~rx) begin //catch first start bit
shifter_rx <= 0;
bitcount_rx <= BIT_COUNT;
end
else if (rx_clk & receiving) begin
shifter_rx <= { rx, shifter_rx[7:1] }; //push start bit and 8 payload bits
bitcount_rx <= bitcount_rx - 1; //decrement count of expected bits
end
else if (rx_clk & rx_busy)
bitcount_rx <= 0; //catch last stop bit
end
end
always @(negedge rx_busy or posedge rst)
rx_reg <= rst ? 0 : shifter_rx;
endmodule |
#include <bits/stdc++.h> int f[100001]; int a[100001]; using namespace std; int main() { bool isAm = false; long long int n, m, x; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> x; if (f[x] == 0) f[x] = i + 1; else f[x] = -1; } for (int i = 0; i < m; i++) { cin >> x; if (f[x] == 0) { cout << Impossible ; return 0; } else if (f[x] != -1) { a[i] = f[x]; } else isAm = true; } if (isAm) { cout << Ambiguity ; return 0; } cout << Possible n ; for (int i = 0; i < m; i++) cout << a[i] << ; return 0; } |
module Process
(
input Clock, press, reset,
input [7:0] voltage, current,
input [3:0] key, bit1, bit2, bit3,
output reg [3:0] out0, out1, out2, out3,
output reg dip
);
reg[7:0] age, vol, cur;
reg[3:0] temp0, temp1, temp2, temp3, dig0, dig1, dig2, dig3;
reg[1:0] state, setting;
reg[25:0] height, weight, BMI, TBW, sex;
reg[10:0] count, flash;
wire[3:0] BMI1, BMI2, BMI3, TBW1, TBW2, TBW3;
parameter
Welcome = 2'b00,
Set = 2'b01,
Measure = 2'b10,
Read = 2'b11;
parameter
Ready = 2'b00,
Sex = 2'b01,
Age = 2'b10,
Height = 2'b11;
always @(posedge press /*or negedge reset*/)
begin
/** if(!reset)
begin
setting <= Sex;
age <= 0;
sex <= 0;
height <= 0;
end
else */if(key == 4'hc)
begin
setting <= Sex;
{dig3, dig2, dig1, dig0} <= 16'b0101111111111111;
age <= 0;
sex <= 0;
height <= 0;
end
else if(state == Set)
begin
if(setting == Sex)
begin
if(key == 1 || key == 2)
begin
sex <= key;
dig0 <= key;
end
else if(key == 4'ha)
begin
sex <= 0;
dig0 <= 4'b1111;
end
else if(key == 4'hb && sex)
begin
{dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
setting <= Age;
end
end
else if(setting == Age)
begin
if(key < 10 && age < 15)
begin
age <= age*10+key;
dig0 <= key;
dig2 = dig1;
if(age)
dig1 <= dig0;
end
else if(key == 4'ha)
begin
age <= 0;
{dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
end
else if(key == 4'hb && age)
begin
setting <= Height;
{dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
end
end
else if(setting == Height)
begin
if(key < 10 && height < 25)
begin
height <= height*10+key;
dig0 <= key;
dig2 <= dig1;
if(height)
dig1 <= dig0;
end
else if(key == 4'ha)
begin
height <= 0;
{dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
end
else if(key == 4'hb && height)
begin
height <= height * height;
setting <= Ready;
{dig3, dig2, dig1, dig0} <= 16'b1001101110111101;
end
end
end
end
always @(posedge Clock /*or negedge reset*/)
begin
/* if(!reset)
begin
state <= Welcome;
count <= 0;
end
else*/ if(setting == Sex)
begin
state <= Set;
count <= 0;
flash <= 0;
end
else
begin
case(state)
Set:
if(setting == Ready)
begin
count <= count+1;
if(count == 250)
begin
state <= Measure;
count <= 0;
end
end
else
count <= 0;
Measure:
begin
if(count == 500)
begin
flash <= flash+1;
BMI <= weight * 100000 / height;
TBW <= 1000 - ((height * current / voltage) /512 + sex * 4 + weight /4) * 100 /73;
if(flash == 500)
begin
state <= Read;
flash <= 750;
count <= 0;
end
end
else
begin
if(temp2 == bit2 && temp3 == bit3)
count <= count+1;
else
count <= 0;
temp1 <= bit1;
temp2 <= bit2;
temp3 <= bit3;
weight <= temp3*100+temp2*10+temp1;
end
end
Read:
begin
if(!flash)
flash <= 750;
else
flash <= flash-1;
if(count)
begin
count <= count+1;
if(count == 2000)
begin
state <= Measure;
flash <= 0;
count <= 0;
end
end
else if(!(bit3 && bit2 && bit1))
count <= count+1;
end
default:
begin
/* if(count)
begin
count <= count+1;
if(count == 500)
begin
{temp3, temp2, temp1, temp0} <= 16'b1100111011001110;
count <= 0;
state <= Set;
end
end
else
count <= count+1;*/
end
endcase
end
end
BinToDec b1(.Code(BMI[7:0]),.bit1(BMI1),.bit2(BMI2),.bit3(BMI3));
BinToDec b2(.Code(TBW[7:0]),.bit1(TBW1),.bit2(TBW2),.bit3(TBW3));
always @(state or bit1 or bit2 or bit3 or flash)
begin
case(state)
/*Welcome:
{out3, out2, out1, out0} = 16'b1100111011001110;*/
Set:
begin
{out3, out2, out1, out0} <= {dig3, dig2, dig1, dig0};
dip <= 0;
end
Measure:
begin
dip <= 0;
if((flash>0 && flash<125) || (flash>250 && flash<375))
{out3, out2, out1, out0} <= 16'b1111111111111111;
else
{out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
end
Read:
if(flash>500)
begin
{out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
dip <= 0;
end
else if(flash>250)
begin
{out3, out2, out1, out0} <= {4'b1111, BMI3, BMI2, BMI1};
dip <= 1;
end
else
begin
{out3, out2, out1, out0} <= {4'b1111, TBW3, TBW2, TBW1};
dip <= 1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(0) * 2; const double EPS = 1e-8; const long long MOD = 1e9 + 7; const int MAXN = 1e4 + 5; const int oo = 1e9; const double foo = 1e30; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcounll(s); } template <class T> T sqr(T x) { return x * x; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } int n; long double val[MAXN], f[MAXN]; vector<int> has[MAXN], ans; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int s, r; scanf( %d%d , &s, &r); if (r > val[s]) { val[s] = r; has[s].clear(); } if (r == val[s]) has[s].push_back(i); } for (int i = 1; i <= 10000; i++) { if (!has[i].empty()) f[i] = val[i] / i; } for (int i = 1; i <= 10000; i++) { if (has[i].empty()) continue; long double r = 10000000000000.0; long double l = 0; int cant = 0; for (int j = 1; j < i; j++) { if (!has[j].empty() && val[j] > val[i]) { long double tmp = ((long double)i - (long double)j) / (val[j] - val[i]) * f[i] * f[j]; r = min(r, tmp); } } for (int j = i + 1; j <= 10000; j++) { if (cant) break; if (!has[j].empty()) { if (val[i] > val[j]) { long double tmp = ((long double)j - (long double)i) / (val[i] - val[j]) * f[i] * f[j]; l = max(l, tmp); } else cant = 1; } } if ((l == 10000000000000.0 || r == 0 || l <= r) && !cant) { for (int j = 0; j < ((int)(has[i]).size()); j++) { ans.push_back(has[i][j]); } } } sort(ans.begin(), ans.end()); for (int i = 0; i < ((int)(ans).size()); i++) { printf( %d , ans[i] + 1); } } |
#include <bits/stdc++.h> using namespace std; const int maxN = 1e6 + 5; int n, x, y, ile[4 * maxN]; long long pref[4 * maxN], mini = 1e18; bool czy = 0; long long spr(long long x, long long y) { long long t; if (__builtin_smulll_overflow(x, y, &t)) czy = 1; return x * y; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> x >> y; for (int i = 0, a; i < n; i++) cin >> a, ile[a]++, pref[a] += a; for (int i = 1; i < 4 * maxN; i++) ile[i] += ile[i - 1], pref[i] += pref[i - 1]; for (int i = 2; i < maxN; i++) { long long temp = 0; int f = max<double>(0, ceil(i - double(x) / y) - 1); czy = 0; for (int j = 0; i * j < maxN && !czy; j++) { temp += (long long)(ile[i * j + f] - ile[i * j]) * x; if (temp < 0) czy = 1; temp += spr(spr(i * j + i, ile[i * j + i] - ile[i * j + f]) - (pref[i * j + i] - pref[i * j + f]), y); if (temp < 0) czy = 1; } if (!czy) { mini = min(mini, temp); } } cout << mini << endl; return 0; } |
// DESCRIPTION: Verilator: Demonstrate deferred linking error messages
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
interface foo_intf;
logic a;
endinterface
function integer the_other_func (input integer val);
return val;
endfunction
module t (/*AUTOARG*/);
localparam N = 4;
foo_intf foos [N-1:0] ();
logic [ 7 : 0 ] bar;
// Non-constant dotted select is not allowed
assign foos[bar].a = 1'b1;
baz baz_inst ();
// Unsure how to produce V3Param AstCellRef visitor errors
//assign baz_inst.x = 1'b1;
//assign baz_inst.N = 1'b1;
//assign baz_inst.7 = 1'b1;
//assign baz_inst.qux_t = 1'b1;
//assign baz_inst.the_func = 1'b1;
//assign baz_inst.the_lp = 1'b1;
//assign bar.x = 1'b1;
//assign fake_inst.x = 1'b1;
//assign the_other_func.x = 1'b1;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module baz;
typedef integer qux_t;
function integer the_func (input integer val);
return val;
endfunction
localparam the_lp = 5;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c, d; cin >> a >> b >> c >> d; int c1 = 0, c2 = 0, c3 = 0, c4 = 0; if ((a.size() - 2) >= (b.size() - 2) * 2 && (a.size() - 2) >= (c.size() - 2) * 2 && (a.size() - 2) >= (d.size() - 2) * 2) { c1 = 1; } else if ((a.size() - 2) * 2 <= (b.size() - 2) && (a.size() - 2) * 2 <= (c.size() - 2) && (a.size() - 2) * 2 <= (d.size() - 2)) { c1 = 1; } if ((b.size() - 2) >= (a.size() - 2) * 2 && (b.size() - 2) >= (c.size() - 2) * 2 && (b.size() - 2) >= (d.size() - 2) * 2) { c2 = 1; } else if ((b.size() - 2) * 2 <= (a.size() - 2) && (b.size() - 2) * 2 <= (c.size() - 2) && (b.size() - 2) * 2 <= (d.size() - 2)) { c2 = 1; } if ((c.size() - 2) >= (a.size() - 2) * 2 && (c.size() - 2) >= (b.size() - 2) * 2 && (c.size() - 2) >= (d.size() - 2) * 2) { c3 = 1; } else if ((c.size() - 2) * 2 <= (a.size() - 2) && (c.size() - 2) * 2 <= (b.size() - 2) && (c.size() - 2) * 2 <= (d.size() - 2)) { c3 = 1; } if ((d.size() - 2) >= (a.size() - 2) * 2 && (d.size() - 2) >= (b.size() - 2) * 2 && (d.size() - 2) >= (c.size() - 2) * 2) { c4 = 1; } else if ((d.size() - 2) * 2 <= (a.size() - 2) && (d.size() - 2) * 2 <= (b.size() - 2) && (d.size() - 2) * 2 <= (c.size() - 2)) { c4 = 1; } if (c1 + c2 + c3 + c4 > 1 || c1 + c2 + c3 + c4 == 0) cout << c[0] << endl; else { if (c1 == 1) cout << a[0] << endl; else if (c2 == 1) cout << b[0] << endl; else if (c3 == 1) cout << c[0] << endl; else if (c4 == 1) cout << d[0] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, maxn = 1000001; long long t[maxn]; void init() { for (int i = 0; i <= 1000000; i++) t[i] = (long long)i * i * i; } int main() { init(); int n, a, b; scanf( %d , &n); while (n--) { scanf( %d%d , &a, &b); long long c = (long long)a * b; int pos = lower_bound(t, t + maxn, c) - t; if ((long long)pos * pos * pos == c && a % pos == 0 && b % pos == 0) printf( Yes n ); else printf( No n ); } return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp_block
(
preIntegrator,
preSat,
saturated,
Clamp
);
input signed [35:0] preIntegrator; // sfix36_En29
input signed [35:0] preSat; // sfix36_En23
input saturated;
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S17>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S17>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp_block
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: unencoded_cam_lut_sm.v
// Project: NF2.1
// Description: controls an unencoded muli-match cam and provides a LUT.
// Matches data and provides reg access
//
///////////////////////////////////////////////////////////////////////////////
module unencoded_cam_lut_sm
#(parameter CMP_WIDTH = 32,
parameter DATA_WIDTH = 3,
parameter LUT_DEPTH = 16,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH),
parameter DEFAULT_DATA = 0, // DATA to return on a miss
parameter RESET_DATA = {DATA_WIDTH{1'b0}}, // value of data on reset
parameter RESET_CMP_DATA = {CMP_WIDTH{1'b0}}, // value of compare datae on reset
parameter RESET_CMP_DMASK = {CMP_WIDTH{1'b0}} // value compare of data mask on reset
)
(// --- Interface for lookups
input lookup_req,
input [CMP_WIDTH-1:0] lookup_cmp_data,
input [CMP_WIDTH-1:0] lookup_cmp_dmask,
output reg lookup_ack,
output reg lookup_hit,
output [DATA_WIDTH-1:0] lookup_data,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] rd_addr, // address in table to read
input rd_req, // request a read
output [DATA_WIDTH-1:0] rd_data, // data found for the entry
output [CMP_WIDTH-1:0] rd_cmp_data, // matching data for the entry
output [CMP_WIDTH-1:0] rd_cmp_dmask, // don't cares entry
output reg rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] wr_addr,
input wr_req,
input [DATA_WIDTH-1:0] wr_data, // data found for the entry
input [CMP_WIDTH-1:0] wr_cmp_data, // matching data for the entry
input [CMP_WIDTH-1:0] wr_cmp_dmask, // don't cares for the entry
output reg wr_ack,
// --- CAM interface
input cam_busy,
input cam_match,
input [LUT_DEPTH-1:0] cam_match_addr,
output [CMP_WIDTH-1:0] cam_cmp_din,
output reg [CMP_WIDTH-1:0] cam_din,
output reg cam_we,
output reg [LUT_DEPTH_BITS-1:0] cam_wr_addr,
output [CMP_WIDTH-1:0] cam_cmp_data_mask,
output reg [CMP_WIDTH-1:0] cam_data_mask,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//-------------------- Internal Parameters ------------------------
localparam RESET = 0;
localparam READY = 1;
//---------------------- Wires and regs----------------------------
reg [LUT_DEPTH_BITS-1:0] lut_rd_addr;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut_rd_data;
reg [DATA_WIDTH-1:0] lut_wr_data;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut[LUT_DEPTH-1:0];
reg lookup_latched;
reg cam_match_found;
reg cam_lookup_done;
reg rd_req_latched;
reg cam_match_encoded;
reg cam_match_found_d1;
reg [LUT_DEPTH-1:0] cam_match_unencoded_addr;
reg [LUT_DEPTH_BITS-1:0] cam_match_encoded_addr;
reg lookup_latched_first_time;
// synthesis attribute PRIORITY_EXTRACT of cam_match_encoded_addr is force;
integer i;
/* used to track the addresses for resetting the CAM and the LUT */
reg [LUT_DEPTH_BITS:0] reset_count;
reg state;
//------------------------- Logic --------------------------------
assign cam_cmp_din = lookup_cmp_data;
assign cam_cmp_data_mask = lookup_cmp_dmask;
assign lookup_data = (lookup_hit & lookup_ack) ? lut_rd_data[DATA_WIDTH-1:0] : DEFAULT_DATA;
assign rd_data = lut_rd_data[DATA_WIDTH-1:0];
assign rd_cmp_data = lut_rd_data[DATA_WIDTH+CMP_WIDTH-1:DATA_WIDTH];
assign rd_cmp_dmask = lut_rd_data[DATA_WIDTH+2*CMP_WIDTH-1:DATA_WIDTH+CMP_WIDTH];
/* encode the match address */
always @(*) begin
cam_match_encoded_addr = LUT_DEPTH[LUT_DEPTH_BITS-1:0] - 1'b1;
for (i = LUT_DEPTH-2; i >= 0; i = i-1) begin
if (cam_match_unencoded_addr[i]) begin
cam_match_encoded_addr = i[LUT_DEPTH_BITS-1:0];
end
end
end
always @(posedge clk) begin
if(reset) begin
lookup_latched <= 0;
cam_match_found <= 0;
cam_lookup_done <= 0;
rd_req_latched <= 0;
lookup_ack <= 0;
lookup_hit <= 0;
cam_we <= 0;
cam_wr_addr <= 0;
cam_din <= 0;
cam_data_mask <= 0;
wr_ack <= 0;
state <= RESET;
reset_count <= 0;
end // if (reset)
else begin
if (state == RESET && !cam_busy) begin
if(reset_count == LUT_DEPTH) begin
state <= READY;
cam_we <= 1'b0;
end
else begin
reset_count <= reset_count + 1'b1;
cam_we <= 1'b1;
cam_wr_addr <= reset_count[LUT_DEPTH_BITS-1:0];
cam_din <= RESET_CMP_DATA;
cam_data_mask <= RESET_CMP_DMASK;
lut_wr_data <= RESET_DATA;
end
end
else if (state == READY) begin
/* first pipeline stage -- do CAM lookup */
lookup_latched_first_time <= lookup_req;
lookup_latched <= lookup_latched_first_time;
/* second pipeline stage -- CAM result/LUT input*/
cam_match_found <= lookup_latched & cam_match;
cam_lookup_done <= lookup_latched;
cam_match_unencoded_addr <= cam_match_addr;
/* third pipeline stage -- encode the CAM output */
cam_match_encoded <= cam_lookup_done;
cam_match_found_d1 <= cam_match_found;
lut_rd_addr <= (!cam_match_found && rd_req) ? rd_addr : cam_match_encoded_addr;
rd_req_latched <= (!cam_match_found && rd_req);
/* fourth pipeline stage -- read LUT */
lookup_ack <= cam_match_encoded;
lookup_hit <= cam_match_found_d1;
lut_rd_data <= lut[lut_rd_addr];
rd_ack <= rd_req_latched;
/* Handle writes */
if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin
cam_we <= 1;
cam_wr_addr <= wr_addr;
cam_din <= wr_cmp_data ;
cam_data_mask <= wr_cmp_dmask;
wr_ack <= 1;
lut_wr_data <= wr_data;
end
else begin
cam_we <= 0;
wr_ack <= 0;
end // else: !if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1)
end // else: !if(state == RESET)
end // else: !if(reset)
// separate this out to allow implementation as BRAM
if(cam_we) begin
lut[cam_wr_addr] <= {cam_data_mask, cam_din, lut_wr_data};
end
end // always @ (posedge clk)
endmodule // cam_lut_sm
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module clk_div(
input clk,
input wire rst,
input wire SW2,
output reg[31:0] clkdiv,
output wire Clk_CPU
);
always @(posedge clk or posedge rst)begin
if (rst) begin
clkdiv <= 0;
end else begin
clkdiv <= clkdiv + 1'b1;
end
end
//assign Clk_CPU = SW2?clkdiv[30]:clkdiv[1];
assign Clk_CPU = clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 5; long long a[N]; int32_t tree[N << 2], bit_cnt[N]; struct seg_tree { long long combine(long long x, long long y) { return max(x, y); } void build(long long l, long long r, long long node) { if (l == r) { tree[node] = bit_cnt[l]; return; } long long mid = (l + r) >> 1, lc = node + node, rc = 1 + lc; build(l, mid, lc); build(mid + 1, r, rc); tree[node] = combine(tree[lc], tree[rc]); } long long query(long long l, long long r, long long ql, long long qr, long long node) { if (qr < l || r < ql) return 0; if (ql <= l and r <= qr) { return tree[node]; } long long mid = (l + r) >> 1, lc = node + node, rc = 1 + lc; return combine(query(l, mid, ql, qr, lc), query(mid + 1, r, ql, qr, rc)); } }; long long dp[N][2]; long long prefix_sum[N]; void solve() { long long n; cin >> n; for (long long i = 1; i <= n; ++i) { cin >> a[i]; bit_cnt[i] = __builtin_popcountll(a[i]); } seg_tree ins; ins.build(1, n, 1); for (long long i = 1; i <= n; ++i) { prefix_sum[i] = bit_cnt[i] + prefix_sum[i - 1]; } dp[0][0] = 1; map<long long, long long> mp; mp[0] = 1; long long ans = 0; for (long long i = 1; i <= n; ++i) { long long c = prefix_sum[i] & 1LL; dp[i][0] = dp[i - 1][0]; dp[i][1] = dp[i - 1][1]; dp[i][c] += 1; ans += dp[i - 1][c]; long long res = -1, mx = bit_cnt[i]; long long sum = 0; for (long long j = i; i - j <= 62 && j > 0; --j) { mx = max(mx, (long long)bit_cnt[j]); sum += bit_cnt[j]; if ((sum - mx < mx) && (sum & 1) == 0) { --ans; } } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; for (long long i = 1; i <= t; ++i) { solve(); } return 0; } |
// Name: WcaWriteWordReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaWriteWordReg
(
input wire reset,
output wire [15:0] out, //Output data.
output wire nd, //new data available indicator.
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire write = addrValid & rbusCtrl[2];
assign nd = write & select == 1'h1;
//Alternate Register for two pulse read.
reg select;
always @(posedge rbusCtrl[0])
begin
if( reset | ~addrValid)
select <= 1'h0;
else if(rbusCtrl[1] & addrValid)
select <= ~select;
end
WcaRegCore8 sr1( .Data(rbusData), .Enable( write & select == 1'h1), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[15:8]));
WcaRegCore8 sr0( .Data(rbusData), .Enable( write & select == 1'h0), .Aclr(reset), .Clock(rbusCtrl[0]), .Q(out[7:0]));
endmodule // WcaWriteWordReg |
#include <bits/stdc++.h> using namespace std; int n, k, l, r, mid, a; int main() { cin >> n >> k; a = 240 - k; l = 0; r = n + 1; while (r - l > 1) { mid = (r + l) / 2; if (5 * (mid * (mid + 1) / 2) > a) { r = mid; } else { l = mid; } } cout << l << endl; return 0; } |
#include <bits/stdc++.h> const int inf = 1e9; const double eps = 1e-9; const int mod = 1e9 + 7; using namespace std; int mypow(int x, int y) { int res = 1; for (; y >= 1; y >>= 1) { if (y & 1) res = (1ll * res * x) % mod; x = (1ll * x * x) % mod; } return res; } int32_t main() { long long n; int k; cin >> n >> k; vector<long long> p; vector<int> al; long long x = n; for (long long i = 2; i * i <= x; ++i) { if (!(x % i)) { p.push_back(i); al.push_back(0); } int c = 0; while (!(x % i)) { al[al.size() - 1]++; x /= i; } } if (x != 1) { p.push_back(x); al.push_back(1); } int ans = 1; for (int o = 0; o < p.size(); ++o) { vector<vector<int>> dp(k + 1, vector<int>(al[o] + 1, 0)); dp[0][al[o]] = 1; for (int i = 1; i <= k; ++i) { for (int j = 0; j <= al[o]; ++j) { int s = (1ll * dp[i - 1][j] * mypow(j + 1, mod - 2)) % mod; for (int h = 0; h <= j; ++h) { dp[i][h] = (dp[i][h] + s) % mod; } } } int l = 0; int r = 1; for (int j = 0; j <= al[o]; ++j) { l = (l + (1ll * dp[k][j] * r) % mod) % mod; r = (1ll * r * (p[o] % mod)) % mod; } ans = (1ll * ans * l) % mod; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int t, m; int a[128], id = 1; int main() { cin >> t >> m; for (int i = 0; i < t; ++i) { string q; cin >> q; switch (q[0]) { case a : { int k; bool ok = false; cin >> k; for (int i = 0; i + k <= m; ++i) { int j = 0; for (j = 0; j < k && a[i + j] == 0; ++j) ; if (j == k) { ok = true; for (int j = 0; j < k; ++j) a[i + j] = id; break; } } if (ok) cout << id++ << endl; else puts( NULL ); break; } case e : { bool ok = false; int x; cin >> x; if (x > 0) { for (int i = 0; i < m; ++i) if (a[i] == x) ok = true, a[i] = 0; } if (!ok) puts( ILLEGAL_ERASE_ARGUMENT ); break; } case d : for (int i = remove(a, a + m, 0) - a; i < m; ++i) a[i] = 0; break; } } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) #pragma warning(disable : 4786) using namespace std; int MIN(int a, int b) { return a < b ? a : b; } int MAX(int a, int b) { return a > b ? a : b; } int GCD(int a, int b) { while (b) b ^= a ^= b ^= a %= b; return a; } int LCM(int a, int b) { return a * (b / GCD(a, b)); } void SWAP(int &a, int &b) { a = a ^ b; b = a ^ b; a = a ^ b; } const double PI = acos(-1); const double EPS = 1e-11; int arr[310][310], memo[310][310][310], N, M; int dp(int i, int j, int k) { int l = i + j - k; if (i == N - 1 && j == M - 1) { return arr[i][j]; } if (i == N || j == M || k >= N || l >= N) { return -(1 << 29); ; } int &ret = memo[i][j][k]; if (ret != -1) { return ret; } int res, r1, val; res = -(1 << 29); ; if (i == k && j == l) { val = arr[i][j]; } else { val = arr[i][j] + arr[k][l]; } r1 = dp(i + 1, j, k + 1) + val; res = MAX(res, r1); r1 = dp(i + 1, j, k) + val; res = MAX(res, r1); r1 = dp(i, j + 1, k + 1) + val; res = MAX(res, r1); r1 = dp(i, j + 1, k) + val; res = MAX(res, r1); return ret = res; } int main() { int T, res, n, i, ind, m, j; while (scanf( %d , &n) != EOF) { int a = -(1 << 29); ; memset(memo, -1, sizeof(memo)); memset(arr, 0, sizeof(arr)); m = n; for (i = 0; i < (n); i++) { for (j = 0; j < (m); j++) { scanf( %d , &arr[i][j]); } } N = n; M = m; res = dp(0, 0, 0); printf( %d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { bool b = 0; char c; while (!isdigit(c = getchar()) && c != - ) ; if (c == - ) c = getchar(), b = 1; x = c - 48; while (isdigit(c = getchar())) x = (x << 3) + (x << 1) + c - 48; if (b) x = -x; } template <typename T> inline void wrip(T x) { if (x > 9) wrip(x / 10); putchar(x % 10 + 48); } template <typename T> inline void write(T x) { if (x < 0) putchar( - ), x = -x; wrip(x); putchar( ); } template <typename T> inline void writeln(T x) { if (x < 0) putchar( - ), x = -x; wrip(x); putchar( n ); } inline char readch() { char c; do c = getchar(); while (c == n || c == ); return c; } inline void reads(string &s) { char c; while ((c = getchar()) == || c == n ) ; s = c; while ((c = getchar()) != && c != n && c != EOF) s += c; } inline void getlines(string &s) { char c; while ((c = getchar()) == n ) ; s = c; while ((c = getchar()) != n ) s += c; } const long double pi = acos(-1); const int inf = 1e9, mod = 1e9 + 7, N = 1e6 + 11; int n; long long m, a[N], cnt[N], pwm[N]; inline long long pw(long long a, long long b) { long long res = 1; while (b) { if (b % 2) res = res * a % mod; a = a * a % mod; b /= 2; } return res; } int main() { int ntest; read(ntest); while (ntest--) { read(n); read(m); for (int i = 1; i <= n; i++) read(a[i]); if (m == 1) { if (n % 2) cout << 1 << n ; else cout << 0 << n ; continue; } for (int i = 1; i <= n; i++) cnt[a[i]]++; sort(a + 1, a + n + 1); n = unique(a + 1, a + n + 1) - a - 1; reverse(a + 1, a + n + 1); long long lim = 2e6, res = 0; long long Max = 0; pwm[0] = 1; for (int i = 1; i <= 1e6; i++) { pwm[i] = pwm[i - 1] * m; if (pwm[i] >= 1e7) { Max = i; break; } } for (int i = 1; i <= n; i++) { if (cnt[a[i]] % 2 == 0) continue; long long num = 1, sum = 0; for (int j = i + 1; j <= n; j++) { num *= pwm[min(Max, a[j - 1] - a[j])]; if (num <= cnt[a[j]]) { cnt[a[j]] -= num; goto line0; } sum = (sum + pw(m, a[j]) * cnt[a[j]]) % mod; num -= cnt[a[j]]; cnt[a[j]] = 0; if (num >= lim) break; } for (int j = i + 1; j <= n; j++) if (cnt[a[j]]) sum = (sum + pw(m, a[j]) * cnt[a[j]]) % mod; res = (pw(m, a[i]) - sum + mod) % mod; break; line0:; } for (int i = 1; i <= n; i++) cnt[a[i]] = 0; cout << res << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_LP__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long dx[8] = {-1, 1, 0, 0, 1, -1, 1, -1}; long long dy[8] = {0, 0, -1, 1, 1, -1, -1, 1}; void solve() { long long n, m; cin >> n >> m; char a[n][m]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) cin >> a[i][j]; } bool f = 1; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == . ) { for (long long k = 0; k < 8; k++) { long long x = i + dx[k]; long long y = j + dy[k]; if (x < 0 || x >= n || y < 0 || y >= m) continue; if (a[x][y] == * ) { cout << NO ; return; } } } else if (a[i][j] >= 1 && a[i][j] <= 8 ) { long long cnt = 0; for (long long k = 0; k < 8; k++) { long long x = i + dx[k]; long long y = j + dy[k]; if (x < 0 || x >= n || y < 0 || y >= m) continue; if (a[x][y] == * ) cnt++; } if (cnt != a[i][j] - 0 ) { cout << NO ; return; } } } } cout << YES ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { solve(); } } |
module receive_top_module (
//input
input clk_50M ,
input clk_100M ,
input reset_n ,
//output
output [7:0] Trans_Data
);
//wire
wire [11:0] Data_A ;
wire [11:0] Data_B ;
wire [11:0] Data_C ;
wire [11:0] Data_D ;
wire [11:0] Data_E ;
wire [11:0] Data_F ;
wire [11:0] Data_G ;
wire [11:0] Data_H ;
wire [7:0] Line_Num;
wire [1:0] Focus_Num;
wire Pr_Gate ;
wire RX_Gate ;
wire Sample_Gate;
wire End_Gate ;
wire [15:0] DAS_Value;
wire So_Gate;
wire [7:0] Coheren_Coff;
wire [29:0] Match_Filter_Data;
wire MF_Output_RDY;
wire MF_Output_Valid;
wire [29:0] ABS_Data ;
wire LF_Valid ;
wire [30:0] LF_Data ;
wire [12:0] Log_IN ;
wire [7:0] Log_OUT ;
wire [7:0] Base_Noise1 ;
wire [7:0] Base_Noise2 ;
wire [7:0] Line_Num_Test;
wire [7:0] Trans_Data1 ;
wire [7:0] Trans_Data2 ;
wire [8:0] Trans_Data_buf;
wire [1:0] Zoom ;
wire Envelop ;
//reg
reg [8:0] WR_RAM_ADDR ;
reg [7:0] LF_Reg ;
reg [7:0] Interlace_Counter ;
reg [7:0] Log1,Log2,Log3,Log4 ;
reg [7:0] Log5,Log6,Log7,Log8 ;
reg [7:0] Log9,Log10,Log11,Log12 ;
reg [7:0] Log13,Log14,Log15 ;
reg [11:0] Sum_Log ;
reg [15:0] Sample_Counter ;
reg Seg_Enable ;
reg [7:0] Interlace ;
reg [1:0] Toggle ;
reg CC3200_SPI_CS ;
reg [11:0] cs_num ;
assign Zoom = 2'b00 ;
//combination
always @(*)
begin
case(Zoom)
2'b00: //90mm
Interlace <= 8'd10;
2'b01: //130mm
Interlace <= 8'd15;
2'b10: //160mm
Interlace <= 8'd19;
2'b11: //200mm
Interlace <= 8'd24;
endcase
end
always @(posedge Envelop)
begin
Toggle <= Toggle + 1'b1;
end
//seq
always @(posedge clk_50M or negedge LF_Valid )
begin
if(~LF_Valid)
begin
Interlace_Counter <= 8'd0;
WR_RAM_ADDR[8:0] <= 8'd0;
Sample_Counter <= 16'd0;
end
else
begin
Log15 <= Log14;
Log14 <= Log13;
Log13 <= Log12;
Log12 <= Log11;
Log11 <= Log10;
Log10 <= Log9;
Log9 <= Log8;
Log8 <= Log7;
Log7 <= Log6;
Log6 <= Log5;
Log5 <= Log4;
Log4 <= Log3;
Log3 <= Log2;
Log2 <= Log1;
Log1 <= Log_OUT;
Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;
if(Sample_Counter <16'd16000)
begin
Sample_Counter <= Sample_Counter + 1'b1;
end
if(Sample_Counter <=16'd2000)
begin //<30mm
if(Focus_Num[1:0] == 2'b00)
begin
Seg_Enable <= 1'b1;
end
else
begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise1)? (Sum_Log[11:4]-Base_Noise1):8'd0 ;
end
else
begin
if(Focus_Num[1:0] == 2'b11)
begin
Seg_Enable <= 1'b1;
end
else
begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise2)? (Sum_Log[11:4]-Base_Noise2): 8'd0 ;
end
if(Interlace_Counter < Interlace)
begin
Interlace_Counter <= Interlace_Counter + 1'b1;
end
else
begin
if(WR_RAM_ADDR[8:0] <9'd511)
begin
WR_RAM_ADDR[8:0] <= WR_RAM_ADDR[8:0] + 1'b1;
end
Interlace_Counter <= 8'd0;
end
end
end
always @(posedge clk_50M or negedge reset_n )
begin
if (!reset_n)
begin
cs_num <= 0;
CC3200_SPI_CS <= 0;
end
else if (cs_num<3)
begin
cs_num <= cs_num +1 ;
CC3200_SPI_CS <= 0;
end
else if (cs_num<6)
begin
cs_num <= cs_num +1 ;
CC3200_SPI_CS <= 1;
end
else
begin
cs_num <= 0;
CC3200_SPI_CS <= 0;
end
end
//initiation
receive_data_gen receive_data_gen (
//input
.clk_50M (clk_50M),
.clk_100M (clk_100M),
.reset_n (reset_n),
//output
.Data_A (Data_A),
.Data_B (Data_B) ,
.Data_C (Data_C) ,
.Data_D (Data_D),
.Data_E (Data_E),
.Data_F (Data_F),
.Data_G (Data_G ),
.Data_H (Data_H),
.Line_Num (Line_Num),
.Focus_Num (Focus_Num),
.Pr_Gate (Pr_Gate),
.RX_Gate (RX_Gate),
.Sample_Gate(Sample_Gate),
.Envelop (Envelop),
.End_Gate (End_Gate)
);
Receive Receive_module (
//input
.AD_CLK (clk_50M),
.Data_A (Data_A),
.Data_B (Data_B),
.Data_C (Data_C),
.Data_D (Data_D),
.Data_E (Data_E),
.Data_F (Data_F),
.Data_G (Data_G),
.Data_H (Data_H),
.Line_Num (Line_Num),
.Focus_Num (Focus_Num),
.Pr_Gate (Pr_Gate),
.RX_Gate (RX_Gate),
.Sample_Gate (Sample_Gate),
.End_Gate (End_Gate),
//output
.So_Gate (So_Gate),
.DAS_Value (DAS_Value),
.Coheren_Coff(Coheren_Coff)
);
matchfilter MatchFilter_module(
//input
.clk (clk_50M),
.reset_n (1'b1),
.ast_sink_data (DAS_Value[14:0]), //15bit
.ast_sink_valid (So_Gate),
.ast_source_ready (1'b1),
.ast_sink_error (2'b00),
//output
.ast_source_data (Match_Filter_Data), //30bit
.ast_sink_ready (MF_Output_RDY),
.ast_source_valid(MF_Output_Valid),
.ast_source_error()
);
ABS ABS_module (
//input
.data (Match_Filter_Data),
//output
.result (ABS_Data)
);
lf LF_module(
//input
.clk (clk_50M),
.reset_n (1'b1),
.ast_sink_data (ABS_Data[26:12]), //15bit
.ast_sink_valid (MF_Output_Valid),
.ast_source_ready (1'b1),
.ast_sink_error (2'b00),
//output
.ast_source_data (LF_Data), //31bit
.ast_sink_ready (),
.ast_source_valid (LF_Valid),
.ast_source_error ()
);
assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:14] > 18'd8091)?13'd8191:LF_Data[26:14]);
LOG_Table LOG_Table_module (
//input
.address ( Log_IN),
.clock (clk_50M ),
//output
.q (Log_OUT )
);
Test Test_module (
//input
.address (1'b0 ),
.clock (clk_50M ),
//output
.q ({Base_Noise1,Base_Noise2})
);
IMG_TRI_BUFFER IMG_TRI_BUFFER_inst (
//input
.data (LF_Reg),
.rdaddress_a ({Toggle[1:0]-2'b01,Trans_Addr}),
.rdaddress_b ({Toggle[1:0]-2'b10,Trans_Addr} ),
.rdclock (CC3200_SPI_CS ),
.wraddress ({Toggle[1:0],WR_RAM_ADDR}),
.wrclock (clk_50M ),
//output
.wren (LF_Valid & Seg_Enable ),
.qa (Trans_Data1 ),
.qb (Trans_Data2 )
);
assign Trans_Data_buf = {1'b0,Trans_Data1} + {1'b0,Trans_Data2};
assign Trans_Data = Trans_Data_buf[8:1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[500][500], st[500][500]; vector<pair<int, int> > go[500][500]; vector<vector<int> > cc; vector<int> c; int mv[1 << 20]; int it; void pr(int n, int k) { if (k == 1) { c.push_back(n); mv[(((c[4] * 16 + c[3]) * 16 + c[2]) * 16 + c[1]) * 16 + c[0]] = it; cc.push_back(c); it++; c.pop_back(); return; } for (int j = 0; j <= n; j++) { c.push_back(j); pr(n - j, k - 1); c.pop_back(); } } int kkk[5] = {1, 16, 256, 4096, 65536}; void get_int(int &ans) { ans = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) { ans = ans * 10 + c - 0 ; c = getchar(); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); pr(8, 5); queue<pair<int, int> > pp; for (int j = 0; j < cc.size(); j++) { vector<int> vv = cc[j]; int cnum = (((vv[4] * 16 + vv[3]) * 16 + vv[2]) * 16 + vv[1]) * 16 + vv[0]; bool ok = true; for (int q = 0; q < cc.size(); q++) { bool ok1 = true; for (int ii = 1; ii < 5; ii++) { if (cc[j][ii]) { ok = false; for (int jj = 1; jj < 5; jj++) { if (cc[q][jj]) { ok1 = false; cnum -= kkk[ii]; cnum += kkk[(ii + jj) % 5]; go[q][mv[cnum]].push_back(make_pair(j, q)); st[j][q]++; cnum += kkk[ii]; cnum -= kkk[(ii + jj) % 5]; } } if (ok) { ans[j][q] = 1; pp.push(make_pair(j, q)); } else if (ok1) { ans[j][q] = 2; pp.push(make_pair(j, q)); } } } } } while (!pp.empty()) { int j = pp.front().first; int q = pp.front().second; pp.pop(); for (auto v : go[j][q]) { if (ans[v.first][v.second]) continue; if (ans[j][q] == 2) { ans[v.first][v.second] = 1; pp.push(v); continue; } st[v.first][v.second]--; if (st[v.first][v.second] == 0) { ans[v.first][v.second] = 2; pp.push(v); continue; } } } int t; cin >> t; for (int i = 0; i < t; i++) { int f; cin >> f; int a = 0, b = 0; for (int j = 0; j < 8; j++) { int k; cin >> k; a += (1 << (k * 4)); } for (int j = 0; j < 8; j++) { int k; cin >> k; b += (1 << (k * 4)); } int k1 = mv[a], k2 = mv[b]; if (f == 0) { if (ans[k1][k2] == 1) cout << Alice << n ; if (ans[k1][k2] == 2) cout << Bob << n ; if (ans[k1][k2] == 0) cout << Deal << n ; } else { swap(k1, k2); if (ans[k1][k2] == 2) cout << Alice << n ; if (ans[k1][k2] == 1) cout << Bob << n ; if (ans[k1][k2] == 0) cout << Deal << n ; } } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma comment(linker, /STACK:100000000 ) const double pi = acos(-1); const int MOD = 1e9 + 7; const int INF = 1e9 + 7; const int MAXN = 5e3 + 5; const double eps = 1e-9; using namespace std; bool vis[MAXN]; int a[MAXN * 20], L[MAXN], R[MAXN], mx[MAXN]; double dp[MAXN][MAXN], P[MAXN], tmp2[MAXN]; set<int> ind; int main() { int n, q; scanf( %d , &(n)), scanf( %d , &(q)); for (int i = 0; i < n; i++) ind.insert(i); for (int i = 0; i < (n); i++) scanf( %d , &(a[i])); for (int i = 0; i < q; i++) { scanf( %d %d %lf , L + i, R + i, P + i); L[i]--, R[i]--; for (int j = 0; j < i; j++) if (R[j] - L[j] > R[i] - L[i]) swap(L[i], L[j]), swap(R[i], R[j]), swap(P[i], P[j]); } L[q] = 0, R[q] = n - 1, P[q] = 0, q++; for (int i = 0; i < q; i++) { vector<int> tmp; for (int j = 0; j < i; j++) if (L[i] <= L[j] && R[j] <= R[i] && !vis[j]) { vis[j] = 1; tmp.push_back(j); mx[i] = max(mx[i], mx[j]); } while (1) { set<int>::iterator it = ind.lower_bound(L[i]); if (it != ind.end() && *it <= R[i]) mx[i] = max(mx[i], a[*it]), ind.erase(it); else break; } for (int j = 0; j <= q; j++) tmp2[j] = 1; for (int x = 0; x < tmp.size(); x++) { int j = tmp[x]; for (int k = 0; k <= q; k++) if (mx[i] + k - mx[j] <= q) tmp2[k] *= dp[j][mx[i] + k - mx[j]]; } for (int j = q; j > 0; j--) tmp2[j] -= tmp2[j - 1]; dp[i][0] = (1 - P[i]) * tmp2[0]; for (int j = 1; j <= q; j++) dp[i][j] = dp[i][j - 1] + P[i] * tmp2[j - 1] + (1 - P[i]) * tmp2[j]; } double ans = dp[q - 1][0] * mx[q - 1]; for (int i = 1; i <= q; i++) ans += (dp[q - 1][i] - dp[q - 1][i - 1]) * (mx[q - 1] + i); printf( %.15f n , ans); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:640000000 ) using namespace std; int fx[] = {0, 0, -1, 1, -1, 1, 1, -1}; int fy[] = {1, -1, 0, 0, 1, 1, -1, -1}; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; const int N = (int)3e5; int a[N], b[N], c[N], d[N], n, b1[N], c1[N]; int bits[32][N], k[32]; bool valid() { memset(bits, 0, sizeof(bits)); for (int i = 0; i < 31; i++) { for (int j = 0; j < n; j++) { if (a[j] < 0) return false; if (a[j] & (1 << i)) bits[i][j] = 1; else bits[i][j] = 0; } } memset(k, 0, sizeof(k)); for (int i = 0; i < 31; i++) { for (int j = 0; j < n; j++) { k[i] += bits[i][j]; } } memset(b1, 0, sizeof(b1)); memset(c1, 0, sizeof(c1)); for (int i = 0; i < 31; i++) { for (int j = 0; j < n; j++) { int _b = bits[i][j] ? k[i] : 0; int _c = bits[i][j] ? n : k[i]; b1[j] += _b << i; c1[j] += _c << i; } } for (int i = 0; i < n; i++) { if (b[i] != b1[i] || c[i] != c1[i]) return false; } return true; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &b[i]); for (int i = 0; i < n; i++) scanf( %d , &c[i]); long long int sum = 0LL; for (int i = 0; i < n; i++) { d[i] = b[i] + c[i]; sum += (long long int)d[i]; } sum /= (2 * n); for (int i = 0; i < n; i++) a[i] = (d[i] - sum) / n; if (!valid()) printf( -1 n ); else { for (int i = 0; i < n; i++) printf( %d , a[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int Lower[1000000 + 1], Higher[1000000 + 1]; char Used[1000000 + 1]; long long SumNat(long long n) { long long p = n, q = n + 1; if (p % 2) q /= 2; else p /= 2; return (p) * (q); } long long PrimePi(long long n) { long long v = sqrt(n + 1e-9), p, temp, q, j, end, i, d, t; for (int i = 0; i <= 1000000; i++) Used[i] = 0; Higher[1] = n - 1; for (p = 2; p <= v; p++) { Lower[p] = p - 1; Higher[p] = (n / p) - 1; } for (p = 2; p <= v; p++) { if (Lower[p] == Lower[p - 1]) continue; temp = Lower[p - 1]; q = p * p; Higher[1] -= Higher[p] - temp; j = 1 + (p & 1); end = (v <= n / q) ? v : n / q; for (i = p + j; i <= 1 + end; i += j) { if (Used[i]) continue; d = i * p; if (d <= v) Higher[i] -= Higher[d] - temp; else { t = n / d; Higher[i] -= Lower[t] - temp; } } if (q <= v) for (i = q; i <= end; i += p * j) Used[i] = 1; for (i = v; i >= q; i--) { t = i / p; Lower[i] -= Lower[t] - temp; } } return Higher[1]; } bool prime[10000000 + 1]; long long piii[10000000 + 1]; long long Prim(long long n) { if (n <= 10000000) return piii[n]; return PrimePi(n); } int main() { long long n, i, j; long long answer; for (i = 2; i * i <= 10000000; i++) if (!prime[i]) for (j = i * i; j <= 10000000; j += i) prime[j] = true; for (i = 2; i <= 10000000; i++) { piii[i] = piii[i - 1]; if (!prime[i]) piii[i]++; } cin >> n; for (i = 1;; i++) { if (i * i * i > n) break; } answer = Prim(i - 1); for (i = 2; i < (n / i); i++) if (!prime[i]) answer += (Prim(n / i) - Prim(i)); cout << answer; return 0; } |
#include <bits/stdc++.h> int main() { int n, i, m; char a[205]; scanf( %s , a); n = strlen(a); for (i = 0; i < n; i++) { if (a[i] == W ) { if (a[i + 1] == U ) { if (a[i + 2] == B ) { a[i] = ; a[i + 1] = ; a[i + 2] = ; } } } printf( %c , a[i]); } return 0; } |
`include "cpu_data.v"
module Cpu(clk, reset, data_bus, address_bus, r, w, interrupts, halt);
input clk /*verilator clocker*/;
wire inv_clk; assign inv_clk = !clk;
input reset;
input [7:0] interrupts;
inout [15:0] data_bus;
output reg [15:0] address_bus;
output reg r; output w; reg _w;
output reg halt;
parameter [3:0]
CYCLE_0 = 0,
CYCLE_1 = 1,
CYCLE_2 = 2,
CYCLE_3 = 3,
CYCLE_4 = 4,
CYCLE_5 = 5;
reg [3:0] cycle /*verilator public*/;
reg [15:0] pc_register, sp_register, data_register, tmp_register;
assign data_bus = _w? data_register : 16'bz;
assign w = _w & !clk;
reg [15:0] word;
wire [7:0] val, decoder_flags;
wire [3:0] operator;
wire [3:0] operator_group;
wire [2:0] num_rg1, num_rg2;
wire [9:0] relative_addr;
Decoder decoder(
.word(word),
.operator_group(operator_group),
.operator(operator),
.val(val),
.flags(decoder_flags),
.rg1(num_rg1),
.rg2(num_rg2),
.relative_addr(relative_addr));
reg [7:0] flags;
wire is_checked;
CheckBranch check_branch(
.operator(operator),
.flags(flags),
.is_checked(is_checked)
);
wire [15:0] int_address;
reg clr_int, support_int;
wire cauch_int, cauch_int_now;
assign cauch_int_now = cauch_int && flags[4];
IntAddrs module_int_addrs(
.clk(clk),
.reset(reset),
.ints(interrupts),
.int_address(int_address),
.cauch_int(cauch_int),
.clr_int(clr_int)
);
reg [1:0] cs_write_registers;
reg [15:0] register_in;
wire [15:0] register_out [0:1];
Registers registers(
.clk(clk),
.num1(num_rg1[2:1]),
.num2(num_rg2[2:1]),
.write(cs_write_registers),
.bus_in(register_in),
.bus_out1(register_out[0]),
.bus_out2(register_out[1])
);
wire [15:0] alu_out;
wire [3:0] alu_flags, alu_flags8;
wire old_carry; assign old_carry = flags[3];
reg [15:0] alu_in [0:1];
Alu alu(
.single(operator_group == `GROUP_CRSMATH || operator_group == `GROUP_WRSMATH),
.value1(alu_in[0]),
.value2(alu_in[1]),
.operator(operator),
.bus_out(alu_out),
.alu_flags(alu_flags),
.alu_flags8(alu_flags8),
.old_carry(old_carry));
initial begin
halt = 0;
cycle = CYCLE_0;
pc_register = 16'h0000;
sp_register = 16'h07FF;
end
always @ (posedge clk or posedge reset)
if (reset)
cycle <= CYCLE_0;
else case(cycle)
CYCLE_0: cycle <= support_int ? CYCLE_4 : CYCLE_1;
CYCLE_1: cycle <= CYCLE_2;
CYCLE_2: cycle <= CYCLE_3;
CYCLE_3: cycle <= (operator_group == `GROUP_SPECIAL_LONG && operator == `OP_CALL) ? CYCLE_4 : CYCLE_0;
CYCLE_4: cycle <= CYCLE_5;
CYCLE_5: cycle <= CYCLE_0;
default: cycle <= CYCLE_0;
endcase
always @ (cycle or operator_group or operator)
casez({cycle, operator_group})
{CYCLE_1, 4'b????}: r = 1'b1;
{CYCLE_3, `GROUP_WRRMATH_MEM}: r = !operator[2];
{CYCLE_3, `GROUP_WRSMATH_STACK}: r = operator == `OP_POP;
{CYCLE_3, `GROUP_SPECIAL}: r = operator == `OP_RET || operator == `OP_RETI;
{CYCLE_3, `GROUP_SPECIAL_LONG}: r = operator == `OP_CALL || operator == `OP_CALLI;
default: r = 1'b0;
endcase
always @ (cycle or operator_group or operator)
casez({cycle, operator_group})
{CYCLE_3, `GROUP_WRRMATH_MEM}: _w = operator[2];
{CYCLE_3, `GROUP_WRSMATH_STACK}: _w = operator == `OP_PUSH;
{CYCLE_5, `GROUP_SPECIAL_LONG}: _w = operator == `OP_CALL || operator == `OP_CALLI;
default: _w = 1'b0;
endcase
task cycle_0_support; begin
address_bus <= pc_register;
clr_int <= 0;
if (cauch_int_now) begin
support_int <= 1;
flags[4] <= 0;
tmp_register <= int_address;
word <= 16'b1100000000011011; // CALL OP
end else
support_int <= 0;
end; endtask
always @ (negedge clk)
if (reset) begin
address_bus <= 16'h0000;
pc_register <= 16'h0000;
sp_register <= 16'h07FF;
cs_write_registers <= 2'b00;
flags <= 8'h0;
support_int <= 0;
clr_int <= 0;
end else casez ({cycle, operator_group})
{CYCLE_0, `GROUP_WRRMATH_MEM}: begin
if (operator[1]) begin
cs_write_registers <= 2'b10;
register_in <= register_out[1] + 1;
end else if (operator[1]) begin
cs_write_registers <= 2'b10;
register_in <= register_out[1] - 1;
end else
cs_write_registers <= 2'b00;
cycle_0_support();
end
{CYCLE_0, 4'b????}: begin
cs_write_registers <= 2'b00;
cycle_0_support();
end
{CYCLE_1, 4'b????}: begin
cs_write_registers <= 2'b00;
pc_register <= pc_register + 1;
word <= data_bus;
end
{CYCLE_2, `GROUP_RJMP}: begin
if (is_checked)
pc_register <= (
pc_register
+ {{7{relative_addr[9]}}, relative_addr[8:0]}
- 1
);
end
{CYCLE_2, `GROUP_SFLAG}: begin
flags <= flags | decoder_flags;
end
{CYCLE_2, `GROUP_UFLAG}: begin
flags <= flags & ~decoder_flags;
end
{CYCLE_2, `GROUP_WRRMATH}: begin
alu_in[0] <= register_out[0];
alu_in[1] <= register_out[1];
end
{CYCLE_2, `GROUP_WRSMATH}: begin
alu_in[0] <= register_out[0];
alu_in[1] <= 16'h0000;
end
{CYCLE_3, `GROUP_WRRMATH}, {CYCLE_3, `GROUP_WRSMATH}: begin
if (operator != `OP_CMP) begin
register_in <= alu_out;
cs_write_registers <= 2'b01;
end
flags[3:0] <= alu_flags;
end
{CYCLE_2, `GROUP_CRVMATH}, {CYCLE_2, `GROUP_CRSMATH}: begin
alu_in[0] <= {8'h00, num_rg1[0] ? register_out[0][15:8] : register_out[0][7:0]};
alu_in[1] <= {{8{val[7]}}, val}; // for single this code is not affected
end
{CYCLE_2, `GROUP_CRRMATH}: begin
alu_in[0] <= {8'h00, num_rg1[0] ? register_out[0][15:8] : register_out[0][7:0]};
alu_in[1] <= {8'h00, num_rg2[0] ? register_out[1][15:8] : register_out[1][7:0]};
end
{CYCLE_3, `GROUP_CRRMATH}, {CYCLE_3, `GROUP_CRSMATH}, {CYCLE_3, `GROUP_CRVMATH}: begin
if (operator != `OP_CMP) begin
register_in <= (
num_rg1[0]
? {alu_out[7:0], register_out[0][7:0]}
: {register_out[0][15:8], alu_out[7:0]}
);
cs_write_registers <= 2'b01;
end
flags[3:0] <= alu_flags8;
end
{CYCLE_2, `GROUP_WRRMATH_MEM}: begin
if (operator[2])
data_register <= register_out[0];
address_bus <= register_out[1];
end
{CYCLE_2, `GROUP_WRSMATH}: begin
alu_in[0] <= register_out[0];
end
{CYCLE_3, `GROUP_WRRMATH_MEM}: begin
if (!operator[2]) begin
register_in <= data_bus;
cs_write_registers <= 2'b01;
end
end
{CYCLE_2, `GROUP_WRSMATH_STACK}: begin
case (operator)
`OP_PUSH: begin
data_register <= register_out[0];
sp_register <= sp_register - 1;
address_bus <= sp_register;
end
`OP_POP: begin
sp_register <= sp_register + 1;
address_bus <= sp_register + 1;
end
endcase
end
{CYCLE_3, `GROUP_WRSMATH_STACK}: begin
case (operator)
`OP_POP: begin
register_in <= data_bus;
end
endcase
end
{CYCLE_2, `GROUP_SPECIAL_LONG}: begin
address_bus <= pc_register;
end
{CYCLE_3, `GROUP_SPECIAL_LONG}: begin
case (operator)
`OP_JMP: begin
pc_register <= data_bus;
end
`OP_CALL, `OP_CALLI: begin
tmp_register <= data_bus;
end
endcase
end
{CYCLE_4, `GROUP_SPECIAL_LONG}: begin
case (operator)
`OP_CALL, `OP_CALLI: begin
data_register <= pc_register;
sp_register <= sp_register - 1;
address_bus <= sp_register;
end
endcase
end
{CYCLE_5, `GROUP_SPECIAL_LONG}: begin
case (operator)
`OP_CALL: begin
pc_register <= tmp_register;
end
`OP_CALLI: begin
pc_register <= tmp_register;
clr_int <= 1;
end
endcase
end
{CYCLE_2, `GROUP_SPECIAL}: begin
case (operator)
`OP_RET, `OP_RETI: begin
sp_register <= sp_register + 1;
address_bus <= sp_register + 1;
end
endcase
end
{CYCLE_3, `GROUP_SPECIAL}: begin
case (operator)
`OP_RET: begin
pc_register <= data_bus;
end
`OP_RETI: begin
pc_register <= data_bus;
flags[4] <= 1; // restore intterups
end
endcase
end
endcase
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
#include <bits/stdc++.h> int main(int argc, const char* argv[]) { int n, k; int a[100000 + 1]; scanf( %d%d , &n, &k); int i; int count = 0; int is_ukn = scanf( %d , a) != 1; for (i = !is_ukn; i <= n; i++) scanf( %d , a + i) != 1 && getchar() && count++; int is_man_move = (n + 1 - count) & 1; int is_man_end = n & 1; if (k == 0) { puts((is_ukn && is_man_move) || (!is_ukn && a[0] == 0) ? Yes : No ); return 0; } int some_ukn = is_ukn || count; if (some_ukn) { puts(is_man_end ? Yes : No ); return 0; } int sum2 = 0; for (i = 0; i <= n && sum2 % k == 0; i++) { sum2 /= k; sum2 += a[i]; } if (i == n + 1) { if (k != 1 && k != -1) while (sum2 != 0 && sum2 % k == 0) sum2 /= k; if (sum2 == 0) { puts( Yes ); return 0; } } puts( No ); return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
module add_compare_select (npm, d, pm1, bm1, pm2, bm2);
/**
* WARNING TO DEVELOPER(S)!!!
*
* CHECK/VERIFY THAT THE WIDTH OF ALL THE PATH METRIC BUSES
* ARE THE SAME
*
* SUCH BUSES INCLUDE npm, pm1, pm2, add1, and add2
*
* THE FOLLOWING BUSES ARE NOT INCLUDED: bm1, bm2, add_temp1,
* and add_temp2
*
* NOTE THAT THE WIDTHS OF add_temp1 AND add_temp2 ARE ONE GREATER
* THAN THOSE OF THE PATH METRIC BUSES
*/
// Output signals for the design module
/**
* New path metric - It keeps growing, so reasonable number
* of bits have to be chosen so that npm is unlikely to overflow
* Number of bits chosen = 4
*
* To handle overflows, I have decided to saturate the result
* of the computation at 2^n - 1 = 2^4 - 1 = 15
*/
output [3:0] npm;
// Decision bit from the add-compare-select unit
output d;
// Input signals for the design module
// Current path metric #1 for a set of addition
input [3:0] pm1;
// Branch metric #1 for a set of addition
input [1:0] bm1;
// Current path metric #2 for another set of addition
input [3:0] pm2;
// Branch metric #2 for another set of addition
input [1:0] bm2;
// Declare "reg" signals... that will be assigned values
reg [3:0] npm;
reg d;
/**
* Result of the additions in the first stage of the
* add-compare-select unit
*/
// Result of a set of addition
reg [3:0] add1;
// Result of another set of addition
reg [3:0] add2;
// Temporary storage for a set of addition to check for overflow
reg [4:0] add_temp1;
// Temporary storage for another set of addition to check for overflow
reg [4:0] add_temp2;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Maximum value that can be stored in a 4-bit bus
parameter max_add = 4'd15;
/**
* Perform the addition stage of the add-compare-select unit
* Result of a set of addition
*/
always @ (pm1 or bm1)
begin
// Add the operands and temporary store them
add_temp1 = pm1 + bm1;
// Did the (temporary) addition cause an overflow
if(add_temp1 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add1 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add1 = pm1 + bm1;
end
end
/**
* Perform the addition stage of the add-compare-select unit
* Result of another set of addition
*/
always @ (pm2 or bm2)
begin
// Add the operands and temporary store them
add_temp2 = pm2 + bm2;
// Did the (temporary) addition cause an overflow
if(add_temp2 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add2 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add2 = pm2 + bm2;
end
end
// ========================================================
// Perform the compare stage of the add-compare-select unit
always @ (add1 or add2)
begin
if(add1 <= add2)
begin
// Select path 1 ==> d=0
d = 1'b0;
end
else
begin
// Select path 2 ==> d=1
d = 1'b1;
end
end
// ========================================================
// Perform the select stage of the add-compare-select unit
always @ (d or add1 or add2)
begin
if(d)
begin
// Select path 2... add1 < add2
npm = add2;
end
else
begin
// Select path 1... add1 >= add2
npm = add1;
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable right shift in always
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
reg [7:0] value;
always @(var1 or var2)
value = var1 >> var2;
initial
begin
error = 0;
#1 ;
var1 = 8'h80;
var2 = 8'h7;
#1;
if(value !== 8'h1)
begin
error = 1;
$display ("FAILED - 80 >> 7 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h6;
#1;
if(value !== 8'h2)
begin
error = 1;
$display ("FAILED - 80 >> 6 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h5;
#1;
if(value !== 8'h4)
begin
error = 1;
$display ("FAILED - 80 >> 5 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h4;
#1;
if(value !== 8'h8)
begin
error = 1;
$display ("FAILED - 80 >> 4 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h3;
#1;
if(value !== 8'h10)
begin
error = 1;
$display ("FAILED - 80 >> 3 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h2;
#1;
if(value !== 8'h20)
begin
error = 1;
$display ("FAILED - 80 >> 2 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h1;
#1;
if(value !== 8'h40)
begin
error = 1;
$display ("FAILED - 80 >> 1 is %h",value);
end
#1 ;
var1 = 8'h80;
var2 = 8'h0;
#1;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - 80 >> 0 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h7;
#1;
if(value !== 8'h01)
begin
error = 1;
$display ("FAILED - a5 >> 7 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h1;
#1;
if(value !== 8'h52)
begin
error = 1;
$display ("FAILED - aa >> 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long int M = 1e9 + 7; long long int cdiv(long long int a, long long int b) { return (a % b == 0) ? a / b : a / b + 1; } long long int myMod(long long int a, long long int b) { long long int r = a % b; return r < 0 ? r + b : r; } long long int ModPow(long long int a, long long int b, long long int M) { if (M == 1) return 0; a %= M; long long int ans = 1, t = 1; while (t > 0 && t <= b) { if (t & b) { ans *= a; ans %= M; } t <<= 1; a *= a; a %= M; } return ans; } struct seg { long long int l, r, u, d; }; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n; cin >> n; seg a[n]; for (long long int i = 0; i < n; i++) cin >> a[i].l >> a[i].d >> a[i].r >> a[i].u; long long int mxll[n], mxlr[n], mnrl[n], mnrr[n]; mxll[0] = a[0].l, mxlr[n - 1] = a[n - 1].l, mnrl[0] = a[0].r, mnrr[n - 1] = a[n - 1].r; for (long long int i = 1; i < n; i++) { mxll[i] = max(mxll[i - 1], a[i].l); mnrl[i] = min(mnrl[i - 1], a[i].r); } for (long long int i = n - 1 - 1; i >= 0; i--) { mxlr[i] = max(mxlr[i + 1], a[i].l); mnrr[i] = min(mnrr[i + 1], a[i].r); } long long int mxdl[n], mxdr[n], mnul[n], mnur[n]; mxdl[0] = a[0].d, mxdr[n - 1] = a[n - 1].d, mnul[0] = a[0].u, mnur[n - 1] = a[n - 1].u; for (long long int i = 1; i < n; i++) { mxdl[i] = max(mxdl[i - 1], a[i].d); mnul[i] = min(mnul[i - 1], a[i].u); } for (long long int i = n - 1 - 1; i >= 0; i--) { mxdr[i] = max(mxdr[i + 1], a[i].d); mnur[i] = min(mnur[i + 1], a[i].u); } if (mnrr[1] - mxlr[1] >= 0 && mnur[1] - mxdr[1] >= 0) { cout << mxlr[1] << << mxdr[1] << n ; return 0; } for (long long int i = 1; i < n - 1; i++) { long long int cix = min(mnrl[i - 1], mnrr[i + 1]) - max(mxll[i - 1], mxlr[i + 1]); long long int ciy = min(mnul[i - 1], mnur[i + 1]) - max(mxdl[i - 1], mxdr[i + 1]); if (cix >= 0 && ciy >= 0) { cout << max(mxll[i - 1], mxlr[i + 1]) << << max(mxdl[i - 1], mxdr[i + 1]); return 0; } } if (mnrl[n - 2] - mxll[n - 2] >= 0 && mnul[n - 2] - mxdl[n - 2] >= 0) { cout << mxll[n - 2] << << mxdl[n - 2] << n ; return 0; } return 0; } |
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build Wed Nov 18 09:43:45 MST 2015
//Date : Tue Feb 02 21:37:26 2016
//Host : running 64-bit Service Pack 1 (build 7601)
//Command : generate_target zc702_wrapper.bd
//Design : zc702_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zc702_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
zc702 zc702_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
#include <bits/stdc++.h> using namespace std; void r(int b, int p, int f, int h, int c); int main() { int b, p, f, h, c, t; cin >> t; while (t--) { cin >> b >> p >> f >> h >> c; r(b, p, f, h, c); } } void r(int b, int p, int f, int h, int c) { int i, j, k, t = 0; i = b / 2; if (i == 0) { cout << 0 << endl; } else { if (i >= (p + f)) { t = (p * h) + (c * f); cout << t << endl; } else { if (h >= c) { if (p >= i) { t = (i * h); cout << t << endl; } else { t = (h * p); i = i - p; t = t + (i * c); cout << t << endl; } } else { if (f >= i) { t = (i * c); cout << t << endl; } else { t = (c * f); i = i - f; t = t + (i * h); cout << t << endl; } } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void no() { cout << NO << endl; } void yes() { cout << YES << endl; } int main() { int q, n, wyn; cin >> q; for (int i = 0; i < q; i++) { cin >> n; char a; string s; cin >> a; cin >> s; if (s.length() == 1 && a >= s[0]) no(); else { yes(); cout << 2 << endl; cout << a << n << s << endl; } } } |
#include <bits/stdc++.h> using namespace std; map<int, bool> mp; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int a; cin >> a; mp[a] = 1; } for (int i = 0; i < 1010; i++) { if (mp[i] && mp[i + 1] && mp[i + 2]) { cout << YES << endl; return 0; } } cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string a, b; cin >> a >> b; vector<int> ans; int l = 0, r = n - 1; for (int i = 0; i < n; i++) { if (!(i & 1)) { if (a[l] == b[n - i - 1]) ans.push_back(1); ans.push_back(max(l, r) - min(l, r) + 1); } else { if (a[l] != b[n - i - 1]) ans.push_back(1); ans.push_back(max(l, r) - min(l, r) + 1); } swap(l, r); if (r > l) r--; else r++; } cout << ans.size() << ; for (auto x : ans) cout << x << ; cout << n ; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; vector<vector<int>> adj; vector<vector<int>> vis; int dfs1(int a, int b) { if (a == n - 1 and b == m - 1) return 1; vis[a][b] = 1; if (a + 1 < n and adj[a + 1][b] and !vis[a + 1][b]) if (dfs1(a + 1, b)) return 1; if (b + 1 < m and adj[a][b + 1] and !vis[a][b + 1]) if (dfs1(a, b + 1)) return 1; vis[a][b] = 2; return 0; } int dfs2(int a, int b) { if (a == n - 1 and b == m - 1) return 1; vis[a][b] = 1; if (a + 1 < n and adj[a + 1][b] and vis[a + 1][b] != 1) if (dfs2(a + 1, b)) return 1; if (b + 1 < m and adj[a][b + 1] and vis[a][b + 1] != 1) if (dfs2(a, b + 1)) return 1; return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; adj = vector<vector<int>>(n, vector<int>(m)); for (int i = 0; i < n; ++i) { string s; cin >> s; for (int j = 0; j < m; ++j) { if (s[j] == . ) adj[i][j] = 1; else adj[i][j] = 0; } } int a = 0; vis = vector<vector<int>>(n, vector<int>(m, 0)); a += dfs1(0, 0); a += dfs2(0, 0); cout << a << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int nCase; scanf( %d , &nCase); while (nCase--) { int a, b; scanf( %d%d , &a, &b); if (a == 0) { if (b == 0) printf( 1 n ); else printf( 0.5 n ); continue; } if (b == 0) { printf( 1 n ); continue; } b *= 4; if (a >= b) printf( %.6f n , (0.5 * (a - b + a) * b + 1.0 * a * b) / (2.0 * b * a)); else printf( %.6f n , (1.0 * a * b + 0.5 * a * a) / (2.0 * b * a)); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: div
// File: div.v
// Author: Lei Silei
// E-mail:
// Description: ³ý·¨Ä£¿é
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module div(
input wire clk,
input wire rst,
input wire signed_div_i,
input wire[31:0] opdata1_i,
input wire[31:0] opdata2_i,
input wire start_i,
input wire annul_i,
output reg[63:0] result_o,
output reg ready_o
);
wire[32:0] div_temp;
reg[5:0] cnt;
reg[64:0] dividend;
reg[1:0] state;
reg[31:0] divisor;
reg[31:0] temp_op1;
reg[31:0] temp_op2;
assign div_temp = {1'b0,dividend[63:32]} - {1'b0,divisor};
always @ (posedge clk) begin
if (rst == `RstEnable) begin
state <= `DivFree;
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end else begin
case (state)
`DivFree: begin //DivFree״̬
if(start_i == `DivStart && annul_i == 1'b0) begin
if(opdata2_i == `ZeroWord) begin
state <= `DivByZero;
end else begin
state <= `DivOn;
cnt <= 6'b000000;
if(signed_div_i == 1'b1 && opdata1_i[31] == 1'b1 ) begin
temp_op1 = ~opdata1_i + 1;
end else begin
temp_op1 = opdata1_i;
end
if(signed_div_i == 1'b1 && opdata2_i[31] == 1'b1 ) begin
temp_op2 = ~opdata2_i + 1;
end else begin
temp_op2 = opdata2_i;
end
dividend <= {`ZeroWord,`ZeroWord};
dividend[32:1] <= temp_op1;
divisor <= temp_op2;
end
end else begin
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end
end
`DivByZero: begin //DivByZero״̬
dividend <= {`ZeroWord,`ZeroWord};
state <= `DivEnd;
end
`DivOn: begin //DivOn״̬
if(annul_i == 1'b0) begin
if(cnt != 6'b100000) begin
if(div_temp[32] == 1'b1) begin
dividend <= {dividend[63:0] , 1'b0};
end else begin
dividend <= {div_temp[31:0] , dividend[31:0] , 1'b1};
end
cnt <= cnt + 1;
end else begin
if((signed_div_i == 1'b1) && ((opdata1_i[31] ^ opdata2_i[31]) == 1'b1)) begin
dividend[31:0] <= (~dividend[31:0] + 1);
end
if((signed_div_i == 1'b1) && ((opdata1_i[31] ^ dividend[64]) == 1'b1)) begin
dividend[64:33] <= (~dividend[64:33] + 1);
end
state <= `DivEnd;
cnt <= 6'b000000;
end
end else begin
state <= `DivFree;
end
end
`DivEnd: begin //DivEnd״̬
result_o <= {dividend[64:33], dividend[31:0]};
ready_o <= `DivResultReady;
if(start_i == `DivStop) begin
state <= `DivFree;
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end
end
endcase
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; struct vec { int to; int fro; }; int fa[200010], son[200010][26], mx[200010]; int rt, lst, tot; int n, m; char s[200010]; vec mp[200010]; int tai[200010], cnt; int P[200010]; int ans[200010]; vector<int> qs[200010]; int av[200010]; int len[200010]; int Rt[200010], Son[4000010][2]; int TOT; inline void be(int x, int y) { mp[++cnt].to = y; mp[cnt].fro = tai[x]; tai[x] = cnt; } int merge(int x, int y) { if (!x || !y) { return x + y; } Son[x][0] = merge(Son[x][0], Son[y][0]); Son[x][1] = merge(Son[x][1], Son[y][1]); return x; } void change(int &x, int y, int z, int p) { if (!x) { x = ++TOT; } if (y == z) { return; } int mid = y + z >> 1; if (p <= mid) { change(Son[x][0], y, mid, p); } else { change(Son[x][1], mid + 1, z, p); } } void ins(int x) { int np = ++tot, p = lst; mx[np] = mx[p] + 1; while (p && !son[p][x]) { son[p][x] = np; p = fa[p]; } if (!p) { fa[np] = rt; } else { int q = son[p][x]; if (mx[q] == mx[p] + 1) { fa[np] = q; } else { int nq = ++tot; mx[nq] = mx[p] + 1; memcpy(son[nq], son[q], sizeof(son[q])); fa[nq] = fa[q]; fa[np] = fa[q] = nq; while (p && son[p][x] == q) { son[p][x] = nq; p = fa[p]; } } } lst = np; } int L; int t[200010]; void DFS(int x, int y, int z) { if (y == z) { t[++L] = y; return; } int mid = y + z >> 1; if (Son[x][0]) { DFS(Son[x][0], y, mid); } if (Son[x][1]) { DFS(Son[x][1], mid + 1, z); } } void dfs(int x) { int i, y; for (i = tai[x]; i; i = mp[i].fro) { y = mp[i].to; dfs(y); } for (i = tai[x]; i; i = mp[i].fro) { y = mp[i].to; Rt[x] = merge(Rt[x], Rt[y]); } L = 0; if (qs[x].size()) { L = 0; DFS(Rt[x], 1, n); for (i = 0; i < qs[x].size(); i++) { int wzh = 1; int ti = qs[x][i]; int tav = av[qs[x][i]]; if (L < tav) { ans[ti] = -1; } else { ans[ti] = 1000000000; for (int j = tav; j <= L; j++) { ans[ti] = min(ans[ti], t[j] - t[j - tav + 1] + len[ti]); } } } } } int main() { int i, x; lst = rt = tot = 1; scanf( %s , s + 1); n = strlen(s + 1); int p = rt; for (i = 1; i <= n; i++) { ins(s[i] - a ); p = son[p][s[i] - a ]; P[i] = p; change(Rt[p], 1, n, i); } for (i = 2; i <= tot; i++) { be(fa[i], i); } scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d%s , &av[i], s + 1); int p = rt; for (int j = 1; s[j]; j++) { p = son[p][s[j] - a ]; } len[i] = strlen(s + 1); if (!p) { ans[i] = -1; } else { qs[p].push_back(i); } } dfs(1); for (i = 1; i <= m; i++) { printf( %d n , ans[i]); } return 0; } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* I2S TX
*/
module i2s_tx #
(
parameter WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_l_tdata,
input wire [WIDTH-1:0] input_r_tdata,
input wire input_tvalid,
output wire input_tready,
/*
* I2S interface
*/
input wire sck,
input wire ws,
output wire sd
);
reg [WIDTH-1:0] l_data_reg = 0;
reg [WIDTH-1:0] r_data_reg = 0;
reg l_data_valid_reg = 0;
reg r_data_valid_reg = 0;
reg [WIDTH-1:0] sreg = 0;
reg [$clog2(WIDTH+1)-1:0] bit_cnt = 0;
reg last_sck = 0;
reg last_ws = 0;
reg sd_reg = 0;
assign input_tready = ~l_data_valid_reg & ~r_data_valid_reg;
assign sd = sd_reg;
always @(posedge clk) begin
if (rst) begin
l_data_reg <= 0;
r_data_reg <= 0;
l_data_valid_reg <= 0;
r_data_valid_reg <= 0;
sreg <= 0;
bit_cnt <= 0;
last_sck <= 0;
last_ws <= 0;
sd_reg <= 0;
end else begin
if (input_tready & input_tvalid) begin
l_data_reg <= input_l_tdata;
r_data_reg <= input_r_tdata;
l_data_valid_reg <= 1;
r_data_valid_reg <= 1;
end
last_sck <= sck;
if (~last_sck & sck) begin
// rising edge sck
last_ws <= ws;
if (last_ws != ws) begin
bit_cnt <= WIDTH;
if (ws) begin
sreg <= r_data_reg;
r_data_valid_reg <= 0;
end else begin
sreg <= l_data_reg;
l_data_valid_reg <= 0;
end
end
end
if (last_sck & ~sck) begin
// falling edge sck
if (bit_cnt > 0) begin
bit_cnt <= bit_cnt - 1;
{sd_reg, sreg} <= {sreg[WIDTH-1:0], 1'b0};
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k, p, total = 0; cin >> n; k = (n - 11) / 2; for (int i = 1; i <= n; i++) { char temp; cin >> temp; if (temp == 8 ) { total++; if (total == k + 1) p = i; } } if (total <= k) cout << NO ; else { p -= k; if ((p - 1) <= k) cout << YES ; else cout << NO ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
/**
* lsbufiso1p: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_BEHAVIORAL_V |
module psdos (
input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
reg [1:0] k;
reg init;
reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
k=0;
DoIt=1;
//NoDoIt=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
DONE=0;
Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
if(DoIt)
begin
k<=k+1;
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(((j%2)&&(regis[8]))||(!(j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long double n; cin >> n; long long m = sqrt(n); if (m * m == n) { cout << 2 * m; } else if ((long long)m * (long long)(m + 1) >= n) { cout << (long long)m + (long long)(m + 1); } else cout << (long long)2 * (long long)(m + 1); } |
#include <bits/stdc++.h> using namespace std; const long double PI = atan(1.0) * 4.0; const long long int MOD = 1e9 + 7; const long long int INF = 1e18; const long double EPS = 0.0000001; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; map<char, int> a; for (int i = 0; i < n; i++) a[s[i]]++; int j = 97; while (k != 0 && j <= 122) { for (int i = 0; i < n; i++) { if (s[i] == char(j)) { s[i] = * ; k--; if (k == 0) break; } } j++; } for (int i = 0; i < n; i++) { if (s[i] != * ) cout << s[i]; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 2e5 + 1; vector<long long int> a[N]; vector<long long int> order, pos(N); bool topsort(long long int n) { order.clear(); queue<long long int> q; vector<long long int> indeg(n + 1, 0); for (long long int i = 1; i <= n; i++) for (auto &it : a[i]) indeg[it]++; for (long long int i = 1; i <= n; i++) if (!indeg[i]) q.push(i); long long int idx = 0; while (!q.empty()) { int v = q.front(); q.pop(); order.push_back(v); idx++; pos[v] = idx; for (auto &u : a[v]) { indeg[u]--; if (!indeg[u]) q.push(u); } } return (order.size() == n); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; vector<long long int> a1(n + 1), b(n + 1), c; for (long long int i = 1; i <= n; i++) cin >> a1[i]; for (long long int i = 1; i <= n; i++) { cin >> b[i]; if (b[i] != -1) a[i].push_back(b[i]); } topsort(n); vector<long long int> ans, tmp; long long int sum1 = 0, k = 0; for (long long int i = 0; i < order.size(); i++) { long long int pos = order[i]; sum1 += a1[pos]; if (b[pos] != -1 && a1[pos] < 0) tmp.push_back(pos); else { if (b[pos] != -1) a1[b[pos]] += a1[pos]; ans.push_back(pos); } } reverse(tmp.begin(), tmp.end()); for (long long int i = 0; i < tmp.size(); i++) ans.push_back(tmp[i]); cout << sum1 << n ; for (long long int i = 0; i < n; i++) cout << ans[i] << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4BB_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long long int INF = 9e18 + 2e17; const int inf = 2e9; const int N = 1e5 + 22; const double eps = 1e-10; bool cmp(pair<int, int> A, pair<int, int> B) { if (A.first != B.first) return A.first < B.first; return A.second > B.second; } void _solve() { int n, m; cin >> n >> m; pair<int, int> sr[n]; for (int i = (int)0; i < (int)n; i++) cin >> sr[i].first >> sr[i].second; sort(sr, sr + n, cmp); int c = 0; for (int i = 0; i < n;) { int x = sr[i].first; while (i < n && x == sr[i].first) i++; c++; } vector<vector<int> > row_sum(c); vector<int> tot_sum; int p = 0; for (int i = 0; i < n;) { int x = sr[i].first, sum = 0; while (i < n && x == sr[i].first) { sum += sr[i].second; i++; if (sum <= 0) continue; row_sum[p].push_back(sum); } if (!row_sum[p].empty()) p++; } pair<int, int> row_sz[p]; for (int i = (int)0; i < (int)p; i++) row_sz[i] = {row_sum[i].size(), i}; sort(row_sz, row_sz + p); for (int y = 0, i = 0; y < p;) { int x = row_sz[y].first; while (i < x) { int sum = 0; for (int j = (int)y; j < (int)p; j++) sum += row_sum[row_sz[j].second][i]; tot_sum.push_back(sum); i++; } while (x == row_sz[y].first) y++; } int ans = 0; for (int i = (int)0; i < (int)tot_sum.size(); i++) ans = max(ans, tot_sum[i]); cout << ans; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); _solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int count0(0), count5(0); for (int i = 1; i <= n; i++) { int a; cin >> a; if (a == 0) count0++; if (a == 5) count5++; } if (count0 == 0) cout << -1; else if (count5 < 9) cout << 0; else { for (int i = 0; i < floor(count5 / 9); i++) { cout << 555555555; } for (int i = 0; i < count0; i++) cout << 0; } } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_data_clk #(
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0) (
input rst,
output locked,
input clk_in_p,
input clk_in_n,
output clk);
localparam VIRTEX7 = 0;
localparam ULTRASCALE_PLUS = 2;
localparam ULTRASCALE = 3;
// internal signals
wire clk_ibuf_s;
// defaults
assign locked = 1'b1;
// instantiations
generate
if (SINGLE_ENDED == 1) begin
IBUFG i_rx_clk_ibuf (
.I (clk_in_p),
.O (clk_ibuf_s));
end else begin
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
end
endgenerate
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353, N = 200200, G = 3, Gi = 332748118; long long power(long long base, long long b) { long long ret = 1; while (b) { if (b & 1) ret = ret * base % mod; base = base * base % mod; b >>= 1; } return ret; } int limit, len, last = -1, pos[N]; long long G0[N], G1[N], G2[N], g[N], F0[N], F1[N], F2[N]; long long w[N]; void getlen(int n) { limit = 1, len = 0; while (limit < n) limit <<= 1, ++len; w[0] = 1; long long gg = power(G, (mod - 1) / limit); for (int i = 1; i < limit; ++i) { pos[i] = (pos[i >> 1] >> 1) | ((i & 1) << (len - 1)); w[i] = w[i - 1] * gg % mod; } } void ntt(long long *a, int n, int type) { for (int i = 0; i < limit; ++i) if (i < pos[i]) swap(a[i], a[pos[i]]); for (int mid = 1; mid < limit; mid <<= 1) for (int j = 0, r = mid << 1; j < limit; j += r) for (int k = 0; k < mid; ++k) { long long x = a[j + k], y = w[limit / r * k] * a[j + mid + k] % mod; a[j + k] = (x + y) % mod; a[j + mid + k] = (x - y + mod) % mod; } if (type == -1) { reverse(a + 1, a + limit); long long inv = power(limit, mod - 2); for (int i = 0; i < limit; ++i) a[i] = inv * a[i] % mod; } } long long f[N], h[N], tmp[N]; void calc(long long *a, int n, long long *b, int m, long long *c, int nm = -1) { if (nm == -1) nm = n + m - 1; getlen(nm); for (int i = 0; i < n; ++i) f[i] = a[i]; for (int i = n; i < limit; ++i) f[i] = 0; for (int i = 0; i < m; ++i) h[i] = b[i]; for (int i = m; i < limit; ++i) h[i] = 0; ntt(f, nm, 1), ntt(h, nm, 1); for (int i = 0; i < limit; ++i) f[i] = f[i] * h[i] % mod; ntt(f, nm, -1); for (int i = 0; i < nm; ++i) c[i] = f[i]; } void CDQ(int l, int r) { if (l == r) { F0[l] = (F0[l] + G0[l]) % mod; F1[l] = (F1[l] + G1[l]) % mod; F2[l] = (F2[l] + G2[l]) % mod; return; } int mid = (l + r) >> 1; CDQ(l, mid); calc(F0 + l, mid - l + 1, G0, r - l + 1, tmp + l, r - l + 1); for (int i = mid + 1; i <= r; ++i) F0[i] = (F0[i] + tmp[i]) % mod; calc(F0 + l, mid - l + 1, G1, r - l + 1, tmp + l, r - l + 1); for (int i = mid + 1; i <= r; ++i) F1[i] = (F1[i] + tmp[i]) % mod; calc(F1 + l, mid - l + 1, G1, r - l + 1, tmp + l, r - l + 1); for (int i = mid + 1; i <= r; ++i) F0[i] = (F0[i] + tmp[i]) % mod; for (int i = mid + 1; i <= r; ++i) F2[i] = (F2[i] + tmp[i]) % mod; calc(F1 + l, mid - l + 1, G2, r - l + 1, tmp + l, r - l + 1); for (int i = mid + 1; i <= r; ++i) F1[i] = (F1[i] + tmp[i]) % mod; calc(F2 + l, mid - l + 1, G2, r - l + 1, tmp + l, r - l + 1); for (int i = mid + 1; i <= r; ++i) F2[i] = (F2[i] + tmp[i]) % mod; CDQ(mid + 1, r); } int n; int main() { scanf( %d , &n); g[0] = g[2] = 1; for (int i = 4; i <= n; ++i) g[i] = (g[i - 2] + g[i - 4]) % mod; for (int i = 1; i <= n; ++i) G0[i] = 1LL * (i - 1) * (i - 1) % mod * g[i - 1] % mod; for (int i = 2; i <= n; ++i) G1[i] = 1LL * (i - 1) * (i - 1) % mod * g[i - 2] % mod; for (int i = 3; i <= n; ++i) G2[i] = 1LL * (i - 1) * (i - 1) % mod * g[i - 3] % mod; CDQ(1, n); long long Ans = 1LL * n * (G0[n] + G2[n]) % mod; for (int i = 2; i <= n - 2; ++i) { Ans = (Ans + (G0[i] * F0[n - i] % mod + 2LL * G1[i] * F1[n - i] % mod + G2[i] * F2[n - i] % mod) * (long long)i % mod) % mod; } printf( %lld n , (Ans % mod + mod) % mod); return 0; } |
#include <bits/stdc++.h> using namespace std; long long sum[500]; int deep[500]; int in1[500]; int out1[500]; int in2[500]; int out2[500]; vector<int> maps1[500]; vector<int> maps2[500]; long long dp[150000]; long long n, m, t; int cnt = 0; void topo2() { queue<int> q; for (int i = 1; i <= n; ++i) if (in2[i] == 0) { q.push(i); deep[i] = 0; } int n1, n2; while (!q.empty()) { n1 = q.front(); q.pop(); cnt++; t -= deep[n1] * sum[n1]; for (int i = 0; i < maps2[n1].size(); ++i) { n2 = maps2[n1][i]; in2[n2]--; deep[n2] = max(deep[n2], deep[n1] + 1); if (in2[n2] == 0) q.push(n2); } } } void topo1() { queue<int> q; int n1, n2; for (int i = 1; i <= n; ++i) if (in1[i] == 0) { q.push(i); } while (!q.empty()) { n1 = q.front(); q.pop(); for (int i = 0; i < maps1[n1].size(); ++i) { n2 = maps1[n1][i]; in1[n2]--; sum[n2] += sum[n1]; if (in1[n2] == 0) { q.push(n2); } } } } int main() { scanf( %lld%lld%lld , &n, &m, &t); for (int i = 1; i <= n; ++i) scanf( %lld , &sum[i]); for (int i = 1; i <= m; ++i) { int x, y; scanf( %d%d , &x, &y); maps1[x].push_back(y); in1[y]++; out1[x]++; maps2[y].push_back(x); in2[x]++; out2[y]++; } topo2(); if (t < 0 || cnt != n) printf( 0 n ); else { topo1(); memset(dp, 0, sizeof(dp)); dp[0] = 1; for (long long i = 1; i <= n; ++i) { for (long long j = sum[i]; j <= t; ++j) { dp[j] += dp[j - sum[i]]; dp[j] %= 1000000007; } } printf( %lld n , dp[t]); } return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame FIFO (64 bit datapath)
*/
module axis_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
reg drop_frame = 1'b0;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
// full when first MSB different but rest same
wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr == rd_ptr;
// overflow in single packet
wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
wire write = input_axis_tvalid & (~full | DROP_WHEN_FULL);
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
// write
always @(posedge clk or posedge rst) begin
if (rst) begin
wr_ptr <= 0;
wr_ptr_cur <= 0;
drop_frame <= 0;
end else if (write) begin
if (full | full_cur | drop_frame) begin
// buffer full, hold current pointer, drop packet at end
drop_frame <= 1;
if (input_axis_tlast) begin
wr_ptr_cur <= wr_ptr;
drop_frame <= 0;
end
end else begin
mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_cur <= wr_ptr_cur + 1;
if (input_axis_tlast) begin
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur <= wr_ptr;
end else begin
// good packet, push new write pointer
wr_ptr <= wr_ptr_cur + 1;
end
end
end
end
end
// read
always @(posedge clk or posedge rst) begin
if (rst) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr <= rd_ptr + 1;
end
end
// source ready output
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<long long> a(n), b(n); for (long long i = 0; i < n; ++i) cin >> a[i]; for (long long i = 0; i < n; ++i) cin >> b[i]; map<long long, vector<long long> > mp; long long m; cin >> m; for (long long i = 0; i < n; ++i) { mp[a[i]].push_back(i + 1); mp[b[i]].push_back(i + 1); } long long ans = 1; for (auto it = mp.begin(); it != mp.end(); ++it) { long long den = 0; long long num = it->second.size(); sort(it->second.begin(), it->second.end()); for (long long i = 1; i < (it->second.size()); ++i) { if ((it->second[i]) == (it->second[i - 1])) den++; } long long nn = 1; for (long long i = num; i > 0; --i) { if (i & 1 || den == 0) nn *= i; else { nn *= (i / 2); den--; } if (nn > m) nn %= m; } ans *= nn; if (ans > m) ans %= m; } cout << ans % m; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; void chis(int x) { switch (x) { case 0: cout << zero << endl; break; case 1: cout << one << endl; break; case 2: cout << two << endl; break; case 3: cout << three << endl; break; case 4: cout << four << endl; break; case 5: cout << five << endl; break; case 6: cout << six << endl; break; case 7: cout << seven << endl; break; case 8: cout << eight << endl; break; case 9: cout << nine << endl; break; } } void chis2(int x) { switch (x) { case 2: cout << twenty ; break; case 3: cout << thirty ; break; case 4: cout << forty ; break; case 5: cout << fifty ; break; case 6: cout << sixty ; break; case 7: cout << seventy ; break; case 8: cout << eighty ; break; case 9: cout << ninety ; break; } } void chis3(int x) { switch (x) { case 10: cout << ten << endl; break; case 11: cout << eleven << endl; break; case 12: cout << twelve << endl; break; case 13: cout << thirteen << endl; break; case 14: cout << fourteen << endl; break; case 15: cout << fifteen << endl; break; case 16: cout << sixteen << endl; break; case 17: cout << seventeen << endl; break; case 18: cout << eighteen << endl; break; case 19: cout << nineteen << endl; break; } } void read() { cin >> n; if (n <= 9) chis(n); else { int des = n / 10; if (des == 1) chis3(n); else { chis2(des); int ost = n % 10; if (ost == 0) cout << endl; else { cout << - ; chis(ost); } } } } int main() { read(); return 0; } |
`ifndef _regstatus
`define _regstatus
// two read ports, two write port
module regstatus (
input clk,
input rst,
input wr_regs_en,
input [4:0] wr_regs_tag,
input [3:0] wr_regs_rb_tag,
input [4:0] rd_reg_tag1,
input [4:0] rd_reg_tag2,
input commit_en,
input [4:0] commit_reg_tag,
input flush_regs,
output [3:0] rd_rb_tag1,
output rd_bsy1,
output [3:0] rd_rb_tag2,
output rd_bsy2
);
typedef struct packed {
bit [3:0] rb_tag;
bit bsy;
}regstatusStruct;
regstatusStruct regs_array [31:0];
always @(posedge clk, negedge rst) begin
if (!rst) begin
for ( int i = 0; i < $size(regs_array); i++) begin
regs_array[i] <= {$size(regstatusStruct){1'b0}};
end
end
else begin
if (flush_regs) begin
for ( int i = 0; i < $size(regs_array); i++) begin
regs_array[i] <= {$size(regstatusStruct){1'b0}};
end
end
else begin
if (wr_regs_en) begin
regs_array[wr_regs_tag].rb_tag <= wr_regs_rb_tag;
regs_array[wr_regs_tag].bsy <= 1'b1;
end
if (commit_en) begin
//wr_regs_en has higher priority
if (!(wr_regs_en && wr_regs_tag == commit_reg_tag)) begin
regs_array[commit_reg_tag].bsy <= 1'b0;
end
end
end
end
end // always @ (posedge clk, negedge rst)
assign rd_rb_tag1 = regs_array[rd_reg_tag1].rb_tag;
assign rd_bsy1 = regs_array[rd_reg_tag1].bsy;
assign rd_rb_tag2 = regs_array[rd_reg_tag2].rb_tag;
assign rd_bsy2 = regs_array[rd_reg_tag2].bsy;
endmodule // regstatus
`endif
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(long long first) { return first ? 8 * sizeof(long long) - __builtin_clzll(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; int Prev[int(1e5) + 3]; class EEgorAndAnRPGGame { public: void solve(istream& cin, ostream& cout) { int T; cin >> T; for (int t = 0; t < T; ++t) { int N; cin >> N; vector<int> A(N); cin >> A; vector<vector<int>> Ans; while (!A.empty()) { int M = A.size(); vector<vector<int>> B{{0}}; for (int i = 0; i < M; ++i) { int s = bsh(0, int(B.size() - 1), [&](int first) { return B[first].back() < A[i]; }); if (s == B.size() - 1) B.emplace_back(); B[s + 1].push_back(A[i]); Prev[A[i]] = B[s].back(); } vector<int> Cur, Left; int idx = B.back().back(); while (idx != 0) { Cur.push_back(idx); idx = Prev[idx]; } reverse(Cur.begin(), Cur.end()); int j = 0; for (int i = 0; i < M; ++i) { if (j != Cur.size() && Cur[j] == A[i]) ++j; else Left.push_back(A[i]); } int K = Cur.size(); if (K * (K + 1) / 2 >= A.size()) { swap(A, Left); Ans.push_back(Cur); } else { for (auto& b : B) { if (b.front() == 0) continue; Ans.emplace_back(); for (auto& bb : b) { Ans.back().push_back(bb); } } break; } } cout << Ans.size() << endl; for (auto& ans : Ans) { cout << ans.size() << << ans; } } } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); EEgorAndAnRPGGame solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module vita_pkt_gen
(input clk, input reset, input clear,
input [15:0] len,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
reg [15:0] state;
reg [31:0] seq, data;
wire sof = (state == 0);
wire eof = (state == (len-1));
wire consume = src_rdy_o & dst_rdy_i;
assign src_rdy_o = 1;
always @(posedge clk)
if(reset | clear)
begin
state <= 0;
seq <= 0;
end
else
if(consume)
if(eof)
begin
state <= 0;
seq <= seq + 1;
end
else
state <= state + 1;
always @*
case(state)
0 : data <= {24'h000,seq[3:0],len};
1 : data <= seq;
default : data <= {~state,state};
endcase // case (state)
assign data_o = {2'b00, eof, sof, data};
endmodule // vita_pkt_gen
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; int *sher = new int[n]; char d; for (int i = 0; i < n; i++) { cin >> d; sher[i] = d - 0 ; } int *mor = new int[n]; for (int i = 0; i < n; i++) { cin >> d; mor[i] = d - 0 ; } sort(sher, sher + n, greater<int>()); sort(mor, mor + n, greater<int>()); int out = 0; int l = 0, r = n - 1; for (int i = 0; i < n; i++) { if (sher[i] > mor[l]) { r--; out++; } else l++; } cout << out << endl; l = 0; r = n - 1; out = 0; for (int i = 0; i < n; i++) { if (sher[i] < mor[l]) { l++; out++; } else r--; } cout << out << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, pos, kol; long long a[1000]; int main() { cin >> n; for (long long i = 1; i <= 2 * n; ++i) cin >> a[i]; for (long long i = 1; i < 2 * n; ++i) { for (long long j = i + 1; j <= 2 * n; ++j) { if (a[i] == a[j]) { pos = j; break; } } while (pos > i + 1) { swap(a[pos - 1], a[pos]); --pos; ++kol; } } cout << kol << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<int> x(n + m - 1); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int a; cin >> a; x[i + j] ^= a; } } bool flag = false; for (int i = 0; i < n + m - 1; i++) { if (x[i] != 0) { flag = true; break; } } cout << (flag ? Ashish : Jeel ) << n ; } return 0; } |
module main;
time period;
reg drive;
// This is the main point of the test. Non-constant delay expressions
// should work here.
wire #(period/3) trace = drive;
initial begin
period = 8*3;
// Initially, set up a period=8 and get the trace to start
// following the drive.
#1 drive <= 1;
#9 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
// The drive should NOT change the trace before the period.
drive <= 0;
#7 if (trace !== 1'b1) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
#2 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
// Change the period.
period = 6*3;
// Now check that the new delay is taken.
#1 drive <= 1;
#5 if (trace !== 1'b0) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
#2 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase w/ null_statement - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000,3'b001: result = 0;
3'b10x: ;
3'b001: result = 1;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9D - lab w/ null expr: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9D - lab w/ null expr: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b010
val2 = 3'b010;
if(result !=1)
begin
$display("FAILED casex 3.9D - lab w/ null expr: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i, j, k, m, c1 = 0, count2 = 0, m3 = 0; cin >> n; long long int a[n]; map<long long int, long long int> m1; for (i = 0; i < n; i++) { cin >> a[i]; m1[i] = -1; } cin >> m; vector<long long int> v; for (i = 0; i < m; i++) { long long int p, q, r; cin >> p; if (p == 1) { cin >> q >> r; a[q - 1] = r; m1[q - 1] = i; v.push_back(0); } else { cin >> q; m3 = max(m3, q); v.push_back(q); } } long long int max1[v.size() - 1]; memset(max1, 0, sizeof(max1)); long long int m_1 = 0; for (i = (m - 1); i >= 0; i--) { if (v[i] > m_1) { max1[i] = max(m_1, v[i]); m_1 = max(m_1, v[i]); } else { max1[i] = m_1; m_1 = max(m_1, v[i]); } } for (i = 0; i < n; i++) { if (m1[i] >= m) { cout << a[i] << ; } else if (m1[i] != -1) { cout << max(a[i], max1[m1[i]]) << ; } else { cout << max(a[i], m3) << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)2e5 + 5; const int K = 30; int p[N]; char s[N]; int get(int l, int r, int s) { l = max(l, s * K); if (l > r) return 0; return r / s - l / s; } int main() { scanf( %s , s); int n = strlen(s); for (int i = 0; i < n; ++i) p[i + 1] = p[i] + (int)(s[i] == 1 ); long long ans = 0; map<int, int> cnt; for (int k = 1; k <= K; ++k) { cnt.clear(); for (int i = 0; i <= n; ++i) ++cnt[i - k * p[i]]; for (auto pr : cnt) ans += pr.second * (long long)(pr.second - 1) / 2; } vector<int> one; for (int i = 0; i < n; ++i) if (s[i] == 1 ) one.push_back(i); one.push_back(n); reverse((one).begin(), (one).end()); for (int i = 0; i < n; ++i) { int sz = (int)(one).size(); for (int j = 0; j < min(n / K + 1, sz - 1); ++j) ans += get(one[sz - j - 1] - i, one[sz - (j + 1) - 1] - i, j + 1); if (s[i] == 1 ) one.pop_back(); } printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, c = 0, i, aa = 0, bb = 0; cin >> n; int a[n], b[n]; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; aa = aa + a[i]; bb = bb + b[i]; } if (aa % 2 == 1 && bb % 2 == 1) { for (i = 0; i < n; i++) { if ((a[i] + b[i]) % 2 == 1) { c++; break; } } } if (aa % 2 == 0 && bb % 2 == 0) cout << 0 ; else if (c == 1) cout << 1 ; else cout << -1 ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> template <typename T> bool chkmax(T &x, T y) { return x < y ? x = y, true : false; } template <typename T> bool chkmin(T &x, T y) { return x > y ? x = y, true : false; } using namespace std; long long ksm(long long a, long long b) { if (!b) return 1; long long ns = ksm(a, b >> 1); ns = ns * ns % 998244353; if (b & 1) ns = ns * a % 998244353; return ns; } int pl[5500]; struct th { int sz; int l, r; vector<int> pls; th *ch[2]; vector<vector<int> > id; } p[200005], *rt[70]; int cal(th *a, int l, int r) { int p1 = lower_bound(a->pls.begin(), a->pls.end(), l) - a->pls.begin(); int p2 = lower_bound(a->pls.begin(), a->pls.end(), r + 1) - a->pls.begin() - 1; if (p1 > p2) return 0; return a->id[p1][p2]; } int cnt = 0; vector<pair<int, int> > g; int mer(int x, int y) { if (!x) return y; if (!y) return x; cnt++; g.push_back(make_pair(x, y)); return cnt; } int stcnt = 0; void bdtree(th *a, int l, int r) { a->l = l, a->r = r; for (int i = l; i <= r; i++) a->pls.push_back(pl[i]); int sz = r - l + 1; sort(a->pls.begin(), a->pls.end()); a->id.resize(sz); for (int j = 0; j < sz; j++) a->id[j].resize(sz); if (sz == 1) a->id[0][0] = a->pls[0]; else { int mid = (l + r) >> 1; a->ch[0] = &p[stcnt++], a->ch[1] = &p[stcnt++]; bdtree(a->ch[0], l, mid); bdtree(a->ch[1], mid + 1, r); for (int i = 0; i < sz; i++) for (int j = i; j < sz; j++) a->id[i][j] = mer(cal(a->ch[0], a->pls[i], a->pls[j]), cal(a->ch[1], a->pls[i], a->pls[j])); } } int re[100005]; int main() { int n, qs; scanf( %d%d , &n, &qs); cnt = n; for (int i = 1; i <= n; i++) { int a; scanf( %d , &a), pl[a] = i; } vector<th *> q; int nr = 1; while (nr <= n) { th *n1 = &p[stcnt++]; int ur = min(n, nr + 200); bdtree(n1, nr, ur); q.push_back(n1); nr = ur + 1; } for (int i = 1; i <= qs; i++) { int pr = 0; int l, r; scanf( %d%d , &l, &r); for (auto m : q) pr = mer(pr, cal(m, l, r)); re[i] = pr; } cout << cnt << endl; for (auto h : g) printf( %d %d n , h.first, h.second); for (int i = 1; i <= qs; i++) printf( %d , re[i]); return 0; } |
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