text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; int main() { string s; int sum = 0, d = 0, diff = 0; int start = 97; cin >> s; for (int i = 0; i < s.size(); i++) { diff = abs((int)s[i] - start); if (diff > 13) { d = 26 - diff; sum += d; } else { sum += diff; } start = (int)s[i]; } cout << sum; return 0; } |
module uart(
clk32,
reset_,
rx,
tx,
txdata,
rxdata,
rx_enable,
tx_enable,
tx_ready);
input clk32; // 32 Mhz clock input
input reset_; // Reset
input rx; // Serial RX from FTDI USB chip
output tx; // Serial TX from FTDI USB chip
input [7:0] txdata; // Byte to be transmitted
output [7:0] rxdata; // Byte received
output rx_enable; // When high, rxdata is ready
input tx_enable; // Set high to tell transmitter to send txdata, no affect when !tx_ready
output tx_ready; // When high, device is ready to transmit
wire baud;
wire sample;
reg [8:0] baud_ctr;
reg [4:0] sample_ctr;
// Serial transmission baud rate
parameter BAUD_FREQ = 115_200;
// Incoming clock frequency
parameter CLK32_FREQ = 32_000_000;
// Serial input is sampled at 16x the baud rate
parameter SAMPLE_FREQ = 16;
// Accumulator/counter max values to create sample/baud pulse
parameter BAUD_MAX = CLK32_FREQ / BAUD_FREQ;
parameter SAMPLE_MAX = CLK32_FREQ / (BAUD_FREQ * SAMPLE_FREQ);
assign baud = baud_ctr == BAUD_MAX; // Pulse at baud frequency
assign sample = sample_ctr == SAMPLE_MAX; // Pulse at sample frequency
// Serial transmitter
tx transmit (
.clk(clk32),
.reset_(reset_),
.baud(baud),
.txdata(txdata),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx));
// Serial receiver
rx receive(
.clk(clk32),
.reset_(reset_),
.sample(sample),
.rx(rx),
.rx_enable(rx_enable),
.rxdata(rxdata));
// Baud frequency counter
always@ (posedge clk32 or negedge reset_)
if (!reset_)
baud_ctr <= 9'd0;
else if (baud_ctr == BAUD_MAX)
baud_ctr <= 9'd0;
else
baud_ctr <= baud_ctr + 9'd1;
// Input sample frequency counter
always@ (posedge clk32 or negedge reset_)
if (!reset_)
sample_ctr <= 5'd0;
else if (sample_ctr == SAMPLE_MAX)
sample_ctr <= 5'd0;
else
sample_ctr <= sample_ctr + 5'd1;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &a) { a = 0; int c = getchar(), b = 1; while (c > 9 || c < 0 ) { if (c == - ) b = -1; c = getchar(); } while (c >= 0 && c <= 9 ) a = (a << 3) + (a << 1) + c - 48, c = getchar(); a *= b; } inline int Rem() { int a = 0, c = getchar(), b = 1; while (c > 9 || c < 0 ) { if (c == - ) b = -1; c = getchar(); } while (c >= 0 && c <= 9 ) a = (a << 3) + (a << 1) + c - 48, c = getchar(); return a *= b; } inline void write(long long x) { if (x > 9) write(x / 10); putchar( 0 + x % 10); } inline void W(long long x) { if (x < 0) { putchar( - ), x = -x; } write(x); } const int N = 2e5 + 5, M = 1e6 + 5; int n, m, a[N], pos[N], block; long long ans, rec[N], cnt[M]; struct node { int l, r, id; } q[N]; inline bool cmp(node a, node b) { return (pos[a.l] == pos[b.l]) ? (pos[a.l] & 1 ? a.r < b.r : a.r > b.r) : a.l < b.l; } inline void add(int x) { cnt[x]++; ans += ((cnt[x] * cnt[x]) - ((cnt[x] - 1) * (cnt[x] - 1))) * x; } inline void del(int x) { ans -= ((cnt[x] * cnt[x]) - ((cnt[x] - 1) * (cnt[x] - 1))) * x; cnt[x]--; } int main() { read(n); read(m); block = sqrt(n); for (register int i = 1; i <= n; i++) read(a[i]), pos[i] = i / block; for (register int i = 1; i <= m; i++) { read(q[i].l); read(q[i].r); q[i].id = i; } sort(q + 1, q + 1 + m, cmp); for (register int i = 1, ql, qr, l = 1, r = 0; i <= m; i++) { ql = q[i].l, qr = q[i].r; while (ql < l) add(a[--l]); while (ql > l) del(a[l++]); while (qr < r) del(a[r--]); while (qr > r) add(a[++r]); rec[q[i].id] = ans; } for (register int i = 1; i <= m; i++) W(rec[i]), putchar( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1000005], b[1000005]; int main() { int n, ans = 0; cin >> n; for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); a[x]++; } for (int i = 1000000; i >= 1; i--) { if (!a[i]) continue; b[i] = 1; for (int j = 2 * i; j <= 1000000; j += i) { if (a[j] && b[i] < b[j] + 1) b[i] = b[j] + 1; } if (ans < b[i]) ans = b[i]; } cout << ans; return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 20:38:45 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/parallella-hw/fpga/vivado/junk/junk.srcs/sources_1/ip/fifo_async_103x16/fifo_async_103x16_stub.v
// Design : fifo_async_103x16
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
module fifo_async_103x16(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[102:0],wr_en,rd_en,dout[102:0],full,empty,prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [102:0]din;
input wr_en;
input rd_en;
output [102:0]dout;
output full;
output empty;
output prog_full;
endmodule
|
//**************************************************************************
// hp_reg3.v - 2 byte FIFO for 16b transfers in host to parasite direction
//
// COPYRIGHT 2010 Richard Evans, Ed Spittles
//
// This file is part of tube - an Acorn Tube ULA compatible system.
//
// tube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// tube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with tube. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
`timescale 1ns / 1ns
module hp_reg3 (
input h_rst_b,
input h_we_b,
input h_selectData,
input h_phi2,
input [7:0] h_data,
input p_selectData,
input p_phi2,
input p_rdnw,
input one_byte_mode,
output [7:0] p_data,
output p_data_available,
output p_two_bytes_available,
output h_full
);
wire [1:0] h_full_w;
wire [1:0] p_data_available_w;
reg [7:0] byte0_q_r ;
reg [7:0] byte1_q_r ;
wire [7:0] byte0_d_w ;
wire [7:0] byte1_d_w ;
// assign primary IOs
assign p_data = ( p_data_available_w[0] ) ? byte0_q_r: byte1_q_r;
// assign p_data = byte0_q_r;
assign p_two_bytes_available = !(one_byte_mode) & ( &p_data_available_w );
// Compute D and resets for state bits
assign byte0_d_w = ( h_selectData & (!h_full_w[0] | one_byte_mode) & !h_we_b ) ? h_data : byte0_q_r;
assign byte1_d_w = ( h_selectData & ( h_full_w[0] & !one_byte_mode) & !h_we_b ) ? h_data : byte1_q_r;
// Register 3 is intended to enable high speed transfers of large blocks of data across the tube.
// It can operate in one or two byte mode, depending on the V flag. In one byte mode the status
// bits make each FIFO appear to be a single byte latch - after one byte is written the register
// appears to be full. In two byte mode the data available flag will only be asserted when two bytes have
// been entered, and the not full flag will only be asserted when both bytes have been removed. Thus data
// available going active means that two bytes are available, but it will remain active until both bytes
// have been removed. Not full going active means that the register is empty, but it will remain active
// until both bytes have been entered. PNMI, N and DRQ also remain active until the full two
// byte operation is completed
assign p_data_available = (p_data_available_w[0] & one_byte_mode) | p_data_available_w[1];
assign h_full = ( one_byte_mode ) ? h_full_w[0] : h_full_w[1];
// Instance the appropriate flag logic
hp_flag_m flag_0 (
.rst_b(h_rst_b),
.p1_rdnw( h_we_b),
.p1_select(h_selectData & (!h_full_w[0] | one_byte_mode)),
.p1_clk(h_phi2),
.p2_select(p_selectData & (p_data_available_w[0] | one_byte_mode)),
.p2_rdnw(p_rdnw),
.p2_clk(p_phi2),
.p2_data_available(p_data_available_w[0]),
.p1_full(h_full_w[0])
);
hp_flag_m flag_1 (
.rst_b(h_rst_b),
.p1_rdnw( h_we_b),
.p1_select(h_selectData & (h_full_w[0] & !one_byte_mode)),
.p1_clk(h_phi2),
.p2_select(p_selectData & (!p_data_available_w[0] & !one_byte_mode)),
.p2_rdnw(p_rdnw),
.p2_clk(p_phi2),
.p2_data_available(p_data_available_w[1]),
.p1_full(h_full_w[1])
);
always @ ( negedge h_phi2 or negedge h_rst_b )
begin
if ( ! h_rst_b)
begin
byte0_q_r <= 8'h0;
byte1_q_r <= 8'h0;
end
else
begin
byte0_q_r <= byte0_d_w ;
byte1_q_r <= byte1_d_w ;
end
end
endmodule // hp_reg3
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int N = 1e5 + 10, INFI = 1e9 + 10; int val[12]; unordered_set<int> s; int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < 12; i++) { s.clear(); for (int a = 0; a <= i + 1; a++) { for (int b = 0; b <= i + 1 - a; b++) { for (int c = 0; c <= i + 1 - a - b; c++) { for (int d = 0; d <= i + 1 - a - b - c; d++) { if (a + b + c + d == i + 1) { s.insert((a * 1) + (b * 5) + (c * 10) + (d * 50)); } } } } } val[i] = s.size(); } if (n <= 12) { cout << val[n - 1] << endl; } else { cout << val[11] + 1LL * 49 * (n - 12) << endl; } return 0; } |
#pragma GCC optimize ( O3 ) #pragma GCC target ( sse4 ) #include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef vector<int> vi; typedef pair<int, int> pi; #define debug(x) cerr << #x << : << x << n #define debug2(x, y) debug(x), debug(y) #define repn(i, a, b) for(int i = (int)(a); i < (int)(b); i++) #define rep(i, a) for(int i = 0; i < (int)(a); i++) #define all(v) v.begin(), v.end() #define mp make_pair #define pb push_back #define lb lower_bound #define ub upper_bound #define fi first #define se second #define sq(x) ((x) * (x)) const int MOD = 1e9 + 7; const int mxN = 205; template<class T> T gcd(T a, T b){ return ((b == 0) ? a : gcd(b, a % b)); } vi g[mxN]; int up[mxN][10]; ll p[mxN][mxN]; int st[mxN], en[mxN], d[mxN]; int cnt = 0; void dfs(int cur, int prev, int di = 0){ st[cur] = cnt++; d[cur] = di; up[cur][0] = prev; repn(i, 1, 10) up[cur][i] = up[up[cur][i - 1]][i - 1]; for(int x : g[cur]) if(x != prev) dfs(x, cur, di + 1); en[cur] = cnt++; } bool upper(int a, int b){ return st[a] <= st[b] && en[a] >= en[b]; } int lca(int a, int b){ if(upper(a, b)) return a; if(upper(b, a)) return b; for(int i = 9; i >= 0; i--) if(!upper(up[a][i], b)) a = up[a][i]; return up[a][0]; } ll mypow(ll a, ll p){ if(p == 0) return 1; if(p == 1) return (a % MOD); if(p & 1) return ((a % MOD) * (mypow(a, p - 1) % MOD)) % MOD; ll x = mypow(a, p / 2) % MOD; return (x * x) % MOD; } ll inv(ll base){ return mypow(base, MOD - 2); } int main(){ ios_base::sync_with_stdio(false); cin.tie(0); //freopen( input.in , r , stdin); //freopen( output.out , w , stdout); ll n; cin >> n; rep(i, n - 1){ int x, y; cin >> x >> y; x--, y--; g[x].pb(y); g[y].pb(x); } p[0][0] = 1LL; rep(i, mxN - 1){ rep(j, i + 1){ int k = i - j; (p[j + 1][k] += (p[j][k] * inv(2)) % MOD) %= MOD; (p[j][k + 1] += (p[j][k] * inv(2)) % MOD) %= MOD; } } rep(k, n) repn(j, 1, n) (p[j][k] += p[j - 1][k]) %= MOD; ll ans = 0LL; rep(i, n){ cnt = 0; dfs(i, i); rep(j, n) repn(k, j + 1, n){ if(upper(k, j)) ans++; else if(!upper(j, k)){ int c = lca(j, k); int a = d[j] - d[c], b = d[k] - d[c]; (ans += (p[a - 1][b - 1] * inv(2)) % MOD) %= MOD; } } } cout << (ans * inv(n)) % MOD << n ; return 0; } /* Things to look out for: - Integer overflows - Make sure that max is large enough (2e9, 4e18) - Special cases Be careful! */ |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int arr[n + 10]; for (int i = 1; i <= n; i++) scanf( %d , &arr[i]); int start, end; start = 1; int pos_1 = -1, pos_2 = -1; int cnt = 0; int t = 0; for (int i = 1; i <= n;) { pos_1 = -1; pos_2 = -1; start = i; for (int j = start; j <= n; j++) { if (arr[j] != -1) { pos_1 = j; break; } } if (pos_1 != -1) { for (int j = pos_1 + 1; j <= n; j++) if (arr[j] != -1) { pos_2 = j; break; } if (pos_2 == -1) { cnt++; break; } t++; if (arr[pos_1] == arr[pos_2]) { start = pos_2 + 1; for (int j = pos_2 + 1; j <= n; j++) if (arr[j] == -1 || arr[j] == arr[pos_1]) start = j + 1; else { start = j; break; } cnt++; } else { long long val = (arr[pos_2] - arr[pos_1]); int d = pos_2 - pos_1; if (val % d == 0) { int yes = val / d; val = arr[pos_1]; yes *= (-1); for (int j = pos_1 - 1; j >= start; j--) { val += yes; if (val <= 0) { cnt++; start = pos_2; goto End; } if (arr[j] != -1 && arr[j] != val) { cnt++; start = pos_2; goto End; } } val = arr[pos_2]; yes *= (-1); start = -1; for (int j = pos_2 + 1; j <= n; j++) { val += yes; if (val <= 0) { start = j; break; } if (arr[j] != -1 && arr[j] != val) { start = j; break; } } if (start == -1) start = n + 1; cnt++; } else { cnt += 1; start = pos_2; } } } else { cnt++; break; } End:; i = start; } cout << cnt << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
typedef struct packed {
logic [3:2] a;
logic [5:4][3:2] b;
} ab_t;
typedef ab_t [7:6] c_t; // array of structs
typedef struct packed {
c_t [17:16] d;
} e_t;
`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
initial begin
e_t e;
`checkh($bits(ab_t),6);
`checkh($bits(c_t),12);
`checkh($bits(e_t),24);
`checkh($bits(e), 24);
`checkh($bits(e.d[17]),12);
`checkh($bits(e.d[16][6]),6);
`checkh($bits(e.d[16][6].b[5]),2);
`checkh($bits(e.d[16][6].b[5][2]), 1);
//
e = 24'b101101010111010110101010;
`checkb(e, 24'b101101010111010110101010);
e.d[17] = 12'b111110011011;
`checkb(e, 24'b111110011011010110101010);
e.d[16][6] = 6'b010101;
`checkb(e, 24'b111110011011010110010101);
e.d[16][6].b[5] = 2'b10;
`checkb(e, 24'b111110011011010110011001);
e.d[16][6].b[5][2] = 1'b1;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 7E5 + 10; const int BASE = 1E6 + 3; int n, p; long long f[MAX]; long long power(int x, int n) { if (n == 0) return 1; long long tmp = power(x, n / 2); tmp = tmp * tmp; if (n % 2) tmp = tmp * x; tmp %= BASE; return tmp; } long long C(int k, int n) { return f[n] * power((f[n - k] * f[k]) % BASE, BASE - 2); } void init() { f[0] = 1; for (int i = 1; i < n + p; i++) f[i] = (f[i - 1] * i) % BASE; } int main() { scanf( %d%d , &n, &p); init(); long long res = 0; for (int i = 1; i <= n; i++) res = (res + C(p - 1, i + p - 1)) % BASE; printf( %I64d , res); } |
`include "defines.v"
`define goldsel_w [7:0]
module sortnet
(
input clk,
input `rmatrix_w rmatrix0,
input `rmatrix_w rmatrix1,
input `rmatrix_w rmatrix2,
input `rmatrix_w rmatrix3,
input `steer_w control0_in,
input `steer_w control1_in,
input `steer_w control2_in,
input `steer_w control3_in,
output `steer_w control0_out,
output `steer_w control1_out,
output `steer_w control2_out,
output `steer_w control3_out
);
wire `goldsel_w gold_sel;
wire [15:0] rand;
gold_counter gc(.clk(clk), .gold_sel(gold_sel));
pseudorandom ps(.clk(clk), .pseudorand(rand));
wire `steer_w inter0, inter1, inter2, inter3;
wire `rmatrix_w inter0_rm, inter1_rm, inter2_rm, inter3_rm;
// always @(*)
// $display("sortnet 0: %04x %04x %04x %04x (gold_sel %d)", control0_in, control1_in, control2_in, control3_in, gold_sel);
arbiter_block arb0(
.gold_sel(gold_sel),
.pseudorand(rand[3]),
.in0(control0_in),
.in1(control2_in),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix2),
.out0(inter0),
.out1(inter2),
.rmout0(inter0_rm),
.rmout1(inter2_rm),
.route_0(4'b1100),
.route_1(4'b0011));
arbiter_block arb1(
.gold_sel(gold_sel),
.pseudorand(rand[3]),
.in0(control1_in),
.in1(control3_in),
.rmatrix0(rmatrix1),
.rmatrix1(rmatrix3),
.out0(inter1),
.out1(inter3),
.rmout0(inter1_rm),
.rmout1(inter3_rm),
.route_0(4'b1100),
.route_1(4'b0011));
wire `rmatrix_w dummy0_rm, dummy1_rm, dummy2_rm, dummy3_rm;
// always @(*)
// $display("sortnet 1: %04x %04x %04x %04x", inter0, inter1, inter2, inter3);
arbiter_block arb2(
.gold_sel(gold_sel),
.pseudorand(rand[3]),
.in0(inter0),
.in1(inter1),
.rmatrix0(inter0_rm),
.rmatrix1(inter1_rm),
.out0(control0_out),
.out1(control1_out),
.rmout0(dummy0_rm),
.rmout1(dummy1_rm),
.route_0(4'b1000),
.route_1(4'b0100));
arbiter_block arb3(
.gold_sel(gold_sel),
.pseudorand(rand[3]),
.in0(inter2),
.in1(inter3),
.rmatrix0(inter2_rm),
.rmatrix1(inter3_rm),
.out0(control2_out),
.out1(control3_out),
.rmout0(dummy2_rm),
.rmout1(dummy3_rm),
.route_0(4'b0010),
.route_1(4'b0001));
// always @(*)
// $display("sortnet 2: %04x %04x %04x %04x", control0_out , control1_out , control2_out , control3_out );
endmodule
module arbiter_block
(
input pseudorand,
input `goldsel_w gold_sel,
input `steer_w in0,
input `steer_w in1,
output `steer_w out0,
output `steer_w out1,
input `rmatrix_w rmatrix0,
input `rmatrix_w rmatrix1,
output `rmatrix_w rmout0,
output `rmatrix_w rmout1,
input `rmatrix_w route_0,
input `rmatrix_w route_1
);
wire desired0 = (rmatrix0 & route_1) != 0 ? 1 : 0;
wire desired1 = (rmatrix1 & route_1) != 0 ? 1 : 0;
// decide winner
wire valid0 = in0[`valid_f], valid1 = in1[`valid_f];
wire `goldsel_w goldnum0 = { in0[`mshr_f], in0[`src_f] }, goldnum1 = { in1[`mshr_f], in1[`src_f] };
wire gold0 = (goldnum0 == gold_sel), gold1 = (goldnum1 == gold_sel);
wire seq0 = in0[`seq_f], seq1 = in1[`seq_f];
wire winner = (
// in1 wins if: both valid both gold and tiebreak 1; both valid 1 gold; both valid,
// neither gold, pseudorand; only 1 is valid.
(valid0 && valid1) && (gold0 && gold1) && (seq1 > seq0) ||
(valid0 && valid1) && (~gold0 && gold1) ||
(valid0 && valid1) && (~gold0 && ~gold1) && pseudorand ||
(~valid0 && valid1)
);
// swap?
wire swap =
winner ? ~desired1 : desired0;
// always @(*)
// $display("pseudorand = %d goldsel = %d in0 = %05x in1 = %05x rm0 = %x rm1 = %x desired0 = %d desired1 = %d valid0 = %d valid1 = %d gold0 = %d gold1 = %d winner = %d swap = %d out0 = %x out1 = %x",
// pseudorand, gold_sel, in0, in1, rmatrix0, rmatrix1, desired0, desired1, valid0, valid1, gold0, gold1, winner, swap, out0, out1);
// assign
assign rmout0 = swap ? rmatrix1 : rmatrix0;
assign rmout1 = swap ? rmatrix0 : rmatrix1;
assign out0 = swap ? in1 : in0;
assign out1 = swap ? in0 : in1;
endmodule
module gold_counter
(
input clk,
output reg `goldsel_w gold_sel
);
initial gold_sel = 0;
always @(posedge clk) gold_sel <= gold_sel + 1;
endmodule
module pseudorandom
(
input clk,
output reg [15:0] pseudorand
);
// LFSR, taps at 7 and 3
always @(posedge clk)
pseudorand <= { pseudorand[14:0], pseudorand[7] ^ pseudorand[3] };
initial pseudorand = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int c = 0; void bfs(map<long long int, vector<long long int> > &map, vector<bool> &visited, long long int x) { queue<long long int> q; q.push(x); visited[x] = true; while (!q.empty()) { long long int y = q.front(); q.pop(); for (long long int i : map[y]) { if (!visited[i]) { q.push(i); visited[i] = true; } } } } int main() { long long int x, y, n, m; cin >> n >> m; map<long long int, vector<long long int> > map; std::vector<bool> visited(n + 1, false), visitedf(n + 1, false); for (long long int i = 0; i < m; i++) { cin >> x >> y; map[x].push_back(y); map[y].push_back(x); } if (m != n - 1) { cout << no ; return 0; } bfs(map, visited, map.begin()->first); for (long long int i = 1; i <= n; i++) { if (!visited[i]) { cout << no ; return 0; } } cout << yes ; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_clz(mantissa, result, all_zero);
// count the number of leading zeros in the 27-bit mantissa
input [26:0] mantissa;
output [4:0] result;
output all_zero;
wire top_16 = ~|mantissa[26:11];
wire top_8 = ~|mantissa[26:19];
wire top_4 = ~|mantissa[26:23];
wire top_2 = ~|mantissa[26:25];
wire bottom_8 = ~(|mantissa[10:3]);
wire bottom_4 = ~(|mantissa[10:7]);
wire bottom_2 = ~(|mantissa[10:9]);
wire all_clear = ~|mantissa;
assign result[4] = top_16;
assign result[3] = top_16 & bottom_8 | ~top_16 & top_8;
assign result[2] = (top_16 & ~bottom_8 & bottom_4) | (~top_16 & top_8 & ~|mantissa[18:15]) |
(~top_16 & ~top_8 & top_4);
assign result[1] = (top_16 & bottom_8 & ~|mantissa[2:1]) | (top_16 & ~bottom_8 & bottom_4 & ~|mantissa[6:5]) |
(top_16 & ~bottom_8 & ~bottom_4 & bottom_2) |
(~top_16 & top_8 & ~|mantissa[18:17] & |mantissa[16:15]) |
(~top_16 & top_8 & ~|mantissa[18:13]) |
(~top_16 & ~top_8 & top_4 & ~|mantissa[22:21]) |
(~top_16 & ~top_8 & ~top_4 & top_2);
assign result[0] = (all_clear) |
(~|mantissa[26:2] & mantissa[1]) |
(~|mantissa[26:4] & mantissa[3]) |
(~|mantissa[26:6] & mantissa[5]) |
(~|mantissa[26:8] & mantissa[7]) |
(~|mantissa[26:10] & mantissa[9]) |
(~|mantissa[26:12] & mantissa[11]) |
(~|mantissa[26:14] & mantissa[13]) |
(~|mantissa[26:16] & mantissa[15]) |
(~|mantissa[26:18] & mantissa[17]) |
(~|mantissa[26:20] & mantissa[19]) |
(~|mantissa[26:22] & mantissa[21]) |
(~|mantissa[26:24] & mantissa[23]) |
(~mantissa[26] & mantissa[25]);
assign all_zero = all_clear;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { map<char, int> ma; int p; char a, k[1000]; cin >> p; for (int i = 0; i < p; i++) { cin >> k[i]; a = tolower(k[i]); ma[a]++; } if (ma.size() == 26) cout << YES << endl; else cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, pos, l, r; cin >> n >> pos >> l >> r; if (pos > r) { if (l - 1 == 0) { cout << 0 + pos - r + 1; } else { cout << pos - r + 1 + r - l + 1; } } else if (pos < l) { if (n == r) { cout << l - pos + 1; } else { cout << l - pos + 1 + r - l + 1; } } else { int x1 = pos - l; int x2 = r - pos; int min; if (x1 < x2) min = x1; else min = x2; int t1, t2; if (l == 1) t1 = 0; else t1 = x1 + 1; if (r == n) t2 = 0; else t2 = x2 + 1; if (t1 != 0 && t2 != 0) { cout << t1 + t2 + min; } else { cout << t1 + t2; } } cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 2; const int INF = 1e9 + 1; const double EPS = 1e-9; int n, m; int a[MAXN]; int r[MAXN], t[MAXN]; int b[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> a[i]; } int it = 0; for (int i = 0; i < m; ++i) { int ct, crt; cin >> ct >> crt; while (it > 0 && crt >= r[it - 1]) --it; t[it] = ct; r[it++] = crt; } r[it] = 0; int bl = 0, br = r[0]; for (int i = 0; i < br; ++i) { b[i] = a[i]; } sort(b, b + br); for (int i = 1; i < it + 1; ++i) { for (int j = r[i - 1]; j > r[i]; --j) { if (t[i - 1] == 1) { a[j - 1] = b[--br]; } else a[j - 1] = b[bl++]; } } for (int i = 0; i < n; ++i) { cout << a[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (int &elem : a) cin >> elem; vector<vector<int>> dp(n, vector<int>(2, -1)); function<int(int, int)> solve = [&](int idx, int turn) -> int { if (idx >= n) { return 0; } if (dp[idx][turn] != -1) return dp[idx][turn]; int ans = INT_MAX; if (turn == 1) { if (a[idx] == 1) { ans = min(ans, 1 + solve(idx + 1, 0)); if (idx + 1 < n && a[idx + 1] == 1) { ans = min(ans, 2 + solve(idx + 2, 0)); } else { ans = min(ans, 1 + solve(idx + 2, 0)); } } else { ans = min(ans, solve(idx + 1, 0)); if (idx + 1 < n) ans = min(ans, (a[idx + 1] == 1) + solve(idx + 2, 0)); } } else { ans = min(ans, solve(idx + 1, 1)); ans = min(ans, solve(idx + 2, 1)); } return dp[idx][turn] = ans; }; cout << solve(0, 1) << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INVLP_PP_BLACKBOX_V
/**
* invlp: Low Power Inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, x, y, z; cin >> a >> b >> c >> x >> y >> z; int rest = 0, my = 0; a -= x; b -= y; c -= z; if (a > 0) my += (a / 2); else rest += -a; if (b > 0) my += (b / 2); else rest += -b; if (c > 0) my += (c / 2); else rest += -c; if (my >= rest) cout << YES << endl; else cout << NO << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_1_V
`define SKY130_FD_SC_LP__FAHCIN_1_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog wrapper for fahcin with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fahcin.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_1_V
|
/*
* Titor - System - Miscellaneous debounce circuitry
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Debounce
`else
`define INC_Debounce
`timescale 1 ns / 100 ps
// Sean Moore
module Debounce(
lineout,
linein,
reset,
clk
);
parameter TIME = 0;
`include "definition/Definition.v"
output reg lineout;
input linein;
input clk;
input reset;
reg [WORD-1:0] count;
reg lineina;
reg lineinb;
wire toggle;
assign toggle = lineina ^^ lineinb;
always @(posedge clk) begin
if(reset) count <= 0;
else if(!toggle)
if(count!=TIME) count <= count+1;
else count <= count;
else count <= 0;
end
always @(posedge clk) begin
if(reset) lineout <= lineinb;
else if((count==TIME) && !toggle) lineout <= lineinb;
else lineout <= lineout;
end
always @(posedge clk) begin
lineina <= linein;
lineinb <= lineina;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_request_generator #(
parameter ID_WIDTH = 3,
parameter BURSTS_PER_TRANSFER_WIDTH = 17)(
input clk,
input resetn,
output [ID_WIDTH-1:0] request_id,
input [ID_WIDTH-1:0] response_id,
input rewind_req_valid,
input [ID_WIDTH+3-1:0] rewind_req_data,
output rewind_state,
output abort_req,
output reg completion_req_valid = 1'b0,
output completion_req_last,
output [1:0] completion_transfer_id,
input req_valid,
output reg req_ready,
input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input req_xlast,
input enable,
output eot
);
`include "inc_id.vh"
localparam STATE_IDLE = 3'h0;
localparam STATE_GEN_ID = 3'h1;
localparam STATE_REWIND_ID = 3'h2;
localparam STATE_CONSUME = 3'h3;
localparam STATE_WAIT_LAST = 3'h4;
reg [2:0] state = STATE_IDLE;
reg [2:0] nx_state;
reg [1:0] rew_transfer_id = 1'b0;
reg rew_req_xlast;
reg [ID_WIDTH-1:0] rew_id = 'h0;
reg cur_transfer_id = 1'b0;
reg cur_req_xlast;
wire transfer_id_match;
reg nx_completion_req_valid;
/*
* Here we only need to count the number of bursts, which means we can ignore
* the lower bits of the byte count. The last last burst may not contain the
* maximum number of bytes, but the address_generator and data_mover will take
* care that only the requested ammount of bytes is transfered.
*/
reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00;
reg [ID_WIDTH-1:0] id;
wire [ID_WIDTH-1:0] id_next = inc_id(id);
wire incr_en;
wire incr_id;
assign eot = burst_count == 'h00;
assign request_id = id;
assign incr_en = (response_id != id_next) && (enable == 1'b1);
assign incr_id = (state == STATE_GEN_ID) && (incr_en == 1'b1);
always @(posedge clk) begin
if (state == STATE_IDLE) begin
burst_count <= req_burst_count;
end else if (state == STATE_REWIND_ID) begin
burst_count <= cur_burst_length;
end else if (incr_id == 1'b1) begin
burst_count <= burst_count - 1'b1;
end
end
always @(posedge clk) begin
if (req_ready == 1'b1 & req_valid == 1'b1) begin
cur_req_xlast <= req_xlast;
cur_burst_length <= req_burst_count;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else if (state == STATE_REWIND_ID) begin
id <= rew_id;
end else if (incr_id == 1'b1) begin
id <= id_next;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
req_ready <= 1'b0;
end else begin
req_ready <= (nx_state == STATE_IDLE || nx_state == STATE_CONSUME);
end
end
assign transfer_id_match = cur_transfer_id == rew_transfer_id[0];
always @(posedge clk) begin
if (resetn == 1'b0) begin
cur_transfer_id <= 1'b0;
end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
cur_transfer_id <= ~cur_transfer_id;
end
end
/*
* Once rewind request is received we need to stop incrementing the burst ID.
*
* If the current segment matches the segment that was interrupted and
* if it was a last segment we ignore consecutive segments until the last
* segment is received, in other case we can jump to the next segment.
*
* If the current segment is newer than the one got interrupted and the
* interrupted one was a last segment we need to replay the current
* segment with the adjusted burst ID. If the interrupted segment was not last
* we need to consume/ignore all segments until a last segment is received.
*
* Completion requests are generated for every segment that is
* consumed/ignored. These are handled by the response_manager once the
* interrupted segment got transferred to the destination.
*/
always @(*) begin
nx_state = state;
nx_completion_req_valid = 0;
case (state)
STATE_IDLE: begin
if (rewind_req_valid == 1'b1) begin
nx_state = STATE_REWIND_ID;
end else if (req_valid == 1'b1) begin
nx_state = STATE_GEN_ID;
end
end
STATE_GEN_ID: begin
if (rewind_req_valid == 1'b1) begin
nx_state = STATE_REWIND_ID;
end else if (eot == 1'b1 && incr_en == 1'b1) begin
nx_state = STATE_IDLE;
end
end
STATE_REWIND_ID: begin
if (transfer_id_match) begin
if (rew_req_xlast) begin
nx_state = STATE_IDLE;
end else begin
nx_state = STATE_CONSUME;
end
end else begin
if (rew_req_xlast) begin
nx_state = STATE_GEN_ID;
end else if (cur_req_xlast) begin
nx_state = STATE_IDLE;
nx_completion_req_valid = 1;
end else begin
nx_state = STATE_CONSUME;
nx_completion_req_valid = 1;
end
end
end
STATE_CONSUME: begin
if (req_valid) begin
nx_completion_req_valid = 1;
nx_state = STATE_WAIT_LAST;
end
end
STATE_WAIT_LAST:begin
if (cur_req_xlast) begin
nx_state = STATE_IDLE;
end else begin
nx_state = STATE_CONSUME;
end
end
default: begin
nx_state = STATE_IDLE;
end
endcase
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
state <= STATE_IDLE;
end else begin
state <= nx_state;
end
end
always @(posedge clk) begin
if (rewind_req_valid == 1'b1) begin
{rew_transfer_id, rew_req_xlast, rew_id} <= rewind_req_data;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
completion_req_valid <= 1'b0;
end else begin
completion_req_valid <= nx_completion_req_valid;
end
end
assign completion_req_last = cur_req_xlast;
assign completion_transfer_id = rew_transfer_id;
assign rewind_state = (state == STATE_REWIND_ID);
assign abort_req = (state == STATE_REWIND_ID) && !rew_req_xlast && !cur_req_xlast;
endmodule
|
`define WIDTH 32
module cmd_module (loaded_data, size,addr_key,sign_ext,result,en,clk);
input [31:0] loaded_data;
input[1:0] size ;
input [1:0] addr_key;
input sign_ext;
input clk;
input en;
output [31:0] result;
reg [31:0] result;
wire addr_key_latched;
register addr_latch (addr_key,clk,1'b1,en,addr_key_latched);
load_data_translator instance1 (loaded_data,addr_key_latched,size,sign_ext,result);
endmodule
module register(d,clk,resetn,en,q);
//parameter WIDTH=32;
// this initialization of a register has WIDTH = 2
input clk;
input resetn;
input en;
input [1:0] d;
output [1:0] q;
reg [1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
module load_data_translator(
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult);
//parameter WIDTH=32;
input [`WIDTH-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [`WIDTH-1:0] d_loadresult;
wire d_adr_one;
assign d_adr_one = d_address [1];
reg [`WIDTH-1:0] d_loadresult;
reg sign;
always @(d_readdatain or d_address or load_size or load_sign_ext)
begin
case (load_size)
2'b11:
begin
case (d_address)
2'b00:
begin
d_loadresult[7:0]=d_readdatain[31:24];
sign = d_readdatain[31];
end
2'b01:
begin
d_loadresult[7:0]=d_readdatain[23:16];
sign = d_readdatain[23];
end
2'b10:
begin
d_loadresult[7:0]=d_readdatain[15:8];
sign = d_readdatain[15];
end
default:
begin
d_loadresult[7:0]=d_readdatain[7:0];
sign = d_readdatain[7];
end
endcase
// peter milankov note: do this by hand
// odin II does not support multiple concatenation
//d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
d_loadresult[15]= load_sign_ext&sign;
d_loadresult[14]= load_sign_ext&sign;
d_loadresult[13]= load_sign_ext&sign;
d_loadresult[12]= load_sign_ext&sign;
d_loadresult[11]= load_sign_ext&sign;
d_loadresult[10]= load_sign_ext&sign;
d_loadresult[9]= load_sign_ext&sign;
d_loadresult[8]= load_sign_ext&sign;
end
2'b01:
begin
case (d_adr_one)
1'b0:
begin
d_loadresult[15:0]=d_readdatain[31:16];
sign = d_readdatain[31];
end
default:
begin
d_loadresult[15:0]=d_readdatain[15:0];
sign = d_readdatain[15];
end
endcase
// peter milankov note sign extend is concat, do by hand
//d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
end
default:
begin
d_loadresult[31:0]=d_readdatain[31:0];
sign = d_readdatain [31];
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e6 + 7; const long double maxx = 1e11; int tmp[MAXN]; int main() { int n, k; cin >> n >> k; string s; cin >> s; k--; if (k >= n / 2) k = n - k - 1; int ans = 0, l = 0, r = 0; for (int i = 0, j = n - 1; i < j; i++, j--) { tmp[i] = min(abs(s[i] - s[j]), 26 - abs(s[i] - s[j])); } for (int i = 1; i <= n / 2; i++) tmp[i] += tmp[i - 1]; for (int i = 0; i < n / 2; i++) { if (tmp[i]) { l = i; break; } } for (int i = 0; i < n / 2; i++) if (tmp[i] == tmp[n / 2]) { r = i; break; } if (tmp[n / 2]) ans = tmp[n / 2] + min(abs(k - l), abs(k - r)) + abs(l - r); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; int ans = 0; int count = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == ) ) { ans--; if (ans < 0) { count++; ans = 0; } } else { ans++; } } cout << count << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5; int n, fa[maxn + 2], cont[maxn + 2]; int mx1[maxn + 2], mx2[maxn + 2], diameter[maxn + 2]; bool vist[maxn + 2]; vector<int> G[maxn + 2]; vector<long long> dist[maxn + 2]; map<pair<int, int>, double> Map; void dfs1(int x, int pre, int col) { vist[x] = 1, fa[x] = col; int aa[3]; for (auto nx : G[x]) { if (nx == pre) continue; dfs1(nx, x, col); aa[0] = mx1[nx] + 1, aa[1] = mx1[x], aa[2] = mx2[x]; sort(aa, aa + 3); mx1[x] = aa[2], mx2[x] = aa[1]; } } void dfs2(int x, int pre, vector<long long> &ds, int di) { ds.push_back(max(di, mx1[x])); for (auto nx : G[x]) { if (nx == pre) continue; if (mx1[nx] + 1 == mx1[x]) dfs2(nx, x, ds, max(di, mx2[x]) + 1); else dfs2(nx, x, ds, max(di, mx1[x]) + 1); } } int BinSearch(vector<long long> &arr, long long key) { int l = 1, r = arr.size() - 1, res = 0; while (l <= r) { int mid = (l + r) >> 1; if (arr[mid] - arr[mid - 1] < key) res = mid, l = mid + 1; else r = mid - 1; } return res; } int main() { int m, T, u, v; scanf( %d%d%d , &n, &m, &T); for (int i = 1; i <= n; ++i) fa[i] = i; for (int i = 1; i <= m; ++i) { scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= n; ++i) if (!vist[i]) { dfs1(i, 0, i); dfs2(i, 0, dist[i], 0); dist[i].push_back(0); sort(dist[i].begin(), dist[i].end()); diameter[i] = dist[i][dist[i].size() - 1]; for (int k = 1; k < dist[i].size(); ++k) dist[i][k] += dist[i][k - 1]; } while (T--) { scanf( %d%d , &u, &v); u = fa[u], v = fa[v]; if (u == v) { printf( %d n , -1); continue; } if (Map.count(make_pair(u, v))) { printf( %f n , Map[make_pair(u, v)]); continue; } if (dist[u].size() > dist[v].size()) swap(u, v); long long mxd = max(diameter[u], diameter[v]), sum = 0; for (int i = 1; i < dist[u].size(); ++i) { int index = BinSearch(dist[v], mxd - (dist[u][i] - dist[u][i - 1]) - 1); sum += (dist[v][dist[v].size() - 1] - dist[v][index]); sum += (dist[u][i] - dist[u][i - 1] + 1) * (dist[v].size() - 1 - index); sum += mxd * index; } double ans = double(sum) / (dist[u].size() - 1) / (dist[v].size() - 1); Map[make_pair(u, v)] = Map[make_pair(v, u)] = ans; printf( %.10f n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 6001; int n, m, k, a, b, x[N], y[N], z[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &x[i]); scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d , &y[i]); scanf( %d , &k); for (int i = 1; i <= k; i++) scanf( %d , &z[i]); scanf( %d%d , &a, &b); sort(x + 1, x + 1 + n); sort(y + 1, y + 1 + m); sort(z + 1, z + 1 + k); double p2 = z[1]; double r1 = x[n]; double res = 0; for (int i = 1; i <= m; i++) { double p1 = y[i]; double cur = (p1 * b * r1 * r1) / (p1 * b + p2 * a); cur = sqrt(cur); if (cur - res > 1e-6) res = cur; } printf( %.7f n , res); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_7_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_7_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_7_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_7_e
//
// No `defines in this module
module inst_7_e
//
// Generated Module inst_7
//
(
);
// Module parameters:
parameter FOO = 34;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_7_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V |
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931283423456;
wire exception_139931284928272;
wire exception_139931283803816;
wire exception_139931284095848;
wire exception_139931280770256;
wire exception_139931284093984;
wire exception_139931280674968;
wire exception_139931282495824;
wire exception_139931280736200;
wire exception_139931283075512;
wire exception_139931279485624;
wire exception_139931283398456;
wire exception_139931279088024;
wire exception_139931282371216;
wire exception_139931278433672;
wire exception_139931280813376;
main_0 main_0_139931283423456(
.clk(clk),
.rst(rst),
.exception(exception_139931283423456),
.input_ps2(input_ps2),
.input_ps2_stb(input_ps2_stb),
.input_ps2_ack(input_ps2_ack),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack));
main_1 main_1_139931284928272(
.clk(clk),
.rst(rst),
.exception(exception_139931284928272),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931283803816(
.clk(clk),
.rst(rst),
.exception(exception_139931283803816),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_3 main_3_139931284095848(
.clk(clk),
.rst(rst),
.exception(exception_139931284095848),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_4 main_4_139931280770256(
.clk(clk),
.rst(rst),
.exception(exception_139931280770256),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_5 main_5_139931284093984(
.clk(clk),
.rst(rst),
.exception(exception_139931284093984),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_6 main_6_139931280674968(
.clk(clk),
.rst(rst),
.exception(exception_139931280674968),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_7 main_7_139931282495824(
.clk(clk),
.rst(rst),
.exception(exception_139931282495824),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_8 main_8_139931280736200(
.clk(clk),
.rst(rst),
.exception(exception_139931280736200),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_9 main_9_139931283075512(
.clk(clk),
.rst(rst),
.exception(exception_139931283075512),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_10 main_10_139931279485624(
.clk(clk),
.rst(rst),
.exception(exception_139931279485624),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_11 main_11_139931283398456(
.clk(clk),
.rst(rst),
.exception(exception_139931283398456),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_12 main_12_139931279088024(
.clk(clk),
.rst(rst),
.exception(exception_139931279088024),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_13 main_13_139931282371216(
.clk(clk),
.rst(rst),
.exception(exception_139931282371216),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_14 main_14_139931278433672(
.clk(clk),
.rst(rst),
.exception(exception_139931278433672),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_15 main_15_139931280813376(
.clk(clk),
.rst(rst),
.exception(exception_139931280813376),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931283423456 || exception_139931284928272 || exception_139931283803816 || exception_139931284095848 || exception_139931280770256 || exception_139931284093984 || exception_139931280674968 || exception_139931282495824 || exception_139931280736200 || exception_139931283075512 || exception_139931279485624 || exception_139931283398456 || exception_139931279088024 || exception_139931282371216 || exception_139931278433672 || exception_139931280813376;
endmodule
|
module control_unit(input clock);
wire[31:0] instruction_data;
wire[2:0] control_store_address;
wire[4:0] control_store_data;
wire output_enable;
wire[3:0] opcode;
wire input_type_1;
wire[1:0] input_register_selector_1;
wire[7:0] input_immediate_1;
wire input_type_2;
wire[1:0] input_register_selector_2;
wire[7:0] input_immediate_2;
wire[1:0] wire_register_selector;
wire[1:0] output_register_selector;
wire[1:0] alu_opcode;
wire next_address;
instruction_decoder id(instruction_data, opcode,
input_type_1, input_register_selector_1,
input_immediate_1,
input_type_2, input_register_selector_2,
input_immediate_2,
output_register_selector);
microsequencer useq(clock, opcode, next_address,
control_store_address);
control_store cs(control_store_address, control_store_data);
microinstruction_decoder uid(control_store_data,
output_enable, output_source_selector,
alu_opcode, next_address);
data_path dp(input_register_selector_1,
input_register_selector_2,
output_register_selector,
output_source_selector, output_enable,
alu_opcode, ir_immediate_1, ir_immediate_2,
instruction_data);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(long long y) { for (long long x = 2; x * x <= y; x++) { if (y % x == 0) return 0; } return 1; } int main() { std::cin.tie(0); std::ios::sync_with_stdio(false); long long n, x, y; cin >> n; for (int i = 0; i < n; i++) { cin >> y >> x; if (y - x == 1 && check(x + y)) { cout << Yes << endl; } else { cout << No << endl; } } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-115 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_115 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; long long res = 0; cin >> n; vector<bool> v(6000, false); for (int i = 0; i < n; ++i) { cin >> k; if (!v[k - 1]) v[k - 1] = true; else while (v[k - 1]) { ++res; ++k; v[k - 2] = true; } v[k - 1] = true; } cout << res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Whitening function of main datapath for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, ////
//// - Younjoo Kim, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module WF(
i_op ,
i_wf_in ,
i_wk ,
o_wf_out
);
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
input i_op ;
input[63:0] i_wf_in ;
input[31:0] i_wk ;
output[63:0] o_wf_out ;
//=====================================
//
// REGISTERS
//
//=====================================
//=====================================
//
// WIRES
//
//=====================================
// w_wf_out
wire[63:0] w_wf_out ;
// w_rf_out(7:0)
wire[7:0] w_wf_out7 ;
wire[7:0] w_wf_out6 ;
wire[7:0] w_wf_out5 ;
wire[7:0] w_wf_out4 ;
wire[7:0] w_wf_out3 ;
wire[7:0] w_wf_out2 ;
wire[7:0] w_wf_out1 ;
wire[7:0] w_wf_out0 ;
//=====================================
//
// MAIN
//
//=====================================
assign w_wf_out7 = i_wf_in[63:56];
assign w_wf_out6 = i_wf_in[55:48] ^ i_wk[31:24];
assign w_wf_out5 = i_wf_in[47:40];
assign w_wf_out4 = (i_op == 0) ? (i_wf_in[39:32] + i_wk[23:16]) :
(i_wf_in[39:32] - i_wk[23:16]) ;
assign w_wf_out3 = i_wf_in[31:24];
assign w_wf_out2 = i_wf_in[23:16] ^ i_wk[15:8];
assign w_wf_out1 = i_wf_in[15:8];
assign w_wf_out0 = (i_op == 0) ? (i_wf_in[7:0] + i_wk[7:0]) :
(i_wf_in[7:0] - i_wk[7:0]) ;
assign w_wf_out = {w_wf_out7, w_wf_out6, w_wf_out5, w_wf_out4, w_wf_out3, w_wf_out2, w_wf_out1, w_wf_out0};
assign o_wf_out = w_wf_out;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const int MAX = 47 + 5; const long long MAX2 = 11; const long long MOD = 1000000007; const long long MOD2 = 1000005329; const long long INF = 2e18; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1, 0}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1, 0}; const double pi = acos(-1); const double EPS = 1e-9; const int block = 555; int n, x[MAX], sm, k, tmp; long long dp[MAX][MAX][MAX], fr[MAX]; double ans, res; long long f(int nw, int rem, int cnt) { if (rem == 0) return cnt == 0; if (cnt < 0 || nw > n) return 0; long long &ret = dp[nw][rem][cnt]; if (ret != -1) return ret; ret = f(nw + 1, rem, cnt); if (x[nw] <= rem) ret += f(nw + 1, rem - x[nw], cnt - 1); return ret; } int main() { cout << fixed << setprecision(10); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; ++i) cin >> x[i], sm += x[i]; cin >> k; if (k >= sm) return cout << n << n , 0; for (int i = 1; i <= n; ++i) { tmp = x[i]; x[i] = 100; memset(dp, -1, sizeof dp); for (int j = max(1, k - tmp + 1); j <= k; ++j) for (int o = 1; o <= n; ++o) fr[o] += f(1, j, o); x[i] = tmp; } for (int i = 1; i <= n; ++i) { res = fr[i] * i; for (int j = i + 1; j < n; ++j) res /= j, res *= n - j; res /= n; ans += res; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> int main() { int n, amount(0); scanf( %d , &n); bool b[3001] = {false}; int pfactors[3001] = {0}; for (int i = 2; i <= n; ++i) { if (!b[i]) { for (int j = i + i; j <= n; j += i) { b[j] = true; pfactors[j] += 1; } } if (pfactors[i] == 2) { amount += 1; } } printf( %d n , amount); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; const long long INF = 1e7; signed main() { cin.tie(0), ios_base::sync_with_stdio(false); ; long long n, s; cin >> n >> s; vector<long long> arr(n); long long su = 0, mi = 1e18; for (long long i = 0; i < n; ++i) { cin >> arr[i]; su += arr[i]; if (mi > arr[i]) { mi = arr[i]; } } su -= s; if (su < 0) { cout << -1; return 0; } cout << min(su / n, mi); return 0; } |
/* anshu shandilya */ /* 2300 codechef rating before 31 December 2020 */ /* 2100 codeforces rating before 31 December 2020 */ #include <bits/stdc++.h> using namespace std; typedef long double LD; typedef long long ll; #define int ll #define itn int #define pb push_back #define mp make_pair #define REP(i,n) for (int i = 0; i < n; i++) #define FOR(i,a,b) for (int i = a; i < b; i++) #define REPD(i,n) for (int i = n-1; i >= 0; i--) #define FORD(i,a,b) for (int i = a; i >= b; i--) #define remax(a,b) a = max(a,b) #define remin(a,b) a = min(a,b) #define all(v) v.begin(),v.end() #define rev(v) v.begin(),v.end(),greater<int>() typedef map<int,int> mii; typedef vector<int> vi; typedef vector<ll> vl; typedef vector<vi> vvi; typedef pair<int,int> pii; typedef vector<pii> vpii; #define ff first #define ss second #define pq(type) priority_queue<type> #define PQD(type) priority_queue<type,vector<type>,greater<type> > #define wt(t) while(t --) #define SZ(x) ((int)(x).size()) #define runtime() ((double)clock() / CLOCKS_PER_SEC) #define inrange(i,a,b) ((i>=min(a,b)) && (i<=max(a,b))) #define FAST_IO ios_base::sync_with_stdio(false);cin.tie(NULL); const int MAXN = 1000005; const int SQRTN = 1003; const int LOGN = 22; const double PI=acos(-1); #ifdef int const int INF=1e16; #else const int INF=1e9; #endif const int MOD = 1000000007; const int FMOD = 998244353; const double eps = 1e-9; /************************** finding a number is prime or not and smallest prime factor of any number *******************************/ bool primes[100001]; int spf[100001]; void sieve() { primes[0]=primes[1]=false; for(int i=1;i<=100000;i++) { spf[i]=i; primes[i]=true; } spf[2]=2; for(int i=4;i<=100000;i+=2) { spf[i]=2; primes[i]=false; } for(int i=3;i*i<=100000;i+=2) { if(spf[i]==i) { for(int j=i*i;j<=100000;j+=i) { if(spf[j]==j) spf[j]=i; primes[j]=false; } } } return ; } /******************************************** code ends *******************************************************************/ /********************************************* modulo exponentation *****************************************************/ int power(int n, int m,int p) { int res=1; n=n%MOD; while(m>0) { if(m&1) { res=((res)%p*(n)%p)%p; m--; } n=((n)%p*(n)%p)%p; m>>=1; } return res; } /************************************************ code ends *************************************************************/ /********************************* NcR MOD P in O(1) for queires type probs ******************************************/ int N=10000; int factorialNumInverse [100001]; int naturalNumInverse[100001]; int fact[100001]; void InverseofNumber(ll p) { naturalNumInverse[0] = naturalNumInverse[1] = 1; for (int i = 2; i <= N; i++) naturalNumInverse[i] = naturalNumInverse[p % i] * (p - p / i) % p; } void InverseofFactorial(ll p) { factorialNumInverse[0] = factorialNumInverse[1] = 1; for (int i = 2; i <= N; i++) factorialNumInverse[i] = (naturalNumInverse[i] * factorialNumInverse[i - 1]) % p; } void factorial(ll p) { fact[0] = 1; for (int i = 1; i <= N; i++) { fact[i] = (fact[i - 1] * i) % p; } } int Binomial(int N, int R, int p) { int ans = ((fact[N] * factorialNumInverse[R]) % p * factorialNumInverse[N - R]) % p; return ans; } /********************************** CODE ENDS ******************************************************************************/ /*********************************** NcR MOD p using FERMAT S THEOREM IN O(LOGY) ******************************************/ int modInverse(int n,int p) { return power(n, p - 2, p); } int nCrModPFermat(int n,int r, int p) { if (n < r) return 0; if (r == 0) return 1; int fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } /**************************************** CODE ENDS ***********************************************************************/ void solvethetestcase(); signed main() { FAST_IO //sieve(); int t = 1; cin >> t; FOR(testcase,1,t+1){ // printf( Case #%lld: ,testcase); solvethetestcase(); } } int n,m,a,b,c,x,zero,p,t1,t2,t,q,cnt; /********************************************* REAL CODE STARTS **********************************************************/ void solvethetestcase(){ cin>>x; set<int>st; string s= 123456789 ; n=s.length(); vi vec,ans; int sz=INT_MAX; string s1,res= ; for(int i=0;i<pow(2,n);i++) { int sum=0; vec.clear(); s1= ; for(int j=0;j<n;j++) { if(i&(1<<j)) { sum+=s[j]- 0 ; s1+=s[j]; } } if(sum==x) { if(res== ) res=s1; else if(s1.compare(res)) res=s1; } } if(res.length()>0) { cout<<res; } else cout<<-1; cout<< n ; } /************************************************ CODE ENDS ***************************************************************/ |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:15:57 06/13/2016
// Design Name:
// Module Name: LZD_4bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_4bit( in, out, valid
);
input [3:0]in;
output reg [1:0]out;
output reg valid;
wire v1,v2, l1, l2; // wire is used to pass data
initial
begin // initializing values to zero
out<=2'b00;
valid<=0;
end
LZD_2bit d1( .in(in[1:0]), .out(l1), .valid(v1)); // instantiating LDZ_2bit
LZD_2bit d2( .in(in[3:2]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2) // logic is carried out when ever change in input, v1,v2,l1,l2 occurs
begin
if(v2==0&& v1==1)
begin
out<={{~v2},{l1}} ;
end
/* condition
when v2=0
v2 is 0 => l2= 0
in that case we see for v1
if v1=0 => l1= 0
we get out=0, valid=0
if v1=1 => l1= x
we take ~v2 in 2^1 position and l1 in 2^0 position to get no of leading zero terms
eg- 0011 we should get 2 as output
here v2= 0, l2=0, v1=1, l1=0
out= {{~(0),{0}}
out= {1,0}= 2'b10= 2 in decimal
there are 2 leading zeros in 0011
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*if v2=1 we dont consider values from v1 so we take
~v2 in 2^1 position and l2 in 2^0 position
so that we get accurate no of leading zero's
eg- 0101 we should get 1 as output
here v2=1, l2= 1, v1=1, l1=1
out={~{1},{1}}= {0,1}=2'b01= 1
there is one leading zero in 0101
*/
valid<= v1|v2; // valid= in[3]|in[2]|in[1]|in[0]
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100, M = 52 + 10, LG = 30, base = 2; const int MOD = 1e9 + 7, mod = 1e9 + 9; const long long INF = 1e9, inf = 1e18; long long p, q, m, k; string w, s, t; vector<long long> a, b; vector<long long> ans; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; cin >> w >> s >> t; while (p = w.find(s, p) + 1) a.push_back(p); while (q = w.find(t, q) + 1) b.push_back(q); for (int i = 0; i < a.size(); i++) { m = 0, k = 0; for (int j = a[i]; j <= w.size(); j++) { while (k < b.size() && b[k] < j) k++; if (k < b.size() && b[k] == j && j + t.size() >= a[i] + s.size()) ans.push_back(m); m = m * mod + (w[j - 1] - a + 1); } } sort(ans.begin(), ans.end()); cout << unique(ans.begin(), ans.end()) - ans.begin(); return 0; } |
#include <bits/stdc++.h> using namespace std; //#pragma GCC optimize( Ofast ) //#pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #define ms(s, n) memset(s, n, sizeof(s)) #define FOR(i, a, b) for (int i = (a); i < (b); ++i) #define FORd(i, a, b) for (int i = (a) - 1; i >= (b); --i) #define FORall(it, a) for (__typeof((a).begin()) it = (a).begin(); it != (a).end(); it++) #define sz(a) int((a).size()) #define present(t, x) (t.find(x) != t.end()) #define all(a) (a).begin(), (a).end() #define uni(a) (a).erase(unique(all(a)), (a).end()) #define pb push_back #define pf push_front #define mp make_pair #define fi first #define se second #define prec(n) fixed<<setprecision(n) #define bit(n, i) (((n) >> (i)) & 1) #define bitcount(n) __builtin_popcountll(n) typedef long long ll; typedef unsigned long long ull; typedef long double ld; typedef pair<int, int> pi; typedef vector<int> vi; typedef vector<pi> vii; const int MOD = (int) 1e9 + 7; const int FFTMOD = 119 << 23 | 1; const int INF = (int) 1e9 + 23111992; const ll LINF = (ll) 1e18 + 23111992; const ld PI = acos((ld) -1); const ld EPS = 1e-9; inline ll gcd(ll a, ll b) {ll r; while (b) {r = a % b; a = b; b = r;} return a;} inline ll lcm(ll a, ll b) {return a / gcd(a, b) * b;} inline ll fpow(ll n, ll k, int p = MOD) {ll r = 1; for (; k; k >>= 1) {if (k & 1) r = r * n % p; n = n * n % p;} return r;} template<class T> inline int chkmin(T& a, const T& val) {return val < a ? a = val, 1 : 0;} template<class T> inline int chkmax(T& a, const T& val) {return a < val ? a = val, 1 : 0;} inline ull isqrt(ull k) {ull r = sqrt(k) + 1; while (r * r > k) r--; return r;} inline ll icbrt(ll k) {ll r = cbrt(k) + 1; while (r * r * r > k) r--; return r;} inline void addmod(int& a, int val, int p = MOD) {if ((a = (a + val)) >= p) a -= p;} inline void submod(int& a, int val, int p = MOD) {if ((a = (a - val)) < 0) a += p;} inline int mult(int a, int b, int p = MOD) {return (ll) a * b % p;} inline int inv(int a, int p = MOD) {return fpow(a, p - 2, p);} inline int sign(ld x) {return x < -EPS ? -1 : x > +EPS;} inline int sign(ld x, ld y) {return sign(x - y);} mt19937 mt(chrono::high_resolution_clock::now().time_since_epoch().count()); inline int mrand() {return abs((int) mt());} inline int mrand(int k) {return abs((int) mt()) % k;} #define db(x) cerr << [ << #x << : << (x) << ] ; #define endln cerr << n ; void chemthan() { int n; cin >> n; vi a(n); vi b(n); FOR(i, 0, n) cin >> a[i]; FOR(i, 0, n) cin >> b[i]; long long sum = 0; FOR(i, 0, n) sum += abs(a[i] - b[i]); auto func = [&] (int sa, int sb) { long long res = sum; vi dc; FOR(i, 0, n) dc.pb(sb * a[i]), dc.pb(sb * b[i]); sort(all(dc)), uni(dc); vector<long long> fen(sz(dc) + 1, LINF); auto upd = [&] (int p, long long v) { p++; for (; p < sz(fen); p += p & -p) { chkmin(fen[p], v); } }; auto query = [&] (int p) { p++; long long res = LINF; for (; 0 < p; p -= p & -p) { chkmin(res, fen[p]); } return res; }; vector<tuple<int, int, int>> v; FOR(i, 0, n) { v.pb({sa * a[i], sb * b[i], 1}); v.pb({sa * b[i], sb * a[i], 0}); } sort(all(v)); for (auto [x, y, t] : v) { int k = lower_bound(all(dc), y) - dc.begin(); if (!t) { upd(k, (long long) - x - y - abs(sa * x - sb * y)); } else { chkmin(res, sum + x + y + query(k) - abs(sa * x - sb * y)); } } return res; }; long long res = sum; for (int sa : {-1, 1}) { for (int sb : {-1, 1}) { chkmin(res, func(sa, sb)); } } cout << res << n ; } int32_t main(int32_t argc, char* argv[]) { ios_base::sync_with_stdio(0), cin.tie(0); if (argc > 1) { assert(freopen(argv[1], r , stdin)); } if (argc > 2) { assert(freopen(argv[2], wb , stdout)); } chemthan(); cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[4000005], t[4000005]; long long ans, now; int k; template <class T> inline T Max(T a, T b) { return a > b ? a : b; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i); int fu = 0, zh = 0; for (int i = 1; i <= n; ++i) { int qwq = a[i] - i; now += qwq < 0 ? -qwq : qwq; if (i == n) continue; if (qwq <= 0) ++fu; else ++t[a[i] - i], ++zh; } ans = now; int las = n; for (int i = 1; i < n; ++i) { now += -zh + fu - (n - a[las]) + a[las] - 1; fu += t[i]; zh -= t[i]; if (a[las] != 1) --fu, ++zh; ++t[i + a[las] - 1]; if (now < ans) ans = now, k = i; --las; } printf( %lld %d n , ans, k); return 0; } |
#include <bits/stdc++.h> const int N = 1e2 + 9; using namespace std; int n, m; int mp[N][N]; int main() { scanf( %d%d , &n, &m); puts( YES ); memset(mp, 0, sizeof mp); if (m <= n - 2) { int mid = (n + 1) / 2; if (m & 1) { mp[2][mid] = 1; } for (int i = 1; i <= m / 2; i++) { mp[2][mid - i] = mp[2][mid + i] = 1; } } else { for (int i = 2; i < n; i++) { mp[2][i] = 1; } m -= n - 2; int mid = (n + 1) / 2; if (m & 1) { mp[3][mid] = 1; } for (int i = 1; i <= m / 2; i++) { mp[3][mid - i] = mp[3][mid + i] = 1; } } for (int i = 1; i <= 4; i++) { for (int j = 1; j <= n; j++) { if (mp[i][j] == 1) printf( # ); else printf( . ); } puts( ); } } |
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: TAMUQ University
// Engineer: Ali Aljaani
// AXI IP core to communicate with the 128x32 OLED screen on the Zedboard
//
// Create Date: 06:11:22 08/18/2014
// Module Name: ZedboardOLED_v1_0
// Project Name: ZedboardOLED
// Target Devices: Zynq
// Tool versions: Vivado 14.2 (64-bits)
// Description: top-level wrapper for the AXI-lite IP core,
//
// Revision: 1.0 - ZedboardOLED_v1_0 completed
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module ZedboardOLED_v1_0 #
(
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Interface with the SSD1306 starts here
output wire SDIN,
output wire SCLK,
output wire DC,
output wire RES,
output wire VBAT,
output wire VDD,
// Interface with the SSD1306 ends here
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ZedboardOLED_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ZedboardOLED_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.SDIN(SDIN),
.SCLK(SCLK),
.DC(DC),
.RES(RES),
.VBAT(VBAT),
.VDD(VDD),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dx[] = {0, 1, 0, -1}; const int dy[] = {1, 0, -1, 0}; inline int mod(int n) { return (n % 1000000007); } int gcd(int a, int b) { if (a == 0 || b == 0) return 0; if (b == 1) return b; else return gcd(b, a % b); } int fpow(int x, unsigned int y, int p) { int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, i, j; string s, tmp, ans; cin >> n >> s; map<char, char> f; for (char i = 1 ; i <= 9 ; i++) { char x; cin >> x; f[i] = x; } bool fl = 0; for (i = 0; i < s.size(); i++) { if (f[s[i]] == s[i]) continue; if (f[s[i]] > s[i]) { s[i] = f[s[i]]; fl = 1; } else if (fl) break; } cout << s << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_TB_V
|
`timescale 1 ps / 1 ps
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
#include <bits/stdc++.h> using namespace std; int main() { char str[10000]; cin >> str; if (str[0] >= a && str[0] <= z ) str[0] = str[0] - 32; cout << str; return 0; } |
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; int main() { int arr[12], k, c = 0, a = 0; cin >> k; for (int i = 0; i < 12; i++) { cin >> arr[i]; } sort(arr, arr + 12); for (int i = 11; i >= 0; i--) { if (c < k) { c += arr[i]; a++; } } if (c < k) cout << -1 ; else cout << a; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int m[] = {6, 2, 5, 5, 4, 5, 6, 3, 7, 6}; long a, b; cin >> a; cin >> b; int count = 0; int i; long x; do { x = a; while (x >= 10) { i = x % 10; count += m[i]; x /= 10; } count += m[x]; a++; } while (a <= b); cout << count; return 0; } |
/*
* high_counter_tb.v: Testbench for high_counter.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
module high_counter_tb ();
reg clk;
reg rst;
wire [31:0] count;
integer pass_count;
integer fail_count;
/* change according to the number of test cases */
localparam total = 3;
integer clk_period;
high_counter dut (
.clk(clk),
.rst(rst),
.count(count));
initial begin
$dumpfile("high_counter_tb.vcd");
$dumpvars(0, high_counter_tb);
rst = 0;
clk = 0;
clk_period = 10;
pass_count = 0;
fail_count = 0;
#10;
rst = 1;
#10;
if (count === 0) begin
$display("PASSED: rst");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rst");
fail_count = fail_count + 1;
end
rst = 0;
#`WAIT_INTERVAL
if (count == (`WAIT_INTERVAL / clk_period)) begin
$display("PASSED: correct count");
pass_count = pass_count + 1;
end else begin
$display("FAILED: correct count");
fail_count = fail_count + 1;
end
rst = 1;
#10;
clk_period = 100;
clk = 0;
rst = 0;
#`WAIT_INTERVAL
if (count == (`WAIT_INTERVAL / clk_period)) begin
$display("PASSED: correct count after changing clk");
pass_count = pass_count + 1;
end else begin
$display("FAILED: correct count after changing clk");
fail_count = fail_count + 1;
end
if (pass_count + fail_count == total) begin
$display("PASSED: correct number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: correct number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(clk_period / 2) clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000010], t[1000010]; int ls, lt; int sum[1000010][3][3]; int main() { scanf( %s%s , s + 1, t + 1); ls = strlen(s + 1); lt = strlen(t + 1); if (ls > lt) { swap(ls, lt); swap(s, t); } for (int i = 1; i <= ls; ++i) { if (s[i] == R ) s[i] = 0; if (s[i] == G ) s[i] = 1; if (s[i] == B ) s[i] = 2; } for (int i = 1; i <= lt; ++i) { if (t[i] == R ) t[i] = 0; if (t[i] == G ) t[i] = 1; if (t[i] == B ) t[i] = 2; } long long ans = 0; int l = 1, r = 1; while (r < lt && t[r] != s[1]) { ++r; for (int j1 = 0; j1 < 3; ++j1) for (int j2 = 0; j2 < 3; ++j2) sum[r][j1][j2] = sum[r - 1][j1][j2]; ++sum[r][t[r - 1]][t[r]]; } for (int i = 1; i <= ls; ++i) { while (r < lt && t[r] != s[i]) { ++r; for (int j1 = 0; j1 < 3; ++j1) for (int j2 = 0; j2 < 3; ++j2) sum[r][j1][j2] = sum[r - 1][j1][j2]; ++sum[r][t[r - 1]][t[r]]; } ans += r - l + 1; if (s[i] != s[i - 1]) ans -= sum[r][s[i]][s[i - 1]] - sum[l - 1][s[i]][s[i - 1]]; if (s[i] == t[l]) ++l; if (r < lt) { ++r; for (int j1 = 0; j1 < 3; ++j1) for (int j2 = 0; j2 < 3; ++j2) sum[r][j1][j2] = sum[r - 1][j1][j2]; ++sum[r][t[r - 1]][t[r]]; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void DBG() { cerr << ] << n ; } template <class H, class... T> void DBG(H h, T... t) { cerr << h; if (sizeof...(t)) cerr << , ; DBG(t...); } template <class H> void DBG(vector<H> v) { for (int i = 0; i < (int)v.size(); i++) { cerr << v[i]; if (i != (int)v.size() - 1) cerr << , ; } cerr << ] << n ; } long long randNum(long long a, long long b) { return a + rand() % (b - a + 1); } long long mPow(long long b, long long p, long long m) { b %= m; long long result = 1; while (p > 0) { if (p & 1) result = (result * b) % m; b = (b * b) % m; p >>= 1; } return result; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long modInverse(long long b, long long m) { long long x, y; long long g = gcdExtended(b, m, &x, &y); if (g != 1) return -1; return (x % m + m) % m; } long long modDivide(long long a, long long b, long long m) { a = a % m; long long inv = modInverse(b, m); if (inv == -1) return -1; else return (inv * a) % m; } unsigned long long nCrModPFermat(unsigned long long n, int r, int p) { if (n < (unsigned long long)r) return 0; if (r == 0) return 1; unsigned long long fac[n + 1]; fac[0] = 1; for (unsigned long long i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } bool sortfunc(pair<int, int> a, pair<int, int> b) { return a.first < b.first; } long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } const int dx4[4] = {-1, 0, 1, 0}, dy4[4] = {0, -1, 0, 1}; const int dx8[8] = {-1, -1, -1, 0, 0, 1, 1, 1}, dy8[8] = {0, 1, -1, -1, 1, 0, 1, -1}; void solve() { vector<string> s; int n, m; cin >> n >> m; string temp; vector<int> cnt(m, 0); for (int i = 0; i < n; i++) { cin >> temp; for (int j = 0; j < m; j++) { if (temp[j] == 1 ) { cnt[j]++; } } s.push_back(temp); } for (int i = 0; i < n; i++) { bool flag = true; for (int j = 0; j < m; j++) { if (s[i][j] == 0 and cnt[j] == 0) { flag = false; break; } if (s[i][j] == 1 and cnt[j] - 1 == 0) { flag = false; break; } } if (flag) { cout << YES << n ; return; } } cout << NO << n ; } signed main() { ios::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 2012; int f[N][N][2]; int n, m, k, flag; int ex, ey; inline int find(int x, int y, int p) { if (y < 0) return y; return f[x][y][p] == y ? y : f[x][y][p] = find(x, f[x][y][p], p); } int dis(int x, int y) { return abs(ex - x) + abs(ey - y); } inline void chk(int &ans, int nx, int ny, int &x, int &y) { int d = dis(nx, ny); if (d < ans) { ans = d, x = nx, y = ny; } else if (ans == d) { if (!flag) { if (nx < x) { x = nx, y = ny; } else if (nx == x && ny < y) y = ny; } else { if (ny < y) { x = nx, y = ny; } else if (ny == y && nx < x) x = nx; } } } void update(int r, int &ans, int &x, int &y) { int nx = r, ny = find(r, ey, 0); if (ny > 0) chk(ans, nx, ny, x, y); ny = find(r, ey, 1); if (ny <= m) chk(ans, nx, ny, x, y); } int main() { for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) f[i][j][0] = f[i][j][1] = j; int x, y; scanf( %d%d%d , &n, &m, &k); if (n > m) swap(n, m), flag = 1; while (k--) { scanf( %d%d , &x, &y); if (flag) swap(x, y); ex = x, ey = y; int d = 0, ans = ~0u >> 2, nx, ny; while (d <= ans) { int pre = ans; int r = x - d; if (r > 0 && r <= n) update(r, ans, nx, ny); r = x + d; if (r > 0 && r <= n) update(r, ans, nx, ny); d++; } f[nx][ny][0] = ny - 1; f[nx][ny][1] = ny + 1; if (flag) swap(nx, ny); printf( %d %d n , nx, ny); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; long long dx[] = {0, 1, 1, 1, 0, -1, -1, -1}; long long dy[] = {1, 1, 0, -1, -1, -1, 0, 1}; struct BipartiteMatcher { vector<vector<long long>> G; vector<long long> L, R, Viz; BipartiteMatcher(long long n, long long m) : G(n), L(n, -1), R(m, -1), Viz(n) {} void AddEdge(long long a, long long b) { G[a].push_back(b); } bool Match(long long node) { if (Viz[node]) return false; Viz[node] = true; for (auto vec : G[node]) { if (R[vec] == -1) { L[node] = vec; R[vec] = node; return true; } } for (auto vec : G[node]) { if (Match(R[vec])) { L[node] = vec; R[vec] = node; return true; } } return false; } long long Solve() { long long ok = true; while (ok--) { fill(Viz.begin(), Viz.end(), 0); for (long long i = 0; i < (long long)L.size(); ++i) if (L[i] == -1) ok |= Match(i); } long long ret = 0; for (long long i = 0; i < L.size(); ++i) ret += (L[i] != -1); return ret; } }; bool comp(const pair<long long, pair<long long, long long>> &a, const pair<long long, pair<long long, long long>> &b) { return a.second.second < b.second.second; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t = 1; while (t--) { long long n, m; cin >> n >> m; vector<pair<long long, pair<long long, long long>>> roads; for (long long i = 0; i < m; ++i) { long long u, v, w; cin >> u >> v >> w; --u; --v; roads.push_back({u, {v, w}}); } sort(roads.begin(), roads.end(), comp); long long lo = 0, hi = 1e9 + 1; while (lo < hi) { long long md = (lo + hi) >> 1; BipartiteMatcher graph(n, n); for (auto it : roads) { if (it.second.second <= md) graph.AddEdge(it.first, it.second.first); else break; } long long cnt = graph.Solve(); if (cnt < n) { lo = md + 1; } else hi = md; } if (hi == (1e9 + 1)) cout << -1; else cout << hi; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, a[1000005]; std::vector<pair<double, pair<long long, long long> > > v; signed main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); } for (long long i = 1; i <= n; i++) { v.push_back(make_pair(1.0 * a[i], make_pair(i, i))); while (v.size() > 1 && v[v.size() - 1].first <= v[v.size() - 2].first) { double val1 = v[v.size() - 1].first; double val2 = v[v.size() - 2].first; pair<long long, long long> interval1 = v[v.size() - 1].second; pair<long long, long long> interval2 = v[v.size() - 2].second; v.pop_back(); v.pop_back(); v.push_back(make_pair((val1 * (interval1.second - interval1.first + 1) + val2 * (interval2.second - interval2.first + 1)) / (interval1.second - interval2.first + 1), make_pair(interval2.first, interval1.second))); } } for (long long i = 0; i < v.size(); i++) { pair<long long, long long> interval = v[i].second; for (long long j = interval.first; j <= interval.second; j++) { printf( %.10lf n , v[i].first); } } return 0; } |
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.ne2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.ne2_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int INFMEM = 63; const int INF = 1061109567; const long long LINF = 4557430888798830399LL; const double DINF = numeric_limits<double>::infinity(); const long long MOD = 1000000007; const int dx[8] = {1, 0, -1, 0, 1, 1, -1, -1}; const int dy[8] = {0, 1, 0, -1, 1, -1, 1, -1}; const double PI = 3.141592653589793; inline void open(string a) { freopen((a + .in ).c_str(), r , stdin); freopen((a + .out ).c_str(), w , stdout); } inline void fasterios() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } long long cnt[1000005]; pair<long long, long long> isi[100005]; bool isAscent[100005]; int main() { fasterios(); long long n; cin >> n; long long cntascent = 0; for (int i = 1; i <= n; i++) { long long k; cin >> k; pair<long long, long long> cur; long long pre = -1; bool ascent = 0; for (int j = 1; j <= k; j++) { long long tmp; cin >> tmp; if (j == 1) { cur.first = cur.second = tmp; pre = tmp; } else { if (pre < tmp) ascent = 1; pre = tmp; } cur.first = min(cur.first, tmp); cur.second = max(cur.second, tmp); } isi[i] = cur; if (!ascent) cnt[cur.first]++; isAscent[i] = ascent; cntascent += ascent; } for (int i = 0; i <= 1000000; i++) cnt[i] += cnt[i - 1]; long long ans = 0; for (int i = 1; i <= n; i++) { if (isAscent[i]) { ans += n; continue; } long long now = isi[i].second; ans += cnt[now - 1]; ans += cntascent; } cout << ans << n ; return 0; } |
// Pentevo project (c) NedoPC 2011
//
// NMI generation
`include "../include/tune.v"
module znmi
(
input wire rst_n,
input wire fclk,
input wire zpos,
input wire zneg,
input wire int_start, // when INT starts
input wire [ 1:0] set_nmi, // NMI requests from slavespi and #BF port
input wire imm_nmi, // immediate NMI from breakpoint
input wire clr_nmi, // clear nmi: from zports, pulsed at out to #xxBE
input wire rfsh_n,
input wire m1_n,
input wire mreq_n,
input wire csrom,
input wire [15:0] a,
output reg in_nmi, // when 1, there must be last (#FF) ram page in 0000-3FFF
output wire gen_nmi // NMI generator: when 1, NMI_N=0, otherwise NMI_N=Z
);
reg [1:0] set_nmi_r;
wire set_nmi_now;
reg imm_nmi_r;
wire imm_nmi_now;
reg pending_nmi;
reg in_nmi_2; // active (=1) when NMIed to ROM, after 0066 M1 becomes 0,
// but in_nmi becomes 1 -- ROM switches to #FF RAM
reg [2:0] nmi_count;
reg [1:0] clr_count;
reg pending_clr;
reg last_m1_rom;
reg last_m1_0066;
wire nmi_start;
//remember whether last M1 opcode read was from ROM or RAM
reg m1_n_reg, mreq_n_reg;
reg [1:0] rfsh_n_reg;
always @(posedge fclk) if( zpos )
rfsh_n_reg[0] <= rfsh_n;
always @(posedge fclk)
rfsh_n_reg[1] <= rfsh_n_reg[0];
always @(posedge fclk) if( zpos )
m1_n_reg <= m1_n;
always @(posedge fclk) if( zneg )
mreq_n_reg <= mreq_n;
wire was_m1 = ~(m1_n_reg | mreq_n_reg);
reg was_m1_reg;
always @(posedge fclk)
was_m1_reg <= was_m1;
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_rom <= csrom && (a[15:14]==2'b00);
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_0066 <= ( a[15:0]==16'h0066 );
always @(posedge fclk)
set_nmi_r <= set_nmi;
//
assign set_nmi_now = | (set_nmi_r & (~set_nmi) );
always @(posedge fclk)
imm_nmi_r <= imm_nmi;
//
assign imm_nmi_now = | ( (~imm_nmi_r) & imm_nmi );
always @(posedge fclk, negedge rst_n)
if( !rst_n )
pending_nmi <= 1'b0;
else // posedge clk
begin
if( int_start )
pending_nmi <= 1'b0;
else if( set_nmi_now )
pending_nmi <= 1'b1;
end
// actual nmi start
assign nmi_start = (pending_nmi && int_start) || imm_nmi_now;
always @(posedge fclk)
if( clr_nmi )
clr_count <= 2'd3;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && clr_count[1] )
clr_count <= clr_count - 2'd1;
always @(posedge fclk)
if( clr_nmi )
pending_clr <= 1'b1;
else if( !clr_count[1] )
pending_clr <= 1'b0;
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi_2 <= 1'b0;
else // posedge fclk
begin
if( nmi_start && (!in_nmi) && last_m1_rom )
in_nmi_2 <= 1'b1;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 )
in_nmi_2 <= 1'b0;
end
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi <= 1'b0;
else // posedge clk
begin
if( pending_clr && (!clr_count[1]) )
in_nmi <= 1'b0;
else if( (nmi_start && (!in_nmi) && (!last_m1_rom)) ||
(rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 && in_nmi_2) )
in_nmi <= 1'b1;
end
always @(posedge fclk, negedge rst_n)
if( !rst_n )
nmi_count <= 3'b000;
else if( nmi_start && (!in_nmi) )
nmi_count <= 3'b111;
else if( nmi_count[2] && zpos )
nmi_count <= nmi_count - 3'd1;
assign gen_nmi = nmi_count[2];
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > V(7); vector<vector<string> > S(7); set<string> SS; int n, m; void DFS(int node, string T) { if (T.length() == n) { SS.insert(T); return; } for (int i = 0; i < S[node].size(); i++) { string R = S[node][i]; string E; E += R[1]; if (T.length() + 2 == n) { DFS(0, T + R); } else DFS(R[0] - a , T + E); } } int main() { cin >> n >> m; string y; char C; char A[m]; for (int i = 0; i < m; i++) { cin >> y >> C; A[i] = C; S[C - a ].push_back(y); } for (int i = 0; i < m; i++) { if (A[i] == a ) { DFS(A[i] - a , ); } } cout << SS.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (1 << 23); bool vis[maxn], num[maxn]; int n, m; void dfs(int x) { if (vis[x]) return; vis[x] = 1; for (int i = 0; i < n; i++) { if (x & (1 << i)) dfs(x ^ (1 << i)); } if (num[x]) dfs((1 << n) - 1 - x); } int main() { int x; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d , &x); num[x] = 1; } int ans = 0; for (int i = 0; i < (1 << n); i++) { if (num[i] && !vis[i]) dfs(((1 << n) - 1) & (~i)), ans++; } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_4_V
`define SKY130_FD_SC_LP__O21BAI_4_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_4_V
|
`include "defines.v"
`timescale 1ns/1ps
module tb(
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
reg `control_w flit1c;
reg `data_w flit1d;
reg `control_w flit2c;
reg `data_w flit2d;
wire `control_w port0_co, port1_co, port2_co, port3_co, port4_co;
wire `data_w port0_do, port1_do, port2_do, port3_do, port4_do;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(flit2c), .port2_co(port2_co),
.port3_ci(28'h0), .port3_co(port3_co),
.port4_ci(28'h0), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(flit1d), .port1_do(port1_do),
.port2_di(flit2d), .port2_do(port2_do),
.port3_di(128'h0), .port3_do(port3_do),
.port4_di(128'h0), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
$set_toggle_region(tb.r);
$toggle_start();
clk = 0;
rst = 0;
flit0c = 28'h8010001;
flit0d = 128'h0;
flit1c = 28'h8040002;
flit1d = 128'h0;
flit2c = 28'h8060003;
flit2d = 128'h0;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 28'h0;
flit0d = 128'h0123456789abcdef0123456789abcdef;
flit1c = 28'h0;
flit1d = 128'h0123456789abcdef0123456789abcdef;
flit2c = 28'h0;
flit2d = 128'h0123456789abcdef0123456789abcdef;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
flit0d = 128'h0;
flit1d = 128'h0;
flit2d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
$toggle_stop();
$toggle_report("./bless_backward_3.saif", 1.0e-9, "tb.r");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; void solve() { string p, h; cin >> p >> h; swap(p, h); sort(h.begin(), h.end()); for (long long i = 0; i + h.size() - 1 < p.size(); ++i) { string temp = p.substr(i, h.size()); sort(temp.begin(), temp.end()); if (temp == h) { cout << YES n ; return; } } cout << NO n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; unordered_set<char> st; for (int i = 0; i < s.length(); i++) { if (s[i] != s[i + 1]) { st.insert(s[i]); } else { i++; } } vector<char> v; for (auto i : st) { v.push_back(i); } sort(v.begin(), v.end()); for (auto i = v.begin(); i != v.end(); i++) { cout << *i; } cout << endl; } } |
#include<bits/stdc++.h> using namespace std; typedef long long int ll; #define endl n bool powerOf2(ll x){ return x && (!(x&(x-1))); } void solve(){ ll u, v; cin>>u>>v; if(v<u || (powerOf2(u) && !powerOf2(v))){ cout<< No n ; }else{ if(u==v || (powerOf2(v))){ cout<< Yes n ; }else{ ll num = u; bool flag = false; while(num<v){ ll maxN = -1; for(int i = 0;i<32; i++){ ll msk = 1<<i; if(num + msk > v){ break; } if(num & msk){ if(num + msk == v){ flag = true; break; } maxN = max(maxN, msk); } } if(flag || maxN == -1) break; num+=maxN; } if(flag || num==v){ cout<< Yes n ; }else{ cout<< No n ; } } } } int main(){ int t; cin>>t; while(t--) solve(); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,popcnt,abm,mmx,tune=native ) using namespace std; int a, b, c, d, e, f, p = 1000000007, base = 157, mi = 1e9, id = 0, q, pos; int ind[300000], ans[300000], si[300000], si2[300000]; pair<int, int> reb_price[300000]; string s, s2; vector<int> vec[300000]; vector<pair<int, int>> rebra[300000]; vector<int> order; void dfs() { for (auto v : order) { int ma = 0, ma2 = 0; si[v] = 1; for (auto i : rebra[v]) { if (i.second == 0) { continue; } b += (si[i.first] + i.second - 1) / id; si[i.first] = (si[i.first] + i.second - 1) % id; if (si[i.first] > ma) { ma2 = ma; ma = si[i.first]; } else if (si[i.first] > ma2) { ma2 = si[i.first]; } } si[v] = ma + 1; if (si[v] + ma2 >= id) { si[v] = 0; b++; } } } pair<int, int> dfs2(int v, int pred, int pred2) { if (rebra[v].size() == 1 && v != 1) { rebra[v][0] = {pred2, 0}; order.push_back(v); return {v, 1}; } if (rebra[v].size() == 2 && v != 1) { if (rebra[v][0].first == pred) { auto pa = dfs2(rebra[v][1].first, v, pred2); return {pa.first, pa.second + 1}; } else { auto pa = dfs2(rebra[v][0].first, v, pred2); return {pa.first, pa.second + 1}; } } int j = 0; for (auto i : rebra[v]) { if (i.first == pred) { rebra[v][j] = {pred2, 0}; j++; continue; } rebra[v][j] = dfs2(i.first, v, v); j++; } order.push_back(v); return {v, 1}; } int readint() { int n = 0; char c; do { c = fgetc(stdin); } while (!(c == - || 0 <= c && c <= 9 )); int sign = 1; if (c == - ) { sign = -1; c = fgetc(stdin); } do { n = n * 10 + (c - 0 ); c = fgetc(stdin); } while ( 0 <= c && c <= 9 ); return n * sign; } signed main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); auto seed = chrono::high_resolution_clock::now().time_since_epoch().count(); a = readint(); for (int i = 0; i < a - 1; i++) { b = readint(); c = readint(); rebra[b].push_back({c, 1}); rebra[c].push_back({b, 1}); } dfs2(1, -1, -1); for (int i = 0; i < a; i = i) { if (i == 0 || i < 500) { b = 0; id = i + 1; dfs(); cout << b << n ; ; i++; } else { b = 0; id = i + 1; dfs(); c = b; int l = i + 1, r = a / max(b, 1) + 1; b = 0; while (r - l > 1) { int res = (r + l) / 2; b = 0; id = res; dfs(); if (b == c) { l = res; } else { r = res; } } for (int j = i; j < l; j++) { cout << c << n ; ; } i = l; } } cin >> a; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 109; int n; int a[N]; map<int, int> m; set<int> s[2]; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; m[a[i]]++; } int pos = 0; for (auto p : m) if (p.second == 1) { s[pos].insert(p.first); pos = 1 - pos; } if (s[0].size() == s[1].size()) { string res(n, A ); for (int i = 0; i < n; ++i) if (s[1].count(a[i])) res[i] = B ; cout << YES << endl; for (auto c : res) cout << c; cout << endl; return 0; } else { assert(int(s[0].size()) - 1 == int(s[1].size())); string res(n, A ); for (int i = 0; i < n; ++i) if (s[1].count(a[i])) res[i] = B ; int id = -1; for (auto p : m) if (p.second >= 3) { id = p.first; break; } if (id == -1) { cout << NO << endl; return 0; } bool flag = false; for (int i = 0; i < n; ++i) { if (a[i] == id) if (!flag) { flag = true; res[i] = B ; } } cout << YES << endl; for (auto c : res) cout << c; cout << endl; return 0; } return 0; } |
//Phy layer of the I2S Reader
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//Attach these signals to the pins
`include "project_defines.v"
`include "i2s_reader_defines.v"
`timescale 1 ns/1 ps
module i2s_reader_phy (
input rst,
/*This signal is connected to the i2s clock (driven either internally or
externally)*/
input clk,
output [31:0] debug,
input i_enable,
input [23:0] i_min_read_size,
//memory interface
input [23:0] i_wfifo_size,
input [1:0] i_wfifo_ready,
output reg [1:0] o_wfifo_activate = 2'b0,
output reg o_wfifo_strobe = 1'b0,
output reg [31:0] o_wfifo_data = 32'h0,
//These signals are connected to the phy signals
input i_i2s_lr,
input i_i2s_data
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ = 4'h1;
//Registers/Wires
reg [3:0] state = IDLE;
reg [31:0] read_word = 32'h0;
reg [23:0] r_count = 24'h0;
reg r_prev_i2s_lr = 1'b0;
//Submodules
//Asynchronous Logic
assign debug[0] = i_i2s_lr;
assign debug[1] = i_i2s_data;
assign debug[2] = i_enable;
assign debug[4:3] = i_wfifo_ready;
assign debug[6:5] = o_wfifo_activate;
assign debug[7] = o_wfifo_strobe;
assign debug[11:8] = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_wfifo_activate <= 2'b0;
o_wfifo_strobe <= 1'b0;
o_wfifo_data <= 32'h0;
r_count <= 0;
r_prev_i2s_lr <= 0;
end
else begin
o_wfifo_strobe <= 0;
if ((state == READ) && ((i_wfifo_ready > 0) && (o_wfifo_activate == 0))) begin
r_count <= 0;
if (i_wfifo_ready[0]) begin
o_wfifo_activate[0] <= 1;
end
else begin
o_wfifo_activate[1] <= 1;
end
end
case (state)
IDLE: begin
if (i_enable) begin
state <= READ;
o_wfifo_activate <= 0;
end
end
READ: begin
if (!i_enable) begin
state <= IDLE;
end
else begin
if (r_count < i_wfifo_size) begin
if (i_i2s_lr != r_prev_i2s_lr) begin
//A word is ready to write to memory
o_wfifo_data <= {r_prev_i2s_lr, 7'h0, read_word[23:0]};
o_wfifo_strobe <= 1;
r_count <= r_count + 1;
end
end
else begin
o_wfifo_activate <= 0;
end
read_word <= {read_word[30:0] << 1, i_i2s_data};
end
end
default: begin
state <= IDLE;
end
endcase
end
r_prev_i2s_lr <= i_i2s_lr;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; using db = long double; using ii = pair<int, int>; const int N = 1e7 + 5, LG = 19, MOD = 1e9 + 7; const int SQ = 225; const long double EPS = 1e-7; int fast(int b, int e) { int res = 1; for (; e; e >>= 1, b = 1ll * b * b % MOD) if (e & 1) res = 1ll * res * b % MOD; return res; } vector<int> adj[10005]; int n, k; map<int, map<int, ll>> mat; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; vector<int> deg(n + 1); for (int i = 1; i <= k; i++) for (int j = i + 1; j <= k; j++) { adj[j].push_back(i); deg[j]++; deg[i]++; } for (int i = k + 1; i <= n; i++) { for (int j = 0; j < k; j++) { int x; cin >> x; adj[i].push_back(x); deg[i]++; deg[x]++; } } for (int i = 1; i <= n; i++) { mat[i][i] = deg[i]; for (auto x : adj[i]) { mat[i][x] = MOD - 1; mat[x][i] = MOD - 1; } } ll ans = 1; for (int i = n; i >= 2; --i) { ll v = mat[i][i]; ll inv = fast(MOD - v, MOD - 2); ans = 1ll * ans * v % MOD; for (auto j : adj[i]) { ll coff = inv * mat[j][i] % MOD; for (auto k : adj[i]) { mat[j][k] = (mat[j][k] + mat[i][k] * coff) % MOD; } } } cout << ans << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:21:49 11/28/2015
// Design Name: sig_extend
// Module Name: /home/avre/Documents/arquitectura/Arquitectura_TPF/Arquitectura_TPF/sig_extend_tb.v
// Project Name: Arquitectura_TPF
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sig_extend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sig_extend_tb;
// Inputs
reg [15:0] reg_in;
reg clk;
reg reset;
// Outputs
wire [31:0] reg_out;
// Instantiate the Unit Under Test (UUT)
sig_extend uut (
.reg_in(reg_in),
.reg_out(reg_out),
.clk(clk),
.reset(reset)
);
initial begin
// Initialize Inputs
reg_in = 10;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#1;
reg_in = 15;
#10
reg_in = -20;
#10
reg_in = 50;
#10
reg_in = -32768;
#10
reg_in = 32767;
#10
reg_in = 0;
#10
reg_in = 1;
#10
reg_in = -1;
// Add stimulus here
end
always
begin
#1
clk=~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(int i, int n, set<pair<int, int> >& st) { for (auto it : st) { pair<int, int> t(it.first + i, it.second + i); if (t.first > n) t.first %= n; if (t.second > n) t.second %= n; if (t.first > t.second) swap(t.first, t.second); if (!st.count(t)) return false; } return true; } int main() { int n, m, a, b; while (cin >> n >> m) { set<pair<int, int> > st; for (int i = 1; i <= m; i++) { cin >> a >> b; st.insert(make_pair(min(a, b), max(a, b))); } bool flg = false; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { if (check(i, n, st)) { flg = true; break; } else if (i != 1 && check(n / i, n, st)) { flg = true; break; } } } cout << (flg ? Yes : No ) << endl; } return 0; } |
/*
- This is a material implementd for google summer of code 2017.
- I built this module to be more familiar with the design required, start edit, re-implement the whole thing
- The mentor feedback would really help me getting more and more clear vision about this project
--------------------------------------------------------------------------------------------------------------
Written by: Abdelrahman Elbehery
*/
module simple_slave ( //The module is implemented without an oversampling clock [for low dynamic power consumption]
input SCK, //I2c SCL [pulled up by external R]
output SDA, //I2c SDA [pulled up by external R]
output reg [7:0] PWM_INTERFACE //To be connected to the PWM Interface
);
//internal registers, signals and wire assignments are here
parameter [7:0] moduleAddress=8'b10101011; //The module i2c address [to be given during the module instantiation]
parameter [4:0] initialState=0, getAddr=1, isItMe=8, ackSent=9,
dataRecv=17, postSend=18, notMe=19;
reg [4:0] eventCounter =0; //The state register [Each point on the transaction has a unique number]
reg sda_ack =0; //An internal signal uesd to send ACK when the correct address is sent, data transaction is over
assign SDA = (sda_ack)? 0:1'bz; //when sda_ack is asserted the module pulls down the SDA bus [i.e. sends an ACK]
//reg busIsBusy =0; //An internal signal providing the bus status used to detect start(), stop() events
wire busIsBusy;
reg [7:0] addrDataBuff; //8-bit registre holding addr, then reads data in case address matches.
reg started =0, stopped =0; //two internal registers to capture the start, stop events
assign busIsBusy= started ^ stopped; //if at any time started bit != to stopped bit, then we have already started a transaction
reg startId; //An internal bit used to differentiate two different transactions
//code body goes here
always @ (negedge SDA) begin
if(SCK==1 & !busIsBusy) //Capture the start() event only if the bus was free
started<=~started;
end
always @ (posedge SDA) begin
if(SCK==1 & busIsBusy) begin //Capture the stop() event only if the bus was already busy
stopped<=~stopped;
//startId<=started;
end
end
always @ (negedge SCK) begin
if(busIsBusy) begin
case(eventCounter)
initialState:
eventCounter<=getAddr; //If start() the slave will start reading the serial address from the bus
isItMe: //Once the data cycle is done, the slave checks if its being called or other device
if(addrDataBuff==moduleAddress) begin
sda_ack<=1; //If so, send and ack, then the next cycle store the serial data
eventCounter<=ackSent;
end
else begin
eventCounter<=notMe; //IF not, stay idle till the next time the bus is free and a transaction starts
startId<=started;
end
dataRecv: begin //Once data is recieved, send an ack, return to the idle state
sda_ack<=1;
PWM_INTERFACE<=addrDataBuff; //output the data to the PWM_INTERFACE
eventCounter<=postSend;
end
notMe: //If not this slave being called, once the last transct. is over and a new one starts, read address
if(startId!=started)
eventCounter<=getAddr;
default: begin //Otherwise, keep incrementing the eventCounter state register
sda_ack<=0;
if(eventCounter==postSend)
eventCounter<=initialState;
else if(eventCounter!=notMe)
eventCounter<=eventCounter+1;
end
endcase
end
end
always @ (posedge SCK) begin
if(busIsBusy) begin
if((eventCounter>initialState &eventCounter<ackSent) | (eventCounter>ackSent &eventCounter<postSend))
addrDataBuff<={addrDataBuff[6:0],SDA}; //Put the coming data at the right time
end
end
endmodule //simple_slave
|
#include <bits/stdc++.h> using namespace std; long long good[3000]; long long fact[20]; int q = 0; void gen(long long sum, int left) { if (!left) { good[q++] = sum; } else { if (!sum) { gen(sum, left - 1); } gen(sum * 10 + 4, left - 1); gen(sum * 10 + 7, left - 1); } } bool is_lucky(int v) { while (v) { if (v % 10 != 4 && v % 10 != 7) { return false; } v /= 10; } return true; } void true_main() { gen(0, 10); vector<int> per(20); vector<bool> fre(20); int n; long long k; fact[0] = 1; for (int i = 1; i < 20; i++) { fact[i] = fact[i - 1] * i; } cin >> n >> k; if (n < 15) { if (k > fact[n]) { puts( -1 ); return; } } int ans = 0; for (int i = 1; i < q; i++) { if (good[i] <= n - 15) { ans++; } } int m = min(n, 15); k--; for (int i = 0; i < m; i++) { long long q = k / fact[m - i - 1]; k -= q * fact[m - i - 1]; for (int j = 0;; j++) { if (!fre[j]) { if (!q) { fre[j] = true; per[i] = j; break; } q--; } } } for (int i = 0; i < m; i++) { if (is_lucky(n - m + per[i] + 1) && is_lucky(n - m + i + 1)) { ans++; } } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { true_main(); cout << n ; } return 0; } |
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module alu_slice_LA(a, b, c, less, sel, out, p, g);
input a, b, c, less;
input [2:0] sel;
output out;
output p, g;
wire sum, cout, ANDresult,less, ORresult, b_inv, p, g;
reg out;
assign b_inv = sel[2] ^ b;
assign ANDresult = a & b;
assign ORresult = a | b;
fulladder_LA f1(a, b_inv, c, sum, p, g);
always @(a or b or c or less or sel)
begin
case(sel[1:0])
2'b00: out = ANDresult;
2'b01: out = ORresult;
2'b10: out = sum;
2'b11: out = less;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; char s[N], t[N]; int dp[N][N][15][2]; int main() { int n, m, lim; scanf( %d %d %d %s %s , &n, &m, &lim, s, t); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { for (int k = 0; k < 15; k++) { dp[i][j][k][0] = dp[i][j][k][1] = -1e9; } } } dp[0][0][0][0] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int k = 0; k <= lim; k++) { int zero = dp[i][j][k][0]; int one = dp[i][j][k][1]; if (s[i] == t[j]) { dp[i + 1][j + 1][k + 1][1] = max(dp[i + 1][j + 1][k + 1][1], zero + 1); dp[i + 1][j + 1][k + 1][1] = max(dp[i + 1][j + 1][k + 1][1], one + 1); dp[i + 1][j + 1][k][1] = max(dp[i + 1][j + 1][k][1], one + 1); } for (int a = 0; a < 2; a++) { dp[i + 1][j][k][0] = max(dp[i + 1][j][k][0], dp[i][j][k][a]); dp[i][j + 1][k][0] = max(dp[i][j + 1][k][0], dp[i][j][k][a]); } } } } int ans = 0; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { ans = max(ans, dp[i][j][lim][0]); ans = max(ans, dp[i][j][lim][1]); } } cout << ans << endl; return 0; } |
// megafunction wizard: %ALTIOBUF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altiobuf_in
// ============================================================
// File Name: in_buf.v
// Megafunction Name(s):
// altiobuf_in
//
// Simulation Library Files(s):
// cyclonev
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altiobuf_in CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" datain dataout
//VERSION_BEGIN 15.0 cbx_altiobuf_in 2015:04:15:19:11:38:SJ cbx_mgl 2015:04:15:20:18:26:SJ cbx_stratixiii 2015:04:15:19:11:39:SJ cbx_stratixv 2015:04:15:19:11:39:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cyclonev_io_ibuf 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module in_buf_iobuf_in_v0i
(
datain,
dataout) ;
input [0:0] datain;
output [0:0] dataout;
wire [0:0] wire_ibufa_o;
cyclonev_io_ibuf ibufa_0
(
.i(datain),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_0.bus_hold = "false",
ibufa_0.differential_mode = "false",
ibufa_0.lpm_type = "cyclonev_io_ibuf";
assign
dataout = wire_ibufa_o;
endmodule //in_buf_iobuf_in_v0i
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module in_buf (
datain,
dataout);
input [0:0] datain;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
in_buf_iobuf_in_v0i in_buf_iobuf_in_v0i_component (
.datain (datain),
.dataout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
// Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_bb.v FALSE
// Retrieval info: LIB_FILE: cyclonev
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; char b[100][100]; int n; bool in(int x) { return x >= 0 && x < n; } bool in(int x, int y) { return in(x) && in(y); } char a[200][200]; int main() { scanf( %d , &n); for (int i = 0; i < (n); i++) scanf( %s , b[i]); vector<pair<int, int> > ans; for (int dx = (-n + 1); dx <= (n - 1); dx++) { for (int dy = (-n + 1); dy <= (n - 1); dy++) { if (dx == 0 && dy == 0) { continue; } bool fail = false; for (int i = 0; i < (n); i++) { for (int j = 0; j < (n); j++) { if (b[i][j] == o && in(i + dx, j + dy) && b[i + dx][j + dy] == . ) { fail = true; } } } if (!fail) { ans.emplace_back(dx, dy); } } } for (int i = 0; i < (n); i++) for (int j = 0; j < (n); j++) { if (b[i][j] == x ) { bool success = false; for (auto& p : ans) { if (in(i - p.first, j - p.second) && b[i - p.first][j - p.second] == o ) { success = true; } } if (!success) { puts( NO ); return 0; } } } puts( YES ); for (int i = 0; i < (2 * n - 1); i++) { for (int j = 0; j < (2 * n - 1); j++) { a[i][j] = . ; } } a[n - 1][n - 1] = o ; for (auto& p : ans) { a[n - 1 + p.first][n - 1 + p.second] = x ; } for (int i = 0; i < (2 * n - 1); i++) { puts(a[i]); } } |
#include <bits/stdc++.h> using namespace std; bool check(long long n, long long s) { long long sum = 0; while (n) { sum += n % 10; n /= 10; } return sum == s; } int main() { long long n, s, rt, ans = -1; cin >> n; for (s = 1; s < 100; s++) { rt = sqrt(s * s + 4 * n); if (rt * rt == s * s + 4 * n) { if ((rt - s) % 2 == 0) { if (check((rt - s) / 2, s)) { if (ans == -1) ans = (rt - s) / 2; else ans = min(ans, (rt - s) / 2); } } } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5, mod = 1e9 + 7; int add(int x, int y) { x += y; return x >= mod ? x - mod : x; } int c[maxn << 1], dp[maxn]; struct node { int x, y, op; } e[maxn]; bool cmp(node a, node b) { if (a.x == b.x) return a.y < b.y; return a.x < b.x; } void ins(int x, int k) { while (x) { c[x] = add(c[x], k); x -= x & (-x); } } int query(int x) { int res = 0; for (; x <= 400000; x += (x & (-x))) { res = add(res, c[x]); } return res; } int main() { int n, q, x; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &e[i].y, &e[i].x); } scanf( %d , &q); while (q--) { scanf( %d , &x); e[x].op = 1; } sort(e + 1, e + 1 + n, cmp); ins(2 * n, 1); for (int i = 1; i <= n; i++) { dp[i] = query(e[i].y); ins(e[i].y, dp[i]); } int pv = 1, ans = 0; for (int i = n; i > 0; i--) { ins(e[i].y, (mod - dp[i]) % mod); if (e[i].op == 1 && e[i].y >= pv) { ans = add(ans, query(pv)); pv = e[i].y; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-6; int H[1005]; int main() { int n, m, h; int l, r, x; int i, j; scanf( %d%d%d , &n, &h, &m); for (i = 1; i <= n; i++) H[i] = h; for (i = 0; i < m; i++) { scanf( %d%d%d , &l, &r, &x); for (j = l; j <= r; j++) H[j] = min(H[j], x); } int ans = 0; for (i = 1; i <= n; i++) ans += H[i] * H[i]; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> long long query(long long q) { std::printf( ? %lld n , q); std::fflush(stdout); long long res; std::scanf( %lld , &res); return res; } long long qpow(long long a, int b) { long long res = 1; while (b) { if (b & 1) res *= a; b >>= 1, a *= a; } return res; } long long tmp; int prime[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719}; int get(int val) { long long now = val; while (now * val <= int(1e9)) now *= val; long long t = query(now); int res = 0; while (t % val == 0) t /= val, ++res; return res; } int ans = 1, us = 0; int mian() { int next = 0; us = 0, ans = 1; while (us < 21) { if (prime[next] == 719) break; long long p = 1; int last = next; while (p * prime[next] < 1e15 && prime[next] != 719) p *= prime[next++]; tmp = query(p); ++us; for (int i = last; i < next; ++i) if (tmp % prime[i] == 0 && us < 22) { int ga = get(prime[i]); ++us; ans *= ga + 1; } } std::printf( ! %d n , std::max(ans + 7, ans * 2)); std::fflush(stdout); return 0; } int main() { int t; std::scanf( %d , &t); while (t--) mian(); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 110005; long long arr[maxn], arr1[maxn], n, m; int judge(long long x) { memcpy(arr1, arr, sizeof(arr)); long long i = n, countt = 1, t = 0; while (i >= 1 && arr1[i] <= 0) --i; while (countt <= m) { t = x - i; while (t > 0) { if (t >= arr1[i]) { t = t - arr1[i]; arr1[i] = 0; i--; if (i < 1) return 1; } else { arr1[i] = arr1[i] - t; t = 0; } } ++countt; } return 0; } long long aa(long long x) { long long i = n, temp; while (i >= 1 && arr[i] <= 0) --i; temp = arr[i]; int countt = 1; while (countt <= m) { long long t = x - i; while (t > 0) { if (t >= temp) { t -= temp; i--; while (i >= 1 && arr[i] <= 0) --i; if (i < 1) return 1; temp = arr[i]; } else { temp -= t; break; } } countt++; } return 0; } int main() { long long left, right, ans, mid; scanf( %lld%lld , &n, &m); left = 0; right = 1e18; ans = 0; for (int i = 1; i <= n; i++) { scanf( %lld , &arr[i]); } while (left <= right) { mid = (left + right) / 2; if (aa(mid)) { ans = mid; right = mid - 1; } else { left = mid + 1; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long mx, my, w; map<double, int> a, b; int rev(long long x) { long long ret = 0; while (x) { ret *= 10; ret += x % 10; x /= 10; } return ret; } long long get(long long x, long long y) { a.clear(); for (long long i = 1; i <= y; ++i) { double tmp = 1.0 * rev(i) / i; a[tmp]++; } long long ret = 0; for (long long i = 1; i <= x; ++i) { double tmp = 1.0 * i / rev(i); ret += a[tmp]; } return ret; } int main() { cin >> mx >> my >> w; if (get(mx, my) < w) { puts( -1 ); return 0; } int nx = mx, ny = 1, ax = mx, ay = my; long long now = get(nx, ny); a.clear(); for (long long i = 1; i <= nx; ++i) { a[1.0 * i / rev(i)]++; } b.clear(); for (long long i = 1; i <= ny; ++i) { b[1.0 * rev(i) / i]++; } while (nx >= 1 && ny <= my) { if (now < w) { ny++; double tmp = 1.0 * rev(ny) / ny; now += a[tmp]; b[tmp]++; } else { if (1ll * nx * ny < 1ll * ax * ay) { ax = nx; ay = ny; } double tmp = 1.0 * nx / rev(nx); nx--; now -= b[tmp]; a[tmp]--; } } cout << ax << << ay << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; unsigned long long ans = 1, ans2 = 1; for (int i = 0; i < n; i++) { ans = (ans * 27); ans2 = (ans2 * 7); if (ans2 > 1000000007 || ans % 1000000007 > ans2) { ans %= 1000000007; ans2 %= 1000000007; } } cout << (1000000007 + ans - ans2) % 1000000007 << endl; } |
#include <bits/stdc++.h> int p, prime[100005], count[100005][20]; void Prime() { int i, j; for (i = 2, p = 0; i < 100005; i++) { for (j = 2; j <= sqrt(i); j++) if (i % j == 0) break; if (j > sqrt(i)) prime[p++] = i; } } void Count() { int i, j; memset(count, 0, sizeof(count)); for (i = 0; i < p; i++) for (j = prime[i]; j < 100005; j += prime[i]) count[j][++count[j][0]] = prime[i]; } int main() { Prime(); Count(); char sym; int n, m, i, j, ind, flag[100005], num[100005]; while (scanf( %d%d , &n, &m) != EOF) { memset(flag, 0, sizeof(flag)); memset(num, 0, sizeof(num)); for (i = 0; i < m; i++) { getchar(); scanf( %c %d , &sym, &ind); if (sym == + ) { if (flag[ind]) printf( Already on n ); else { for (j = 1; j <= count[ind][0]; j++) if (num[count[ind][j]]) break; if (j > count[ind][0]) { printf( Success n ); flag[ind] = 1; for (j = 1; j <= count[ind][0]; j++) num[count[ind][j]] = ind; } else printf( Conflict with %d n , num[count[ind][j]]); } } else { if (!flag[ind]) printf( Already off n ); else { printf( Success n ); flag[ind] = 0; for (j = 1; j <= count[ind][0]; j++) num[count[ind][j]] = 0; } } } } return 0; } |
#include <bits/stdc++.h> const int MAX = (int)1e5 + 5; int a[MAX], b[MAX], n, m, c; int main() { scanf( %d%d%d , &n, &m, &c); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) { scanf( %d , b + i); b[i] = (b[i] + b[i - 1]) % c; } for (int i = 1; i <= n; i++) { a[i] = (i <= n - m + 1 ? (a[i] + (i >= m ? b[m] : b[i])) % c : (a[i] + c + b[(i >= m) ? m : i] - b[m - 1 - (n - i)]) % c); printf( %d , a[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } template <class T> T min(T a, T b, T c, T d) { return min(a, min(b, min(c, d))); } template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } template <class T> T max(T a, T b, T c, T d) { return max(a, max(b, max(c, d))); } bool cmp(const pair<int, int>& a, const pair<int, int>& b) { return (a.first > b.first || (a.first == b.first && a.second >= b.second)); } long long GCD(long long a, long long b) { return (a % b) ? GCD(b, a % b) : b; } int f[7][100007]; int main() { int n, a, b, c; scanf( %d%d%d%d , &n, &a, &b, &c); --n; f[0][0] = 0; f[1][0] = f[2][0] = 1000000000LL; for (int i = (1); i <= (n); ++i) { f[0][i] = min(f[2][i - 1] + b, f[1][i - 1] + a); f[1][i] = min(f[2][i - 1] + c, f[0][i - 1] + a); f[2][i] = min(f[1][i - 1] + c, f[0][i - 1] + b); } cout << min(f[0][n], f[1][n], f[2][n]) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int T, N; int arr[500005]; stack<int> stk; vector<pair<int, int>> v; int main() { cin.sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> T; while (T--) { cin >> N; bool pos = 1; while (stk.size()) { stk.pop(); } v.clear(); for (int i = 1; i <= N; i++) { while (stk.size() && stk.top() == i) { stk.pop(); } cin >> arr[i]; if (arr[i] == -1) { if (stk.empty()) { arr[i] = N + 1; } else { arr[i] = stk.top(); } } v.push_back({-arr[i], i}); if (stk.size() && stk.top() < arr[i]) { pos = 0; } stk.push(arr[i]); } if (pos) { sort(v.begin(), v.end()); int cnt = N; for (auto p : v) { arr[p.second] = cnt--; } for (int i = 1; i <= N; i++) { cout << arr[i] << ; } cout << n ; } else { cout << -1 << n ; } } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_5_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_5_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_5_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_5_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; const ll MOD = 998244353; #define rep(i,a,b) for(ll i=a;i<b;++i) #define pii pair<int,int> int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tt=1; cin>>tt; while(tt--) { int n; cin>>n; int a[n]; rep(i,0,n) cin>>a[i]; vector<int> v; rep(i,0,n) { v.push_back(a[i]); int p = i+1; rep(j,i+1,n) { p = j; if(a[j]>a[i]) break; v.push_back(a[j]); } reverse(v.begin()+i,v.end()); i = p-1; if(p==n-1 && v.size()==n) i=n; } for(int i=v.size()-1;i>=0;--i) cout<<v[i]<< ; cout<< n ; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1100; int n; char s[maxn + 10]; int data[maxn + 10]; int dp[maxn + 10][2]; int main() { cin >> n; getchar(); gets(s); int i; for (i = 0; s[i]; i++) data[i] = s[i] - 0 ; if (i == 1) printf( 0 n ); else { int ans1 = 0, ans2 = 0; for (int j = 0; j < i; j++) { if ((j & 1) != data[j]) ans1++; } for (int j = 0; j < i; j++) { if ((j & 1) == data[j]) ans2++; } printf( %d n , min(ans1, ans2)); } return 0; } |
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