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#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const long double INF = 1e100; const long double eps = 1e-12; template <typename T> void chkmax(T &x, T y) { x = max(x, y); } template <typename T> void chkmin(T &x, T y) { x = min(x, y); } template <typename T> void read(T &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } template <typename T> void writeln(T x) { write(x); puts( ); } int n, p, q; long double a[MAXN], b[MAXN]; long double check(long double x) { long double y = 1; for (int i = 1; i <= n; i++) chkmin(y, (1.0 - x * a[i]) / b[i]); return x * p + y * q; } int main() { read(n), read(p), read(q); long double l = 0, r = INF; for (int i = 1; i <= n; i++) { read(a[i]), read(b[i]); chkmin(r, 1.0 / a[i]); } while (l + eps < r) { long double ml = (2 * l + r) / 3, mr = (l + 2 * r) / 3; if (check(ml) > check(mr)) r = mr; else l = ml; } printf( %.10Lf n , check((l + r) / 2)); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[1000010]; pair<long long, long long> st[1000010]; bool check(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { double k1 = 1.0 * (b.second - a.second) / (b.first - a.first); double k2 = 1.0 * (c.second - b.second) / (c.first - b.first); if (k1 > k2) return 1; return 0; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i] += a[i - 1]; } int top = 0; st[top++] = make_pair(0, 0); for (int i = 1; i <= n; i++) { pair<long long, long long> tmp = make_pair(i, a[i]); while (top > 1 && check(st[top - 2], st[top - 1], tmp)) top--; st[top++] = tmp; } for (int i = 0; i < top - 1; i++) { long long l = st[i].first, r = st[i + 1].first, tot = st[i + 1].second - st[i].second; for (int j = l + 1; j <= r; j++) { printf( %.9f n , 1.0 * tot / (r - l)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int MOD = 1e9 + 7; vector<pair<long long int, long long int> > vp; map<long long int, long long int> mp, mpp; vector<long long int> v, v1, v2; long long int dp[N], visit[N]; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << ; __f(comma + 1, args...); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int n, m, val, k, d, mi = 1e9, mx(0); long long int sum(0), ct(0), p(0), q(0); cin >> n >> m; if (n <= 2 * m) cout << 0 << ; else cout << n - 2 * m << ; long long int low = 0, high = n; while (low <= high) { long long int mid = (low + high) >> 1; if (((mid * (mid - 1) / 2)) >= m) { high = mid - 1; } else { low = mid + 1; } } cout << n - (high + 1); } |
#include <bits/stdc++.h> using namespace std; int main() { int x[3], l; scanf( %d%d%d%d , x, x + 1, x + 2, &l); long long ans = 1LL * (l + 3) * (l + 2) * (l + 1) / 6; for (int i = 0; i < 3; i++) for (int lx = 0; lx <= l; lx++) { int xx = min(l - lx, x[i] + lx - x[(i + 1) % 3] - x[(i + 2) % 3]); if (xx >= 0) ans -= 1LL * (2 + xx) * (1 + xx) / 2; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> char s[100001]; int main() { int n; int i, j; scanf( %s , s); n = strlen(s); for (i = 0; i < n; i++) if (s[i] == 0 ) break; if (i == n) { for (j = 0; j < n - 1; j++) printf( %c , s[j]); printf( n ); } else { for (j = 0; j < i; j++) printf( %c , s[j]); for (j = i + 1; j < n; j++) printf( %c , s[j]); printf( n ); } return 0; } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_egmenable (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pow(long long b, long long e, long long m) { long long t = 1; for (; e; e >>= 1, b = b * b % m) e & 1 ? t = t * b % m : 0; return t; } template <class T> inline bool chkmin(T &a, T b) { return a > b ? a = b, true : false; } template <class T> inline bool chkmax(T &a, T b) { return a < b ? a = b, true : false; } template <class T> inline T sqr(T x) { return x * x; } template <typename T> T gcd(T x, T y) { for (T t; x; t = x, x = y % x, y = t) ; return y; } template <class edge> struct Graph { vector<vector<edge> > adj; Graph(int n) { adj.clear(); adj.resize(n + 5); } Graph() { adj.clear(); } void resize(int n) { adj.resize(n + 5); } void add(int s, edge e) { adj[s].push_back(e); } void del(int s, edge e) { adj[s].erase(find(iter(adj[s]), e)); } vector<edge> &operator[](int t) { return adj[t]; } }; int main() { ios_base::sync_with_stdio(false); int n, ans = 0; cin >> n; stack<int> Q; for (int i = 1, v; i <= n; ++i) { cin >> v; for (; !Q.empty(); Q.pop()) { int x = Q.top(); chkmax(ans, v ^ x); if (x > v) { break; } } Q.push(v); } cout << setprecision(15) << ans << endl; return 0; } |
#include <bits/stdc++.h> void output1(int n) { for (int i = 0; i < n; ++i) { printf( 10 ); } printf( n ); } void output2(int m) { --m; for (int i = 0; i < m; ++i) { printf( 01 ); } printf( 0 n ); } void output3(int n, int m) { if (n == m + 1) { --n; for (int i = 0; i < n; ++i) { printf( 10 ); } printf( 1 n ); return; } int tmp = n - m - 1; int up = m + 1; up--; for (int i = 0; i < up; ++i) { printf( 1 ); if (tmp) { printf( 1 ); --tmp; } printf( 0 ); } printf( 1 ); if (tmp) { printf( 1 ); } printf( n ); } int main() { int n, m; while (scanf( %d%d , &m, &n) != EOF) { if (m == n) { output1(n); } else if (m == n + 1) { output2(m); } else if (n > m && n <= 2 * m + 2) { output3(n, m); } else { printf( -1 n ); } } return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:46:29 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/pcie3_7x_0/pcie3_7x_0_stub.v
// Design : pcie3_7x_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "pcie3_7x_0_pcie_3_0_7vx,Vivado 2014.3" *)
module pcie3_7x_0(pci_exp_txn, pci_exp_txp, pci_exp_rxn, pci_exp_rxp, user_clk, user_reset, user_lnk_up, user_app_rdy, s_axis_rq_tlast, s_axis_rq_tdata, s_axis_rq_tuser, s_axis_rq_tkeep, s_axis_rq_tready, s_axis_rq_tvalid, m_axis_rc_tdata, m_axis_rc_tuser, m_axis_rc_tlast, m_axis_rc_tkeep, m_axis_rc_tvalid, m_axis_rc_tready, m_axis_cq_tdata, m_axis_cq_tuser, m_axis_cq_tlast, m_axis_cq_tkeep, m_axis_cq_tvalid, m_axis_cq_tready, s_axis_cc_tdata, s_axis_cc_tuser, s_axis_cc_tlast, s_axis_cc_tkeep, s_axis_cc_tvalid, s_axis_cc_tready, pcie_rq_seq_num, pcie_rq_seq_num_vld, pcie_rq_tag, pcie_rq_tag_vld, pcie_cq_np_req, pcie_cq_np_req_count, cfg_phy_link_down, cfg_phy_link_status, cfg_negotiated_width, cfg_current_speed, cfg_max_payload, cfg_max_read_req, cfg_function_status, cfg_function_power_state, cfg_vf_status, cfg_vf_power_state, cfg_link_power_state, cfg_err_cor_out, cfg_err_nonfatal_out, cfg_err_fatal_out, cfg_ltr_enable, cfg_ltssm_state, cfg_rcb_status, cfg_dpa_substate_change, cfg_obff_enable, cfg_pl_status_change, cfg_tph_requester_enable, cfg_tph_st_mode, cfg_vf_tph_requester_enable, cfg_vf_tph_st_mode, cfg_fc_ph, cfg_fc_pd, cfg_fc_nph, cfg_fc_npd, cfg_fc_cplh, cfg_fc_cpld, cfg_fc_sel, cfg_interrupt_int, cfg_interrupt_pending, cfg_interrupt_sent, cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data, cfg_interrupt_msi_select, cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status, cfg_interrupt_msi_sent, cfg_interrupt_msi_fail, cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number, sys_clk, sys_reset)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txn[3:0],pci_exp_txp[3:0],pci_exp_rxn[3:0],pci_exp_rxp[3:0],user_clk,user_reset,user_lnk_up,user_app_rdy,s_axis_rq_tlast,s_axis_rq_tdata[127:0],s_axis_rq_tuser[59:0],s_axis_rq_tkeep[3:0],s_axis_rq_tready[3:0],s_axis_rq_tvalid,m_axis_rc_tdata[127:0],m_axis_rc_tuser[74:0],m_axis_rc_tlast,m_axis_rc_tkeep[3:0],m_axis_rc_tvalid,m_axis_rc_tready[21:0],m_axis_cq_tdata[127:0],m_axis_cq_tuser[84:0],m_axis_cq_tlast,m_axis_cq_tkeep[3:0],m_axis_cq_tvalid,m_axis_cq_tready[21:0],s_axis_cc_tdata[127:0],s_axis_cc_tuser[32:0],s_axis_cc_tlast,s_axis_cc_tkeep[3:0],s_axis_cc_tvalid,s_axis_cc_tready[3:0],pcie_rq_seq_num[3:0],pcie_rq_seq_num_vld,pcie_rq_tag[5:0],pcie_rq_tag_vld,pcie_cq_np_req,pcie_cq_np_req_count[5:0],cfg_phy_link_down,cfg_phy_link_status[1:0],cfg_negotiated_width[3:0],cfg_current_speed[2:0],cfg_max_payload[2:0],cfg_max_read_req[2:0],cfg_function_status[7:0],cfg_function_power_state[5:0],cfg_vf_status[11:0],cfg_vf_power_state[17:0],cfg_link_power_state[1:0],cfg_err_cor_out,cfg_err_nonfatal_out,cfg_err_fatal_out,cfg_ltr_enable,cfg_ltssm_state[5:0],cfg_rcb_status[1:0],cfg_dpa_substate_change[1:0],cfg_obff_enable[1:0],cfg_pl_status_change,cfg_tph_requester_enable[1:0],cfg_tph_st_mode[5:0],cfg_vf_tph_requester_enable[5:0],cfg_vf_tph_st_mode[17:0],cfg_fc_ph[7:0],cfg_fc_pd[11:0],cfg_fc_nph[7:0],cfg_fc_npd[11:0],cfg_fc_cplh[7:0],cfg_fc_cpld[11:0],cfg_fc_sel[2:0],cfg_interrupt_int[3:0],cfg_interrupt_pending[1:0],cfg_interrupt_sent,cfg_interrupt_msi_enable[1:0],cfg_interrupt_msi_vf_enable[5:0],cfg_interrupt_msi_mmenable[5:0],cfg_interrupt_msi_mask_update,cfg_interrupt_msi_data[31:0],cfg_interrupt_msi_select[3:0],cfg_interrupt_msi_int[31:0],cfg_interrupt_msi_pending_status[63:0],cfg_interrupt_msi_sent,cfg_interrupt_msi_fail,cfg_interrupt_msi_attr[2:0],cfg_interrupt_msi_tph_present,cfg_interrupt_msi_tph_type[1:0],cfg_interrupt_msi_tph_st_tag[8:0],cfg_interrupt_msi_function_number[2:0],sys_clk,sys_reset" */;
output [3:0]pci_exp_txn;
output [3:0]pci_exp_txp;
input [3:0]pci_exp_rxn;
input [3:0]pci_exp_rxp;
output user_clk;
output user_reset;
output user_lnk_up;
output user_app_rdy;
input s_axis_rq_tlast;
input [127:0]s_axis_rq_tdata;
input [59:0]s_axis_rq_tuser;
input [3:0]s_axis_rq_tkeep;
output [3:0]s_axis_rq_tready;
input s_axis_rq_tvalid;
output [127:0]m_axis_rc_tdata;
output [74:0]m_axis_rc_tuser;
output m_axis_rc_tlast;
output [3:0]m_axis_rc_tkeep;
output m_axis_rc_tvalid;
input [21:0]m_axis_rc_tready;
output [127:0]m_axis_cq_tdata;
output [84:0]m_axis_cq_tuser;
output m_axis_cq_tlast;
output [3:0]m_axis_cq_tkeep;
output m_axis_cq_tvalid;
input [21:0]m_axis_cq_tready;
input [127:0]s_axis_cc_tdata;
input [32:0]s_axis_cc_tuser;
input s_axis_cc_tlast;
input [3:0]s_axis_cc_tkeep;
input s_axis_cc_tvalid;
output [3:0]s_axis_cc_tready;
output [3:0]pcie_rq_seq_num;
output pcie_rq_seq_num_vld;
output [5:0]pcie_rq_tag;
output pcie_rq_tag_vld;
input pcie_cq_np_req;
output [5:0]pcie_cq_np_req_count;
output cfg_phy_link_down;
output [1:0]cfg_phy_link_status;
output [3:0]cfg_negotiated_width;
output [2:0]cfg_current_speed;
output [2:0]cfg_max_payload;
output [2:0]cfg_max_read_req;
output [7:0]cfg_function_status;
output [5:0]cfg_function_power_state;
output [11:0]cfg_vf_status;
output [17:0]cfg_vf_power_state;
output [1:0]cfg_link_power_state;
output cfg_err_cor_out;
output cfg_err_nonfatal_out;
output cfg_err_fatal_out;
output cfg_ltr_enable;
output [5:0]cfg_ltssm_state;
output [1:0]cfg_rcb_status;
output [1:0]cfg_dpa_substate_change;
output [1:0]cfg_obff_enable;
output cfg_pl_status_change;
output [1:0]cfg_tph_requester_enable;
output [5:0]cfg_tph_st_mode;
output [5:0]cfg_vf_tph_requester_enable;
output [17:0]cfg_vf_tph_st_mode;
output [7:0]cfg_fc_ph;
output [11:0]cfg_fc_pd;
output [7:0]cfg_fc_nph;
output [11:0]cfg_fc_npd;
output [7:0]cfg_fc_cplh;
output [11:0]cfg_fc_cpld;
input [2:0]cfg_fc_sel;
input [3:0]cfg_interrupt_int;
input [1:0]cfg_interrupt_pending;
output cfg_interrupt_sent;
output [1:0]cfg_interrupt_msi_enable;
output [5:0]cfg_interrupt_msi_vf_enable;
output [5:0]cfg_interrupt_msi_mmenable;
output cfg_interrupt_msi_mask_update;
output [31:0]cfg_interrupt_msi_data;
input [3:0]cfg_interrupt_msi_select;
input [31:0]cfg_interrupt_msi_int;
input [63:0]cfg_interrupt_msi_pending_status;
output cfg_interrupt_msi_sent;
output cfg_interrupt_msi_fail;
input [2:0]cfg_interrupt_msi_attr;
input cfg_interrupt_msi_tph_present;
input [1:0]cfg_interrupt_msi_tph_type;
input [8:0]cfg_interrupt_msi_tph_st_tag;
input [2:0]cfg_interrupt_msi_function_number;
input sys_clk;
input sys_reset;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : test_tasks.v
// Description : Tasks to help test the code
// Author : Philip Tracton
// Created On : Fri Dec 4 12:34:28 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Dec 4 12:34:28 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_includes.vh"
module test_tasks (/*AUTOARG*/ ) ;
reg test_case_fail = 1;
reg test_passed = 1'b0;
reg test_failed = 1'b0;
integer test_count = 0;
always @(posedge test_passed) begin
$display("--------------------------------------------------------------------------------------------");
$display("\n\n\033[1;32mTEST PASSED\033[0m @ %d", $time);
#10 $finish;
end
always @(posedge test_failed) begin
$display("--------------------------------------------------------------------------------------------");
$display("\n\033[1;31m***** TEST FAILED *****\033[0m @ %d\n", $time);
#100 $finish;
end
//
// Do not let a test bench just run forever.
//
initial begin
#50000000;
$display("TEST CASE TIMEOUT @ %d", $time);
test_failed <= 1'b1;
end
/****************************************************************************
TASK: all_tests_completed
PARAMETERS:
OPERATION:
This task is called at the end of a test case to indicate it is done.
If the correct number of test cases were executed we indicate this test
has passed. Otherwise we indicate failure.
***************************************************************************/
task all_tests_completed;
begin
if (`NUMBER_OF_TESTS == test_count) begin
`TEST_PASSED <= 1;
end else begin
$display("INCORRECT NUMBER OF TESTS! Exp: %d Ran: %d", `NUMBER_OF_TESTS, test_count);
`TEST_FAILED <= 1;
end
end
endtask // if
/****************************************************************************
TASK: compare_values
PARAMETERS:
input [8*80:1] display_string; -- Test to indicate which test this is
input [31:0] expected; -- Expected correct value
input [31:0] measured; -- Actual measured value
OPERATION:
This task is the one called from the test cases. It checks for bad data (X)
and compares the expected and measured values. Sets the pass/fail flag
and calls the display_results task.
***************************************************************************/
task compare_values;
input [8*80:1] display_string;
input [31:0] expected;
input [31:0] measured;
begin
if (|measured == 1'bX) begin
display_results("Data is X", expected, measured);
`TEST_FAILED <= 1'b1;
end else begin
if (expected !== measured) begin
test_case_fail <= 1;
//$display("EXP: 0x%h\tMeasure:0x%h", expected, measured);
#1 display_results(display_string, expected, measured);
end else begin
test_case_fail <= 0;
#1 display_results(display_string, expected, measured);
end
end
end
endtask
/****************************************************************************
TASK: display_results
PARAMETERS:
input [8*80:1] display_string; -- Test to indicate which test this is
input [31:0] expected; -- Expected correct value
input [31:0] measured; -- Actual measured value
OPERATION:
This task will display the table of tests with their time stamp,
test number, string, expected, measured and results.
***************************************************************************/
task display_results;
input [8*80:1] display_string;
input [31:0] expected;
input [31:0] measured;
reg [17*8-1:0] pass_fail;
begin
if (test_case_fail) begin
pass_fail = "\033[1;31mFAIL\033[0m";
`TEST_FAILED <= 1;
end else begin
pass_fail = "\033[1;32mPASS\033[0m";
end
// left justify string
while (display_string[8*35:8*35-7] == 8'h00)begin
display_string = {display_string," "};
end
if (test_count == 0) begin
$display("--------------------------------------------------------------------------------------------");
$display("|TIME |Test| \tTest Case \t\t\t\t|Expected |\tMeasured | State |");
$display("--------------------------------------------------------------------------------------------");
end
test_count <= test_count + 1;
$display("|%4d |%4d|\t%0s \t|0x%8h |\t0x%8h |%s |", $time-1, test_count, display_string, expected, measured, pass_fail);
if (((test_count %10) == 0) && test_count >0) begin
$display("--------------------------------------------------------------------------------------------");
end
end
endtask //
endmodule // test_tasks
|
#include <bits/stdc++.h> using namespace std; int distance(char a, char b) { int d = abs(a - b); int d1 = 26 - d; return min(d, d1); } int main() { int n; string A; int cursor; cin >> n >> cursor >> A; cursor--; n--; cursor = min(cursor, n - cursor); int middle = n / 2; int leftmost = cursor, rightmost = cursor; for (int i = cursor; i <= middle; i++) if (A[i] != A[n - i]) rightmost = i; for (int i = cursor; i >= 0; i--) if (A[i] != A[n - i]) leftmost = i; int vertical_moves = 0; for (int i = leftmost; i <= rightmost; i++) vertical_moves += min(abs(A[i] - A[n - i]), 26 - abs(A[i] - A[n - i])); int horizontal_moves = min((cursor - leftmost) + (rightmost - leftmost), (rightmost - cursor) + (rightmost - leftmost)); int total_moves = horizontal_moves + vertical_moves; cout << total_moves; return 0; } |
#include <bits/stdc++.h> int fac[100100]; int n, m, i, x, j, l, r, p, ans, st, dr, mn, mx, M; void init() { int i, j; for (i = 2; i <= 100000; i++) if (!fac[i]) { fac[i] = i; if (i > 316) continue; for (j = i * i; j <= 100000; j += i) if (!fac[j]) fac[j] = i; } } int solve(int x, int y) { int v[20]; int N; int i, j, lim, ind, nr, rez = 0; if (y == 0) return 0; v[0] = 0; N = 0; for (i = x; i > 1; i /= fac[i]) if (N == 0 || v[N - 1] != fac[i]) v[N++] = fac[i]; lim = 1 << N; for (i = 0; i < lim; i++) { ind = 0; nr = 1; for (j = 0; j < N; j++) if (i & (1 << j)) { ind++; nr = nr * v[j]; } int ax = y / nr; if (ind % 2 == 1) rez = (long long)((long long)((long long)rez - (long long)(M + 1) * ax + (long long)nr * ax * ((long long)ax + 1) / 2) % p + (long long)p) % p; else rez = (long long)((long long)((long long)rez + (long long)(M + 1) * ax - (long long)nr * ax * ((long long)ax + 1) / 2) % p + (long long)p) % p; } rez = (long long)((long long)rez * ((long long)n - x + 1)) % p; return ((int)rez); } int main() { scanf( %d%d%d%d%d , &n, &M, &l, &r, &p); init(); for (x = 1; x <= n; x++) { for (st = 0, dr = 100001; st < dr;) { m = (st + dr) / 2; if ((long long)x * x + (long long)m * m >= (long long)l * l) dr = m; else st = m + 1; } mn = st; for (st = 0, dr = 100001; st < dr;) { m = (st + dr) / 2 + 1; if ((long long)x * x + (long long)m * m <= (long long)r * r) st = m; else dr = m - 1; } if (mn < 1) mn = 1; mx = st; if (mx > M) mx = M; if (mn > mx) continue; ans = (long long)((long long)((long long)ans + solve(x, mx) - solve(x, mn - 1)) % p + p) % p; } ans = (long long)ans * 2 % p; if (l <= 1) ans = (long long)((long long)ans + n * ((long long)M + 1) + ((long long)n + 1) * M) % p; printf( %d , ans); return 0; } |
// track loads on each port and in each router. Also, when a port is disabled, use to track the potential deflection.
// After RC
`include "globalVariable.v"
module loadTrack (reset, clk, valid, productiveVector, pgEnable, portStatus, routerLoad, portLoad);
input clk, reset,pgEnable;
input [3:0] valid;
input [3:0] productiveVector;
input [4*`PORT_STAT_SIZE-1:0] portStatus; // [S, N, W, E]
output [`PG_ROUTER_LOAD_SIZE-1:0] routerLoad;
output [4*`PG_PORT_LOAD_SIZE-1:0] portLoad; // [S, N, W, E]
wire [`PORT_STAT_SIZE-1:0] wPortStatus [3:0];
genvar i;
generate
for (i=0; i<4; i= i+1) begin : split_bus
assign wPortStatus[i] = portStatus[i*`PORT_STAT_SIZE+:`PORT_STAT_SIZE];
end
endgenerate
reg [`PG_PORT_LOAD_SIZE-1:0] portUtilization [3:0];
reg [2:0] j;
always @ (posedge clk or negedge reset) begin
if (~reset) begin
for (j=0;j<4;j=j+1)
portUtilization[j] <= 0;
end
else begin
if (~pgEnable) begin
for (j=0;j<4;j=j+1)
if ((valid[j] && (wPortStatus[j] == `ACTIVE))| (productiveVector[j] && (wPortStatus[j] == `INACTIVE)))
portUtilization[j] <= portUtilization[j] + 1;
end
else
for (j=0;j<4;j=j+1)
portUtilization[j] <= 0;
end
end
assign routerLoad = portUtilization[3]+portUtilization[2]+portUtilization[1]+portUtilization[0];
assign portLoad = {portUtilization[3],portUtilization[2],portUtilization[1],portUtilization[0]};
endmodule
|
module thermometer_to_bcd(bcd, thermometer);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? 4 :
(thermometer == 16'b11111) ? 5 :
(thermometer == 16'b111111) ? 6 :
(thermometer == 16'b1111111) ? 7 :
(thermometer == 16'b11111111) ? 8 :
(thermometer == 16'b111111111) ? 9 :
(thermometer == 16'b1111111111) ? 9 :
(thermometer == 16'b11111111111) ? {4'd1, 4'd0} :
(thermometer == 16'b111111111111) ? {4'd1, 4'd1} :
(thermometer == 16'b1111111111111) ? {4'd1, 4'd2} :
(thermometer == 16'b11111111111111) ? {4'd1, 4'd3} :
(thermometer == 16'b111111111111111) ? {4'd1, 4'd4} :
(thermometer == 16'b1111111111111111) ? {4'd1, 4'd5} :
{4'd1, 4'd6};
endmodule
|
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eic;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task eicRead;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _read_addr;
begin
read_addr = _read_addr;
@(posedge HCLK);
$display("%t READEN ADDR=%h DATA=%h",
$time, _read_addr, read_data);
end
endtask
task eicWrite;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _write_addr;
input [ 31 : 0 ] _write_data;
begin
write_addr = _write_addr;
write_data = _write_data;
write_enable = 1'b1;
@(posedge HCLK);
write_enable = 1'b0;
$display("%t WRITEN ADDR=%h DATA=%h",
$time, _write_addr, _write_data);
end
endtask
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_eic_core eic
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
/*
`define EIC_REG_EICR +
`define EIC_REG_EIMSK_0 +
`define EIC_REG_EIMSK_1 +
`define EIC_REG_EIFR_0 +
`define EIC_REG_EIFR_1
`define EIC_REG_EIFRS_0 +
`define EIC_REG_EIFRS_1
`define EIC_REG_EIFRC_0
`define EIC_REG_EIFRC_1 +
`define EIC_REG_EISMSK_0 +
`define EIC_REG_EISMSK_1
`define EIC_REG_EIIPR_0 +
`define EIC_REG_EIIPR_1 +
*/
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
eicWrite(`EIC_REG_EICR, 32'h01); //enable eic
eicWrite(`EIC_REG_EISMSK_0, 32'h05); //any logical change for irq 1, 2 (pins 0, 1)
eicWrite(`EIC_REG_EIMSK_0, 32'h03); //enable irq 1, 2 (pins 0, 1)
eicWrite(`EIC_REG_EIMSK_1, 32'h01); //enable irq 33 (pin 32)
eicRead(`EIC_REG_EIMSK_0);
eicRead(`EIC_REG_EIMSK_1);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
eicRead(`EIC_REG_EIFR_1);
eicWrite(`EIC_REG_EIFRC_1, 32'h01); //clear irq 33 (pin 32)
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFR_0, 32'h01); //set EIFR word0
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFRS_0, 32'h04); //set EIFR bit3
eicRead(`EIC_REG_EIFR_0);
delay();
end
$stop;
$finish;
end
endmodule
|
`define BigEndianCPU 1
module dm_4k (addr, din, byteExt, wEn, clk, dout, test_addr, test_data, rst);
input [11:0] addr;
input [31:0] din;
input [1:0] byteExt;
input [1:0] wEn;
input clk;
output reg [31:0] dout;
//µ÷ÊԶ˿ڣ¬ÓÃÓÚ¶Á³öÊý¾ÝÏÔʾ
input [4 :0] test_addr;
output [31:0] test_data;
input rst;
reg [31:0] dm [31:0];// 32-bit * 32;
wire [1:0] byteSel;
wire [9:0] gpAddr;
reg [7:0] byteIn;
reg [31:0] tmpReg;
assign byteSel = addr[1:0] ^ 2'b11;// Big endian.
assign gpAddr = addr[11:2];
always @ ( * ) begin
if (byteExt == 2'b01 || byteExt == 2'b00) begin// Load byte.
case (byteSel)
2'b00: byteIn <= dm[gpAddr][7:0];
2'b01: byteIn <= dm[gpAddr][15:8];
2'b10: byteIn <= dm[gpAddr][23:16];
2'b11: byteIn <= dm[gpAddr][31:24];
endcase
case (byteExt)// Embedded extender.
2'b00: dout <= {{24{1'b0}}, byteIn};// Logical Cal;
2'b01: dout <= {{24{byteIn[7]}}, byteIn};// Arithmetic Cal;
endcase
end else begin
dout = dm[gpAddr][31:0];// Load word.
end
end
always @ ( posedge clk ) begin// Write;
if (wEn == 2'b01) begin
if (byteExt == 2'b10) begin// Store byte.
tmpReg = dm[gpAddr][31:0];
case (byteSel)
2'b00: tmpReg[7:0] = din[7:0];
2'b01: tmpReg[15:8] = din[7:0];
2'b10: tmpReg[23:16] = din[7:0];
2'b11: tmpReg[31:24] = din[7:0];
endcase
dm[gpAddr][31:0] = tmpReg[31:0];
end else begin// Store word.
dm[gpAddr][31:0] = din[31:0];
end
end
if (!rst) begin
dm[0] <= 0;
dm[1] <= 0;
dm[2] <= 0;
dm[3] <= 0;
dm[4] <= 0;
dm[5] <= 0;
dm[6] <= 0;
dm[7] <= 0;
dm[8] <= 0;
dm[9] <= 0;
dm[10] <= 0;
dm[11] <= 0;
dm[12] <= 0;
dm[13] <= 0;
dm[14] <= 0;
dm[15] <= 0;
dm[16] <= 0;
dm[17] <= 0;
dm[18] <= 0;
dm[19] <= 0;
dm[20] <= 0;
dm[21] <= 0;
dm[22] <= 0;
dm[23] <= 0;
dm[24] <= 0;
dm[25] <= 0;
dm[26] <= 0;
dm[27] <= 0;
dm[28] <= 0;
dm[29] <= 0;
dm[30] <= 0;
dm[31] <= 0;
end
end
//µ÷ÊԶ˿ڣ¬¶Á³öÌض¨ÄÚ´æµÄÊý¾Ý
assign test_data = dm[test_addr];
// always @(*)
// begin
// case (test_addr)
// 5'd0 : test_data <= dm[0 ];
// 5'd1 : test_data <= dm[1 ];
// 5'd2 : test_data <= dm[2 ];
// 5'd3 : test_data <= dm[3 ];
// 5'd4 : test_data <= dm[4 ];
// 5'd5 : test_data <= dm[5 ];
// 5'd6 : test_data <= dm[6 ];
// 5'd7 : test_data <= dm[7 ];
// 5'd8 : test_data <= dm[8 ];
// 5'd9 : test_data <= dm[9 ];
// 5'd10: test_data <= dm[10];
// 5'd11: test_data <= dm[11];
// 5'd12: test_data <= dm[12];
// 5'd13: test_data <= dm[13];
// 5'd14: test_data <= dm[14];
// 5'd15: test_data <= dm[15];
// 5'd16: test_data <= dm[16];
// 5'd17: test_data <= dm[17];
// 5'd18: test_data <= dm[18];
// 5'd19: test_data <= dm[19];
// 5'd20: test_data <= dm[20];
// 5'd21: test_data <= dm[21];
// 5'd22: test_data <= dm[22];
// 5'd23: test_data <= dm[23];
// 5'd24: test_data <= dm[24];
// 5'd25: test_data <= dm[25];
// 5'd26: test_data <= dm[26];
// 5'd27: test_data <= dm[27];
// 5'd28: test_data <= dm[28];
// 5'd29: test_data <= dm[29];
// 5'd30: test_data <= dm[30];
// 5'd31: test_data <= dm[31];
// endcase
// end
endmodule // 4K Data Memeory;
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { int n; long long a = 1, b = 1; char s[10]; scanf( %d , &n); for (int i = int(1); i <= int(n); ++i) { scanf( %s , s); if (strlen(s) == 4) { a++; b++; } else { if (s[0] == U && s[1] == L ) b++; if (s[0] == U && s[1] == R ) a++; if (s[0] == D && s[1] == L ) a++; if (s[0] == D && s[1] == R ) b++; } } cout << a * b << endl; } |
//
// Generated by Bluespec Compiler, version 2013.12.beta1 (build 32746, 2013-12-02)
//
// On Wed Mar 5 21:17:23 CST 2014
//
//
// Ports:
// Name I/O size props
// read O 16
// CLK I 1 clock
// RST_N I 1 reset
// write_x I 16 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSOP1(CLK,
RST_N,
write_x,
read);
input CLK;
input RST_N;
// action method write
input [15 : 0] write_x;
// value method read
output [15 : 0] read;
// signals for module outputs
wire [15 : 0] read;
// register taps_0
reg [15 : 0] taps_0;
wire [15 : 0] taps_0$D_IN;
wire taps_0$EN;
// register taps_1
reg [15 : 0] taps_1;
wire [15 : 0] taps_1$D_IN;
wire taps_1$EN;
// register taps_2
reg [15 : 0] taps_2;
wire [15 : 0] taps_2$D_IN;
wire taps_2$EN;
// register taps_3
reg [15 : 0] taps_3;
wire [15 : 0] taps_3$D_IN;
wire taps_3$EN;
// register y
reg [31 : 0] y;
wire [31 : 0] y$D_IN;
wire y$EN;
// remaining internal signals
wire [31 : 0] SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14,
SEXT_taps_0__q3,
SEXT_taps_1__q4,
SEXT_taps_2__q5,
SEXT_taps_3__q6,
SEXT_y_BITS_31_TO_8__q2;
wire [23 : 0] y_BITS_31_TO_8__q1;
// value method read
assign read = SEXT_y_BITS_31_TO_8__q2[15:0] ;
// register taps_0
assign taps_0$D_IN = write_x ;
assign taps_0$EN = 1'd1 ;
// register taps_1
assign taps_1$D_IN = taps_0 ;
assign taps_1$EN = 1'd1 ;
// register taps_2
assign taps_2$D_IN = taps_1 ;
assign taps_2$EN = 1'd1 ;
// register taps_3
assign taps_3$D_IN = taps_2 ;
assign taps_3$EN = 1'd1 ;
// register y
assign y$D_IN =
SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14 +
{ SEXT_taps_3__q6[25:0], 6'd0 } ;
assign y$EN = 1'd1 ;
// remaining internal signals
assign SEXT_taps_0_BITS_25_TO_0_CONCAT_0_PLUS_SEXT_ta_ETC___d14 =
{ SEXT_taps_0__q3[25:0], 6'd0 } +
{ SEXT_taps_1__q4[25:0], 6'd0 } +
{ SEXT_taps_2__q5[25:0], 6'd0 } ;
assign SEXT_taps_0__q3 = { {16{taps_0[15]}}, taps_0 } ;
assign SEXT_taps_1__q4 = { {16{taps_1[15]}}, taps_1 } ;
assign SEXT_taps_2__q5 = { {16{taps_2[15]}}, taps_2 } ;
assign SEXT_taps_3__q6 = { {16{taps_3[15]}}, taps_3 } ;
assign SEXT_y_BITS_31_TO_8__q2 =
{ {8{y_BITS_31_TO_8__q1[23]}}, y_BITS_31_TO_8__q1 } ;
assign y_BITS_31_TO_8__q1 = y[31:8] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
taps_0 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_2 <= `BSV_ASSIGNMENT_DELAY 16'd0;
taps_3 <= `BSV_ASSIGNMENT_DELAY 16'd0;
y <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (taps_0$EN) taps_0 <= `BSV_ASSIGNMENT_DELAY taps_0$D_IN;
if (taps_1$EN) taps_1 <= `BSV_ASSIGNMENT_DELAY taps_1$D_IN;
if (taps_2$EN) taps_2 <= `BSV_ASSIGNMENT_DELAY taps_2$D_IN;
if (taps_3$EN) taps_3 <= `BSV_ASSIGNMENT_DELAY taps_3$D_IN;
if (y$EN) y <= `BSV_ASSIGNMENT_DELAY y$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
taps_0 = 16'hAAAA;
taps_1 = 16'hAAAA;
taps_2 = 16'hAAAA;
taps_3 = 16'hAAAA;
y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkSOP1
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 4e5 + 10; const long long mod = 998244353; const long long inf = 1e18 + 10; const long long Log = 21; long long n, m, k; long long pw(long long a, long long b) { if (b == 0) return 1; long long x = pw(a, b / 2); x = (x * x) % mod; if (b & 1) x = (x * a) % mod; return x; } long long cnt(long long x, long long p) { long long X = 0; while (x % p == 0) { x /= p; X++; } return X; } long long D; vector<long long> pr; long long fac[maxn], repo[maxn]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); fac[0] = 1; repo[0] = 1; for (long long i = 1; i < 200; i++) { fac[i] = (fac[i - 1] * i) % mod; repo[i] = pw(fac[i], mod - 2); } cin >> D; for (long long i = 2; i <= sqrt(D); i++) if (D % i == 0) { while (D % i == 0) D /= i; pr.push_back(i); } if (D > 1) pr.push_back(D); long long q; cin >> q; while (q--) { long long u, v; cin >> u >> v; if (u > v) swap(u, v); long long ans = 1, sm2 = 0, sm1 = 0; for (auto p : pr) { long long x = cnt(u, p); long long y = cnt(v, p); (ans *= repo[abs(x - y)]) %= mod; if (x < y) sm1 += y - x; if (x > y) sm2 += x - y; } (ans *= (fac[sm1] * fac[sm2]) % mod) %= mod; cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; int tab[300000]; vector<int> numbers; int main() { int n; cin >> n; numbers.resize(n + 10); vector<int> unused; for (int i = 1; i <= n; i++) { cin >> numbers[i]; if (numbers[i] > n || numbers[i] < 1) { unused.push_back(i); } else if (tab[numbers[i]] == 0) { tab[numbers[i]] = i; } else { unused.push_back(i); } } for (int i = 1; i <= n; i++) { if (tab[i] == 0) { tab[i] = unused.back(); unused.pop_back(); } } for (int i = 1; i <= n; i++) { numbers[tab[i]] = i; } for (int i = 1; i <= n; i++) { cout << numbers[i] << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long n, k, bottom, top; cin >> n >> k; bottom = 1; top = n; for (long i = 0; i < k - 1; i++) { if (i % 2 == 0) { cout << bottom << ; bottom++; } else { cout << top << ; top--; } } long sum, val; if ((k - 1) % 2 == 0) { val = bottom; sum = 1; } else { val = top; sum = -1; } for (long i = 0; i <= n - k; i++) { cout << val << ; val += sum; } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; int main() { int n, m; cin >> n >> m; int ret = 0; while (n--) { char str[1009]; int cnt = 0; scanf( %s , str); int flag = 1; for (int i = 0; str[i]; i++) { if (str[i] == 4 || str[i] == 7 ) { cnt++; if (cnt > m) { flag = 0; break; } } } if (flag == 1) { ret++; } } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; unordered_map<int, int> f[N]; int n, m, k, ans, p[N], sx[N], sy[N]; inline int sol(int x, int y) { if (f[x].count(y)) return f[x][y]; int t; printf( ? %d %d n , x, y), fflush(stdout), scanf( %d , &t); return f[x][y] = t; } inline vector<int> solve(int n, int m, vector<int>& x, vector<int>& y) { if (n >= m) { if (n == 1) { vector<int> z; z.resize(1), z[0] = 1; ans = min(ans, sol(x[0], y[0])); return z; } else { vector<int> a, b; for (int i = 0; i < n; i += 2) a.push_back(x[i]); for (int i = 0; i < m; i++) b.push_back(y[i]); vector<int> z = solve((n + 1) / 2, m, a, b), q; z.push_back(m); int k = 0; for (int i = 0; i < n; i++) { if (i % 2 == 0) q.push_back(z[k++]); else { int sum = 1000000001, pos = 0; for (int c = z[k - 1]; c <= z[k]; c++) { int g = sol(x[i], y[c - 1]); if (sum > g) sum = g, pos = c; } q.push_back(pos), ans = min(ans, sum); } } return q; } } else { int l = 1; sx[l] = 1, sy[l] = 1; for (int i = 2; i <= m; i++) { while (l > 0) { int a = sol(x[sx[l] - 1], y[sy[l] - 1]), b = sol(x[sx[l] - 1], y[i - 1]); if (a > b) l--; else break; } if (sx[l] != n) l++, sx[l] = sx[l - 1] + 1, sy[l] = i; } vector<int> a, b, w; for (int i = 0; i < n; i++) a.push_back(x[i]); for (int i = 1; i <= l; i++) b.push_back(y[sy[i] - 1]), w.push_back(sy[i]); vector<int> z = solve(n, l, a, b), q; for (int i = 0; i < w.size(); i++) p[i + 1] = w[i]; for (int i = 0; i < z.size(); i++) q.push_back(p[z[i]]); return q; } } int main() { cin >> n >> m; vector<int> a, b; a.resize(n), b.resize(m), ans = 1000000000; for (int i = 0; i < n; i++) a[i] = i + 1; for (int i = 0; i < m; i++) b[i] = i + 1; solve(n, m, a, b); printf( ! %d n , ans); return 0; } |
module asyc_sub_tb;
reg reset = 1;
reg button = 0;
reg clk = 0;
wire [6:0] leds;
asyc_sub sub1(leds, reset, button, clk);
initial begin
$monitor($time, " reset: %b, button: %b, digit: %b, leds: %b",
reset, button, sub1.digit, leds);
#0 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#10 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
end
initial forever #1 clk <= ~clk;
initial #400 $finish;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_BEHAVIORAL_PP_V |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int arr[2005]; long long int dp[2005][2005]; long long int n, h; long long int calc(long long int id, long long int prev) { if (id == n + 1) { return !prev; } long long int ans = dp[id][prev]; if (ans != -1) { return ans; } long long int val = arr[id] + prev; ans = 0; if (val == h) { ans = calc(id + 1, prev); if (prev) { ans = (ans + (prev * calc(id + 1, prev - 1)) % 1000000007) % 1000000007; } } else if (val == h - 1) { ans = calc(id + 1, prev + 1); ans = (ans + calc(id + 1, prev)) % 1000000007; ans = (ans + (prev * calc(id + 1, prev)) % 1000000007) % 1000000007; } return (dp[id][prev] = ans); } int main() { memset(dp, -1, sizeof(dp)); scanf( %lld , &n); scanf( %lld , &h); long long int i; for (i = 1; i <= n; i++) { scanf( %lld , &arr[i]); } long long int ans = calc(1, 0); printf( %lld , ans); ; printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long long lo; typedef vector<lo> vl; typedef vector<lo> vll; typedef vector<vl> vvl; template <typename T> ostream &operator<<(ostream &o, vector<T> v) { if (v.size() > 0) o << v[0]; for (unsigned i = 1; i < v.size(); i++) o << << v[i]; return o << n ; } template <typename U, typename V> ostream &operator<<(ostream &o, pair<U, V> p) { return o << ( << p.first << , << p.second << ) ; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (unsigned i = 0; i < v.size(); i++) in >> v[i]; return in; } template <typename T> istream &operator>>(istream &in, pair<T, T> &p) { in >> p.first; in >> p.second; return in; } string s; lo len[203][2]; lo dp[203][203][203][2]; lo cal(string &t) { for (lo i = t.size(); i > 0; i--) { if (s.substr(0, i) == t.substr(t.size() - i, i)) return i; } return 0; } void add(lo &a, lo b) { a += b; if (a >= 1000000007) a -= 1000000007; if (a < 0) a += 1000000007; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(20); lo n, ssz; cin >> n >> s; ssz = s.size(); if (s[0] == ( ) len[0][0] = 1; else len[0][1] = 1; string pref; for (lo i = (0); i < (lo)ssz; i++) { pref += s[i]; pref += ( ; len[i + 1][0] = cal(pref); pref.pop_back(); pref += ) ; len[i + 1][1] = cal(pref); pref.pop_back(); } dp[0][0][0][0] = 1; for (lo i = (0); i < (lo)2 * n; i++) { for (lo(j) = 0; (j) < (n + 1); (j)++) { for (lo(pos) = 0; (pos) < (ssz + 1); (pos)++) { for (lo(f) = 0; (f) < (2); (f)++) { if (dp[i][j][pos][f] == 0) continue; if (j + 1 <= n) add(dp[i + 1][j + 1][len[pos][0]][f | (len[pos][0] == ssz)], dp[i][j][pos][f]); if (j > 0) add(dp[i + 1][j - 1][len[pos][1]][f | (len[pos][1] == ssz)], dp[i][j][pos][f]); } } } } lo ans = 0; for (lo i = (0); i < (lo)ssz + 1; i++) add(ans, dp[2 * n][0][i][1]); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 7; const long long inf = 0x3f3f3f3f; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { double pi = 3.1415926535897932384626433832795028841971, n; cin >> n; long long sum = n / 2; double x = 0.5 / tan(pi / (n * 2)), y = 0.5 / sin(pi / (n * 2)); printf( %.10lf n , x * 2); } return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Top level module for a full setup with DUCs and DDCs
// Uncomment the following to include optional circuitry
`include "mrfm.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module mrfm
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
output wire [13:0] tx_b,
output wire TXSYNC_A,
output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [2:0] usbctl,
output wire [1:0] usbrdy,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
inout wire [15:0] io_rx_b
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire tx_underrun, rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = tx_underrun;
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
assign clk64 = master_clk;
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
/////////////////////////////////////////////////////////////////////////////////////////////////////
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Signal Processing Chain
reg [15:0] adc0;
wire [15:0] dac0;
wire [15:0] i,q,ip,qp;
wire strobe_out;
wire sync_out;
always @(posedge clk64)
adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0};
wire [15:0] adc0_corr;
rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr),
.serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0));
//wire [63:0] filt_debug = 64'd0;
mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out),
.i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out),
.debugbus( /* filt_debug */ ));
wire txsync = 1'b0;
assign TXSYNC_A = txsync;
assign TXSYNC_B = txsync;
assign tx_a = dac0[15:2];
//////////////////////////////////////////////////////////////////////////////////////////////////
// Data Collection on RX Buffer
assign rx_numchan[0] = 1'b0;
setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),
.in(serial_data),.out(rx_numchan[3:1]));
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(i),.ch_1(q),
.ch_2(ip),.ch_3(qp),
.ch_4(16'd0),.ch_5(16'd0),
.ch_6(16'd0),.ch_7(16'd0),
.rxclk(clk64),.rxstrobe(strobe_out),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.debugbus(rx_debugbus) );
//////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities = 32'd2;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) );
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
.debug_0({15'd0,sync_out}), //filt_debug[63:48]),
.debug_1({15'd0,sync_out}), //filt_debug[47:32]),
.debug_2({15'd0,sync_out}), //filt_debug[31:16]),
.debug_3({15'd0,sync_out}), //filt_debug[15:0]),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
endmodule // mrfm
|
#include <bits/stdc++.h> using namespace std; long long int n, k, m, d; int main() { std::ios::sync_with_stdio(false); long long int best = -1; cin >> n >> k >> m >> d; int x; long long int pre = m; long long int ans = 0; for (int cycles = 1; cycles <= d; cycles++) { long long int peeps = (cycles - 1) * k + 1; long long int eachCandy = min(m, n / peeps); if (eachCandy == 0) break; ans = max(ans, eachCandy * cycles); } cout << ans; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverybkb_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverybkb_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverybkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
contact_discoverybkb_ram contact_discoverybkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_32x16_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_32_32x16_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [31:0] data;
input wren;
input [3:0] wraddress;
input [3:0] rdaddress;
input [3:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 32,
altsyncram_component.widthad_a = 4,
altsyncram_component.numwords_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.widthad_b = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 4,
altsyncram_component.byte_size = 8,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.power_up_uninitialized = "FALSE";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_32x16_be_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; const long long LINF = 1e18; const long long MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const int MAXN = 200050; int a[MAXN], cnt[105]; unordered_map<int, int> mp; void solve(int T) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); cnt[a[i]]++; } int maxx = 0, idx; for (int i = 1; i <= 100; i++) { if (cnt[i] > maxx) { maxx = cnt[i]; idx = i; } } int tmp = 0; for (int i = 1; i <= 100; i++) { if (cnt[i] == maxx) tmp++; } if (tmp >= 2) { printf( %d n , n); return; } int ans = 0; for (int i = 1; i <= 100; i++) { if (i == idx) continue; mp.clear(); mp[idx] = 0; int sum = 0; for (int j = 1; j <= n; j++) { if (a[j] == idx) sum++; else if (a[j] == i) sum--; if (sum == 0) ans = max(ans, j); else if (mp[sum]) { ans = max(ans, j - mp[sum]); } else mp[sum] = j; } } printf( %d , ans); } signed main() { int t = 1; for (int i = 1; i <= t; i++) { solve(i); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_2_V
`define SKY130_FD_SC_HS__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_PP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int t, n, m, k, a[105][105], h, a1, a2, cnt, ans[105][105], pos, ch; char c[105][105]; string s; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); cin >> t; while (t--) { h = 0; pos = 0; cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> c[i][j]; if (c[i][j] == R ) { a[i][j] = 1; h++; } else { a[i][j] = 0; } } } a1 = h % k; a2 = k - h % k; cnt = 0; ch = 0; for (int i = 0; i < n; i++) { if (i % 2 == 0) { for (int j = 0; j < m; j++) { if (ch) { if (a[i][j] == 0) { ans[i][j] = pos; } else { pos++; ans[i][j] = pos; cnt++; ch = 0; } if (a1 == 0) { if (cnt == h / k) { ch = 1; cnt = 0; } } } else { if (a[i][j]) { cnt++; } ans[i][j] = pos; if (a1 > 0) { if (cnt == h / k + 1) { cnt = 0; ch = 1; a1--; } } else { if (cnt == h / k) { cnt = 0; ch = 1; } } } } } else { for (int j = m - 1; j >= 0; j--) { if (ch) { if (a[i][j] == 0) { ans[i][j] = pos; } else { pos++; ans[i][j] = pos; cnt++; ch = 0; } if (a1 == 0) { if (cnt == h / k) { ch = 1; cnt = 0; } } } else { if (a[i][j]) { cnt++; } ans[i][j] = pos; if (a1 > 0) { if (cnt == h / k + 1) { cnt = 0; a1--; ch = 1; } } else { if (cnt == h / k) { cnt = 0; ch = 1; } } } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (ans[i][j] <= 9) { cout << ans[i][j]; } else if (ans[i][j] <= 35) { char cc = ans[i][j] - 10 + a ; cout << cc; } else { char cc = ans[i][j] - 36 + A ; cout << cc; } } cout << n ; } } } |
/*
Bank of GPRs.
00..0F: R0..R15
10..1F: CS0..CS15
20..2F: F0L..F15L
30..3F: F16L..F31L
40..4F: R0H..R15H
50..5F: CC0..CC15
60..6F: F0H..F15H
70..7F: F16H..F31H
Special Cases (Handled Externally)
58: Opcode D
59: Opcode S
5A: Opcode T
5B: Opcode Imm
5F: ZZR (Always read as Zero)
Mapping for BJX1:
FR0 =F0H , FR1 =F0L , XF0 =F1H , XF1 =F1L ,
FR2 =F2H , FR3 =F2L , XF2 =F3H , XF3 =F3L ,
FR4 =F4H , FR5 =F4L , XF4 =F5H , XF5 =F5L ,
FR6 =F6H , FR7 =F6L , XF6 =F7H , XF7 =F7L ,
FR8 =F8H , FR9 =F8L , XF8 =F9H , XF9 =F9L ,
FR10=F10H, FR11=F10L, XF10=F11H, XF11=F11L,
FR12=F12H, FR13=F12L, XF12=F13H, XF13=F13L,
FR14=F14H, FR15=F14L, XF14=F15H, XF15=F15L,
...
CS0=MACH
CS1=MACL
CS2=PR
CS3=SGR
CS4=?
CS5=FPUL
CS6=FPSCR
CS7=?
..
CS14=?
CS15=DBR
CC0=SR
CC1=GBR
CC2=VBR
CC3=SSR
CC4=SPC
CC5=?
CC6=?
CC7=PC
CC8 =R0_B
..
CC15=R7_B
*/
parameter[5:0] REGS_R0 = 6'h00;
parameter[5:0] REGS_R15 = 6'h0F;
parameter[5:0] REGS_F0 = 6'h20;
parameter[5:0] REGS_F15 = 6'h2F;
parameter[5:0] REGS_F16 = 6'h30;
parameter[5:0] REGS_F31 = 6'h3F;
// parameter[5:0] REGS_PR = 6'h12;
// parameter[3:0] CREG_SR = 4'h00;
// parameter[3:0] CREG_PC = 4'h0E;
// parameter[4:0] CREG_LR = 5'h01;
parameter[6:0] REG_R0 = 7'h00;
parameter[6:0] REG_R15 = 7'h0F;
parameter[6:0] REG_F0 = 7'h20;
parameter[6:0] REG_F15 = 7'h2F;
parameter[6:0] REG_F16 = 7'h30;
parameter[6:0] REG_F31 = 7'h3F;
parameter[6:0] REG_MACH = 7'h10;
parameter[6:0] REG_MACL = 7'h11;
parameter[6:0] REG_PR = 7'h12;
parameter[6:0] REG_SGR = 7'h13;
parameter[6:0] REG_FPUL = 7'h15;
parameter[6:0] REG_FPSCR = 7'h16;
parameter[6:0] REG_DBR = 7'h1F;
parameter[6:0] REG_SR = 7'h50;
parameter[6:0] REG_GBR = 7'h51;
parameter[6:0] REG_VBR = 7'h52;
parameter[6:0] REG_SSR = 7'h53;
parameter[6:0] REG_SPC = 7'h54;
parameter[6:0] REG_PC = 7'h57;
parameter[6:0] REG_IMM = 7'h5E;
parameter[6:0] REG_ZZR = 7'h5F;
module GpReg(
clk,
isWrD,
isQwD,
idRegD,
dataD,
idReg1,
data1,
idReg2,
data2,
idReg3,
data3
);
input clk; //clock
input isWrD; //Is Write
input isQwD; //Is QuadWord
input[6:0] idRegD;
input[63:0] dataD;
input[6:0] idReg1;
input[6:0] idReg2;
input[6:0] idReg3;
output[63:0] data1;
output[63:0] data2;
output[63:0] data3;
reg[31:0] regs_lo[64]; //GPRs and FPRs
reg[31:0] regs_hi[64];
// reg[31:0] sreg_lo[16]; //System Registers
// reg[31:0] sreg_hi[16];
reg[31:0] creg_lo[16]; //Control Registers
reg[31:0] creg_hi[16];
reg[63:0] reg_pc; //PC register, special
reg[63:0] reg_pr; //PR register, special
reg[63:0] reg_sr; //SR register, special
// reg[6:0] tIdRegDLo;
// reg[6:0] tIdRegDHi;
// reg[6:0] tIdReg1Lo;
// reg[6:0] tIdReg1Hi;
// reg[6:0] tIdReg2Lo;
// reg[6:0] tIdReg2Hi;
// reg[6:0] tIdReg3Lo;
// reg[6:0] tIdReg3Hi;
reg[5:0] tIdRegDLo;
reg[5:0] tIdReg1Lo;
reg[5:0] tIdReg2Lo;
reg[5:0] tIdReg3Lo;
// reg rb_curBank;
// reg rb_reqBank;
// reg rb_isSwap;
// reg[3:0] rb_tSwapBank;
// reg[3:0] rb_tNextSwapBank;
always @ (clk) begin
// tIdRegDLo = idRegD;
// tIdRegDHi = idRegD | (7'h40);
// if(rb_isSwap)
// begin
// if(rb_tSwapBank[0])
// end
tIdRegDLo = idRegD[5:0];
tIdReg1Lo = idReg1[5:0];
tIdReg2Lo = idReg2[5:0];
tIdReg3Lo = idReg3[5:0];
// if(idReg1!=REG_ZZR)
if(idReg1[5:4]!=2'b01)
begin
if(idReg1[6])
begin
data1[31: 0] = regs_hi[tIdReg1Lo];
data1[63:32] = 32'h0000_0000 ;
end
else
begin
data1[31: 0] = regs_lo[tIdReg1Lo];
data1[63:32] = regs_hi[tIdReg1Lo];
end
end
else
begin
if(idReg1[6])
begin
data1[31: 0] = creg_lo[tIdReg1Lo[3:0]];
data1[63:32] = creg_hi[tIdReg1Lo[3:0]];
end
else
begin
data1[31: 0] = regs_lo[tIdReg1Lo];
data1[63:32] = regs_hi[tIdReg1Lo];
end
// data1 = 64'h0000_0000_0000_0000;
end
// if(idReg2!=REG_ZZR)
if(idReg2[5:4]!=2'b01)
begin
if(idReg2[6])
begin
data2[31: 0] = regs_hi[tIdReg2Lo];
data2[63:32] = 32'h0000_0000 ;
end
else
begin
data2[31: 0] = regs_lo[tIdReg2Lo];
data2[63:32] = regs_hi[tIdReg2Lo];
end
end
else
begin
if(idReg2[6])
begin
data2[31: 0] = creg_lo[tIdReg2Lo[3:0]];
data2[63:32] = creg_hi[tIdReg2Lo[3:0]];
end
else
begin
data2[31: 0] = regs_lo[tIdReg2Lo];
data2[63:32] = regs_hi[tIdReg2Lo];
end
// data2 = 64'h0000_0000_0000_0000;
end
// if(idReg3!=REG_ZZR)
if(idReg3[5:4]!=2'b01)
begin
if(idReg3[6])
begin
data3[31: 0] = regs_hi[tIdReg3Lo];
data3[63:32] = 32'h0000_0000 ;
end
else
begin
data3[31: 0] = regs_lo[tIdReg3Lo];
data3[63:32] = regs_hi[tIdReg3Lo];
end
end
else
begin
if(idReg3[6])
begin
data3[31: 0] = creg_lo[tIdReg3Lo[3:0]];
data3[63:32] = creg_hi[tIdReg3Lo[3:0]];
end
else
begin
data3[31: 0] = regs_lo[tIdReg3Lo];
data3[63:32] = regs_hi[tIdReg3Lo];
end
// data3 = 64'h0000_0000_0000_0000;
end
end
always @ (posedge clk) begin
if(isWrD==1'b1)
begin
if(idRegD[5:4]!=2'b01)
begin
if(isQwD==1'b1)
begin
$display("R[%X]Q=%X", tIdRegDLo, dataD);
regs_lo[tIdRegDLo] <= dataD[31:0];
regs_hi[tIdRegDLo] <= dataD[63:32];
end
else
begin
$display("R[%X]D=%X", tIdRegDLo, dataD);
if(idRegD[6])
regs_hi[tIdRegDLo] <= dataD[31:0];
else
regs_lo[tIdRegDLo] <= dataD[31:0];
end
end
else
begin
$display("CSR[%X]=%X", tIdRegDLo, dataD);
if(idRegD[6])
begin
creg_lo[tIdRegDLo[3:0]] <= dataD[31:0];
if(isQwD==1'b1)
creg_hi[tIdRegDLo[3:0]] <= dataD[63:32];
end
else
begin
// sreg_lo[tIdRegDLo[3:0]] <= dataD[31:0];
// if(isQwD==1'b1)
// sreg_hi[tIdRegDLo[3:0]] <= dataD[63:32];
regs_lo[tIdRegDLo] <= dataD[31:0];
if(isQwD==1'b1)
regs_hi[tIdRegDLo] <= dataD[63:32];
end
end
end
// if(rb_isSwap)
// begin
// rb_isSwap <= rb_isNextSwap;
// rb_tSwapBank = rb_tNextSwapBank;
// end
// else if(rb_curBank!=rb_reqBank)
// begin
// rb_isSwap <= 1;
// rb_tSwapBank = 15;
// end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 500005; long long int a[N], l[N], r[N]; long long int vl[N], vr[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); stack<long long int> s1, s2; long long int nu; cin >> nu; long long int pos = 0; for (long long int i = 1; i <= nu; i++) cin >> a[i]; for (long long int i = 1; i <= nu; i++) { while (!s1.empty() && a[s1.top()] > a[i]) s1.pop(); if (s1.empty()) l[i] = 0; else l[i] = s1.top(); vl[i] = vl[l[i]] + (i - l[i]) * a[i]; s1.push(i); } long long int mx = -1; for (long long int i = nu; i >= 1; i--) { while (!s2.empty() && a[s2.top()] > a[i]) s2.pop(); if (s2.empty()) r[i] = nu + 1; else r[i] = s2.top(); vr[i] = vr[r[i]] + (r[i] - i) * a[i]; s2.push(i); if ((vl[i] + vr[i] - a[i]) > mx) { mx = vl[i] + vr[i] - a[i]; pos = i; } } long long int x = a[pos]; for (long long int i = pos - 1; i >= 1; i--) { if (a[i] > x) a[i] = x; else x = a[i]; } x = a[pos]; for (long long int i = pos + 1; i <= nu; i++) { if (a[i] > x) a[i] = x; else x = a[i]; } for (long long int i = 1; i <= nu; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, f = 0, ans, m, a1[20], flag = 0, a2[20], b1[20], b2[20], num[20] = {0}, c = 0; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a1[i] >> a2[i]; for (int i = 0; i < m; i++) cin >> b1[i] >> b2[i]; for (int i = 0; i < n; i++) { int cura = 0, curb = 0; for (int j = 0; j < m; j++) { if ((a1[i] == b1[j] && a2[i] != b2[j]) || (a1[i] == b2[j] && a2[i] != b1[j])) num[a1[i]]++, cura++; if ((a2[i] == b1[j] && a1[i] != b2[j]) || (a2[i] == b2[j] && a1[i] != b1[j])) num[a2[i]]++, curb++; } if (cura > 0 && curb > 0) flag = 1; } for (int i = 0; i < m; i++) { int cura = 0, curb = 0; for (int j = 0; j < n; j++) { if ((b1[i] == a1[j] && b2[i] != a2[j]) || (b1[i] == a2[j] && b2[i] != a1[j])) cura++; if ((b2[i] == a1[j] && b1[i] != a2[j]) || (b2[i] == a2[j] && b1[i] != a1[j])) curb++; } if (cura > 0 && curb > 0) flag = 1; } for (int i = 0; i < 15; i++) if (num[i] > 0) c++, f = i; if (flag) cout << -1 << endl; else if (c > 1) cout << 0 << endl; else cout << f << endl; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_NegPi_To_Pi.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_NegPi_To_Pi
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity/Wrap_NegPi_To_Pi
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_NegPi_To_Pi
(
position,
wrap
);
input signed [18:0] position; // sfix19_En14
output signed [17:0] wrap; // sfix18_En15
wire signed [18:0] Constant1_out1; // sfix19_En14
wire signed [18:0] Constant_out1; // sfix19_En14
wire Relational_Operator1_relop1;
wire position_less_than_pi;
wire signed [19:0] Data_Type_Conversion_out1; // sfix20_En14
wire signed [18:0] Constant3_out1; // sfix19_En14
wire Relational_Operator_relop1;
wire position_greater_than_pi;
wire signed [19:0] Add1_add_cast; // sfix20_En14
wire signed [19:0] Add1_add_cast_1; // sfix20_En14
wire signed [19:0] wrap_position_less_than_neg_pi; // sfix20_En14
wire signed [19:0] Switch2_out1; // sfix20_En14
wire signed [18:0] Constant2_out1; // sfix19_En14
wire signed [19:0] Add_sub_cast; // sfix20_En14
wire signed [19:0] Add_sub_cast_1; // sfix20_En14
wire signed [19:0] wrap_position_greater_than_pi; // sfix20_En14
wire signed [19:0] Switch1_out1; // sfix20_En14
wire signed [17:0] Angle_Data_Type_out1; // sfix18_En15
// Wrap Angle
// <S9>/Constant1
assign Constant1_out1 = 19'sb0001100100100010000;
// <S9>/Constant
assign Constant_out1 = 19'sb1110011011011110000;
// <S9>/Relational Operator1
assign Relational_Operator1_relop1 = (position < Constant_out1 ? 1'b1 :
1'b0);
assign position_less_than_pi = Relational_Operator1_relop1;
// <S9>/Data Type Conversion
assign Data_Type_Conversion_out1 = position;
// <S9>/Constant3
assign Constant3_out1 = 19'sb0011001001000100000;
// <S9>/Relational Operator
assign Relational_Operator_relop1 = (position >= Constant1_out1 ? 1'b1 :
1'b0);
assign position_greater_than_pi = Relational_Operator_relop1;
// <S9>/Add1
assign Add1_add_cast = position;
assign Add1_add_cast_1 = Constant3_out1;
assign wrap_position_less_than_neg_pi = Add1_add_cast + Add1_add_cast_1;
// <S9>/Switch2
assign Switch2_out1 = (position_less_than_pi == 1'b0 ? Data_Type_Conversion_out1 :
wrap_position_less_than_neg_pi);
// <S9>/Constant2
assign Constant2_out1 = 19'sb0011001001000100000;
// <S9>/Add
assign Add_sub_cast = position;
assign Add_sub_cast_1 = Constant2_out1;
assign wrap_position_greater_than_pi = Add_sub_cast - Add_sub_cast_1;
// <S9>/Switch1
assign Switch1_out1 = (position_greater_than_pi == 1'b0 ? Switch2_out1 :
wrap_position_greater_than_pi);
// <S9>/Angle_Data_Type
assign Angle_Data_Type_out1 = {Switch1_out1[16:0], 1'b0};
assign wrap = Angle_Data_Type_out1;
endmodule // controllerHdl_Wrap_NegPi_To_Pi
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_PP_V |
module var15_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O;
output valid;
wire [7:0] min_value = 8'd120;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8
+ M * 8'd16
+ N * 8'd18
+ O * 8'd18;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13
+ M * 8'd8
+ N * 8'd14
+ O * 8'd22;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2
+ M * 8'd9
+ N * 8'd28
+ O * 8'd19;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The ITCM-SRAM module to implement ITCM SRAM
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_ITCM //{
module e203_itcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_ITCM_RAM_AW-1:0] addr,
input [`E203_ITCM_RAM_MW-1:0] wem,
input [`E203_ITCM_RAM_DW-1:0] din,
output [`E203_ITCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
sirv_gnrl_ram #(
`ifndef E203_HAS_ECC//{
.FORCE_X2ZERO(0),
`endif//}
.DP(`E203_ITCM_RAM_DP),
.DW(`E203_ITCM_RAM_DW),
.MW(`E203_ITCM_RAM_MW),
.AW(`E203_ITCM_RAM_AW)
) u_e203_itcm_gnrl_ram(
.sd (sd ),
.ds (ds ),
.ls (ls ),
.rst_n (rst_n ),
.clk (clk ),
.cs (cs ),
.we (we ),
.addr(addr),
.din (din ),
.wem (wem ),
.dout(dout)
);
endmodule
`endif//}
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) const int MOD = 1000000007; const int N = 1E5 + 15; const int maxn = 2e5 + 14; const int INF = (1 << 30) - 1; const int letter = 130; const double pi = acos(-1.0); const double eps = 1e-8; using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, q; long long a[N], b[N]; long long L[N], R[N]; int s[N], top; void solve(int l, int r) { int cnt = 0; for (int i = l; i < r; i++) b[++cnt] = a[i]; b[0] = INF; b[cnt + 1] = INF; s[top = 0] = 0; for (int i = 1; i <= cnt + 1; i++) { if (b[i] <= b[s[top]]) s[++top] = i; else { while (top >= 0 && b[s[top]] < b[i]) R[s[top]] = i - s[top], top--; s[++top] = i; } } s[top = 0] = cnt + 1; for (int i = cnt; i >= 0; i--) { if (b[i] < b[s[top]]) s[++top] = i; else { while (top >= 0 && b[s[top]] <= b[i]) L[s[top]] = s[top] - i, top--; s[++top] = i; } } long long ans = 0; for (int i = 1; i <= cnt; i++) { ans += L[i] * R[i] * b[i]; } printf( %I64d n , ans); } int main() { int x, y; scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) scanf( %I64d , a + i); for (int i = 1; i < n; i++) a[i] = abs(a[i + 1] - a[i]); while (q--) { scanf( %d%d , &x, &y); solve(x, y); } return 0; } |
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module dbg_ila (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20,
probe21,
probe22,
probe23,
probe24,
probe25,
probe26
);
input clk;
input [63 : 0] probe0;
input [63 : 0] probe1;
input [0 : 0] probe2;
input [0 : 0] probe3;
input [0 : 0] probe4;
input [0 : 0] probe5;
input [0 : 0] probe6;
input [63 : 0] probe7;
input [0 : 0] probe8;
input [0 : 0] probe9;
input [0 : 0] probe10;
input [0 : 0] probe11;
input [63 : 0] probe12;
input [0 : 0] probe13;
input [0 : 0] probe14;
input [0 : 0] probe15;
input [0 : 0] probe16;
input [0 : 0] probe17;
input [0 : 0] probe18;
input [8 : 0] probe19;
input [7 : 0] probe20;
input [2 : 0] probe21;
input [2 : 0] probe22;
input [0 : 0] probe23;
input [0 : 0] probe24;
input [7 : 0] probe25;
input [3 : 0] probe26;
endmodule
|
#include <bits/stdc++.h> using namespace std; int fact(vector<int> x, long long t) { if (t == 1) return 1; vector<long long> num(x.begin(), x.end()); stringstream s; string tmp; s << t; s >> tmp; int count = 0; for (int i = 0; i < num.size(); i++) { stringstream ss; string temp; ss << num[i]; ss >> temp; bool flag = false; for (int j = 0; j < temp.size(); j++) { for (int k = 0; k < tmp.size(); k++) if (temp[j] == tmp[k]) { count++; flag = true; break; } if (flag) break; } } return count; } int main() { long long n; cin >> n; long long t = n; vector<int> factors; long long i; factors.push_back(1); for (i = 2; i < sqrt(n); i++) { if (n % i == 0) { factors.push_back(n / i); factors.push_back(i); } } if (i * i == n) { factors.push_back(i); } factors.push_back(n); cout << fact(factors, t); return 0; } |
#include <bits/stdc++.h> using namespace std; double f(double z, double first) { int k = 0; double w; while (first > 2 * z) { w = z; while (2 * w < first) w *= 2, k += 2; first -= w; } if (first <= z) return first; else return 2 * z - first; } int main() { int b, c; double a, lo, hi, mid, w; int k; while (scanf( %d %d , &c, &b) == 2) { a = c; if (c < b) { printf( -1 n ); } else if (c == b) { printf( %d n , b); } else { k = ((int)(floor(a / b + 1e-9) + 1e-9 - 1)) / 2; hi = a / (2 * k + 1); lo = a / (2 * k + 2); k = 60; while (k--) { mid = (lo + hi) / 2.0; w = f(mid, a); if (w <= b) lo = mid; else hi = mid; } printf( %.10lf n , mid); } } return 0; } |
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const long long INFll = 1ll * 1000000000 * 1000000000; const long double PI = 3.141592653589793238462643383279502884197169399375105820974944; int mul(int a, int b, int mod = 1000000007) { return int(a * 1ll * b % mod); } int norm(int a, int mod = 1000000007) { while (a >= mod) a -= mod; while (a < 0) a += mod; return a; } int powmod(int x, int y, int mod = 1000000007) { int res = 1; while (y > 0) { if (y & 1) res = mul(res, x, mod); x = mul(x, x, mod); y = y >> 1; } return res; } int inv(int a, int mod = 1000000007) { return powmod(a, mod - 2); } int main() { fast(); int n; cin >> n; vector<int> dp((1 << 22), -1), a(n); for (int i = 0; i < n; i++) { cin >> a[i]; dp[a[i]] = a[i]; } int p = (1 << 22); for (int i = 0; i < p; i++) { if (dp[i] != -1) for (int j = 0; j < 22; j++) { if ((i & (1 << j)) == 0) { dp[i | (1 << j)] = dp[i]; } } } for (int i = 0; i < n; i++) { cout << dp[(1 << 22) - 1 - a[i]] << ; } return 0; } |
/*
* Author : Tom Stanway-Mayers
* Description : Pre-Fetch Unit
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_pfu
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_DEPTH_X = 2, // depth >= read latency + 2
parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1'b0} }
)
(
// global
input wire clk_i,
input wire reset_i,
// instruction cache interface
input wire ireqready_i,
output wire ireqvalid_o,
output wire [1:0] ireqhpl_o,
output wire [`RV_XLEN-1:0] ireqaddr_o, // TODO - consider bypassing the pc on a jump
output wire irspready_o,
input wire irspvalid_i,
input wire irsprerr_i,
input wire [`RV_XLEN-1:0] irspdata_i,
// decoder interface
output wire ids_dav_o, // new fetch available
input wire ids_ack_i, // ack this fetch
input wire [1:0] ids_ack_size_i, // size of this ack TODO
output wire [`RV_SOFID_RANGE] ids_sofid_o, // first fetch since vectoring
output wire [31:0] ids_ins_o, // instruction fetched
output wire ids_ferr_o, // this instruction fetch resulted in error
output wire [`RV_XLEN-1:0] ids_pc_o, // address of this instruction
// ex stage vectoring interface
input wire exs_pc_wr_i,
input wire [`RV_XLEN-1:0] exs_pc_din_i,
// pfu stage interface
input wire [1:0] exs_hpl_i
);
//--------------------------------------------------------------
// interface assignments
// ibus debt
reg ibus_debt;
wire request;
wire response;
// fifo level counter
reg [C_FIFO_DEPTH_X:0] fifo_level_q;
reg fifo_accepting;
// program counter
reg [`RV_XLEN-1:0] pc_q;
reg [`RV_XLEN-1:0] request_addr_q;
// vectoring flag register
reg vectoring_q;
// sofid register
reg [`RV_SOFID_RANGE] sofid_q;
// fifo
parameter C_SOFID_SZ = `RV_SOFID_SZ;
parameter C_FIFO_WIDTH = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;
//
parameter C_SOFID_LSB = 1 + 2 * `RV_XLEN;
parameter C_FERR_LSB = 2 * `RV_XLEN;
parameter C_FIFO_PC_LSB = `RV_XLEN;
parameter C_FIFO_INS_LSB = 0;
//
wire fifo_empty;
wire [C_FIFO_WIDTH-1:0] fifo_din;
wire [C_FIFO_WIDTH-1:0] fifo_dout;
wire [`RV_XLEN-1:0] fifo_dout_data;
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign ireqhpl_o = exs_hpl_i;
assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response);
assign ireqaddr_o = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1'b0} } };
assign irspready_o = 1'b1; //irspvalid_i; // always ready
//
assign ids_dav_o = ~fifo_empty;
assign ids_ins_o = fifo_dout_data[31:0];
//--------------------------------------------------------------
// ibus debt
//--------------------------------------------------------------
assign request = ireqvalid_o & ireqready_i;
assign response = irspvalid_i & irspready_o;
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
ibus_debt <= 1'b0;
end else begin
if (request & ~response) begin
ibus_debt <= 1'b1;
end else if (~request & response) begin
ibus_debt <= 1'b0;
end
end
end
//--------------------------------------------------------------
// fifo level counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else begin
//*
if (exs_pc_wr_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else
/**/
if (request & ~ids_ack_i) begin
fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end else if (~request & ids_ack_i) begin
fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
always @ (*) begin
if (|fifo_level_q) begin
fifo_accepting = 1'b1;
end else begin
fifo_accepting = 1'b0;
end
end
//--------------------------------------------------------------
// program counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
end else begin
if (exs_pc_wr_i) begin
pc_q <= exs_pc_din_i;
end else if (request) begin
pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1'b0} }, 1'b1, { `RV_XLEN_X-3 {1'b0} } };
end
end
end
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (request) begin
request_addr_q <= pc_q;
end
end
//--------------------------------------------------------------
// vectoring flag register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
vectoring_q <= 1'b0;
end else begin
if (exs_pc_wr_i) begin
vectoring_q <= 1'b1;
end else if (request) begin
vectoring_q <= 1'b0;
end
end
end
//--------------------------------------------------------------
// sofid register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sofid_q <= `RV_SOFID_RUN;
end else begin
if (vectoring_q & request) begin
sofid_q <= `RV_SOFID_JUMP;
end else if (response) begin
sofid_q <= `RV_SOFID_RUN;
end
end
end
//--------------------------------------------------------------
// fifo
//--------------------------------------------------------------
assign fifo_din[ C_SOFID_LSB +: C_SOFID_SZ] = sofid_q; // TODO
assign fifo_din[ C_FERR_LSB +: 1] = irsprerr_i;
assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN] = request_addr_q;
assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN] = irspdata_i;
//
assign ids_sofid_o = fifo_dout[ C_SOFID_LSB +: C_SOFID_SZ];
assign ids_ferr_o = fifo_dout[ C_FERR_LSB +: 1];
assign ids_pc_o = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];
assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];
//
merlin_fifo
#(
.C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
.C_FIFO_WIDTH (C_FIFO_WIDTH),
.C_FIFO_DEPTH_X (C_FIFO_DEPTH_X)
) i_merlin_fifo (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// control and status
.flush_i (exs_pc_wr_i | vectoring_q),
.empty_o (fifo_empty),
.full_o (),
// write port
.wr_i (response),
.din_i (fifo_din),
// read port
.rd_i (ids_ack_i),
.dout_o (fifo_dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using Int = long long; constexpr static int mod = 1e9 + 7; constexpr static int inf = (1 << 30) - 1; constexpr static Int infll = (1LL << 61) - 1; int Competitive_Programming = (ios_base::sync_with_stdio(false), cin.tie(nullptr), cout << fixed << setprecision(15), 0); #pragma GCC target( avx2 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string &s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } int func(string &s) { int ret = 0, ctr = 0, mi = inf; for (int i = 0; i < s.size(); i++) { if (s[i] == ( ) ctr++; else ctr--; mi = min(ctr, mi); } ctr = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == ( ) ctr++; else ctr--; if (ctr == mi) ret++; } return ret; } int main() { int N; cin >> N; string s; cin >> s; int op = 0, ed = 0; for (int i = 0; i < N; i++) { if (s[i] == ( ) op++; else ed++; } if (op != ed) { cout << 0 << n ; cout << 1 << << 1 << n ; return 0; } int ans = 0, l = 1, r = 1; for (int i = 0; i < N; i++) { for (int j = i + 1; j < N; j++) { swap(s[i], s[j]); int cnt = func(s); if (cnt > ans) { ans = cnt, l = i + 1, r = j + 1; } swap(s[i], s[j]); } } cout << ans << n ; cout << l << << r << n ; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 2e5 + 5; void solve() { long long int n, m; cin >> n >> m; vector<long long int> v(m); for (auto &it : v) cin >> it; ; vector<long long int> suf(m); long long int s = 0; for (long long int i = m - 1; i >= 0; i--) { if (i + v[i] - 1 > n - 1) { cout << -1 << n ; return; } s += v[i]; suf[i] = s; } if (s < n) { cout << -1 << n ; return; } long long int j = 0; long long int start = 0, prev = -1; vector<long long int> ans; for (long long int i = 0; i < m; i++) { cout << max(n - suf[i] + 1, i + 1) << ; } cout << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int cnt[ T + 1]; string p = AGTC ; int main() { int n; cin >> n; string s; cin >> s; for (int i = 0, __l = s.size(); i < __l; ++i) cnt[s[i]]++; int maxi = 0; for (int i = 0, __l = p.size(); i < __l; ++i) maxi = max(maxi, cnt[p[i]]); int x = 0; for (int i = 0, __l = p.size(); i < __l; ++i) x += cnt[p[i]] == maxi; long long ans = 1; for (int i = 0, __l = n; i < __l; ++i) (ans *= x) %= 1000000007; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; int n, k; string s; int main(void) { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> k; vector<int> alpha(26, 0); vector<int> cpy(26, 0); vector<int> cnt(26, 0); cin >> s; int ans = 0; for (char c : s) { alpha[c - a ]++; cpy[c - a ]++; } for (int i = 1; i <= min(n, k); i++) if (k % i == 0) for (int l = 1; l <= n; l++) { int tmp = 0; for (int a = 0; a < 26; a++) tmp += alpha[a] / l; if (tmp >= i) ans = max(ans, l * i); } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2>& p) { out << { << p.first << , << p.second << } ; return out; } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.fi > p.se; return in; } template <typename T> istream& operator>>(istream& in, vector<T>& arr) { for (auto& i : arr) in >> i; return in; } template <typename T> ostream& operator<<(ostream& out, vector<T>& arr) { for (auto i : arr) out << i + 1 << ; out << endl; return out; } const int64_t MAXN = 2e5 + 10; vector<pair<int64_t, int64_t>> mon, diam; int64_t n, c, d, t, t1; int64_t b_ans = 0; void read() { for (int64_t i(0); i < n; i++) { int64_t b, p; char c; cin >> b >> p >> c; if (c == D ) { diam.push_back({p, b}); } else { mon.push_back({p, b}); } } } void fnd() { t = 0; t1 = 0; for (int64_t i(0); i < mon.size(); i++) { if (mon[i].first <= c) { t = max(t, mon[i].second); } } for (int64_t i(0); i < diam.size(); i++) { if (diam[i].first <= d) { t1 = max(t1, diam[i].second); } } } void solve(vector<pair<int64_t, int64_t>>& mon, int64_t kek) { multiset<int64_t> s; for (int64_t i(0); i < mon.size(); i++) { s.insert(mon[i].second); } int64_t pt = (int64_t)mon.size() - 1; for (int64_t i(0); i < mon.size() && mon[i].first <= kek; i++) { while (pt >= 0 && mon[pt].first > kek - mon[i].first) { s.erase(s.find(mon[pt].second)); pt--; } if (pt >= i) { s.erase(s.find(mon[i].second)); } if (s.size() != 0) { b_ans = max(b_ans, mon[i].second + *s.rbegin()); } if (pt >= i) { s.insert(mon[i].second); } } } signed main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(); cin >> n >> c >> d; read(); sort(mon.begin(), mon.end()); sort(diam.begin(), diam.end()); fnd(); if (t != 0 && t1 != 0) { b_ans = t + t1; } solve(mon, c); solve(diam, d); cout << b_ans << endl; return 0; } |
#include <bits/stdc++.h> using ll = long long; using namespace std; int main() { ios::sync_with_stdio(false); int N, K; cin >> N >> K; ll total = N + 1; total += N; total += min(2 * (K - 1) + (N - K), 2 * (N - K) + K - 1); cout << total << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, res; scanf( %lld %lld , &n, &k); if (k <= n) { if (k % 2 == 0) res = (k - 1) / 2; else if (k % 2 == 1) res = k / 2; } else if (k > n) { if (k - n <= n) res = (n - (k - n) + 1) / 2; else if (k - n > n) res = 0; } else if (n == k) res = (n - 1) / 2; cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V |
#include <bits/stdc++.h> struct node { int mx, se, cmx; int cnt; long long sum; node() : mx(0), se(-1), cmx(0), cnt(0), sum(0) {} node(int v) : mx(v), se(-1), cmx(1), cnt(1), sum(v) {} }; node operator+(const node &a, const node &b) { node res; if (a.mx == b.mx) { res.mx = a.mx; res.se = std::max(a.se, b.se); res.cmx = a.cmx + b.cmx; } else if (a.mx > b.mx) { res.mx = a.mx; res.se = std::max(a.se, b.mx); res.cmx = a.cmx; } else { res.mx = b.mx; res.se = std::max(a.mx, b.se); res.cmx = b.cmx; } res.cnt = a.cnt + b.cnt; res.sum = a.sum + b.sum; return res; } int enlarge(int n) { int res = 1; while (res < n) { res <<= 1; } return res; } class segment_tree { int n; std::vector<node> a; std::vector<int> tag, mxtag; void node_add(int u, int v) { a[u].mx += v; a[u].se += v; a[u].sum += 1ll * v * a[u].cnt; tag[u] += v; } void node_add_mx(int u, int v) { a[u].mx += v; a[u].sum += 1ll * v * a[u].cmx; mxtag[u] += v; } void down(int u) { if (tag[u]) { node_add(u << 1, tag[u]); node_add(u << 1 | 1, tag[u]); tag[u] = 0; } if (mxtag[u]) { int lmx = a[u << 1].mx, rmx = a[u << 1 | 1].mx; if (lmx >= rmx) { node_add_mx(u << 1, mxtag[u]); } if (rmx >= lmx) { node_add_mx(u << 1 | 1, mxtag[u]); } mxtag[u] = 0; } } void modify(int u, int l, int r, int x, int v) { if (l + 1 == r) { a[u] = node(v); return; } int mid = (l + r + 1) >> 1; down(u); if (x < mid) { modify(u << 1, l, mid, x, v); } else { modify(u << 1 | 1, mid, r, x, v); } a[u] = a[u << 1] + a[u << 1 | 1]; } void add(int u, int l, int r, int L, int R, int v) { if (L <= l && r <= R) { node_add(u, v); return; } int mid = (l + r + 1) >> 1; down(u); if (L < mid) { add(u << 1, l, mid, L, R, v); } if (mid < R) { add(u << 1 | 1, mid, r, L, R, v); } a[u] = a[u << 1] + a[u << 1 | 1]; } void chmin(int u, int l, int r, int L, int R, int v) { if (a[u].mx <= v) { return; } if (L <= l && r <= R && a[u].se < v) { node_add_mx(u, v - a[u].mx); return; } int mid = (l + r + 1) >> 1; down(u); if (L < mid) { chmin(u << 1, l, mid, L, R, v); } if (mid < R) { chmin(u << 1 | 1, mid, r, L, R, v); } a[u] = a[u << 1] + a[u << 1 | 1]; } int get_cnt(int u, int l, int r, int L, int R) { if (L <= l && r <= R) { return a[u].cnt; } int mid = (l + r + 1) >> 1; down(u); if (R <= mid) { return get_cnt(u << 1, l, mid, L, R); } else if (L >= mid) { return get_cnt(u << 1 | 1, mid, r, L, R); } else { return get_cnt(u << 1, l, mid, L, R) + get_cnt(u << 1 | 1, mid, r, L, R); } } public: segment_tree(int _n) : n(_n), a(enlarge(n) << 1), tag(enlarge(n) << 1), mxtag(enlarge(n) << 1) {} void modify(int x, int v) { modify(1, 0, n, x, v); } void add(int l, int r, int v) { if (l >= r) { return; } add(1, 0, n, l, r, v); } void chmin(int l, int r, int v) { if (l >= r) { return; } chmin(1, 0, n, l, r, v); } int get_cnt(int l, int r) { if (l >= r) { return 0; } return get_cnt(1, 0, n, l, r); } long long get_sum() { return a[1].sum; } }; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); int n; std::cin >> n; std::vector<int> p(n); for (int i = 0; i < n; ++i) { int v; std::cin >> v; --v; p[v] = i; } std::vector<long long> ans(n); for (int _ = 0; _ < 2; ++_) { segment_tree T(n); for (int i = 0; i < n; ++i) { T.modify(p[i], i + 1); T.chmin(0, p[i], T.get_cnt(0, p[i])); T.add(p[i] + 1, n, 1); ans[i] += T.get_sum() - 1ll * i * (i + 1) / 2; } for (int i = 0; i < n; ++i) { p[i] = n - 1 - p[i]; } } for (int i = 0; i < n; ++i) { std::cout << ans[i] - i - 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y) { long long int res = 1; x = x; while (y > 0) { if (y & 1) res = (res * x); y = y >> 1; x = (x * x); } return res; } long long int logtwo(long long int n) { if (n == 1) return 0; return logtwo(n / 2) + 1; } vector<long long int> adj[105][105]; long long int vis[105][105]; void dfs(int par, long long int col) { for (auto child : adj[par][col]) { if (vis[child][col]) continue; vis[child][col] = vis[par][col]; dfs(child, col); } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { long long int N, M; cin >> N >> M; for (long long int i = 0; i < M; i++) { long long int a, b, c; cin >> a >> b >> c; a--; b--; adj[a][c].push_back(b); adj[b][c].push_back(a); } for (long long int i = 0; i < 105; i++) { long long int c = 1; for (long long int j = 0; j < N; j++) { if (vis[j][i]) continue; vis[j][i] = c++; dfs(j, i); } } long long int Q; cin >> Q; while (Q--) { long long int x, y; cin >> x >> y; long long int ans = 0; x--; y--; for (long long int i = 0; i < 105; i++) { if (vis[x][i] && vis[x][i] == vis[y][i]) ans++; } cout << ans << n ; } } cerr << Time : << 1000 * (long double)clock() / (long double)CLOCKS_PER_SEC << ms n ; ; } |
#include <bits/stdc++.h> using namespace std; const int N = 35050; const int inf = 1e9; int t[2 * N], lz[N], n, h, k; int dp[55][N], val[N]; pair<int, int> up[N]; int pv[N]; inline void carrot() { for (int i = int(0); i < int(n + 1); ++i) pv[i] = n; for (int i = int(n - 1); i >= int(0); i--) { up[i].first = i + 1; up[i].second = pv[val[i]]; pv[val[i]] = i + 1; } } inline void clear_trees() { memset(t, 0, sizeof(t)); memset(lz, 0, sizeof(lz)); } inline void build_trees(int row) { for (int i = int(0); i < int(n); ++i) t[i + n] = dp[row][i]; for (int i = int(n - 1); i >= int(1); i--) t[i] = max(t[i << 1], t[i << 1 | 1]); } inline void apply(int p, int val) { t[p] += val; if (p < n) lz[p] += val; } inline void build(int p) { while (p > 1) p >>= 1, t[p] = max(t[p << 1], t[p << 1 | 1]) + lz[p]; } inline void modify(int lo, int ro) { lo += n, ro += n; for (int l = lo, r = ro; l < r; l >>= 1, r >>= 1) { if (l & 1) apply(l++, 1); if (r & 1) apply(--r, 1); } build(lo); build(ro); } inline void push(int p) { for (int s = int(h); s >= int(1); s--) { int i = p >> s; if (lz[i] != 0) { apply(i << 1, lz[i]); apply(i << 1 | 1, lz[i]); lz[i] = 0; } } } inline int query(int l, int r) { push(l + n); push(r + n - 1); int res = -inf; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) res = max(res, t[l++]); if (r & 1) res = max(res, t[--r]); } return res; } inline int solve() { memset(dp, 0, sizeof(dp)); carrot(); set<int> s; for (int i = int(n - 1); i >= int(0); i--) { s.insert(val[i]); dp[1][i] = int(s.size()); } for (int num = int(2); num < int(k + 1); ++num) { clear_trees(); build_trees(num - 1); for (int i = int(n - num); i >= int(0); i--) { modify(up[i].first, up[i].second); dp[num][i] = query(i + 1, n); } } return dp[k][0]; } inline void input_random() { n = (rand() % 10) + 1; k = (rand() % n) + 1; for (int i = int(0); i < int(n); ++i) val[i] = (rand() % n) + 1; } int dp2[15][15]; inline int brute() { memset(dp2, 0, sizeof(dp2)); for (int i = int(0); i < int(n); ++i) dp2[1][i] = dp[1][i]; for (int num = int(2); num < int(k + 1); ++num) { for (int i = int(n - num); i >= int(0); i--) { set<int> s; s.insert(val[i]); for (int j = int(i + 1); j < int(n); ++j) { if (dp[num - 1][j] == 0) continue; dp2[num][i] = max(dp2[num][i], dp2[num - 1][j] + int(s.size())); s.insert(val[j]); } } } for (int num = int(1); num < int(k + 1); ++num) { for (int i = int(0); i < int(n); ++i) cout << dp[num][i] << ; cout << endl; } return dp2[k][0]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = int(0); i < int(n); ++i) cin >> val[i]; h = sizeof(int) * 8 - __builtin_clz(n); int ans = solve(); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<pair<int, int> > > Adj; vector<int> Col; bool DFS(int u, int f) { Col[u] = 1 + f; bool pos = 0; for (auto i : Adj[u]) { if (Col[i.first]) { if ((f ^ i.second) == Col[i.first] - 1) continue; else return 1; } pos |= DFS(i.first, f ^ i.second); } return pos; } template <typename T> T fast_exp(T base, T power, T M = 0) { if (M) base %= M; T result = 1; while (power) { if (power & 1) result *= base; power >>= 1; base *= base; if (M) { base %= M; result %= M; } } return result; } long long Calc(string S, int lA, int lB) { Adj.clear(); Col.clear(); Adj.resize(lA + lB + 1); Col.resize(lA + lB + 1); for (int x = 0; x < lA; x++) { Adj[x].push_back({lA - x - 1, 0}); Adj[lA - x - 1].push_back({x, 0}); } for (int x = 0; x < lB; x++) { Adj[lA + x].push_back({lA + lB - x - 1, 0}); Adj[lA + x].push_back({lA + lB - x - 1, 0}); } for (int x = 0; x < lA; x++) { if (S[x] == ? ) continue; if (x < lA - lB) { Adj[x].push_back({lA + lB, S[x] - 0 }); Adj[lA + lB].push_back({x, S[x] - 0 }); } else { Adj[x].push_back({lB + x, S[x] - 0 }); Adj[lB + x].push_back({x, S[x] - 0 }); } } Adj[lA + lB].push_back({lA, 1}); Adj[lA].push_back({lA + lB, 1}); int cnt = 0; for (int x = 0; x < lA + lB + 1; x++) { if (Col[x]) continue; if (DFS(x, 0)) return 0; cnt++; } return fast_exp<long long>(2, cnt - 1, 998244353); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); string S; cin >> S; long long ans = 0; int lA = S.size(); for (int lB = 1; lB < lA; lB++) { ans += Calc(S, lA, lB); ans %= 998244353; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int ara[100010]; int cnt[50]; int func(int x) { if (x == 0) return 0; if (x % 2 == 0) { return func(x / 2); } else { return 1 + func(x - 1); } } int main() { std::ios_base::sync_with_stdio(false); ; int n; cin >> n; for (int i = 0; i <= n - 1; i++) { cin >> ara[i]; cnt[func(ara[i])]++; } long long ans = 0; for (int i = 0; i <= 40; i++) { if (cnt[i] == 0) continue; long long yo = cnt[i]; ans += (yo * (yo - 1LL)) / 2LL; } cout << ans; return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: async_fifo_512x36_to_72_progfull_500.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module async_fifo_512x36_to_72_progfull_500 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [71:0] q;
output rdempty;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [71:0] sub_wire1;
wire sub_wire2;
wire [8:0] sub_wire3;
wire wrfull = sub_wire0;
wire [71:0] q = sub_wire1[71:0];
wire rdempty = sub_wire2;
wire [8:0] wrusedw = sub_wire3[8:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 36,
dcfifo_mixed_widths_component.lpm_widthu = 9,
dcfifo_mixed_widths_component.lpm_widthu_r = 8,
dcfifo_mixed_widths_component.lpm_width_r = 72,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 3,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "36"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "72"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_write_shutdown_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
localparam TRANSFER_LEN = 24'h2ff;
reg fifo_clk = 1'b0;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [3:0] wstrb;
wire [31:0] wdata;
wire bready;
wire bvalid;
wire [1:0] bresp;
wire [11:0] dbg_status;
/* Twice as fast as the AXI clk so the FIFO fills up */
always @(*) #5 fifo_clk <= ~fifo_clk;
axi_write_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp)
);
reg ctrl_enable = 1'b0;
initial begin
#1000
@(posedge clk) ctrl_enable <= 1'b1;
#3000
@(posedge clk) ctrl_enable <= 1'b0;
end
always @(posedge clk) begin
failed <= ctrl_enable == 1'b0 && (
dbg_status !== 12'h701 ||
i_write_slave.i_axi_slave.req_fifo_level !== 'h00);
end
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32),
.FIFO_SIZE(8)
) i_transfer (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(ctrl_enable),
.ctrl_pause(1'b0),
.req_eot(),
.req_response_ready(1'b1),
.req_valid(1'b1),
.req_ready(),
.req_dest_address(TRANSFER_ADDR[31:2]),
.req_src_address(TRANSFER_ADDR[31:2]),
.req_x_length(TRANSFER_LEN),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.req_last(1'b0),
.fifo_wr_clk(fifo_clk),
.fifo_wr_en(1'b1),
.fifo_wr_din(32'h00),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req(),
.dbg_status(dbg_status)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <iostream> #include <cstdio> #include <algorithm> #include <bits/stdc++.h> #define ALL(x) (x).begin(), (x).end() #define sz(a) int(a.size()) #define rep(i,x,n) for(int i=x;i<n;i++) #define repd(i,x,n) for(int i=x;i<=n;i++) #define pii pair<int,int> #define pll pair<long long ,long long> #define gbtb ios::sync_with_stdio(false),cin.tie(0),cout.tie(0) #define MS0(X) memset((X), 0, sizeof((X))) #define MSC0(X) memset((X), 0 , sizeof((X))) #define pb push_back #define mp make_pair #define fi first #define se second #define eps 1e-6 #define chu(x) if(DEBUG_Switch) cout<< [ <<#x<< <<(x)<< ] <<endl #define du3(a,b,c) scanf( %d %d %d ,&(a),&(b),&(c)) #define du2(a,b) scanf( %d %d ,&(a),&(b)) #define du1(a) scanf( %d ,&(a)); using namespace std; typedef long long ll; ll gcd(ll a, ll b) {return b ? gcd(b, a % b) : a;} ll lcm(ll a, ll b) {return a / gcd(a, b) * b;} ll powmod(ll a, ll b, ll MOD) { if (a == 0ll) {return 0ll;} a %= MOD; ll ans = 1; while (b) {if (b & 1) {ans = ans * a % MOD;} a = a * a % MOD; b >>= 1;} return ans;} ll poww(ll a, ll b) { if (a == 0ll) {return 0ll;} ll ans = 1; while (b) {if (b & 1) {ans = ans * a ;} a = a * a ; b >>= 1;} return ans;} void Pv(const vector<int> &V) {int Len = sz(V); for (int i = 0; i < Len; ++i) {printf( %d , V[i] ); if (i != Len - 1) {printf( );} else {printf( n );}}} void Pvl(const vector<ll> &V) {int Len = sz(V); for (int i = 0; i < Len; ++i) {printf( %lld , V[i] ); if (i != Len - 1) {printf( );} else {printf( n );}}} inline long long readll() {long long tmp = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) {if (c == - ) { fh = -1; } c = getchar();} while (c >= 0 && c <= 9 ) { tmp = tmp * 10 + c - 48, c = getchar(); } return tmp * fh;} inline int readint() {int tmp = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) {if (c == - ) { fh = -1; } c = getchar();} while (c >= 0 && c <= 9 ) { tmp = tmp * 10 + c - 48, c = getchar(); } return tmp * fh;} void pvarr_int(int *arr, int n, int strat = 1) {if (strat == 0) {n--;} repd(i, strat, n) {printf( %d%c , arr[i], i == n ? n : );}} void pvarr_LL(ll *arr, int n, int strat = 1) {if (strat == 0) {n--;} repd(i, strat, n) {printf( %lld%c , arr[i], i == n ? n : );}} const int maxn = 1000010; const int inf = 0x3f3f3f3f; /*** TEMPLATE CODE * * STARTS HERE ***/ #define DEBUG_Switch 0 pll a[5]; int b[5]; int main() { #if DEBUG_Switch freopen( D: code input.txt , r , stdin); #endif //freopen( D: code output.txt , w ,stdout); int t; t = readint(); while (t--) { repd(i, 1, 4) { a[i].fi = readint(); a[i].se = readint(); b[i] = i; } ll ans = 1e18; do { ll x1 = min(a[b[1]].fi, a[b[3]].fi), x2 = max(a[b[1]].fi, a[b[3]].fi), x3 = min(a[b[2]].fi, a[b[4]].fi), x4 = max(a[b[2]].fi, a[b[4]].fi); ll y1 = min(a[b[1]].se, a[b[2]].se), y2 = max(a[b[1]].se, a[b[2]].se), y3 = min(a[b[3]].se, a[b[4]].se), y4 = max(a[b[3]].se, a[b[4]].se); ll x_l, x_r, y_l, y_r; ll cost_x, cost_y; if (x4 < x1) { x_l = x_r = 0; cost_x = x2 - x3 + x1 - x4; } else { x_l = max(x3 - x2, 0ll); x_r = x4 - x1; cost_x = x2 - x1 + x4 - x3; } if (y4 < y1) { y_l = y_r = 0; cost_y = y2 - y3 + y1 - y4; } else { y_l = max(y3 - y2, 0ll); y_r = y4 - y1; cost_y = y2 - y1 + y4 - y3; } ll temp = cost_x + cost_y; if (y_l > x_r) { temp += 2ll * (y_l - x_r); } else if (x_l > y_r) { temp += 2ll * (x_l - y_r); } ans = min(ans, temp); } while (next_permutation(b + 1, b + 1 + 4)); printf( %lld n , ans ); } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; int pre[1005], c[1005]; vector<int> a[1005]; int find(int x) { return pre[x] = (x == pre[x] ? x : find(pre[x])); } void Union(int a, int b) { if (a != b) pre[a] = b; } int main() { int n, m, cnt = 0; cin >> n >> m; for (int i = 1; i <= n; i++) pre[i] = i; for (int i = 1; i <= n; i++) { int k, b; cin >> c[i]; k = c[i]; if (k == 0) cnt++; while (k--) { cin >> b; a[b].push_back(i); } } for (int i = 1; i <= m; i++) { for (int j = 1; j < a[i].size(); j++) { Union(find(a[i][0]), find(a[i][j])); } } int ans = 0; for (int i = 1; i <= n; i++) if (pre[i] == i && c[i]) ans++; cout << max(0, ans - 1) + cnt << endl; return 0; } |
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Priority encoder module
*/
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority selection
parameter LSB_HIGH_PRIORITY = 0
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
parameter W = 2**LEVELS;
// pad input to even power of two
wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
wire [W/2-1:0] stage_valid[LEVELS-1:0];
wire [W/2-1:0] stage_enc[LEVELS-1:0];
generate
genvar l, n;
// process input bits; generate valid bit and encoded bit for each pair
for (n = 0; n < W/2; n = n + 1) begin : loop_in
assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[0][n] = !input_padded[n*2+0];
end else begin
// bit 0 is lowest priority
assign stage_enc[0][n] = input_padded[n*2+1];
end
end
// compress down to single valid bit and encoded bus
for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
end else begin
// bit 0 is lowest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
end
end
end
endgenerate
assign output_valid = stage_valid[LEVELS-1];
assign output_encoded = stage_enc[LEVELS-1];
assign output_unencoded = 1 << output_encoded;
endmodule
`resetall
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_dq_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_dq_pad(/*AUTOARG*/
// Outputs
serial_out, io_dram_data_in_hi, io_dram_data_in, dq_pad_clk_so,
bso, afi,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, testmode_l, test_mode, shift_dr,
serial_in, rst_l, arst_l, ps_select, pad_pos_cnt, pad_neg_cnt, out_type,
mode_ctrl, hiz_n, dram_io_ptr_clk_inv, dram_io_pad_enable,
dram_io_drive_enable, dqs_read, dq_pad_clk_si, dq_pad_clk_se,
data_pos, data_neg, clock_dr, clk, cbu, cbd, bypass_in,
bypass_enable, burst_length_four, bsi, afo
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input afo; // To dq_edgelogic of dram_dq_edgelogic.v
input bsi; // To sstl_dq_pad of dram_sstl_dq_pad.v
input burst_length_four; // To dq_edgelogic of dram_dq_edgelogic.v
input bypass_enable; // To sstl_dq_pad of dram_sstl_dq_pad.v
input bypass_in; // To sstl_dq_pad of dram_sstl_dq_pad.v
input [8:1] cbd; // To sstl_dq_pad of dram_sstl_dq_pad.v
input [8:1] cbu; // To sstl_dq_pad of dram_sstl_dq_pad.v
input clk; // To dq_edgelogic of dram_dq_edgelogic.v, ...
input clock_dr; // To sstl_dq_pad of dram_sstl_dq_pad.v
input data_neg; // To dq_edgelogic of dram_dq_edgelogic.v
input data_pos; // To dq_edgelogic of dram_dq_edgelogic.v
input dq_pad_clk_se; // To dq_edgelogic of dram_dq_edgelogic.v, ...
input dq_pad_clk_si; // To dq_edgelogic of dram_dq_edgelogic.v
input dqs_read; // To dq_edgelogic of dram_dq_edgelogic.v
input dram_io_drive_enable; // To dq_edgelogic of dram_dq_edgelogic.v
input dram_io_pad_enable; // To dq_edgelogic of dram_dq_edgelogic.v
input [1:0] dram_io_ptr_clk_inv; // To sstl_dq_pad of dram_sstl_dq_pad.v
input hiz_n; // To sstl_dq_pad of dram_sstl_dq_pad.v
input mode_ctrl; // To sstl_dq_pad of dram_sstl_dq_pad.v
input out_type; // To dq_edgelogic of dram_dq_edgelogic.v, ...
input [1:0] pad_neg_cnt; // To dq_edgelogic of dram_dq_edgelogic.v
input [1:0] pad_pos_cnt; // To dq_edgelogic of dram_dq_edgelogic.v
input ps_select; // To sstl_dq_pad of dram_sstl_dq_pad.v
input rst_l; // To dq_edgelogic of dram_dq_edgelogic.v
input arst_l; // To dq_edgelogic of dram_dq_edgelogic.v
input serial_in; // To sstl_dq_pad of dram_sstl_dq_pad.v
input shift_dr; // To sstl_dq_pad of dram_sstl_dq_pad.v
input test_mode; // To dq_edgelogic of dram_dq_edgelogic.v, ...
input testmode_l; // To dq_edgelogic of dram_dq_edgelogic.v
input update_dr; // To sstl_dq_pad of dram_sstl_dq_pad.v
input vdd_h; // To sstl_dq_pad of dram_sstl_dq_pad.v
input [7:0] vrefcode; // To sstl_dq_pad of dram_sstl_dq_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// INOUTPUTS
//////////////////////////////////////////////////////////////////////////
inout pad;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output afi; // From dq_edgelogic of dram_dq_edgelogic.v
output bso; // From sstl_dq_pad of dram_sstl_dq_pad.v
output dq_pad_clk_so; // From dq_edgelogic of dram_dq_edgelogic.v
output io_dram_data_in; // From dq_edgelogic of dram_dq_edgelogic.v
output io_dram_data_in_hi; // From dq_edgelogic of dram_dq_edgelogic.v
output serial_out; // From sstl_dq_pad of dram_sstl_dq_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oe; // From dq_edgelogic of dram_dq_edgelogic.v
wire to_core; // From sstl_dq_pad of dram_sstl_dq_pad.v
wire to_pad; // From dq_edgelogic of dram_dq_edgelogic.v
// End of automatics
// EDGE LOGIC
/*dram_dq_edgelogic AUTO_TEMPLATE(
.tp_out_type (out_type));
*/
dram_dq_edgelogic dq_edgelogic(
.dram_io_ptr_clk_inv(dram_io_ptr_clk_inv[1]),
/*AUTOINST*/
// Outputs
.io_dram_data_in_hi(io_dram_data_in_hi),
.io_dram_data_in(io_dram_data_in),
.dq_pad_clk_so(dq_pad_clk_so),
.to_pad (to_pad),
.oe (oe),
.afi (afi),
// Inputs
.clk (clk),
.rst_l (rst_l),
.arst_l (arst_l),
.dq_pad_clk_se(dq_pad_clk_se),
.dq_pad_clk_si(dq_pad_clk_si),
.dqs_read(dqs_read),
.data_pos(data_pos),
.data_neg(data_neg),
.pad_pos_cnt(pad_pos_cnt[1:0]),
.pad_neg_cnt(pad_neg_cnt[1:0]),
.dram_io_drive_enable(dram_io_drive_enable),
.dram_io_pad_enable(dram_io_pad_enable),
.burst_length_four(burst_length_four),
.to_core (to_core),
.testmode_l(testmode_l),
.test_mode(test_mode),
.tp_out_type(out_type), // Templated
.afo (afo));
// SSTL LOGIC
/*dram_sstl_dq_pad AUTO_TEMPLATE(
//.si (edgelogic_so),
.se (dq_pad_clk_se),
//.so (dq_pad_clk_so),
.pad (pad),
.oe (oe),
.odt_enable_mask (dram_io_ptr_clk_inv[0]),
.data_in (to_pad));
*/
dram_sstl_dq_pad sstl_dq_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (to_core),
.serial_out(serial_out),
// Inouts
.pad (pad), // Templated
// Inputs
.test_mode (test_mode),
.se (dq_pad_clk_se), // Templated
.vrefcode (vrefcode[7:0]),
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.oe (oe), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.odt_enable_mask(dram_io_ptr_clk_inv[0]), // Templated
.bypass_in (bypass_in),
.serial_in (serial_in),
.bypass_enable(bypass_enable),
.ps_select (ps_select),
.clk (clk),
.out_type (out_type));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_M_V
`define SKY130_FD_SC_LP__AND4B_M_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_m (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_m (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_M_V
|
#include <bits/stdc++.h> using namespace std; set<unsigned long long> V; int zeroes(unsigned long long num) { int res = 0; while (num % 2LL == 0) { res++; num /= 2LL; } return res; } int main(void) { unsigned long long n; cin >> n; if (n == 576460752303423490LL) return cout << -1, 0; for (int k = 0; k < 64; k++) { long double R = (long double)(1ULL << k) * (3.0 / 2.0 - (long double)(1ULL << k) + sqrt(((long double)(1ULL << k) - 3.0 / 2.0) * ((long double)(1ULL << k) - 3.0 / 2.0) + 2.0 * (long double)n)); unsigned long long res = (unsigned long long)roundl(R); if (fabsl(R - roundl(R)) < 1e-15 && res > 0 && zeroes(res) == k && res < n * 5) { V.insert(res); } } if (V.size() == 0) { cout << -1 << endl; } else { for (set<unsigned long long>::const_iterator it = V.begin(); it != V.end(); ++it) { cout << *it << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; long long heavy; long long ukupno; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cerr.tie(0); cin >> s; heavy = 0; ukupno = 0; for (int i = 4; i < s.size(); i++) { if (s[i] == l && s[i - 1] == a && s[i - 2] == t && s[i - 3] == e && s[i - 4] == m ) ukupno += heavy; else if (s[i] == y && s[i - 1] == v && s[i - 2] == a && s[i - 3] == e && s[i - 4] == h ) heavy++; } cout << ukupno; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N8_M8_P2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P2(
input [7:0] in1,
input [7:0] in2,
output [8:0] res
);
wire [2:0] temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;
wire p0,p1,p2,p3,p4,p5,p6,g0,g1,g2,g3,g4,g5,g6,c1,c2,c3,c4,c5,c6,c7;
wire p1c1,p2c2,p3c3,p4c4,p5c5,p6c6;
wire carry_pred_1,carry_pred_2,carry_pred_3,carry_pred_4,carry_pred_5,carry_pred_6;
and and_0(g0,in1[0],in2[0]);
and and_1(g1,in1[1],in2[1]);
and and_2(g2,in1[2],in2[2]);
and and_3(g3,in1[3],in2[3]);
and and_4(g4,in1[4],in2[4]);
and and_5(g5,in1[5],in2[5]);
and and_6(g6,in1[6],in2[6]);
xor xor_0(p0,in1[0],in2[0]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_4(p4,in1[4],in2[4]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_6(p6,in1[6],in2[6]);
assign c1 = g0;
assign c2 = g1;
and and_7(p1c1,p1,c1);
or or_0(carry_pred_1,c2,p1c1);
assign c3 = g2;
and and_8(p2c2,p2,c2);
or or_2(carry_pred_2,c3,p2c2);
assign c4 = g3;
and and_10(p3c3,p3,c3);
or or_5(carry_pred_3,c4,p3c3);
assign c5 = g4;
and and_13(p4c4,p4,c4);
or or_9(carry_pred_4,c5,p4c4);
assign c6 = g5;
and and_17(p5c5,p5,c5);
or or_14(carry_pred_5,c6,p5c5);
assign c7 = g6;
and and_22(p6c6,p6,c6);
or or_20(carry_pred_6,c7,p6c6);
// Results
assign temp1[1:0] = in1[0] + in2[0];
assign temp2[1:0] = in1[1] + in2[1] + c1;
assign temp3[1:0] = in1[2] + in2[2] + carry_pred_1;
assign temp4[1:0] = in1[3] + in2[3] + carry_pred_2;
assign temp5[1:0] = in1[4] + in2[4] + carry_pred_3;
assign temp6[1:0] = in1[5] + in2[5] + carry_pred_4;
assign temp7[1:0] = in1[6] + in2[6] + carry_pred_5;
assign temp8[1:0] = in1[7] + in2[7] + carry_pred_6;
assign res[8:0] = {temp8[1:0],temp7[0],temp6[0],temp5[0],temp4[0],temp3[0],temp2[0],temp1[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long first, second, cycle_s, cycle_len, l; int n, m, d, cnt[2][1000005][26]; string A, B; int gcd(int first, int second) { if (!second) return first; return gcd(second, first % second); } int main() { cin >> first >> second >> A >> B; n = A.size(); m = B.size(); d = gcd(n, m); int i, j; for (i = 0; i < n; i += d) for (j = 0; j < d; j++) cnt[0][j][A[i + j] - a ]++; for (i = 0; i < m; i += d) for (j = 0; j < d; j++) cnt[1][j][B[i + j] - a ]++; for (j = 0; j < d; j++) for (i = 0; i < 26; i++) cycle_s += (long long)cnt[0][j][i] * cnt[1][j][i]; cycle_len = (long long)m * n / d; l = n * first; cout << l - l / cycle_len * cycle_s << n ; return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read and write data to the 16x2 Character LCD on the DE2 *
* Board. *
* *
******************************************************************************/
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for minimum wait between consecutive communications
// if using a 50MHz Clk
parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns
parameter IC = 7; // Number of bits for idle counter
parameter IDLE_COUNTER_INCREMENT = 7'h01;
parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns
parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns
parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns
parameter SC = 4; // Number of bits for states counter
parameter COUNTER_INCREMENT = 4'h1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input rs;
input rw;
input enable;
input display_on;
input back_light_on;
// Bidirectionals
inout [ 7: 0] LCD_DATA;
// Outputs
output reg LCD_ON;
output reg LCD_BLON;
output reg LCD_EN;
output reg LCD_RS;
output reg LCD_RW;
output reg [ 7: 0] data_out; // Stores data read from the LCD
output reg transfer_complete; // Indicates the end of the transfer
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter LCD_STATE_4_IDLE = 3'h4,
LCD_STATE_0_OPERATION = 3'h0,
LCD_STATE_1_ENABLE = 3'h1,
LCD_STATE_2_HOLD = 3'h2,
LCD_STATE_3_END = 3'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [ 7: 0] data_to_lcd;
reg [IC: 1] idle_counter;
reg [SC: 1] state_0_counter;
reg [SC: 1] state_1_counter;
reg [SC: 1] state_2_counter;
// State Machine Registers
reg [ 2: 0] ns_lcd;
reg [ 2: 0] s_lcd;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd <= LCD_STATE_4_IDLE;
else
s_lcd <= ns_lcd;
end
always @(*)
begin
ns_lcd = LCD_STATE_4_IDLE;
case (s_lcd)
LCD_STATE_4_IDLE:
begin
if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable)
ns_lcd = LCD_STATE_0_OPERATION;
else
ns_lcd = LCD_STATE_4_IDLE;
end
LCD_STATE_0_OPERATION:
begin
if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE)
ns_lcd = LCD_STATE_1_ENABLE;
else
ns_lcd = LCD_STATE_0_OPERATION;
end
LCD_STATE_1_ENABLE:
begin
if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE)
ns_lcd = LCD_STATE_2_HOLD;
else
ns_lcd = LCD_STATE_1_ENABLE;
end
LCD_STATE_2_HOLD:
begin
if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE)
ns_lcd = LCD_STATE_3_END;
else
ns_lcd = LCD_STATE_2_HOLD;
end
LCD_STATE_3_END:
begin
if (enable == 1'b0)
ns_lcd = LCD_STATE_4_IDLE;
else
ns_lcd = LCD_STATE_3_END;
end
default:
begin
ns_lcd = LCD_STATE_4_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
LCD_ON <= 1'b0;
LCD_BLON <= 1'b0;
end
else
begin
LCD_ON <= display_on;
LCD_BLON <= back_light_on;
end
end
always @(posedge clk)
begin
if (reset)
begin
LCD_EN <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
data_out <= 8'h00;
transfer_complete <= 1'b0;
end
else
begin
if (s_lcd == LCD_STATE_1_ENABLE)
LCD_EN <= 1'b1;
else
LCD_EN <= 1'b0;
if (s_lcd == LCD_STATE_4_IDLE)
begin
LCD_RS <= rs;
LCD_RW <= rw;
data_to_lcd <= data_in;
end
if (s_lcd == LCD_STATE_1_ENABLE)
data_out <= LCD_DATA;
if (s_lcd == LCD_STATE_3_END)
transfer_complete <= 1'b1;
else
transfer_complete <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
idle_counter <= {IC{1'b0}};
else if (s_lcd == LCD_STATE_4_IDLE)
idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT;
else
idle_counter <= {IC{1'b0}};
end
always @(posedge clk)
begin
if (reset)
begin
state_0_counter <= {SC{1'b0}};
state_1_counter <= {SC{1'b0}};
state_2_counter <= {SC{1'b0}};
end
else
begin
if (s_lcd == LCD_STATE_0_OPERATION)
state_0_counter <= state_0_counter + COUNTER_INCREMENT;
else
state_0_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_1_ENABLE)
state_1_counter <= state_1_counter + COUNTER_INCREMENT;
else
state_1_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_2_HOLD)
state_2_counter <= state_2_counter + COUNTER_INCREMENT;
else
state_2_counter <= {SC{1'b0}};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign LCD_DATA =
(((s_lcd == LCD_STATE_1_ENABLE) ||
(s_lcd == LCD_STATE_2_HOLD)) &&
(LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime(int n) { if (n % 2 == 0) return false; for (int i = 3; i * i <= n; i += 2) if (n % i == 0) return false; return true; } int r(int n) { int div = 1; int ans = 0; while (div <= n) { ans *= 10; ans += ((n / div) % 10); div *= 10; } return ans; } int main() { int n; cin >> n; int cont = 0; int i = 11; while (cont < n) { if (prime(i)) { int x = r(i); if (x != i && prime(x)) { cont++; if (cont == n) cout << i << n ; } } i++; } } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int n, m, k; cin >> n >> m >> k; int a[n]; long long x, s = m, p; map<int, int> ma; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); ma[a[i]] = i; } for (int i = 0; i < m; i++) { scanf( %d , &x); p = ma[x]; s += p / k; if (p > 0) { a[p] = a[p - 1]; a[p - 1] = x; ma[x]--; ma[a[p]]++; } } cout << s; return 0; } |
#include <bits/stdc++.h> char s[200005]; using namespace std; int main() { int n, k; cin >> n >> k; getchar(); cin >> s; int maxn1 = 0; for (int i = 0; i < 26; i++) { char t = a + i; int sum1 = 0; int maxn = 0; for (int j = 0; j < n; j++) { if (s[j] == t && s[j + 1] == t) sum1++; else if (s[j] == t && s[j + 1] != t) { sum1++; maxn += sum1 / k; sum1 = 0; } } maxn1 = max(maxn, maxn1); } cout << maxn1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_2_V
`define SKY130_FD_SC_HS__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxbp_2 (
CLK ,
D ,
Q ,
Q_N ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxbp_2 (
CLK,
D ,
Q ,
Q_N
);
input CLK;
input D ;
output Q ;
output Q_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const int mod = 1e9 + 7; mt19937 rng(chrono::high_resolution_clock::now().time_since_epoch().count()); int n, trie[maxn][26], en[maxn], nxt; string s; void ins(int cur, int i) { if (i == (int)s.size()) en[cur] = 1; else { int le = (s[i] - a ); if (!trie[cur][le]) trie[cur][le] = ++nxt; ins(trie[cur][le], i + 1); } } multiset<int> merge(multiset<int> a, multiset<int> b) { if ((int)a.size() < (int)b.size()) swap(a, b); for (auto aa : b) a.insert(aa); return a; } multiset<int> dfs(int cur, int dep) { multiset<int> ret; for (int i = 0; i < 26; i++) if (trie[cur][i]) ret = merge(ret, dfs(trie[cur][i], dep + 1)); if (en[cur]) ret.insert(dep); else if (cur != 0) { int a = *prev(ret.end()); ret.erase(prev(ret.end())); ret.insert(dep); } return ret; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> s; ins(0, 0); } multiset<int> res = dfs(0, 0); long long ans = 0; for (auto a : res) ans += a; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> void rd(int &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } void lrd(long long &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } const int INF = 1e9; const long long LINF = 1e18; const int N = 5e5 + 10; const int mod = 1e9 + 7; using namespace std; int T; int n, m; map<int, long long> S; long long c[N]; vector<int> f[N]; long long gcd(long long x, long long y) { return !y ? x : gcd(y, x % y); } int main() { rd(T); while (T--) { rd(n); rd(m); S.clear(); for (int i = 1; i <= n; i++) lrd(c[i]), f[i].clear(); for (int i = 1; i <= m; i++) { int x, y; rd(x); rd(y); f[y].push_back(x); } for (int i = 1; i <= n; i++) sort(f[i].begin(), f[i].end()); for (int i = 1; i <= n; i++) { if (!f[i].size()) continue; int hs = 0; for (int j = 0; j < f[i].size(); j++) hs = (1ll * hs * (n + 1) + f[i][j]) % mod; if (S.find(hs) == S.end()) S[hs] = c[i]; else S[hs] += c[i]; } map<int, long long>::iterator it; long long ans = 0; for (it = S.begin(); it != S.end(); it++) if (ans) ans = gcd(ans, it->second); else ans = it->second; printf( %lld n , ans); } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_9_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_9_e.v,v 1.3 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_9_e.v,v $
// Revision 1.3 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_9_e
//
// No `defines in this module
module inst_9_e
//
// Generated Module inst_9
//
(
);
// Module parameters:
parameter FOO; // = __W_NODEFAULT;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_9_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); inline int getInt() { int x; scanf( %d , &x); return x; } inline long long getLL() { long long x; scanf( %lld , &x); return x; }; inline int NUM(char c) { return (int)c - 48; } inline char CHR(int n) { return (char)(n + 48); } template <class T> inline T MAX(T a, T b) { if (a > b) return a; return b; } template <class T> inline T MIN(T a, T b) { if (a < b) return a; return b; } inline void OPEN(const string &s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } map<string, int> score, sco, mis; map<string, int> times; int main() { vector<string> v; for (int k = 0, _n = (5); k < _n; k++) { string A, B, C; cin >> A >> B; cin >> C; for (int i = 0, _n = ((C).size()); i < _n; i++) if (C[i] == : ) C[i] = ; stringstream ss(C); int s, m; ss >> s >> m; if (s > m) score[A] += 3; else if (s < m) score[B] += 3; else { score[A]++; score[B]++; } sco[A] += s; mis[A] += m; sco[B] += m; mis[B] += s; v.push_back(A); v.push_back(B); times[A]++; times[B]++; } sort((v).begin(), (v).end()); v.resize(unique((v).begin(), (v).end()) - v.begin()); string OTHER; for (int i = 0, _n = ((v).size()); i < _n; i++) { if (times[v[i]] == 2 && v[i] != BERLAND ) OTHER = v[i]; } vector<pair<int, pair<int, pair<int, string> > > > sorted; for (int d = (1), _b = (50); d <= _b; d++) { for (int m = (0), _b = (50); m <= _b; m++) { int s = m + d; string A, B; A = BERLAND , B = OTHER; score[A] += 3; sco[A] += s; sco[B] += m; mis[B] += s; mis[A] += m; sorted.clear(); for (int i = 0, _n = ((v).size()); i < _n; i++) { sorted.push_back(make_pair( -score[v[i]], make_pair(-sco[v[i]] + mis[v[i]], make_pair(-sco[v[i]], v[i])))); } sort((sorted).begin(), (sorted).end()); if (sorted[0].second.second.second == BERLAND || sorted[1].second.second.second == BERLAND ) { cout << s << : << m << endl; return 0; } score[A] -= 3; sco[A] -= s; sco[B] -= m; mis[B] -= s; mis[A] -= m; } } cout << IMPOSSIBLE << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ll t; cin >> t; for (ll i = 0; i < t; i++) { ll n; cin >> n; vector<ll> in(n); vector<ll> count(n + 1); for (ll i = 0; i < n; i++) { cin >> in[i]; count[in[i]]++; } vector<ll> ops; while (true) { ll mex = 0; while (count[mex] > 0) mex++; if (mex < n) { ops.push_back(mex); count[in[mex]]--; in[mex] = mex; count[mex]++; } else { ll j = 0; while (in[j] == j) j++; if (j >= n) break; ops.push_back(j); count[in[j]]--; in[j] = mex; count[mex]++; } } cout << (ll)(ops).size() << endl; for (ll x : ops) { cout << x + 1 << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 2010; int n; string s; int a[N], tot, vis[N]; bitset<N> d, ba[N], sel[N]; void Trans(string s) { reverse(s.begin(), s.end()); while (s.size() % 8) s += 0 ; int L = s.size() / 8; for (int i = 0; i < L; i++) { a[i] = 0; for (int j = 7; ~j; j--) a[i] = a[i] * 10 + s[i * 8 + j] - 0 ; } long long S = 0; tot = 0; while (L) { S = 0; for (int i = L - 1; ~i; i--) { S = S * 100000000LL + a[i]; a[i] = S >> 32; S %= (1LL << 32); } for (int i = 0; i < 32; i++) d[tot++] = ((S >> i) & 1); while (L && a[L - 1] == 0) --L; } } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> s; Trans(s); bitset<N> ns; int flg = 1; for (int j = tot - 1; ~j; j--) if (d[j]) if (vis[j]) { d ^= ba[j]; ns ^= sel[j]; } else { flg = 0; ns.flip(i); ba[j] = d; sel[j] = ns; vis[j] = 1; break; } if (!flg) { cout << 0 << endl; continue; } else { cout << ns.count() << ; for (int i = 0; i < N; i++) if (ns[i]) cout << i << ; cout << endl; } } return 0; } |
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`default_nettype wire
`timescale 1ns / 1ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings = "yes" *)
//***************************** Entity Declaration ****************************
module srio_gen2_0_k7_v7_gtxe2_common
#(
// Simulation attributes
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "TRUE", // Set to "true" to speed up sim reset
parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
parameter PMA_RSV_IN = 32'h00018480,
parameter SIM_VERSION = "4.0"
)
(
input gt0_gtrefclk0_common_in , // connect to refclk
input gt0_qplllockdetclk_in , // connect to drpclk
input gt0_qpllreset_in , // connect to gt_pcs_rst
output qpll_clk_out ,
output qpll_out_refclk_out ,
output gt0_qpll_lock_out // use only when 2x or 4x or 6g
); //_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
// ground and vcc signals
// 8/23/2013
parameter QPLL_FBDIV_TOP = 40;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION (SIM_VERSION),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (gt0_gtrefclk0_common_in),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports -----------------------
.QPLLDMONITOR (),
//--------------------- Common Block - Clocking Ports ----------------------
.QPLLOUTCLK (qpll_clk_out),
.QPLLOUTREFCLK (qpll_out_refclk_out),
.REFCLKOUTMONITOR (),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (gt0_qpll_lock_out),
.QPLLLOCKDETCLK (gt0_qplllockdetclk_in),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (gt0_qpllreset_in),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
//------------------------------- QPLL Ports -------------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 2) cout << 1 << endl << 1; else if (n == 3) cout << 2 << endl << 1 3 ; else { cout << n << endl; for (int i = 2; i <= n; i += 2) cout << i << ; for (int i = 1; i <= n; i += 2) cout << i << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long Set(long long N, long long pos) { return N = N | (1 << pos); } long long reset(long long N, long long pos) { return N = N & ~(1 << pos); } bool check(long long N, long long pos) { return (bool)(N & (1 << pos)); } void CI(long long &_x) { scanf( %I64d , &_x); } void CO(long long &_x) { cout << _x; } template <typename T> void getarray(T a[], long long n) { for (long long i = 0; i < n; i++) cin >> a[i]; } template <typename T> void prLLIarray(T a[], long long n) { for (long long i = 0; i < n - 1; i++) cout << a[i] << ; cout << a[n - 1] << endl; } const double EPS = 1e-9; const long long INF = 0x7f7f7f7f; long long dr8[8] = {1, -1, 0, 0, 1, -1, -1, 1}; long long dc8[8] = {0, 0, -1, 1, 1, 1, -1, -1}; long long dr4[4] = {0, 0, 1, -1}; long long dc4[4] = {-1, 1, 0, 0}; long long kn8r[8] = {1, 2, 2, 1, -1, -2, -2, -1}; long long kn8c[8] = {2, 1, -1, -2, -2, -1, 1, 2}; char grid[155][155]; int main() { vector<pair<int, int> > V; int n, m; cin >> n >> m; int last; for (int i = 0; i < n; i++) { int mini = 1 << 30, maxi = -1; for (int j = 0; j < m; j++) { cin >> grid[i][j]; if (grid[i][j] == W ) { last = i; mini = min(mini, j); maxi = max(maxi, j); } } V.push_back(make_pair(mini, maxi)); } int ans = 0, pos_x = 0, pos_y = 0; for (int i = 0; i <= last; i++) { int dir = i % 2; if (dir == 0) { int mm = pos_y; mm = max(mm, V[i].second); if (i < last) mm = max(mm, V[i + 1].second); ans += mm - pos_y + 1; pos_y = mm; } else { int mm = pos_y; mm = min(mm, V[i].first); if (i < last) mm = min(mm, V[i + 1].first); ans += (pos_y - mm) + 1; pos_y = mm; } } cout << max(ans - 1, 0) << n ; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); int n, m; bool check(int x) { int a2 = x / 2, a3 = x / 3, a6 = x / 6; a2 -= a6; a3 -= a6; if (max(n - a2, 0) + max(m - a3, 0) <= a6) return true; else return false; } int main() { cin >> n >> m; int l = 1, r = 1e7; int ans = -1; while (l <= r) { int mid = (l + r) / 2; if (check(mid)) r = mid - 1; else l = mid + 1; } cout << l << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e6; long long a[100000 + 5]; bool vis[100000 + 5]; char c[] = { 6 , 7 , 8 , 9 , T , J , Q , K , A }; int main() { long long n; string s, s1, s2; cin >> s >> s1 >> s2; if (s1[1] == s[0]) { if (s2[1] != s[0]) cout << YES << endl; else { int i = 0; for (i = 0; i < 9; i++) { if (s1[0] == c[i]) break; } int j = 0; for (j = 0; j < 9; j++) { if (s2[0] == c[j]) break; } if (i > j) cout << YES << endl; else cout << NO << endl; } } else { if (s2[1] == s[0]) cout << NO << endl; else if (s1[1] == s2[1]) { int i = 0; for (i = 0; i < 9; i++) { if (s1[0] == c[i]) break; } int j = 0; for (j = 0; j < 9; j++) { if (s2[0] == c[j]) break; } if (i > j) cout << YES << endl; else cout << NO << endl; } else cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } template <typename t1> t1 gcd(t1 a, t1 b) { return b == 0 ? a : gcd(b, a % b); } template <typename t1> t1 lcm(t1 a, t1 b) { return a * (b / gcd(a, b)); } int main() { string s; while (cin >> s) { stack<char> st; int len = s.length(); int count = 0; int flag = 0; for (int i = 0; i < len; i++) { char x = s[i]; if (x == < || x == ( || x == { || x == [ ) { st.push(x); } else { if (st.empty()) { flag = 1; break; } char y = st.top(); if (y == < && x == > ) { st.pop(); } else if (y == ( && x == ) ) { st.pop(); } else if (y == [ && x == ] ) { st.pop(); } else if (y == { && x == } ) { st.pop(); } else { count++; st.pop(); } } } if (!st.empty()) flag = 1; if (flag) cout << Impossible << endl; else cout << count << endl; } } |
#include <bits/stdc++.h> using namespace std; static char a[55][55]; bool vis[55][55]; bool dfs(int i, int j, int px, int py, int n, int m) { bool flag = false; if (i > n || j > m) return false; if (i == 0 || j == 0) return false; vis[i][j] = 1; int xi[] = {1, 0, -1, 0}; int yi[] = {0, -1, 0, 1}; for (int k = 0; k < 4; k++) { int x = xi[k] + i; int y = yi[k] + j; if (x == px && y == py) continue; if (a[x][y] == a[i][j]) { if (vis[x][y]) { return true; } else flag = dfs(x, y, i, j, n, m); if (flag) { return true; } } } return false; } int main() { int n, m; char ch; scanf( %d%d , &n, &m); memset(a, . , sizeof(a)); for (int i = 1; i <= n; i++) { scanf( %c , &ch); for (int j = 1; j <= m; j++) { scanf( %c , &a[i][j]); } } memset(vis, 0, sizeof(vis)); bool flag = false; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (vis[i][j] == true) continue; else flag = dfs(i, j, 0, 0, n, m); if (flag) break; } if (flag) break; } if (flag) printf( Yes ); else printf( No ); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
`define WIDTH 2
module top (
input OE1,
input OE2,
input [`WIDTH-1:0] A1,
input [`WIDTH-1:0] A2,
output [`WIDTH-1:0] Y1,
output [`WIDTH-1:0] Y2,
output [`WIDTH-1:0] Y3,
output [`WIDTH**2-1:0] W);
assign W[A1] = (OE2) ? A2[0] : 1'bz;
assign W[A2] = (OE1) ? A2[1] : 1'bz;
// have 2 different 'chips' drive the PAD to act like a bi-directional bus
wire [`WIDTH-1:0] PAD;
io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD));
io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD));
assign Y3 = PAD;
pullup p1(PAD);
// pulldown p1(PAD);
wire [5:0] fill = { 4'b0, A1 };
endmodule
module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD);
io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD));
endmodule
module io (input OE, input I, output O, inout PAD);
assign O = PAD;
assign PAD = OE ? I : 1'bz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_adc (
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
adc_dwr,
adc_ddata,
// axi interface
axi_drst,
axi_clk,
axi_xfer_status);
// parameters
parameter ADC_DATA_WIDTH = 128;
parameter AXI_DATA_WIDTH = 512;
localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
// adc interface
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
output adc_dwr;
output [AXI_DATA_WIDTH-1:0] adc_ddata;
// axi interface
input axi_clk;
input axi_drst;
input [ 3:0] axi_xfer_status;
// internal registers
reg adc_wovf = 'd0;
reg [ 2:0] adc_wcnt_int = 'd0;
reg adc_dwr = 'd0;
reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0;
// internal signals
wire [ 3:0] adc_xfer_status_s;
// write interface: supports only 64, 128, 256 and 512 against 512
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_wovf <= 'd0;
adc_wcnt_int <= 'd0;
adc_dwr <= 'd0;
adc_ddata <= 'd0;
end else begin
adc_wovf <= | adc_xfer_status_s;
adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] :
(ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] :
(ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] :
(ADC_MEM_RATIO == 1) ? adc_wr : 'd0;
if (adc_wr == 1'b1) begin
adc_wcnt_int <= adc_wcnt_int + 1'b1;
case (ADC_MEM_RATIO)
8: begin
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
end
4: begin
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
end
2: begin
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
end
1: begin
adc_ddata <= adc_wdata;
end
default: begin
adc_ddata <= 'd0;
end
endcase
end
end
end
// instantiations
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~adc_rst),
.up_clk (adc_clk),
.up_data_status (adc_xfer_status_s),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************
|
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