text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; template <typename arg> void debugger(const char* varname, arg&& var) { cout << varname << = << var << endl; } template <typename arg, typename... args> void debugger(const char* varnames, arg&& var, args&&... vars) { const char* comma = strchr(varnames + 1, , ); cout.write(varnames, comma - varnames) << = << var << | ; int sz = 1; if (isspace(comma[sz])) sz++; debugger(comma + sz, vars...); } using ll = long long; using ii = pair<ll, ll>; using vi = vector<ll>; extern const int INF = INT_MAX - 5; extern const ll LINF = LLONG_MAX - 5; extern const int MOD = 1e9 + 7; extern const int N = 2e5 + 200; int t, n; string s; vi find_min() { vi ret(n), pos; if (s[0] == < ) pos.emplace_back(0); for (int i = 1; i < (int)s.size(); ++i) { if (s[i - 1] == > and s[i] == < ) { pos.emplace_back(i); } } if (s[(int)s.size() - 1] == > ) pos.emplace_back(n - 1); int c = 1; for (int i = (int)pos.size() - 1; i >= 0; --i) { ret[pos[i]] = c; c++; } for (int i = pos[pos.size() - 1] + 1; i < n; ++i) { ret[i] = c; c++; } for (int i = (int)pos.size() - 1; i >= 1; --i) { int r = pos[i] - 1, l = pos[i - 1]; while (s[r] == > and s[r - 1] == > ) { ret[r] = c; r--, c++; } while (s[l] == < and s[l + 1] == < ) { ret[l + 1] = c; l++, c++; } ret[l + 1] = c; c++; } for (int i = pos[0] - 1; i >= 0; --i) { ret[i] = c; c++; } return ret; } vi find_max() { vi ret(n); vector<ii> rng; int ant = 0; for (int i = 0; i < (int)s.size(); ++i) { if (s[i] == < ) { rng.emplace_back(ant, i); ant = i + 1; } } rng.emplace_back(ant, n - 1); int c = 1; for (auto i : rng) { ret[i.second] = c; c++; } for (auto i : rng) { for (int k = i.second - 1; k >= i.first; --k) { ret[k] = c; c++; } } return ret; } int main() { cin >> t; while (t--) { cin >> n >> s; vi mn = find_min(); vi mx = find_max(); for (int i = 0; i < n; ++i) { if (i != 0) cout << ; cout << mn[i]; } cout << n ; for (int i = 0; i < n; ++i) { if (i != 0) cout << ; cout << mx[i]; } cout << n ; } return 0; } |
/*
PWM Generator
This module will generate a PWM output signal whose duty cycle is determined
by the duty_cycle input. Valid duty_cycle values include the full range from 0 to (2^N)-1,
where N is the PWM_DEPTH in bits (for example, 0-255 for an 8 bit depth).
This design uses an internal counter and comparator to control the PWM output.
The PWM output can be disabled either by applying the value of zero to the
duty_cycle input, or by holding the module in reset.
How to create an instance using Verilog 2001 syntax:
- The PWM_DEPTH parameter determines how many bits are used
for the PWM target input and the internal PWM counter.
// PWM generator instance
pwm_generator #(.PWM_DEPTH(8)) pwm0 // pwm0 is your instance name
(//ports
.pwm( <your pwm signal> ), // PWM output signal
.duty_cycle( <your pwm duty cycle> ), // PWM duty cycle (vector)
.rst_n( <your reset signal> ), // Active-low reset
.clk( <your clock signal> ) // Clock signal
);
Note: Verilog 2001, ANSI C Syntax
Original author: Mark Young
Date: 2016/05/19
Adapted by: Nathan Larson
Date: 2016/10/20
*/
module pwm_generator
#(parameter PWM_DEPTH=8) // PWM depth in bits (default)
(//ports
output reg pwm, // PWM output signal
input wire [PWM_DEPTH-1:0] duty_cycle, // PWM target value (vector)
input wire rst_n, // Active-low reset
input wire clk // Clock signal
);
//internal signals
reg [PWM_DEPTH-1:0] count; // internal count for PWM comparator
wire pwm_next; // result of PWM comparison
// Comparator (direct assignment; will synthesize combinational logic)
assign pwm_next = (duty_cycle) ? (count <= duty_cycle) : 1'b0;
// PWM output signal (synchronous logic)
always @ (negedge rst_n, posedge clk)
begin
if (!rst_n)
pwm <= 1'b0;
else
pwm <= pwm_next; //the comparator result is registered synchronously in pwm
end
// Internal counter for PWM comparator (synchronous logic)
always @ (negedge rst_n, posedge clk)
begin
if (!rst_n)
count <= 1'b0;
else
count <= count + 1'b1; //this increment will generate a combinational adder,
//and the result will be registered synchronously in count
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 20; int n; int a[N]; int b[N]; vector<string> ans; int get(int s, int e) { int res = 0; for (int i = s; i < e; ++i) { res = res * 10 + b[i]; } return res; } string getstr(int x, int y, int z, int l) { string s = ; for (int i = 0; i < x; ++i) { s += b[i] + 0 ; } s += . ; for (int i = x; i < y; ++i) { s += b[i] + 0 ; } s += . ; for (int i = y; i < z; ++i) { s += b[i] + 0 ; } s += . ; for (int i = z; i < l; ++i) { s += b[i] + 0 ; } return s; } int check(int x, int y, int z, int l) { if (x > 3) return 0; if (y - x > 3) return 0; if (z - y > 3) return 0; if (l - z > 3) return 0; if (b[0] == 0 && x != 1 || b[x] == 0 && y - x != 1 || b[y] == 0 && z - y != 1 || b[z] == 0 && l - z != 1) { return 0; } int num[4] = {get(0, x), get(x, y), get(y, z), get(z, l)}; for (int i = 0; i < 4; ++i) { if (num[i] < 0 || num[i] >= 256) { return 0; } } return 1; } int cntsplit(int l) { int res = 0; for (int i = 1; i < l; ++i) { if (i - 0 > 3) break; for (int j = i + 1; j < l && j <= i + 3; ++j) { if (j - i > 3) break; for (int k = j + 1; k < l && k <= j + 3; ++k) { if (k - j > 3) break; if (check(i, j, k, l)) { ans.push_back(getstr(i, j, k, l)); ++res; } } } } return res; } int cnt(int d) { int l = 2 * d; int res = 0; for (int i = 0; i < d; ++i) { b[l - i - 1] = b[i]; } res += cntsplit(l); --l; for (int i = 0; i < d - 1; ++i) { b[l - i - 1] = b[i]; } res += cntsplit(l); return res; } void dfs(int d, int msk) { if (msk == (1 << n) - 1) { cnt(d); } if (d >= 6) return; for (int i = 0; i < n; ++i) { b[d] = a[i]; dfs(d + 1, msk | (1 << i)); } } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , a + i); } if (n > 6) { puts( 0 ); return 0; } dfs(0, 0); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); ++i) { printf( %s n , ans[i].c_str()); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000, M = 2000; int head[N + 10], ver[M + 10], nxt[M + 10], tot = 0; void add(int x, int y) { ver[++tot] = y; nxt[tot] = head[x]; head[x] = tot; } int col[N + 10], cnt = 0; void dfs(int x) { col[x] = cnt; for (int i = head[x]; i; i = nxt[i]) { int y = ver[i]; if (col[y]) continue; dfs(y); } } vector<int> seq[N + 10]; pair<int, int> que[N + 10]; int h = 1, t = 0, fa[N + 10]; bool vis[N + 10]; pair<int, int> bfs(int x, bool f) { memset(vis, 0, sizeof(vis)); if (f) memset(fa, -1, sizeof(fa)); h = 1; t = 0; pair<int, int> ans = make_pair(0, 0); que[++t] = make_pair(0, x); vis[x] = 1; while (h <= t) { pair<int, int> H = que[h++]; ans = max(ans, H); for (int i = head[H.second]; i; i = nxt[i]) { int y = ver[i]; if (vis[y]) continue; vis[y] = 1; if (f) fa[y] = H.second; que[++t] = make_pair(H.first + 1, y); } } return ans; } int dis[N + 10], v[N + 10]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d %d , &x, &y); add(x, y); add(y, x); } int maxx = 0, f = 0; for (int i = 1; i <= n; i++) { if (!col[i]) { cnt++; dfs(i); pair<int, int> tmp = bfs(bfs(i, false).second, true); int y = tmp.second; if (tmp.first >= maxx) { maxx = tmp.first; f = cnt; } while (~y) { seq[cnt].push_back(y); y = fa[y]; } v[cnt] = seq[cnt][seq[cnt].size() / 2]; } } for (int i = 1; i <= cnt; i++) { if (i == f) continue; add(v[i], v[f]); add(v[f], v[i]); } printf( %d n , bfs(bfs(1, false).second, false).first); for (int i = 1; i <= cnt; i++) { if (i == f) continue; printf( %d %d n , v[i], v[f]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int c1, c2, x, y, l, r, mid; int main() { ios::sync_with_stdio(false); cin >> c1 >> c2 >> x >> y; l = c1 + c2; r = 2000000009; while (l < r) { mid = (l + r) / 2; if ((mid - (mid / x) >= c1) && (mid - (mid / y) >= c2) && (mid - (mid / (x * y)) >= (c1 + c2))) r = mid; else l = mid + 1; } cout << l << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int a[5][101][101]; int sd[5][3]; int main() { scanf( %d , &n); for (int t = 1; t <= 4; t++) { char ss[101]; for (int i = 1; i <= n; i++) { scanf( %s , ss + 1); for (int j = 1; j <= n; j++) { int f = ss[j] - 0 ; a[t][i][j] = f; } } } for (int t = 1; t <= 4; t++) { for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (((i - 1) * n + j) % 2 == 1 && a[t][i][j] == 0) sd[t][1]++; if (((i - 1) * n + j) % 2 == 0 && a[t][i][j] == 1) sd[t][1]++; if (((i - 1) * n + j) % 2 == 1 && a[t][i][j] == 1) sd[t][2]++; if (((i - 1) * n + j) % 2 == 0 && a[t][i][j] == 0) sd[t][2]++; } } int ans = 1e9; if (sd[1][1] + sd[2][1] + sd[3][2] + sd[4][2] < ans) ans = sd[1][1] + sd[2][1] + sd[3][2] + sd[4][2]; if (sd[1][1] + sd[3][1] + sd[2][2] + sd[4][2] < ans) ans = sd[1][1] + sd[3][1] + sd[2][2] + sd[4][2]; if (sd[1][1] + sd[4][1] + sd[3][2] + sd[2][2] < ans) ans = sd[1][1] + sd[4][1] + sd[3][2] + sd[2][2]; if (sd[1][2] + sd[2][2] + sd[3][1] + sd[4][1] < ans) ans = sd[1][2] + sd[2][2] + sd[3][1] + sd[4][1]; if (sd[1][2] + sd[3][2] + sd[2][1] + sd[4][1] < ans) ans = sd[1][2] + sd[3][2] + sd[2][1] + sd[4][1]; if (sd[1][2] + sd[4][2] + sd[3][1] + sd[2][1] < ans) ans = sd[1][2] + sd[4][2] + sd[3][1] + sd[2][1]; printf( %d , ans); return 0; } |
`timescale 10ns/10ns
module ascii_tb();
// Declare inputs as regs and outputs as wires
reg clk;
reg scan_ready;
reg [7:0] scan_code;
wire [7:0] ascii;
ascii ascii_DUT(
.clk(clk),
.scan_ready(scan_ready),
.scan_code(scan_code),
.ascii(ascii)
);
// Initialize all variables
initial begin
clk = 1;
scan_ready = 0;
#2
scan_ready = 1;
scan_code = 8'h1c;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h1c; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: a
#10
scan_ready = 1;
scan_code = 8'h32;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h32; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: b
#10
scan_ready = 1;
scan_code = 8'h32;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h32; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: b
// Caps lock on
#10
scan_ready = 1;
scan_code = 8'h58;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h58; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: b
// Caps lock still on
#10
scan_ready = 1;
scan_code = 8'h32;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h32; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: B
// Shift aswell as caps lock
#10
scan_ready = 1;
scan_code = 8'h12;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h32;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h32; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: b
// Shift off
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h12; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: B
// Caps lock off
#50
scan_ready = 1;
scan_code = 8'h58;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h58; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: b
// c
#30
scan_ready = 1;
scan_code = 8'h21;
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h21; // scan code repeated after break code
#10
scan_ready = 0;
// ascii: c
// Multiple keys simulataniously
#30
scan_ready = 1;
scan_code = 8'h23; // d
#10
scan_ready = 0;
#30
scan_ready = 1;
scan_code = 8'h24; // e
#10
scan_ready = 0;
// ascii: e
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h24; // e key up
#10
scan_ready = 0;
// ascii: d
#10
scan_ready = 1;
scan_code = 8'hf0; // Break code (key up)
#10
scan_ready = 0;
#10
scan_ready = 1;
scan_code = 8'h23; // d key up
#10
scan_ready = 0;
// none
end
always begin
#1 clk = !clk;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:38:07 04/17/2016
// Design Name: Comparator
// Module Name: D:/Documents/College/CalPolyPomona/SeniorProject/hardware-accelerated-dna-matching-and-variation-detection/Hardware/Verilog/Comparator_tf.v
// Project Name: Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comparator_tf;
// Inputs
reg clock;
reg [63:0] data;
reg [63:0] key;
// Outputs
wire match;
// Instantiate the Unit Under Test (UUT)
Comparator uut (
.clock(clock),
.data(data),
.key(key),
.match(match)
);
initial begin
clock = 0;
repeat (1_000_000)
#1 clock =~ clock;
end
initial begin
// Initialize 64-bit data and a template of the same 64-bit data.
// Expect: match = 1
data = 64'b0010000011000111101000010111011010101010111110100110100111100111;
key = 64'b0010000011000111101000010111011010101010111110100110100111100111;
@(posedge clock);
// Change template to a different 64-bit data.
// Expect: match = 0
@(negedge clock) key = 64'b0010000011000110101000010111011010101010111110100110100111100111;
// Change template to a smaller size.
// Expect: match = 0
@(negedge clock) key = 6'b001000;
// Change data to same size as template and same data.
// Expect: match = 1
@(negedge clock) data = 6'b001000;
// Change the data of same size to different data.
// Expect: match = 0
@(negedge clock) data = 6'b001100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s1, s2; int a, b; int nxt[205], cnt[205]; int main() { scanf( %d%d , &a, &b); cin >> s1 >> s2; for (int i = 0; i < s2.size(); i++) { int pos = i; for (int r = 0; r < s1.size(); r++) { if (s2[pos] == s1[r]) { pos++; if (pos == s2.size()) cnt[i]++, pos = 0; } } nxt[i] = pos; } int ans = 0; int poss = 0; for (int i = 1; i <= a; i++) ans += cnt[poss], poss = nxt[poss]; cout << ans / b; } |
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX
*/
module eth_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_sequence_error,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_TB_V
/**
* udp_dlatch$P_pp$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_p_pp_sn.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SLEEP_B = 1'b0;
#80 D = 1'b1;
#100 NOTIFIER = 1'b1;
#120 SLEEP_B = 1'b1;
#140 D = 1'b0;
#160 NOTIFIER = 1'b0;
#180 SLEEP_B = 1'b0;
#200 SLEEP_B = 1'b1;
#220 NOTIFIER = 1'b1;
#240 D = 1'b1;
#260 SLEEP_B = 1'bx;
#280 NOTIFIER = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$P_pp$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 15:09:47 01/19/2012
// Design Name:
// Module Name: ag_main
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RAM2kx8(input CLK, input[10:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:2047];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
initial begin
`include "monitor7.v"
mem['h7FC] = 8'h00;
mem['h7FD] = 8'h50;
end
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module RAM4kx8(input CLK, input[11:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:4095];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module RAM8kx8(input CLK, input[12:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:8191];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module ag_main(
input clk50,
input[3:0] btns,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
input[1:0] ps2_bus_in,
output clk_cpu
);
// assign leds = 0;
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk10;
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1);
wire clk_vram;
wire[13:0] AB2;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs, xram_cs;
wire phi_1, phi_2;
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
RAM2kx8 rom1(phi_2, AB[10:0], rom_cs, read, DI, DO);
RAM8kx8 xram(phi_2, AB[12:0], xram_cs, read, DI, DO);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
assign xram_cs = (AB_HH[3:1] == 3'b100);
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
supply0 NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
reg[7:0] vmode = 0;
wire[7:0] key_reg;
reg[7:0] b_reg;
reg lb;
wire key_rus;
reg key_clear = 0;
wire key_rst, key_pause;
reg beep_reg = 0, tape_out_reg = 0;
assign reset = 0;//btns[0];
assign leds = AB[11:4];
assign controls = {1'b0, beep_reg ^ tape_out_reg, tape_out_reg, beep_reg};
ag_video video(clk50, vmode, clk_vram, AB2, DI2, vga_bus);
wire[1:0] ps2_bus;
signal_filter sf1(clk1, ps2_bus_in[0], ps2_bus[0]);
signal_filter sf2(clk1, ps2_bus_in[1], ps2_bus[1]);
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?b_reg?b_reg:key_reg:8'bZ;
always @(posedge phi_2) begin
key_clear <= AB_C01X;
if (AB_C01X) b_reg <= 0;
if (btns[2] & ~lb) b_reg <= 8'hDD;
else if (btns[0]) b_reg <= 8'h9C;
else if (btns[1]) b_reg <= 8'hA0;
else if (btns[3]) b_reg <= 8'h93;
lb <= btns[2];
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
end
always @(posedge vga_bus[0]) begin
reset_auto <= 0;
end
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~(reset | reset_auto | key_rst), ~IRQ, ~NMI, SO, SYNC);
assign clk_cpu = clk1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; priority_queue<pair<long long, int> > Q; int h[N], a[N]; int n, m, k, p; bool check(long long lim) { static long long now[N]; for (int i = 1; i <= n; i++) now[i] = lim; while (!Q.empty()) Q.pop(); for (int i = 1; i <= n; i++) if (now[i] - 1ll * a[i] * m < h[i]) Q.push(make_pair(-lim / a[i], i)); for (int i = 1; i <= m; i++) for (int j = 1; j <= k; j++) { if (Q.empty()) return true; pair<long long, int> mx = Q.top(); Q.pop(); if (-mx.first < i) return false; now[mx.second] += p; if (now[mx.second] - 1ll * a[mx.second] * m < h[mx.second]) Q.push(make_pair(-now[mx.second] / a[mx.second], mx.second)); } return Q.empty(); } int main() { scanf( %d%d%d%d , &n, &m, &k, &p); for (int i = 1; i <= n; i++) scanf( %d%d , &h[i], &a[i]); long long l = 0, r = 6e12, ans; while (l <= r) { long long mid = (l + r) >> 1ll; if (check(mid)) ans = mid, r = mid - 1; else l = mid + 1; } printf( %lld , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ad5545
(
input wire clk,
input wire rstn,
input wire [31:0] data,
input wire valid,
output wire ready,
output wire cs,
output wire din,
output wire ldac,
output wire sclk
);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_DAC1 = 3'd1,
STATE_WRITE_DAC2 = 3'd2,
STATE_LOAD = 3'd3,
STATE_WAIT = 3'd4;
reg [2:0] state_reg, state_next;
reg [6:0] count_reg, count_next;
reg [35:0] data_reg, data_next;
reg ready_reg, ready_next;
reg cs_reg, cs_next;
reg din_reg, din_next;
reg ldac_reg, ldac_next;
reg sclk_reg, sclk_next;
reg sclk_enable;
assign ready = ready_reg;
assign cs = cs_reg;
assign din = din_reg;
assign ldac = ldac_reg;
assign sclk = sclk_reg;
always @* begin
state_next = STATE_IDLE;
cs_next = cs_reg;
din_next = din_reg;
ldac_next = ldac_reg;
sclk_next = sclk_reg;
count_next = count_reg;
data_next = data_reg;
ready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
if (ready & valid) begin
data_next = {2'b01, data[31:16], 2'b10, data[15:0]};
ready_next = 1'b0;
state_next = STATE_WRITE_DAC1;
end else begin
ready_next = 1'b1;
end
end
STATE_WRITE_DAC1: begin
state_next = STATE_WRITE_DAC1;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (count_reg == 7'h02) begin
cs_next = 1'b0;
end
if (count_reg >= 7'h02 && count_reg[0] == 1'b0) begin
{din_next, data_next} = {data_reg, 1'b0};
end
if (count_reg == 7'h26) begin
cs_next = 1'b1;
count_next = 7'b0;
state_next = STATE_WRITE_DAC2;
end
end
STATE_WRITE_DAC2: begin
state_next = STATE_WRITE_DAC2;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (count_reg == 7'h02) begin
cs_next = 1'b0;
end
if (count_reg >= 7'h04 && count_reg[0] == 1'b0) begin
{din_next, data_next} = {data_reg, 1'b0};
end
if (count_reg == 7'h26) begin
cs_next = 1'b1;
count_next = 7'b0;
state_next = STATE_LOAD;
end
end
STATE_LOAD: begin
state_next = STATE_LOAD;
count_next = count_reg + 1;
if (count_reg[0] == 1'b1) begin
ldac_next = ~ldac_reg;
end
if (count_reg[2] == 1'b1) begin
state_next = STATE_WAIT;
count_next = 7'b0;
end
end
STATE_WAIT: begin
state_next = STATE_WAIT;
count_next = count_reg + 1;
if (count_reg == 7'h0e) begin
state_next = STATE_IDLE;
count_next = 7'b0;
end
end
endcase
end
always @(posedge clk) begin
if (~rstn) begin
state_reg <= STATE_IDLE;
data_reg <= 16'b0;
ready_reg <= 1'b0;
count_reg <= 7'b0;
cs_reg <= 1'b1;
din_reg <= 1'b0;
ldac_reg <= 1'b1;
sclk_reg <= 1'b0;
end else begin
state_reg <= state_next;
data_reg <= data_next;
count_reg <= count_next;
ready_reg <= ready_next;
cs_reg <= cs_next;
din_reg <= din_next;
ldac_reg <= ldac_next;
sclk_reg <= sclk_next;
end
end
endmodule
|
/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core TEST
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
`define AEMB_SIMULATION_KERNEL
module edk32 ();
`include "random.v"
// INITIAL SETUP //////////////////////////////////////////////////////
reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
reg svc;
integer inttime;
integer seed;
integer theend;
always #5 sys_clk_i = ~sys_clk_i;
initial begin
//$dumpfile("dump.vcd");
//$dumpvars(1,dut);
end
initial begin
seed = randseed;
theend = 0;
svc = 0;
sys_clk_i = $random(seed);
sys_rst_i = 1;
sys_int_i = 0;
sys_exc_i = 0;
#50 sys_rst_i = 0;
end
initial fork
//inttime $display("FSADFASDFSDAF");
//#10000 sys_int_i = 1;
//#1100 sys_int_i = 0;
//#100000 $displayh("\nTest Completed.");
//#4000 $finish;
join
// FAKE MEMORY ////////////////////////////////////////////////////////
wire fsl_stb_o;
wire fsl_wre_o;
wire [31:0] fsl_dat_o;
wire [31:0] fsl_dat_i;
wire [6:2] fsl_adr_o;
wire [15:2] iwb_adr_o;
wire iwb_stb_o;
wire dwb_stb_o;
reg [31:0] rom [0:65535];
wire [31:0] iwb_dat_i;
reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
reg [31:0] ram[0:65535];
wire [31:0] dwb_dat_i;
reg [31:0] dwblat;
wire dwb_we_o;
reg [15:2] dadr,iadr;
wire [3:0] dwb_sel_o;
wire [31:0] dwb_dat_o;
wire [15:2] dwb_adr_o;
wire [31:0] dwb_dat_t;
initial begin
dwb_ack_i = 0;
iwb_ack_i = 0;
fsl_ack_i = 0;
end
assign dwb_dat_t = ram[dwb_adr_o];
assign iwb_dat_i = ram[iadr];
assign dwb_dat_i = ram[dadr];
assign fsl_dat_i = fsl_adr_o;
`ifdef POSEDGE
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_ack_i <= 1'h0;
fsl_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
end // else: !if(sys_rst_i)
always @(posedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (posedge sys_clk_i)
`else // !`ifdef POSEDGE
always @(negedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_ack_i <= 1'h0;
fsl_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
fsl_ack_i <= #1 fsl_stb_o;
end // else: !if(sys_rst_i)
always @(negedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (negedge sys_clk_i)
`endif // !`ifdef POSEDGE
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
#1 $readmemh("dump.vmem",ram);
end
// DISPLAY OUTPUTS ///////////////////////////////////////////////////
integer rnd;
always @(posedge sys_clk_i) begin
// Interrupt Monitors
if (!dut.cpu.rMSR_IE) begin
rnd = $random % 30;
inttime = $stime + 1000 + (rnd*rnd * 10);
end
if ($stime > inttime) begin
sys_int_i = 1;
svc = 0;
end
if (($stime > inttime + 500) && !svc) begin
$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
$finish;
end
if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin
svc = 1;
//$display("\nLATENCY: ", ($stime - inttime)/10);
end
// Pass/Fail Monitors
if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
$display("\n\tFAIL");
$finish;
end
if (iwb_dat_i == 32'hb8000000) begin
theend = theend + 1;
end
if (theend == 5) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end
end // always @ (posedge sys_clk_i)
// INTERNAL WIRING ////////////////////////////////////////////////////
aeMB_sim #(16,16)
dut (
.sys_int_i(sys_int_i),
.dwb_ack_i(dwb_ack_i),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o),
.dwb_dat_o(dwb_dat_o),
.dwb_dat_i(dwb_dat_i),
.dwb_wre_o(dwb_we_o),
.dwb_sel_o(dwb_sel_o),
.fsl_ack_i(fsl_ack_i),
.fsl_stb_o(fsl_stb_o),
.fsl_adr_o(fsl_adr_o),
.fsl_dat_o(fsl_dat_o),
.fsl_dat_i(fsl_dat_i),
.fsl_wre_o(fsl_we_o),
.iwb_adr_o(iwb_adr_o),
.iwb_dat_i(iwb_dat_i),
.iwb_stb_o(iwb_stb_o),
.iwb_ack_i(iwb_ack_i),
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i)
);
endmodule // edk32
/*
$Log: edk32.v,v $
Revision 1.12 2007/12/23 20:40:51 sybreon
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
Revision 1.11 2007/12/11 00:44:31 sybreon
Modified for AEMB2
Revision 1.10 2007/11/30 17:08:30 sybreon
Moved simulation kernel into code.
Revision 1.9 2007/11/20 18:36:00 sybreon
Removed unnecessary byte acrobatics with VMEM data.
Revision 1.8 2007/11/18 19:41:45 sybreon
Minor simulation fixes.
Revision 1.7 2007/11/14 22:11:41 sybreon
Added posedge/negedge bus interface.
Modified interrupt test system.
Revision 1.6 2007/11/13 23:37:28 sybreon
Updated simulation to also check BRI 0x00 instruction.
Revision 1.5 2007/11/09 20:51:53 sybreon
Added GET/PUT support through a FSL bus.
Revision 1.4 2007/11/08 14:18:00 sybreon
Parameterised optional components.
Revision 1.3 2007/11/05 10:59:31 sybreon
Added random seed for simulation.
Revision 1.2 2007/11/02 19:16:10 sybreon
Added interrupt simulation.
Changed "human readable" simulation output.
Revision 1.1 2007/11/02 03:25:45 sybreon
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
*/ |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_0_V
`define SKY130_FD_SC_LP__A311O_0_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_0 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_0_V
|
#include <bits/stdc++.h> using namespace std; int N; int Move[100005], cnt, P[100005]; vector<int> G[100005]; int TT[100005], Next[100005]; int DP[100005], Stack[100005], top; void Read() { scanf( %d , &N); for (int i = 1; i < N; i++) { int father; scanf( %d , &father); ++father; G[father].push_back(i + 1); TT[i + 1] = father; } } void DFS(int node) { for (int i = 0; i < G[node].size(); i++) { int neighb = G[node][i]; DFS(neighb); DP[node] = max(DP[node], DP[neighb] + 1); } } void precalcPath() { int node = 1; while (G[node].size() != 0) { Stack[++top] = node; for (int i = 0; i < G[node].size(); i++) { int neighb = G[node][i]; if (DP[neighb] == DP[node] - 1) { swap(G[node][i], G[node][G[node].size() - 1]); G[node].pop_back(); node = neighb; break; } } } Stack[++top] = node; } void Solve(int node, int next) { int last = next; for (int i = 0; i < G[node].size(); i++) { int neighb = G[node][i]; TT[last] = neighb; Move[++cnt] = last; last = neighb; } for (int i = G[node].size() - 1; i >= 1; i--) Solve(G[node][i], G[node][i - 1]); if (G[node].size() > 0) Solve(G[node][0], next); } void printSol() { int node = 1; for (int i = 1; i <= N; i++) Next[TT[i]] = i; for (int i = 1; i <= N; i++) { printf( %d , node - 1); node = Next[node]; } printf( n%d n , cnt); for (int i = cnt; i >= 1; i--) printf( %d , Move[i] - 1); printf( n ); } int main() { Read(); DFS(1); precalcPath(); for (int i = 1; i < top; i++) Solve(Stack[i], Stack[i + 1]); printSol(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t, x, y, f1, f2, f3, f4, LIMH = 100000, LIML = -100000; cin >> t; while (t--) { int q; cin >> q; int hiX, loX, hiY, loY; hiX = LIMH; hiY = LIMH; loX = LIML; loY = LIML; for (int i = 0; i < q; i++) { cin >> x >> y >> f1 >> f2 >> f3 >> f4; if (!f1 && x > loX) loX = x; if (!f2 && y < hiY) hiY = y; if (!f3 && x < hiX) hiX = x; if (!f4 && y > loY) loY = y; } if (loX > hiX || loY > hiY) cout << 0 << endl; else cout << 1 << << loX << << loY << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> t; int n, x, i, j, h, sol, temp; int main() { ios::sync_with_stdio(false); cin >> n; for (i = 0; i < n; i++) { cin >> x; t.push_back(x); } cin >> h; sort(t.begin(), t.end()); sol = 0; for (i = 0; i < n; i++) { temp = 1; for (j = i + 1; j < n; j++) { if (t[j] - t[i] <= h) temp++; } sol = max(sol, temp); } cout << sol << endl; return 0; } |
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_macro_byte(words,bits,lgEls,mux) \
if (els_p == words && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_byte(words,bits,lgEls,mux) \
if (els_p == words && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_byte_banks(words,bits,lgEls,mux) \
if (els_p == 2*``words`` && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
wire [data_width_p-1:0] bank_data [0:1]; \
logic sel; \
always_ff @(posedge clk_i) \
sel <= addr_i[0]; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem0 \
(.A ( addr_i[addr_width_lp-1:1] ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i | addr_i[0] ) \
,.CEB ( ~v_i | addr_i[0] ) \
,.CLK ( clk_i ) \
,.Q ( bank_data[0] ) \
,.DELAY ( 2'b0 )); \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem1 \
(.A ( addr_i[addr_width_lp-1:1] ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i | ~addr_i[0] ) \
,.CEB ( ~v_i | ~addr_i[0] ) \
,.CLK ( clk_i ) \
,.Q ( bank_data[1] ) \
,.DELAY ( 2'b0 )); \
assign data_o = sel? bank_data[1]: bank_data[0]; \
end
module bsg_mem_1rw_sync_mask_write_byte
#(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
wire unused = reset_i;
`bsg_mem_1rw_sync_macro_byte(4096,64,12,8) else
`bsg_mem_1rw_sync_macro_byte(2048,64,11,4) else
`bsg_mem_1rw_sync_macro_byte(2048,64,11,4) else
`bsg_mem_1rf_sync_macro_byte_banks(512,32,9,4) else
`bsg_mem_1rf_sync_macro_byte(1024,32,10,8) else
`bsg_mem_1rw_sync_macro_byte(1024,32,10,4) else
// no hardened version found
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth
#(.els_p(els_p), .data_width_p(data_width_p))
synth (.*);
end
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
`include "../src/include/asym_ram.v"
`include "../src/include/line_reader.v"
`include "../src/include/scale_1d.v"
`include "../src/mm2s_adv.v"
`timescale 1ns / 1ps
module test();
localparam integer C_PIXEL_WIDTH = 8;
localparam integer C_PIXEL_STORE_WIDTH = 8;
localparam integer C_IMG_STRIDE_SIZE = 1024;
localparam integer C_IMG_WBITS = 12;
localparam integer C_IMG_HBITS = 12;
localparam integer C_M_AXI_BURST_LEN = 4;
localparam integer C_M_AXI_ADDR_WIDTH = 32;
localparam integer C_M_AXI_DATA_WIDTH = 32;
reg clk;
reg resetn;
reg soft_resetn;
/// mm to fifo
reg [C_IMG_WBITS-1:0] img_width;
reg [C_IMG_HBITS-1:0] img_height;
reg [C_IMG_WBITS-1:0] win_left;
reg [C_IMG_WBITS-1:0] win_width;
reg [C_IMG_HBITS-1:0] win_top;
reg [C_IMG_HBITS-1:0] win_height;
reg [C_IMG_WBITS-1:0] dst_width;
reg [C_IMG_HBITS-1:0] dst_height;
reg fsync;
wire sof;
wire [C_M_AXI_ADDR_WIDTH-1:0] frame_addr;
// Ports of Axi Master Bus Interface M_AXI
wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr;
wire [7 : 0] m_axi_arlen;
wire [2 : 0] m_axi_arsize;
wire [1 : 0] m_axi_arburst;
wire m_axi_arlock;
wire [3 : 0] m_axi_arcache;
wire [2 : 0] m_axi_arprot;
wire [3 : 0] m_axi_arqos;
wire m_axi_arvalid;
wire m_axi_arready;
reg [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata;
reg [1 : 0] m_axi_rresp;
wire m_axi_rlast;
reg m_axi_rvalid;
wire m_axi_rready;
wire m_axis_tvalid;
wire [C_PIXEL_WIDTH-1:0] m_axis_tdata;
wire m_axis_tuser;
wire m_axis_tlast;
reg m_axis_tready;
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
mm2s_adv #(
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_PIXEL_STORE_WIDTH(C_PIXEL_STORE_WIDTH),
.C_IMG_STRIDE_SIZE(C_IMG_STRIDE_SIZE),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) uut (
.clk(clk),
.resetn(resetn),
.soft_resetn(soft_resetn),
.img_width(img_width),
.img_height(img_height),
.win_left(win_left),
.win_width(win_width),
.win_top(win_top),
.win_height(win_height),
.dst_width(dst_width),
.dst_height(dst_height),
.fsync(fsync),
.sof(sof),
.frame_addr(frame_addr),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tdata(m_axis_tdata),
.m_axis_tuser(m_axis_tuser),
.m_axis_tlast(m_axis_tlast),
.m_axis_tready(m_axis_tready)
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg running;
initial begin
running <= 0;
repeat (20) #2 running <= 0;
repeat (1) #2 running <= 1;
forever #2 running <= 0;
end
assign frame_addr = 32'h3FF80000;
assign m_axi_arready = 1;
////////////////////////////////// file ////////////////////////////////////////
integer fileR, picType, dataPosition, grayDepth;
reg[80*8:0] outputFileName;
reg[11:0] outputFileIdx = 0;
integer fileW = 0;
initial begin
fileR=$fopen("a.pgm", "r");
$fscanf(fileR, "P%d\n%d %d\n%d\n", picType, img_width, img_height, grayDepth);
dataPosition=$ftell(fileR);
$display("header: %dx%d, %d", img_width, img_height, grayDepth);
win_left <= img_width/4 + 1;
win_width <= img_width/2;
win_top <= img_height/4 + 1;
win_height <= img_height/2;
dst_width <= img_width /4;
dst_height <= img_height /4;
end
////////////////////////////////////////////////////////////////////////////////
reg [C_M_AXI_ADDR_WIDTH-1:0] img_offset;
reg[7 : 0] burstIdx;
reg[C_M_AXI_ADDR_WIDTH-1:0] burstAddr;
always @(posedge clk) begin: readfile
integer i;
if (resetn == 0) begin
burstIdx = 0;
burstAddr = 0;
m_axi_rdata = 0;
end
else if (m_axi_arvalid && m_axi_arready) begin
burstIdx = m_axi_arlen;
burstAddr = m_axi_araddr;
img_offset = (burstAddr - frame_addr) / C_IMG_STRIDE_SIZE * img_width + (burstAddr - frame_addr) % C_IMG_STRIDE_SIZE;
$fseek(fileR, dataPosition + img_offset, 0);
for (i = 0; i < C_M_AXI_DATA_WIDTH; i = i+8) begin
m_axi_rdata[i+7 -: 8] = $fgetc(fileR);
end
end
else if (m_axi_rready && m_axi_rvalid && ~m_axi_rlast) begin
burstIdx = burstIdx - 1;
burstAddr = burstAddr + (C_M_AXI_DATA_WIDTH / 8);
img_offset = (burstAddr - frame_addr) / C_IMG_STRIDE_SIZE * img_width + (burstAddr - frame_addr) % C_IMG_STRIDE_SIZE;
$fseek(fileR, dataPosition + img_offset, 0);
for (i = 0; i < C_M_AXI_DATA_WIDTH; i = i+8) begin
m_axi_rdata[i+7 -: 8] = $fgetc(fileR);
end
end
end
assign m_axi_rlast = (burstIdx == 0);
reg readingmm;
always @(posedge clk) begin
if (resetn == 0) begin
readingmm <= 0;
end
else if (m_axi_arvalid && m_axi_arready) begin
readingmm <= 1;
end
else if (m_axi_rready && m_axi_rvalid && m_axi_rlast) begin
readingmm <= 0;
end
end
always @(posedge clk) begin
if (resetn == 0) begin
m_axi_rvalid <= 0;
end
else if (m_axi_rready && m_axi_rvalid && m_axi_rlast) begin
m_axi_rvalid <= 0;
end
else if (readingmm) begin
if (~m_axi_rvalid || m_axi_rready) begin
m_axi_rvalid <= (RANDOMINPUT ? {$random}%2 : 1);
end
end
end
//////////////////////////////////////////// output ////////////////////////////
always @(posedge clk) begin
if (resetn == 0) begin
m_axis_tready <= 0;
end
else if (~m_axis_tready || m_axis_tvalid)
m_axis_tready <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
reg [C_IMG_WBITS-1:0] m_axis_width;
reg [C_IMG_HBITS-1:0] m_axis_height;
reg [C_IMG_WBITS-1:0] m_axis_col;
reg [C_IMG_HBITS-1:0] m_axis_row;
reg [C_M_AXI_ADDR_WIDTH-1:0] outputFileIdx;
reg[80*8:0] outputFileName;
integer fileW = 0;
always @ (posedge clk) begin
if (resetn == 0) begin
m_axis_width <= 0;
m_axis_height <= 0;
outputFileIdx <= 0;
end
else if (fsync) begin
m_axis_width <= dst_width;
m_axis_height <= dst_height;
m_axis_col <= 1;
m_axis_row <= 1;
outputFileIdx <= outputFileIdx + 1;
$sformat(outputFileName, "output%0d.pgm", outputFileIdx);
fileW=$fopen(outputFileName, "w");
$display("outputFileName: %s - %0d", outputFileName, fileW);
$fwrite(fileW, "P%0d\n%0d %0d\n%0d\n", picType, dst_width, dst_height, grayDepth);
end
else if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_col > m_axis_width || m_axis_row > m_axis_height) begin
$error("too big frame!\n");
end
if (m_axis_tuser) begin
if (m_axis_col != 1 || m_axis_row != 1) begin
$error("start frame col/row index error!\n");
end
else begin
$write("start frame\n");
end
end
$write("%0d ", m_axis_tdata);
if (m_axis_tlast) begin
if (m_axis_col != m_axis_width) begin
$error("\nline end error!\n");
end
else begin
$write("\n");
end
end
$fwrite(fileW, "%c", m_axis_tdata);
if (m_axis_col == m_axis_width && m_axis_row == m_axis_height) begin
$fclose(fileW);
end
if (m_axis_tlast) begin
m_axis_row <= m_axis_row + 1;
m_axis_col <= 1;
end
else begin
m_axis_col <= m_axis_col + 1;
end
end
end
reg end_of_frame;
always @(posedge clk) begin
if (resetn == 0)
end_of_frame <= 0;
else if (end_of_frame)
end_of_frame <= 0;
else if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_col == m_axis_width && m_axis_row == m_axis_height)
end_of_frame <= 1;
end
end
reg framing;
always @(posedge clk) begin
if (resetn == 0)
framing <= 0;
else if (fsync)
framing <= 1;
else if (end_of_frame)
framing <= 0;
end
always @(posedge clk) begin
if (resetn == 0) begin
fsync <= 0;
soft_resetn <= 0;
end
else if (fsync) begin
fsync <= 0;
soft_resetn <= 0;
end
else if (~framing) begin
fsync <= 1;
soft_resetn <= 1;
win_left <= win_left + 1;
win_width <= win_width - 1;
win_top <= win_top + 1;
win_height <= win_height - 1;
dst_width <= dst_width + 1;
dst_height <= dst_height + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string a[100], b[100]; map<string, int> m; int n, s; int main(void) { scanf( %d , &n); for (int i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } for (int i = 0; i < n; i++) { cin >> b[i]; m[b[i]]--; } s += abs(m[ S ]); s += abs(m[ M ]); s += abs(m[ L ]); s += abs(m[ XS ]); s += abs(m[ XXS ]); s += abs(m[ XXXS ]); s += abs(m[ XL ]); s += abs(m[ XXL ]); s += abs(m[ XXXL ]); cout << s / 2; return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// clock divider generating clock and clock enable
module clock_divider
#(
parameter DIVISOR = 40000000
)
(
input wire CLK,
input wire RESET,
output reg CE, // for sequential logic driven by CLK
output reg CLOCK // only for combinatorial logic, does not waste bufg
);
integer counter_ce;
initial counter_ce = 0;
integer counter_clk;
initial counter_clk = 0;
initial CLOCK = 1'b0;
initial CE = 1'b0;
// clock enable
always @ (posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
CE <= 1'b0;
end
else
begin
if (counter_ce == 0)
begin
CE <= 1'b1;
end
else
begin
CE <= 1'b0;
end
end
end
always @ (posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
counter_ce <= 0;
end
else
begin
if (counter_ce == (DIVISOR - 1))
counter_ce <= 0;
else
counter_ce <= counter_ce + 1;
end
end
// clock
always @ (posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
CLOCK <= 1'b0;
end
else
begin
if (counter_clk == 0)
begin
CLOCK <= ~CLOCK;
end
else
begin
CLOCK <= CLOCK;
end
end
end
always @ (posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
counter_clk <= 0;
end
else
begin
if (counter_clk == ((DIVISOR >> 1) - 1)) // DIVISOR/2
counter_clk <= 0;
else
counter_clk <= counter_clk + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a; cin >> a; if (a < 2520) { cout << 0; } else { cout << a / 2520; } return 0; } |
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Table containing collision detection results.
`include "collision.vh"
`define MPU_DATA_WIDTH 16
module CollisionTable(clk, reset,
write_collision, table_index, table_value,
wr, be, addr, data_in, data_out);
input clk; // System clock.
input reset; // System reset.
// Interface to write collision info.
// TODO: consider registering these inputs to improve timing.
input write_collision; // Enable writing to table.
input [`COLL_ADDR_WIDTH-1:0] table_index; // Index of table entry.
input [`COLL_DATA_WIDTH-1:0] table_value; // Value to write to table.
// Interface for reading from collision table.
input wr; // Write enable.
input [1:0] be; // Byte enable.
input [`COLL_ADDR_WIDTH-1:0] addr; // Address bus.
input [`MPU_DATA_WIDTH-1:0] data_in; // Data to write.
output [`MPU_DATA_WIDTH-1:0] data_out; // Data that was read.
// Determine what data is being read.
assign data_out = table_select ? table_data_out :
(reg_select ? status_regs[reg_addr] : 0);
// Select the collision status registers.
wire reg_select = (addr >= `COLL_REGS_BASE) &
(addr < `COLL_REGS_BASE + `NUM_COLL_STATUS_REGS);
wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;
wire reg_reset = reset | (wr & (addr == `COLL_REGS_CLEAR));
// Per-sprite collision status registers.
reg [`MPU_DATA_WIDTH-1:0] status_regs[`NUM_COLL_STATUS_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_COLL_STATUS_REGS; i = i + 1) begin : REGS
always @ (posedge reg_reset or posedge clk) begin
if (reg_reset)
status_regs[i] <= 0;
else if (write_collision & table_index / `MPU_DATA_WIDTH == i)
status_regs[i][table_index % `MPU_DATA_WIDTH] <= 1;
end
end
endgenerate
// Select the collision lookup table.
wire table_select = (addr >= `COLL_TABLE_BASE) &
(addr < `COLL_TABLE_BASE + `COLL_TABLE_SIZE);
wire [`MPU_DATA_WIDTH-1:0] table_data_out;
// Table containing list of actual collisions.
collision_table_256x16 collision_table(
.clock(clk),
// Convert byte to word.
.wren_a(write_collision),
.byteena_a(table_index[0] ? 'b10 : 'b01),
.address_a(table_index / 2),
.data_a({table_value[`BYTE_WIDTH-1:0], table_value[`BYTE_WIDTH-1:0]}),
.wren_b(0), // MPU-side interface is read-only.
.address_b(addr - `COLL_TABLE_BASE),
.q_b(table_data_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 31400; struct point { int x, y; }; int n; pair<point, point> p[5]; bool used[5]; bool func() { long long s = 0; point MIN, MAX; MIN.x = MIN.y = NMAX; MAX.x = MAX.y = 0; for (int i = 0; i < n; i++) { s += (p[i].second.x - p[i].first.x) * (p[i].second.y - p[i].first.y); MIN.x = min(MIN.x, p[i].first.x); MIN.y = min(MIN.y, p[i].first.y); MAX.x = max(MAX.x, p[i].second.x); MAX.y = max(MAX.y, p[i].second.y); } if ((MAX.x - MIN.x) == (MAX.y - MIN.y) && s == pow(MAX.x - MIN.x, 2)) { return true; } return false; } int main() { cin >> n; pair<int, int> a, b, MAX, MIN; for (int i = 0; i < n; i++) { cin >> p[i].first.x >> p[i].first.y >> p[i].second.x >> p[i].second.y; } if (func()) cout << YES ; else cout << NO ; return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// idxram.v: indices RAM //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module idxram
#( parameter CDEP = 4 , // depth (k-entries, power of 2)
parameter PIPE = 1 ) // pipelined?
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input [4 :0] vacFLoc , // vacancy first location
input [4 :0] newPattOccFLoc , // first location of a new pattern occurrence
output [4 :0] oldIdx , // old pattern index
output [4 :0] newIdx ); // new pattern index
wire [2 :0] wAddrLL = wAddr[2 :0];
wire [1 :0] wAddrLH = wAddr[4 :3];
wire [4 :0] wAddrL = wAddr[4 :0];
wire [`log2(CDEP)+4:0] wAddrH = wAddr[`log2(CDEP)+9:5];
wire [32*5-1:0] rIdx;
genvar gi;
generate
for (gi=0 ; gi<4 ; gi=gi+1) begin: STG
// instantiate M20K
mwm20k #( .WWID (5 ), // write width
.RWID (40 ), // read width
.WDEP (CDEP*1024/4 ), // write lines depth
.OREG (0 ), // read output reg
.INIT (1 )) // initialize to zeros
idxrami ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb ( wEnb && (gi==wAddrLH)), // write enable // input : choose block
.wAddr ({wAddrH,wAddrLL} ), // write address // input [`log2(WDEP)-1 :0]
.wData (vacFLoc ), // write data // input [WWID-1 :0]
.rAddr (wAddrH ), // read address // input [`log2(WDEP/(RWID/WWID))-1:0]
.rData (rIdx[gi*40 +: 40] )); // read data // output [RWID-1 :0]
end
endgenerate
///////////////////////////////////////////////////////////////////////////////
// generate old pattern index
`ifdef SIM
// HDL muxes
assign oldIdx = rIdx[ wAddrL*5 +: 5];
`else
// custom synthesis muxes
mux_oldIdx mux_oldIdx_inst(clk,rst,rIdx,wAddrL,oldIdx);
`endif
///////////////////////////////////////////////////////////////////////////////
// generate new pattern index
`ifdef SIM
// HDL muxes
assign newIdx = rIdx[newPattOccFLoc*5 +: 5];
`else
// custom synthesis muxes
mux_newIdx mux_newIdx_inst(clk,rst,rIdx,newPattOccFLoc,newIdx);
`endif
///////////////////////////////////////////////////////////////////////////////
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long SIZE = 100000; const int INF = 0x3f3f3f3f; const long long ll_INF = 0x3f3f3f3f3f3f3f3f; const long double PI = acos(-1); const long long MAXN = numeric_limits<long long>::max(); const long long MAX = 2000000; void solve() { string s; long long k, i = 1; cin >> k; while (((int)(s).size()) < k) { s += to_string(i); i++; } cout << s[k - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_4_V
`define SKY130_FD_SC_HS__XOR3_4_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_4_V
|
#include <bits/stdc++.h> using namespace std; int M[2002][2002]; struct TA { int a[2002], n; void init(int _n) { n = _n; memset(a, 0, sizeof a); } int get(int p) { int ret = 0; for (p++; p > 0; p -= p & -p) ret ^= a[p - 1]; return ret; } void change(int l) { for (l++; l <= n; l += l & -l) a[l - 1] ^= 1; } void change(int l, int r) { change(l); change(r + 1); } } R[2002], C[2002]; void put(int r, int c) { R[r].change(min(r, c), max(r, c)); C[c].change(min(r, c), max(r, c)); M[r][c] ^= 1; } int get(int r, int c) { return R[r].get(c) ^ C[c].get(r) ^ M[r][c]; } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( ); for (int j = 0; j < n; ++j) { M[i][j] = getchar() == 1 ; } R[i].init(n); C[i].init(n); } int ans = 0; for (int i = 0; i < n; ++i) { for (int r = n - 1; r > i; --r) { if (get(r, i)) { ++ans; put(r, i); } } for (int c = n - 1; c > i; --c) { if (get(i, c)) { ++ans; put(i, c); } } if (get(i, i)) { ++ans; put(i, i); } } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_2_V
`define SKY130_FD_SC_LS__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, i, m, x, s = 0; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> x; s += x; } if (s == m) cout << YES ; else cout << NO ; cout << n ; } return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
// (sender) Each tile sends a packet to every tile.
// (receiver) The tile assert done_o, when it has received packets from everyone.
module test_tile
import test_pkg::*;
import bsg_noc_pkg::*;
#(parameter dims_p=2
, parameter x_cord_width_p=4
, parameter y_cord_width_p=3
, parameter num_tiles_x_p=16
, parameter num_tiles_y_p=8
, parameter data_width_p=32
, parameter ruche_factor_X_p=0
, parameter ruche_factor_Y_p=0
, parameter XY_order_p=1
, parameter dirs_lp=(dims_p*2)+1
, parameter link_sif_width_lp = `test_link_sif_width(data_width_p,x_cord_width_p,y_cord_width_p)
)
(
input clk_i
, input reset_i
, input [dirs_lp-1:W][link_sif_width_lp-1:0] link_i
, output [dirs_lp-1:W][link_sif_width_lp-1:0] link_o
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output logic done_o
);
typedef int fifo_els_arr_t[dirs_lp-1:0];
function fifo_els_arr_t get_fifo_els();
fifo_els_arr_t retval;
for (int i = 0; i < dirs_lp; i++) begin
retval[i] = 2;
end
return retval;
endfunction
localparam num_tiles_lp = num_tiles_x_p*num_tiles_y_p;
`declare_test_link_sif_s(data_width_p,x_cord_width_p,y_cord_width_p);
test_link_sif_s [dirs_lp-1:P] link_li;
test_link_sif_s [dirs_lp-1:P] link_lo;
assign link_li[dirs_lp-1:W] = link_i;
assign link_o = link_lo[dirs_lp-1:W];
test_packet_s packet_lo;
test_packet_s packet_li;
assign link_li[P].data = packet_li;
assign packet_lo = link_lo[P].data;
bsg_mesh_router_buffered #(
.width_p(`test_packet_width(data_width_p,x_cord_width_p,y_cord_width_p))
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.ruche_factor_X_p(ruche_factor_X_p)
,.ruche_factor_Y_p(ruche_factor_Y_p)
,.dims_p(dims_p)
,.fifo_els_p(get_fifo_els())
,.XY_order_p(XY_order_p)
) router (
.clk_i(clk_i)
,.reset_i(reset_i)
,.link_i(link_li)
,.link_o(link_lo)
,.my_x_i(my_x_i)
,.my_y_i(my_y_i)
);
wire [data_width_p-1:0] my_id = (data_width_p)'(my_x_i+(my_y_i*num_tiles_x_p));
// sender
logic [x_cord_width_p-1:0] curr_x_r, curr_x_n;
logic [y_cord_width_p-1:0] curr_y_r, curr_y_n;
integer send_count_r, send_count_n;
assign packet_li.x_cord = curr_x_r;
assign packet_li.y_cord = curr_y_r;
assign packet_li.data = my_id;
always_comb begin
send_count_n = send_count_r;
curr_x_n = curr_x_r;
curr_y_n = curr_y_r;
link_li[P].v = 1'b0;
if (send_count_r != num_tiles_lp) begin
link_li[P].v = 1'b1;
if (link_lo[P].ready_and_rev) begin
curr_x_n = (curr_x_r == num_tiles_x_p-1)
? '0
: (curr_x_r + 1);
curr_y_n = (curr_x_r == num_tiles_x_p-1)
? curr_y_r + 1
: curr_y_r;
send_count_n = send_count_r + 1;
end
end
else begin
link_li[P].v = 1'b0;
end
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
curr_x_r <= '0;
curr_y_r <= '0;
send_count_r <= '0;
end
else begin
curr_x_r <= curr_x_n;
curr_y_r <= curr_y_n;
send_count_r <= send_count_n;
end
end
// receiver
logic [num_tiles_lp-1:0] v_r, v_n;
assign link_li[P].ready_and_rev = 1'b1;
assign v_n = link_lo[P].v << packet_lo.data;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_r <= '0;
end
else begin
for (integer i = 0; i < num_tiles_lp; i++) begin: l
if (v_n[i]) begin
v_r[i] <= 1'b1;
$display("(x,y)=(%2d,%2d) receiving id=%6d.", my_x_i, my_y_i, packet_lo.data);
end
end
// assert that packet arrived at correct dest.
if (link_lo[P].v) begin
assert((packet_lo.x_cord == my_x_i) & (packet_lo.y_cord == my_y_i)) else
$error("[BSG_ERROR] wrong packet (%0d, %0d) arrived at (%0d, %0d).",
packet_lo.x_cord, packet_lo.y_cord,
my_x_i, my_y_i
);
end
end
end
assign done_o = &v_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int x, in; } arr[210000], qu[210000]; int n, m, k, ans, len; int head, tail; int cmp(node a, node b) { if (a.x == b.x) return a.in < b.in; else return a.x < b.x; } int main() { int i, j, tp; while (scanf( %d%d%d , &n, &m, &k) != EOF) { for (i = 1; i <= n; ++i) scanf( %d , &arr[i].x), arr[i].in = i; sort(arr + 1, arr + 1 + n, cmp); ans = 1, len = 0; head = 0, tail = 1; qu[++head] = arr[1]; for (i = 2; i <= n; ++i) { if (arr[i].x != qu[head].x) { while (tail < head) tail++; len = head = 0; tail = 1; qu[++head] = arr[i]; } else { tp = arr[i].in - qu[head].in - 1; if (tp + len > k) { while (tp + len > k && tail < head) { len -= qu[tail + 1].in - qu[tail].in - 1; tail++; } if (tail == head) len = 0; } len += tp; qu[++head] = arr[i]; } if (head - tail + 1 > ans) ans = head - tail + 1; } printf( %d n , ans); } } |
#include <bits/stdc++.h> using namespace std; int cnt[200001], n, par; vector<int> adj[200001]; vector<pair<int, int> > v; void count(int h, int p) { cnt[h]++; for (auto it : adj[h]) if (it ^ p) { count(it, h); cnt[h] += cnt[it]; } } int ct(int h, int p) { for (auto it : adj[h]) if (it ^ p) { if (cnt[it] > n / 2) return ct(it, h); } par = p; return h; } vector<pair<int, pair<int, int> > > res; void dfs(int h, int p) { for (auto it : adj[h]) if (it ^ p) { dfs(it, h); } v.push_back({h, p}); } void f(int h, int p) { v.clear(); dfs(h, p); v.pop_back(); int t = h; for (auto it : v) { res.push_back({p, {t, it.first}}); res.push_back({it.first, {it.second, h}}); t = it.first; } res.push_back({p, {t, h}}); } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); adj[x].push_back(y); adj[y].push_back(x); } count(1, 0); int cen = ct(1, 0), cen2 = 0; for (auto it : adj[cen]) if (par != it && 2 * cnt[it] == n) cen2 = it; for (auto it : adj[cen]) if (it != cen2) f(it, cen); for (auto it : adj[cen2]) if (it != cen) f(it, cen2); printf( %d n , res.size()); for (auto it : res) printf( %d %d %d n , it.first, it.second.first, it.second.second); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:33 09/09/2014
// Design Name:
// Module Name: sevensegdecoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sevensegdecoder(
input [4:0] nIn,
output reg [6:0] ssOut
);
always @(nIn)
case (nIn)
5'h0: ssOut = 7'b1000000;
5'h1: ssOut = 7'b1111001;
5'h2: ssOut = 7'b0100100;
5'h3: ssOut = 7'b0110000;
5'h4: ssOut = 7'b0011001;
5'h5: ssOut = 7'b0010010;
5'h6: ssOut = 7'b0000010;
5'h7: ssOut = 7'b1111000;
5'h8: ssOut = 7'b0000000;
5'h9: ssOut = 7'b0011000;
5'hA: ssOut = 7'b0001000;
5'hB: ssOut = 7'b0000011;
5'hC: ssOut = 7'b1000110;
5'hD: ssOut = 7'b0100001;
5'hE: ssOut = 7'b0000110;
5'hF: ssOut = 7'b0001110;
5'h10: ssOut = 7'b0101111;
5'h11: ssOut = 7'b0001100;
5'h12: ssOut = 7'b0000110;
5'h13: ssOut = 7'b1111111;
default: ssOut = 7'b1001001;
endcase
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:07:26 01/23/2017
// Design Name: bi_directional_shift
// Module Name: /home/aaron/Git Repos/CSE311/lab1_reverse/bi_directional_shift_tb.v
// Project Name: lab1_reverse
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bi_directional_shift
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bi_directional_shift_tb;
// Inputs
reg [7:0] d_in;
reg [2:0] shift_amount;
reg shift_direction;
// Outputs
wire [7:0] shifter_out;
// Instantiate the Unit Under Test (UUT)
bi_directional_shift uut (
.d_in(d_in),
.shift_amount(shift_amount),
.shift_direction(shift_direction),
.shifter_out(shifter_out)
);
initial begin
// Initialize Inputs
d_in = 0;
shift_amount = 0;
shift_direction = 0;
// Wait 100 ns for global reset to finish
#100;
// Test Case 1: Shift Right by 2
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b1;
#100;
// Test Case 2: Shift Left by 2
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_TB_V
`define SKY130_FD_SC_LP__A22OI_TB_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a22oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_TB_V
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T_container, typename T = typename enable_if< !is_same<T_container, string>::value, typename T_container::value_type>::type> ostream &operator<<(ostream &os, const T_container &v) { os << { ; string sep; for (const T &x : v) os << sep << x, sep = , ; return os << } ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } const int MX = 1e5 + 1; int cnt = 0; vector<int> adj[MX]; bool vis[MX]; void dfs(int node) { if (vis[node]) return; vis[node] = true; for (auto &u : adj[node]) if (!vis[u]) dfs(u); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; unordered_map<int, bool> mp; for (int i = 1; i <= n; ++i) { int tmp; cin >> tmp; adj[i].emplace_back(tmp); adj[tmp].emplace_back(i); } for (int i = 1; i <= n; ++i) { if (vis[i]) continue; ++cnt; dfs(i); } cout << cnt << n ; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; template <class T> using pq = priority_queue<T>; template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T& x) { int first = 0; cerr << { ; for (auto& i : x) cerr << (first++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const int MOD = 1000000007; const char nl = n ; const int MX = 100001; void solve() { int N; cin >> N; int A[N]; for (int i = 0; i < (N); i++) cin >> A[i]; int sum = 0; for (int i = 0; i < (N); i++) sum += A[i]; if (sum % 2) { cout << NO << nl; return; } int cnt = 0; vector<int> ops; for (int i = 0; i < (N); i++) { cnt += A[i]; if (A[i] == 0) { if (cnt % 2) { ops.push_back(i - 1); int X = 0; for (int j = 0; j < (3); j++) X ^= A[i - 1 + j]; for (int j = 0; j < (3); j++) A[i - 1 + j] = X; } if (A[i] == 0) { cnt = 0; } else cnt++; } } sum = 0; for (int i = 0; i < (N); i++) sum += A[i]; if (sum == N) { cout << NO << nl; return; } int fz = 0; for (int i = (N)-1; i >= 0; i--) if (A[i] == 0) fz = i; while (fz > 0) { ops.push_back(fz - 2); A[fz - 2] = 0; A[fz - 1] = 0; A[fz] = 0; fz -= 2; } for (int i = 0; i < (N - 1); i++) { if (A[i] == 0 && A[i + 1] == 1) { ops.push_back(i); A[i] = 0; A[i + 1] = 0; A[i + 2] = 0; } } cout << YES << nl; cout << (int)(ops).size() << nl; for (auto& a : ops) { cout << a + 1 << ; } cout << nl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int T = 1; cin >> T; while (T--) { solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_SYMBOL_V
`define SKY130_FD_SC_LP__O32AI_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__BUFBUF_PP_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, s, inp; int c[10]; int best = -1; int b3, b4, b5; struct bezout { long long d, a, b; }; bezout extgcd(long long x, long long y) { if (y == 0) return (bezout){x, 1, 0}; bezout s = extgcd(y, x % y); return (bezout){s.d, s.b, s.a - x / y * s.b}; } void check(int k3, int k4, int k5) { int a = k3 * c[3], b = k4 * c[4], z = k5 * c[5]; if (a + b + z != s) return; if (k3 < 0 || k3 > k4 || k4 > k5 || k3 > k5) return; int ct = abs(a - b) + abs(z - b); if (best == -1 || best > ct) { best = ct; b3 = k3; b4 = k4; b5 = k5; } } int main() { scanf( %d %d , &n, &s); for (int i = 0; i < n; i++) { scanf( %d , &inp); c[inp]++; } for (int k4 = 0; c[4] * k4 <= s; k4++) { int C = s - c[4] * k4; bezout t = extgcd(c[3], c[5]); if (C % t.d != 0) continue; long long k3 = t.a * C / t.d; long long k5 = t.b * C / t.d; int lcm = c[3] * c[5] / t.d; int inc3 = lcm / c[3], inc5 = lcm / c[5]; if (k3 >= 0) { int mod = k3 / inc3; k3 = k3 % inc3; k5 = k5 + mod * inc5; } if (k3 < 0) { int mod = -k3 / inc3; if ((-k3) % inc3 != 0) mod++; k3 = k3 + inc3 * mod; k5 = k5 - inc5 * mod; } check(k3, k4, k5); int st = 0, ed = s; while (st < ed) { int m = (st + ed + 1) / 2; int nk5 = k5 - m * inc5; if (k3 + m * inc3 <= k4 && nk5 >= k4 && c[5] * nk5 >= c[4] * k4) st = m; else ed = m - 1; } int maxk3 = k3 + inc3 * st; int maxk5 = k5 - inc5 * st; check(maxk3, k4, maxk5); check(maxk3 + inc3, k4, maxk5 - inc5); } if (best == -1) printf( %d n , best); else printf( %d %d %d n , b3, b4, b5); } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:47 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_stub.v
// Design : bg_pole
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bg_pole(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[6:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [6:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Edge { int u, v; } e[200050 << 1]; int fa[200050]; int n, color[200050], s, d; int cnt[2], dis[200050]; bool vis[200050]; vector<int> G[200050]; int find(int x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } void _union(int x, int y) { int f1 = find(x); int f2 = find(y); if (f1 == f2) return; if (f1 < f2) fa[f2] = f1; else fa[f1] = f2; } queue<int> q; void bfs(int u) { memset(vis, false, sizeof(vis)); memset(dis, 0, sizeof(dis)); while (!q.empty()) q.pop(); q.push(u); vis[u] = true; while (!q.empty()) { int now = q.front(); q.pop(); for (int i = 0; i < G[now].size(); i++) { int v = G[now][i]; if (!vis[v]) { q.push(v); vis[v] = true; s = v; dis[v] = dis[now] + 1; } } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &color[i]); fa[i] = i; } for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); e[2 * i - 1].u = u; e[2 * i - 1].v = v; e[i * 2].u = v; e[i * 2].v = u; if (color[u] == color[v]) _union(u, v); } for (int i = 1; i <= n; i++) fa[i] = find(i); for (int i = 1; i < n; i++) { int u = e[i * 2 - 1].u, v = e[i * 2 - 1].v; if (fa[u] != fa[v]) { G[fa[u]].push_back(fa[v]); G[fa[v]].push_back(fa[u]); } } int i = 1; for (; G[i].size() == 0 && i <= n; i++) ; if (i > n) { printf( 0 n ); return 0; } bfs(i); bfs(s); printf( %d n , (dis[s] + 1) / 2); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<long long> a; for (int i = 0; i < n; i++) { long long x; cin >> x; a.push_back(x); } long long m = 0; for (int i = 0; i < (n - 1); i++) { long long x = a[i] * a[i + 1]; if (x > m) m = x; } cout << m << endl; } } |
//-----------------------------------------------------
// Design Name : hw2_A
// File Name : hw2_A.v
// Function : This program designs an One-Pulse Generator.
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_A (
input in,
input clk,
input rst_n,
output reg out
);
parameter S0 = 0;
parameter S1 = 1;
reg state, nextState;
reg tmp_out;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= S0;
end else begin
state <= nextState;
end // end of if-else block
end // end of always
// next state
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
nextState <= 0;
end else begin // 0 -> 1 => 1
nextState <= 1;
end
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 0
nextState <= 0;
end else begin // 1 -> 1 => 0;
nextState <= 1;
end
end
endcase
end
// output
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
tmp_out <= 0;
end else begin // 0 -> 1 => 1
tmp_out <= 1;
end
end
S1: begin // previous input is 1
tmp_out <= 0;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
out <= 0;
end else begin
out <= tmp_out;
end
end
endmodule // endmodule of hw2_A
|
#include <bits/stdc++.h> using namespace std; vector<int> z; vector<int> pr; vector<vector<int>> ans; int s, f; long long pow(long long n, long long s) { if (s == 0) return 1; else { if (s % 2 == 1) { return (n * (pow(n, s - 1))) % 1000000007; } if (s % 2 == 0) { long long k = (pow(n, s / 2)) % 1000000007; return (k * k) % 1000000007; } } } void prfix(string s) { for (int i = 1; i < s.size(); i++) { pr[i] = pr[i - 1]; while (pr[i] > 0 && s[i] != s[pr[i]]) { pr[i] = pr[pr[i] - 1]; } if (s[i] == s[pr[i]]) pr[i]++; } } void zet(string s) { int l = 0, r = 0; for (int i = 1; i < s.size(); i++) { if (i <= r) { z[i] = min(z[i - l], r - i + 1); } for (; z[i] + i < s.size() && s[z[i] + i] == s[z[i]]; z[i]++) ; if (i + z[i] - 1 >= r) { l = i; r = i + z[i] - 1; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long double R, x1, y1, x2, y2; cin >> R >> x1 >> y1 >> x2 >> y2; if (sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)) >= R) { cout << x1 << << y1 << << R; return 0; } if (x1 == x2 && y1 == y2) { long double y3 = y1 + R / 2; cout << x1 << << y3 << << R / 2; return 0; } long double c = sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); long double x4 = (x1 - x2) * (R + c) / 2 / c + x2; long double y4 = (y1 - y2) * (R + c) / 2 / c + y2; cout.precision(10); cout << fixed << x4 << << y4 << << (R + c) / 2; } |
#include <bits/stdc++.h> using namespace std; long long head[100005]; long long memory[100005]; int n, m; bool possible(long long t) { int curr = 1; for (int i = 1; i <= n; i++) { long long headloc = head[i]; if (headloc <= memory[curr]) { headloc += t; while (headloc >= memory[curr] && curr <= m) curr++; } else { if (headloc - t > memory[curr]) return false; long long d = headloc - memory[curr]; long long next = max(headloc + (t - d) / 2, headloc + (t - 2 * d)); headloc = next; while (headloc >= memory[curr] && curr <= m) curr++; } if (curr == m + 1) return true; } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> head[i]; for (int i = 1; i <= m; i++) cin >> memory[i]; long long start = 0; long long endi = 20000000000; while (start < endi) { long long mid = (start + endi) / 2; if (possible(mid)) endi = mid; else start = mid + 1; } cout << endi; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_BLACKBOX_V
`define SKY130_FD_SC_LS__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long t, n, k, z, x, s, a[31], v[31][101], c[31]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; cin >> t; for (int zxc = 1; zxc <= t; zxc++) { cin >> n >> k; for (int i = 1; i <= 30; i++) for (int j = 1; j <= 100; j++) v[i][j] = 0; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { long long z = a[i]; long long x = 0; while (z != 0) { x++; v[i][x] = z % k; z /= k; } } int ff = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= 100; j++) { if (v[i][j] > 1) { ff = 1; break; } } if (ff == 1) break; } if (ff == 1) cout << NO << n ; else { for (int j = 1; j <= 100; j++) { long long x = 0; for (int i = 1; i <= n; i++) if (v[i][j] == 1) x++; if (x > 1) { ff = 1; break; } } if (ff == 1) cout << NO << n ; else cout << YES << n ; } } } |
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : v7_enet_top.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Merged Ethernet Controller Top File for V7
//
//--------------------------------------------------------------------------------
module ethernet_top(
input i_rst,
input i_clk_125,
input i_clk_200,
output phy_resetn,
// V6 GMII I/F
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
output gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
input gmii_col,
input gmii_crs,
input mii_tx_clk,
// V7 SGMII I/F
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// PHY MDIO I/F
output mdio_out,
input mdio_in,
output mdc_out,
output mdio_t,
//Reg file
input i_enet_enable, // Enable the ethernet core
input i_enet_loopback, // Enable loopback mode
input [31:0] i_enet_ddr_source_addr, // Where is data for ethernet
input [31:0] i_enet_ddr_dest_addr, // Where to store ethernet data
input [31:0] i_enet_rcv_data_size, // How much data should be received from enet
input [31:0] i_enet_snd_data_size, // How much data should be sent through enet
output [31:0] o_enet_rx_cnt, // Ethernet RX Performance Counter
output [31:0] o_enet_tx_cnt, // Ethernet TX Performance Counter
output o_enet_rx_done, // Ethernet RX Completed
output o_enet_tx_done, // Ethernet TX Completed
//To DDR controller
output o_ddr_wr_req,
output o_ddr_rd_req,
output [255:0] o_ddr_wr_data,
output [31:0] o_ddr_wr_be,
output [31:0] o_ddr_wr_addr,
output [31:0] o_ddr_rd_addr,
input [255:0] i_ddr_rd_data,
input i_ddr_wr_ack,
input i_ddr_rd_ack,
input i_ddr_rd_data_valid
);
// Instantiate V7 Top File
v7_ethernet_top v7_et
(
.glbl_rst(i_rst),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_in),
.mdio_o(mdio_out),
.mdio_t(mdio_t),
.mdc(mdc_out),
.i_enet_enable(i_enet_enable),
.i_enet_loopback(i_enet_loopback),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid)
);
endmodule |
//¶¥²ãÄ£¿é
module top_greedy_snake
(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
);
wire left_key_press;
wire right_key_press;
wire up_key_press;
wire down_key_press;
wire [1:0]snake;
wire [9:0]x_pos;
wire [9:0]y_pos;
wire [5:0]apple_x;
wire [4:0]apple_y;
wire [5:0]head_x;
wire [5:0]head_y;
wire add_cube;
wire[1:0]game_status;
wire hit_wall;
wire hit_body;
wire die_flash;
wire restart;
wire [6:0]cube_num;
wire rst_n;
wire [15:0] point;
assign rst_n = ~rst;
Game_Ctrl_Unit U1 (
.clk(clk),
.rst(rst_n),
.key1_press(left_key_press),
.key2_press(right_key_press),
.key3_press(up_key_press),
.key4_press(down_key_press),
.game_status(game_status),
.hit_wall(hit_wall),
.hit_body(hit_body),
.die_flash(die_flash),
.restart(restart)
);
Snake_Eatting_Apple U2 (
.clk(clk),
.rst(rst_n),
.apple_x(apple_x),
.apple_y(apple_y),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube)
);
Snake U3 (
.clk(clk),
.rst(rst_n),
.left_press(left_key_press),
.right_press(right_key_press),
.up_press(up_key_press),
.down_press(down_key_press),
.snake(snake),
.x_pos(x_pos),
.y_pos(y_pos),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube),
.game_status(game_status),
.cube_num(cube_num),
.hit_body(hit_body),
.hit_wall(hit_wall),
.die_flash(die_flash),
.point(point)
);
VGA_top U4 (
.clk(clk),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
Key U5 (
.clk(clk),
.rst(rst_n),
.left(left),
.right(right),
.up(up),
.down(down),
.left_key_press(left_key_press),
.right_key_press(right_key_press),
.up_key_press(up_key_press),
.down_key_press(down_key_press)
);
Seg_Display U6 (
.clk(clk),
.rst(rst_n),
.add_cube(add_cube),
.game_status(game_status),
.seg_out(seg_out),
.sel(sel),
.point(point)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 2e2 + 10; int main() { int n, m; cin >> n >> m; int l = 1, r = INF; int ans = 0; while (l <= r) { int mid = (r + l) / 2; int z = mid / 6; int x = mid / 2 - z; int y = mid / 3 - z; if (z >= max(0, n - x) + max(0, m - y)) ans = mid, r = mid - 1; else l = mid + 1; } cout << ans << endl; return 0; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: four_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module four_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/four_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/four_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; vector<int> zp; int zer; int one; int n; int allz; int q() { cout << ? << ; for (int i = 0; i < n; i++) { cout << zp[i]; } cout << endl; int x; cin >> x; return x; } void get(int bg, int ed, int W) { if ((zer != -1) and (one != -1)) { return; } int cur = W; int L = ed - bg; int d = cur - allz; if (d == -L) { one = bg; return; } if (d == L) { zer = bg; return; } int mid = (bg + ed) / 2; for (int i = mid; i < ed; i++) { zp[i] = 0; } int D = q(); get(bg, mid, D); for (int i = mid; i < ed; i++) { zp[i] = 1; } if ((zer != -1) and (one != -1)) { return; } for (int i = bg; i < mid; i++) { zp[i] = 0; } get(mid, ed, W - D + allz); for (int i = bg; i < mid; i++) { zp[i] = 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; zp.resize(n); zer = -1; one = -1; allz = q(); for (int i = 0; i < n; i++) { zp[i] = 1; } get(0, n, n - allz); cout << ! << zer + 1 << << one + 1 << endl; return 0; } |
// $Id: c_dff.v 1752 2010-02-12 02:16:21Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// configurable register
module c_dff
(clk, reset, d, q);
`include "c_constants.v"
// width of register
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter [offset:(offset+width)-1] reset_value = {width{1'b0}};
input clk;
input reset;
// data input
input [offset:(offset+width)-1] d;
// data output
output [offset:(offset+width)-1] q;
reg [offset:(offset+width)-1] q;
generate
case(reset_type)
`RESET_TYPE_ASYNC:
always @(posedge clk, posedge reset)
if(reset)
q <= reset_value;
else
q <= d;
`RESET_TYPE_SYNC:
always @(posedge clk)
if(reset)
q <= reset_value;
else
q <= d;
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; mt19937 rng; ll MAX = 1e18; const int MN = 1e3 + 100; int get_rand(int x) { return static_cast<int>(static_cast<ll>(rng()) * x / (static_cast<ll>(rng.max()) - rng.min() + 1)); } int N; ll L, E; array<ll, 2> ans[MN]; ll get(int f, ll x) { printf( ? %d %lld n , f, x); fflush(stdout); ll r; scanf( %lld , &r); return r; } ll loc(int f, ll v, ll l = 0, ll r = MAX) { r++; ll m; while (r - l > 1) { m = l + (r - l >> 1); if (get(f, m) > v) r = m; else l = m; } return l; } void solve(vector<int>& v, int l, int r, ll lp, ll rp) { if (v.size() == 1) return ans[v[0]] = {lp, rp}, void(); random_shuffle(v.begin(), v.end(), get_rand); int m = l + (r - l >> 1); ll mp; function<ll(vector<int>&, int)> kth_element = [&](vector<int>& x, int k) { vector<int> a, b, c; b.push_back(x.back()); ll t = loc(x.back(), m * E, lp, rp); for (x.pop_back(); !x.empty(); x.pop_back()) { ll q = get(x.back(), t); if (m * E < q) a.push_back(x.back()); else if (q < m * E) c.push_back(x.back()); else b.push_back(x.back()); } if (k < a.size()) t = kth_element(a, k); else if (a.size() + b.size() <= k) t = kth_element(c, k - a.size() - b.size()); for (int i : a) x.push_back(i); for (int i : b) x.push_back(i); for (int i : c) x.push_back(i); return t; }; mp = kth_element(v, m - l); vector<int> L, R; for (int i = 0; i < m - l; i++) L.push_back(v[i]); for (int i = m - l; i < r - l; i++) R.push_back(v[i]); solve(L, l, m, lp, mp); solve(R, m, r, mp, rp); } int main(void) { srand(clock()); scanf( %d%lld , &N, &L); E = L / N; vector<int> a; for (int i = 1; i <= N; i++) a.push_back(i); solve(a, 0, N, 0, MAX); printf( ! n ); for (int i = 1; i <= N; i++) printf( %lld %lld n , ans[i][0], ans[i][1]); fflush(stdout); return 0; } |
/*
* Character ROM for text mode fonts
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module vdu_char_rom (
input clk,
input [11:0] addr,
output reg [ 7:0] q
);
// Registers, nets and parameters
reg [7:0] rom[0:4095];
// Behaviour
always @(posedge clk) q <= rom[addr];
initial $readmemh("char_rom.dat", rom);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int inf = 1e9 + 10; const long long INF = 1e18; const long double EPS = 1e-10; const int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; const int dy[8] = {0, 1, 0, -1, 1, 1, -1, -1}; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return 1; } return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(25); int t; cin >> t; while (t--) { int n; string s; cin >> n >> s; string ans = ; int idx = 0; while (idx < n && s[idx] == 0 ) { ans += s[idx]; idx++; } s = s.substr(idx); reverse(s.begin(), s.end()); n = s.size(); string ans2 = ; idx = 0; while (idx < n && s[idx] == 1 ) { ans2 += s[idx]; idx++; } s = s.substr(idx); n = s.size(); if (n) ans += 0 ; ans += ans2; cout << ans << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_PP_V
/**
* lsbuf: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbuf (
X ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int a = 0, b = 0, r = 0; while (true) { a = (int)n / 36; r = n % 36; b = (int)r / 3; if (r % 3 == 2) b += 1; if (b >= 12) n = b * 3 + a * 36; else break; } cout << a << << b << endl; ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18 + 7; long long f[105]; long long g[105]; int main() { long long n; cin >> n; f[1] = 2, f[2] = 3; g[1] = 2, g[2] = 4; for (int h = 3; h <= 100; h++) { f[h] = f[h - 1] + f[h - 2]; g[h] = g[h - 1] + g[h - 1]; if (f[h] > n) break; g[h] = min(g[h], inf); } long long res = 0; for (int h = 1; h <= 100; h++) { if (f[h] > n) break; if (f[h] <= n && g[h] >= n) res = h; } cout << res; return 0; } |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Read #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 32,
parameter MEMADDR_WIDTH = 20
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ = 3,
ST_OUTPUT_KEY = 4;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH-1:0] in_data;
wire in_valid;
reg in_ready;
wire[31:0] hash_data;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH];
wire[MEMADDR_WIDTH-1:0] addr;
assign addr = hash_data[31:32 - MEMADDR_WIDTH] ^ hash_data[MEMADDR_WIDTH-1:0];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ;
end
end
end
ST_ISSUE_READ: begin
if (in_data[KEY_WIDTH+META_WIDTH-4]==1) begin
// ignore this and don't send read!
end else begin
rdcmd_data <= addr;
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
state <= ST_OUTPUT_KEY;
output_data <= in_data;
output_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] <= addr; //(in_data[KEY_WIDTH+META_WIDTH-1]==0) ? addr1 : addr2;
in_ready <= 1;
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
// Copyright 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.
// Written by Tim Edwards
`include "digital_pll_controller.v"
`include "ring_osc2x13.v"
module digital_pll (reset, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim);
input reset; // Sense positive reset
input extclk_sel; // External clock select (acts as 2nd reset)
input osc; // Input oscillator to match
input [4:0] div; // PLL feedback division ratio
input [2:0] sel; // Core clock select
input dco; // Run in DCO mode
input [25:0] ext_trim; // External trim for DCO mode
output clockc; // Selected core clock output
output [1:0] clockp; // Two 90 degree clock phases
output [3:0] clockd; // Divided clock (2, 4, 8, 16)
wire [25:0] itrim; // Internally generated trim bits
wire [25:0] otrim; // Trim bits applied to the ring oscillator
wire [3:0] nint; // Internal divided down clocks
wire resetb; // Internal positivie sense reset
wire creset; // Controller reset
wire ireset; // Internal reset (external reset OR extclk_sel)
assign ireset = reset | extclk_sel;
// In DCO mode: Hold controller in reset and apply external trim value
assign itrim = (dco == 1'b0) ? otrim : ext_trim;
assign creset = (dco == 1'b0) ? ireset : 1'b1;
ring_osc2x13 ringosc (
.reset(ireset),
.trim(itrim),
.clockp(clockp)
);
digital_pll_controller pll_control (
.reset(creset),
.clock(clockp[0]),
.osc(osc),
.div(div),
.trim(otrim)
);
// Select core clock output
assign clockc = (sel == 3'b000) ? clockp[0] :
(sel == 3'b001) ? clockd[0] :
(sel == 3'b010) ? clockd[1] :
(sel == 3'b011) ? clockd[2] :
clockd[3];
// Derive negative-sense reset from the input positive-sense reset
sky130_fd_sc_hd__inv_4 irb (
.A(reset),
.Y(resetb)
);
// Create divided down clocks. The inverted output only comes
// with digital standard cells with inverted resets, so the
// reset has to be inverted as well.
sky130_fd_sc_hd__dfrbp_1 idiv2 (
.CLK(clockp[1]),
.D(clockd[0]),
.Q(nint[0]),
.Q_N(clockd[0]),
.RESET_B(resetb)
);
sky130_fd_sc_hd__dfrbp_1 idiv4 (
.CLK(clockd[0]),
.D(clockd[1]),
.Q(nint[1]),
.Q_N(clockd[1]),
.RESET_B(resetb)
);
sky130_fd_sc_hd__dfrbp_1 idiv8 (
.CLK(clockd[1]),
.D(clockd[2]),
.Q(nint[2]),
.Q_N(clockd[2]),
.RESET_B(resetb)
);
sky130_fd_sc_hd__dfrbp_1 idiv16 (
.CLK(clockd[2]),
.D(clockd[3]),
.Q(nint[3]),
.Q_N(clockd[3]),
.RESET_B(resetb)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int inf = 0x3f3f3f3f, N = 1e7; using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } char s[10]; int d(char c) { return c - 0 ; } int main() { while (~scanf( %s , s)) { long long x = d(s[0]) * 10000 + d(s[2]) * 1000 + d(s[4]) * 100 + d(s[3]) * 10 + d(s[1]); long long ans = x; for (int i = 1; i < 5; i++) ans = ans * x % 100000; printf( %05d , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> v[3005]; long long f[20][3005], ans; int n, k; void solve(int l, int r, int d) { if (l == r) { for (int i = (int)(0); i <= (int)(v[l].size() - 1); i++) if (i + 1 <= k) ans = max(ans, v[l][i] + f[d][k - i - 1]); return; } int mid = (l + r) / 2; memcpy(f[d + 1], f[d], sizeof(f[d])); for (int i = (int)(mid + 1); i <= (int)(r); i++) { long long v1 = v[i].size(), v2 = v[i][v1 - 1]; for (int j = (int)(k - v1); j >= (int)(0); j--) f[d + 1][j + v1] = max(f[d + 1][j + v1], f[d + 1][j] + v2); } solve(l, mid, d + 1); memcpy(f[d + 1], f[d], sizeof(f[d])); for (int i = (int)(l); i <= (int)(mid); i++) { long long v1 = v[i].size(), v2 = v[i][v1 - 1]; for (int j = (int)(k - v1); j >= (int)(0); j--) f[d + 1][j + v1] = max(f[d + 1][j + v1], f[d + 1][j] + v2); } solve(mid + 1, r, d + 1); } int main() { scanf( %d%d , &n, &k); for (int i = (int)(1); i <= (int)(n); i++) { int t; scanf( %d , &t); v[i].resize(t); for (int j = (int)(0); j <= (int)(t - 1); j++) scanf( %lld , &v[i][j]); for (int j = (int)(1); j <= (int)(t - 1); j++) v[i][j] += v[i][j - 1]; } solve(1, n, 0); cout << ans << endl; } |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ()
* Description:
* Tranlates data from a Ping Pong FIFO to an AXI Stream
*
* Changes: Who? What?
* 04/06/2017: DFM Initial check in.
* 04/06/2017: DFM Added count so that the 'last' will not be strobed until
* all is sent.
*/
`timescale 1ps / 1ps
module adapter_ppfifo_2_axi_stream #(
parameter DATA_WIDTH = 24,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//Ping Poing FIFO Read Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
input [23:0] i_ppfifo_size,
input [(DATA_WIDTH + 1) - 1:0] i_ppfifo_data,
output o_ppfifo_stb,
//AXI Stream Output
input i_axi_clk,
output [3:0] o_axi_user,
input i_axi_ready,
output [DATA_WIDTH - 1:0] o_axi_data,
output o_axi_last,
output reg o_axi_valid,
output [31:0] o_debug
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
assign o_axi_data = i_ppfifo_data[DATA_WIDTH - 1: 0];
assign o_ppfifo_stb = (i_axi_ready & o_axi_valid);
assign o_axi_user[0] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH] : 1'b0;
assign o_axi_user[3:1] = 3'h0;
assign o_axi_last = ((r_count + 1) >= i_ppfifo_size) & o_ppfifo_act & o_axi_valid;
//synchronous logic
assign o_debug[3:0] = state;
assign o_debug[4] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH]: 1'b0;
assign o_debug[5] = o_ppfifo_act;
assign o_debug[6] = i_ppfifo_rdy;
assign o_debug[7] = (r_count > 0);
assign o_debug[8] = (i_ppfifo_size > 0);
assign o_debug[9] = (r_count == i_ppfifo_size);
assign o_debug[15:10] = 0;
assign o_debug[23:16] = r_count[7:0];
assign o_debug[31:24] = 0;
always @ (posedge i_axi_clk) begin
o_axi_valid <= 0;
if (rst) begin
state <= IDLE;
o_ppfifo_act <= 0;
r_count <= 0;
end
else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if (i_ppfifo_rdy && !o_ppfifo_act) begin
r_count <= 0;
o_ppfifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
o_axi_valid <= 1;
if (i_axi_ready && o_axi_valid) begin
r_count <= r_count + 1;
if ((r_count + 1) >= i_ppfifo_size) begin
o_axi_valid <= 0;
end
end
end
else begin
o_ppfifo_act <= 0;
state <= RELEASE;
end
end
RELEASE: begin
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
//----------------------------------------------------------------------------
//-- Memoria ROM genérica
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Memoria con los siguientes parametros:
//-- * AW: Numero de bits de las direcciones
//-- * DW: Numero de bits de los datos
//-- * ROMFILE: Fichero a usar para cargar la memoria
//--
//-- Con este componente podemos hacer memorias rom de cualquier tamaño
//----------------------------------------------------------------------------
module genrom #( //-- Parametros
parameter AW = 5, //-- Bits de las direcciones (Adress width)
parameter DW = 8) //-- Bits de los datos (Data witdh)
( //-- Puertos
input clk, //-- Señal de reloj global
input wire [AW-1: 0] addr, //-- Direcciones
output reg [DW-1: 0] data); //-- Dato de salida
//-- Parametro: Nombre del fichero con el contenido de la ROM
parameter ROMFILE = "prog.list";
//-- Calcular el numero de posiciones totales de memoria
localparam NPOS = 2 ** AW;
//-- Memoria
reg [DW-1: 0] rom [0: NPOS-1];
//-- Lectura de la memoria
always @(posedge clk) begin
data <= rom[addr];
end
//-- Cargar en la memoria el fichero ROMFILE
//-- Los valores deben estan dados en hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file xilinx_ddr2_if_cache.v when simulating
// the core, xilinx_ddr2_if_cache. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module xilinx_ddr2_if_cache(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb);
input clka;
input ena;
input [3 : 0] wea;
input [11 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input enb;
input [15 : 0] web;
input [9 : 0] addrb;
input [127 : 0] dinb;
output [127 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V3_1 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(128),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(16),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(128),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ml501_ddr2_if_cache is "black_box"
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_nlb # (
parameter P_DATA_WIDTH = 19,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input rst_n,
input wr0_en,
input [P_ADDR_WIDTH-1:0] wr0_addr,
input [P_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
input wr1_en,
input [P_ADDR_WIDTH-1:0] wr1_addr,
input [P_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
reg r_wr_en;
reg [P_ADDR_WIDTH-1:0] r_wr_addr;
reg [P_DATA_WIDTH-1:0] r_wr_data;
reg [P_ADDR_WIDTH-1:0] r_wr0_addr;
reg [P_DATA_WIDTH-1:0] r_wr0_data;
reg [P_ADDR_WIDTH-1:0] r_wr1_addr;
reg [P_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_req | r_wr0_req;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_addr <= wr0_addr;
r_wr0_data <= wr0_data;
end
if(wr1_en == 1) begin
r_wr1_addr <= wr1_addr;
r_wr1_data <= wr1_data;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1 || r_wr1_req == 1)
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
else if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: begin
r_wr_addr <= r_wr0_addr;
r_wr_data <= r_wr0_data;
end
2'b10: begin
r_wr_addr <= r_wr1_addr;
r_wr_data <= r_wr1_data;
end
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = r_wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; long long k; cin >> n; cin >> k; vector<long long> d(n); vector<long long> afterd(n); for (long long i = 0; i < n; i++) cin >> d[i]; for (long long i = 0; i < n; i++) cin >> afterd[i]; vector<pair<long long, long long> > utility(n); for (long long i = 0; i < n; i++) { utility[i].first = d[i] - afterd[i]; utility[i].second = i; } sort(utility.begin(), utility.end()); set<long long> u2; long long p = 0; while (k > 0 || utility[p].first < 0) { u2.insert(utility[p].second); p += 1; k -= 1; } long long cost = 0; for (long long i = 0; i < n; i++) { if (u2.find(i) != u2.end()) cost += d[i]; else cost += afterd[i]; } cout << cost; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; } |
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: D5M CCD_Capture
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module CCD_Capture(
iDATA,
iFVAL,
iLVAL,
iSTART,
iEND,
iCLK,
iRST,
oDATA,
oDVAL,
oX_Cont,
oY_Cont,
oFrame_Cont,
oADDRESS,
oLVAL
);
input [11:0] iDATA;
input iFVAL;
input iLVAL;
input iSTART;
input iEND;
input iCLK;
input iRST;
output [11:0] oDATA;
output [15:0] oX_Cont;
output [15:0] oY_Cont;
output [31:0] oFrame_Cont;
output [23:0] oADDRESS;
output oDVAL;
output oLVAL;
reg temp_oLVAL;
reg Pre_FVAL;
reg mCCD_FVAL;
reg mCCD_LVAL;
reg [11:0] mCCD_DATA;
reg [15:0] X_Cont;
reg [15:0] Y_Cont;
reg [31:0] Frame_Cont;
reg [23:0] regADDRESS;
reg mSTART;
parameter COLUMN_WIDTH = 1280;
assign oX_Cont = X_Cont;
assign oY_Cont = Y_Cont;
assign oFrame_Cont = Frame_Cont;
assign oDATA = mCCD_DATA;
assign oDVAL = mCCD_FVAL&mCCD_LVAL;
assign oADDRESS = regADDRESS;
assign oLVAL = temp_oLVAL;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mSTART <= 0;
else
begin
if(iSTART)
mSTART <= 1;
if(iEND)
mSTART <= 0;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Pre_FVAL <= 0;
mCCD_FVAL <= 0;
mCCD_LVAL <= 0;
X_Cont <= 0;
Y_Cont <= 0;
end
else
begin
Pre_FVAL <= iFVAL;
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
mCCD_FVAL <= 1;
else if({Pre_FVAL,iFVAL}==2'b10)
mCCD_FVAL <= 0;
mCCD_LVAL <= iLVAL;
if(mCCD_FVAL)
begin
if(mCCD_LVAL)
begin
if(X_Cont<(COLUMN_WIDTH-1))
X_Cont <= X_Cont+1;
else
begin
X_Cont <= 0;
Y_Cont <= Y_Cont+1;
end
if(X_Cont>=320 && X_Cont<960 && Y_Cont>=120 && Y_Cont<600)
begin
temp_oLVAL <=1'b1;
regADDRESS <=regADDRESS+1;
end
else
temp_oLVAL <=1'b0;
end
end
else
begin
X_Cont <= 0;
Y_Cont <= 0;
regADDRESS<=0;
end
end
end
//always@(posedge iCLK or negedge iRST)
//begin
// if(!iRST)
// regADDRESS <= 0;
// else
// begin
// if((X_Cont<640) && (Y_Cont<480))
// regADDRESS <= regADDRESS+1;
// else if(Y_Cont==481)
// begin
// regADDRESS <= 0;
// end;
// end
//end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
Frame_Cont <= 0;
else
begin
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
Frame_Cont <= Frame_Cont+1;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mCCD_DATA <= 0;
else if (iLVAL)
mCCD_DATA <= iDATA;
else
mCCD_DATA <= 0;
end
reg ifval_dealy;
wire ifval_fedge;
reg [15:0] y_cnt_d;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
y_cnt_d <= 0;
else
y_cnt_d <= Y_Cont;
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
ifval_dealy <= 0;
else
ifval_dealy <= iFVAL;
end
assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;
endmodule |
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 11:41:13 05/10/2011
// Description: log image to ppm file
//-----------------------------------------------
module hdmi_out
(
input hdmi_clk,
input hdmi_vs,
input hdmi_de,
input [31:0] hdmi_data
);
//-----------------------------------------------
integer fm1=0;
reg [7:0]vsc=8'h0;
reg vse=1;
//-----------------------------------------------
initial
begin
//fm1 = $fopen("outA.ppm","wb");
end
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
vse<=hdmi_vs;
if((hdmi_vs==1'b0)&&(vse==1'b1))
begin
$fclose(fm1);
//$stop;
end
if((hdmi_vs==1'b1)&&(vse==1'b0))
begin
fm1 = $fopen({"out/out_",vsc[5:0]/10+8'h30,vsc[5:0]%10+8'h30,".ppm"},"wb");
$display("out/out%d.ppm saved",vsc);
$fwrite(fm1,"P6%c64 64%c255\n",10,10);
vsc<=vsc+1;
end else
begin
if(hdmi_de)
begin
//just for good debugging
$fwrite(fm1,"%c",{hdmi_data[23:16]});
$fwrite(fm1,"%c",{hdmi_data[15:8]});
$fwrite(fm1,"%c",{hdmi_data[7:0]});
end
end
end
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using ld = long double; template <typename Arg1> void debug_out(const char* name, Arg1&& arg1) { cerr << name << = << arg1 << ] << n ; } template <typename Arg1, typename... Args> void debug_out(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << = << arg1 << , ; debug_out(comma + 1, args...); } const long long mod = 1e9 + 7; const long long N = 5e3 + 5, M = 2e5 + 5; long long n; long long v[N]; long long solve(long long l, long long r) { if (r < l) return 0; long long res = r - l + 1; long long mn = *min_element(v + l, v + r + 1); for (long long i = (l); i <= (r); ++i) v[i] -= mn; long long ans = mn; for (long long i = (l); i <= (r); ++i) { if (v[i] == 0) { ans += solve(l, i - 1); l = i + 1; } } ans += solve(l, r); res = min(res, ans); return res; } void Solve_main() { cin >> n; for (long long i = (1); i <= (n); ++i) cin >> v[i]; cout << solve(1, n) << n ; } int32_t main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); long long tc = 1; for (long long i = 1; i <= tc; i++) { Solve_main(); } cerr << [time: << 1.0 * clock() / CLOCKS_PER_SEC << s] ; return 0; } |
module ptr(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* Console panel */
input wire key_start,
input wire key_stop,
input wire key_tape_feed,
output wire [35:0] ptr_ind,
output wire [6:0] status_ind, // also includes motor on
/* Avalon slave */
input wire s_write,
input wire [31:0] s_writedata,
output wire fe_data_rq
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
assign ptr_ind = ptr;
assign status_ind = { motor_on, ptr_b, ptr_busy, ptr_flag, ptr_pia };
wire ptr_sel = iobus_ios == 7'b001_000_1;
wire [8:1] stb_hole = ptr_b ? { 2'b0, hole[6:1] } : hole[8:1];
wire ptr_data_clr;
wire ptr_data_set;
wire ptr_ic_clr;
wire ptr_ic_set;
wire iob_reset;
wire ptr_datai = ptr_sel & iobus_iob_fm_datai;
wire ptr_status = ptr_sel & iobus_iob_fm_status;
wire ptr_start_clr, ptr_stop_clr;
wire ptr_busy_set;
pa ptr_pa0(clk, reset, ptr_sel & iobus_datao_clear, ptr_data_clr);
pa ptr_pa1(clk, reset, ptr_sel & iobus_datao_set, ptr_data_set);
pa ptr_pa2(clk, reset, ptr_sel & iobus_cono_clear | iob_reset, ptr_ic_clr);
pa ptr_pa3(clk, reset, ptr_sel & iobus_cono_set, ptr_ic_set);
pa ptr_pa4(clk, reset, iobus_iob_reset, iob_reset);
pg ptr_pg0(clk, reset, motor_on, ptr_start_clr);
pg ptr_pg1(clk, reset, ~motor_on, ptr_stop_clr);
pa ptr_pa5(clk, reset, ~ptr_datai, ptr_busy_set); // CDG actually
wire ptr_clr;
pa ptr_pa6(clk, reset, ptr_busy, ptr_clr);
reg [36:31] ptr_sr; // actually 36,30,24,18,12,6
reg [35:0] ptr;
reg motor_on = 0;
wire ptr_lead;
wire ptr_mid; // mid hole, this is where the strobe happens.
// normally 400μs after leading edge of feed hole
wire ptr_strobe = ptr_mid & (~ptr_b | hole[8]);
wire ptr_trail;
assign iobus_iob_out =
ptr_datai ? ptr :
ptr_status ? { 27'b0, motor_on, 2'b0, ptr_b, ptr_busy, ptr_flag, ptr_pia } :
36'b0;
wire [1:7] ptr_req = { ptr_flag, 7'b0 } >> ptr_pia;
assign iobus_pi_req = ptr_req;
reg [33:35] ptr_pia;
reg ptr_busy;
reg ptr_flag;
reg ptr_b;
`ifdef simulation
initial begin
ptr_busy <= 0;
ptr_flag <= 0;
ptr_b <= 0;
end
`endif
always @(posedge clk) begin
if(ptr_ic_clr) begin
ptr_pia <= 0;
ptr_busy <= 0;
ptr_flag <= 0;
ptr_b <= 0;
end
if(ptr_ic_set) begin
ptr_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[32])
ptr_flag <= 1;
if(iobus_iob_in[31])
ptr_busy <= 1;
if(iobus_iob_in[30])
ptr_b <= 1;
end
if(ptr_busy_set)
ptr_busy <= 1;
if(ptr_start_clr)
ptr_busy <= 0;
if(ptr_start_clr | ptr_stop_clr)
ptr_flag <= 1;
if(ptr_datai)
ptr_flag <= 0;
if(ptr_trail & ptr_busy & (~ptr_b | ptr_sr[36])) begin
ptr_busy <= 0;
ptr_flag <= 1;
end
if(ptr_clr) begin
ptr <= 0;
ptr_sr <= 0;
end
if(ptr_strobe) begin
ptr_sr <= { ptr_sr[35:31], 1'b1 };
ptr <= { ptr[29:0], 6'b0 } | stb_hole;
end
if(key_start)
motor_on <= 1;
if(key_stop | reset)
motor_on <= 0;
end
// front end interface
assign fe_data_rq = fe_req;
wire moving = motor_on & (key_tape_feed | ptr_busy);
reg fe_req; // requesting data from FE
reg fe_rs; // FE responded with data
reg [8:1] hole; // FE data
reg mid_sync; // set when mid hole
reg trail_sync; // set when trailing edge of feed hole would happen
wire start_signal = ~moving | ptr_trail;
wire start_pulse;
dly50ns fe_dly3(clk, reset, start_signal, start_pulse);
wire fe_mid_pulse, fe_trail_pulse;
`ifdef simulation
dly200ns fe_dly0(clk, reset, start_signal, ptr_lead);
dly800ns fe_dly1(clk, reset, start_signal, fe_mid_pulse);
dly1us fe_dly2(clk, reset, start_signal, fe_trail_pulse);
`else
dly1us fe_dly0(clk, reset, start_signal, ptr_lead);
dly2_1ms fe_dly1(clk, reset, start_signal, fe_mid_pulse);
dly2_5ms fe_dly2(clk, reset, start_signal, fe_trail_pulse);
`endif
pa fe_pa0(clk, reset, fe_rs & mid_sync & ptr_busy, ptr_mid);
pa fe_pa1(clk, reset, fe_rs & trail_sync, ptr_trail);
always @(posedge clk) begin
if(~moving | start_pulse) begin
fe_req <= 0;
fe_rs <= 0;
hole <= 0;
mid_sync <= 0;
trail_sync <= 0;
end
// start FE request
if(ptr_lead)
fe_req <= 1;
// got response from FE
if(s_write & fe_req) begin
hole <= s_writedata[7:0];
fe_req <= 0;
fe_rs <= 1;
end
if(fe_mid_pulse)
mid_sync <= 1;
if(fe_trail_pulse)
trail_sync <= 1;
// all done
if(ptr_trail)
fe_rs <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 75005; const long long maxm = (1 << 15) + 5; long long k, n[16], s[16], a[16][5005], co[maxn], col[maxn], idx, b[maxn], yhp[16], num; long long st[maxn], cnt[16], vis[maxm], lst[maxm], from[maxm], sel[maxn]; long long head[maxn], ecnt, d[maxn]; struct edge { long long to, next; } e[maxn << 1]; map<long long, long long> id, ans; long long sum[maxn]; vector<long long> to, nxt; void adde(long long u, long long v) { e[++ecnt].to = v; d[v]++; e[ecnt].next = head[u]; head[u] = ecnt; } long long read() { long long res = 0, f = 1; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (!isdigit(ch)); do { res = res * 10 + ch - 0 ; ch = getchar(); } while (isdigit(ch)); return res * f; } void topsort() { queue<long long> q; for (long long i = (1); i <= (s[k]); ++i) if (!d[i]) q.push(i); while (!q.empty()) { long long u = q.front(); q.pop(); for (long long i = head[u]; i; i = e[i].next) { long long v = e[i].to; d[v]--; if (!d[v]) q.push(v); } } } void dfs(long long u) { col[u] = idx; st[idx] |= (1 << (yhp[co[u]] - 1)); cnt[yhp[co[u]]]++; for (long long i = head[u]; i; i = e[i].next) { long long v = e[i].to; if (!d[v] || col[v]) continue; dfs(v); } } signed main() { k = read(); for (long long i = (1); i <= (k); ++i) { n[i] = read(); s[i] = s[i - 1] + n[i]; for (long long j = (1); j <= (n[i]); ++j) a[i][j] = read(), id[a[i][j]] = s[i - 1] + j, co[id[a[i][j]]] = i, b[id[a[i][j]]] = a[i][j], sum[i] += a[i][j]; sum[0] += sum[i]; } if (sum[0] % k != 0) { puts( No ); return 0; } sum[0] /= k; for (long long i = (1); i <= (k); ++i) if (sum[i] == sum[0]) yhp[i] = yhp[i - 1]; else yhp[i] = ++num; for (long long i = (1); i <= (k); ++i) for (long long j = (1); j <= (n[i]); ++j) { if (sum[i] == sum[0]) continue; long long x = (sum[0] - (sum[i] - a[i][j])); if (id[x] == 0 || (co[id[a[i][j]]] == co[id[x]] && id[a[i][j]] != id[x])) continue; adde(id[a[i][j]], id[x]); } topsort(); for (long long i = (1); i <= (s[k]); ++i) { if (d[i] && !col[i]) { ++idx; memset(cnt, 0, sizeof(cnt)); dfs(i); for (long long j = (1); j <= (k); ++j) if (cnt[j] > 1) st[idx] = 0; } } vis[0] = 1; to.push_back(0); long long S = (1 << num) - 1; for (long long i = (1); i <= (idx); ++i) { if (!st[i]) continue; nxt.clear(); for (long long x : to) { if (x & st[i]) continue; if (vis[x | st[i]]) continue; vis[x | st[i]] = 1; lst[x | st[i]] = x; from[x | st[i]] = i; nxt.push_back(x | st[i]); } for (long long x : nxt) to.push_back(x); } if (!vis[S]) { puts( No ); return 0; } puts( Yes ); long long tmp = S; while (tmp) sel[from[tmp]] = 1, tmp = lst[tmp]; for (long long u = (1); u <= (s[k]); ++u) if (sel[col[u]]) for (long long i = head[u]; i; i = e[i].next) { long long v = e[i].to; if (d[v]) ans[b[v]] = co[u]; } for (long long i = (1); i <= (k); ++i) { if (sum[i] == sum[0]) printf( %lld %lld n , a[i][1], i); else for (long long j = (1); j <= (n[i]); ++j) if (ans[a[i][j]]) printf( %lld %lld n , a[i][j], ans[a[i][j]]); } } |
// MBT 10-26-14
//
//
// Counts the number of set bits in a thermometer code.
// A thermometer code is of the form 0*1*.
//
`include "bsg_defines.v"
module bsg_thermometer_count #(parameter `BSG_INV_PARAM(width_p ))
(input [width_p-1:0] i
// we need to represent width_p+1 values (0..width_p), so
// we need the +1.
, output [$clog2(width_p+1)-1:0] o
);
// parallel prefix is a bit slow for these cases
if (width_p == 1)
assign o = i;
else
if (width_p == 2)
assign o = { i[1], i[0] & ~ i[1] };
else
// 000 0 0
// 001 0 1
// 011 1 0
// 111 1 1
if (width_p == 3)
assign o = { i[1], i[2] | (i[0] & ~i[1]) };
else
// 3210
// 0000 0 0 0
// 0001 0 0 1
// 0011 0 1 0
// 0111 0 1 1
// 1111 1 0 0
if (width_p == 4)
// assign o = {i[3], ~i[3] & i[1], (~i[3] & i[0]) & ~(i[2]^i[1]) };
// DC likes the xor's
assign o = {i[3], ~i[3] & i[1], ^i };
else
// this converts from a thermometer code (01111)
// to a one hot code (10000)
// basically by edge-detecting it.
//
// the important parts are the corner cases:
// 0000 --> ~(0_0000) & (0000_1) --> 0000_1 (0)
// 1111 --> ~(0_1111) & (1111_0) --> 1_0000 (4)
//
begin : big
wire [width_p:0] one_hot = ( ~{ 1'b0, i } )
& ( { i , 1'b1 } );
bsg_encode_one_hot #(.width_p(width_p+1)) encode_one_hot
(.i(one_hot)
,.addr_o(o)
,.v_o()
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_thermometer_count)
|
// audio data processing
// stereo sigma/delta bitstream modulator
module paula_audio_sigmadelta
(
input clk, //bus clock
input clk7_en,
input [14:0] ldatasum, // left channel data
input [14:0] rdatasum, // right channel data
output reg left=0, //left bitstream output
output reg right=0 //right bitsteam output
);
// local signals
localparam DW = 15;
localparam CW = 2;
localparam RW = 4;
localparam A1W = 2;
localparam A2W = 5;
wire [DW+2+0 -1:0] sd_l_er0, sd_r_er0;
reg [DW+2+0 -1:0] sd_l_er0_prev=0, sd_r_er0_prev=0;
wire [DW+A1W+2-1:0] sd_l_aca1, sd_r_aca1;
wire [DW+A2W+2-1:0] sd_l_aca2, sd_r_aca2;
reg [DW+A1W+2-1:0] sd_l_ac1=0, sd_r_ac1=0;
reg [DW+A2W+2-1:0] sd_l_ac2=0, sd_r_ac2=0;
wire [DW+A2W+3-1:0] sd_l_quant, sd_r_quant;
// LPF noise LFSR
reg [24-1:0] seed1 = 24'h654321;
reg [19-1:0] seed2 = 19'h12345;
reg [24-1:0] seed_sum=0, seed_prev=0, seed_out=0;
always @ (posedge clk) begin
if (clk7_en) begin
if (&seed1)
seed1 <= #1 24'h654321;
else
seed1 <= #1 {seed1[22:0], ~(seed1[23] ^ seed1[22] ^ seed1[21] ^ seed1[16])};
end
end
always @ (posedge clk) begin
if (clk7_en) begin
if (&seed2)
seed2 <= #1 19'h12345;
else
seed2 <= #1 {seed2[17:0], ~(seed2[18] ^ seed2[17] ^ seed2[16] ^ seed2[13] ^ seed2[0])};
end
end
always @ (posedge clk) begin
if (clk7_en) begin
seed_sum <= #1 seed1 + {5'b0, seed2};
seed_prev <= #1 seed_sum;
seed_out <= #1 seed_sum - seed_prev;
end
end
// linear interpolate
localparam ID=4; // counter size, also 2^ID = interpolation rate
reg [ID+0-1:0] int_cnt = 0;
always @ (posedge clk) begin
if (clk7_en) begin
int_cnt <= #1 int_cnt + 'd1;
end
end
reg [DW+0-1:0] ldata_cur=0, ldata_prev=0;
reg [DW+0-1:0] rdata_cur=0, rdata_prev=0;
wire [DW+1-1:0] ldata_step, rdata_step;
reg [DW+ID-1:0] ldata_int=0, rdata_int=0;
wire [DW+0-1:0] ldata_int_out, rdata_int_out;
assign ldata_step = {ldata_cur[DW-1], ldata_cur} - {ldata_prev[DW-1], ldata_prev}; // signed subtract
assign rdata_step = {rdata_cur[DW-1], rdata_cur} - {rdata_prev[DW-1], rdata_prev}; // signed subtract
always @ (posedge clk) begin
if (clk7_en) begin
if (~|int_cnt) begin
ldata_prev <= #1 ldata_cur;
ldata_cur <= #1 ldatasum; //{~ldatasum[DW-1], ldatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
rdata_prev <= #1 rdata_cur;
rdata_cur <= #1 rdatasum; //{~rdatasum[DW-1], rdatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
ldata_int <= #1 {ldata_cur[DW-1], ldata_cur, {ID{1'b0}}};
rdata_int <= #1 {rdata_cur[DW-1], rdata_cur, {ID{1'b0}}};
end else begin
ldata_int <= #1 ldata_int + {{ID{ldata_step[DW+1-1]}}, ldata_step};
rdata_int <= #1 rdata_int + {{ID{rdata_step[DW+1-1]}}, rdata_step};
end
end
end
assign ldata_int_out = ldata_int[DW+ID-1:ID];
assign rdata_int_out = rdata_int[DW+ID-1:ID];
// input gain x3
wire [DW+2-1:0] ldata_gain, rdata_gain;
assign ldata_gain = {ldata_int_out[DW-1], ldata_int_out, 1'b0} + {{(2){ldata_int_out[DW-1]}}, ldata_int_out};
assign rdata_gain = {rdata_int_out[DW-1], rdata_int_out, 1'b0} + {{(2){rdata_int_out[DW-1]}}, rdata_int_out};
/*
// random dither to 15 bits
reg [DW-1:0] ldata=0, rdata=0;
always @ (posedge clk) begin
if (clk7_en) begin
ldata <= #1 ldata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
rdata <= #1 rdata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
end
end
*/
// accumulator adders
assign sd_l_aca1 = {{(A1W){ldata_gain[DW+2-1]}}, ldata_gain} - {{(A1W){sd_l_er0[DW+2-1]}}, sd_l_er0} + sd_l_ac1;
assign sd_r_aca1 = {{(A1W){rdata_gain[DW+2-1]}}, rdata_gain} - {{(A1W){sd_r_er0[DW+2-1]}}, sd_r_er0} + sd_r_ac1;
assign sd_l_aca2 = {{(A2W-A1W){sd_l_aca1[DW+A1W+2-1]}}, sd_l_aca1} - {{(A2W){sd_l_er0[DW+2-1]}}, sd_l_er0} - {{(A2W+1){sd_l_er0_prev[DW+2-1]}}, sd_l_er0_prev[DW+2-1:1]} + sd_l_ac2;
assign sd_r_aca2 = {{(A2W-A1W){sd_r_aca1[DW+A1W+2-1]}}, sd_r_aca1} - {{(A2W){sd_r_er0[DW+2-1]}}, sd_r_er0} - {{(A2W+1){sd_r_er0_prev[DW+2-1]}}, sd_r_er0_prev[DW+2-1:1]} + sd_r_ac2;
// accumulators
always @ (posedge clk) begin
if (clk7_en) begin
sd_l_ac1 <= #1 sd_l_aca1;
sd_r_ac1 <= #1 sd_r_aca1;
sd_l_ac2 <= #1 sd_l_aca2;
sd_r_ac2 <= #1 sd_r_aca2;
end
end
// value for quantizaton
assign sd_l_quant = {sd_l_ac2[DW+A2W+2-1], sd_l_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
assign sd_r_quant = {sd_r_ac2[DW+A2W+2-1], sd_r_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
// error feedback
assign sd_l_er0 = sd_l_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
assign sd_r_er0 = sd_r_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
always @ (posedge clk) begin
if (clk7_en) begin
sd_l_er0_prev <= #1 (&sd_l_er0) ? sd_l_er0 : sd_l_er0+1;
sd_r_er0_prev <= #1 (&sd_r_er0) ? sd_r_er0 : sd_r_er0+1;
end
end
// output
always @ (posedge clk) begin
if (clk7_en) begin
left <= #1 (~|ldata_gain) ? ~left : ~sd_l_er0[DW+2-1];
right <= #1 (~|rdata_gain) ? ~right : ~sd_r_er0[DW+2-1];
end
end
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Top-level implementation module for DuinoCube interfaced with AVR-style bus.
`define RGB_COLOR_DEPTH 18
`define AVR_MPU_ADDR_WIDTH 16
`define AVR_MPU_DATA_WIDTH 8
`define AVR_MPU_AD_BUS_WIDTH `AVR_MPU_DATA_WIDTH
`define AVR_MPU_AH_BUS_WIDTH (`AVR_MPU_ADDR_WIDTH - `AVR_MPU_AD_BUS_WIDTH)
`define AVR_MPU_MAPPING_ADDR 'h8000
`define VRAM_ADDR_WIDTH 18
`define VRAM_DATA_WIDTH 16
`define MPU_ADDR_WIDTH 16
`define MPU_DATA_WIDTH 16
module MainAVR(clk, _reset,
_mpu_rd, _mpu_wr, mpu_ale, mpu_ah, mpu_ad,
_vram_en, _vram_rd, _vram_wr, _vram_be, vram_addr, vram_data,
vsync, hsync, rgb);
input clk;
input _reset;
// To AVR-style memory interface.
// TODO: support other interfaces.
input _mpu_rd; // Read enable (active low)
input _mpu_wr; // Write enable (active low)
input mpu_ale; // Address latch enable
input [`AVR_MPU_AH_BUS_WIDTH-1:0] mpu_ah; // Upper address bus
inout [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_ad; // Multiplexed lower A/D bus
// To VRAM.
output _vram_en; // Enable access (active low)
output _vram_rd; // Read enable (active low)
output _vram_wr; // Write enable (active low)
output [1:0] _vram_be; // Byte enable (active low)
output [`VRAM_ADDR_WIDTH-1:0] vram_addr; // Address bus
inout [`VRAM_DATA_WIDTH-1:0] vram_data; // Data bus
// To VGA connector.
output vsync;
output hsync;
output [`RGB_COLOR_DEPTH-1:0] rgb;
//////////////////////////////////////////////////////////////////////
// Internal MPU bus conversion.
// Convert a multiplexed 8-bit data bus to a full 16-bit data bus.
// - Latch lower address bits.
// - Shift address bits down by 1.
// - Determine byte enable.
//////////////////////////////////////////////////////////////////////
wire [`AVR_MPU_ADDR_WIDTH-1:0] cc_addr;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_in;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_out;
// Latch lower address bits.
wire [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_al;
CC_DLatch #(`AVR_MPU_AD_BUS_WIDTH)
address_latch(.en(mpu_ale),
.d(mpu_ad),
.q(mpu_al));
// Shift the address bits down by 1 to convert to a 16-bit bus address.
assign cc_addr = {1'b0, mpu_ah, mpu_al[`AVR_MPU_AD_BUS_WIDTH-1:1]};
// Handle bidirectional data port.
assign mpu_ad = (~_mpu_rd & _mpu_wr & ~mpu_ale) ? mpu_data_out
: {`AVR_MPU_DATA_WIDTH{1'bz}};
// Distribute the incoming 8-bit data to both bytes of the 16-bit data port.
wire [`MPU_DATA_WIDTH-1:0] cc_data_in;
wire [`MPU_DATA_WIDTH-1:0] cc_data_out;
assign cc_data_in = {mpu_ad, mpu_ad};
// Convert an outgoing 16-bit data bus to an 8-bit data bus by selecting the
// high or low byte.
assign mpu_data_out =
mpu_al[0] ? cc_data_out[`MPU_DATA_WIDTH-1:`AVR_MPU_DATA_WIDTH]
: cc_data_out[`AVR_MPU_DATA_WIDTH-1:0];
// Determine byte enable based on whether the incoming address is odd or even.
wire [1:0] _mpu_be = mpu_al[0] ? 2'b01 : 2'b10;
// Bus enable is just if either read or write is enabled.
wire _mpu_en = ~(~_mpu_rd ^ ~_mpu_wr);
/////////////////////////////////////////////////
// VRAM interface
/////////////////////////////////////////////////
wire vram_en; // All control signals are internally active high.
wire vram_rd;
wire vram_wr;
wire [1:0] vram_be;
assign _vram_en = ~vram_en;
assign _vram_rd = ~vram_rd;
assign _vram_wr = ~vram_wr;
assign _vram_be = ~vram_be;
// Set up VRAM bidirectional I/Os.
wire [`VRAM_DATA_WIDTH-1:0] vram_data_in;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out;
// Output to VRAM active only during write.
assign vram_data = (vram_en & vram_wr) ? vram_data_out
: {`VRAM_DATA_WIDTH {1'bz}};
assign vram_data_in = vram_data;
Core core(.clk(clk),
.reset(~_reset),
.mpu_rd(~_mpu_rd),
.mpu_wr(~_mpu_wr),
.mpu_en(~_mpu_en),
.mpu_be(~_mpu_be),
.mpu_addr_in(cc_addr),
.mpu_data_in(cc_data_in),
.mpu_data_out(cc_data_out),
.vram_en(vram_en),
.vram_rd(vram_rd),
.vram_wr(vram_wr),
.vram_be(vram_be),
.vram_addr(vram_addr),
.vram_data_in(vram_data_in),
.vram_data_out(vram_data_out),
.vga_vsync(vsync),
.vga_hsync(hsync),
.vga_rgb(rgb)
);
endmodule
|
#include <bits/stdc++.h> int a[200001]; int main() { int n, i, ans = 0; scanf( %d , &n); for (i = 0; i < n; i++) { int x; scanf( %d , &x); if (a[100000 + x] == 0 && x != 0) { ans++; a[100000 + x] = 1; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string s, t; cin >> n >> s >> t; vector<int> a(n + 1); for (int i = 0; i < n; ++i) a[i] = (s[n - i - 1] - a ) + (t[n - i - 1] - a ); for (int i = 0; i < n; ++i) { if (a[i] >= 26) { ++a[i + 1]; a[i] -= 26; } } vector<int> b(n + 1); b[0] = a[0] / 2; for (int i = 1; i <= n; ++i) { b[i] = a[i] / 2; if (a[i] & 1) b[i - 1] += 13; } for (int i = n - 1; i >= 0; --i) cout << char( a + b[i]); } |
/* Module: vga640x480
Description: Generates VGA signals for 640x480 resolution
using a 25 MHz pixel clock. Once Vertical and
Horizontal sync signals are in between front
and back porch, VIDON is enabled
to display data. */
module vga640x480(
CLK,
CLR,
HSYNC,
VSYNC,
HC,
VC,
VIDON
);
// |--------------------|
// | Port Declarations |
// | -------------------|
input CLK; // Clock
input CLR; // Clear
output HSYNC; // Horizontal Sync
output VSYNC; // Vertical Sync
output [9:0] HC; // Horizontal Counter
output [9:0] VC; // Vertical Counter
output VIDON; // When active, data may be displayed
// |------------------------|
// | Parameters (Constants) |
// | -----------------------|
localparam hpixels = 800 /*10'b1100100000*/, // Pixels in horizontal line = 800
vlines = 521 /*10'b1000001001*/, // Horizontal lines = 521
hbp = 144 /*10'b0010010000*/, // Horizontal Back Porch = 144 (128+16)
hfp = 784 /*10'b1100010000*/, // Horizontal Front Porch = 784 (128+16+640)
vbp = 31 /*10'b0000011111*/, // Vertical Back Porch = 31 (2+29)
vfp = 511 /*10'b0111111111*/; // Vertical Front Porch = 511 (2+29+480)
reg [9:0] HCS, VCS; // Horizontal and Vertical counters
reg VSenable; // Enable for Vertical counter
assign HC = HCS;
assign VC = VCS;
assign HSYNC = (HCS < 128) ? 1'b0 : 1'b1; // HS Pulse is low for HCS from 0-127
assign VSYNC = (VCS < 2) ? 1'b0 : 1'b1; // VS Pulse is low for VCS from 0-1
assign VIDON = (((HCS < hfp) && (HCS >= hbp)) && ((VCS < vfp) && (VCS >= vbp))) ? 1'b1 : 1'b0;
// Counter for the horizontal sync signal
always @ (posedge CLK)
begin
if(CLR == 1'b1)
HCS <= 10'b0000000000;
else if(CLK == 1'b1)
begin
if(HCS < (hpixels - 1'b1) )
begin
HCS <= HCS + 1'b1;
VSenable <= 1'b0; // Leave VSenable off
end
else
begin
// Counter reached end of the pixel count
HCS <= 10'b0000000000; // Reset counter, then,
VSenable <= 1'b1; // Enable vertical counter
end
end
end
// Counter for the vertical sync signal
always @ (posedge CLK)
begin
if(CLR == 1'b1)
VCS <= 10'b0000000000;
else if(CLK == 1'b1 && VSenable == 1'b1)
begin
// Increment when enabled
if( VCS < (vlines - 1'b1) )
begin
VCS <= VCS + 1'b1; // Increment vertical counter
end
else
begin
VCS <= 10'b0000000000;
end
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, m, k, dp[2020][2020]; long long int getDp(long long int x, long long int y) { if (x == n) return y == k; if (~dp[x][y]) return dp[x][y]; long long int &ret = dp[x][y] = 0; ret = getDp(x + 1, y); ret = (ret + (getDp(x + 1, y + 1) * (m - 1)) % 998244353); ret %= 998244353; return ret; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; memset(dp, -1, sizeof(dp)); cout << ((getDp(1, 0) * m) % 998244353) << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int arr[100][100] = {0}; int n, x; cin >> n >> x; for (int i = 0; i < n; i++) { arr[i][i] = x; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cout << arr[i][j] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long solve(long long a, long long b, long long c) { long long a1 = a - c; a1 *= a1; long long b1 = c - b; b1 *= b1; long long c1 = b - a; c1 *= c1; return a1 + b1 + c1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; t = 1; cin >> t; while (t--) { long long a, b, c; cin >> a >> b >> c; vector<long long> arr(a, 0), arr1(b, 0), arr2(c, 0); for (int i = 0; i < a; i++) { cin >> arr[i]; } for (int i = 0; i < b; i++) { cin >> arr1[i]; } for (int i = 0; i < c; i++) { cin >> arr2[i]; } sort((arr).begin(), (arr).end()); sort((arr1).begin(), (arr1).end()); sort((arr2).begin(), (arr2).end()); long long ans = 4 * (1e18); vector<long long>::iterator it; it = unique((arr).begin(), (arr).end()); arr.resize(distance(arr.begin(), it)); it = unique((arr1).begin(), (arr1).end()); arr1.resize(distance(arr1.begin(), it)); it = unique((arr2).begin(), (arr2).end()); arr2.resize(distance(arr2.begin(), it)); a = arr.size(); b = arr1.size(); c = arr2.size(); for (int i = 0; i < a; i++) { long long in = lower_bound((arr1).begin(), (arr1).end(), arr[i]) - arr1.begin(); vector<long long> a1; vector<long long> b1; if (in == b) { a1.push_back(arr1[in - 1]); } else { a1.push_back(arr1[in]); if (in < b - 1) { a1.push_back(arr1[in + 1]); } if (in > 0) { a1.push_back(arr1[in - 1]); } } in = lower_bound((arr2).begin(), (arr2).end(), arr[i]) - arr2.begin(); if (in == c) { b1.push_back(arr2[in - 1]); } else { b1.push_back(arr2[in]); if (in < c - 1) { b1.push_back(arr2[in + 1]); } if (in > 0) { b1.push_back(arr2[in - 1]); } } for (int j = 0; j < a1.size(); j++) { for (int l = 0; l < b1.size(); l++) { long long k = solve(arr[i], a1[j], b1[l]); ans = min(k, ans); } } } for (int i = 0; i < b; i++) { long long in = lower_bound((arr).begin(), (arr).end(), arr1[i]) - arr.begin(); vector<long long> a1; vector<long long> b1; if (in == a) { a1.push_back(arr[in - 1]); } else { a1.push_back(arr[in]); if (in < a - 1) { a1.push_back(arr[in + 1]); } if (in > 0) { a1.push_back(arr[in - 1]); } } in = lower_bound((arr2).begin(), (arr2).end(), arr1[i]) - arr2.begin(); if (in == c) { b1.push_back(arr2[in - 1]); } else { b1.push_back(arr2[in]); if (in < c - 1) { b1.push_back(arr2[in + 1]); } if (in > 0) { b1.push_back(arr2[in - 1]); } } for (int j = 0; j < a1.size(); j++) { for (int l = 0; l < b1.size(); l++) { long long k = solve(arr1[i], a1[j], b1[l]); ans = min(k, ans); } } } for (int i = 0; i < c; i++) { long long in = lower_bound((arr1).begin(), (arr1).end(), arr2[i]) - arr1.begin(); vector<long long> a1; vector<long long> b1; if (in == b) { a1.push_back(arr1[in - 1]); } else { a1.push_back(arr1[in]); if (in < b - 1) { a1.push_back(arr1[in + 1]); } if (in > 0) { a1.push_back(arr1[in - 1]); } } in = lower_bound((arr).begin(), (arr).end(), arr2[i]) - arr.begin(); if (in == a) { b1.push_back(arr[in - 1]); } else { b1.push_back(arr[in]); if (in < a - 1) { b1.push_back(arr[in + 1]); } if (in > 0) { b1.push_back(arr[in - 1]); } } for (int j = 0; j < a1.size(); j++) { for (int l = 0; l < b1.size(); l++) { long long k = solve(arr2[i], a1[j], b1[l]); ans = min(k, ans); } } } cout << ans << n ; } return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Generate_Position_And_Voltage_Ramp.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Generate_Position_And_Voltage_Ramp
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Generate_Position_And_Voltage_Ramp
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
target_velocity,
param_open_loop_bias,
param_open_loop_scalar,
Q_Voltage,
Position
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] target_velocity; // sfix18_En8
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [17:0] Q_Voltage; // sfix18_En12
output signed [17:0] Position; // sfix18_En14
wire signed [31:0] rotor_velocity; // sfix32_En22
wire signed [17:0] volts_dt; // sfix18_En12
wire signed [17:0] electrical_velocity; // sfix18_En6
wire signed [17:0] electrical_position; // sfix18_En14
// Generate Position And Voltage
// <S17>/Rotor_Acceleration_To_Velocity
controllerHdl_Rotor_Acceleration_To_Velocity u_Rotor_Acceleration_To_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.Vel_Target(target_velocity), // sfix18_En8
.RV(rotor_velocity) // sfix32_En22
);
// <S17>/Frequency_To_Volts
controllerHdl_Frequency_To_Volts u_Frequency_To_Volts (.F(rotor_velocity), // sfix32_En22
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.V(volts_dt) // sfix18_En12
);
assign Q_Voltage = volts_dt;
// <S17>/Rotor_To_Electical_Velocity
controllerHdl_Rotor_To_Electical_Velocity u_Rotor_To_Electical_Velocity (.RV(rotor_velocity), // sfix32_En22
.EV(electrical_velocity) // sfix18_En6
);
// <S17>/Electrical_Velocity_To_Position
controllerHdl_Electrical_Velocity_To_Position u_Electrical_Velocity_To_Position (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.EV(electrical_velocity), // sfix18_En6
.EP(electrical_position) // sfix18_En14
);
assign Position = electrical_position;
endmodule // controllerHdl_Generate_Position_And_Voltage_Ramp
|
// $Id: c_prefix_arbiter_base.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// prefix tree based round-robin arbiter basic block
//==============================================================================
module c_prefix_arbiter_base
(prio_port, req, gnt);
// number of input ports
parameter num_ports = 32;
// port priority pointer
input [0:num_ports-1] prio_port;
// vector of requests
input [0:num_ports-1] req;
// vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
wire [0:num_ports-1] g_in;
assign g_in = prio_port;
wire [0:num_ports-1] p_in;
assign p_in = ~{req[num_ports-1], req[0:num_ports-2]};
wire [0:num_ports-1] g_out;
wire [0:num_ports-1] p_out;
c_prefix_net
#(.width(num_ports),
.enable_wraparound(1))
g_out_pn
(.g_in(g_in),
.p_in(p_in),
.g_out(g_out),
.p_out(p_out));
assign gnt = req & g_out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package pkga;
int pvar;
class MyClass;
int member;
function int getpvar(); return pvar; endfunction
endclass
endpackage
package pkgb;
int pvar;
class MyClass;
int member;
function int getpvar(); return pvar; endfunction
function int getavar(); return pkga::pvar; endfunction
endclass
endpackage
module t (/*AUTOARG*/);
initial begin
pkga::MyClass a;
pkgb::MyClass b;
pkga::pvar = 100;
pkgb::pvar = 200;
if (pkga::pvar != 100) $stop;
if (pkgb::pvar != 200) $stop;
a = new;
b = new;
a.member = 10;
b.member = 20;
if (a.member != 10) $stop;
if (b.member != 20) $stop;
if (a.getpvar() != 100) $stop;
if (b.getpvar() != 200) $stop;
if (b.getavar() != 100) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, x; cin >> n; vector<long long> a; for (int i = 0; i < n; i++) { cin >> x; a.push_back(x); } for (int i = 0; i < n - 1; i++) { cout << a[i] + a[i + 1] << ; } cout << a[n - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void Solution() { int n, k; cin >> n >> k; int a[n]; vector<int> v; for (int i = 0; i < n; i++) { cin >> a[i]; if (5 - a[i] >= k) { v.push_back(a[i]); } } cout << v.size() / 3 << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); Solution(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 1e6 + 5, P = 1e9 + 7; long long n, k, m, res, l, T, ans, mi; int dp[2][M], A[M], B[M], sum[M]; int main() { cin >> n >> l >> k; for (int i = 1; i <= n; i++) { scanf( %d , A + i); B[i] = A[i]; } sort(B + 1, B + 1 + n); m = unique(B + 1, B + 1 + n) - B - 1; for (int i = 1; i <= n; i++) A[i] = lower_bound(B + 1, B + 1 + m, A[i]) - B; T = l / n; res = l % n; for (int i = 1; i <= n; i++) dp[1][A[i]]++; ans = l % P; for (int i = 2; i <= m; i++) dp[1][i] += dp[1][i - 1]; for (int i = 1; i <= m; i++) sum[i] += dp[1][i]; for (int lop = 2; lop <= min(1ll * k, T); lop++) { int c = lop & 1; for (int i = 1; i <= m; i++) dp[c][i] = 0; for (int i = 1; i <= n; i++) dp[c][A[i]] = (1ll * (dp[c][A[i]] % P) + 1ll * (dp[!c][A[i]] % P)) % P; for (int i = 2; i <= m; i++) dp[c][i] = (1ll * (dp[c][i] % P) + 1ll * (dp[c][i - 1] % P)) % P; if (lop < k) for (int i = 1; i <= m; i++) sum[i] = (1ll * (sum[i] % P) + 1ll * (dp[c][i] % P)) % P; long long len = (T - lop + 1) % P; ans = (1ll * (ans % P) + 1ll * (len * dp[c][m] % P)) % P; } if (k >= 2 && T >= 1) for (int i = 1; i <= res; i++) ans = (1ll * (ans % P) + 1ll * (sum[A[i]] % P)) % P; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 500 * 1000 + 10; int n, h[Maxn], ans; vector<int> adj[Maxn], vec; bool mark[Maxn]; void dfs(int v) { mark[v] = true; if ((int)adj[v].size() == 1) vec.push_back(h[v]); for (int i = 0; i < (int)adj[v].size(); i++) if (!mark[adj[v][i]]) { h[adj[v][i]] = h[v] + 1; dfs(adj[v][i]); } return; } int main() { scanf( %d , &n); int u, v; for (int i = 0; i < n - 1; i++) { scanf( %d%d , &u, &v); u--; v--; adj[u].push_back(v); adj[v].push_back(u); } mark[0] = true; for (int i = 0; i < (int)adj[0].size(); i++) { dfs(adj[0][i]); sort(vec.begin(), vec.end()); reverse(vec.begin(), vec.end()); int cnt = 1; for (int j = 0; j < (int)vec.size(); j++) { if (vec[j] + cnt > ans) ans = vec[j] + cnt; cnt++; } vec.clear(); } printf( %d n , ans); return 0; } |
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