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//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_PO_reset for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_PO_reset
// Module Name: NPCG_Toggle_SCC_PO_reset
// File Name: NPCG_Toggle_SCC_PO_reset.v
//
// Version: v1.0.0
//
// Description: NFC phy output module reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_PO_reset
#
(
parameter NumberOfWays = 4
)
(
iSystemClock,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep,
oPM_PCommand
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
wire wModuleTriggered ;
localparam State_Idle = 3'b000;
localparam State_POResetIssue = 3'b001;
localparam State_POWait = 3'b011;
reg [1:0] rCurState ;
reg [1:0] rNextState ;
wire wPOResetTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_POResetIssue:State_Idle;
State_POResetIssue:
rNextState <= (iPM_Ready)?State_POWait:State_POResetIssue;
State_POWait:
rNextState <= (oLastStep)?State_Idle:State_POWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b110000);
assign oCMDReady = (rCurState == State_Idle);
assign wPOResetTrig = (rCurState == State_POResetIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_POWait) & iPM_LastStep[5];
assign oPM_PCommand = {1'b0, 1'b0, wPOResetTrig, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:38:14 02/27/2016
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(
input CLOCK,
input wire RESET,
input [2:0] MODE,
output [7:0] LED,
input FAST
);
//// GENRERATING SLOW CLOCK /////////////
wire CLOCK_IN;
reg [26:0] Buffer = 0;
always@ (posedge CLOCK) Buffer = Buffer + 1;
assign CLOCK_IN = FAST ? Buffer[1] : Buffer[0];
//// IO MODE SEL //////////////
assign LED[7] = RESET;
assign LED[6] = CLOCK_IN;
wire [5:0] OUTPUT;
assign LED[5:0] = OUTPUT;
wire [31:0] reg1;
wire [31:0] reg2;
wire [7:0] reg12;
assign reg12[5:3] = reg2;
assign reg12[2:0] = reg1;
wire [31:0] CURR_PC_IO;
wire [5:0] TEMP1;
wire [5:0] TEMP2;
assign TEMP1 = MODE[0] ? reg1:reg12;
assign TEMP2 = MODE[1] ? reg2:TEMP1;
assign OUTPUT = MODE[2]? CURR_PC_IO>>2:TEMP2;
////// main control signal / /////
wire REG_DST,
JUMP,
BRANCH,
MEM_READ,
MEM_TO_REG,
MEM_WRITE,
ALU_SRC,
REG_WRITE,
ZERO; //generated by ALU
wire [1:0] ALU_OP;
wire [3:0] ALU_CTR;
///////// data bus //////
wire [31:0] REG_DATA_1;
wire [31:0] REG_DATA_2; //reg read output
wire [4:0] REG_WRITE_ADDRESS;//reg write address, the data will be from the MEM_REG_MUX
wire [31:0] ALU_RES;
wire [31:0] EXTENDED_RES;
wire [31:0] MEM_READ_DATA; //address specified by alu result
wire [31:0] MEM_REG_MUX; //to be written into reg(memomy or alu result)
wire [31:0] REG_ALU_MUX; //which one to be used by ALU as the 2nd src(rt or imm)
/////////////////////////////////////////////////////////////////////////////////////////
//Instruction Memory
///////////////// ////////////////////////////////////////////////////////////////////////
reg [31:0] InstrMemory[9:0];
initial $readmemb("./src/inst.txt",InstrMemory);
//define AND initial Instruction Memory
wire [31:0] INSTR;
wire [31:0] PCp4;
wire [31:0] CURR_PC;
assign CURR_PC_IO = CURR_PC; //for the output part
assign INSTR = InstrMemory[CURR_PC>>2]; //fetch instruction by PC
/////////////////////////////////////////////////////////////////////////////////////////
//generating PC
/////////////////////////////////////////////////////////////////////////////////////////
wire [31:0] JUMP_ADDRESS;
wire [31:0] BEQ_ADDRESS;
//assign JUMP_ADDRESS
assign JUMP_ADDRESS[31:28] = PCp4[31:28];
assign JUMP_ADDRESS[27:2] = INSTR[25:0];
assign JUMP_ADDRESS[1:0] = 'b00;
//assign BEQ_ADDRESS
assign BEQ_ADDRESS[31:0] = (EXTENDED_RES<<2) + PCp4;
wire [31:0] PC_SRC_SEL;
wire [31:0] NEXT_PC;
//wire [31:0] PCp4;
//wire [31:0] CURR_PC; //declared above;
wire PC_SRC;
assign PC_SRC = BRANCH & ZERO;
assign PCp4[31:0] = CURR_PC[31:0] + 4;
//serval MUX below
assign PC_SRC_SEL[31:0] = PC_SRC ? BEQ_ADDRESS[31:0]: PCp4[31:0];
assign NEXT_PC[31:0] = JUMP ? JUMP_ADDRESS[31:0] : PC_SRC_SEL[31:0];
//serval MUX below:
assign MEM_REG_MUX = MEM_TO_REG ? MEM_READ_DATA : ALU_RES; //REG_WRITE_DATA
//R-type or load word
assign REG_ALU_MUX = ALU_SRC ? EXTENDED_RES : REG_DATA_2;
//which one to be used by ALU as the 2nd src
assign REG_WRITE_ADDRESS = REG_DST ? INSTR[15:11] : INSTR[20:16];
//which reg will be written
////////////////////////////////////////////////////////////////////////
//instances
////////////////////////////////////////////////////////////////////////
Pc mainPC(
.clock_in(CLOCK_IN),
.nextPC(NEXT_PC),
.currPC(CURR_PC),
.rst(RESET)
);
Ctr mainCtr(
.opCode(INSTR[31:26]),
.regDst(REG_DST),
.aluSrc(ALU_SRC),
.memToReg(MEM_TO_REG),
.regWrite(REG_WRITE),
.memRead(MEM_READ),
.memWrite(MEM_WRITE),
.branch(BRANCH),
.aluOp(ALU_OP),
.jump(JUMP)
);
AluCtr mainAluCtr (
.aluOp(ALU_OP),
.funct(INSTR[5:0]),
.aluCtr(ALU_CTR)
);
Alu mainAlu (
.input1(REG_DATA_1),
.input2(REG_ALU_MUX),
.aluCtr(ALU_CTR),
.zero(ZERO),
.aluRes(ALU_RES)
);
signExt mainSignExt (
.inst(INSTR[15:0]),
.data(EXTENDED_RES)
);
dataMemory mainDataMemory (
.clock_in(CLOCK_IN),
.address(ALU_RES),
.writeData(REG_DATA_2),
.readData(MEM_READ_DATA),
.memWrite(MEM_WRITE),
.memRead(MEM_READ)
);
Register mainRegister (
.clock_in(CLOCK_IN),
.regWrite(REG_WRITE),
.readReg1(INSTR[25:21]),
.readReg2(INSTR[20:16]),
.writeReg(REG_WRITE_ADDRESS),
.writeData(MEM_REG_MUX),
.reset(RESET),
.readData1(REG_DATA_1),
.readData2(REG_DATA_2),
.reg1(reg1),
.reg2(reg2)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; long long f = 0; char ch = getchar(); while (!isdigit(ch)) f = ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x = f ? -x : x; } const long long N = 15, M = 105; long long mp[N][N], f[N][1 << N], n, m, q; struct lca { long long x, y, z; } L[M]; struct xy { long long x, y; } B[M]; bool in(long long x, long long y) { return x & (1 << y); } long long dfs(long long u, long long mask) { if (~f[u][mask]) return f[u][mask]; long long &now = f[u][mask]; mask ^= (1 << u), now = 0; long long pos; for (long long i = 0; i < n; i++) if (mask & (1 << i)) { pos = i; break; } for (long long sub = mask; sub; sub = (sub - 1) & mask) { if (!(sub & (1 << pos))) continue; long long flag = 0, v = -1; for (long long i = 1; i <= q; i++) if (in(sub, L[i].z)) { if (!in(sub, L[i].x) || !in(sub, L[i].y)) { flag = 1; break; } } else if (u == L[i].z) { if (in(sub, L[i].x) && in(sub, L[i].y)) { flag = 1; break; } } if (flag) continue; for (long long i = 1; i <= m; i++) if (B[i].x != u && B[i].y != u && (in(sub, B[i].x) ^ in(sub, B[i].y))) { flag = 1; break; } if (flag) continue; for (long long i = 0; i < n; i++) if (mp[u][i] && in(sub, i)) if (!~v) v = i; else { flag = 1; break; } if (flag) continue; if (~v) now = (now + dfs(u, mask ^ (1 << u) ^ sub) * dfs(v, sub)); else for (long long i = 0; i < n; i++) if (in(sub, i)) now = (now + dfs(u, mask ^ (1 << u) ^ sub) * dfs(i, sub)); } return now; } signed main() { read(n), read(m), read(q); for (long long i = 1, x, y; i <= m; i++) read(B[i].x), read(B[i].y), --B[i].x, --B[i].y, mp[B[i].x][B[i].y] = mp[B[i].y][B[i].x] = 1; for (long long x, y, z, i = 1; i <= q; i++) read(L[i].x), read(L[i].y), read(L[i].z), L[i].x--, L[i].y--, L[i].z--; memset(f, -1, sizeof(f)); for (long long i = 0; i < n; i++) f[i][1 << i] = 1; printf( %lld , dfs(0, (1 << n) - 1)); } |
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
module DE1_SoC (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output reg [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
wire clk;
wire [15:0] data;
reg [6:0] hold;
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
wire [1:0] state, blockSel;
wire clkControl, rst, slowClk, outSel;
reg [4:0] readAdd0, readAdd1, writeAdd;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
//reg [15:0] data;
//assign data[6:0] = SW[6:0]
assign clkControl = SW[8];
assign state = SW[7:6];
assign blockSel = SW[5:4];
assign outSel = SW[3];
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store;
SRAM2Kby16 memory(clk, adx, WrEn, data);
clkSlower counter(slowClk, CLOCK_50, rst);
registerFile regs(clk, readAdd0, readAdd1, writeAdd, regWR, writeData, readOutput0, readOutput1);
always @(posedge clk) begin
if(rst) begin
hold = 0;
adx = 0;
WrEn = 1;
LEDR = 0;
end else if(state == 0) begin
WrEn = 0;
adx = hold;
store = 7'b1111111 - hold;
LEDR[6:0] = hold;
end else if(state == 1) begin
WrEn = 1;
regWR = 1;
writeAdd = hold[4:0];
adx = blockSel * 32 + hold[4:0];
writeData[15:0] = data;
end else if(state == 2) begin
WrEn = 1;
regWR = 0;
readAdd0 = hold[3:0];
readAdd1 = 16 + hold[3:0];
LEDR = outSel ? readOutput0[9:0] : readOutput1[9:0];
end else if(state == 3) begin
WrEn = 0;
regWR = 0;
if(blockSel[0]) begin
readAdd1 = hold[5:2] + 16;
if(hold[0]) begin
store = readOutput1[15:0];
adx = 179 + hold[5:2];
end else begin
store = readOutput1[15:0];
adx = 145 + hold[5:2];
end
end else begin
readAdd0 = hold[5:2];
if(hold[0]) begin
store = readOutput0[15:0];
adx = 162 + hold[5:2];
end else begin
store = readOutput0[15:0];
adx = 128 + hold[5:2];
end
end
end
hold = hold + 1'b1;
end
assign clk = clkControl ? slowClk : CLOCK_50;
endmodule
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoC dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter d = 20;
initial begin
CLOCK_50 = 1;
SW = 12;
KEY = 0;
end
always #(d/2) CLOCK_50 = ~CLOCK_50;
// Set up the inputs to the design
initial begin
#(d*10); SW[9] = 1;
#d; SW[9] = 0; SW[8] = 1;
#(d*500); SW[8] = 0;
#d SW[5:0] = 64;
#d SW[5:0] = 32;
#d SW[5:0] = 16;
#d SW[5:0] = 8;
#d SW[5:0] = 120;
$stop;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int c[210]; int pre[210][210]; int precnt[210]; int cnt[210] = {0}; int main() { int n; scanf( %d , &n); for (int i = 0; i < (n); i++) { scanf( %d , c + i); c[i] %= 3; } for (int i = 0; i < (n); i++) for (int j = 0; j < (n); j++) pre[i][j] = 0; for (int i = 0; i < (n); i++) { scanf( %d , precnt + i); int t; for (int j = 0; j < (precnt[i]); j++) { scanf( %d , &t); pre[i][t - 1] = 1; } } int mintime = 1000100; for (int p = 0; p < (3); p++) { int pos = p, time = 0, done = 0; for (int i = 0; i < (n); i++) cnt[i] = 0; while (done < n) { queue<int> Q; for (int i = 0; i < (n); i++) if (precnt[i] == cnt[i] && c[i] == pos) Q.push(i); while (!Q.empty()) { int part = Q.front(); Q.pop(); done++; time++; cnt[part]++; for (int i = 0; i < (n); i++) if (pre[i][part] == 1) { cnt[i]++; if (cnt[i] == precnt[i] && c[i] == pos) Q.push(i); } } pos = (pos + 1) % 3; time++; } time--; if (time < mintime) mintime = time; } printf( %d n , mintime); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [31:0] r32;
wire [3:0] w4;
wire [4:0] w5;
assign w4 = NUMONES_8 ( r32[7:0] );
assign w5 = NUMONES_16( r32[15:0] );
function [3:0] NUMONES_8;
input [7:0] i8;
reg [7:0] i8;
begin
NUMONES_8 = 4'b1;
end
endfunction // NUMONES_8
function [4:0] NUMONES_16;
input [15:0] i16;
reg [15:0] i16;
begin
NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] ));
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
r32 <= 32'h12345678;
end
if (cyc==2) begin
if (w4 !== 1) $stop;
if (w5 !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_PP_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; using LL = long long; using ll = long long; using pii = pair<int, int>; const int N = 2123456; const int INF = int(1e9); LL x; LL C[25][25]; int main() { for (int i = 0; i <= 20; ++i) { C[i][0] = 1; for (int j = 1; j <= i; ++j) C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; } ios_base::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; while (T--) { cin >> x; vector<int> cnt(25); int n = 0; for (int i = 2;; ++i) { if (x == 0) break; ++n; ++cnt[x % i]; x /= i; } LL ans = 1; int alr = 0; for (int i = n; i >= 0; --i) { if (cnt[i] == 0) continue; ans *= C[min(n - i + 1, n) - alr][cnt[i]]; alr += cnt[i]; } if (cnt[0]) { LL tot = 1; alr = 1; for (int i = n; i >= 1; --i) { if (cnt[i] == 0) continue; int cur = min(n - i + 1, n) - alr; if (cur < cnt[i]) { tot = 0; break; } tot *= C[cur][cnt[i]]; alr += cnt[i]; } ans -= tot; } cout << ans - 1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int an = 0; int ht; char a[20][20][20]; int h[20][20][20]; int fill(int x, int y, int k) { if (k <= 0 || k > ht || a[k][x][y] == # || h[k][x][y]) return 1; an++; h[k][x][y] = 1; fill(x - 1, y, k); fill(x, y - 1, k); fill(x, y + 1, k); fill(x + 1, y, k); fill(x, y, k - 1); fill(x, y, k + 1); return 1; } int main() { char s[100]; int x, y, i, j, k, n, m, u; memset(h, 0, sizeof(h)); scanf( %d%d%d , &k, &n, &m); ht = k; for (i = k; i > 0; i--) { for (j = 1; j < n + 1; j++) { scanf( %s , &a[i][j][1]); } } for (i = 1; i < k + 1; i++) { for (j = 0; j < m + 2; j++) { a[i][0][j] = # ; a[i][n + 1][j] = # ; } for (j = 0; j < n + 2; j++) { a[i][j][0] = # ; a[i][j][m + 1] = # ; } } scanf( %d%d , &x, &y); fill(x, y, k); printf( %d n , an); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5000 + 10; const int MOD = 998244353; long long f[maxn]; int lim[maxn]; long long frac[maxn], ifrac[maxn]; int arr[maxn], b[maxn]; int n; long long fpow(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret = (ret * a) % MOD; a = (a * a) % MOD; b >>= 1; } return ret; } void init() { frac[0] = 1; for (int i = 1; i < maxn; i++) frac[i] = frac[i - 1] * i % MOD; ifrac[maxn - 1] = fpow(frac[maxn - 1], MOD - 2); for (int i = maxn - 2; i >= 0; i--) ifrac[i] = ifrac[i + 1] * (i + 1) % MOD; return; } long long A(int a, int b) { if (a < b || b < 0) return 0; return frac[a] * ifrac[a - b] % MOD; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); init(); cin >> n; for (int i = 1; i <= n; i++) { cin >> arr[i]; b[i] = arr[i] * 2; } sort(arr + 1, arr + 1 + n); sort(b + 1, b + 1 + n); for (int i = 1; i <= n; i++) { int dex = upper_bound(b + 1, b + 1 + n, arr[i]) - b; --dex; lim[i] = dex; } f[0] = 1; lim[0] = -1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= lim[i]; j++) f[i] = (f[i] + f[j] * A(n - 2 - lim[j], lim[i] - lim[j] - 1) % MOD) % MOD; } if (lim[n] == n - 1) cout << f[n] << n ; else cout << 0 << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct edge { int flow; int next; int inv; int cap; int cost; }; const int N = 1100000; vector<edge> v[N]; int d[N]; int phi[N]; int from[N]; bool vis[N]; void add_edge(int x1, int x2, int x3, int x4) { edge x; x.next = x2; x.cost = x4; x.cap = x3; x.flow = 0; x.inv = v[x2].size(); v[x1].push_back(x); x.next = x1; x.cost = -x4; x.cap = 0; x.flow = 0; x.inv = v[x1].size() - 1; v[x2].push_back(x); } const int inf = (int)1e9; void init() { for (int i = 0; i < N; i++) { phi[i] = 0; v[i].clear(); } } void bfs(int n) { for (int i = 0; i < n; i++) vis[i] = false; queue<int> q; q.push(0); vis[0] = true; while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < v[x].size(); i++) if (!vis[v[x][i].next] && v[x][i].cap > v[x][i].flow) { vis[v[x][i].next] = true; from[v[x][i].next] = v[x][i].inv; q.push(v[x][i].next); } } } void dijkstra(int n) { for (int i = 0; i < n; i++) { d[i] = inf; vis[i] = false; } for (int i = 0; i < n; i++) vis[i] = false; set<pair<int, int> > q; d[0] = 0; for (int i = 1; i < n; i++) { d[i] = inf; q.insert(make_pair(d[i], i)); } q.insert(make_pair(0, 0)); while (!q.empty()) { int x = q.begin()->second; vis[x] = true; q.erase(q.begin()); if (d[x] == inf) break; for (int i = 0; i < v[x].size(); i++) if (!vis[v[x][i].next] && v[x][i].cap > v[x][i].flow) { int to = v[x][i].next; if (d[to] > d[x] + v[x][i].cost + phi[x] - phi[to]) { q.erase(make_pair(d[to], to)); d[to] = d[x] + v[x][i].cost + phi[x] - phi[to]; from[to] = v[x][i].inv; q.insert(make_pair(d[to], to)); } } } } int id[N]; void fuckin_levit(int n) { for (int i = 0; i < n; i++) { d[i] = inf; id[i] = 0; } d[0] = 0; deque<int> q; q.push_back(0); while (!q.empty()) { int x = q.front(); q.pop_front(); vis[x] = true; if (d[x] == inf) break; id[x] = 1; for (int i = 0; i < v[x].size(); i++) if (v[x][i].cap - v[x][i].flow > 0) { int to = v[x][i].next; int len = v[x][i].cost; if (d[to] > d[x] + len) { d[to] = d[x] + len; if (id[to] == 0) q.push_front(to); else if (id[to] == 1) q.push_back(to); from[to] = v[x][i].inv; id[to] = 1; } } } } pair<int, int> maxflow(int n, int mode) { int res_flow = 0; int res_cost = 0; while (true) { if (mode == 1) dijkstra(n); if (mode == 0) bfs(n); if (mode == 2) fuckin_levit(n); if (!vis[n - 1]) break; if (d[n - 1] == inf) break; if (mode == 1) { for (int i = 0; i < n - 1; i++) phi[i] += vis[i] ? d[i] : d[n - 1]; } int x = n - 1; int dflow = inf; int dcost = 0; while (x != 0) { int a = v[x][from[x]].next; int b = v[x][from[x]].inv; dflow = min(dflow, v[a][b].cap - v[a][b].flow); dcost += v[a][b].cost; x = a; } x = n - 1; while (x != 0) { int a = v[x][from[x]].next; int b = v[x][from[x]].inv; v[a][b].flow += dflow; v[x][from[x]].flow -= dflow; x = a; } res_flow += dflow; res_cost += dflow * dcost; } return make_pair(res_flow, res_cost); } int a[100][100]; vector<pair<int, int> > v1; vector<pair<int, int> > v2; int main() { cin.sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; init(); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> a[i][j]; if (((i + j) % 2) == 0) v1.push_back(make_pair(i, j)); else v2.push_back(make_pair(i, j)); } for (int i = 0; i < v2.size(); i++) add_edge(i + v1.size() + 1, n * m + 1, 1, 0); for (int i = 0; i < n * m / 2; i++) add_edge(0, i + 1, 1, 0); for (int i = 0; i < v1.size(); i++) for (int j = 0; j < v2.size(); j++) { int cost = 1; if (a[v1[i].first][v1[i].second] == a[v2[j].first][v2[j].second]) cost = 0; if ((abs(v1[i].first - v2[j].first) + abs(v1[i].second - v2[j].second)) == 1) if (cost == 0) add_edge(i + 1, j + v1.size() + 1, 1, cost); } maxflow(n * m + 2, 0); for (int i = 0; i < v1.size(); i++) for (int j = 0; j < v2.size(); j++) { int cost = 1; if (a[v1[i].first][v1[i].second] == a[v2[j].first][v2[j].second]) cost = 0; if ((abs(v1[i].first - v2[j].first) + abs(v1[i].second - v2[j].second)) == 1) if (cost == 1) add_edge(i + 1, j + v1.size() + 1, 1, cost); } pair<int, int> res = maxflow(n * m + 2, 2); cout << res.second << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int ans; int main() { int a[101010]; int b, c; cin >> b >> c; for (int i = 1; i <= b; ++i) { cin >> a[i]; } for (int i = 1; i <= b; ++i) { if (a[i] > c) ans += 2; else if (a[i] <= c) ans++; } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; if (n % 2) { cout << black ; } else { cout << white << endl; cout << 1 2 ; } return 0; } |
//`include "elink_regmap.v"
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
reg_write, reg_addr, clk1, clk2, nreset, vdd, vss, access_in,
packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
parameter IW = 10;
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//####################################################################
//#BODY
//####################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [5:0] reg_addr; // To pic of pic.v
input reg_write; // To pic of pic.v
// End of automatics
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire ic_flush; // From pic of pic.v
wire [IW-1:0] ic_ilat_reg; // From pic of pic.v
wire [IW-1:0] ic_imask_reg; // From pic of pic.v
wire [IW-1:0] ic_ipend_reg; // From pic of pic.v
wire [AW-1:0] ic_iret_reg; // From pic of pic.v
wire ic_irq; // From pic of pic.v
wire [AW-1:0] ic_irq_addr; // From pic of pic.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
assign clkout = clk1;
assign dut_active = 1'b1;
assign wait_out = 1'b0;
assign reg_write = write_in & access_in;
assign reg_addr[5:0] = dstaddr_in[7:2];
packet2emesh p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
pic #(.AW(AW),
.IW(IW))
pic (.reg_wdata (data_in[31:0]),
.ext_irq ({(IW){1'b0}}),
.sq_pc_next ({(AW){1'b0}}),
.de_rti (1'b0),
.sq_irq_en (1'b1),
.sq_ic_wait (1'b0),
.clk (clk1),
/*AUTOINST*/
// Outputs
.ic_iret_reg (ic_iret_reg[AW-1:0]),
.ic_imask_reg (ic_imask_reg[IW-1:0]),
.ic_ilat_reg (ic_ilat_reg[IW-1:0]),
.ic_ipend_reg (ic_ipend_reg[IW-1:0]),
.ic_flush (ic_flush),
.ic_irq (ic_irq),
.ic_irq_addr (ic_irq_addr[AW-1:0]),
// Inputs
.nreset (nreset),
.reg_write (reg_write),
.reg_addr (reg_addr[5:0]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> int main(void) { char a[100001]; long long current, jump[100001], n, i; int flag = 1, visited[100001]; memset(visited, 0, sizeof(visited)); scanf( %lld , &n); if (n == 1) { printf( FINITE ); return 0; } scanf( %s , a); for (i = 1; i <= n; i++) scanf( %lld , &jump[i]); current = 1; i = 1; while (flag == 1) { visited[current] = 1; if (a[current - 1] == > ) { current = current + jump[current]; } else { current = current - jump[current]; } if (current < 1 || current > n) { flag = 0; break; } if (visited[current] == 1) { break; } } if (flag == 0) { printf( FINITE ); } else { printf( INFINITE ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int const mod = 1e9 + 7; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int MIN(long long int a, long long int b) { if (a < b) return a; return b; } long long int MAX(long long int a, long long int b) { if (a > b) return a; return b; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); bool p[1000001]; memset(p, true, sizeof p); p[0] = p[1] = false; p[2] = true; for (int i = 2; i * i <= 1000001; i++) { if (p[i]) { for (int j = i * i; j <= 1000001; j += i) { p[j] = false; } } } vector<int> pp; for (int i = 2; i <= 1000001; i++) { if (p[i]) pp.push_back(i); } int t; cin >> t; while (t--) { int n; cin >> n; long long int a[n + 1]; for (int i = 0; i < n; i++) cin >> a[i + 1]; int dp[n + 1], ans = 1; dp[1] = 1; for (int i = 2; i <= n; i++) { dp[i] = 1; for (int j = 1; j * j <= i; j++) { if (i % j == 0) { if (a[i] > a[j]) dp[i] = MAX(dp[i], dp[j] + 1); if (a[i] > a[i / j]) dp[i] = MAX(dp[i], dp[i / j] + 1); } } ans = MAX(dp[i], ans); } cout << ans << n ; } return 0; } |
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone multiplexer, burst-compatible ////
/// ////
/// Simple mux with an arbitrary number of slaves. ////
/// ////
/// The parameters MATCH_ADDR and MATCH_MASK are flattened arrays ////
/// aw*NUM_SLAVES sized arrays that are used to calculate the ////
/// active slave. slave i is selected when ////
/// (wb_adr_i & MATCH_MASK[(i+1)*aw-1:i*aw] is equal to ////
/// MATCH_ADDR[(i+1)*aw-1:i*aw] ////
/// If several regions are overlapping, the slave with the lowest ////
/// index is selected. This can be used to have fallback ////
/// functionality in the last slave, in case no other slave was ////
/// selected. ////
/// ////
/// If no match is found, the wishbone transaction will stall and ////
/// an external watchdog is required to abort the transaction ////
/// ////
/// Olof Kindgren, ////
/// ////
/// Todo: ////
/// Registered master/slave connections ////
/// Rewrite with System Verilog 2D arrays when tools support them ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_mux
#(parameter dw = 32, // Data width
parameter aw = 32, // Address width
parameter num_slaves = 2, // Number of slaves
parameter [num_slaves*aw-1:0] MATCH_ADDR = 0,
parameter [num_slaves*aw-1:0] MATCH_MASK = 0)
(input wb_clk_i,
input wb_rst_i,
// Master Interface
input [aw-1:0] wbm_adr_i,
input [dw-1:0] wbm_dat_i,
input [3:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
input [2:0] wbm_cti_i,
input [1:0] wbm_bte_i,
output [dw-1:0] wbm_dat_o,
output wbm_ack_o,
output wbm_err_o,
output wbm_rty_o,
// Wishbone Slave interface
output [num_slaves*aw-1:0] wbs_adr_o,
output [num_slaves*dw-1:0] wbs_dat_o,
output [num_slaves*4-1:0] wbs_sel_o,
output [num_slaves-1:0] wbs_we_o,
output [num_slaves-1:0] wbs_cyc_o,
output [num_slaves-1:0] wbs_stb_o,
output [num_slaves*3-1:0] wbs_cti_o,
output [num_slaves*2-1:0] wbs_bte_o,
input [num_slaves*dw-1:0] wbs_dat_i,
input [num_slaves-1:0] wbs_ack_i,
input [num_slaves-1:0] wbs_err_i,
input [num_slaves-1:0] wbs_rty_i);
`include "verilog_utils.vh"
///////////////////////////////////////////////////////////////////////////////
// Master/slave connection
///////////////////////////////////////////////////////////////////////////////
localparam slave_sel_bits = num_slaves > 1 ? `clog2(num_slaves) : 1;
reg wbm_err;
wire [slave_sel_bits-1:0] slave_sel;
wire [num_slaves-1:0] match;
genvar idx;
generate
for(idx=0; idx<num_slaves ; idx=idx+1) begin : addr_match
assign match[idx] = (wbm_adr_i & MATCH_MASK[idx*aw+:aw]) == MATCH_ADDR[idx*aw+:aw];
end
endgenerate
assign slave_sel = ff1(match, num_slaves);
always @(posedge wb_clk_i)
wbm_err <= wbm_cyc_i & !(|match);
assign wbs_adr_o = {num_slaves{wbm_adr_i}};
assign wbs_dat_o = {num_slaves{wbm_dat_i}};
assign wbs_sel_o = {num_slaves{wbm_sel_i}};
assign wbs_we_o = {num_slaves{wbm_we_i}};
assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel);
assign wbs_stb_o = {num_slaves{wbm_stb_i}};
assign wbs_cti_o = {num_slaves{wbm_cti_i}};
assign wbs_bte_o = {num_slaves{wbm_bte_i}};
assign wbm_dat_o = wbs_dat_i[slave_sel*dw+:dw];
assign wbm_ack_o = wbs_ack_i[slave_sel];
assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err;
assign wbm_rty_o = wbs_rty_i[slave_sel];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int x; cin >> x; cin.ignore(); string input; getline(cin, input); int len = input.length(); int cnt[3] = {0}; for (int i = 0; i < len; i++) { if (input[i] == 0 ) cnt[0]++; else if (input[i] == 1 ) cnt[1]++; else if (input[i] == 2 ) cnt[2]++; } int max = len / 3; cnt[0] = max - cnt[0]; cnt[1] = max - cnt[1]; cnt[2] = max - cnt[2]; if (cnt[0] == 0 && cnt[1] == 0 && cnt[2] == 0) { std::cout << input << n ; } else { for (int i = 0; i < len && cnt[0] > 0; i++) { if (input[i] == 1 && cnt[1] < 0) { input[i] = 0 ; cnt[1]++; cnt[0]--; } else if (input[i] == 2 && cnt[2] < 0) { input[i] = 0 ; cnt[2]++; cnt[0]--; } } for (int i = len - 1; cnt[2] > 0; i--) { if (input[i] == 1 && cnt[1] < 0) { input[i] = 2 ; cnt[1]++; cnt[2]--; } else if (input[i] == 0 && cnt[0] < 0) { input[i] = 2 ; cnt[0]++; cnt[2]--; } } for (int i = 0; i < len && cnt[1] > 0 && cnt[2] < 0; i++) { if (input[i] == 2 ) { input[i] = 1 ; cnt[1]--; cnt[2]++; } } for (int i = len - 1; i >= 0 && cnt[1] > 0 && cnt[0] < 0; i--) { if (input[i] == 0 ) { input[i] = 1 ; cnt[1]--; cnt[2]++; } } std::cout << input << n ; } return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Shift CK/Address/Commands/Controls
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter DQS_CNT_WIDTH = 3,
parameter N_CTL_LANES = 3,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
// Start only after PO_CIRC_BUF_DELAY decremented
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_stg2_f_incdec,
output reg po_en_stg2_f,
output reg po_stg2_c_incdec,
output reg po_en_stg2_c,
// Completed delaying CK/Address/Commands/Controls
output po_ck_addr_cmd_delay_done
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
tCK > 2500 ? 2 : 1);
localparam integer PHASER_TAP_RES = ((tCK/2)/64);
// Determine whether 300 ps or 350 ps delay required
localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
// Determine the number of Phaser_Out taps required to delay by 300 ps
// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// Increment control byte lanes
localparam TAP_CNT = 0;
//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
//Decrement control byte lanes
localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
reg delay_dec_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
reg [5:0] delay_cnt_r;
reg [5:0] delaydec_cnt_r;
reg po_cnt_inc;
reg po_cnt_dec;
reg [3:0] wait_cnt_r;
assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
always @(posedge clk) begin
if (rst || po_cnt_dec || po_cnt_inc)
wait_cnt_r <= #TCQ 'd8;
else if (cmd_delay_start && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
po_cnt_inc <= #TCQ 1'b0;
else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_inc <= #TCQ 1'b1;
else
po_cnt_inc <= #TCQ 1'b0;
end
//Tap decrement
always @(posedge clk) begin
if (rst || (delaydec_cnt_r == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end else begin
if (po_cnt_dec) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b1;
end else begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end
if (po_cnt_inc) begin
po_stg2_c_incdec <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b1;
end else begin
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end
end
end
// delay counter to count 2 cycles
// Increment coarse taps by 2 for all control byte lanes
// to mitigate late writes
always @(posedge clk) begin
// load delay counter with init value
if (rst || (tCK >= 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
delay_cnt_r <= #TCQ 'd0;
else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delay_cnt_r <= #TCQ 'd1;
else if (po_cnt_inc && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// delay counter to count TAP_DEC cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_DEC
if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delaydec_cnt_r <= #TCQ TAP_DEC;
else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// All control lanes have decremented to 31 fine taps from 46
always @(posedge clk) begin
if (rst || ~cmd_delay_start) begin
delay_dec_done <= #TCQ 1'b0;
end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
delay_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_dec_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, y = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) y = 1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return y ? -x : x; } template <typename T> inline T read() { T x = 0; int y = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) y = 1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return y ? -x : x; } char s[40]; long long pw[40] = {-0x3f3f3f3f, 1}, f[40][40]; bool g[40][40]; signed main() { int n = read(); scanf( %s , s + 1); for (register int i = 2; i <= n; ++i) pw[i] = pw[i - 1] * 10; memset(f, ~0x3f, sizeof f); f[(n << 1) + 1][0] = 0; for (register int i = n << 1; i; --i) for (register int j = 0; j <= min((n << 1) - i + 1, n); ++j) { f[i][j] = max(f[i + 1][j - 1] + pw[j] * (s[i] - 0 ), f[i + 1][j] + pw[(n << 1) - i + 1 - j] * (s[i] - 0 )); g[i][j] = f[i + 1][j - 1] + pw[j] * (s[i] - 0 ) > f[i + 1][j] + pw[(n << 1) - i + 1 - j] * (s[i] - 0 ); } for (register int i = 1, j = n; i <= n << 1; ++i) putchar(g[i][j] ? H : M ), j -= g[i][j]; putchar( n ); } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int M = 100005; const int MOD = 1e9 + 7; long long c[100005], x, k, tot = 0; vector<long long> son[100005]; void dfs(int n, int m) { if (tot >= 100000) return; if (n == 0 || m == 0) { printf( %I64d , c[n]); ++tot; return; } for (int v : son[n]) dfs(v, m - 1); } int main() { cin >> x >> k; if (k == 0) { printf( %I64d n , x); return 0; } int top = 0; for (int i = 1; i * 1ll * i < x; ++i) { if (x % i == 0) { c[top++] = i; c[top++] = x / i; } } if (sqrt(x) * sqrt(x) == x) c[top++] = sqrt(x); sort(c, c + top); for (int i = 0; i < top; ++i) for (int j = 0; j <= i; ++j) if (c[i] % c[j] == 0) son[i].push_back(j); dfs(top - 1, k); return 0; } |
#include <bits/stdc++.h> using namespace std; void OJ() {} long long n, m, x, k, y; long long a[200000 + 5], b[200000 + 5]; void imp() { cout << -1 << n , exit(0); } long long remove(long long start, long long end) { if (start > end) return 0; long long sz = end - start + 1; long long maxneb = max(a[start - 1], a[end + 1]); long long m = *max_element(a + start, a + end + 1); long long a1 = (sz / k) * x + (sz % k) * y; if (maxneb > m) return min(a1, y * sz); if (sz < k) imp(); return min(a1, (sz - k) * y + x); } void solve() { cin >> n >> m >> x >> k >> y; for (long long i = 1; i <= n; ++i) cin >> a[i]; for (long long i = 1; i <= m; ++i) cin >> b[i]; long long ans = 0; long long j = 1; for (long long i = 1; i <= m; ++i) { long long start = j; while (j <= n && a[j] != b[i]) j++; if (j > n) imp(); ans += remove(start, j - 1); j++; } ans += remove(j, n); cout << ans << n ; } signed main() { OJ(); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (osc_clk);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 0 will completely
// unroll the calculations, resulting in 128 rounds and a large, but
// fast design.
//
// A setting of 1 will result in 64 rounds, with half the size and
// half the speed. 2 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 0;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input osc_clk;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
`ifndef SIM
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("STAT")) midstate_vw_blk(.probe(), .source(midstate_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
`endif
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
`ifndef SIM
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce), .source());
//virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce), .source());
`endif
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
`ifndef SIM
wire reset;
assign reset = 1'b0;
`else
reg reset = 1'b0; // NOTE: Reset is not currently used in the actual FPGA; for simulation only.
`endif
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decaphe ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9, N = 101; int n, m, q, tot, a[N], b[N]; int vis[N]; bool solve(int pos) { memset(vis, 0, sizeof(vis)); for (int i = pos; i < pos + tot; i++) vis[a[i]]++; for (int i = 1; i < m + 1; i++) if (vis[i] != b[i]) return 0; return 1; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < m + 1; i++) { cin >> b[i]; tot += b[i]; } for (int i = 0; i < n - tot + 1; i++) if (solve(i)) return !(cout << YES << endl); cout << NO << endl; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : ime_sad_16x16_buffer.v
// Author : Huang Lei Lei
// Created : 2014-12-10
// Description : buffer 16x16 sad
//
//-------------------------------------------------------------------
//
// Modified : 2014-12-21
// Description : bug removed (port name and memory datawidth)
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module ime_sad_16x16_buffer (
// global
clk ,
rstn ,
// ctrl_i
addr_i ,
wren_i ,
block_i ,
// sad_i
sad_16x16_x0_i ,
sad_16x16_x1_i ,
sad_16x16_x2_i ,
sad_16x16_x3_i ,
// sad_o
sad_16x16_00_o ,
sad_16x16_01_o ,
sad_16x16_02_o ,
sad_16x16_03_o ,
sad_16x16_10_o ,
sad_16x16_11_o ,
sad_16x16_12_o ,
sad_16x16_13_o ,
sad_16x16_20_o ,
sad_16x16_21_o ,
sad_16x16_22_o ,
sad_16x16_23_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// global
input clk ;
input rstn ;
// ctrl_i
input [4 : 0] addr_i ;
input wren_i ;
input [1 : 0] block_i ;
// sad_i
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x0_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x1_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x2_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x3_i ;
// sad_o
output [`PIXEL_WIDTH+7 : 0] sad_16x16_00_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_01_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_02_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_03_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_10_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_11_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_12_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_13_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_20_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_21_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_22_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_23_o ;
//*** WIRE & REG DECLARATION ***************************************************
//*** MAIN BODY ****************************************************************
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer0 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b00)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_00_o ,sad_16x16_01_o ,sad_16x16_02_o ,sad_16x16_03_o } )
);
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer1 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b01)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_10_o ,sad_16x16_11_o ,sad_16x16_12_o ,sad_16x16_13_o } )
);
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer2 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b10)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_20_o ,sad_16x16_21_o ,sad_16x16_22_o ,sad_16x16_23_o } )
);
//*** DEBUG ********************************************************************
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int n, k, size[maxn]; bool f[maxn]; long long dp[maxn]; vector<int> g[maxn]; void dfs(int u, int fa) { if (f[u]) size[u] = 1; else size[u] = 0; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == fa) continue; dfs(v, u); size[u] += size[v]; dp[u] += dp[v] + size[v]; } } long long ans = 0; int solve(int u, int fa) { int sum = (f[u] ? 1 : 0); for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == fa) continue; sum += solve(v, u); } ans += min(sum, 2 * k - size[u]); return min(sum, 2 * k - size[u]); } int main() { scanf( %d%d , &n, &k); int x; for (int i = 1; i <= 2 * k; i++) scanf( %d , &x), f[x] = 1; int u, v; for (int i = 1; i <= n - 1; i++) scanf( %d%d , &u, &v), g[u].push_back(v), g[v].push_back(u); dfs(1, -1); solve(1, -1); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long num[100010]; int main() { int n, q, req; while (~scanf( %d%d%d , &n, &q, &req)) { bool res[100010]; res[0] = true; res[n + 1] = true; for (int i = 1; i <= n; i++) { scanf( %d , &num[i]); if (num[i] <= req) res[i] = true; else res[i] = false; } int qiu = 0; bool flag = true; for (int i = 1; i <= n; i++) { if (flag == true && res[i] == false) { qiu++; flag = false; } if (res[i] == true) flag = true; } for (int i = 0; i < q; i++) { int cur; scanf( %d , &cur); if (cur == 0) { cout << qiu << endl; } else { int a; long long b; scanf( %d%lld , &a, &b); num[a] += b; if (res[a] == true && num[a] > req) { res[a] = false; if (res[a - 1] == false && res[a + 1] == false) qiu--; if (res[a - 1] == true && res[a + 1] == true) qiu++; } } } } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000009; const double PI = acos(-1.0); const double eps = 1e-8; const int MAXN = 0; const int MAXM = 0; bool a[5002]; int i, j, k, n, h, m, id, p, hesh; map<int, int> M; char c; int ans = 0; int main() { cin >> h >> m >> n; for (i = 0; i < n; i++) { cin >> c; if (c == - ) { cin >> id; a[M[id]] = 0; } else { cin >> id >> hesh; while (a[hesh] != 0) { hesh = (hesh + m) % h; ans++; } a[hesh] = true; M[id] = hesh; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, a[N], maxi[4 * N]; pair<int, int> p[N]; vector<int> v[3]; bool cmp(pair<int, int> p1, pair<int, int> p2) { if (p1.first == p2.first) return p1.second > p2.second; else return p1.first < p2.first; } void merge(int at) { maxi[at] = max(maxi[2 * at], maxi[2 * at + 1]); } void build(int at, int L, int R) { if (L == R) { maxi[at] = 0; return; } int mid = (L + R) / 2; build(2 * at, L, mid); build(2 * at + 1, mid + 1, R); merge(at); } void update(int at, int L, int R, int pos, int val) { if (L == R) { maxi[at] = val; return; } int mid = (L + R) / 2; if (pos <= mid) update(2 * at, L, mid, pos, val); else update(2 * at + 1, mid + 1, R, pos, val); merge(at); } int query(int at, int L, int R, int l, int r) { if (r < L || l > R) return 0; if (l <= L && r >= R) return maxi[at]; int mid = (L + R) / 2; int x = query(2 * at, L, mid, l, r); int y = query(2 * at + 1, mid + 1, R, l, r); return max(x, y); } int main() { int n, n1, n2, n3, q, x; scanf( %d %d %d , &n1, &n2, &n3); ; n = n1 + n2 + n3; for (int j = 0; j < n1; j++) { scanf( %d , &x); v[0].push_back(x); } for (int j = 0; j < n2; j++) { scanf( %d , &x); v[1].push_back(x); } for (int j = 0; j < n3; j++) { scanf( %d , &x); v[2].push_back(x); } for (int i = 0; i < 3; i++) sort(v[i].begin(), v[i].end()); int cnt = 0; for (int i = 0; i < 3; i++) { for (int u : v[i]) { p[cnt] = make_pair(u, cnt); cnt++; } } sort(p, p + n, cmp); build(1, 0, n - 1); int maxi = 0; for (int i = 0; i < n; i++) { int tmp = query(1, 0, n - 1, 0, p[i].second - 1); maxi = max(maxi, tmp + 1); update(1, 0, n - 1, p[i].second, tmp + 1); } printf( %d n , n - maxi); } |
#include <bits/stdc++.h> const double eps = 1e-19; const double PI = acos(-1.0); const int INF = 1000 * 1000 * 1000 + 7; const int MAXN = 300005; using namespace std; int n, m; int ans[MAXN]; vector<int> g[MAXN]; bool used[MAXN]; void dfs(int v) { int kol = 0; for (int j = 0; j < (int)g[v].size(); j++) if (ans[v] == ans[g[v][j]]) kol++; if (kol > 1) { ans[v] ^= 1; for (int j = 0; j < (int)g[v].size(); j++) { dfs(g[v][j]); } } } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int ta, tb; scanf( %d %d , &ta, &tb); ta--; tb--; g[ta].push_back(tb); g[tb].push_back(ta); } memset(ans, 0, sizeof ans); for (int i = 0; i < n; i++) dfs(i); for (int i = 0; i < n; i++) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; const double INF = 1e18; int n, m, c; int a[N], p[N], f[N]; double E[N]; struct Node { double L, M, R, S; Node() {} Node(double L, double M, double R, double S) : L(L), M(M), R(R), S(S) {} }; struct SegmentTree { Node st[4 * N]; Node Merge(Node A, Node B) { Node C; C.L = max(A.L, A.S + B.L); C.R = max(B.R, B.S + A.R); C.M = max(A.M, max(B.M, A.R + B.L)); C.S = A.S + B.S; return C; } void Init(int k, int l, int r) { if (l == r) { double val = E[l]; st[k] = Node(val, val, val, val); return; } Init(k << 1, l, ((l + r) >> 1)); Init(k << 1 | 1, ((l + r) >> 1) + 1, r); st[k] = Merge(st[k << 1], st[k << 1 | 1]); } Node Query(int k, int l, int r, int i, int j) { if (l > j || r < i) return Node(-INF, -INF, -INF, 0); if (i <= l && r <= j) return st[k]; return Merge(Query(k << 1, l, ((l + r) >> 1), i, j), Query(k << 1 | 1, ((l + r) >> 1) + 1, r, i, j)); } } ST; double Query(int l, int r) { Node ans = ST.Query(1, 1, n - 1, l, r); return max(ans.L, max(ans.R, ans.M)); } int main() { cin >> n >> m >> c; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i < n; ++i) cin >> p[i]; for (int i = 1; i < n; ++i) { double prob = (double)p[i] / 100; double val = (double)(a[i + 1] - a[i]) / 2 - prob * c; E[i] = val; } ST.Init(1, 1, n - 1); double ans = 0; while (m--) { int u, v; cin >> u >> v; ans += max(0.00, Query(u, v - 1)); } cout << fixed << setprecision(10) << ans << endl; return 0; } |
module FpuFp64_Add(
/* verilator lint_off UNUSED */
clk,
enable,
doSub,
srca,
srcb,
dst
);
input clk;
input enable;
input doSub;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
reg[12:0] exm;
reg[63:0] tFracA;
reg[63:0] tFracB;
reg[63:0] tFracC;
reg[63:0] tFracA1;
reg[63:0] tFracB1;
reg[63:0] tFracC1;
reg[63:0] tFracC2;
reg[63:0] tFracC2_A; //32
reg[63:0] tFracC2_B; //16
reg[63:0] tFracC2_C; //8
reg[63:0] tFracC2_D; //4
reg[63:0] tFracC2_E; //2
reg[12:0] tExc_A;
reg[12:0] tExc_B;
reg[12:0] tExc_C;
reg[12:0] tExc_D;
reg[12:0] tExc_E;
reg[63:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
sgna=srca[63];
sgnb=srcb[63];
exa[10:0]=srca[62:52];
exb[10:0]=srcb[62:52];
exa[12:11]=0;
exb[12:11]=0;
exm=(exa>=exb)?exa:exb;
if(sgna)
begin
tFracA[63:52]=~(12'h1);
tFracA[51:0]=~(srca[51:0]);
end
else
begin
tFracA[63:52]=12'h1;
tFracA[51:0]=srca[51:0];
end
if(sgnb^doSub)
begin
tFracB[63:52]=~(12'h1);
tFracB[51:0]=~(srcb[51:0]);
end
else
begin
tFracB[63:52]=12'h1;
tFracB[51:0]=srcb[51:0];
end
tFracA1=tFracA>>>(exm-exa);
tFracB1=tFracB>>>(exm-exb);
tFracC1=tFracA1+tFracB1;
if(tFracC1[63])
begin
sgnc=1;
tFracC2=~tFracC1;
end
else
begin
sgnc=0;
tFracC2=tFracC1;
end
if(tFracC2[52:0]==0)
begin
sgnc=0;
tFracC=0;
exc=0;
end
else
if(tFracC2[53:52]==0)
begin
if(tFracC2[52:21]==0)
begin
tFracC2_A=tFracC2<<32;
tExc_A=exm-32;
end
else
begin
tFracC2_A=tFracC2;
tExc_A=exm;
end
if(tFracC2_A[52:37]==0)
begin
tFracC2_B=tFracC2_A<<16;
tExc_B=tExc_A-16;
end
else
begin
tFracC2_B=tFracC2_A;
tExc_B=tExc_A;
end
if(tFracC2_B[52:45]==0)
begin
tFracC2_C=tFracC2_B<<8;
tExc_C=tExc_B-8;
end
else
begin
tFracC2_C=tFracC2_B;
tExc_C=tExc_B;
end
if(tFracC2_C[52:49]==0)
begin
tFracC2_D=tFracC2_C<<4;
tExc_D=tExc_C-4;
end
else
begin
tFracC2_D=tFracC2_C;
tExc_D=tExc_C;
end
if(tFracC2_D[52:51]==0)
begin
tFracC2_E=tFracC2_D<<2;
tExc_E=tExc_D-2;
end
else
begin
tFracC2_E=tFracC2_D;
tExc_E=tExc_D;
end
if(tFracC2_E[52]==0)
begin
tFracC=tFracC2_E<<1;
exc=tExc_E-1;
end
else
begin
tFracC=tFracC2_E;
exc=tExc_E;
end
end
else
begin
if(tFracC2[53])
begin
tFracC=tFracC2>>1;
exc=exm+1;
end
else
begin
tFracC=tFracC2;
exc=exm;
end
end
if(exc[12])
begin
tDst[63:0]=64'h0;
end
else if(exc[11])
begin
tDst[63]=sgnc;
tDst[62:0]=63'h7FF0_0000_0000_0000;
end
else
begin
tDst[63]=sgnc;
tDst[62:52]=exc[10:0];
tDst[51:0]=tFracC[51:0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000 + 10]; int ret[21][21]; int pool[410], two[100]; int main() { ios::sync_with_stdio(false); memset(a, 0, sizeof(a)); memset(ret, 0, sizeof(ret)); memset(pool, 0, sizeof(pool)); memset(two, 0, sizeof(two)); int n; cin >> n; int t, tag = 0, tt = 0; for (int i = 0; i < n * n; i++) { cin >> t; a[t]++; } if (n == 1) { cout << yes << n ; cout << t << n ; return 0; } if (n % 2) { int cnt = 0; for (int i = 1; i <= 1000; i++) { if (a[i] % 4) { if (a[i] % 2) { if (cnt == 0) { ret[n / 2][n / 2] = i; a[i]--; cnt = 1; } else { cout << no << n ; return 0; } } if (a[i] % 4) { two[tt++] = i; a[i] -= 2; if (tt > (n - 1)) { cout << no << n ; return 0; } } } while (a[i] > 0) { pool[tag++] = i; a[i] -= 4; } } while (tt < (n - 1)) { two[tt++] = pool[--tag]; two[tt++] = pool[tag]; } int cnt2 = 0, cnt4 = 0; for (int i = 0; i * 2 < n; i++) { for (int j = 0; j * 2 < n; j++) { if (i == n / 2 && j == n / 2) continue; if (i == n / 2) { ret[i][j] = two[cnt2++]; ret[i][n - j - 1] = ret[i][j]; } else if (j == n / 2) { ret[i][j] = two[cnt2++]; ret[n - i - 1][j] = ret[i][j]; } else { ret[i][j] = pool[cnt4++]; ret[n - i - 1][n - j - 1] = ret[i][j]; ret[i][n - j - 1] = ret[i][j]; ret[n - i - 1][j] = ret[i][j]; } } } } else { bool can = true; for (int i = 1; i <= 1000; i++) { if (a[i] % 4) { cout << no << n ; return 0; } while (a[i] > 0) { pool[tag++] = i; a[i] -= 4; } } for (int i = 0; i * 2 < n; i++) { for (int j = 0; j * 2 < n; j++) { ret[i][j] = pool[i * n / 2 + j]; ret[n - i - 1][n - j - 1] = ret[i][j]; ret[i][n - j - 1] = ret[i][j]; ret[n - i - 1][j] = ret[i][j]; } } } cout << yes << n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cout << ret[i][j]; if (j == n - 1) cout << n ; else cout << ; } } } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool f = 0; char ch = getchar(); while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return f ? -x : x; } inline void write(int x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(48 + x % 10); } inline void writeln(int x) { write(x); putchar( n ); } inline void writebl(int x) { write(x); putchar( ); } const int maxn = 2e5 + 5; struct edge { int v, w, next; } e[maxn]; int head[maxn], ecnt; int color[maxn], out[maxn]; int tot1, tot2, n, ans = -1, want; queue<int> q; void dfs(int x) { if (color[x]) ++tot1; else ++tot2; q.push(x); for (register int i = head[x]; i; i = e[i].next) { int v = e[i].v, w = color[x] ^ want ^ e[i].w; if (color[v] < 0) { color[v] = w; dfs(v); if (tot1 < 0) return; } else if (color[v] != w) { tot1 = -1; return; } } } inline void solve(int op) { want = op; int res = 0; memset(color, -1, sizeof(color)); for (register int i = 1; i <= n; ++i) if (color[i] < 0) { while (q.size()) q.pop(); tot1 = tot2 = 0; color[i] = 1; dfs(i); if (tot1 < 0) { res = -1; break; } res += tot1 < tot2 ? tot1 : tot2; register bool t = tot1 > tot2; while (q.size()) color[q.front()] ^= t, q.pop(); } if ((ans == -1 || ans > res) && res != -1) { for (register int i = 1; i <= n; ++i) out[i] = color[i]; ans = res; } } int main() { n = read(); int m = read(); for (register int i = 1; i <= m; ++i) { int u = read(), v = read(), w; char ch = getchar(); while (ch != R && ch != B ) ch = getchar(); w = ch == R ; e[++ecnt] = (edge){v, w, head[u]}, head[u] = ecnt; e[++ecnt] = (edge){u, w, head[v]}, head[v] = ecnt; } solve(0); solve(1); writeln(ans); if (ans != -1) for (register int i = 1; i <= n; ++i) if (out[i]) writebl(i); } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { if (i == 1) printf( 14 n ); else { if (i == 2) printf( 16 n ); else printf( %lld n , (1LL * i * (i + 1) * (i + 1) - (i - 1))); } } return 0; } |
`timescale 1ns / 1ps
`define intN 32
`define addrN 9
`include "primitives.v"
`define axi_module tests_axil_map_w
`include "tests_axil_map_w.v"
`include "array.v"
module tests_axi_lite_slave_top
(
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [8:0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [31:0] s_axi_wdata,
input wire [3:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [8:0] s_axi_araddr,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [31:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready
);
wire clk = s_axi_aclk;
wire nrst = s_axi_aresetn;
`wire(Array, (`addrN, `intN), arr);
array #(.N(64))
arr(.clk(clk),
`out(Array, 0, arr));
`wire(stream, `addrN, ar);
`wire(stream, `addrN, aw);
`wire(stream, `intN , w);
`wire(stream, `intN , r);
`wire(null_stream, 0, b);
wire inst_in_ready;
`inst_sync(`id(`axi_module), inst, #())(
`sync(`true, `true),
`in(Array, 0, arr),
`in(stream, 1, ar),
`in(stream, 2, aw),
`in(stream, 3, w),
`out(stream, 0, r),
`out(null_stream, 1, b));
`define from_axi_hs(stream) \
assign stream``_valid = s_axi_``stream``valid; \
assign s_axi_``stream``ready = stream``_ready
`define from_axi(stream, signal, shift) \
assign stream = s_axi_``stream``signal >> shift; \
`from_axi_hs(stream)
`define to_axi_hs(stream) \
assign s_axi_``stream``valid = stream``_valid; \
assign stream``_ready = s_axi_``stream``ready
`define to_axi(stream, signal) \
assign s_axi_``stream``signal = stream; \
`to_axi_hs(stream)
`from_axi(ar, addr, 2);
`from_axi(aw, addr, 2);
`from_axi(w, data, 0);
`to_axi(r, data);
`to_axi_hs(b);
assign s_axi_wstrb = 4'b1111;
assign s_axi_bresp = 2'b00; // OKAY
assign s_axi_rresp = 2'b00; // OKAY
endmodule // tests_axi_lite_slave_top
|
#include <bits/stdc++.h> int main() { int sum = 0, a, n, m, i; scanf( %d %d , &n, &m); for (i = 1; i <= n; i++) { sum = sum + i; if (m > sum && i == n) { i = 0; } a = m - sum; if (a < i + 1) { printf( %d , a); break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, i, j = 0, k, l, T, c = 0, t = 0; long long a[10010], d[10010], e[10010]; string s; int main() { getline(cin, s); a[0] = s[0] - 48; d[0] = a[0]; e[0] = 0; for (i = 1; i < s.length() - 1; i += 2) { if (s[i] == * ) { a[i + 1] = a[i - 1] - d[i - 1] + d[i - 1] * (s[i + 1] - 48); d[i + 1] = d[i - 1] * (s[i + 1] - 48); e[i + 1] = i + 1; for (k = j; k < i; k += 2) { e[k] = i + 1; d[k] = d[i + 1]; } } else if (s[i] == + ) { a[i + 1] = a[i - 1] + s[i + 1] - 48; d[i + 1] = s[i + 1] - 48; e[i + 1] = i + 1; j = i + 1; } } for (i = 1; i < s.length() - 1; i += 2) { if (s[i] == * ) { t = 1; c = max(c, a[i - 1] * (d[i + 1] / (s[i - 1] - 48)) + a[s.length() - 1] - a[e[i + 1]]); if (i > 1) { if (s[i - 2] == + ) { c = max(c, a[i - 3] + (d[e[i + 1]] / (s[e[i + 1]] - 48)) * (a[s.length() - 1] - a[e[i + 1]] + (s[e[i + 1]] - 48))); } } else { c = max(c, (d[e[i + 1]] / (s[e[i + 1]] - 48)) * (a[s.length() - 1] - a[e[i + 1]] + (s[e[i + 1]] - 48))); } for (j = e[i + 1] + 1; j < s.length() - 1; j += 2) { if (s[j] == * and s[j - 2] == + ) { c = max(c, a[i - 3] + (d[i + 1] / (s[e[i + 1]] - 48)) * (d[j + 1] / (s[j - 1] - 48)) * (a[j - 1] - a[e[i + 1]] + s[e[i + 1]] - 48) + a[s.length() - 1] - a[e[j + 1]]); } } i = e[i + 1] - 1; } } if (t == 0) { c = a[s.length() - 1]; } cout << c; } |
#include <bits/stdc++.h> using namespace std; char str[200], pat[20][200]; map<pair<int, int>, int> H[20]; set<pair<int, int> > st; int a[20], b[20]; int N; int main() { int i, j, k, h, len, ans, cnt; scanf( %s , str); scanf( %d , &N); for (i = 0; i < N; i++) scanf( %s%d%d , &pat[i], &a[i], &b[i]); for (i = 0; i < N; i++) { len = strlen(pat[i]); for (j = 0; j < len; j++) { h = 0; for (k = j; k < len; k++) { h = h * 129 + pat[i][k]; if (!H[i].count(pair<int, int>(h, k - j + 1))) H[i][pair<int, int>(h, k - j + 1)] = 0; H[i][pair<int, int>(h, k - j + 1)]++; } } } ans = 0; len = strlen(str); for (i = 0; i < len; i++) { h = 0; for (j = i; j < len; j++) { h = h * 129 + str[j]; if (st.find(pair<int, int>(h, j - i + 1)) != st.end()) continue; st.insert(pair<int, int>(h, j - i + 1)); for (k = 0; k < N; k++) { if (!H[k].count(pair<int, int>(h, j - i + 1))) cnt = 0; else cnt = H[k][pair<int, int>(h, j - i + 1)]; if (cnt < a[k] || cnt > b[k]) break; } if (k == N) ans++; } } printf( %d n , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 11:21:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_util_ds_buf_0_0 -prefix
// system_util_ds_buf_0_0_ system_util_ds_buf_0_0_stub.v
// Design : system_util_ds_buf_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_ds_buf,Vivado 2016.4" *)
module system_util_ds_buf_0_0(BUFG_I, BUFG_O)
/* synthesis syn_black_box black_box_pad_pin="BUFG_I[0:0],BUFG_O[0:0]" */;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int p, n, m, x[10005], ans; char c[10005], *s; void Init() { scanf( %d , &p); scanf( %s , c + 1); if (c[1] == - ) s = c + 1; else { c[0] = + ; s = c; } n = strlen(s); int d, t; for (int i = 0; i <= n - 1; ++i) { if (s[i] == + ) d = 1; else d = -1; ++i; if (s[i] == + ) ans += d, x[++m] = d; else if (s[i] == a ) x[++m] = d; else { t = 0; while (s[i] != * ) { t = t * 10 + (s[i] - 48) * d; ++i; } ++i; if (s[i] == + ) ans += t, x[++m] = t; else if (s[i] == a ) x[++m] = t; } i += 2; } } void Work() { sort(x + 1, x + 1 + m); for (int i = 1; i <= m; ++i) { ans += x[i] * p; ++p; } printf( %d n , ans); } int main() { Init(); Work(); return 0; } |
//`include "quad_detector.v"
//`include "reciprocal_divider.v"
module gearbox(clk, phaseA, phaseB, step_pulse);
parameter COUNT_BITS = 32;
parameter CLKF = 53200000; // clock freq Hz
parameter REGTICKSX = 19;
parameter REGTICKS = 1 << REGTICKSX; // =2^19 clk ticks for each regulator loop turn (CLKF/REGTICKS = 101 approx)
parameter STEP_PULSE_TICKS = 5;
parameter m = 1;
parameter d = 1;
parameter MPE = 200 * 32 * 6 / 1600; // motor revolution pulses per encoder revolution pulses
parameter MXMPE = m * MPE;
input clk, phaseA, phaseB;
output step_pulse;
reg [COUNT_BITS - 1:0] encoder_position = 0, scaled_encoder_position = 0, scaled_motor_position = 0, step_freq_m, step_freq_d;
quad_detector qd(clk, phaseA, phaseB, encoder_step, encoder_up);
reciprocal_divider rd(clk, step_freq_m, step_freq_d, motor_step);
reg [31:0] step_pulse_timer = 0;
assign step_pulse = step_pulse_timer > 0;
reg [COUNT_BITS - 1:0] prev_encoder_position = 0;
reg [31:0] reg_tick_counter = 0;
always @(posedge clk) begin
if (reg_tick_counter == 0) begin
// regulator step
step_freq_m = 2 * scaled_encoder_position - prev_encoder_position - scaled_motor_position;
step_freq_d = d << REGTICKSX; // d / dt = d * REGTICKS
$display(scaled_encoder_position, scaled_encoder_position-prev_encoder_position,scaled_motor_position, step_freq_m);
prev_encoder_position = scaled_encoder_position;
reg_tick_counter = REGTICKS;
end
reg_tick_counter = reg_tick_counter - 1;
end
always @(posedge clk) begin
if (motor_step == 1) begin
scaled_motor_position = scaled_motor_position + d;
step_pulse_timer = STEP_PULSE_TICKS;
end
if (step_pulse_timer > 0) step_pulse_timer = step_pulse_timer - 1;
end
always @(posedge encoder_step) begin
if (encoder_up) begin
encoder_position = encoder_position + 1;
scaled_encoder_position = scaled_encoder_position + MXMPE;
end else begin
encoder_position = encoder_position - 1;
scaled_encoder_position = scaled_encoder_position - MXMPE;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long const mod = 998244353; long long const inf = 1e15; long long n, m, k, x; long long w[200004], ans[200004]; pair<long long, long long> t[800003]; void build(long long nd, long long l, long long r) { if (l == r) { t[nd] = {w[l], l}; return; } long long mid = (l + r) / 2; build(2 * nd, l, mid); build(2 * nd + 1, mid + 1, r); if (t[2 * nd].first <= t[2 * nd + 1].first) t[nd] = t[2 * nd]; else t[nd] = t[2 * nd + 1]; } void up(long long nd, long long l, long long r, long long a, long long b) { if (a > r || a < l) return; if (l == r) { t[nd] = {b, a}; return; } long long mid = (l + r) / 2; up(2 * nd, l, mid, a, b); up(2 * nd + 1, mid + 1, r, a, b); if (t[2 * nd].first <= t[2 * nd + 1].first) t[nd] = t[2 * nd]; else t[nd] = t[2 * nd + 1]; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k >> x; long long d1 = 0, d2 = 0; long long mn = 0, mx = n + 1; w[0] = inf; w[n + 1] = -inf; long long v = -1; for (int i = 1; i <= n; i++) { cin >> w[i]; if (w[i] == 0) { if (v == -1) v = i; else { if (k) { w[i] -= x; k--; } } } if (w[i] > 0) { d1++; if (w[i] < w[mn]) mn = i; } else if (w[i] < 0) { d2++; if (w[i] > w[mx]) mx = i; } } if (v != -1 && k) { if (d2 % 2) w[v] = x; else w[v] = -x, d2++; k--; } if (d2 % 2 == 0) { long long dd1, dd2; dd1 = dd2 = 1e9; if (d1) dd1 = w[mn] / x + 1; if (d2) dd2 = (abs(w[mx])) / x + 1; if ((dd1 == dd2 && (x - w[mn] % x) >= (x - (abs(w[mx])) % x)) || (dd1 < dd2)) { w[mn] -= min(dd1, k) * x; k -= min(dd1, k); } else { w[mx] += min(dd2, k) * x; k -= min(dd2, k); } } for (int i = 1; i <= n; i++) ans[i] = w[i], w[i] = abs(w[i]); build(1, 1, n); for (int ff = 1; ff <= k; ff++) { pair<long long, long long> d = t[1]; if (ans[d.second] > 0) ans[d.second] += x; else ans[d.second] -= x; up(1, 1, n, d.second, abs(ans[d.second])); } for (int i = 1; i <= n; i++) cout << ans[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; using big = long long; const int N = 200200; int a[N]; int f[N][2][2][2][2]; int dfs(int n, int x, int y, int v1, int v2) { if (!n) { assert(!x && !y); return v1 > v2; } if (x && !dfs(n - 1, x - 1, y, v2, !v1)) { return true; } if (y && !dfs(n - 1, x, y - 1, v2, v1)) { return true; } return false; } vector<int> to_vec(int x, int y) { return {x % 4, y % 4}; } map<vector<int>, int> init() { map<vector<int>, int> g; vector<vector<int>> ans; for (int n = 1; n <= 16; ++n) { for (int x = 1; x <= n; x += 2) { int y = n - x; int res = dfs(n, x, y, 0, 0); if (g.count(to_vec(x, y)) && g[to_vec(x, y)] != res) { cerr << ERRRR << endl; } assert(!g.count(to_vec(x, y)) || g[to_vec(x, y)] == res); g[to_vec(x, y)] = res; ans.push_back({x, y, res}); } } return g; } int main() { ios_base::sync_with_stdio(false); auto g = init(); int cas; cin >> cas; memset(f, -1, sizeof(f)); while (cas--) { int n; cin >> n; int s = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; s ^= a[i]; } int highest = 0; for (int i = 0; (1ll << i) <= s; ++i) { highest = i; } int cnt = 0; for (int i = 0; i < n; ++i) { if (a[i] >> highest & 1) { ++cnt; } } int other = n - cnt; if (!s) { cout << DRAW << n ; } else { assert(cnt & 1); if (g[to_vec(cnt, other)]) { cout << WIN << n ; } else { cout << LOSE << n ; } } } return 0; } |
// MBT 10/16/14
//
// note: this does a scan from hi bit to lo
// so the high bit is always unchanged
//
// note: implements Kogge-Stone style prefix tree
// which may have excessive wiring as width_p grows
//
`include "bsg_defines.v"
module bsg_scan #(parameter `BSG_INV_PARAM(width_p)
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter lo_to_hi_p = 0
, parameter debug_p = 0
)
(input [width_p-1:0] i
, output logic [width_p-1:0] o
);
// derivation of the scan code (xor case):
// width_p = 1 1
// t1 = i
//
// width_p = 4 1111
// t1 = i ^ (i >> 1) 1111 ^ 0111 --> 1000
// t2 = t1 ^ (t1 >> 2) 1000 ^ 0010 --> 1010
// t4 = t2 ^ (t2 >> 4) 1010 ^ 0000 --> 1010 (not needed)
// width_p = 5 11111
// t1 = i ^ (i >> 1) 11111 ^ 01111 --> 10000
// t2 = t1 ^ (t1 >> 2) 10000 ^ 00100 --> 10100
// t4 = t2 ^ (t2 >> 4) 10100 ^ 00001 --> 10101 (needed)
// width_p = 8 1111_1111
// t1 = i ^ (i >> 1) 1111_1111 ^ 0111_1111 --> 1000_0000
// t2 = t1 ^ (t1 >> 2) 1000_0000 ^ 0010_0000 --> 1010_0000
// t4 = t2 ^ (t2 >> 4) 1010_0000 ^ 0000_1010 --> 1010_1010 (needed)
//
// 1 2 3 4 5 6 7 8 9
// clog2 0 1 2 2 3 3 3 3 4
genvar j;
wire [$clog2(width_p):0][width_p-1:0] t;
wire [width_p-1:0] fill;
// synopsys translate_off
initial
assert( $countones({xor_p[0], and_p[0], or_p[0]}) == 1)
else $error("bsg_scan: only one function may be selected\n");
if (debug_p)
always @(o)
begin
`BSG_HIDE_FROM_VERILATOR(#1)
for (integer k = 0; k <= $clog2(width_p); k=k+1)
$display("%b",t[k]);
$display("i=%b, o=%b",i, o);
end
// synopsys translate_on
// streaming operation; reverses bits
if (lo_to_hi_p)
assign t[0] = {<< {i}};
else
assign t[0] = i;
// we optimize for the common case of small and-scans
// used in round_robin_fifo_to_fifo
// we could generalize for OR/XORs as well.
// fixme style: use a loop instead
if ((width_p == 4) & and_p)
begin : scand4
assign t[$clog2(width_p)] = { t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0] };
end
else if ((width_p == 3) & and_p)
begin: scand3
assign t[$clog2(width_p)] = { t[0][2], &t[0][2:1], &t[0][2:0] };
end
else if ((width_p == 2) & and_p)
begin: scand3
assign t[$clog2(width_p)] = { t[0][1], &t[0][1:0] };
end
else
begin : scanN
for (j = 0; j < $clog2(width_p); j = j + 1)
begin : row
wire [width_p-1:0] shifted = width_p ' ({fill, t[j]} >> (1 << j));
if (xor_p)
begin
assign fill = { width_p {1'b0} };
assign t[j+1] = t[j] ^ shifted;
end
else if (and_p)
begin
assign fill = { width_p {1'b1} };
assign t[j+1] = t[j] & shifted;
end
else if (or_p)
begin
assign fill = { width_p {1'b0} };
assign t[j+1] = t[j] | shifted;
end
end
end // block: scanN
// reverse bits
if (lo_to_hi_p)
//assign o = {<< {t[$clog2(width_p)]}};
for (j = 0; j < width_p; j++) begin
assign o[j] = t[$clog2(width_p)][width_p-1-j];
end
else
assign o = t[$clog2(width_p)];
// always @(o)
// $display("bsg_scan (xor_p %b and_p %b or_p %b) %b = %b",xor_p[0],and_p[0],or_p[0],i,o);
endmodule
`BSG_ABSTRACT_MODULE(bsg_scan)
|
#include <bits/stdc++.h> using namespace std; const int Imx = 2147483647; const long long Lbig = 2e18; const int mod = 1e9 + 7; struct fastio { char s[100000]; int it, len; fastio() { it = len = 0; } inline char get() { if (it < len) return s[it++]; it = 0; len = fread(s, 1, 100000, stdin); if (len == 0) return EOF; else return s[it++]; } bool notend() { char c = get(); while (c == || c == n ) c = get(); if (it > 0) it--; return c != EOF; } } _buff; inline long long getnum() { long long r = 0; bool ng = 0; char c; c = _buff.get(); while (c != - && (c < 0 || c > 9 )) c = _buff.get(); if (c == - ) ng = 1, c = _buff.get(); while (c >= 0 && c <= 9 ) r = r * 10 + c - 0 , c = _buff.get(); return ng ? -r : r; } template <class T> inline void putnum(T x) { if (x < 0) putchar( - ), x = -x; register short a[20] = {}, sz = 0; while (x) a[sz++] = x % 10, x /= 10; if (sz == 0) putchar( 0 ); for (int i = sz - 1; i >= 0; i--) putchar( 0 + a[i]); } inline char getreal() { char c = _buff.get(); while (c <= 32) c = _buff.get(); return c; } long long qpow(long long x, long long k) { return k == 0 ? 1 : 1ll * qpow(1ll * x * x % mod, k >> 1) * (k & 1 ? x : 1) % mod; } int n; vector<int> vy; int getidy(int y) { return upper_bound(vy.begin(), vy.end(), y) - vy.begin(); } bool ANS[100111]; struct node { set<int> st, tst; int mn, mx; int cmxu, hmxu; void add(int x) { st.insert(x); tst.insert(x); mx = *st.rbegin(); } void del(int x) { st.erase(x); tst.erase(x); assert(st.size() > 0); mx = *st.rbegin(); } node() { add(0); cmxu = hmxu = mn = 0; } void query(int x) { while (tst.size() > 0 && *tst.rbegin() >= x) ANS[*tst.rbegin()] = 1, tst.erase(--tst.end()); } } a[800111]; void updateu(int p) { a[p].cmxu = max(a[p >> 1].cmxu, a[p].mx); } void update(int p, bool isl) { a[p].mn = max(a[p].mx, (isl ? 0 : min(a[p << 1].mn, a[p << 1 | 1].mn))); } void deltag(int p, bool isl) { a[p].query(max(a[p].mn, max(a[p].hmxu, a[p].mx))); if (!isl) { int cmxu = max(a[p].hmxu, a[p].mx); a[p << 1].hmxu = min(a[p << 1].hmxu, cmxu), a[p << 1 | 1].hmxu = min(a[p << 1 | 1].hmxu, cmxu); } a[p].hmxu = a[p >> 1].cmxu; } void modify(int x, int y, int op, int v, int l, int r, int p = 1) { deltag(p, l == r); updateu(p); if (x <= l && r <= y) { if (op == 1) a[p].add(v); else a[p].del(v); updateu(p); update(p, l == r); if (l < r) { a[p << 1].hmxu = min(a[p << 1].hmxu, a[p].cmxu); a[p << 1 | 1].hmxu = min(a[p << 1 | 1].hmxu, a[p].cmxu); } a[p].query(max(a[p].mn, a[p].cmxu)); return; } int m = l + r >> 1; if (x <= m) modify(x, y, op, v, l, m, p << 1); if (m < y) modify(x, y, op, v, m + 1, r, p << 1 | 1); update(p, l == r); a[p].query(max(a[p].mn, a[p].cmxu)); } void pushdownall(int l, int r, int p) { deltag(p, l == r); updateu(p); a[p].query(max(a[p].mn, a[p].cmxu)); if (l == r) return; int m = l + r >> 1; pushdownall(l, m, p << 1); pushdownall(m + 1, r, p << 1 | 1); } struct query { int op, x, yl, yr, id; bool operator<(const query &t) const { return make_pair(make_pair(x, op), op == 1 ? -id : id) < make_pair(make_pair(t.x, t.op), t.op == 1 ? -t.id : t.id); } }; vector<query> qr; int main() { n = getnum(); for (int i = 1; i <= n; i++) { int xl, yl, xr, yr; xl = getnum(), yl = getnum(); xr = getnum(), yr = getnum(); yr--; vy.push_back(yl); vy.push_back(yr + 1); query tmp; tmp.yl = yl; tmp.yr = yr; tmp.id = i; tmp.x = xl; tmp.op = 1; qr.push_back(tmp); tmp.x = xr; tmp.op = 2; qr.push_back(tmp); } sort(vy.begin(), vy.end()); vy.erase(unique(vy.begin(), vy.end()), vy.end()); sort(qr.begin(), qr.end()); int sz = vy.size(); for (int i = 0; i < qr.size(); i++) { int yl = getidy(qr[i].yl); int yr = getidy(qr[i].yr); modify(yl, yr, qr[i].op, qr[i].id, 1, sz); } int ans = 0; for (int i = 0; i <= n; i++) ans += ANS[i]; cout << ans << endl; return 0; } |
#include<bits/stdc++.h> using namespace std; int main() { int t,p,k,q,b; cin>>t; string s; while(t--) { cin>>s; k=0; q=0; b=0; p=0; for(int i=0;i<s.size();i++) { if(s[0]== ) || s[s.size()-1]== ( ) { p=0; break;} else if( s[i]== ( ) { k++; } else if(s[i]== ? ) q++; else if(s[i]== ) ) b++; } if(k==b && q%2!=0 && k>0) p=0; else if(k==b&& q%2==0&& k>0) p=1; else if(q== abs(k-b) && k>0) p=1; if(p==1) cout<< yes <<endl; else cout<< NO <<endl; } } |
#include <bits/stdc++.h> using namespace std; using ll = unsigned long long; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int k; cin >> k; int n = (1 << k); vector<vector<ll> > a(n, vector<ll>(n, 0)); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; int t; cin >> t; vector<pair<int, int> > shape(t); for (int i = 0; i < t; i++) cin >> shape[i].first >> shape[i].second; for (int r = 0; r < k; r++) { vector<vector<ll> > b(n, vector<ll>(n, 0)); for (int c = 0; c < t; c++) { for (int i = 0; i < (1 << k); i++) { for (int j = 0; j < (1 << k); j++) { b[(i + shape[c].first) & ((1 << k) - 1)] [(j + shape[c].second) & ((1 << k) - 1)] ^= a[i][j]; } } } a = b; for (int c = 0; c < t; c++) { shape[c].first = (shape[c].first * 2) % n; shape[c].second = (shape[c].second * 2) % n; } } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (a[i][j]) ans++; cout << ans << n ; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module aceusb(
/* WISHBONE interface */
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* Signals shared between SystemACE and USB */
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output aceusb_oe_n,
output aceusb_we_n,
/* SystemACE signals */
input ace_clkin,
output ace_mpce_n,
input ace_mpirq,
output usb_cs_n,
output usb_hpi_reset_n,
input usb_hpi_int
);
wire access_read1;
wire access_write1;
wire access_ack1;
/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
reg load_adr_dat;
reg [5:0] address_reg;
reg [15:0] data_reg;
always @(posedge sys_clk) begin
if(load_adr_dat) begin
address_reg <= wb_adr_i[7:2];
data_reg <= wb_dat_i[15:0];
end
end
aceusb_access access(
.ace_clkin(ace_clkin),
.rst(sys_rst),
.a(address_reg),
.di(data_reg),
.do(wb_dat_o[15:0]),
.read(access_read1),
.write(access_write1),
.ack(access_ack1),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign wb_dat_o[31:16] = 16'h0000;
/* Synchronize read, write and acknowledgement pulses */
reg access_read;
reg access_write;
wire access_ack;
aceusb_sync sync_read(
.clk0(sys_clk),
.flagi(access_read),
.clk1(ace_clkin),
.flago(access_read1)
);
aceusb_sync sync_write(
.clk0(sys_clk),
.flagi(access_write),
.clk1(ace_clkin),
.flago(access_write1)
);
aceusb_sync sync_ack(
.clk0(ace_clkin),
.flagi(access_ack1),
.clk1(sys_clk),
.flago(access_ack)
);
/* Main FSM */
reg state;
reg next_state;
parameter IDLE = 1'd0;
parameter WAIT = 1'd1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
load_adr_dat = 1'b0;
wb_ack_o = 1'b0;
access_read = 1'b0;
access_write = 1'b0;
next_state = state;
case(state)
IDLE: begin
if(wb_cyc_i & wb_stb_i) begin
load_adr_dat = 1'b1;
if(wb_we_i)
access_write = 1'b1;
else
access_read = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(access_ack) begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; struct par { int x, t; bool operator!=(par k) { return x != k.x || t != k.t; } } p[N], p2[N]; int flag, n, sa[N], ea[N], sb[N], eb[N], _[N], _lans, _rans, key1[N], key2[N]; bool cmp(par x, par y) { int kx = x.t == 1 ? sa[x.x] : ea[x.x]; int ky = y.t == 1 ? sa[y.x] : ea[y.x]; return kx * 2 + (1 ^ x.t) == ky * 2 + (1 ^ y.t) ? x.x < y.x : kx * 2 + (1 ^ x.t) < ky * 2 + (1 ^ y.t); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d%d%d , sa + i, ea + i, sb + i, eb + i); for (int i = 1; i <= n; i++) _[i] = rand(); for (int i = 1; i <= 2 * n; i++) p[i] = (par){(i - 1) / 2 + 1, i & 1}; sort(p + 1, p + 1 + n + n, cmp); _lans = _rans = 0; for (int i = 1; i <= n; i++) _lans ^= _[i]; for (int i = 1; i <= 2 * n; i++) { int x = p[i].x, t = p[i].t; if (t) { _lans ^= _[x]; key1[x] ^= _rans; } else { _rans ^= _[x]; key1[x] ^= _lans; } } memcpy(p2, p, sizeof(p)); for (int i = 1; i <= n; i++) swap(sa[i], sb[i]), swap(ea[i], eb[i]); for (int i = 1; i <= 2 * n; i++) p[i] = (par){(i - 1) / 2 + 1, i & 1}; sort(p + 1, p + 1 + n + n, cmp); _lans = _rans = 0; for (int i = 1; i <= n; i++) _lans ^= _[i]; for (int i = 1; i <= 2 * n; i++) { int x = p[i].x, t = p[i].t; if (t) { _lans ^= _[x]; key2[x] ^= _rans; } else { _rans ^= _[x]; key2[x] ^= _lans; } } for (int i = 1; i <= n; i++) if (key1[i] != key2[i]) flag = 1; puts(flag ? NO : YES ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_4_V
`define SKY130_FD_SC_HDLL__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_4_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T CMP_MIN(T a, T b) { return a < b; } template <class T> T CMP_MAX(T a, T b) { return a > b; } template <class T> T MAX(T a, T b) { return a > b ? a : b; } template <class T> T MIN(T a, T b) { return a < b ? a : b; } template <class T> T GCD(T a, T b) { return b ? GCD(b, a % b) : a; } template <class T> T LCM(T a, T b) { return a / GCD(a, b) * b; } const int MAXN = 110000; const int MAXM = 1000006; const double eps = 1e-10; const long long MOD = 1000000007; int n, k, l, r, sa, sk; int main() { while (~scanf( %d %d %d %d %d %d , &n, &k, &l, &r, &sa, &sk)) { int p = sk % k, v = sk / k; printf( %d , v + (p ? 1 : 0)); for (int i = 1; i < k; i++) { printf( %d , v + (i < p ? 1 : 0)); } if (k < n) { p = (sa - sk) % (n - k); v = (sa - sk) / (n - k); for (int i = 0; i < n - k; i++) { printf( %d , v + (i < p ? 1 : 0)); } } printf( n ); } return 0; } |
// Based on https://github.com/YosysHQ/yosys/blob/master/tests/various/const_func.v
//
// ISC License
//
// Copyright (C) 2012 - 2020 Claire Wolf <>
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
module Example(outA, outB, outC, outD);
parameter OUTPUT = "FOO";
output wire [23:0] outA;
output wire [23:0] outB;
output reg outC, outD;
function automatic [23:0] flip;
input [23:0] inp;
flip = ~inp;
endfunction
generate
if (flip(OUTPUT) == flip("BAR"))
assign outA = OUTPUT;
else
assign outA = 0;
case (flip(OUTPUT))
flip("FOO"): assign outB = OUTPUT;
flip("BAR"): assign outB = 0;
flip("BAZ"): assign outB = "HI";
endcase
genvar i;
initial outC = 0;
for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
if (i + 1 == flip(flip("O")))
initial #1 outC = 1;
endgenerate
integer j;
initial begin
outD = 1;
for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
if (j + 1 == flip(flip("O")))
outD = 0;
end
endmodule
module top(out);
wire [23:0] a1, a2, a3, a4;
wire [23:0] b1, b2, b3, b4;
wire c1, c2, c3, c4;
wire d1, d2, d3, d4;
Example e1(a1, b1, c1, d1);
Example #("FOO") e2(a2, b2, c2, d2);
Example #("BAR") e3(a3, b3, c3, d3);
Example #("BAZ") e4(a4, b4, c4, d4);
output wire [24 * 8 - 1 + 4 :0] out;
assign out = {
a1, a2, a3, a4,
b1, b2, b3, b4,
c1, c2, c3, c4,
d1, d2, d3, d4};
initial begin
#2;
$display("%h %h %h %h", a1, a2, a3, a4);
$display("%h %h %h %h", b1, b2, b3, b4);
$display(c1,,c2,,c3,,c4);
$display(d1,,d2,,d3,,d4);
if((a1 === 0)
&& (a2 === 0)
&& (a3 === "BAR")
&& (a4 === 0)
&& (b1 === "FOO")
&& (b2 === "FOO")
&& (b3 === 0)
&& (b4 === "HI")
&& (c1 === 1)
&& (c2 === 1)
&& (c3 === 0)
&& (c4 === 0)
&& (d1 === 0)
&& (d2 === 0)
&& (d3 === 1)
&& (d4 === 1))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ans, k, cnt1[200010], cnt2[200010][10]; vector<long long> adj[200010]; long long sub(long long a, long long b) { return (a - b + k) % k; } void dfs(long long st, long long par, long long depth) { cnt2[st][depth % k] = 1; cnt1[st] = 1; for (int l = 0; l < adj[st].size(); l++) { long long to = adj[st][l]; if (to != par) { dfs(to, st, depth + 1); for (int i = 0; i < k; i++) { for (int j = 0; j < k; j++) { long long rem = sub(i + j, 2 * depth); long long need = sub(k, rem); ans += need * cnt2[st][i] * cnt2[to][j]; } } for (int i = 0; i < k; i++) { cnt2[st][i] += cnt2[to][i]; } cnt1[st] += cnt1[to]; } } long long sv = cnt1[st]; ans += sv * (n - sv); } int main() { ans = 0; memset(cnt1, 0, sizeof(cnt1)); ; memset(cnt2, 0, sizeof(cnt2)); ; cin >> n >> k; for (int i = 1; i < n; i++) { long long a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } dfs(1, -1, 0); cout << ans / k << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 5; struct segment_change { int to_add; segment_change(int _to_add = 0) : to_add(_to_add) {} void reset() { to_add = 0; } bool has_change() const { return to_add != 0; } segment_change combine(const segment_change &other) const { return segment_change(to_add + other.to_add); } }; struct segment { int maximum; segment(int _maximum = -INF) : maximum(_maximum) {} void apply(int, const segment_change &change) { maximum += change.to_add; } void join(const segment &other) { maximum = max(maximum, other.maximum); } void join(const segment &a, const segment &b) { *this = a; join(b); } }; struct add_max_seg_tree { int tree_n = 0; vector<segment> tree; vector<segment_change> changes; add_max_seg_tree(int n = 0) { if (n > 0) init(n); } void init(int n) { tree_n = 1; while (tree_n < n) tree_n *= 2; tree.assign(2 * tree_n, segment()); changes.assign(tree_n, segment_change()); } void build(const vector<segment> &initial) { int n = initial.size(); assert(n <= tree_n); for (int i = 0; i < n; i++) tree[tree_n + i] = initial[i]; for (int position = tree_n - 1; position > 0; position--) tree[position].join(tree[2 * position], tree[2 * position + 1]); } void push_down(int position, int length) { if (!changes[position].has_change()) return; if (2 * position < tree_n) { changes[2 * position] = changes[2 * position].combine(changes[position]); changes[2 * position + 1] = changes[2 * position + 1].combine(changes[position]); } tree[2 * position].apply(length / 2, changes[position]); tree[2 * position + 1].apply(length / 2, changes[position]); changes[position].reset(); } void push_all(int a, int b) { assert(0 <= a && a < b && b <= tree_n); a += tree_n; b += tree_n - 1; for (int up = 31 - __builtin_clz(tree_n); up > 0; up--) { int x = a >> up, y = b >> up; push_down(x, 1 << up); if (x != y) push_down(y, 1 << up); } } void join_and_apply(int position, int length) { tree[position].join(tree[2 * position], tree[2 * position + 1]); tree[position].apply(length, changes[position]); } void join_all(int a, int b) { assert(0 <= a && a < b && b <= tree_n); a += tree_n; b += tree_n - 1; int length = 1; while (a > 1) { a /= 2; b /= 2; length *= 2; join_and_apply(a, length); if (a != b) join_and_apply(b, length); } } pair<int, int> right_half[32]; template <typename T_range_op> void process_range(int a, int b, bool needs_join, T_range_op &&range_op) { if (a == b) return; push_all(a, b); int original_a = a, original_b = b; int length = 1, r_size = 0; for (a += tree_n, b += tree_n; a < b; a /= 2, b /= 2, length *= 2) { if (a & 1) range_op(a++, length); if (b & 1) right_half[r_size++] = {--b, length}; } for (int i = r_size - 1; i >= 0; i--) range_op(right_half[i].first, right_half[i].second); if (needs_join) join_all(original_a, original_b); } segment query(int a, int b) { assert(0 <= a && a <= b && b <= tree_n); segment answer; process_range(a, b, false, [&](int position, int) { answer.join(tree[position]); }); return answer; } void update(int a, int b, const segment_change &change) { assert(0 <= a && a <= b && b <= tree_n); process_range(a, b, true, [&](int position, int length) { tree[position].apply(length, change); if (position < tree_n) changes[position] = changes[position].combine(change); }); } void set_value(int index, int value) { assert(0 <= index && index < tree_n); int current = query(index, index + 1).maximum; update(index, index + 1, segment_change(value - current)); } }; int N; vector<int> parent; vector<vector<int>> children; vector<int> tour_start, tour_end; int tour; void dfs(int node) { tour_start[node] = tour++; for (int child : children[node]) dfs(child); tour_end[node] = tour; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; for (typename vector<T>::const_iterator vi = v.begin(); vi != v.end(); ++vi) { if (vi != v.begin()) os << , ; os << *vi; } os << } ; return os; } template <> ostream &operator<<(ostream &os, const vector<string> &v) { os << { ; for (vector<string>::const_iterator vi = v.begin(); vi != v.end(); ++vi) { if (vi != v.begin()) os << , ; os << << *vi << ; } os << } ; return os; } vector<int> solve(vector<int> perm) { assert((int)perm.size() == N); assert(perm.front() == 1); for (int &p : perm) p--; parent.assign(N, -1); vector<pair<int, int>> events; vector<int> stack = {-1}; for (int x : perm) { int erased = -1; while (stack.back() > x) { erased = stack.back(); stack.pop_back(); } events.emplace_back(x, stack.back()); events.emplace_back(erased, x); parent[x] = stack.back(); if (erased >= 0) parent[erased] = x; stack.push_back(x); } children.assign(N, {}); tour_start.resize(N); tour_end.resize(N); for (int i = 0; i < N; i++) if (parent[i] >= 0) children[parent[i]].push_back(i); tour = 0; dfs(0); vector<int> answers(N, INF); add_max_seg_tree tree(N); for (int i = 0; i < N; i++) { int a = events[2 * i].first; int b = events[2 * i].second; assert(a >= 0); tree.set_value( tour_start[a], b < 0 ? 1 : tree.query(tour_start[b], tour_start[b] + 1).maximum + 1); a = events[2 * i + 1].first; b = events[2 * i + 1].second; if (a >= 0) { tree.update(tour_start[a], tour_end[a], segment_change(+1)); } answers[i] = tree.query(0, N).maximum; } return answers; } vector<int> A; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> N; A.resize(N); for (int &a : A) cin >> a; int one = find(A.begin(), A.end(), 1) - A.begin(); vector<int> start_one, end_one; for (int i = one; (int)start_one.size() < N; i = (i + 1) % N) start_one.push_back(A[i]); for (int i = one; (int)end_one.size() < N; i = (i + N - 1) % N) end_one.push_back(A[i]); vector<int> left = solve(end_one), right = solve(start_one); int best_left = 0, best = INF; for (int i = 0; i < N; i++) { if (max(left[i], right[N - 1 - i]) < best) { best = max(left[i], right[N - 1 - i]); best_left = i; } } cout << best << << (one - best_left + N) % N << n ; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000009; const int MAXN = 100000; int n, m; vector<pair<int, int> > graph[MAXN + 3]; bool vis[MAXN + 3]; bool color[MAXN + 3]; vector<int> ans[2], curr, output; int counter; void Read() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int a, b, c; char col; scanf( %d %d %c , &a, &b, &col); if (col == B ) c = 1; else c = 0; graph[a].push_back(make_pair(b, c)); graph[b].push_back(make_pair(a, c)); } } void Clean() { for (int i = 1; i <= n; i++) vis[i] = false; for (int i = 1; i <= n; i++) color[i] = 0; for (int i = 1; i <= n; i++) for (int j = 0; j < (int)graph[i].size(); j++) graph[i][j].second = (graph[i][j].second + 1) % 2; curr.clear(); } bool Dfs(int v) { vis[v] = true; curr.push_back(v); if (color[v] == 0) counter++; for (int i = 0; i < (int)graph[v].size(); i++) { int u = graph[v][i].first; int sum = graph[v][i].second; if (!vis[u]) { color[u] = (sum - color[v] + 2) % 2; if (Dfs(u) == false) return false; } else { if (color[u] != (sum - color[v] + 2) % 2) return false; } } return true; } bool Solve(int ind) { for (int v = 1; v <= n; v++) { if (!vis[v]) { if (Dfs(v) == false) return false; } for (int i = 0; i < (int)curr.size(); i++) { if (color[curr[i]] == 0 && 2 * counter < (int)curr.size()) ans[ind].push_back(curr[i]); else if (color[curr[i]] == 1 && 2 * counter >= (int)curr.size()) ans[ind].push_back(curr[i]); } curr.clear(); counter = 0; } return true; } int main() { Read(); bool check0 = Solve(0); Clean(); bool check1 = Solve(1); if (!check0 && !check1) { puts( -1 ); return 0; } if (!check1 || (ans[0].size() < ans[1].size() && check0)) output = ans[0]; else output = ans[1]; printf( %d n , (int)output.size()); for (int i = 0; i < (int)output.size(); i++) { printf( %d , output[i]); } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Room { int length, width, height, total_length; } room[500]; struct Wallpaper { int length, width, price; } wallpaper[500]; int main() { int n, m, i, j, ans, tmp, price, ret; cin >> n; for (i = 0; i < n; ++i) { cin >> room[i].length >> room[i].width >> room[i].height; room[i].total_length = 2 * (room[i].length + room[i].width); } cin >> m; for (i = 0; i < m; ++i) cin >> wallpaper[i].length >> wallpaper[i].width >> wallpaper[i].price; for (ret = i = 0; i < n; ++i) { for (price = 500 * 500 * 500, ans = j = 0; j < m; ++j) { tmp = wallpaper[j].length / room[i].height; tmp *= wallpaper[j].width; if (tmp == 0) continue; ans = (room[i].total_length / tmp + (room[i].total_length % tmp == 0 ? 0 : 1)) * wallpaper[j].price; price = min(price, ans); } ret += price; } cout << ret << endl; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long num = 0, neg = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) neg = -1; c = getchar(); } while (isdigit(c)) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } return num * neg; } int p, lmt; int n, cnt[200010], a[200010], sum[200010]; int exs[200010], exs1[200010], ans, first[400010]; vector<int> loc; map<int, int> used; inline bool check() { int mx = 0, tot = 0; for (int i = 1; i <= n; i++) { if (cnt[i] > mx) mx = cnt[i], tot = 0, p = i; if (cnt[i] == mx) tot++; } return tot > 1; } int main() { n = read(); lmt = 400; for (int i = 1; i <= n; i++) { a[i] = read(); cnt[a[i]]++; } if (check()) { printf( %d n , n); return 0; } for (int i = 1; i <= n; i++) if (a[i] == p) loc.push_back(i); for (int u = 1; u <= n; u++) if (cnt[u] > lmt && u != p) { for (int i = 0; i <= 2 * n; i++) first[i] = n + 1; first[n] = 0, sum[0] = n; for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + (a[i] == u) - (a[i] == p); if (first[sum[i]] <= n) ans = max(ans, i - first[sum[i]]); else first[sum[i]] = i; } } vector<pair<int, int> > seg; for (int len = 1; len <= lmt + 1; len++) { seg.clear(); for (int i = 0; i < loc.size(); i++) { int j = i + len - 1; if (j >= loc.size()) break; int l = (i == 0 ? 1 : loc[i - 1] + 1), r = (j == loc.size() - 1 ? n : loc[j + 1] - 1); seg.push_back(make_pair(l, r)); } int l = 1, r = 0, mx = 0; memset(exs, 0, sizeof(exs)); memset(exs1, 0, sizeof(exs1)); for (int i = 0; i < seg.size(); i++) { while (r < seg[i].second) { mx += 2; r++; if (a[r] != p) { exs1[exs[a[r]]]--; exs[a[r]]++; exs1[exs[a[r]]]++; } while (!exs1[mx] && mx) mx--; } while (l < seg[i].first) { mx += 2; if (a[l] != p) { exs1[exs[a[l]]]--; exs[a[l]]--; exs1[exs[a[l]]]++; } l++; while (!exs1[mx] && mx) mx--; } if (mx >= len) ans = max(ans, r - l + 1); } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100110; const int maxm = 100010; char s[maxn][5]; long long sum[maxm * 4][5][11]; int n; void init() { for (int i = 1; i < maxn; i++) for (int z = 2; z <= 6; z++) { int tp = i % (2 * (z - 1)); if (tp == 0) s[i][z - 2] = 2; else if (tp <= z) s[i][z - 2] = tp; else s[i][z - 2] = 2 * z - tp; } } void build(int pos, int l, int r) { for (int i = 2; i <= 6; i++) for (int j = 0; j <= 10; j++) sum[pos][i - 2][j] = 0; if (l == r) return; int mid = (l + r) >> 1; build((pos << 1), l, mid); build(((pos << 1) | 1), mid + 1, r); } void insert(int pos, int l, int r, int i, int a) { if (i < l || i > r) return; if (l == r) { for (int z = 2; z <= 6; z++) for (int j = 0; j <= 10; j++) sum[pos][z - 2][j] = (long long)s[i + j][z - 2] * a; return; } int mid = (l + r) >> 1; insert((pos << 1), l, mid, i, a); insert(((pos << 1) | 1), mid + 1, r, i, a); for (int z = 2; z <= 6; z++) for (int j = 0; j <= 10; j++) sum[pos][z - 2][j] = sum[(pos << 1)][z - 2][j] + sum[((pos << 1) | 1)][z - 2][j]; } long long search(int pos, int l, int r, int x, int y, int z, int offset) { if (y < l || r < x) return 0; if (x <= l && r <= y) return sum[pos][z - 2][offset]; int mid = (l + r) >> 1; return search((pos << 1), l, mid, x, y, z, offset) + search(((pos << 1) | 1), mid + 1, r, x, y, z, offset); } int main() { init(); while (~scanf( %d , &n)) { build(1, 1, n); for (int i = 1; i <= n; i++) { int a; scanf( %d , &a); insert(1, 1, n, i, a); } int m; scanf( %d , &m); while (m-- > 0) { int t, p, v, l, r, z; scanf( %d , &t); if (t == 1) { scanf( %d%d , &p, &v); insert(1, 1, n, p, v); } else { scanf( %d%d%d , &l, &r, &z); int offset = 0; if (s[l][z - 2] <= s[l + 1][z - 2]) { if (s[l][z - 2] == 1) offset = 0; else offset = z - s[l][z - 2] + z - 1; } else { offset = s[l][z - 2] - 1; } cout << search(1, 1, n, l, r, z, offset) << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int x, y, a, b, r, m, t, pr; int poc, kraj, uk; int drvo[2000], sveca[2000]; void apdejt(int a, int b) { while (a <= 2000) { drvo[a] += b; a += (a & -a); } } int koliko(int a) { int zbir = 0; while (a > 0) { zbir += drvo[a]; a -= (a & -a); } return zbir; } void solve() { cin >> m >> t >> r; uk = 0; for (int i = 0; i < m; i++) { cin >> a; a += 500; if (koliko(a) >= r) continue; kraj = r - koliko(a); for (int j = 0; j < kraj; j++) { x = -1; for (int z = a - 1; z >= a - t; z--) { if (sveca[z] == 0) { sveca[z] = 1; uk++; apdejt(z, 1); apdejt(z + t + 1, -1); x = 1; break; } } if (x == -1) { cout << -1 << endl; return; } } } cout << (uk) << endl; } int main() { ios_base::sync_with_stdio(false); int t; t = 1; while (t--) { solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:16:33 03/29/2015
// Design Name:
// Module Name: aluparam
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aluparam
#( parameter BITSIZE = 16)
( output [BITSIZE-1:0] Y,
output [15:0] flags,
input [BITSIZE-1:0] A,
input [BITSIZE-1:0] B,
input [3:0] sel
);
// Carry Ripple Adder Based ALU
wire [BITSIZE-1:0] src1;
wire [BITSIZE-1:0] src2;
wire [BITSIZE-1:0] Sout;
wire [BITSIZE-1:0] Cout;
wire [BITSIZE-1:0] Cin;
wire [BITSIZE-2:0] Ors; // One less NOR gate then BITSIZE
wire ofint;
assign src1 = A;
// Flag Register contains the following.
// 0 Carry // IMPLEMENTED
// 1 Trace // NOT IMPLEMENTED
// 2 Low // IMPLEMENTED
// 3 '0' // EMPTY
// 4 '0' // EMPTY
// 5 Overflow // IMPLEMENTED
// 6 Zero // IMPLEMENTED
// 7 Negative // IMPLEMENTED
// 8 '0' // EMPTY
// 9 E // NOT IMPLEMENTED
// 10 P // NOT IMPLEMENTED
// 11 I // NOT IMPLEMENTED
// 12, 13, 14, 15 // RESERVED
and(flags[0], Cout[BITSIZE-1], !sel[3], sel[2], !sel[1], !sel[0]); // Last Carry Out. Logic operators should set this to 0.
// Also I chose subtraction to set it to 0, since we are using signed numbers.
assign flags[1] = 1'b0;
and lowflag(flags[2], !Cout[BITSIZE-1], !sel[3], sel[2], !sel[1], sel[0]); // Only set on subtraction.
assign flags[4:3] = 2'b00;
xor overflow_flag(ofint, Cout[BITSIZE-1], Cin[BITSIZE-1]); // XOR of Carry Out and Carry In of Last Bit.
and(flags[5], ofint, !sel[3], sel[2], !sel[1]); // Logic operators should set this to 0.
not zero_flag(flags[6], Ors[BITSIZE-2]); // Negate Last OR output.
assign flags[7] = Y[BITSIZE-1]; // Most Significant Bit is Sign Bit.
assign flags[15:8] = 8'b0000_0000; // Either NOT IMPLEMENTED OR 0.
// Generate SRC2 selection muxes.
genvar c;
generate
for (c=0; c < BITSIZE; c=c+1) begin : GEN_SRC2_MUX
muxparam #(.WIDTH(2), .BITSIZE(1)) src2_mux (
.y(src2[c]),
.a({!B[c],B[c]}),
.sel(sel[0])
);
end
endgenerate
// Generate 16 full adders
genvar d;
generate
for (d=0; d < BITSIZE; d=d+1) begin : GEN_FULL_ADDERS
fulladder1bit full_adders(
.S(Sout[d]),
.Cout(Cout[d]),
.A(src1[d]),
.B(src2[d]),
.Cin(Cin[d])
);
end
endgenerate
// Create first OR
or or_ripple_init(Ors[0], Y[0], Y[1]);
// Generate ORS for Zero Flag
genvar g;
generate
for (g=1; g < BITSIZE-1; g=g+1) begin : GEN_ZERO_FLAG // Note that there is one nor gate less.
or or_ripple(Ors[g], Y[g+1], Ors[g-1]);
end
endgenerate
// Create first CARRY selection mux.
muxparam #(.WIDTH(4), .BITSIZE(1)) carry_mux (
.y(Cin[0]),
.a({B[0], sel[0], 1'b1, 1'b0}),
.sel(sel[2:1])
);
// Generate remaining CARRY selection muxes.
genvar e;
generate
for (e=1; e < BITSIZE; e=e+1) begin : GEN_CARRY_MUX
muxparam #(.WIDTH(4), .BITSIZE(1)) carry_mux (
.y(Cin[e]),
.a({B[e], Cout[e-1], 1'b1, 1'b0}),
.sel(sel[2:1])
);
end
endgenerate
// Generate OUTPUT selection muxes.
genvar f;
generate
for (f=0; f < BITSIZE; f=f+1) begin : GEN_OUT_MUX
muxparam #(.WIDTH(2), .BITSIZE(1)) out_mux (
.y(Y[f]),
.a({Cout[f],Sout[f]}),
.sel(sel[3])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int solve() { int n, x; cin >> n >> x; vector<int> inp(n, 0); for (int i = 0; i < n; i++) cin >> inp[i]; for (int i = 0; i < n; i++) { if (inp[i] != x) break; if (i == (n - 1)) return 0; } for (int i = 0; i < n; i++) { if (inp[i] == x) return 1; } int dec = 0, inc = 0; for (int i = 0; i < n; i++) { if (inp[i] > x) inc += (inp[i] - x); else dec += (x - inp[i]); } if (inc == dec) return 1; else return 2; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int t; cin >> t; for (int i = 1; i <= t; i++) cout << solve() << n ; return 0; } |
#include <bits/stdc++.h> enum { N = 201 }; int n; int where[N][N]; int cnt[N] = {}; int what[N]; int set[N][N]; int sn[N] = {}; int eq(int i, int j) { int k; for (k = 0; k < n - 1; ++k) { if (where[i][k] != where[j][k]) return 0; } return 1; } int main(void) { scanf( %d , &n); int i, j, k, x; if (n == 2) { scanf( %d %d , &k, &x); printf( 1 %d n%d , x, k - 1); for (i = 0; i < k - 1; ++i) { scanf( %d , &x); printf( %d , x); } printf( n ); return 0; } int nn = n * (n - 1) / 2; for (i = 0; i < nn; ++i) { scanf( %d , &k); for (j = 0; j < k; ++j) { scanf( %d , &x); where[x][cnt[x]] = i; ++cnt[x]; } } for (i = 1; i < N; ++i) { if (cnt[i] == 0) continue; what[i] = i; for (j = 1; j < i; ++j) { if (cnt[j] == 0) continue; if (eq(j, i)) { what[i] = j; break; } } set[what[i]][sn[what[i]]] = i; ++sn[what[i]]; } for (i = 1; i < N; ++i) { if (sn[i] == 0) continue; printf( %d , sn[i]); for (j = 0; j < sn[i]; ++j) { printf( %d , set[i][j]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, s; int a[110][2]; int main() { scanf( %d %d , &n, &s); for (int i = 0; i < n; i++) { scanf( %d %d , &a[i][0], &a[i][1]); } int cnt = 0; int maxcnt = 0; int temp = 0; for (int i = 0; i < n; i++) { if ((a[i][0] == s && a[i][1] != 0) || a[i][0] > s) temp++; else cnt = 100 - a[i][1]; if (cnt > maxcnt && cnt < 100) { maxcnt = cnt; } cnt = 0; } if (temp == n) printf( -1 n ); else printf( %d n , maxcnt); return 0; } |
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main (
output v6e100e,
output v0b941e,
output v2a3480
);
wire w0;
wire w1;
wire w2;
assign v0b941e = w0;
assign v6e100e = w1;
assign v2a3480 = w2;
vfebcfe v7dc4a3 (
.v9fb85f(w0)
);
vfebcfe va834d8 (
.v9fb85f(w1)
);
vd30ca9 v9ceafe (
.v9fb85f(w2)
);
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module pixelq_op_CONTROL_BUS_if
#(parameter
C_ADDR_WIDTH = 5,
C_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESETN,
input wire [C_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_DATA_WIDTH-1:0] WDATA,
input wire [C_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire [31:0] I_rows,
output wire [31:0] I_cols,
output wire I_ap_start,
input wire O_ap_ready,
input wire O_ap_done,
input wire O_ap_idle
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : reserved
// 0x14 : Data signal of rows
// bit 31~0 - rows[31:0] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of cols
// bit 31~0 - cols[31:0] (Read/Write)
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
// address bits
localparam
ADDR_BITS = 5;
// address
localparam
ADDR_AP_CTRL = 5'h00,
ADDR_GIE = 5'h04,
ADDR_IER = 5'h08,
ADDR_ISR = 5'h0c,
ADDR_ROWS_CTRL = 5'h10,
ADDR_ROWS_DATA_0 = 5'h14,
ADDR_COLS_CTRL = 5'h18,
ADDR_COLS_DATA_0 = 5'h1c;
// axi write fsm
localparam
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2;
// axi read fsm
localparam
RDIDLE = 2'd0,
RDDATA = 2'd1;
//------------------------Local signal-------------------
// axi write
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
// axi read
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire ap_idle;
reg ap_done;
wire ap_ready;
reg ap_start;
reg auto_restart;
reg gie;
reg [1:0] ier;
reg [1:0] isr;
reg [31:0] _rows;
reg [31:0] _cols;
//------------------------Body---------------------------
//++++++++++++++++++++++++axi write++++++++++++++++++++++
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (~ARESETN)
wstate <= WRIDLE;
else
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi read+++++++++++++++++++++++
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (~ARESETN)
rstate <= RDIDLE;
else
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= ap_start;
rdata[1] <= ap_done;
rdata[2] <= ap_idle;
rdata[3] <= ap_ready;
rdata[7] <= auto_restart;
end
ADDR_GIE: begin
rdata <= gie;
end
ADDR_IER: begin
rdata <= ier;
end
ADDR_ISR: begin
rdata <= isr;
end
ADDR_ROWS_DATA_0: begin
rdata <= _rows[31:0];
end
ADDR_COLS_DATA_0: begin
rdata <= _cols[31:0];
end
endcase
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++internal registers+++++++++++++
assign interrupt = gie & (|isr);
assign I_ap_start = ap_start;
assign ap_idle = O_ap_idle;
assign ap_ready = O_ap_ready;
assign I_rows = _rows;
assign I_cols = _cols;
// ap_start
always @(posedge ACLK) begin
if (~ARESETN)
ap_start <= 1'b0;
else if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
ap_start <= 1'b1;
else if (O_ap_ready)
ap_start <= auto_restart; // clear on handshake/auto restart
end
// ap_done
always @(posedge ACLK) begin
if (~ARESETN)
ap_done <= 1'b0;
else if (O_ap_done)
ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
ap_done <= 1'b0; // clear on read
end
// auto_restart
always @(posedge ACLK) begin
if (~ARESETN)
auto_restart <= 1'b0;
else if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
auto_restart <= WDATA[7];
end
// gie
always @(posedge ACLK) begin
if (~ARESETN)
gie <= 1'b0;
else if (w_hs && waddr == ADDR_GIE && WSTRB[0])
gie <= WDATA[0];
end
// ier
always @(posedge ACLK) begin
if (~ARESETN)
ier <= 1'b0;
else if (w_hs && waddr == ADDR_IER && WSTRB[0])
ier <= WDATA[1:0];
end
// isr[0]
always @(posedge ACLK) begin
if (~ARESETN)
isr[0] <= 1'b0;
else if (ier[0] & O_ap_done)
isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
isr[0] <= isr[0] ^ WDATA[0]; // toggle on write
end
// isr[1]
always @(posedge ACLK) begin
if (~ARESETN)
isr[1] <= 1'b0;
else if (ier[1] & O_ap_ready)
isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
isr[1] <= isr[1] ^ WDATA[1]; // toggle on write
end
// _rows[31:0]
always @(posedge ACLK) begin
if (w_hs && waddr == ADDR_ROWS_DATA_0)
_rows[31:0] <= (WDATA[31:0] & wmask) | (_rows[31:0] & ~wmask);
end
// _cols[31:0]
always @(posedge ACLK) begin
if (w_hs && waddr == ADDR_COLS_DATA_0)
_cols[31:0] <= (WDATA[31:0] & wmask) | (_cols[31:0] & ~wmask);
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
|
// adapter from DDR3 interface to 64-bit CS1 burst interface
module ddr3_eim_cs1(
input wire clk,
input wire [63:0] ctl,
input wire ctl_stb, // strobes when control register updated
output wire [63:0] burst_rd,
input wire rd_stb, // strobes when burst read register has been accessed
output wire [63:0] status,
output wire [2:0] ddr3_rd_cmd,
output wire [5:0] ddr3_rd_bl,
output wire [29:0] ddr3_rd_adr,
output wire ddr3_rd_cmd_en,
input wire ddr3_rd_cmd_empty,
input wire ddr3_rd_cmd_full,
input wire [31:0] ddr3_rd_data,
input wire [6:0] ddr3_rd_count,
input wire ddr3_rd_empty,
input wire ddr3_rd_full,
output reg ddr3_rd_en,
input wire reset
);
reg [29:0] cmd_adr;
reg [4:0] num_pkts; // 256 byte queue max, 8-byte packets = 32 max packet request
reg [4:0] outstanding;
reg [63:0] rd_cache;
reg cmd_go;
reg reset_errors;
reg cmd_err;
reg [7:0] readcount;
assign burst_rd[63:0] = rd_cache[63:0];
assign status = {readcount,
3'b0,cmd_err,
ddr3_rd_cmd_empty, ddr3_rd_cmd_full, ddr3_rd_empty, ddr3_rd_full,
1'b0, ddr3_rd_count[6:0]};
// readcount helps sanity-check i.MX6 errors. Sometimes the compiler will kick out
// integer (32-bit) reads and double the read count. Read count should equal packet request count.
always @(posedge clk) begin
if( ctl_stb ) begin
readcount <= 8'b0;
end else if( rd_stb ) begin
readcount <= readcount + 8'b1;
end else begin
readcount <= readcount;
end
end
always @(posedge clk) begin
if( ctl_stb ) begin
cmd_adr <= ctl[29:0];
num_pkts <= ctl[36:32]; // specified in 64-bit increments, up to 32 packets; 0 = no transaction
end else begin
cmd_adr <= cmd_adr;
num_pkts <= num_pkts;
end
cmd_go <= ctl_stb && (ctl[36:32] != 5'b0);
end
assign ddr3_rd_cmd = 3'b001; // always read
assign ddr3_rd_adr = {cmd_adr[29:2],2'b00}; // passed through from host, snapped to 32-bit boundary
assign ddr3_rd_bl[5:0] = {num_pkts[4:0],1'b0} - 6'b1;
assign ddr3_rd_cmd_en = cmd_go; // always assume we have space in cmd fifo
parameter READ_IDLE = 6'b1 << 0;
parameter READ_PENDING = 6'b1 << 1;
parameter READ_FETCH = 6'b1 << 2;
parameter READ_UPDATE_LSB = 6'b1 << 3;
parameter READ_UPDATE_MSB = 6'b1 << 4;
parameter READ_WAIT = 6'b1 << 5;
parameter READ_nSTATES = 6;
reg [(READ_nSTATES - 1):0] cstate;
reg [(READ_nSTATES - 1):0] nstate;
always @(posedge clk) begin
cstate <= nstate;
end
// state evolution
always @(*) begin
case(cstate)
// starting assumptions:
// - rd_cache is invalid
// - no burst read is pending
READ_IDLE: begin
if( cmd_go ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_IDLE;
end
end
READ_PENDING: begin
if( outstanding != 5'b0 ) begin
if( ddr3_rd_count[6:0] < 7'b10 ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_FETCH;
end
end else begin
nstate <= READ_IDLE;
end
end // case: READ_PENDING
READ_FETCH: begin
nstate <= READ_UPDATE_LSB;
end
READ_UPDATE_LSB: begin
nstate <= READ_UPDATE_MSB;
end
READ_UPDATE_MSB: begin
nstate <= READ_WAIT;
end
READ_WAIT: begin
if( rd_stb ) begin // min 30 bclk cycles between read strobes, so plenty of time to cycle back
nstate <= READ_PENDING;
end else begin
nstate <= READ_WAIT;
end
end
default: begin
nstate <= READ_IDLE;
end
endcase // case (cstate)
end // always @ (*)
// state output
always @(posedge clk) begin
case(cstate)
READ_IDLE: begin
outstanding[4:0] <= num_pkts[4:0];
rd_cache <= rd_cache;
if( ddr3_rd_count[6:0] > 7'b0 ) begin
ddr3_rd_en <= 1'b1; // discard any mismatch/overruns
end else begin
ddr3_rd_en <= 1'b0;
end
end
READ_PENDING: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
READ_FETCH: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_LSB: begin
outstanding <= outstanding;
rd_cache[63:0] <= {rd_cache[63:32],ddr3_rd_data[31:0]};
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_MSB: begin
outstanding <= outstanding - 5'b1;
rd_cache[63:0] <= {ddr3_rd_data[31:0],rd_cache[31:0]};
// rd_cache[63:0] <= {ddr3_rd_data[31:0] + 32'hbabe1234,rd_cache[31:0]};
ddr3_rd_en <= 1'b0;
end
READ_WAIT: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
default: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
endcase // case (cstate)
end
// catch and track errors -- we assume that cmd fifo always has space for us in this implementation
// make sure we catch when this fails
always @(posedge clk) begin
reset_errors <= ctl[63];
if( reset_errors ) begin
cmd_err <= 1'b0;
end else begin
if( cmd_go && ddr3_rd_cmd_full ) begin
cmd_err <= 1'b1;
end else begin
cmd_err <= cmd_err;
end
end
end // always @ (posedge clk)
endmodule // ddr3_eim_cs1
|
//////////////////////////////////////////////////////////////////////////////
//
// Module: nf2_dma_sync.v
// Project: NetFPGA 2.1 (NF2 Control Network FPGA)
// Description: DMA synchronizer
//
// Provides signal synchronization between CPCI clk domain and
// system clk domain
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// txfifo_rd_data includes:
// 1 bit. 1'b 0 for "data format"; 1'b 1 for "req format"
// 1 bit. EOP in "data format". 1'b 1 indicates the last pkt word.
// 1'b 0 indicates this is not the last pkt word.
// in "req format", 1'b 0 for "dma tx", 1'b 1 for "dma rx"
// 2 bits. bytecnt in "data format". 2'b 00: 4 bytes; 2'b 01: 1 byte;
// 2'b 10: 2 bytes; 2'b 11: 3 bytes.
// always 2'b 00 in "req format"
// 32 bits. pkt data in "data format".
// {28'b 0, 4-bits queue_id} in "req format"
//
// rxfifo_wr_data includes:
// 1 bit. EOP. 1'b 1 indicates the last pkt word.
// 1'b 0 indicates this is not the last pkt word.
// 2 bits. bytecnt. 2'b 00: 4 bytes; 2'b 01: 1 byte;
// 2'b 10: 2 bytes; 2'b 11: 3 bytes.
// 32 bits. pkt data .
//
///////////////////////////////////////////////////////////////////////////////
module nf2_dma_sync
#(parameter DMA_DATA_WIDTH = 32,
parameter NUM_CPU_QUEUES = 4)
(
// -- signals from/to bus FSM
output reg [NUM_CPU_QUEUES-1:0] cpci_cpu_q_dma_pkt_avail,
output reg [NUM_CPU_QUEUES-1:0] cpci_cpu_q_dma_nearly_full,
output cpci_txfifo_full,
output cpci_txfifo_nearly_full,
input cpci_txfifo_wr,
input [DMA_DATA_WIDTH +3:0] cpci_txfifo_wr_data,
output cpci_rxfifo_empty,
input cpci_rxfifo_rd_inc,
output [DMA_DATA_WIDTH +2:0] cpci_rxfifo_rd_data,
// --- signals from/to NetFPGA core logic
input [NUM_CPU_QUEUES-1:0] sys_cpu_q_dma_pkt_avail,
input [NUM_CPU_QUEUES-1:0] sys_cpu_q_dma_nearly_full,
output sys_txfifo_empty,
output [DMA_DATA_WIDTH +3:0] sys_txfifo_rd_data,
input sys_txfifo_rd_inc,
output sys_rxfifo_full,
output sys_rxfifo_nearly_full,
input sys_rxfifo_wr,
input [DMA_DATA_WIDTH +2:0] sys_rxfifo_wr_data,
//clks and resets
input cpci_clk,
input cpci_reset,
input sys_clk,
input sys_reset
);
reg [NUM_CPU_QUEUES-1:0] cpci_sync_cpu_q_dma_pkt_avail;
reg [NUM_CPU_QUEUES-1:0] cpci_sync_cpu_q_dma_nearly_full;
always @(posedge cpci_clk)
if (cpci_reset) begin
cpci_sync_cpu_q_dma_pkt_avail <= 'h 0;
cpci_sync_cpu_q_dma_nearly_full <= 'h 0;
cpci_cpu_q_dma_pkt_avail <= 'h 0;
cpci_cpu_q_dma_nearly_full <= 'h 0;
end
else begin
cpci_sync_cpu_q_dma_pkt_avail <= sys_cpu_q_dma_pkt_avail;
cpci_sync_cpu_q_dma_nearly_full <= sys_cpu_q_dma_nearly_full;
cpci_cpu_q_dma_pkt_avail <= cpci_sync_cpu_q_dma_pkt_avail;
cpci_cpu_q_dma_nearly_full <= cpci_sync_cpu_q_dma_nearly_full;
end
//---------------------------------------
// Instantiations
small_async_fifo #(.DSIZE(DMA_DATA_WIDTH +4),
.ASIZE(3),
.ALMOST_FULL_SIZE(5),
.ALMOST_EMPTY_SIZE(3))
tx_async_fifo (
//wr interface
.wfull ( cpci_txfifo_full ),
.w_almost_full ( cpci_txfifo_nearly_full ),
.wdata ( cpci_txfifo_wr_data ),
.winc ( cpci_txfifo_wr ),
.wclk ( cpci_clk ),
.wrst_n ( ~cpci_reset ),
//rd interface
.rdata ( sys_txfifo_rd_data ),
.rempty ( sys_txfifo_empty ),
.r_almost_empty ( ),
.rinc ( sys_txfifo_rd_inc ),
.rclk ( sys_clk ),
.rrst_n ( ~sys_reset )
);
small_async_fifo #(.DSIZE(DMA_DATA_WIDTH +3),
.ASIZE(3),
.ALMOST_FULL_SIZE(5),
.ALMOST_EMPTY_SIZE(3))
rx_async_fifo (
//wr interface
.wfull ( sys_rxfifo_full ),
.w_almost_full ( sys_rxfifo_nearly_full ),
.wdata ( sys_rxfifo_wr_data ),
.winc ( sys_rxfifo_wr ),
.wclk ( sys_clk ),
.wrst_n ( ~sys_reset ),
//rd interface
.rdata ( cpci_rxfifo_rd_data ),
.rempty ( cpci_rxfifo_empty ),
.r_almost_empty ( ),
.rinc ( cpci_rxfifo_rd_inc ),
.rclk ( cpci_clk ),
.rrst_n ( ~cpci_reset )
);
endmodule // nf2_dma_sync
|
/* -------------------------------------------------------------------------------
* Physical cgannel (PC) allocator
* Allocates new physical-channels in the destination trunk
* for newly arrived packets.
*
* "unrestricted" allocation (Peh/Dally style)
*
* Takes place in two stages:
*
* stage 1. ** Physical channel selection **
* Each waiting packet determines which PC it will request.
* (v:1 arbitration).
*
*
* stage 2. ** PC Allocation **
* Access to each output PC is arbitrated (PV x PV:1 arbiters)
*
*/
`include "types.v"
module LAG_pl_unrestricted_allocator (req, // PC request
output_port, // for which trunk?
pl_status, // which PCs are free
pl_new, // newly allocated PC id.
pl_new_valid, // has new PC been allocated?
pl_allocated, // change PC status from free to allocated?
clk, rst_n);
// `include "LAG_functions.v";
parameter buf_len = 4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter alloc_stages = 1;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] pl_status;
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
output [np-1:0][nv-1:0] pl_allocated;
input clk, rst_n;
genvar i,j,k,l;
logic [np-1:0][nv-1:0][nv-1:0] stage1_request, stage1_grant, stage1_grant_reg;
logic [np-1:0][nv-1:0][nv-1:0] selected_status;
logic [np-1:0][nv-1:0][np-1:0][nv-1:0] stage2_requests, stage2_requests_, stage2_grants;
logic [np-1:0][nv-1:0][nv-1:0][np-1:0] pl_new_;
output_port_t output_port_reg [np-1:0][nv-1:0];
generate
for (i=0; i<np; i++) begin:foriports
for (j=0; j<nv; j++) begin:forpls
if (alloc_stages == 2) begin
//
// Select PL status bits at output port of interest (determine which PLs are free to be allocated)
//
assign selected_status[i][j] = pl_status[oh2bin(output_port[i][j])];
//
// Requests for PL selection arbiter
//
// Narrows requests from all possible PLs that could be requested to 1
//
for (k=0; k<nv; k++) begin:forpls2
// Request is made if
// (1) Packet requires PL
// (2) PL Mask bit is set
// (3) PL is currently free, so it can be allocated
//
assign stage1_request[i][j][k] = req[i][j] && selected_status[i][j][k] && ~(|stage1_grant_reg[i][j]);
end
always @(posedge clk) begin
if (!rst_n) begin
stage1_grant_reg[i][j] <= '0;
output_port_reg[i][j] <= '0;
end else begin
stage1_grant_reg[i][j] <= stage1_grant[i][j];
output_port_reg[i][j] <= output_port[i][j];
end
end
//
// second-stage of arbitration, determines who gets PL
//
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant_reg[i][j][l] && output_port_reg[i][j][k];
assign stage2_requests_[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
assign pl_allocated[i][j] = |(stage2_requests_[i][j]);
end else if (alloc_stages == 1) begin
assign selected_status[i][j] = pl_status[oh2bin(output_port[i][j])];
for (k=0; k<nv; k++) begin:forpls2
assign stage1_request[i][j][k] = req[i][j] && selected_status[i][j][k];
end
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
assign pl_allocated[i][j] = |(stage2_requests[i][j]);
end else begin
//$display("Error: parameter <alloc_stages> can obtain only (1) or (2) values!");
//$finish;
end
//
// first-stage of arbitration
//
// Arbiter state doesn't mean much here as requests on different clock cycles may be associated
// with different output ports. plselect_arbstateupdate determines if state is always or never
// updated.
//
//This stage determines one of free physical channel in te destination trunk
//for each input physical channel that form request
matrix_arb #(.size(nv), .multistage(1))
stage1arb
(.request(stage1_request[i][j]),
.grant(stage1_grant[i][j]),
.success((plselect_arbstateupdate==1)),
.clk, .rst_n);
//Second stage of arbitration. Eaxh output PC has one np*nv:1 arbiter
//
// np*nv np*nv:1 tree arbiters
//
LAG_tree_arbiter #(.multistage(0),
.size(np*nv),
.groupsize(nv)) plarb
(.request(stage2_requests[i][j]),
.grant(stage2_grants[i][j]),
.clk, .rst_n);
for (k=0; k<np; k++) begin:fo2
for (l=0; l<nv; l++) begin:fv2
// could get pl x from any one of the output ports
assign pl_new_[i][j][l][k]=stage2_grants[k][l][i][j];
end
end
for (l=0; l<nv; l++) begin:fv3
assign pl_new[i][j][l]=|pl_new_[i][j][l];
end
assign pl_new_valid[i][j]=|pl_new[i][j];
end
end
endgenerate
endmodule // LAG_pl_unrestricted_allocator
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; int n, m, a[N], b[N]; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > Q; long long ans; int solve(int x) { ans = 0; int num = 0; for (int i = (int)(1); i <= (int)(n); i++) { Q.push(pair<long long, long long>(a[i], 0)); long long t = Q.top().first, now = b[i] - x; if (now + t < 0) { ans += now + t; Q.pop(); Q.push(pair<long long, long long>(-now, 1)); } } for (; !Q.empty(); num += Q.top().second, Q.pop()) ; return num; } int main() { scanf( %d%d , &n, &m); for (int i = (int)(1); i <= (int)(n); i++) scanf( %d , &a[i]); for (int i = (int)(1); i <= (int)(n); i++) scanf( %d , &b[i]); long long l = 0, r = 2e9; while (l <= r) { long long mid = (l + r) / 2; int sum = solve(mid); if (sum == m) { printf( %lld n , ans + 1ll * m * mid); return 0; } if (sum < m) l = mid + 1; else r = mid - 1; } } |
#include <bits/stdc++.h> using namespace std; void fun(long long int n) { int count = 0; while (n) { if (n % 10 == 7 || n % 10 == 4) count++; n = n / 10; } if (count == 0) { cout << NO ; return; } while (count) { int r = count % 10; if (r != 7 && r != 4) { cout << NO ; return; } count = count / 10; } cout << YES ; return; } int main() { long long int n; cin >> n; fun(n); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; using LL = long long; using pss = pair<string, string>; using pis = pair<int, string>; const int maxn = 300300; int n; LL val[maxn], mask[maxn], sum; signed main() { while (cin >> n) { sum = 0; for (int i = 1; i <= n; i++) { cin >> val[i] >> mask[i]; sum += val[i]; } for (int i = 1; i <= n; i++) { if (sum < 0) { val[i] = -val[i]; } } LL ret = 0; for (int k = 0; k < 62; k++) { LL tot = 0; for (int i = 1; i <= n; i++) { if (mask[i] == (1LL << k)) { tot += val[i]; } } if (tot > 0) ret |= (1LL << k); for (int i = 1; i <= n; i++) { if ((1LL << k) & mask[i]) { mask[i] ^= (1LL << k); if (tot > 0) { val[i] = -val[i]; } } } } cout << ret << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int dx[] = {1, 0, -1, 0}, dy[] = {0, 1, 0, -1}; int n, m, gx, gy, len, vis[15][15], ucs; inline bool out(int x, int y) { return x < 0 || x >= n || y < 0 || y >= m; } char s[15][15 + 1]; struct P { int x[9], y[9], step, h; P() { step = 0; } void cal_h() { h = step + abs(gx - x[0]) + abs(gy - y[0]); } int get_hsh() { int hsh = 0; for (int i = 0; i < len; i++) hsh = hsh * 131 + x[i] + 1; for (int i = 0; i < len; i++) hsh = hsh * 131 + y[i] + 1; return hsh; } bool operator<(const P &p) const { return h > p.h; } }; int vc[15][15]; bool chk(int x, int y) { vc[x][y] = 1; if (s[x][y] == @ ) return 1; for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (out(nx, ny) || vc[nx][ny] || s[nx][ny] == # ) continue; if (chk(nx, ny)) return 1; } return 0; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (s[i][j] == @ ) gx = i, gy = j; P p, np; for (int i = 1; i <= 9; i++) for (int j = 0; j < n; j++) for (int k = 0; k < m; k++) if (s[j][k] == 0 + i) { p.x[len] = j; p.y[len] = k; len++; } if (!chk(p.x[0], p.y[0])) return puts( -1 ), 0; set<int> vs; priority_queue<P> q; p.cal_h(); q.push(p); vs.insert(p.get_hsh()); while (!q.empty()) { p = q.top(); q.pop(); ucs++; for (int i = 0; i < len - 1; i++) vis[p.x[i]][p.y[i]] = ucs; for (int i = 0; i < 4; i++) { int hx = p.x[0] + dx[i], hy = p.y[0] + dy[i]; if (out(hx, hy)) continue; if (vis[hx][hy] == ucs) continue; if (s[hx][hy] == # ) continue; if (s[hx][hy] == @ ) return printf( %d n , p.step + 1), 0; np.x[0] = hx; np.y[0] = hy; np.step = p.step + 1; memcpy(np.x + 1, p.x, (len - 1) * sizeof(int)); memcpy(np.y + 1, p.y, (len - 1) * sizeof(int)); if (vs.count(np.get_hsh())) continue; vs.insert(np.get_hsh()); np.cal_h(); q.push(np); } } puts( -1 ); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v2_0_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 10; const long long inf = 1e15; const int mod = 1e6; void faster() { ios_base::sync_with_stdio(false); cin.tie(NULL); } const long long N = 3e5 + 10; int n, m; long long a[N]; int main() { faster(); cin >> n; if (n % 10 < 10 - (n % 10)) cout << n - n % 10 << endl; else cout << n + (10 - (n % 10)) << endl; } |
#include<bits/stdc++.h> #define ll long long #define ri register int #define lowbit(x) x&(-x) #define lson rt<<1, l, mid #define rson rt<<1|1, mid+1, r using namespace std; const int p = 1e9+7; const int maxn = 4e5+10; int n, m, t, q; int a[maxn], vis[maxn], go[maxn], two; int dp[maxn][30]; void divide(int x, int k){ int t = sqrt(x); for(int i = 2;i <= t;i ++){ if(x%i == 0){ vis[i] += k; if(vis[i] == 1 && k == -1) two --; else if(vis[i] >= 2) two ++; while(x%i == 0) x /= i; } } if(x > 1){ vis[x] += k; if(vis[x] == 1 && k == -1) two --; else if(vis[x] >= 2) two ++; } } int main(){ scanf( %d%d ,&n,&q); for(int i = 1;i <= n;i ++) scanf( %d ,&a[i]); int l = 1, r = 0; while(r < n){ r ++; divide(a[r], 1); if(two){ go[l] = r; while(two){ divide(a[l], -1); l ++; go[l] = r; } } } for(int i = l;i <= n+1;i ++) go[i] = n+1; for(int i = 1;i <= n;i ++){ dp[i][0] = go[i]; } for(int j = 1;j <= 20;j ++) for(int i = 1;i <= n+1;i ++){ if(dp[dp[i][j-1]][j-1]) dp[i][j] = dp[dp[i][j-1]][j-1]; else dp[i][j] = n+1; } for(int i = 1;i <= q;i ++){ int l, r; ll ans = 0; scanf( %d%d ,&l,&r); for(int j = 20;j >= 0;j --){ //cout << l << << j << << dp[l][j] << endl; if(dp[l][j] <= r){ l = dp[l][j]; ans += 1ll<<j; } } printf( %lld n ,ans+1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 1e5 + 1, mod = 1000000007; vector<long long int> adj[N]; signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int pro = 1, temp, t, n, i, m, k, j, l, r, mid, x, y, z, rem, carry = 0, ind, ans = 0, mx = -LONG_LONG_MAX, mn = LONG_LONG_MAX, cnt = 0, curr = 0, prev, sum = 0, flag = 0, i1 = -1, i2 = -1; cin >> n >> m; for (i = 1; i <= m; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } if (n < 2 || m >= (n * (n - 1)) / 2) { return cout << NO , 0; } cout << YES n ; long long int a[n + 1], b[n + 1]; for (i = 1; i <= n; i++) { b[i] = 1; } curr = 2; for (i = 1; i <= n; i++) { flag = 0; for (auto it : adj[i]) { if (b[it] == b[i]) { flag = 1; b[it] = curr; } } if (flag) { curr++; } } vector<pair<long long int, long long int> > v; v.push_back({-1, 0}); for (i = 1; i <= n; i++) { v.push_back({b[i], i}); } sort(v.begin(), v.end()); for (i = 1; i <= n; i++) { a[v[i].second] = i; } for (i = 1; i <= n; i++) { cout << a[i] << ; } cout << endl; for (i = 1; i <= n; i++) { cout << b[i] << ; } return 0; } |
module SSDS_misr #(parameter n = 32)
(input
clock,
reset,
enable,
input [n-1:0]
poly,
seed,
in,
output
reg [n-1:0] out
);
integer i;
reg [n-1:0] prev_out;
always @(posedge clock, posedge reset) begin
if (reset == 1'b1)
out <= seed;
else if (^in === 1'bx)
out <= prev_out;
else if (enable == 1'b1 && ^in !== 1'bx) begin
out[n-1] <= (out[0] & poly [n-1]) ^ in[n-1];
for(i=0; i < n-1; i=i+1) begin
out[i] <= (out[0]&poly[i]) ^ in[i] ^ out[i+1];
end
end
end
always @(out) begin
prev_out <= out;
end
endmodule
/*module SSDS_misr #(parameter n = 32)
(input
clock,
reset,
enable,
inlen,
input [n-1:0]
poly,
seed,
in,
output
reg [n-1:0] out
);
integer i;
always @(posedge clock, posedge reset) begin
if (reset == 1'b1)
out <= seed;
else if (enable == 1'b1) begin
out[n-1] <= (out[0] & poly [n-1]) ^ in[n-1];
for(i=0; i < n-1; i=i+1) begin
out[i] <= (out[0]&poly[i]) ^ in[i] ^ out[i+1];
end
end
end
endmodule*/
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; struct ST { int l, r, mx, c; } t[N << 2]; int n, k, m, nn, tot, R, sum; int ls[N], rs[N], a[N], rk[N], sa[N], h[N], tp[N], tax[N], f[N][18], lg[N], tag[N], len[N], num[N]; long long ans[N]; char s[N]; void rsort() { int i; for (i = 0; i <= m; i++) tax[i] = 0; for (i = 1; i <= n; i++) tax[rk[tp[i]]]++; for (i = 1; i <= m; i++) tax[i] += tax[i - 1]; for (i = n; i >= 1; i--) sa[tax[rk[tp[i]]]--] = tp[i]; } void suffix() { int i; for (i = 1; i <= n; i++) rk[i] = a[i], tp[i] = i; m = tot; rsort(); for (int w = 1, p = 0; p < n; w += w, m = p) { p = 0; for (i = n - w + 1; i <= n; i++) tp[++p] = i; for (i = 1; i <= n; i++) if (sa[i] > w) tp[++p] = sa[i] - w; rsort(); swap(rk, tp); rk[sa[1]] = p = 1; for (i = 2; i <= n; i++) if (tp[sa[i]] == tp[sa[i - 1]] && tp[sa[i] + w] == tp[sa[i - 1] + w]) rk[sa[i]] = p; else rk[sa[i]] = ++p; } } void height() { int i, j = 0, k = 0; for (i = 1; i <= n; i++) rk[sa[i]] = i; for (i = 1; i <= n; i++) { if (k) k--; if (rk[i] == 1) continue; j = sa[rk[i] - 1]; while (a[j + k] == a[i + k]) k++; h[rk[i]] = k; } } void build(int k, int l, int r) { t[k].l = l; t[k].r = r; t[k].mx = 0; t[k].c = 0; if (l == r) return; int mid = (l + r) >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); } void add(int k, int w) { t[k].mx = max(t[k].mx, w); t[k].c = max(t[k].c, w); } void pushdown(int k) { if (t[k].c) { add(k << 1, t[k].c); add(k << 1 | 1, t[k].c); t[k].c = 0; } } void modify(int k, int L, int R, int w) { if (L <= t[k].l && t[k].r <= R) { add(k, w); return; } pushdown(k); int mid = (t[k].l + t[k].r) >> 1; if (L <= mid) modify(k << 1, L, R, w); if (R > mid) modify(k << 1 | 1, L, R, w); } int query(int k, int p) { if (t[k].l == t[k].r) return t[k].mx; pushdown(k); int mid = (t[k].l + t[k].r) >> 1; if (p <= mid) return query(k << 1, p); else return query(k << 1 | 1, p); } void init() { int i, j; for (i = 1; i <= n; i++) f[i][0] = h[i]; for (i = 1; i <= n; i++) lg[i] = log2(i); for (i = 1; i <= 17; i++) for (j = 1; j + (1 << i) - 1 <= n; j++) f[j][i] = min(f[j][i - 1], f[j + (1 << i - 1)][i - 1]); } int rmq(int l, int r) { l = rk[l]; r = rk[r]; if (l > r) swap(l, r); l++; if (l > r) return len[sa[r]]; int d = lg[r - l + 1]; return min(f[l][d], f[r - (1 << d) + 1][d]); } void solve() { int i, l1, r1 = 0, l2 = 0, r2 = 0; build(1, 1, n); for (l1 = 1; l1 <= n; l1++) { if (!tag[sa[l1]]) continue; if (l1 > 1) { num[tag[sa[l1 - 1]]]--; if (!num[tag[sa[l1 - 1]]] && tag[sa[l1 - 1]]) sum--; } while (r1 < n && sum < k) { r1++; if (!num[tag[sa[r1]]] && tag[sa[r1]]) sum++; num[tag[sa[r1]]]++; } if (sum < k) break; modify(1, l1, r1, rmq(sa[l1], sa[r1])); if (l2 > 0) for (i = r2 + 1; i <= r1; i++) modify(1, i, i, rmq(sa[l2], sa[i])); l2 = l1; r2 = r1; } if (r2 < n && l2 > 0) for (i = r2 + 1; i <= n; i++) modify(1, i, i, rmq(sa[l2], sa[i])); } int main() { int i, j; scanf( %d%d , &nn, &k); tot = 26; for (i = 1; i <= nn; i++) { scanf( %s , s + 1); m = strlen(s + 1); ls[i] = n + 1; for (j = 1; j <= m; j++) { a[++n] = s[j] - a + 1; tag[n] = i; len[n] = m - j + 1; } rs[i] = n; if (i < nn) a[++n] = ++tot; if (k == 1) ans[i] = 1ll * m * (m + 1) / 2; } if (k == 1) { for (i = 1; i <= nn; i++) printf( %I64d , ans[i]); return 0; } a[0] = -1; a[n + 1] = 1000000000; suffix(); height(); init(); solve(); for (i = 1; i <= n; i++) if (tag[sa[i]]) ans[tag[sa[i]]] += 1ll * query(1, i); for (i = 1; i <= nn; i++) printf( %I64d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long arr[n]; vector<long long> prime(200010); vector<long long> temp; for (long long i = 2; i <= sqrt(200010); i++) { if (prime[i] == 1) continue; for (long long j = 2; i * j < 200010; j++) prime[i * j] = 1; } for (long long i = 2; i < 200010; i++) { if (prime[i] == 0) temp.push_back(i); } for (long long i = 0; i < n; i++) cin >> arr[i]; map<long long, vector<long long> > m; for (long long i = 0; i < n; i++) { long long a = arr[i]; for (long long j = 0; j < temp.size(); j++) { if (a == 1) break; long long c = 0; if (temp[j] > sqrt(a)) { m[a].push_back(1); break; } while (a % temp[j] == 0 && a != 1) { a /= temp[j]; c++; } if (c) m[temp[j]].push_back(c); } } long long ans = 1; for (long long i = 0; i < temp.size(); i++) { if (m[temp[i]].size() < n - 1) continue; sort(m[temp[i]].begin(), m[temp[i]].end()); long long o; if (m[temp[i]].size() == n - 1) o = m[temp[i]][0]; else o = m[temp[i]][1]; while (o--) ans = ans * temp[i]; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { int n; string s, ss; cin >> s >> n; vector<pair<int, string> > v(n + 1); v[0] = make_pair(0, s); char next; while (cin.get(next)) if (next == n ) break; for (int i = 1; i <= n; ++i) { getline(cin, ss); if (ss.length() > 3) v[i] = make_pair(ss[0] - 0 , ss.substr(3)); else v[i] = make_pair(ss[0] - 0 , ); } long long val[10], len[10]; for (int i = 0; i < 10; ++i) val[i] = i, len[i] = 10; for (int i = n; i >= 0; --i) { int cu = v[i].first; string s = v[i].second; if (s.empty()) { val[cu] = 0; len[cu] = 1; continue; } long long pow = 1; long long va = 0; for (int j = s.length() - 1; j >= 0; --j) { va += ((val[(s[j] - 0 )]) * pow) % MOD; va %= MOD; pow = (pow * len[(s[j] - 0 )]) % MOD; } len[cu] = pow; val[cu] = va; } cout << val[0] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, logN = 20; const int M = 350; int d[N], h[N], floorlog[N << 1]; long long D[N], F1[N], F2[N], lft[N], rgt[N], total = 0; map<pair<int, int>, long long> st; vector<pair<int, int> > queries, q; pair<int, int> rmq1[logN][N], rmq2[logN][N]; int max(int i, int j, long long f[]) { return f[i] > f[j] ? i : j; } pair<int, int> merge(pair<int, int>& x, pair<int, int>& y, long long f[]) { if (f[x.first] > f[y.first]) { return {x.first, max(x.second, y.first, f)}; } if (x.first == y.first) { return {y.first, max(x.second, y.second, f)}; } return {y.first, max(x.first, y.second, f)}; } void make_rmq(long long f[], pair<int, int> rmq[][N], int n) { for (int i = n; i >= 1; i--) { rmq[0][i] = {i, 0}; for (int j = 1; i + (1 << j) - 1 <= n; j++) { rmq[j][i] = merge(rmq[j - 1][i], rmq[j - 1][i + (1 << (j - 1))], f); } } } pair<int, int> get(int i, int j, pair<int, int> rmq[][N], long long f[]) { int k = floorlog[j - i + 1]; return merge(rmq[k][i], rmq[k][j - (1 << k) + 1], f); } long long query(int l, int r) { pair<int, int> P = get(l, r, rmq1, F1); pair<int, int> Q = get(l, r, rmq2, F2); long long mx = 0; if (P.first != Q.first) mx = max(mx, F1[P.first] + F2[Q.first]); if (P.second != Q.first) mx = max(mx, F1[P.second] + F2[Q.first]); if (P.first != Q.second) mx = max(mx, F1[P.first] + F2[Q.second]); if (P.second != Q.second) mx = max(mx, F1[P.second] + F2[Q.second]); return mx; } int main() { for (int i = 0; (1 << i) < N; i++) for (int j = (1 << i); j < (1 << (i + 1)); j++) floorlog[j] = i; int n, m; scanf( %d , &(n)); scanf( %d , &(m)); for (int i = 1; i <= n; i++) { D[i] = D[i - 1] + d[i - 1]; scanf( %d , &(d[i])); total += d[i]; } for (int i = 1; i <= n; i++) { scanf( %d , &(h[i])); F1[i] = D[i] + 2 * h[i]; F2[i] = -D[i] + 2 * h[i]; rgt[i] = max(rgt[i - 1], D[i] + 2 * h[i]); } for (int i = n; i >= 1; i--) { lft[i] = max(lft[i + 1], total - D[i] + 2 * h[i]); } F1[0] = -1e18; F2[0] = -1e18; make_rmq(F1, rmq1, n); make_rmq(F2, rmq2, n); for (int i = 1; i <= m; i++) { int a, b; scanf( %d , &(a)); scanf( %d , &(b)); q.push_back({a, b}); if (a > b) { int l = b + 1, r = a - 1; printf( %lld n , query(l, r)); } else { long long ans = 0; if (b != n && a != 1) ans = max(ans, lft[b + 1] + rgt[a - 1]); if (b != n) ans = max(ans, query(b + 1, n)); if (a != 1) ans = max(ans, query(1, a - 1)); printf( %lld n , ans); } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbp (
RESET_B,
D ,
GATE ,
Q ,
Q_N ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input D ;
input GATE ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_V |
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests size casting of complex expressions.
module resize(output wire logic [4:0] result);
logic [6:0] a;
assign result = (5'(a + 2));
initial begin
a = 7'd39;
end
endmodule
module resize_test();
logic [4:0] result;
resize dut(result);
initial begin
#1;
if(result !== 5'd9) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int l, r, n, k, m, now, tot, all; int a[200000], s[200000]; struct fk { int num, val; bool operator==(const fk &b) { return (num + b.num == k && val == b.val); } } tp[200000]; int main() { scanf( %d%d%d , &n, &k, &m); for (int i = 1; i <= n; ++i) scanf( %d , a + i); all = 0; tp[0].num = tp[0].val = -1; for (int i = 1; i <= n; ++i) { if (a[i] == tp[all].val) { ++tp[all].num; if (tp[all].num == k) --all; } else { tp[++all].val = a[i]; tp[all].num = 1; } } n = 0; for (int i = 1; i <= all; ++i) n += tp[i].num; int p = 0; for (int i = 1; i <= all; ++i) { if (tp[i] == tp[all - i + 1]) p = i; else break; } long long ans = 0, temp; if (p >= (all + 1) / 2) { if (m % 2) for (int i = 1; i <= all; ++i) ans += tp[i].num; } else if (all % 2 == 1 && p == all / 2) { temp = m % k * tp[p + 1].num % k; if (temp % k == 0) ans = 0; else { ans = (long long)p * k; ans = ans + temp; } } else { ans = (long long)m * n; for (int i = 1; i <= p; ++i) ans -= (long long)p * k * (m - 1); ans -= (tp[p + 1].val == tp[all - p].val && tp[p + 1].num + tp[all - p].num >= k) ? (long long)k * (m - 1) : 0; } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int arr[N]; int main() { int n; memset(arr, 0, sizeof arr); cin >> n; int maxx = n; int num; for (int i = 0; i < n; i++) { cin >> num; arr[num] = -1; while (arr[maxx] == -1) { cout << maxx << ; maxx -= 1; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> xMap; map<int, int> yMap; vector<pair<int, int> > row[200005], col[200005]; int x[200005], y[200005], tmr[200005], parent[200005]; int findrep(int u) { if (parent[u] != u) parent[u] = findrep(parent[u]); return parent[u]; } void Union(int x, int y) { int px = findrep(x); int py = findrep(y); if (px != py) { parent[px] = py; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t, n, m, i, j, k; cin >> t; while (t--) { xMap.clear(); yMap.clear(); cin >> n >> k; for (i = 0; i <= n; i++) { row[i].clear(); col[i].clear(); } int id1 = 0, id2 = 0; for (i = 0; i < n; i++) { cin >> x[i] >> y[i] >> tmr[i]; if (!xMap[x[i]]) { id1++; xMap[x[i]] = id1; } if (!yMap[y[i]]) { id2++; yMap[y[i]] = id2; } row[yMap[y[i]]].push_back({x[i], i}); col[xMap[x[i]]].push_back({y[i], i}); } for (i = 1; i <= id1; i++) sort(col[i].begin(), col[i].end()); for (i = 1; i <= id2; i++) sort(row[i].begin(), row[i].end()); for (i = 0; i < n; i++) parent[i] = i; for (i = 1; i <= id1; i++) { int sz = col[i].size(); for (j = 1; j < sz; j++) { if (col[i][j].first - col[i][j - 1].first <= k) { Union(col[i][j].second, col[i][j - 1].second); } } } for (i = 1; i <= id2; i++) { int sz = row[i].size(); for (j = 1; j < sz; j++) { if (row[i][j].first - row[i][j - 1].first <= k) { Union(row[i][j].second, row[i][j - 1].second); } } } for (i = 0; i < n; i++) { j = findrep(i); tmr[j] = min(tmr[j], tmr[i]); } vector<int> tt; for (i = 0; i < n; i++) { if (findrep(i) == i) tt.push_back(tmr[i]); } sort(tt.begin(), tt.end()); int ans = -1; int sz = tt.size(); for (i = sz - 1; i >= 0; i--) { if (tt[i] <= ans) break; ans++; } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { map<pair<int, int>, int> dat; vector<pair<int, int> > p; int np; cin >> np; int res = 0; while (np--) { int x, y; cin >> x >> y; p.push_back(make_pair(x, y)); dat[make_pair(x, y)] = 1; } int sz = p.size(); for (int i = 0; i < sz; i++) for (int j = i + 1; j < sz; j++) { double x = p[i].first + p[j].first; double y = p[i].second + p[j].second; x /= 2.0; y /= 2.0; pair<int, int> tmp; if (fabs(x - int(x)) < 1e-9 && fabs(y - int(y)) < 1e-9) { tmp = make_pair(int(x), int(y)); if (dat.find(tmp) != dat.end()) res++; } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; vector<long long> dan, ans; vector<pair<long long, long long> > check; long long calc(long long st) { multiset<long long> otr; long long otv = 0; for (long long i = 0; i < dan.size(); i++) { st += dan[i]; if (dan[i] < 0) otr.insert(dan[i]); if (st < 0) { st -= *otr.begin(); otr.erase(otr.begin()); otv++; } } return otv; } int main() { long long n, m; cin >> n >> m; dan.resize(n); ans.resize(m, -1); check.resize(m, {0, 0}); for (long long i = 0; i < n; i++) { cin >> dan[i]; } for (long long i = 0; i < m; i++) { cin >> check[i].first; check[i].second = i + 1; } sort(check.begin(), check.end()); reverse(check.begin(), check.end()); long long l = 0; while (l < m) { long long l1 = l, r1 = m, mid, mida; long long now; if (ans[l1] != -1) now = ans[l1]; else { now = calc(check[l1].first); ans[l1] = now; } while (l1 + 1 != r1) { mid = (l1 + r1) / 2; if (ans[mid] != -1) mida = ans[mid]; else { mida = calc(check[mid].first); ans[mid] = mida; } if (mida > now) { r1 = mid; } else { l1 = mid; } } if (ans[l1] == -1) { ans[l1] = calc(check[l1].first); } l = l1 + 1; } long long last = -1; for (long long i = 0; i < m; i++) { if (ans[i] != -1) last = ans[i]; else ans[i] = last; } for (long long i = 0; i < m; i++) { swap(check[i].first, check[i].second); check[i].second = ans[i]; } sort(check.begin(), check.end()); for (long long i = 0; i < m; i++) { cout << check[i].second << n ; } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 50; const int LOG = 19; const int INF = 1e9; int m, p[MAXN], par[12][MAXN], nxt[MAXN], id[MAXN], ss[MAXN], ans, l[MAXN], r[MAXN]; int tt[LOG][MAXN], lc[LOG][MAXN]; string s[14]; pair<pair<int, int>, int> vec[MAXN]; int lcp(int a, int b) { int ta = a, tb = b; for (int i = LOG - 1; i >= 0 && a < nxt[ta] && b < nxt[tb]; i--) if (a + (1 << i) <= nxt[ta] && b + (1 << i) <= nxt[tb] && tt[i][a] == tt[i][b]) a += 1 << i, b += 1 << i; return a - ta; } bool ok(int sz, int ind) { int tl = ind, tr = ind; for (int w = LOG - 1; w >= 0; w--) if (tr + (1 << w) < p[m] && lc[w][tr] >= sz) tr += 1 << w; tr++; for (int w = LOG - 1; w >= 0; w--) if (tl - (1 << w) >= 0 && lc[w][tl - (1 << w)] >= sz) tl -= (1 << w); for (int i = 1; i < m; i++) if (par[i][tr] - par[i][tl] > r[i]) return false; return true; } bool ok2(int sz, int ind) { int tl = ind, tr = ind; for (int w = LOG - 1; w >= 0; w--) if (tr + (1 << w) < p[m] && lc[w][tr] >= sz) tr += 1 << w; tr++; for (int w = LOG - 1; w >= 0; w--) if (tl - (1 << w) >= 0 && lc[w][tl - (1 << w)] >= sz) tl -= (1 << w); for (int i = 1; i < m; i++) if (par[i][tr] - par[i][tl] < l[i]) return false; return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> s[0] >> m; m++; for (int i = 1; i < m; i++) cin >> s[i] >> l[i] >> r[i], p[i] = p[i - 1] + (int)s[i - 1].size(); p[m] = p[m - 1] + (int)s[m - 1].size(); for (int i = 0; i < m; i++) for (int j = 0; j < (int)s[i].size(); j++) tt[0][p[i] + j] = s[i][j]; for (int w = 1; w < LOG; w++) { for (int i = 0; i < m; i++) for (int j = 0; j < (int)s[i].size(); j++) if (j + (1 << (w - 1)) >= (int)s[i].size()) vec[p[i] + j] = {{tt[w - 1][p[i] + j], -1}, p[i] + j}; else vec[p[i] + j] = { {tt[w - 1][p[i] + j], tt[w - 1][p[i] + j + (1 << (w - 1))]}, p[i] + j}; sort(vec, vec + p[m]); for (int i = 1; i < p[m]; i++) if (vec[i].first == vec[i - 1].first) tt[w][vec[i].second] = tt[w][vec[i - 1].second]; else tt[w][vec[i].second] = i; } for (int i = 0; i < p[m]; i++) ss[i] = vec[i].second; for (int i = 0; i < m; i++) for (int j = 0; j < (int)s[i].size(); j++) id[p[i] + j] = i, nxt[p[i] + j] = p[i + 1]; for (int i = 0; i < p[m]; i++) for (int j = 1; j < m; j++) par[j][i + 1] = par[j][i] + bool(id[ss[i]] == j); for (int i = 0; i < p[m] - 1; i++) lc[0][i] = lcp(ss[i], ss[i + 1]); for (int i = 1; i < LOG; i++) for (int j = 0; j < p[m] - 1; j++) if (j + (1 << (i - 1)) >= p[m] - 1) lc[i][j] = lc[i - 1][j]; else lc[i][j] = min(lc[i - 1][j], lc[i - 1][j + (1 << (i - 1))]); int mn = 0; for (int i = 0; i < p[m]; i++) { if (id[ss[i]]) { mn = min(mn, lc[0][i]); continue; } int sz = nxt[ss[i]] - ss[i]; int cur = ss[i]; for (int w = LOG - 1; w >= 0 && cur < nxt[ss[i]]; w--) if (cur + (1 << w) <= nxt[ss[i]] && !ok(cur + (1 << w) - ss[i], i)) cur += (1 << w); int cur2 = ss[i]; for (int w = LOG - 1; w >= 0 && cur2 < nxt[ss[i]]; w--) if (cur2 + (1 << w) <= nxt[ss[i]] && ok2(cur2 + (1 << w) - ss[i], i)) cur2 += (1 << w); cur = max(cur, ss[i] + mn); ans += max(0, cur2 - cur); mn = lc[0][i]; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n & 1) cout << -1 * (n / 2 + 1) << endl; else cout << n / 2 << endl; return 0; } |
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