name string | code string | asm string | file string |
|---|---|---|---|
testing::internal::AppendUserMessage(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>> const&, testing::Message const&) | std::string AppendUserMessage(const std::string& gtest_msg,
const Message& user_msg) {
// Appends the user message if it's non-empty.
const std::string user_msg_string = user_msg.GetString();
if (user_msg_string.empty()) {
return gtest_msg;
}
if (gtest_msg.empty()) {
retu... | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x48, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdx), %rsi
leaq -0x58(%rbp), %r15
movq %r15, %rdi
callq 0x22c69
movq 0x8(%r15), %rdx
testq %rdx, %rdx
je 0x1f2d8
movq 0x8(%r14), %rax
testq %rax, %rax
je 0x1f2f3
leaq -0x28(%rbp), %r15
movq %r15, -0x10(%r... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest.cc |
testing::TestSuite::successful_test_count() const | int TestSuite::successful_test_count() const {
return CountIf(test_info_list_, TestPassed);
} | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq 0x30(%rdi), %r15
cmpq 0x38(%rdi), %r15
je 0x223c6
movq %rdi, %rbx
xorl %r14d, %r14d
movq (%r15), %rdi
callq 0x39518
movzbl %al, %eax
addl %eax, %r14d
addq $0x8, %r15
cmpq 0x38(%rbx), %r15
jne 0x223ac
jmp 0x223c9
xorl %r14d, %r14d
movl %r14d, %e... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest.cc |
testing::internal::UnitTestImpl::failed_test_count() const | int UnitTestImpl::failed_test_count() const {
return SumOverTestSuiteList(test_suites_, &TestSuite::failed_test_count);
} | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq 0xb8(%rdi), %rax
cmpq %rax, 0xc0(%rdi)
je 0x224e0
movq %rdi, %rbx
xorl %r15d, %r15d
xorl %r14d, %r14d
movq (%rax,%r15,8), %rdi
callq 0x224f2
addl %eax, %r14d
incq %r15
movq 0xb8(%rbx), %rax
movq 0xc0(%rbx), %rcx
subq %rax, %rcx
sarq $0x3, %rcx
... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest.cc |
testing::TestSuite::failed_test_count() const | int TestSuite::failed_test_count() const {
return CountIf(test_info_list_, TestFailed);
} | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq 0x30(%rdi), %r15
cmpq 0x38(%rdi), %r15
je 0x2253b
movq %rdi, %rbx
xorl %r14d, %r14d
movq (%r15), %rdi
cmpb $0x1, 0x80(%rdi)
movl $0x0, %eax
jne 0x2252c
addq $0x90, %rdi
callq 0x26182
movzbl %al, %eax
addl %eax, %r14d
addq $0x8, %r15
cmpq 0x38(%... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest.cc |
testing::UnitTest::PopGTestTrace() | GTEST_LOCK_EXCLUDED_(mutex_) {
internal::MutexLock lock(&mutex_);
impl_->gtest_trace_stack().pop_back();
} | pushq %rbp
movq %rsp, %rbp
pushq %r14
pushq %rbx
movq %rdi, %r14
leaq 0x8(%rdi), %rbx
movq %rbx, %rdi
callq 0x3b3f4
movl $0x2b8, %edi # imm = 0x2B8
addq 0x40(%r14), %rdi
callq 0x3bb6c
movq 0x8(%rax), %rcx
leaq -0x30(%rcx), %rdx
movq %rdx, 0x8(%rax)
movq -0x20(%rcx), %rdi
addq $-0x10, %rcx
cmpq %rcx, %rdi
je ... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest.cc |
testing::internal::DeathTestImpl::Passed(bool) | bool DeathTestImpl::Passed(bool status_ok) {
if (!spawned()) return false;
const std::string error_message = GetErrorLogs();
bool success = false;
Message buffer;
buffer << "Death test: " << statement() << "\n";
switch (outcome()) {
case LIVED:
buffer << " Result: failed to die.\n"
... | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x1e0, %rsp # imm = 0x1E0
cmpb $0x1, 0x28(%rdi)
jne 0x4172d
movl %esi, %r14d
movq %rdi, %rbx
movq (%rdi), %rax
leaq -0x68(%rbp), %rdi
movq %rbx, %rsi
callq *0x30(%rax)
leaq -0x28(%rbp), %rdi
callq 0x229e0
movq -0x28(%rbp), %rdi
addq... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest-death-test.cc |
testing::internal::ParseInternalRunDeathTestFlag() | InternalRunDeathTestFlag* ParseInternalRunDeathTestFlag() {
if (GTEST_FLAG_GET(internal_run_death_test).empty()) return nullptr;
// GTEST_HAS_DEATH_TEST implies that we have ::std::string, so we
// can use it here.
int line = -1;
int index = -1;
::std::vector< ::std::string> fields;
SplitString(GTEST_FLA... | pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x50, %rsp
cmpq $0x0, 0x1e9cb(%rip) # 0x64a10
je 0x46125
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
movl %eax, -0x2c(%rbp)
movl %eax, -0x28(%rbp)
xorps %xmm0, %xmm0
leaq -0x50(%rbp), %rdx
movaps %xmm0, (%rdx)
movq $0x0, 0x10(%rdx)
lea... | /alk[P]gperftools/vendor/googletest/googletest/src/gtest-death-test.cc |
lto_module_create_in_local_context | lto_module_t lto_module_create_in_local_context(const void *mem, size_t length,
const char *path) {
lto_initialize();
llvm::TargetOptions Options =
codegen::InitTargetOptionsFromCodeGenFlags(Triple());
// Create a local context. Ownership will be transferred ... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x228(%rsp)
movq %rsi, 0x220(%rsp)
movq %rdx, 0x218(%rsp)
callq 0x3ef4f0
leaq 0x78(%rsp), %rdi
xorl %esi, %esi
movl $0x38, %edx
callq 0x348990
leaq 0x78(%rsp), %rdi
callq 0x3ef5d0
leaq 0xb0(%rsp), %rdi
leaq 0x78(%rsp), %rsi
callq 0x326d200
leaq 0x78(%rsp), %rdi
call... | /lto/lto.cpp |
(anonymous namespace)::AArch64AsmParser::tryParseBTIHint(llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&) | ParseStatus AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
SMLoc S = getLoc();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
return TokError("invalid operand for instruction");
auto BTI = AArch64BTIHint::lookupBTIByName(Tok.getString());
if (!BTI)
return TokError(... | subq $0xd8, %rsp
movq %rdi, 0xc8(%rsp)
movq %rsi, 0xc0(%rsp)
movq 0xc8(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x40bcb0
movq 0x18(%rsp), %rdi
movq %rax, 0xb8(%rsp)
callq 0x40be40
movq %rax, 0xb0(%rsp)
movq 0xb0(%rsp), %rdi
movl $0x2, %esi
callq 0x40a4f0
testb $0x1, %al
jne 0x42555b
jmp 0x425599
leaq 0x88(%rsp), %rdi
le... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
(anonymous namespace)::AArch64Operand::AArch64Operand((anonymous namespace)::AArch64Operand const&) | AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand(), Ctx(o.Ctx) {
Kind = o.Kind;
StartLoc = o.StartLoc;
EndLoc = o.EndLoc;
switch (Kind) {
case k_Token:
Tok = o.Tok;
break;
case k_Immediate:
Imm = o.Imm;
break;
case k_ShiftedImm:
ShiftedImm = o.Shifte... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movups %xmm0, 0x10(%rdi)
movups %xmm0, (%rdi)
callq 0x41b2a0
movq 0x8(%rsp), %rdi
leaq 0x91676a9(%rip), %rax # 0x95a8730
movq %rax, (%rdi)
addq $0x38, %rdi
callq 0x40ad80... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
bool (anonymous namespace)::AArch64Operand::isImmInRange<1, 64>() const | bool isImmInRange() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Val = MCE->getValue();
return (Val >= N && Val <= M);
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq (%rdi), %rax
callq *0x28(%rax)
testb $0x1, %al
jne 0x467054
movb $0x0, 0x37(%rsp)
jmp 0x4670ae
movq 0x10(%rsp), %rdi
callq 0x41c110
movq %rax, %rdi
callq 0x41d9b0
movq %rax, 0x20(%rsp)
cmpq $0x0, 0x20(%rsp)
jne 0x46707a
movb $0x0, 0... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 76u, (llvm::AArch64_AM::ShiftExtendType)7, 16, false>() const | DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
if (!VectorMatch.isMatch())
return DiagnosticPredicateTy::NoMatch;
// Give a more specific diagnostic when the user has explicitly typed in
// a shift-amount that d... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x46dee0
movl %eax, 0x14(%rsp)
leaq 0x14(%rsp), %rdi
callq 0x465840
testb $0x1, %al
jne 0x46cd7e
leaq 0x24(%rsp), %rdi
movl $0x2, %esi
callq 0x472250
jmp 0x46ce10
movq 0x8(%rsp), %rdi
callq 0x41c350
movl %eax, 0x4(%rsp)
movl $0x2, %... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<3u>() const | DiagnosticPredicate isExactFPImm() const {
if (Kind != k_FPImm)
return DiagnosticPredicateTy::NoMatch;
if (getFPImmIsExact()) {
// Lookup the immediate from table of supported immediates.
auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
assert(Desc && "Unknown enum value... | subq $0x98, %rsp
movq %rdi, 0x88(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x8(%rsp)
cmpl $0xf, 0x30(%rax)
je 0x4772a9
leaq 0x94(%rsp), %rdi
movl $0x2, %esi
callq 0x472250
jmp 0x4773f3
movq 0x8(%rsp), %rdi
callq 0x41bfa0
testb $0x1, %al
jne 0x4772bc
jmp 0x4773e1
movl $0x3, %edi
callq 0x41f71c0
movq %rax, 0x80(%rsp)
callq ... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::parseSwizzleOffset(long&) | bool
AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
SMLoc OffsetLoc = getLoc();
if (!parseExpr(Imm, "a swizzle macro")) {
return false;
}
if (!isUInt<16>(Imm)) {
Error(OffsetLoc, "expected a 16-bit offset");
return false;
}
return true;
} | subq $0x88, %rsp
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x78(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x483760
movq %rax, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x58(%rsp), %rdi
leaq 0x58d38c1(%rip), %rsi # 0x5da01cc
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movq 0x10(%rsp), %rsi
movq 0x58(%rsp... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::parseIntWithPrefix(char const*, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&, (anonymous namespace)::AMDGPUOperand::ImmTy, std::function<bool (long&)>) | ParseStatus AMDGPUAsmParser::parseIntWithPrefix(
const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
std::function<bool(int64_t &)> ConvertResult) {
SMLoc S = getLoc();
int64_t Value = 0;
ParseStatus Res = parseIntWithPrefix(Prefix, Value);
if (!Res.isSuccess())
return Res;
... | subq $0x118, %rsp # imm = 0x118
movq %r8, 0x8(%rsp)
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
movq %rdx, 0xf8(%rsp)
movl %ecx, 0xf4(%rsp)
movq %r8, 0xe8(%rsp)
movq 0x108(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x483760
movq 0x10(%rsp), %rdi
movq %rax, 0xe0(%rsp)
movq $0x0, 0xd8(%rsp)
movq 0x100(%rsp), %r... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
bool llvm::isUInt<8u>(unsigned long) | constexpr bool isUInt(uint64_t x) {
if constexpr (N == 0)
return 0 == x;
if constexpr (N == 8)
return static_cast<uint8_t>(x) == x;
if constexpr (N == 16)
return static_cast<uint16_t>(x) == x;
if constexpr (N == 32)
return static_cast<uint32_t>(x) == x;
if constexpr (N < 64)
return x < (UI... | movq %rdi, -0x8(%rsp)
movq -0x8(%rsp), %rax
movzbl %al, %eax
cmpq -0x8(%rsp), %rax
sete %al
andb $0x1, %al
retq
nopl (%rax,%rax)
| /llvm/Support/MathExtras.h |
(anonymous namespace)::AMDGPUAsmParser::validateInstruction(llvm::MCInst const&, llvm::SMLoc const&, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>> const&) | bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
const SMLoc &IDLoc,
const OperandVector &Operands) {
if (auto ErrMsg = validateLdsDirect(Inst)) {
Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);
return false;
}... | subq $0x388, %rsp # imm = 0x388
movq %rdi, 0x378(%rsp)
movq %rsi, 0x370(%rsp)
movq %rdx, 0x368(%rsp)
movq %rcx, 0x360(%rsp)
movq 0x378(%rsp), %rsi
movq %rsi, (%rsp)
movq 0x370(%rsp), %rdx
leaq 0x348(%rsp), %rdi
callq 0x541130
leaq 0x348(%rsp), %rdi
callq 0x417a00
testb $0x1, %al
jne 0x4e39de
jmp 0x4e3a70
mov... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::validateMIMGGatherDMask(llvm::MCInst const&) | bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)
return true;
int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);
unsigned DMask = Inst.g... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x30(%rsp), %rdi
callq 0x47b1b0
movl %eax, %ecx
movq 0x10(%rsp), %rax
movl %ecx, 0x2c(%rsp)
movq 0x128(%rax), %rdi
movl 0x2c(%rsp), %esi
callq 0x47b180
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rcx
movabsq $0x200... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::validateCoherencyBits(llvm::MCInst const&, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>> const&, llvm::SMLoc const&) | bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands,
const SMLoc &IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpN... | subq $0x228, %rsp # imm = 0x228
movq %rdi, 0x218(%rsp)
movq %rsi, 0x210(%rsp)
movq %rdx, 0x208(%rsp)
movq %rcx, 0x200(%rsp)
movq 0x218(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x210(%rsp), %rdi
callq 0x47b1b0
movl $0x5, %esi
movzwl %ax, %edi
callq 0x41fedb0
cwtl
movl %eax, 0x1fc(%rsp)
cmpl $-0x1, 0x1fc(%rsp)
j... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::validateExeczVcczOperands(llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>> const&) | bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
if (!isGFX11Plus())
return true;
for (auto &Operand : Operands) {
if (!Operand->isReg())
continue;
unsigned Reg = Operand->getReg();
if (Reg == SRC_EXECZ || Reg == SRC_VCCZ) {
Error(getRegLoc(Reg, Operands),... | subq $0x88, %rsp
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x78(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x486230
testb $0x1, %al
jne 0x5454b0
movb $0x1, 0x87(%rsp)
jmp 0x5455c8
movq 0x70(%rsp), %rax
movq %rax, 0x68(%rsp)
movq 0x68(%rsp), %rdi
callq 0x41fd10
movq %rax, 0x60(%rsp)
movq 0x68(%rsp), %rdi
callq 0x41fd20
... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
llvm::ARM_AM::getShiftOpcStr(llvm::ARM_AM::ShiftOpc) | inline const StringRef getShiftOpcStr(ShiftOpc Op) {
switch (Op) {
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return "asr";
case ARM_AM::lsl: return "lsl";
case ARM_AM::lsr: return "lsr";
case ARM_AM::ror: return "ror";
case ARM_AM::rrx: return "rrx";
case ARM_AM:... | subq $0x28, %rsp
movl %edi, 0x14(%rsp)
movl 0x14(%rsp), %eax
decl %eax
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rax
leaq 0x5d757a9(%rip), %rcx # 0x62c36f8
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
leaq 0x18(%rsp), %rdi
leaq 0x7d46097(%rip), %rsi # 0x8293ffb
callq 0x3ee9c0
jmp 0x54dfc8
leaq 0x18(%rsp), %rdi... | /Target/ARM/MCTargetDesc/ARMAddressingModes.h |
(anonymous namespace)::ARMAsmParser::tryConvertingToTwoOperandForm(llvm::StringRef, llvm::ARMCC::CondCodes, bool, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&, unsigned int) | void ARMAsmParser::tryConvertingToTwoOperandForm(
StringRef Mnemonic, ARMCC::CondCodes PredicationCode, bool CarrySetting,
OperandVector &Operands, unsigned MnemonicOpsEndInd) {
if (operandsContainWide(Operands, MnemonicOpsEndInd))
return;
if (Operands.size() != MnemonicOpsEndInd + 3)
return;
co... | subq $0x348, %rsp # imm = 0x348
movb %r8b, %al
movl 0x350(%rsp), %r8d
movq %rsi, 0x338(%rsp)
movq %rdx, 0x340(%rsp)
movq %rdi, 0x330(%rsp)
movl %ecx, 0x32c(%rsp)
andb $0x1, %al
movb %al, 0x32b(%rsp)
movq %r9, 0x320(%rsp)
movq 0x330(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x320(%rsp), %rdi
movl 0x350(%rsp), %e... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::StringRef, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::StringRef, void>, llvm::detail::DenseSetPair<llvm::StringRef>>, llvm::StringRef, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::StringRef, void>, llvm::detail::DenseSetPair<llvm::StringRef>>::initEmpty() | void initEmpty() {
setNumEntries(0);
setNumTombstones(0);
assert((getNumBuckets() & (getNumBuckets()-1)) == 0 &&
"# initial buckets must be a power of two!");
const KeyT EmptyKey = getEmptyKey();
for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B)
::new (&B->getFirst... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %esi, %esi
callq 0x5713d0
movq 0x8(%rsp), %rdi
xorl %esi, %esi
callq 0x5713f0
callq 0x571410
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
movq %rdx, 0x28(%rsp)
callq 0x571440
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0x571450
mo... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::ARMAsmParser::parseAM3Offset(llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&) | ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// am3offset := '+' register
// | '-' register
// | register
// | # imm
// | # + imm
// | # - imm
// ... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x178(%rsp)
movq %rsi, 0x170(%rsp)
movq 0x178(%rsp), %rdi
movq %rdi, 0x30(%rsp)
callq 0x3fb960
movq %rax, 0x168(%rsp)
movq 0x168(%rsp), %rdi
callq 0x5b2a510
movq %rax, %rsi
leaq 0x140(%rsp), %rdi
callq 0x40a170
leaq 0x140(%rsp), %rdi
callq 0x5b2a240
movq %rax, 0x138... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
(anonymous namespace)::ARMAsmParser::parsePostIdxReg(llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&) | ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// postidx_reg := '+' register {, shift}
// | '-' register {, shift}
// | register {, shift}
// This method must return ParseStatus::NoMatch with... | subq $0x108, %rsp # imm = 0x108
movq %rdi, 0xf8(%rsp)
movq %rsi, 0xf0(%rsp)
movq 0xf8(%rsp), %rdi
movq %rdi, 0x20(%rsp)
callq 0x3fb960
movq %rax, 0xe8(%rsp)
movq 0xe8(%rsp), %rdi
callq 0x5b2a510
movq %rax, %rsi
leaq 0xc0(%rsp), %rdi
callq 0x40a170
leaq 0xc0(%rsp), %rdi
callq 0x5b2a240
movq %rax, 0xb8(%rsp)
m... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
(anonymous namespace)::ARMAsmParser::parseVectorLane((anonymous namespace)::VectorLaneTy&, unsigned int&, llvm::SMLoc&) | ParseStatus ARMAsmParser::parseVectorLane(VectorLaneTy &LaneKind,
unsigned &Index, SMLoc &EndLoc) {
MCAsmParser &Parser = getParser();
Index = 0; // Always return a defined index value.
if (Parser.getTok().is(AsmToken::LBrac)) {
Parser.Lex(); // Eat the '['.
if (P... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x178(%rsp)
movq %rsi, 0x170(%rsp)
movq %rdx, 0x168(%rsp)
movq %rcx, 0x160(%rsp)
movq 0x178(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3fb960
movq %rax, 0x158(%rsp)
movq 0x168(%rsp), %rax
movl $0x0, (%rax)
movq 0x158(%rsp), %rdi
callq 0x5b2a510
movq %rax, %rdi
movl $0x13... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
bool (anonymous namespace)::ARMOperand::isImmediateS4<-511l, 511l>() const | bool isImmediateS4() const {
if (!isImm()) return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false;
int64_t Value = CE->getValue();
return ((Value & 3) == 0) && Value >= N && Value <= M;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq (%rdi), %rax
callq *0x28(%rax)
testb $0x1, %al
jne 0x5b8684
movb $0x0, 0x37(%rsp)
jmp 0x5b86f9
movq 0x10(%rsp), %rdi
callq 0x54dc00
movq %rax, %rdi
callq 0x41d9b0
movq %rax, 0x20(%rsp)
cmpq $0x0, 0x20(%rsp)
jne 0x5b86aa
movb $0x0, 0... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
(anonymous namespace)::ARMOperand::addExpr(llvm::MCInst&, llvm::MCExpr const*) const | void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdx, 0x50(%rsp)
cmpq $0x0, 0x50(%rsp)
jne 0x5be032
movq 0x58(%rsp), %rax
movq %rax, 0x10(%rsp)
xorl %eax, %eax
movl %eax, %edi
callq 0x4777d0
movq 0x10(%rsp), %rdi
movb %al, 0x40(%rsp)
movq %rdx, 0x48(%rsp)
movb 0x40(%rsp), %al
movq 0x48(%rsp), %rdx
mov... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
(anonymous namespace)::MipsAsmParser::MatchAndEmitInstruction(llvm::SMLoc, unsigned int&, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&, llvm::MCStreamer&, unsigned long&, bool) | bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
bool M... | subq $0x10c8, %rsp # imm = 0x10C8
movb 0x10d0(%rsp), %al
movq %rsi, 0x10b8(%rsp)
movq %rdi, 0x10b0(%rsp)
movq %rdx, 0x10a8(%rsp)
movq %rcx, 0x10a0(%rsp)
movq %r8, 0x1098(%rsp)
movq %r9, 0x1090(%rsp)
andb $0x1, %al
movb %al, 0x108f(%rsp)
movq 0x10b0(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x1008(%rsp), %rdi
mov... | /Target/Mips/AsmParser/MipsAsmParser.cpp |
(anonymous namespace)::MipsAsmParser::parseSetReorderDirective() | bool MipsAsmParser::parseSetReorderDirective() {
MCAsmParser &Parser = getParser();
Parser.Lex();
// If this is not the end of the statement, report an error.
if (getLexer().isNot(AsmToken::EndOfStatement)) {
reportParseError("unexpected token, expected end of statement");
return false;
}
AssemblerO... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3fb960
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq (%rdi), %rax
callq *0xb8(%rax)
movq (%rsp), %rdi
callq 0x415e80
movq %rax, %rdi
movl $0x9, %esi
callq 0x415ea0
testb $0x1, %al
jne 0x62fa66
jmp 0x62fa8c
leaq 0x8(%rsp), %rdi
lea... | /Target/Mips/AsmParser/MipsAsmParser.cpp |
(anonymous namespace)::MipsAsmParser::parseSetNoReorderDirective() | bool MipsAsmParser::parseSetNoReorderDirective() {
MCAsmParser &Parser = getParser();
Parser.Lex();
// If this is not the end of the statement, report an error.
if (getLexer().isNot(AsmToken::EndOfStatement)) {
reportParseError("unexpected token, expected end of statement");
return false;
}
Assemble... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3fb960
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq (%rdi), %rax
callq *0xb8(%rax)
movq (%rsp), %rdi
callq 0x415e80
movq %rax, %rdi
movl $0x9, %esi
callq 0x415ea0
testb $0x1, %al
jne 0x62fb26
jmp 0x62fb4c
leaq 0x8(%rsp), %rdi
lea... | /Target/Mips/AsmParser/MipsAsmParser.cpp |
(anonymous namespace)::MipsOperand::isMM16AsmRegMoveP() const | bool isMM16AsmRegMoveP() const {
if (!(isRegIdx() && RegIdx.Kind))
return false;
return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
(RegIdx.Index >= 16 && RegIdx.Index <= 20));
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x6258e0
testb $0x1, %al
jne 0x63f19e
jmp 0x63f1a9
movq 0x10(%rsp), %rax
cmpl $0x0, 0x44(%rax)
jne 0x63f1b0
movb $0x0, 0x27(%rsp)
jmp 0x63f210
movq 0x10(%rsp), %rcx
movb $0x1, %al
cmpl $0x0, 0x40(%rcx)
movb %al, 0xf(%rsp)
je 0x63f2... | /Target/Mips/AsmParser/MipsAsmParser.cpp |
(anonymous namespace)::RISCVOperand::isUImm9Lsb000() const | bool isUImm9Lsb000() const {
if (!isImm())
return false;
int64_t Imm;
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && isShiftedUInt<6, 3>(Imm) &&
VK == RISCVMCExpr::VK_RISCV_None;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x67d110
testb $0x1, %al
jne 0x694863
movb $0x0, 0x37(%rsp)
jmp 0x6948c9
movq 0x10(%rsp), %rdi
movl $0x0, 0x1c(%rsp)
callq 0x67d530
movq %rax, %rdi
leaq 0x20(%rsp), %rsi
leaq 0x1c(%rsp), %rdx
callq 0x685170
andb $0x1, %al
movb %al,... | /Target/RISCV/AsmParser/RISCVAsmParser.cpp |
(anonymous namespace)::RISCVAsmParser::emitVMSGE(llvm::MCInst&, unsigned int, llvm::SMLoc, llvm::MCStreamer&) | void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
MCStreamer &Out) {
if (Inst.getNumOperands() == 3) {
// unmasked va >= x
//
// pseudoinstruction: vmsge{u}.vx vd, va, x
// expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
emitToStream... | subq $0x668, %rsp # imm = 0x668
movq %rcx, 0x660(%rsp)
movq %rdi, 0x658(%rsp)
movq %rsi, 0x650(%rsp)
movl %edx, 0x64c(%rsp)
movq %r8, 0x640(%rsp)
movq 0x658(%rsp), %rax
movq %rax, 0xe8(%rsp)
movq 0x650(%rsp), %rdi
callq 0x47b350
cmpl $0x3, %eax
jne 0x6977c3
movq 0x640(%rsp), %rax
movq %rax, 0xc8(%rsp)
movl 0... | /Target/RISCV/AsmParser/RISCVAsmParser.cpp |
(anonymous namespace)::WebAssemblyAsmParser::parseSpecialFloatMaybe(bool, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&) | bool parseSpecialFloatMaybe(bool IsNegative, OperandVector &Operands) {
if (Lexer.isNot(AsmToken::Identifier))
return true;
auto &Flt = Lexer.getTok();
auto S = Flt.getString();
double Val;
if (S.compare_insensitive("infinity") == 0) {
Val = std::numeric_limits<double>::infinity();
}... | subq $0xa8, %rsp
movb %sil, %al
movq %rdi, 0x98(%rsp)
andb $0x1, %al
movb %al, 0x97(%rsp)
movq %rdx, 0x88(%rsp)
movq 0x98(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x138(%rax), %rdi
movl $0x2, %esi
callq 0x415ea0
testb $0x1, %al
jne 0x6d6157
jmp 0x6d6164
movb $0x1, 0xa7(%rsp)
jmp 0x6d62f0
movq 0x10(%rsp), %rax
movq 0x138(... | /Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MCSection*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSection*, void>, llvm::detail::DenseSetPair<llvm::MCSection*>>, llvm::MCSection*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSection*, void>, llvm::detail::DenseSetPair<llvm::MCSection*>>::initEmpty(... | void initEmpty() {
setNumEntries(0);
setNumTombstones(0);
assert((getNumBuckets() & (getNumBuckets()-1)) == 0 &&
"# initial buckets must be a power of two!");
const KeyT EmptyKey = getEmptyKey();
for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B)
::new (&B->getFirst... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
xorl %esi, %esi
callq 0x6dd4d0
movq (%rsp), %rdi
xorl %esi, %esi
callq 0x6dd4f0
callq 0x6dcce0
movq (%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0x6dca60
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x6dca70
movq %rax, 0x8(%rsp)
movq 0x10(%rsp)... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::X86AsmParser::GetSIDIForRegClass(unsigned int, unsigned int, bool) | unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
bool IsSIReg) {
switch (RegClassID) {
default: llvm_unreachable("Unexpected register class");
case X86::GR64RegClassID:
return IsSIReg ? X86::RSI : X86::RDI;
case X86::GR32RegClassID:
r... | movb %cl, %al
movq %rdi, -0x10(%rsp)
movl %esi, -0x14(%rsp)
movl %edx, -0x18(%rsp)
andb $0x1, %al
movb %al, -0x19(%rsp)
movl -0x14(%rsp), %eax
movl %eax, -0x20(%rsp)
subl $0x7, %eax
je 0x705be5
jmp 0x705ba4
movl -0x20(%rsp), %eax
subl $0x23, %eax
je 0x705bcb
jmp 0x705baf
jmp 0x705bb1
movb -0x19(%rsp), %dl
movl $0x37, %... | /Target/X86/AsmParser/X86AsmParser.cpp |
(anonymous namespace)::X86AsmParser::parseDirectiveSEHPushFrame(llvm::SMLoc) | bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
bool Code = false;
StringRef CodeID;
if (getLexer().is(AsmToken::At)) {
SMLoc startLoc = getLexer().getLoc();
getParser().Lex();
if (!getParser().parseIdentifier(CodeID)) {
if (CodeID != "code")
return Error(startLoc, "expected @... | subq $0xd8, %rsp
movq %rsi, 0xc8(%rsp)
movq %rdi, 0xc0(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, (%rsp)
movb $0x0, 0xbf(%rsp)
leaq 0xa8(%rsp), %rdi
callq 0x3f36f0
movq (%rsp), %rdi
callq 0x415e80
movq %rax, %rdi
movl $0x2e, %esi
callq 0x431140
testb $0x1, %al
jne 0x707957
jmp 0x707a69
movq (%rsp), %rdi
callq 0x415e80
movq... | /Target/X86/AsmParser/X86AsmParser.cpp |
llvm::X86Operand::isDstIdx() const | bool isDstIdx() const {
return !getMemIndexReg() && getMemScale() == 1 &&
(getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
(getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
cast<MCConstantExpr>(getMemDisp(... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x70b110
movl %eax, %ecx
xorl %eax, %eax
cmpl $0x0, %ecx
movb %al, 0x17(%rsp)
jne 0x71d880
movq 0x8(%rsp), %rdi
callq 0x70b0f0
movl %eax, %ecx
xorl %eax, %eax
cmpl $0x1, %ecx
movb %al, 0x17(%rsp)
jne 0x71d880
movq 0x8(%rsp), %rdi
ca... | /Target/X86/AsmParser/X86Operand.h |
llvm::MachineInstr::hasProperty(unsigned int, llvm::MachineInstr::QueryType) const | bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
assert(MCFlag < 64 &&
"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
// Inline the fast path for unbundled or bundle-internal instructions.
if (Type == IgnoreBundle || !isBundled() || isBundledWithPred(... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movl %edx, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
cmpl $0x0, 0x10(%rsp)
je 0x734912
movq 0x8(%rsp), %rdi
callq 0x734980
testb $0x1, %al
jne 0x734902
jmp 0x734912
movq 0x8(%rsp), %rdi
callq 0x7349c0
testb $0x1, %al
jne 0x734912
jmp 0x734945
movq... | /llvm/CodeGen/MachineInstr.h |
llvm::AArch64_AM::getShifterImm(llvm::AArch64_AM::ShiftExtendType, unsigned int) | static inline unsigned getShifterImm(AArch64_AM::ShiftExtendType ST,
unsigned Imm) {
assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
unsigned STEnc = 0;
switch (ST) {
default: llvm_unreachable("Invalid shift requested");
case AArch64_AM::LSL: STEnc = 0; ... | movl %edi, -0x4(%rsp)
movl %esi, -0x8(%rsp)
movl $0x0, -0xc(%rsp)
movl -0x4(%rsp), %eax
movq %rax, -0x18(%rsp)
movq -0x18(%rsp), %rax
leaq 0x5d3465f(%rip), %rcx # 0x64745f4
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x0, -0xc(%rsp)
jmp 0x73ffce
movl $0x1, -0xc(%rsp)
jmp 0x73ffce
movl $0x2, -0xc(%rsp)... | /Target/AArch64/MCTargetDesc/AArch64AddressingModes.h |
llvm::InstructionCost::operator-=(llvm::InstructionCost const&) | InstructionCost &operator-=(const InstructionCost &RHS) {
propagateState(RHS);
// Saturating subtract.
InstructionCost::CostType Result;
if (SubOverflow(Value, RHS.Value, Result))
Result = RHS.Value > 0 ? getMinValue() : getMaxValue();
Value = Result;
return *this;
} | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x7854e0
movq 0x8(%rsp), %rax
movq (%rax), %rdi
movq 0x18(%rsp), %rax
movq (%rax), %rsi
leaq 0x10(%rsp), %rdx
callq 0x7b91a0
cmpq $0x0, %rax
je 0x7b918a
movq 0x18(%rsp), %rax
cmpq $0x0, (%... | /llvm/Support/InstructionCost.h |
void llvm::OptimizationRemarkEmitter::emit<llvm::AArch64TargetLowering::LowerCall(llvm::TargetLowering::CallLoweringInfo&, llvm::SmallVectorImpl<llvm::SDValue>&) const::$_2>(llvm::AArch64TargetLowering::LowerCall(llvm::TargetLowering::CallLoweringInfo&, llvm::SmallVectorImpl<llvm::SDValue>&) const::$_2, decltype(fp())*... | void emit(T RemarkBuilder, decltype(RemarkBuilder()) * = nullptr) {
// Avoid building the remark unless we know there are at least *some*
// remarks enabled. We can't currently check whether remarks are requested
// for the calling pass since that requires actually building the remark.
if (enabled()) {... | subq $0x1d8, %rsp # imm = 0x1D8
leaq 0x1e0(%rsp), %rax
movq %rax, 0x8(%rsp)
movq %rdi, 0x1d0(%rsp)
movq %rsi, 0x1c8(%rsp)
movq 0x1d0(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x7d9bc0
testb $0x1, %al
jne 0xa15e4c
jmp 0xa15e74
movq 0x8(%rsp), %rsi
leaq 0x18(%rsp), %rdi
callq 0xac6fd0
movq 0x10(%rsp), %rdi
leaq ... | /llvm/Analysis/OptimizationRemarkEmitter.h |
tryToConvertShuffleOfTbl2ToTbl4(llvm::SDValue, llvm::ArrayRef<int>, llvm::SelectionDAG&) | static SDValue tryToConvertShuffleOfTbl2ToTbl4(SDValue Op,
ArrayRef<int> ShuffleMask,
SelectionDAG &DAG) {
SDValue Tbl1 = Op->getOperand(0);
SDValue Tbl2 = Op->getOperand(1);
SDLoc dl(Op);
SDValue Tbl2ID =
DAG.ge... | subq $0x438, %rsp # imm = 0x438
movq %rdi, 0x418(%rsp)
movl %esi, 0x420(%rsp)
movq %rdx, 0x408(%rsp)
movq %rcx, 0x410(%rsp)
movq %r8, 0x400(%rsp)
leaq 0x418(%rsp), %rdi
movq %rdi, 0x80(%rsp)
callq 0x988cf0
movq %rax, %rdi
xorl %esi, %esi
movl %esi, 0x9c(%rsp)
callq 0x981ab0
movq 0x80(%rsp), %rdi
movups (%rax... | /Target/AArch64/AArch64ISelLowering.cpp |
getPackedSVEVectorVT(llvm::ElementCount) | static inline EVT getPackedSVEVectorVT(ElementCount EC) {
switch (EC.getKnownMinValue()) {
default:
llvm_unreachable("unexpected element count for vector");
case 16:
return MVT::nxv16i8;
case 8:
return MVT::nxv8i16;
case 4:
return MVT::nxv4i32;
case 2:
return MVT::nxv2i64;
}
} | subq $0x28, %rsp
movq %rdi, 0x10(%rsp)
leaq 0x10(%rsp), %rdi
callq 0x7841a0
addl $-0x2, %eax
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rax
leaq 0x5b58da1(%rip), %rcx # 0x6595f48
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
leaq 0x18(%rsp), %rdi
movl $0x94, %esi
callq 0x793360
jmp 0xa3d1f2
leaq 0x18(%rsp), %rdi
m... | /Target/AArch64/AArch64ISelLowering.cpp |
getPredicateForFixedLengthVector(llvm::SelectionDAG&, llvm::SDLoc&, llvm::EVT) | static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
EVT VT) {
assert(VT.isFixedLengthVector() &&
DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
"Expected legal fixed length vector!");
std::optional<unsigned> PgPattern =
... | subq $0xe8, %rsp
movb %dl, %al
movb %al, 0xc8(%rsp)
movq %rcx, 0xd0(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
leaq 0xc8(%rsp), %rdi
callq 0x7abb40
movl %eax, %edi
callq 0xa23180
movq %rax, 0xb0(%rsp)
movq 0xc0(%rsp), %rdi
callq 0xa417f0
movq %rax, 0xa8(%rsp)
movq 0xa8(%rsp), %rdi
callq 0x7908b0
movl %eax, 0xa4(... | /Target/AArch64/AArch64ISelLowering.cpp |
llvm::DenseMap<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo, llvm::DenseMapInfo<llvm::SDNode const*, void>, llvm::detail::DenseMapPair<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0xa8f217
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0xa8f23f
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
shlq... | /llvm/ADT/DenseMap.h |
calculatePreExtendType(llvm::SDValue) | static EVT calculatePreExtendType(SDValue Extend) {
switch (Extend.getOpcode()) {
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
return Extend.getOperand(0).getValueType();
case ISD::AssertSext:
case ISD::AssertZext:
case ISD::SIGN_EXTEND_INREG: {
VTSDNode *TypeNode = dyn_cast<VTSDNode>(Extend.getOpe... | subq $0x38, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x20(%rsp)
leaq 0x18(%rsp), %rdi
callq 0x98d4c0
movl %eax, %ecx
movl %ecx, %eax
addl $-0x3, %eax
movl %ecx, (%rsp)
subl $0x2, %eax
jb 0xaa6cf8
jmp 0xaa6ca8
movl (%rsp), %eax
subl $0xb9, %eax
je 0xaa6d48
jmp 0xaa6cb8
movl (%rsp), %eax
addl $0xffffff2c, %eax # imm =... | /Target/AArch64/AArch64ISelLowering.cpp |
llvm::rewriteAArch64FrameIndex(llvm::MachineInstr&, unsigned int, unsigned int, llvm::StackOffset&, llvm::AArch64InstrInfo const*) | bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
unsigned FrameReg, StackOffset &Offset,
const AArch64InstrInfo *TII) {
unsigned Opcode = MI.getOpcode();
unsigned ImmIdx = FrameRegIdx + 1;
if (Opcode == AArch64::AD... | subq $0x128, %rsp # imm = 0x128
movq %rdi, 0x118(%rsp)
movl %esi, 0x114(%rsp)
movl %edx, 0x110(%rsp)
movq %rcx, 0x108(%rsp)
movq %r8, 0x100(%rsp)
movq 0x118(%rsp), %rdi
callq 0x72bbb0
movl %eax, 0xfc(%rsp)
movl 0x114(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xf8(%rsp)
cmpl $0x5a9, 0xfc(%rsp) # imm = 0x5A9
je 0... | /Target/AArch64/AArch64InstrInfo.cpp |
llvm::AArch64InstrInfo::probedStackAlloc(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool) const | MachineBasicBlock::iterator
AArch64InstrInfo::probedStackAlloc(MachineBasicBlock::iterator MBBI,
Register TargetReg, bool FrameSetup) const {
assert(TargetReg != AArch64::SP && "New top of stack cannot aleady be in SP");
MachineBasicBlock &MBB = *MBBI->getParent();
MachineFunct... | pushq %rbx
subq $0x450, %rsp # imm = 0x450
movb %cl, %al
movq %rsi, 0x440(%rsp)
movl %edx, 0x43c(%rsp)
movq %rdi, 0x430(%rsp)
andb $0x1, %al
movb %al, 0x42f(%rsp)
leaq 0x440(%rsp), %rdi
callq 0x73ff20
movq %rax, %rdi
callq 0x73fb40
movq %rax, 0x420(%rsp)
movq 0x420(%rsp), %rdi
callq 0x73fb50
movq %rax, 0x418... | /Target/AArch64/AArch64InstrInfo.cpp |
llvm::TargetInstrInfo::buildClearRegister(llvm::Register, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc&, bool) const | virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator Iter,
DebugLoc &DL,
bool AllowSideEffects = true) const {
#if 0
// FIXME: This should exist once all platforms that ... | movb %r9b, %al
movl %esi, -0x4(%rsp)
movq %rcx, -0x10(%rsp)
movq %rdi, -0x18(%rsp)
movq %rdx, -0x20(%rsp)
movq %r8, -0x28(%rsp)
andb $0x1, %al
movb %al, -0x29(%rsp)
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/CodeGen/TargetInstrInfo.h |
llvm::AArch64_AM::processLogicalImmediate(unsigned long, unsigned int, unsigned long&) | static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
uint64_t &Encoding) {
if (Imm == 0ULL || Imm == ~0ULL ||
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
return false;
// First, determine the elemen... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movl %esi, 0x44(%rsp)
movq %rdx, 0x38(%rsp)
cmpq $0x0, 0x48(%rsp)
je 0xafd9fd
cmpq $-0x1, 0x48(%rsp)
je 0xafd9fd
cmpl $0x40, 0x44(%rsp)
je 0xafda07
movq 0x48(%rsp), %rax
movl 0x44(%rsp), %ecx
shrq %cl, %rax
cmpq $0x0, %rax
jne 0xafd9fd
movq 0x48(%rsp), %rax
movl $0x40, %ecx
subl 0... | /Target/AArch64/MCTargetDesc/AArch64AddressingModes.h |
llvm::SmallVectorImpl<unsigned long>::operator=(llvm::SmallVectorImpl<unsigned long> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)
cmpq 0x60(%rsp), %rax
jne 0xb0069e
movq 0x40(%rsp), %rax
movq %rax, 0x70(%rsp)
jmp 0xb00863
movq 0x60(%rsp), %rdi
callq 0x3a8dca0
movq 0x40(%rsp), %rdi
movq %rax, 0x58(%rsp)
callq 0x3a8dca0
movq %rax, 0x50(%rsp)
mov... | /llvm/ADT/SmallVector.h |
getLdStRegOp(llvm::MachineInstr&, unsigned int) | static MachineOperand &getLdStRegOp(MachineInstr &MI,
unsigned PairedRegOp = 0) {
assert(PairedRegOp < 2 && "Unexpected register operand idx.");
bool IsPreLdSt = AArch64InstrInfo::isPreLdSt(MI);
if (IsPreLdSt)
PairedRegOp += 1;
unsigned Idx =
AArch64InstrInfo::isPai... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
callq 0xad9410
andb $0x1, %al
movb %al, 0xb(%rsp)
testb $0x1, 0xb(%rsp)
je 0xb0f6df
movl 0xc(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xc(%rsp)
movq 0x10(%rsp), %rdi
callq 0xadf530
testb $0x1, %al
jne 0xb0f6f4
testb $0x1, 0xb(%rsp)
je 0xb0f... | /Target/AArch64/AArch64LoadStoreOptimizer.cpp |
(anonymous namespace)::AArch64MIPeepholeOpt::visitINSviGPR(llvm::MachineInstr&, unsigned int) | bool AArch64MIPeepholeOpt::visitINSviGPR(MachineInstr &MI, unsigned Opc) {
// Check if this INSvi[X]gpr comes from COPY of a source FPR128
//
// From
// %intermediate1:gpr64 = COPY %src:fpr128
// %intermediate2:gpr32 = COPY %intermediate1:gpr64
// %dst:fpr128 = INSvi[X]gpr %dst_vec:fpr128, dst_index, %in... | subq $0xc8, %rsp
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movl %edx, 0xac(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x50(%rax), %rax
movq %rax, 0x40(%rsp)
movq 0xb0(%rsp), %rdi
movl $0x3, %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x72c500
movq 0x40(%rsp), %rdi
movl %eax, 0x9c(%rsp)
movl 0x9c(%rsp), %esi... | /Target/AArch64/AArch64MIPeepholeOpt.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Instruction*, llvm::SmallVector<std::pair<llvm::Instruction*, unsigned int>, 4u>, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::SmallVector<std::pair<llvm::Instruction*, unsigned int>, 4u>>>, llvm::Instruction*, llvm::SmallVect... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xb35e9e
movl $0x0, 0x14(%rsp)
jmp 0xb35ebe
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<std::pair<llvm::Instruction*, unsigned int>>::operator=(llvm::SmallVectorImpl<std::pair<llvm::Instruction*, unsigned int>>&&) | SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If the RHS isn't small, clear this vector and then steal its buffer.
if (!RHS.isSmall()) {
this->assignRemote(std::move(RHS));
return *this;
}
// If we already... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x30(%rsp)
cmpq 0x50(%rsp), %rax
jne 0xb36ece
movq 0x30(%rsp), %rax
movq %rax, 0x60(%rsp)
jmp 0xb370b0
movq 0x50(%rsp), %rdi
callq 0xb37140
testb $0x1, %al
jne 0xb36efa
movq 0x30(%rsp), %rdi
movq 0x50(%rsp), %rsi
callq 0xb3717... | /llvm/ADT/SmallVector.h |
llvm::A57ChainingConstraint::addInterChainConstraint(llvm::PBQP::RegAlloc::PBQPRAGraph&, unsigned int, unsigned int) | void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
unsigned Ra) {
LiveIntervals &LIs = G.getMetadata().LIS;
// Do some Chain management
if (Chains.count(Ra)) {
if (Rd != Ra) {
LLVM_DEBUG(dbgs() << "Moving acc chain from " <<... | subq $0x128, %rsp # imm = 0x128
movq %rdi, 0x120(%rsp)
movq %rsi, 0x118(%rsp)
movl %edx, 0x114(%rsp)
movl %ecx, 0x110(%rsp)
movq 0x120(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x118(%rsp), %rdi
callq 0xb38cb0
movq 0x40(%rsp), %rdi
movq 0x8(%rax), %rax
movq %rax, 0x108(%rsp)
addq $0x8, %rdi
leaq 0x110(%rsp), %r... | /Target/AArch64/AArch64PBQPRegAlloc.cpp |
llvm::SetVector<unsigned int, llvm::SmallVector<unsigned int, 32u>, llvm::DenseSet<unsigned int, llvm::DenseMapInfo<unsigned int, void>>, 32u>::remove(unsigned int const&) | bool remove(const value_type& X) {
if constexpr (canBeSmall())
if (isSmall()) {
typename vector_type::iterator I = find(vector_, X);
if (I != vector_.end()) {
vector_.erase(I);
return true;
}
return false;
}
if (set_.erase(X)) {
typename vec... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xb431c0
testb $0x1, %al
jne 0xb39b53
jmp 0xb39baf
movq 0x8(%rsp), %rdi
addq $0x18, %rdi
movq 0x20(%rsp), %rsi
callq 0xb43610
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
a... | /llvm/ADT/SetVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::PBQP::ValuePool<llvm::PBQP::MDMatrix<llvm::PBQP::RegAlloc::MatrixMetadata>>::PoolEntry*, llvm::detail::DenseSetEmpty, llvm::PBQP::ValuePool<llvm::PBQP::MDMatrix<llvm::PBQP::RegAlloc::MatrixMetadata>>::PoolEntryDSInfo, llvm::detail::DenseSetPair<llvm::PBQP::ValuePool<llvm::PBQP::M... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x20(%rsp), %rsi
leaq 0x18(%rsp), %rdx
callq 0xb40210
testb $0x1, %al
jne 0xb401c2
movb $0x0, 0x37(%rsp)
jmp 0xb40201
movq 0x18(%rsp), %rdi
callq 0xb40260
callq 0xb3ccd0
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::initializeAArch64SpeculationHardeningPass(llvm::PassRegistry&) | bool AArch64SpeculationHardening::endsWithCondControlFlow(
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
AArch64CC::CondCode &CondCode) const {
SmallVector<MachineOperand, 1> analyzeBranchCondCode;
if (TII->analyzeBranch(MBB, TBB, FBB, analyzeBranchCondCode, false))
return fa... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x7ddcb0
movq %rax, 0x8(%rsp)
leaq 0x8c0dbb9(%rip), %rdi # 0x97594b8
leaq 0x1a(%rip), %rsi # 0xb4b920
leaq 0x8(%rsp), %rdx
callq 0x7ddbd0
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nop
| /Target/AArch64/AArch64SpeculationHardening.cpp |
initializeAArch64SpeculationHardeningPassOnce(llvm::PassRegistry&) | bool AArch64SpeculationHardening::endsWithCondControlFlow(
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
AArch64CC::CondCode &CondCode) const {
SmallVector<MachineOperand, 1> analyzeBranchCondCode;
if (TII->analyzeBranch(MBB, TBB, FBB, analyzeBranchCondCode, false))
return fa... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movl $0x50, %edi
callq 0x349070
movq %rax, 0x20(%rsp)
leaq 0x38(%rsp), %rdi
leaq 0x5a58412(%rip), %rsi # 0x65a3d56
callq 0x3ee9c0
leaq 0x28(%rsp), %rdi
leaq 0x5a58424(%rip), %rsi # 0x65a3d79
callq 0x3ee9c0
movq 0x20(%rsp), %rdi
movq 0x38(%rsp), %rsi
movq 0x40(%rsp), %rdx
movq ... | /Target/AArch64/AArch64SpeculationHardening.cpp |
(anonymous namespace)::AArch64SpeculationHardening::instrumentControlFlow(llvm::MachineBasicBlock&, bool&) | bool AArch64SpeculationHardening::instrumentControlFlow(
MachineBasicBlock &MBB, bool &UsesFullSpeculationBarrier) {
LLVM_DEBUG(dbgs() << "Instrument control flow tracking on MBB: " << MBB);
bool Modified = false;
MachineBasicBlock *TBB = nullptr;
MachineBasicBlock *FBB = nullptr;
AArch64CC::CondCode Con... | subq $0x2f8, %rsp # imm = 0x2F8
movq %rdi, 0x2f0(%rsp)
movq %rsi, 0x2e8(%rsp)
movq %rdx, 0x2e0(%rsp)
movq 0x2f0(%rsp), %rax
movq %rax, 0x40(%rsp)
jmp 0xb4cb5e
movq 0x40(%rsp), %rdi
movb $0x0, 0x2df(%rsp)
movq $0x0, 0x2d0(%rsp)
movq $0x0, 0x2c8(%rsp)
movq 0x2e8(%rsp), %rsi
leaq 0x2d0(%rsp), %rdx
leaq 0x2c8(%r... | /Target/AArch64/AArch64SpeculationHardening.cpp |
(anonymous namespace)::AArch64SpeculationHardening::lowerSpeculationSafeValuePseudos(llvm::MachineBasicBlock&, bool) | bool AArch64SpeculationHardening::lowerSpeculationSafeValuePseudos(
MachineBasicBlock &MBB, bool UsesFullSpeculationBarrier) {
bool Modified = false;
RegsNeedingCSDBBeforeUse.reset();
// The following loop iterates over all instructions in the basic block,
// and performs 2 operations:
// 1. Insert a CS... | subq $0x118, %rsp # imm = 0x118
movb %dl, %al
movq %rdi, 0x110(%rsp)
movq %rsi, 0x108(%rsp)
andb $0x1, %al
movb %al, 0x107(%rsp)
movq 0x110(%rsp), %rdi
movq %rdi, 0x28(%rsp)
movb $0x0, 0x106(%rsp)
addq $0x58, %rdi
callq 0x8c86c0
movq 0x108(%rsp), %rdi
callq 0x73fe80
movq %rax, 0xf8(%rsp)
movq 0x108(%rsp), %r... | /Target/AArch64/AArch64SpeculationHardening.cpp |
(anonymous namespace)::InitializerBuilder::Range* llvm::SmallVectorImpl<(anonymous namespace)::InitializerBuilder::Range>::insert_one_impl<(anonymous namespace)::InitializerBuilder::Range const&>((anonymous namespace)::InitializerBuilder::Range*, (anonymous namespace)::InitializerBuilder::Range const&) | iterator insert_one_impl(iterator I, ArgType &&Elt) {
// Callers ensure that ArgType is derived from T.
static_assert(
std::is_same<std::remove_const_t<std::remove_reference_t<ArgType>>,
T>::value,
"ArgType must be derived from T!");
if (I == this->end()) { // Importan... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x38(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x40(%rsp)
callq 0xb57a30
movq %rax, %rcx
movq 0x40(%rsp), %rax
cmpq %rcx, %rax
jne 0xb57e10
movq 0x38(%rsp), %rdi
movq 0x58(%rsp), %rsi
callq 0xb57f90
movq 0x3... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::InitializerBuilder::Range const* llvm::SmallVectorTemplateCommon<(anonymous namespace)::InitializerBuilder::Range, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<(anonymous namespace)::InitializerBuilder::Range, true>>(llvm::SmallVectorTemplateBase<(anonymous namespace)::In... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dca0
addq 0x38(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dab0
movq %rax, %rcx
movq 0x18(%rsp), %rax
cmpq %rcx, %rax
ja 0xb58167
movq 0x... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::AArch64FastISel::emitLSR_rr(llvm::MVT, unsigned int, unsigned int) | unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
unsigned Op1Reg) {
unsigned Opc = 0;
bool NeedTrunc = false;
uint64_t Mask = 0;
switch (RetVT.SimpleTy) {
default: return 0;
case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
c... | subq $0x58, %rsp
movb %sil, %al
movb %al, 0x53(%rsp)
movq %rdi, 0x48(%rsp)
movl %edx, 0x44(%rsp)
movl %ecx, 0x40(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x8(%rsp)
movl $0x0, 0x3c(%rsp)
movb $0x0, 0x3b(%rsp)
movq $0x0, 0x30(%rsp)
movzbl 0x53(%rsp), %eax
addl $-0x5, %eax
movl %eax, %ecx
movq %rcx, 0x10(%rsp)
subl $0x3, %e... | /Target/AArch64/AArch64FastISel.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::AllocaInst const*, int, llvm::DenseMapInfo<llvm::AllocaInst const*, void>, llvm::detail::DenseMapPair<llvm::AllocaInst const*, int>>, llvm::AllocaInst const*, int, llvm::DenseMapInfo<llvm::AllocaInst const*, void>, llvm::detail::DenseMapPair<llvm::AllocaInst const*, int>>::find(l... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x18(%rsp)
leaq 0x28(%rsp), %rsi
leaq 0x20(%rsp), %rdx
callq 0xb8ed60
testb $0x1, %al
jne 0xb8e73d
jmp 0xb8e79b
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xb8ee90
testb $0x1, %al
jne 0xb8e752
jmp 0xb8e763
movq 0x18(%rs... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AArch64FastISel::computeCallAddress(llvm::Value const*, (anonymous namespace)::AArch64FastISel::Address&) | bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
const User *U = nullptr;
unsigned Opcode = Instruction::UserOp1;
bool InMBB = true;
if (const auto *I = dyn_cast<Instruction>(V)) {
Opcode = I->getOpcode();
U = I;
InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
} ... | subq $0xe8, %rsp
movq %rdi, 0xd8(%rsp)
movq %rsi, 0xd0(%rsp)
movq %rdx, 0xc8(%rsp)
movq 0xd8(%rsp), %rax
movq %rax, 0x40(%rsp)
movq $0x0, 0xc0(%rsp)
movl $0x3a, 0xbc(%rsp)
movb $0x1, 0xbb(%rsp)
movq 0xd0(%rsp), %rdi
callq 0x78c230
movq %rax, 0xb0(%rsp)
cmpq $0x0, 0xb0(%rsp)
je 0xb915e6
movq 0xb0(%rsp), %rdi
callq 0x785... | /Target/AArch64/AArch64FastISel.cpp |
llvm::AMDGPUMachineFunction::getLDSAbsoluteAddress(llvm::GlobalValue const&) | std::optional<uint32_t>
AMDGPUMachineFunction::getLDSAbsoluteAddress(const GlobalValue &GV) {
if (GV.getAddressSpace() != AMDGPUAS::LOCAL_ADDRESS)
return {};
std::optional<ConstantRange> AbsSymRange = GV.getAbsoluteSymbolRange();
if (!AbsSymRange)
return {};
if (const APInt *V = AbsSymRange->getSingle... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq 0x48(%rsp), %rdi
callq 0x9508c0
cmpl $0x3, %eax
je 0xbf2c17
leaq 0x50(%rsp), %rdi
callq 0x412920
jmp 0xbf2cd9
movq 0x48(%rsp), %rsi
leaq 0x20(%rsp), %rdi
callq 0x30619a0
leaq 0x20(%rsp), %rdi
callq 0xbf2de0
testb $0x1, %al
jne 0xbf2c4b
leaq 0x50(%rsp), %rdi
callq 0x412920
mov... | /Target/AMDGPU/AMDGPUMachineFunction.cpp |
llvm::AMDGPUSubtarget::getEffectiveWavesPerEU(std::pair<unsigned int, unsigned int>, std::pair<unsigned int, unsigned int>) const | std::pair<unsigned, unsigned> AMDGPUSubtarget::getEffectiveWavesPerEU(
std::pair<unsigned, unsigned> Requested,
std::pair<unsigned, unsigned> FlatWorkGroupSizes) const {
// Default minimum/maximum number of waves per execution unit.
std::pair<unsigned, unsigned> Default(1, getMaxWavesPerEU());
// If mini... | subq $0x48, %rsp
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movl $0x1, 0x1c(%rsp)
callq 0xc02160
movl %eax, 0x18(%rsp)
leaq 0x20(%rsp), %rdi
leaq 0x1c(%rsp), %rsi
leaq 0x18(%rsp), %rdx
callq 0xbf2480
movq 0x8(%rsp), %rdi
movl 0x34(%rsp), %esi
movq (%rdi)... | /Target/AMDGPU/AMDGPUSubtarget.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [21], llvm::cl::desc, llvm::cl::initializer<bool>>(char const (&) [21], llvm::cl::desc const&, llvm::cl::initializer<bool> const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x3f7700
movq 0x8(%rsp), %rsi
leaq 0x8ad6c98(%rip), %rax # 0x96df180
addq $0x10... | /llvm/Support/CommandLine.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [33], llvm::cl::desc, llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(char const (&) [33], llvm::cl::desc const&, llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, (%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq (%rsp), %rdi
addq $0x80, %rdi
callq 0x3f7700
movq (%rsp), %rsi
leaq 0x8ad68f6(%rip), %rax # 0x96df18... | /llvm/Support/CommandLine.h |
LLVMInitializeAMDGPUTarget | LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
PassRegistry *PR = PassRegistry::getPassRegistry();
initializeR600ClauseMergePassPass(*PR);
initi... | subq $0x18, %rsp
callq 0x2e09740
movq %rax, %rsi
leaq 0x17(%rsp), %rdi
callq 0xc09230
callq 0x2e09780
movq %rax, %rsi
leaq 0x16(%rsp), %rdi
callq 0xc09260
callq 0x3143d70
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rdi
callq 0xcd1af0
movq 0x8(%rsp), %rdi
callq 0xcd2770
movq 0x8(%rsp), %rdi
callq 0xcf9fc0
movq 0x8(%rsp), %rdi... | /Target/AMDGPU/AMDGPUTargetMachine.cpp |
createGCNMaxOccupancyMachineScheduler(llvm::MachineSchedContext*) | static ScheduleDAGInstrs *
createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
ScheduleDAGMILive *DAG =
new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
DAG->addMutation(createLoadClusterDAGMutation(DAG->T... | subq $0x88, %rsp
movq %rdi, 0x80(%rsp)
movq 0x80(%rsp), %rax
movq 0x8(%rax), %rdi
callq 0xbd6260
movq %rax, 0x78(%rsp)
movl $0x1e20, %edi # imm = 0x1E20
callq 0x349070
movq %rax, 0x28(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0x60(%rsp), %rdi
leaq 0x80(%rsp), %rsi
callq 0xc12ca0
leaq 0x68(%rsp), ... | /Target/AMDGPU/AMDGPUTargetMachine.cpp |
computeDataLayout(llvm::Triple const&) | static StringRef computeDataLayout(const Triple &TT) {
if (TT.getArch() == Triple::r600) {
// 32-bit pointers.
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
}
// 32-bit private, local, and region pointers. 64... | subq $0x18, %rsp
movq %rdi, (%rsp)
movq (%rsp), %rdi
callq 0x4093d0
cmpl $0x19, %eax
jne 0xc09b49
leaq 0x8(%rsp), %rdi
leaq 0x59a190c(%rip), %rsi # 0x65ab44e
callq 0x3ee9c0
jmp 0xc09b5a
leaq 0x8(%rsp), %rdi
leaq 0x59a1970(%rip), %rsi # 0x65ab4c5
callq 0x3ee9c0
movq 0x8(%rsp), %rax
movq 0x10(%rsp), %rdx
addq $0x18, ... | /Target/AMDGPU/AMDGPUTargetMachine.cpp |
llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::buildPipeline(llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>&, llvm::raw_pwrite_stream&, llvm::raw_pwrite_stream*, llvm::CodeGenFileType) const | Error CodeGenPassBuilder<Derived, TargetMachineT>::buildPipeline(
ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType) const {
auto StartStopInfo = TargetPassConfig::getStartStopInfo(*PIC);
if (!StartStopInfo)
return StartStopInfo.takeError();
setStartSt... | subq $0x1c8, %rsp # imm = 0x1C8
movq %rdi, 0x28(%rsp)
movq %rdi, %rax
movq %rax, 0x30(%rsp)
movq %rdi, 0x1c0(%rsp)
movq %rsi, 0x1b8(%rsp)
movq %rdx, 0x1b0(%rsp)
movq %rcx, 0x1a8(%rsp)
movq %r8, 0x1a0(%rsp)
movl %r9d, 0x19c(%rsp)
movq 0x1b8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x90(%rax), %rsi
leaq 0x160(%r... | /llvm/Passes/CodeGenPassBuilder.h |
non-virtual thunk to llvm::RegisterPassParser<(anonymous namespace)::SGPRRegisterRegAlloc>::~RegisterPassParser() | void initialize() {
cl::parser<typename RegistryClass::FunctionPassCtor>::initialize();
// Add existing passes to option.
for (RegistryClass *Node = RegistryClass::getList();
Node; Node = Node->getNext()) {
this->addLiteralOption(Node->getName(),
(typename RegistryClass... | movq %rdi, -0x8(%rsp)
movq -0x8(%rsp), %rdi
addq $-0x8, %rdi
jmp 0xc0f5f0
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/CodeGen/MachinePassRegistry.h |
llvm::cl::parser<llvm::FunctionPass* (*)()>::OptionInfo const* llvm::SmallVectorTemplateCommon<llvm::cl::parser<llvm::FunctionPass* (*)()>::OptionInfo, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<llvm::cl::parser<llvm::FunctionPass* (*)()>::OptionInfo, false>>(llvm::SmallVectorTemplateBase<llv... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dca0
addq 0x38(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dab0
movq %rax, %rcx
movq 0x18(%rsp), %rax
cmpq %rcx, %rax
ja 0xc0fe17
movq 0x... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::AnalysisKey*, std::unique_ptr<llvm::detail::AnalysisPassConcept<llvm::LazyCallGraph::SCC, llvm::AnalysisManager<llvm::LazyCallGraph::SCC, llvm::LazyCallGraph&>::Invalidator, llvm::LazyCallGraph&>, std::default_delete<llvm::detail::AnalysisPassConcept<llvm::LazyCallGraph::SCC, llv... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xc1e550
cmpl $0x0, %eax
jne 0xc1e4a2
jmp 0xc1e542
callq 0xc1e560
movq %rax, 0x28(%rsp)
callq 0xc1e570
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0xc1e580
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0xc1e590
movq %rax, 0x... | /llvm/ADT/DenseMap.h |
void llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::AddIRPass::operator()<llvm::RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Module>>>(llvm::RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Mo... | void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
bool Required = false;
if const... | subq $0x78, %rsp
movq %rdx, 0x68(%rsp)
movq %rcx, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x10(%rsp)
movb $0x0, 0x57(%rsp)
callq 0xc2f840
movb %al, %cl
movq 0x10(%rsp), %rax
andb $0x1, %cl
movb %cl, 0x57(%rsp)
movq 0x20(%rax), %rdi
movq 0x68(%rsp), %rax
movq %rax, 0x40(%r... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::MachineModuleAnalysis::Result& llvm::AnalysisManager<llvm::Module>::getResult<llvm::MachineModuleAnalysis>(llvm::Module&) | typename PassT::Result &getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs) {
assert(AnalysisPasses.count(PassT::ID()) &&
"This analysis pass was not registered prior to being queried");
ResultConceptT &ResultConcept =
getResultImpl(PassT::ID(), IR, ExtraArgs...);
using ResultModelT =
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xc2f290
movq 0x8(%rsp), %rdi
movq %rax, %rsi
movq 0x18(%rsp), %rdx
callq 0x31334c0
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
addq $0x8, %rax
addq $0x28, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Module>>, llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>>, void>::type llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::addPass<llvm::RequireAnalysi... | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x10, %edi
callq 0x349070
movq %rax, %rdi
movq %rdi, 0x8(%rsp)
callq 0xc2f8b0
movq 0x8(%rsp), %rsi
leaq 0x20(%rsp), %rdi
callq 0xc2d9d0
movq 0x10(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0xc2d910
leaq 0x20(%rsp... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::LowerEmuTLSPass, llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>>, void>::type llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::addPass<llvm::LowerEmuTLSPass>(llvm::LowerEmuTLSPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x10, %edi
callq 0x349070
movq %rax, %rdi
movq %rdi, 0x8(%rsp)
callq 0xc311a0
movq 0x8(%rsp), %rsi
leaq 0x20(%rsp), %rdi
callq 0xc2d9d0
movq 0x10(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0xc2d910
leaq 0x20(%rsp... | /llvm/IR/PassManager.h |
llvm::StringRef llvm::getTypeName<llvm::PreISelIntrinsicLoweringPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x597a346(%rip), %rsi # 0x65aba01
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x58841ac(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
llvm::StringRef llvm::getTypeName<llvm::ShadowStackGCLoweringPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x5976be7(%rip), %rsi # 0x65abd02
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x588074c(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
llvm::StringRef llvm::getTypeName<llvm::ScalarizeMaskedMemIntrinPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x597064b(%rip), %rsi # 0x65abf36
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x5879f7c(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
void llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::AddMachinePass::operator()<llvm::FinalizeISelPass>(llvm::FinalizeISelPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | subq $0x78, %rsp
movb %dl, %al
movq %rcx, 0x68(%rsp)
movq %r8, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
andb $0x1, %al
movb %al, 0x57(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
testb $0x1, 0x57(%rsp)
jne 0xc3fb56
movq 0x8(%rsp), %rax
movq 0x20(%rax), %rdi
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)
... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::addMachineLateOptimization(llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::AddMachinePass&) const | void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineLateOptimization(
AddMachinePass &addPass) const {
// Branch folding must be run after regalloc and prolog/epilog insertion.
addPass(BranchFolderPass());
// Tail duplication.
// Note that duplicating tail just increases code size and degrades
//... | subq $0x98, %rsp
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x18(%rsp)
leaq 0x87(%rsp), %rdi
callq 0xc4ae50
callq 0xc4ae60
movq 0x18(%rsp), %rdi
movq %rax, 0x70(%rsp)
movq %rdx, 0x78(%rsp)
movq 0x70(%rsp), %rcx
movq 0x78(%rsp), %r8
leaq 0x87(... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::StringRef llvm::getTypeName<llvm::MachineLateInstrsCleanupPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x59613e4(%rip), %rsi # 0x65ace8f
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x5869dbc(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Metadata*, llvm::SmallSet<std::pair<llvm::GlobalVariable*, unsigned long>, 4u, std::less<std::pair<llvm::GlobalVariable*, unsigned long>>>, llvm::DenseMapInfo<llvm::Metadata*, void>, llvm::detail::DenseMapPair<llvm::Metadata*, llvm::SmallSet<std::pair<llvm::GlobalVariable*, unsig... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xc5e29e
movl $0x0, 0x14(%rsp)
jmp 0xc5e2be
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::StringRef llvm::getTypeName<llvm::InferAddressSpacesPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x594d94c(%rip), %rsi # 0x65adee7
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x58552cc(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>* llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::Den... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0xcaaf50
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0xc92e70
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %eax
... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<unsigned int, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<unsigned int, unsigned int>, unsigned int>, false>, bool> llvm::DenseMapBase<llvm::SmallDenseMap<std::pair<unsigned int, unsigned in... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | subq $0x88, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, 0x28(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movq 0x78(%rsp), %rsi
leaq 0x68(%rsp), %rdx
callq 0xcb3240
testb $0x1, %al
jne 0xcb30a5
jmp 0xcb311f
movq 0x68(%rsp), %rax
movq %rax, 0x18(%rsp)
call... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<std::pair<unsigned int, unsigned int>, unsigned int, 4u, llvm::DenseMapInfo<std::pair<unsigned int, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<unsigned int, unsigned int>, unsigned int>>, std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdx, 0x50(%rsp)
movq 0x60(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xcadea0
callq 0xcadf70
movq %rax, 0x48(%rsp)
callq 0xcaee40
movq %rax, 0x40(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x38(%rsp),... | /llvm/ADT/DenseMap.h |
llvm::GCNSchedStrategy::pickNodeBidirectional(bool&) | SUnit *GCNSchedStrategy::pickNodeBidirectional(bool &IsTopNode) {
// Schedule as far as possible in the direction of no choice. This is most
// efficient, but also provides the best heuristics for CriticalPSets.
if (SUnit *SU = Bot.pickOnlyChoice()) {
IsTopNode = false;
return SU;
}
if (SUnit *SU = To... | subq $0xb8, %rsp
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
movq 0xa8(%rsp), %rdi
movq %rdi, 0x28(%rsp)
addq $0x358, %rdi # imm = 0x358
callq 0x34c84a0
movq %rax, 0x98(%rsp)
cmpq $0x0, 0x98(%rsp)
je 0xcb7cd3
movq 0xa0(%rsp), %rax
movb $0x0, (%rax)
movq 0x98(%rsp), %rax
movq %rax, 0xb0(%rsp)
jmp 0xcb7fd2
mov... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::GCNScheduleDAGMILive::finalizeSchedule() | void GCNScheduleDAGMILive::finalizeSchedule() {
// Start actual scheduling here. This function is called by the base
// MachineScheduler after all regions have been recorded by
// GCNScheduleDAGMILive::schedule().
LiveIns.resize(Regions.size());
Pressure.resize(Regions.size());
RescheduleRegions.resize(Regi... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x38(%rsp)
movq %rdi, %rax
addq $0x17d0, %rax # imm = 0x17D0
movq %rax, (%rsp)
addq $0x1458, %rdi # imm = 0x1458
callq 0x3a8dca0
movq (%rsp), %rdi
movq %rax, %rsi
callq 0xcbac40
movq 0x38(%rsp), %rdi
movq %rdi, %rax
addq $0x1ae0... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::PreRARematStage::initGCNSchedStage() | bool PreRARematStage::initGCNSchedStage() {
if (!GCNSchedStage::initGCNSchedStage())
return false;
if (DAG.RegionsWithMinOcc.none() || DAG.Regions.size() == 1)
return false;
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
// Check maximum occupancy
if (ST.computeOccupancy(MF.getFuncti... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xcbb290
testb $0x1, %al
jne 0xcbb566
movb $0x0, 0x37(%rsp)
jmp 0xcbb668
movq 0x18(%rsp), %rax
movq 0x8(%rax), %rdi
addq $0x1740, %rdi # imm = 0x1740
callq 0xcbb440
testb $0x1, %al
jne 0xcbb59a
movq 0x18(%rsp), %rax
movq ... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::GCNSchedStage::checkScheduling() | void GCNSchedStage::checkScheduling() {
// Check the results of scheduling.
PressureAfter = DAG.getRealRegPressure(RegionIdx);
LLVM_DEBUG(dbgs() << "Pressure after scheduling: " << print(PressureAfter));
LLVM_DEBUG(dbgs() << "Region: " << RegionIdx << ".\n");
if (PressureAfter.getSGPRNum() <= S.SGPRCriticalL... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x130(%rsp)
movq 0x130(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x8(%rax), %rsi
movl 0x40(%rax), %edx
leaq 0x118(%rsp), %rdi
callq 0xcb9570
movq 0x40(%rsp), %rax
movq 0x118(%rsp), %rcx
movq %rcx, 0x78(%rax)
movq 0x120(%rsp), %rcx
movq %rcx, 0x80(%rax)
movq 0x128(%rsp)... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::ClusteredLowOccStage::shouldRevertScheduling(unsigned int) | bool ClusteredLowOccStage::shouldRevertScheduling(unsigned WavesAfter) {
if (PressureAfter == PressureBefore)
return false;
if (GCNSchedStage::shouldRevertScheduling(WavesAfter))
return true;
if (mayCauseSpilling(WavesAfter))
return true;
return false;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rsi
movq %rsi, 0x8(%rsp)
movq %rsi, %rdi
addq $0x78, %rdi
addq $0x60, %rsi
callq 0xcaa500
testb $0x1, %al
jne 0xcbeedd
jmp 0xcbeee4
movb $0x0, 0x27(%rsp)
jmp 0xcbef1f
movq 0x8(%rsp), %rdi
movl 0x14(%rsp), %esi
callq 0xcbeb80
testb $0x1, %al
... | /Target/AMDGPU/GCNSchedStrategy.cpp |
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