name string | code string | asm string | file string |
|---|---|---|---|
llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(llvm::CallLowering::CallLoweringInfo&, llvm::MachineFunction&, llvm::SmallVectorImpl<llvm::CallLowering::ArgInfo>&) const | bool AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(
CallLoweringInfo &Info, MachineFunction &MF,
SmallVectorImpl<ArgInfo> &InArgs) const {
const Function &CallerF = MF.getFunction();
CallingConv::ID CalleeCC = Info.CallConv;
CallingConv::ID CallerCC = CallerF.getCallingConv();
// If the calli... | subq $0x118, %rsp # imm = 0x118
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
movq %rdx, 0xf8(%rsp)
movq %rcx, 0xf0(%rsp)
movq 0x108(%rsp), %rax
movq %rax, (%rsp)
movq 0xf8(%rsp), %rdi
callq 0x727890
movq %rax, 0xe8(%rsp)
movq 0x100(%rsp), %rax
movl (%rax), %eax
movl %eax, 0xe4(%rsp)
movq 0xe8(%rsp), %rdi
ca... | /Target/AMDGPU/AMDGPUCallLowering.cpp |
addCallTargetOperands(llvm::MachineInstrBuilder&, llvm::MachineIRBuilder&, llvm::CallLowering::CallLoweringInfo&) | static bool addCallTargetOperands(MachineInstrBuilder &CallInst,
MachineIRBuilder &MIRBuilder,
AMDGPUCallLowering::CallLoweringInfo &Info) {
if (Info.Callee.isReg()) {
CallInst.addReg(Info.Callee.getReg());
CallInst.addImm(0);
} else if (In... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x58(%rsp), %rdi
addq $0x8, %rdi
callq 0x737b30
testb $0x1, %al
jne 0xf19657
jmp 0xf19698
movq 0x68(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x58(%rsp), %rdi
addq $0x8, %rdi
callq 0x72c500
movq 0x10(%rsp), %rdi
movl %eax, 0x54(%rsp)
m... | /Target/AMDGPU/AMDGPUCallLowering.cpp |
(anonymous namespace)::AMDGPUIncomingArgHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
auto &MFI = MIRBuilder.getMF().getFrameInfo();
// Byval is assumed to be writable memory, but other stack passed arguments
// are not.
... | subq $0xa8, %rsp
movq %r8, 0x94(%rsp)
movq %r9, 0x9c(%rsp)
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x8(%rax), %rdi
callq 0x7f4fa0
movq %rax, %rdi
callq 0x73fb60
movq %rax, 0x68(%rsp)
leaq 0x94(%rsp), %rdi
callq 0x8001f0
xor... | /Target/AMDGPU/AMDGPUCallLowering.cpp |
llvm::AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(llvm::AMDGPUTargetMachine&, llvm::CGPassBuilderOption const&, llvm::PassInstrumentationCallbacks*) | AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
AMDGPUTargetMachine &TM, const CGPassBuilderOption &Opts,
PassInstrumentationCallbacks *PIC)
: CodeGenPassBuilder(TM, Opts, PIC) {
Opt.RequiresCodeGenSCCOrder = true;
// Exceptions and StackMaps are not supported, so these passes will never do
// any... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq %rdx, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movq 0x18(%rsp), %rsi
movq 0x10(%rsp), %rdx
movq 0x8(%rsp), %rcx
callq 0xf1c900
movq (%rsp), %rdi
movb $0x1, 0x21(%rdi)
callq 0xf1ca50
addq $0x28, %rsp
retq
nopw (%rax,%rax)
| /Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp |
(anonymous namespace)::AMDGPUCodeGenPrepareImpl::divHasSpecialOptimization(llvm::BinaryOperator&, llvm::Value*, llvm::Value*) const | bool AMDGPUCodeGenPrepareImpl::divHasSpecialOptimization(BinaryOperator &I,
Value *Num,
Value *Den) const {
if (Constant *C = dyn_cast<Constant>(Den)) {
// Arbitrary constants get a better expansion a... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq %rcx, 0x40(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x40(%rsp), %rdi
callq 0x7b9680
movq %rax, 0x38(%rsp)
cmpq $0x0, 0x38(%rsp)
je 0xf24c87
movq 0x38(%rsp), %rdi
callq 0x782840
movq %rax, %rdi
callq 0x315d4a0
cmpl $0x2... | /Target/AMDGPU/AMDGPUCodeGenPrepare.cpp |
llvm::SmallDenseMap<std::pair<llvm::BasicBlock*, llvm::Value*>, llvm::Value*, 4u, llvm::DenseMapInfo<std::pair<llvm::BasicBlock*, llvm::Value*>, void>, llvm::detail::DenseMapPair<std::pair<llvm::BasicBlock*, llvm::Value*>, llvm::Value*>>::deallocateBuckets() | void deallocateBuckets() {
if (Small)
return;
deallocate_buffer(getLargeRep()->Buckets,
sizeof(BucketT) * getLargeRep()->NumBuckets,
alignof(BucketT));
getLargeRep()->~LargeRep();
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, 0x8(%rsp)
movl (%rax), %eax
andl $0x1, %eax
cmpl $0x0, %eax
je 0xf2e62f
jmp 0xf2e669
movq 0x8(%rsp), %rdi
callq 0xf2db90
movq 0x8(%rsp), %rdi
movq (%rax), %rax
movq %rax, (%rsp)
callq 0xf2db90
movq (%rsp), %rdi
movl 0x8(%rax), %eax
imulq $0x18, %ra... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUCodeGenPrepareImpl::promoteUniformOpToI32(llvm::SelectInst&) const | bool AMDGPUCodeGenPrepareImpl::promoteUniformOpToI32(SelectInst &I) const {
assert(needsPromotionToI32(I.getType()) &&
"I does not need promotion to i32");
IRBuilder<> Builder(&I);
Builder.SetCurrentDebugLocation(I.getDebugLoc());
Type *I32Ty = getI32Ty(Builder, I.getType());
Value *ExtOp1 = nullpt... | subq $0x268, %rsp # imm = 0x268
movq %rdi, 0x260(%rsp)
movq %rsi, 0x258(%rsp)
movq 0x260(%rsp), %rax
movq %rax, 0x78(%rsp)
movq 0x258(%rsp), %rax
movq %rax, 0x70(%rsp)
leaq 0x1b8(%rsp), %rdi
callq 0x7b2080
movq 0x70(%rsp), %rsi
movq 0x1b8(%rsp), %rcx
movq 0x1c0(%rsp), %r8
leaq 0x1c8(%rsp), %rdi
xorl %eax, %e... | /Target/AMDGPU/AMDGPUCodeGenPrepare.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayState, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayState>>, llvm::MachineBasicBlock*, (anonymous na... | void initEmpty() {
setNumEntries(0);
setNumTombstones(0);
assert((getNumBuckets() & (getNumBuckets()-1)) == 0 &&
"# initial buckets must be a power of two!");
const KeyT EmptyKey = getEmptyKey();
for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B)
::new (&B->getFirst... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
xorl %esi, %esi
callq 0xf385d0
movq (%rsp), %rdi
xorl %esi, %esi
callq 0xf385f0
callq 0xf38610
movq (%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0xf38620
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0xf38630
movq %rax, 0x8(%rsp)
movq 0x10(%rsp)... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>>, llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::Den... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x20(%rsp), %rsi
leaq 0x18(%rsp), %rdx
callq 0xeb3f20
testb $0x1, %al
jne 0xf396b2
movb $0x0, 0x37(%rsp)
jmp 0xf396f1
movq 0x18(%rsp), %rdi
callq 0xeb4610
callq 0xeb39c0
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo>>, unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::D... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x28(%rsp), %rsi
leaq 0x20(%rsp), %rdx
callq 0xf3ad40
testb $0x1, %al
jne 0xf39a4d
jmp 0xf39aab
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x547e50
testb $0x1, %al
jne 0xf39a62
jmp 0xf39a73
movq 0x18(%rs... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo>>, unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::D... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x20(%rsp), %rsi
leaq 0x18(%rsp), %rdx
callq 0xf3ad40
testb $0x1, %al
jne 0xf39ca2
movb $0x0, 0x37(%rsp)
jmp 0xf39cde
movq 0x18(%rsp), %rdi
callq 0xf389c0
callq 0xf38950
movl %eax, 0xc(%rsp)
movq 0x18(%rsp), %r... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUInsertDelayAlu::emitDelayAlu(llvm::MachineInstr&, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::MachineInstr*) | MachineInstr *emitDelayAlu(MachineInstr &MI, DelayInfo Delay,
MachineInstr *LastDelayAlu) {
unsigned Imm = 0;
// Wait for a TRANS instruction.
if (Delay.TRANSNum < DelayInfo::TRANS_MAX)
Imm |= 4 + Delay.TRANSNum;
// Wait for a VALU instruction (if it's more recent th... | subq $0xb8, %rsp
movl %edx, %eax
movl %eax, 0xaa(%rsp)
shrq $0x20, %rdx
movw %dx, %ax
movw %ax, 0xae(%rsp)
movq %rdi, 0xa0(%rsp)
movq %rsi, 0x98(%rsp)
movq %rcx, 0x90(%rsp)
movq 0xa0(%rsp), %rax
movq %rax, 0x20(%rsp)
movl $0x0, 0x8c(%rsp)
movzbl 0xad(%rsp), %eax
cmpl $0x4, %eax
jae 0xf39d65
movzbl 0xad(%rsp), %eax
addl... | /Target/AMDGPU/AMDGPUInsertDelayAlu.cpp |
(anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo::DelayInfo((anonymous namespace)::AMDGPUInsertDelayAlu::DelayType, unsigned int) | DelayInfo(DelayType Type, unsigned Cycles) {
switch (Type) {
default:
llvm_unreachable("unexpected type");
case VALU:
VALUCycles = Cycles;
VALUNum = 0;
break;
case TRANS:
TRANSCycles = Cycles;
TRANSNum = 0;
TRANSNumVALU = 0;
break;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movl %edx, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, (%rax)
movb $0x5, 0x1(%rax)
movb $0x0, 0x2(%rax)
movb $0x4, 0x3(%rax)
movb $0x5, 0x4(%rax)
movb $0x0, 0x5(%rax)
movl 0x1c(%rsp), %eax
movl %eax, 0x14(%rsp)
testl %eax, %eax
je 0xf3a0d... | /Target/AMDGPU/AMDGPUInsertDelayAlu.cpp |
llvm::DenseMap<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xf3a360
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xf3a3b0
testb $0x1, %al
jne 0xf3a336
jmp 0xf3a341
movq (%rsp), %rdi
callq 0xf3a420
jmp 0xf3a353
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::AMDGPUInsertDelayAlu::DelayInfo>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<unsigned int, (anonymous namesp... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | subq $0x88, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, 0x28(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movq 0x78(%rsp), %rsi
leaq 0x68(%rsp), %rdx
callq 0xf3ad40
testb $0x1, %al
jne 0xf3ac25
jmp 0xf3ac9f
movq 0x68(%rsp), %rax
movq %rax, 0x18(%rsp)
call... | /llvm/ADT/DenseMap.h |
llvm::PatternMatch::cstval_pred_ty<llvm::PatternMatch::is_any_zero_fp, llvm::ConstantFP, true>::cstval_pred_ty() | bool match_impl(ITy *V) {
if (const auto *CV = dyn_cast<ConstantVal>(V))
return this->isValue(CV->getValue());
if (const auto *VTy = dyn_cast<VectorType>(V->getType())) {
if (const auto *C = dyn_cast<Constant>(V)) {
if (const auto *CV = dyn_cast_or_null<ConstantVal>(C->getSplatValue()))
... | movq %rdi, -0x8(%rsp)
movq -0x8(%rsp), %rax
movq $0x0, (%rax)
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/IR/PatternMatch.h |
canSafelyConvertTo16Bit(llvm::Value&, bool) | static bool canSafelyConvertTo16Bit(Value &V, bool IsFloat) {
Type *VTy = V.getType();
if (VTy->isHalfTy() || VTy->isIntegerTy(16)) {
// The value is already 16-bit, so we don't want to convert to 16-bit again!
return false;
}
if (IsFloat) {
if (ConstantFP *ConstFloat = dyn_cast<ConstantFP>(&V)) {
... | subq $0xb8, %rsp
movb %sil, %al
movq %rdi, 0xa8(%rsp)
andb $0x1, %al
movb %al, 0xa7(%rsp)
movq 0xa8(%rsp), %rdi
callq 0x782840
movq %rax, 0x98(%rsp)
movq 0x98(%rsp), %rdi
callq 0x790930
testb $0x1, %al
jne 0xf46d69
movq 0x98(%rsp), %rdi
movl $0x10, %esi
callq 0x315c680
testb $0x1, %al
jne 0xf46d69
jmp 0xf46d76
movb $0x... | /Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp |
llvm::SmallVectorImpl<llvm::Value*>::erase(llvm::Value* const*) | iterator erase(const_iterator CI) {
// Just cast away constness because this is a non-const member function.
iterator I = const_cast<iterator>(CI);
assert(this->isReferenceToStorage(CI) && "Iterator to erase is out of bounds.");
iterator N = I;
// Shift all elts down one.
std::move(I+1, this->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x20(%rsp), %rax
addq $0x8, %rax
movq %rax, 0x8(%rsp)
callq 0x7a1a10
movq 0x8(%rsp), %rdi
movq %rax, %rsi
movq 0x20(%rsp),... | /llvm/ADT/SmallVector.h |
llvm::AMDGPUInstructionSelector::selectScratchSVAddr(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const {
Register Addr = Root.getReg();
Register PtrBase;
int64_t ConstOffset;
int64_t ImmOffset = 0;
// Match the immediate offset first, which canonically is moved as low as
// possible.
std::tie... | subq $0x348, %rsp # imm = 0x348
movq %rdi, 0x38(%rsp)
movq %rdi, %rax
movq %rax, 0x40(%rsp)
movq %rdi, 0x340(%rsp)
movq %rsi, 0x338(%rsp)
movq %rdx, 0x330(%rsp)
movq 0x338(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x330(%rsp), %rdi
callq 0x72c500
movl %eax, 0x32c(%rsp)
leaq 0x328(%rsp), %rdi
xorl %esi, %esi
cal... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectSWMMACIndex8(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectSWMMACIndex8(MachineOperand &Root) const {
Register Src =
getDefIgnoringCopies(Root.getReg(), *MRI)->getOperand(0).getReg();
unsigned Key = 0;
Register ShiftSrc;
std::optional<ValueAndVReg> ShiftAmt;
if (mi_match(Src, *MRI, m_GLSh... | subq $0x1c8, %rsp # imm = 0x1C8
movq %rdi, 0x18(%rsp)
movq %rdi, %rax
movq %rax, 0x20(%rsp)
movq %rdi, 0x1c0(%rsp)
movq %rsi, 0x1b8(%rsp)
movq %rdx, 0x1b0(%rsp)
movq 0x1b8(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x1b0(%rsp), %rdi
callq 0x72c500
movl %eax, %ecx
movq 0x28(%rsp), %rax
movl %ecx, 0x1a8(%rsp)
movq... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
MachineOperand &Root) const {
Register Src;
unsigned Mods;
bool Matched;
std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
if (!Matched)
return {};
return {{
[=](MachineInstrBuilder &MIB... | subq $0x158, %rsp # imm = 0x158
movq %rdi, 0x18(%rsp)
movq %rdi, %rax
movq %rax, 0x20(%rsp)
movq %rdi, 0x150(%rsp)
movq %rsi, 0x148(%rsp)
movq %rdx, 0x140(%rsp)
movq 0x148(%rsp), %rax
movq %rax, 0x28(%rsp)
leaq 0x13c(%rsp), %rdi
xorl %esi, %esi
callq 0x72e210
movq 0x28(%rsp), %rdi
movq 0x140(%rsp), %rsi
leaq... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing(
MachineOperand &Root) const {
Register Src;
unsigned Mods;
std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /*IsCanonicalizing=*/false);
return {{
[=](MachineInstrBuilder &MIB) {
MIB.addReg(copyT... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x20(%rsp)
movq %rdi, %rax
movq %rax, 0x10(%rsp)
movq %rdi, 0x180(%rsp)
movq %rsi, 0x178(%rsp)
movq %rdx, 0x170(%rsp)
movq 0x178(%rsp), %rax
movq %rax, 0x18(%rsp)
leaq 0x16c(%rsp), %rdi
xorl %esi, %esi
callq 0x72e210
movq 0x18(%rsp), %rdi
movq 0x170(%rsp), %rsi
xorl... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectPHI(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
const Register DefReg = I.getOperand(0).getReg();
const LLT DefTy = MRI->getType(DefReg);
// S1 G_PHIs should not be selected in instruction-select, instead:
// - divergent S1 G_PHI should go through lane mask merging algorithm
// and be fu... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x60(%rsp), %rdi
xorl %esi, %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x72c500
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x5c(%rsp)
movq 0x48(%rax), %rdi
movl 0x5c(%rsp), %eax
movl %eax, 0x4c(%rsp)
movl 0x... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
AMDGPUDAGToDAGISel::glueCopyToM0LDSInit(llvm::SDNode*) const | SDNode *AMDGPUDAGToDAGISel::glueCopyToM0LDSInit(SDNode *N) const {
unsigned AS = cast<MemSDNode>(N)->getAddressSpace();
if (AS == AMDGPUAS::LOCAL_ADDRESS) {
if (Subtarget->ldsRequiresM0Init())
return glueCopyToM0(N, CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
} else if (AS == AMDGPUAS::REGION_AD... | subq $0xf8, %rsp
movq %rdi, 0xe8(%rsp)
movq %rsi, 0xe0(%rsp)
movq 0xe8(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0xe0(%rsp), %rdi
callq 0x98ac20
movq %rax, %rdi
callq 0x9e24c0
movl %eax, 0xdc(%rsp)
cmpl $0x3, 0xdc(%rsp)
jne 0xf94169
movq 0x40(%rsp), %rax
movq 0x108(%rax), %rdi
callq 0xe51030
testb $0x1, %al
jne 0xf94098
j... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
SDLoc SL(N);
// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
SDValue Ops[10];
SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
SelectVOP3Mods(N->get... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x160(%rsp)
movq %rsi, 0x158(%rsp)
movq 0x160(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x158(%rsp), %rsi
leaq 0x148(%rsp), %rdi
callq 0x9817d0
leaq 0xa0(%rsp), %rax
movq %rax, %rcx
addq $0xa0, %rcx
movq %rcx, 0x38(%rsp)
movq %rax, 0x40(%rsp)
movq 0x40(%rsp), %rdi
movq... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::getBFE32(bool, llvm::SDLoc const&, llvm::SDValue, unsigned int, unsigned int) | SDNode *AMDGPUDAGToDAGISel::getBFE32(bool IsSigned, const SDLoc &DL,
SDValue Val, uint32_t Offset,
uint32_t Width) {
if (Val->isDivergent()) {
unsigned Opcode = IsSigned ? AMDGPU::V_BFE_I32_e64 : AMDGPU::V_BFE_U32_e64;
SDValue Off = Cur... | subq $0x208, %rsp # imm = 0x208
movb %sil, %al
movl 0x210(%rsp), %esi
movq %rcx, 0x1f0(%rsp)
movl %r8d, 0x1f8(%rsp)
movq %rdi, 0x1e8(%rsp)
andb $0x1, %al
movb %al, 0x1e7(%rsp)
movq %rdx, 0x1d8(%rsp)
movl %r9d, 0x1d4(%rsp)
movq 0x1e8(%rsp), %rax
movq %rax, 0xc0(%rsp)
leaq 0x1f0(%rsp), %rdi
callq 0x988cf0
movq... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(SDNode *N) {
unsigned IntrID = N->getConstantOperandVal(1);
switch (IntrID) {
case Intrinsic::amdgcn_ds_gws_init:
case Intrinsic::amdgcn_ds_gws_barrier:
case Intrinsic::amdgcn_ds_gws_sema_v:
case Intrinsic::amdgcn_ds_gws_sema_br:
case Intrinsic::amdgcn_ds_gws_... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %rdi
movl $0x1, %esi
callq 0x981a80
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addl $0xfffff837, %eax # imm = 0xFFFFF837
subl $0x5, %eax
ja 0xf9a2e0
jmp 0xf9a2cb
movq 0x8(%rsp), %rdi
movq 0x18... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectSTACKRESTORE(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectSTACKRESTORE(SDNode *N) {
SDValue SrcVal = N->getOperand(1);
if (SrcVal.getValueType() != MVT::i32) {
SelectCode(N); // Emit default error
return;
}
SDValue CopyVal;
Register SP = TLI->getStackPointerRegisterToSaveRestore();
SDLoc SL(N);
if (SrcVal.getOpcode() == A... | subq $0x1d8, %rsp # imm = 0x1D8
movq %rdi, 0x1d0(%rsp)
movq %rsi, 0x1c8(%rsp)
movq 0x1d0(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x1c8(%rsp), %rdi
movl $0x1, %esi
callq 0x981ab0
movq (%rax), %rcx
movq %rcx, 0x1b8(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x1c0(%rsp)
leaq 0x1b8(%rsp), %rdi
callq 0x98a410
movb %al,... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectADDRIndirect(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
SDValue &Offset) {
ConstantSDNode *C;
SDLoc DL(Addr);
if ((C = dyn_cast<ConstantSDNode>(Addr))) {
Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
Offset = CurDAG->getTarget... | subq $0x1d8, %rsp # imm = 0x1D8
movq %rsi, 0x1c8(%rsp)
movl %edx, 0x1d0(%rsp)
movq %rdi, 0x1c0(%rsp)
movq %rcx, 0x1b8(%rsp)
movq %r8, 0x1b0(%rsp)
movq 0x1c0(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0x1c8(%rsp), %rax
movq %rax, 0x188(%rsp)
movq 0x1d0(%rsp), %rax
movq %rax, 0x190(%rsp)
movq 0x188(%rsp), %rsi
mov... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectGlobalSAddr(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
SDValue Addr,
SDValue &SAddr,
SDValue &VOffset,
SDValue &Offset) const {
int64_t ImmOffset =... | subq $0x418, %rsp # imm = 0x418
movq 0x420(%rsp), %rax
movq %rdx, 0x400(%rsp)
movl %ecx, 0x408(%rsp)
movq %rdi, 0x3f8(%rsp)
movq %rsi, 0x3f0(%rsp)
movq %r8, 0x3e8(%rsp)
movq %r9, 0x3e0(%rsp)
movq 0x3f8(%rsp), %rax
movq %rax, 0x108(%rsp)
movq $0x0, 0x3d8(%rsp)
leaq 0x3c8(%rsp), %rdi
callq 0x98b9c0
leaq 0x3b8(... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::isSOffsetLegalWithImmOffset(llvm::SDValue*, bool, bool, long) const | bool AMDGPUDAGToDAGISel::isSOffsetLegalWithImmOffset(SDValue *SOffset,
bool Imm32Only,
bool IsBuffer,
int64_t ImmOffset) const {
if (!IsBuffer && !Imm32Only &&... | subq $0x88, %rsp
movb %cl, %al
movb %dl, %cl
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
andb $0x1, %cl
movb %cl, 0x6f(%rsp)
andb $0x1, %al
movb %al, 0x6e(%rsp)
movq %r8, 0x60(%rsp)
movq 0x78(%rsp), %rax
movq %rax, 0x10(%rsp)
testb $0x1, 0x6e(%rsp)
jne 0xfa38aa
testb $0x1, 0x6f(%rsp)
jne 0xfa38aa
cmpq $0x0, 0x60(%rsp)
... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectMOVRELOffset(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
SDValue &Base,
SDValue &Offset) const {
SDLoc DL(Index);
if (CurDAG->isBaseWithConstantOffset(Index)) {
SDValue N0 = Index.getOperand(0);
SDValue N1 = Index.get... | subq $0x128, %rsp # imm = 0x128
movq %rsi, 0x110(%rsp)
movl %edx, 0x118(%rsp)
movq %rdi, 0x108(%rsp)
movq %rcx, 0x100(%rsp)
movq %r8, 0xf8(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x110(%rsp), %rax
movq %rax, 0xd8(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0xe0(%rsp)
movq 0xd8(%rsp), %rsi
movl 0x... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectSWMMACIndex8(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectSWMMACIndex8(SDValue In, SDValue &Src,
SDValue &IndexKey) const {
unsigned Key = 0;
Src = In;
if (In.getOpcode() == ISD::SRL) {
const llvm::SDValue &ShiftSrc = In.getOperand(0);
ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(... | subq $0xf8, %rsp
movq %rsi, 0xe8(%rsp)
movl %edx, 0xf0(%rsp)
movq %rdi, 0xe0(%rsp)
movq %rcx, 0xd8(%rsp)
movq %r8, 0xd0(%rsp)
movq 0xe0(%rsp), %rax
movq %rax, 0x28(%rsp)
movl $0x0, 0xcc(%rsp)
movq 0xd8(%rsp), %rax
movq 0xe8(%rsp), %rcx
movq %rcx, (%rax)
movl 0xf0(%rsp), %ecx
movl %ecx, 0x8(%rax)
leaq 0xe8(%rsp), %rdi
c... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::isVGPRImm(llvm::SDNode const*) const | bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
assert(CurDAG->getTarget().getTargetTriple().getArch() == Triple::amdgcn);
const SIRegisterInfo *SIRI =
static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
const SIInstrInfo * SII =
static_cast<const SIInstrInfo *>(Subtarget->get... | subq $0xa8, %rsp
movq %rdi, 0x98(%rsp)
movq %rsi, 0x90(%rsp)
movq 0x98(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x108(%rax), %rdi
callq 0xbf62f0
movq %rax, %rcx
movq 0x28(%rsp), %rax
movq %rcx, 0x88(%rsp)
movq 0x108(%rax), %rdi
callq 0xbdd4d0
movq %rax, 0x80(%rsp)
movl $0x0, 0x7c(%rsp)
movb $0x1, 0x7b(%rsp)
movq 0x90(%rs... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
SDValue LHS, SDValue RHS,
SDValue True, SDValue False,
SDValue CC,
... | subq $0x278, %rsp # imm = 0x278
movq %rsi, %rax
movq 0x2c0(%rsp), %rsi
leaq 0x2b0(%rsp), %rsi
movq %rsi, 0x50(%rsp)
leaq 0x2a0(%rsp), %rsi
movq %rsi, 0x58(%rsp)
leaq 0x290(%rsp), %rsi
movq %rsi, 0x60(%rsp)
leaq 0x280(%rsp), %r10
movq %r10, 0x68(%rsp)
movb %dl, 0x258(%rsp)
movq %rcx, 0x260(%rsp)
movq %r8, 0x2... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(llvm::SDValue, llvm::SelectionDAG&, bool) const | SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
bool Signed) const {
// The regular method converting a 64-bit integer to float roughly consists of
// 2 steps: normalization and rounding. In fact, after normalization, the
// conversion f... | subq $0xa98, %rsp # imm = 0xA98
movb %r8b, %al
movq %rsi, 0xa78(%rsp)
movl %edx, 0xa80(%rsp)
movq %rdi, 0xa70(%rsp)
movq %rcx, 0xa68(%rsp)
andb $0x1, %al
movb %al, 0xa67(%rsp)
movq 0xa70(%rsp), %rax
movq %rax, 0x198(%rsp)
movq 0xa78(%rsp), %rax
movq %rax, 0xa40(%rsp)
movq 0xa80(%rsp), %rax
movq %rax, 0xa48(%... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::performLoadCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
if (!DCI.isBeforeLegalize())
return SDValue();
LoadSDNode *LN = cast<LoadSDNode>(N);
if (!LN->isSimple() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
return SDVa... | subq $0x2f8, %rsp # imm = 0x2F8
movq %rdi, 0x2e0(%rsp)
movq %rsi, 0x2d8(%rsp)
movq %rdx, 0x2d0(%rsp)
movq 0x2e0(%rsp), %rax
movq %rax, 0x88(%rsp)
movq 0x2d0(%rsp), %rdi
callq 0xa9a240
testb $0x1, %al
jne 0xfe5ea6
leaq 0x2e8(%rsp), %rdi
xorl %esi, %esi
movl $0x10, %edx
callq 0x348990
leaq 0x2e8(%rsp), %rdi
ca... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::performCtlz_CttzCombine(llvm::SDLoc const&, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
SDValue LHS, SDValue RHS,
DAGCombinerInfo &DCI) const {
if (!isNullConstant(Cond.getOperand(1)))
return SDValue();
SelectionDAG ... | subq $0xf8, %rsp
movq 0x110(%rsp), %rax
leaq 0x100(%rsp), %rax
movq %rax, (%rsp)
movq %rdx, 0xd8(%rsp)
movl %ecx, 0xe0(%rsp)
movq %r8, 0xc8(%rsp)
movl %r9d, 0xd0(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0xd8(%rsp), %rdi
movl $0x1, %esi
callq 0x98cd00
movq (%rax),... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::performSelectCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
return Folded;
SDValue Cond = N->getOperand(0);
if (Cond.getOpcode() != ISD::SETCC)
return SDValue(... | subq $0x318, %rsp # imm = 0x318
movq %rdi, 0x300(%rsp)
movq %rsi, 0x2f8(%rsp)
movq %rdx, 0x2f0(%rsp)
movq 0x300(%rsp), %rax
movq %rax, 0x70(%rsp)
movq 0x2f0(%rsp), %rax
movq %rax, 0x78(%rsp)
movq 0x2f8(%rsp), %rsi
leaq 0x2e0(%rsp), %rdi
xorl %edx, %edx
callq 0x981ae0
movq 0x70(%rsp), %rdi
movq 0x78(%rsp), %r... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::performRcpCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
if (!CFP)
return SDValue();
// XXX - Should this flush denormals?
const APFloat &Val = CFP->getValueAPF();... | subq $0xe8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq %rdx, 0xc0(%rsp)
movq 0xc8(%rsp), %rdi
xorl %esi, %esi
callq 0x981ab0
movq %rax, %rdi
callq 0x9a36f0
movq %rax, 0xb8(%rsp)
cmpq $0x0, 0xb8(%rsp)
jne 0xff1a8f
leaq 0xd8(%rsp), %rdi
xorl %esi, %esi
movl $0x10, %edx
callq 0x348990
leaq 0xd8(%rsp), %rdi
call... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::APFloat::add(llvm::APFloat const&, llvm::RoundingMode) | opStatus add(const APFloat &RHS, roundingMode RM) {
assert(&getSemantics() == &RHS.getSemantics() &&
"Should only call on two APFloats with the same semantics");
if (usesLayout<IEEEFloat>(getSemantics()))
return U.IEEE.add(RHS.U.IEEE, RM);
if (usesLayout<DoubleAPFloat>(getSemantics()))
... | subq $0x28, %rsp
movb %dl, %al
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movb %al, 0xf(%rsp)
movq 0x18(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x41c790
movq %rax, %rdi
callq 0x41c730
testb $0x1, %al
jne 0xff3f60
jmp 0xff3f81
movq (%rsp), %rdi
addq $0x8, %rdi
movq 0x10(%rsp), %rsi
addq $0x8, %rsi
movsbl 0xf(%rsp), %edx
ca... | /llvm/ADT/APFloat.h |
fnegFoldsIntoOpcode(unsigned int) | LLVM_READNONE
static bool fnegFoldsIntoOpcode(unsigned Opc) {
switch (Opc) {
case ISD::FADD:
case ISD::FSUB:
case ISD::FMUL:
case ISD::FMA:
case ISD::FMAD:
case ISD::FMINNUM:
case ISD::FMAXNUM:
case ISD::FMINNUM_IEEE:
case ISD::FMAXNUM_IEEE:
case ISD::FMINIMUM:
case ISD::FMAXIMUM:
case ISD::SE... | movl %edi, -0x8(%rsp)
movl -0x8(%rsp), %eax
movl %eax, -0xc(%rsp)
addl $-0x60, %eax
subl $0x3, %eax
jb 0xff9142
jmp 0xff907a
movl -0xc(%rsp), %eax
addl $0xffffff6b, %eax # imm = 0xFFFFFF6B
subl $0x2, %eax
jb 0xff9142
jmp 0xff908e
movl -0xc(%rsp), %eax
subl $0x99, %eax
je 0xff9142
jmp 0xff909f
movl -0xc(%rsp), %ea... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
(anonymous namespace)::AMDGPULateCodeGenPrepare::runOnFunction(llvm::Function&) | bool AMDGPULateCodeGenPrepare::runOnFunction(Function &F) {
if (skipFunction(F))
return false;
const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
const TargetMachine &TM = TPC.getTM<TargetMachine>();
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
AC = &getAnalysis<AssumptionCache... | subq $0x1a8, %rsp # imm = 0x1A8
movq %rdi, 0x198(%rsp)
movq %rsi, 0x190(%rsp)
movq 0x198(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x190(%rsp), %rsi
callq 0x312ea30
testb $0x1, %al
jne 0xffa2b7
jmp 0xffa2c4
movb $0x0, 0x1a7(%rsp)
jmp 0xffa584
movq 0x18(%rsp), %rdi
callq 0x882750
movq %rax, 0x188(%rsp)
movq 0x18... | /Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp |
llvm::InstVisitor<(anonymous namespace)::AMDGPULateCodeGenPrepare, bool>::visit(llvm::Instruction&) | RetTy visit(Instruction &I) {
static_assert(std::is_base_of<InstVisitor, SubClass>::value,
"Must pass the derived type to this template!");
switch (I.getOpcode()) {
default: llvm_unreachable("Unknown instruction type encountered!");
// Build the switch statement using the Instructio... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
movq 0x10(%rsp), %rdi
callq 0x785480
decl %eax
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rax
leaq 0x58cfb1c(%rip), %rcx # 0x68ca6d0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq (%rsp), %rdi
movq 0x10(%rsp), ... | /llvm/IR/InstVisitor.h |
llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xffc7a0
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xffc7f0
testb $0x1, %al
jne 0xffc776
jmp 0xffc781
movq (%rsp), %rdi
callq 0xffc860
jmp 0xffc793
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::BasicBlock*, llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::DenseMap<llvm::Value const*, ll... | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xffca60
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xffcab0
testb $0x1, %al
jne 0xffca36
jmp 0xffca41
movq (%rsp), %rdi
callq 0xffcb20
jmp 0xffca53
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::BasicBlock*, llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::DenseMap<llvm::Value const*, ll... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>::... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xffc9e0
cmpl $0x0, %eax
jne 0x10036f2
jmp 0x100378a
callq 0xffc920
movq %rax, 0x28(%rsp)
callq 0x1001af0
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0xffc930
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0xffc940
movq %rax,... | /llvm/ADT/DenseMap.h |
llvm::AMDGPULegalizerInfo::legalizeFPTOI(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineIRBuilder&, bool) const | bool AMDGPULegalizerInfo::legalizeFPTOI(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B,
bool Signed) const {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperan... | subq $0x6d8, %rsp # imm = 0x6D8
movb %r8b, %al
movq %rdi, 0x6d0(%rsp)
movq %rsi, 0x6c8(%rsp)
movq %rdx, 0x6c0(%rsp)
movq %rcx, 0x6b8(%rsp)
andb $0x1, %al
movb %al, 0x6b7(%rsp)
movq 0x6c8(%rsp), %rdi
xorl %esi, %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x72c500
movl %eax, 0x6b0(%rsp)
movq 0x6c8(%rsp), %rdi
mo... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeSignedDIV_REM(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
const LLT S64 = LLT::scalar(64);
const LLT S32 = LLT::scalar(32);
LLT Ty = MRI.getType(MI.getOpe... | subq $0x748, %rsp # imm = 0x748
movq %rdi, 0x738(%rsp)
movq %rsi, 0x730(%rsp)
movq %rdx, 0x728(%rsp)
movq %rcx, 0x720(%rsp)
movq 0x738(%rsp), %rax
movq %rax, 0x140(%rsp)
movl $0x40, %edi
callq 0x7f5450
movq %rax, 0x718(%rsp)
movl $0x20, %edi
callq 0x7f5450
movq %rax, 0x710(%rsp)
movq 0x728(%rsp), %rax
movq %... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeMul(llvm::LegalizerHelper&, llvm::MachineInstr&) const | bool AMDGPULegalizerInfo::legalizeMul(LegalizerHelper &Helper,
MachineInstr &MI) const {
assert(ST.hasMad64_32());
assert(MI.getOpcode() == TargetOpcode::G_MUL);
MachineIRBuilder &B = Helper.MIRBuilder;
MachineRegisterInfo &MRI = *B.getMRI();
Register DstReg = MI.getOpe... | pushq %rbx
subq $0x240, %rsp # imm = 0x240
movq %rdi, 0x238(%rsp)
movq %rsi, 0x230(%rsp)
movq %rdx, 0x228(%rsp)
movq 0x238(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x230(%rsp), %rax
movq (%rax), %rax
movq %rax, 0x220(%rsp)
movq 0x220(%rsp), %rdi
callq 0x800310
movq %rax, 0x218(%rsp)
movq 0x228(%rsp), %rdi
xorl... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(llvm::MachineIRBuilder&, llvm::Register, llvm::Register, llvm::Register, llvm::Register) const | void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B,
Register DstDivReg,
Register DstRemReg,
Register X,
... | subq $0xa38, %rsp # imm = 0xA38
movl %edx, 0xa34(%rsp)
movl %ecx, 0xa30(%rsp)
movl %r8d, 0xa2c(%rsp)
movl %r9d, 0xa28(%rsp)
movq %rdi, 0xa20(%rsp)
movq %rsi, 0xa18(%rsp)
movl $0x1, %edi
callq 0x7f5450
movq %rax, 0xa10(%rsp)
movl $0x20, %edi
callq 0x7f5450
movq %rax, 0xa08(%rsp)
movq 0xa18(%rsp), %rax
movq %r... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(llvm::MachineInstr&, llvm::MachineIRBuilder&, llvm::GISelChangeObserver&, llvm::AMDGPU::ImageDimIntrinsicInfo const*) const | bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer,
const AMDGPU::ImageDimIntrinsicInfo *Intr) const {
const MachineFunction &MF = *MI.getMF();
const unsigned NumDefs = MI.getNumExplicitDefs();
const unsigned ArgOffset = NumDefs + 1;
b... | subq $0x9a8, %rsp # imm = 0x9A8
movq %rdi, 0x998(%rsp)
movq %rsi, 0x990(%rsp)
movq %rdx, 0x988(%rsp)
movq %rcx, 0x980(%rsp)
movq %r8, 0x978(%rsp)
movq 0x998(%rsp), %rax
movq %rax, 0x158(%rsp)
movq 0x990(%rsp), %rdi
callq 0x741a30
movq %rax, 0x970(%rsp)
movq 0x990(%rsp), %rdi
callq 0x341b500
movl %eax, 0x96c(... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
isSmallOddVector(unsigned int)::$_0::operator()(llvm::LegalityQuery const&) const | static LegalityPredicate isSmallOddVector(unsigned TypeIdx) {
return [=](const LegalityQuery &Query) {
const LLT Ty = Query.Types[TypeIdx];
if (!Ty.isVector())
return false;
const LLT EltTy = Ty.getElementType();
const unsigned EltSize = EltTy.getSizeInBits();
return Ty.getNumElements() % 2... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq 0x60(%rsp), %rdi
addq $0x8, %rdi
movl (%rax), %eax
movl %eax, %esi
callq 0x86a550
movq (%rax), %rax
movq %rax, 0x58(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x7f5550
testb $0x1, %al
jne 0x1041e35
movb $0x0, 0x77(%rsp)
jmp 0x1041ef9
leaq 0x... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULibCalls::fold(llvm::CallInst*) | bool AMDGPULibCalls::fold(CallInst *CI) {
Function *Callee = CI->getCalledFunction();
// Ignore indirect calls.
if (!Callee || Callee->isIntrinsic() || CI->isNoBuiltin())
return false;
FuncInfo FInfo;
if (!parseFunctionName(Callee->getName(), FInfo))
return false;
// Further check the number of ar... | subq $0x358, %rsp # imm = 0x358
movq %rdi, 0x348(%rsp)
movq %rsi, 0x340(%rsp)
movq 0x348(%rsp), %rax
movq %rax, 0xb8(%rsp)
movq 0x340(%rsp), %rdi
callq 0x7893a0
movq %rax, 0x338(%rsp)
cmpq $0x0, 0x338(%rsp)
je 0x105138b
movq 0x338(%rsp), %rdi
callq 0x78bb20
testb $0x1, %al
jne 0x105138b
movq 0x340(%rsp), %rd... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::AMDGPULibCalls::TDOFold(llvm::CallInst*, llvm::AMDGPULibFunc const&) | bool AMDGPULibCalls::TDOFold(CallInst *CI, const FuncInfo &FInfo) {
// Table-Driven optimization
const TableRef tr = getOptTable(FInfo.getId());
if (tr.empty())
return false;
int const sz = (int)tr.size();
Value *opr0 = CI->getArgOperand(0);
if (getVecSize(FInfo) > 1) {
if (ConstantDataVector *CV ... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x128(%rsp)
movq %rsi, 0x120(%rsp)
movq %rdx, 0x118(%rsp)
movq 0x118(%rsp), %rdi
callq 0x1050bd0
movl %eax, %edi
callq 0x10561f0
movq %rax, 0x108(%rsp)
movq %rdx, 0x110(%rsp)
leaq 0x108(%rsp), %rdi
callq 0x10564f0
testb $0x1, %al
jne 0x1052476
jmp 0x1052483
movb $0x... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::SmallVector<llvm::IntrinsicInst*, 4u>& llvm::SmallVectorTemplateBase<llvm::SmallVector<llvm::IntrinsicInst*, 4u>, false>::growAndEmplaceBack<int, llvm::IntrinsicInst*&>(int&&, llvm::IntrinsicInst*&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %eax, %eax
movl %eax, %esi
leaq 0x18(%rsp), %rdx
callq 0x105c780
movq 0x8(%rsp), %rdi
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
callq 0x3a8dca0
movq (%rsp), %rdi
imulq $... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::SplitPtrStructs::visitIntToPtrInst(llvm::IntToPtrInst&) | PtrParts SplitPtrStructs::visitIntToPtrInst(IntToPtrInst &IP) {
if (!isSplitFatPtr(IP.getType()))
return {nullptr, nullptr};
IRB.SetInsertPoint(&IP);
const DataLayout &DL = IP.getDataLayout();
unsigned RsrcPtrWidth = DL.getPointerSizeInBits(AMDGPUAS::BUFFER_RESOURCE);
Value *Int = IP.getOperand(0);
Type... | subq $0x208, %rsp # imm = 0x208
movq %rdi, 0x1f0(%rsp)
movq %rsi, 0x1e8(%rsp)
movq 0x1f0(%rsp), %rax
movq %rax, 0x78(%rsp)
movq 0x1e8(%rsp), %rdi
callq 0x782840
movq %rax, %rdi
callq 0x1073fa0
testb $0x1, %al
jne 0x1076c67
movq $0x0, 0x1e0(%rsp)
movq $0x0, 0x1d8(%rsp)
leaq 0x1f8(%rsp), %rdi
leaq 0x1e0(%rsp),... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
getInsertPt(llvm::BasicBlock&) | static BasicBlock::iterator getInsertPt(BasicBlock &BB) {
BasicBlock::iterator InsPt = BB.getFirstInsertionPt();
for (BasicBlock::iterator E = BB.end(); InsPt != E; ++InsPt) {
AllocaInst *AI = dyn_cast<AllocaInst>(&*InsPt);
// If this is a dynamic alloca, the value may depend on the loaded kernargs,
//... | subq $0x58, %rsp
movq %rdi, 0x40(%rsp)
movq 0x40(%rsp), %rdi
callq 0x7e52a0
movq %rdx, 0x38(%rsp)
movq %rax, 0x30(%rsp)
movw 0x38(%rsp), %ax
movw %ax, 0x50(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x40(%rsp), %rdi
callq 0x7b1b70
movq %rdx, 0x18(%rsp)
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, ... | /Target/AMDGPU/AMDGPULowerKernelArguments.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>>, llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm:... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x10874f0
testb $0x1, %al
jne 0x1087536
jmp 0x10875a2
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>, false>::DenseMapIterator(llvm::detail::DenseSetPair<llvm::GlobalVariable*>*, llvm::detail::DenseSetPair<llvm::GlobalVariable*>*, llvm::DebugEpoch... | DenseMapIterator(pointer Pos, pointer E, const DebugEpochBase &Epoch,
bool NoAdvance = false)
: DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) {
assert(isHandleInSync() && "invalid construction!");
if (NoAdvance) return;
if (shouldReverseIterate<KeyT>()) {
RetreatPastEm... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x5481a0
movq 0x8(%rsp), %rax
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq 0x20(%rsp), %rcx
m... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>, false>::AdvancePastEmptyBuckets() | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xc35f50
movq %rax, 0x18(%rsp)
callq 0xc3ad20
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x1087818
movq 0x8(%rsp), %rax
movq (%rax), %rdi
callq 0x1087840
... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::Function*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseSetPair<llvm::Function*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::De... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | subq $0x88, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, 0x28(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movq 0x78(%rsp), %rsi
leaq 0x68(%rsp), %rdx
callq 0x7e1e50
testb $0x1, %al
jne 0x1089f35
jmp 0x1089faf
movq 0x68(%rsp), %rax
movq %rax, 0x18(%rsp)
ca... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0x1091690
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0x10916e0
testb $0x1, %al
jne 0x1091666
jmp 0x1091671
movq (%rsp), %rdi
callq 0x1091750
jmp 0x1091683
movq (%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>, llvm::Function*, (anonymous namespace)::AM... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0x10916ae
movl $0x0, 0x14(%rsp)
jmp 0x10916ce
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>>, llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x1089c70
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0x1087850
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0x1091a82
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rs... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>, llvm::Function*, (anonymous namespace... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x10920f0
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0x10918d0
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0x1091fa2
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rs... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>, llvm::Function*, (anonymous namespace)::AM... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdx, 0x50(%rsp)
movq 0x60(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x1091750
callq 0x1091810
movq %rax, 0x48(%rsp)
callq 0x1092100
movq %rax, 0x40(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x38(%rs... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>>, llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm:... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x1088390
callq 0x1088450
movq %rax, 0x38(%rsp)
callq 0x1089cc0
movq %rax, 0x30(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x28(%rsp... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUMachineCFGStructurizer::structurizeRegions((anonymous namespace)::RegionMRT*, bool) | bool AMDGPUMachineCFGStructurizer::structurizeRegions(RegionMRT *Region,
bool isTopRegion) {
bool Changed = false;
auto Children = Region->getChildren();
for (auto *CI : *Children) {
if (CI->isRegion()) {
Changed |= structurizeRegions(CI->getRegionMRT(), ... | subq $0x48, %rsp
movb %dl, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
andb $0x1, %al
movb %al, 0x37(%rsp)
movq 0x40(%rsp), %rax
movq %rax, (%rsp)
movb $0x0, 0x36(%rsp)
movq 0x38(%rsp), %rdi
callq 0x10a2180
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rdi
callq 0x109fdf0
movq ... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>, llvm::MachineBasicBlo... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x109e9c0
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x109da30
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
getSingleExitNode(llvm::MachineFunction&) | static MachineBasicBlock *getSingleExitNode(MachineFunction &MF) {
MachineBasicBlock *result = nullptr;
for (auto &MFI : MF) {
if (MFI.succ_empty()) {
if (result == nullptr) {
result = &MFI;
} else {
return nullptr;
}
}
}
return result;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq $0x0, 0x20(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x18(%rsp), %rdi
callq 0x7edfc0
movq %rax, 0x10(%rsp)
movq 0x18(%rsp), %rdi
callq 0x7edff0
movq %rax, 0x8(%rsp)
leaq 0x10(%rsp), %rdi
leaq 0x8(%rsp), %rsi
callq 0x7ee020
testb $0x1, %al
jne 0x10a3f5f
jmp 0x10a3... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
(anonymous namespace)::LinearizedRegion::storeMBBLiveOuts(llvm::MachineBasicBlock*, llvm::MachineRegisterInfo const*, llvm::TargetRegisterInfo const*, (anonymous namespace)::PHILinearize&, (anonymous namespace)::RegionMRT*) | void LinearizedRegion::storeMBBLiveOuts(MachineBasicBlock *MBB,
const MachineRegisterInfo *MRI,
const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo,
RegionMRT ... | subq $0xe8, %rsp
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
movq %rdx, 0xd0(%rsp)
movq %rcx, 0xc8(%rsp)
movq %r8, 0xc0(%rsp)
movq %r9, 0xb8(%rsp)
movq 0xe0(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0xd8(%rsp), %rax
movq %rax, 0xb0(%rsp)
movq 0xb0(%rsp), %rdi
callq 0x73fe80
movq %rax, 0xa8(%rsp)
movq 0xb0(%rsp), %rdi
call... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::DenseMap<std::pair<unsigned int, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<unsigned int, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<unsigned int, llvm::MachineBasicBlock*>>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0x10a7387
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0x10a73af
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
sh... | /llvm/ADT/DenseMap.h |
removeExternalCFGEdges(llvm::MachineBasicBlock*, llvm::MachineBasicBlock*) | static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
MachineBasicBlock *EndMBB) {
// We have to check against the StartMBB successor because a
// structurized region with a loop will have the entry block split,
// and the backedge will go to the entry successor.
De... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x130(%rsp)
movq %rsi, 0x128(%rsp)
leaq 0x110(%rsp), %rdi
callq 0x10aab60
movq 0x130(%rsp), %rdi
callq 0x8fe220
movl %eax, 0x10c(%rsp)
cmpl $0x0, 0x10c(%rsp)
jbe 0x10aa970
movq 0x130(%rsp), %rdi
callq 0x8fe240
movq %rax, 0xf8(%rsp)
leaq 0xf8(%rsp), %rdi
callq 0x8ff6... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::DenseMapIterator<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>, false>::RetreatPastEmptyB... | void RetreatPastEmptyBuckets() {
assert(Ptr >= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr[-1].getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr[-1].getFirst(), Tombstone)))
-... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0x10aafe0
movq %rax, 0x20(%rsp)
movq %rdx, 0x28(%rsp)
callq 0x10ab6b0
movq %rax, 0x10(%rsp)
movq %rdx, 0x18(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x10ab88a
movq 0x8(... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<unsigned int, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseSetPair<unsigned int>, false>::operator++() | inline DenseMapIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
assert(Ptr != End && "incrementing end() iterator");
if (shouldReverseIterate<KeyT>()) {
--Ptr;
RetreatPastEmptyBuckets();
return *this;
}
++Ptr;
AdvancePastEmptyBuc... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0x547e50
testb $0x1, %al
jne 0x10acddd
jmp 0x10acdfb
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x4, %rax
movq %rax, (%rdi)
callq 0x5481b0
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0x10ace17
movq (%rsp), %rdi
movq (%rdi), %rax
addq $0x... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, unsigned int) | void AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(MachineBasicBlock *CodeBB,
MachineBasicBlock *MergeBB,
unsigned BBSelectReg) {
MachineBasicBlock *TrueBB = nullptr;
MachineBasicBlock *FalseBB = nullpt... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x230(%rsp)
movq %rsi, 0x228(%rsp)
movq %rdx, 0x220(%rsp)
movl %ecx, 0x21c(%rsp)
movq 0x230(%rsp), %rax
movq %rax, 0xc8(%rsp)
movq $0x0, 0x210(%rsp)
movq $0x0, 0x208(%rsp)
leaq 0x1d8(%rsp), %rdi
callq 0xb4e940
movq 0xc8(%rsp), %rdi
addq $0x88, %rdi
leaq 0x228(%rsp),... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
(anonymous namespace)::IGroupLPDAGMutation::apply(llvm::ScheduleDAGInstrs*) | void IGroupLPDAGMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel();
if (!TSchedModel || DAGInstrs->SUnits.empty())
return;
LLVM_DEBUG(dbgs() << "Applying IGroupLPDAGMutation...\n");
const GCNSubtarget &ST = DAGInstrs->MF.getSubtarget<GCNSubtarge... | subq $0x3528, %rsp # imm = 0x3528
movq %rdi, 0x3520(%rsp)
movq %rsi, 0x3518(%rsp)
movq 0x3520(%rsp), %rax
movq %rax, (%rsp)
movq 0x3518(%rsp), %rdi
callq 0xc06790
movq %rax, 0x3510(%rsp)
cmpq $0x0, 0x3510(%rsp)
je 0x10b214a
movq 0x3518(%rsp), %rdi
addq $0x30, %rdi
callq 0xc067b0
testb $0x1, %al
jne 0x10b214a
... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
llvm::DenseMapBase<llvm::DenseMap<int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u>>>, int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u>, llvm::DenseMapInfo<int, void>, llvm::... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x10b2630
cmpl $0x0, %eax
jne 0x10b2cd1
jmp 0x10b2d6f
callq 0x10b2570
movl %eax, 0x1c(%rsp)
callq 0x10b2d80
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x10b2580
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x10b2590
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::EnablesInitialMFMA::~EnablesInitialMFMA() | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
if (!SyncPipe.size())
return false;
int MFMAsFound = 0;
if (!Cache->size()) {
for (auto &Elt : SyncPipe[0].DAG->SUnits) {
if (TII->isMFMAorWMMA(*El... | pushq %rax
movq %rdi, (%rsp)
movq (%rsp), %rdi
callq 0x10be2e0
popq %rax
retq
| /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::IsSuccOfPrevGroup::apply(llvm::SUnit const*, llvm::ArrayRef<llvm::SUnit*>, llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&) | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
SchedGroup *OtherGroup = nullptr;
for (auto &PipeSG : SyncPipe) {
if ((unsigned)PipeSG.getSGID() == SGID - 1) {
OtherGroup = &PipeSG;
}
}
if... | subq $0x78, %rsp
movq %rdx, 0x60(%rsp)
movq %rcx, 0x68(%rsp)
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %r8, 0x48(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x10(%rsp)
movq $0x0, 0x40(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0x10b2e30
movq %rax, 0x30(%rsp)
movq 0x38(%rsp), %rdi
ca... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::PipelineSolver::convertSyncMapsToArrays() | void PipelineSolver::convertSyncMapsToArrays() {
for (auto &SyncPipe : SyncedSchedGroups) {
BestPipeline.insert(BestPipeline.begin(), SyncPipe.second);
}
int PipelineIDx = SyncedInstrs.size() - 1;
PipelineInstrs.resize(SyncedInstrs.size());
for (auto &SyncInstrMap : SyncedInstrs) {
for (auto &SUsToCa... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x130(%rsp)
movq 0x130(%rsp), %rax
movq %rax, 0x38(%rsp)
addq $0x2f0, %rax # imm = 0x2F0
movq %rax, 0x128(%rsp)
movq 0x128(%rsp), %rdi
callq 0x10d7a40
movq %rax, 0x118(%rsp)
movq %rdx, 0x120(%rsp)
movq 0x128(%rsp), %rdi
callq 0x10d7b10
movq %rax, 0x108(%r... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
llvm::DenseMapBase<llvm::DenseMap<int, llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xb5f430
testb $0x1, %al
jne 0x10d7786
jmp 0x10d77f2
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>, false>::operator++() | inline DenseMapIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
assert(Ptr != End && "incrementing end() iterator");
if (shouldReverseIterate<KeyT>()) {
--Ptr;
RetreatPastEmptyBuckets();
return *this;
}
++Ptr;
AdvancePastEmptyBuc... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0x10da130
testb $0x1, %al
jne 0x10d803d
jmp 0x10d805b
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x28, %rax
movq %rax, (%rdi)
callq 0x10da2a0
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0x10d8077
movq (%rsp), %rdi
movq (%rdi), %rax
addq ... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u>>, false>::DenseMapIterator(llvm::detail::DenseMapPair<int, llvm::SmallVector<(anonymous namespace)::SchedGroup, 4u... | DenseMapIterator(pointer Pos, pointer E, const DebugEpochBase &Epoch,
bool NoAdvance = false)
: DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) {
assert(isHandleInSync() && "invalid construction!");
if (NoAdvance) return;
if (shouldReverseIterate<KeyT>()) {
RetreatPastEm... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x5481a0
movq 0x8(%rsp), %rax
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq 0x20(%rsp), %rcx
m... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::PipelineSolver::solveGreedy() | bool PipelineSolver::solveGreedy() {
BestCost = 0;
std::vector<std::pair<SUnit *, SUnit *>> AddedEdges;
while (static_cast<size_t>(CurrSyncGroupIdx) < PipelineInstrs.size()) {
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
IsBottomUp
? greedyFind(AddedEdges, CurrSU.se... | subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x18(%rsp)
movl $0x0, 0x34b0(%rax)
leaq 0x58(%rsp), %rdi
callq 0x10dbae0
movq 0x18(%rsp), %rdi
movslq 0x34bc(%rdi), %rax
movq %rax, 0x10(%rsp)
addq $0x20, %rdi
callq 0x3a8dca0
movq %rax, %rcx
movq 0x10(%rsp), %rax
cmpq %rcx, %rax
jae 0x10db0ab
movq... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::PipelineSolver::reset() | void PipelineSolver::reset() {
for (auto &SyncPipeline : CurrPipeline) {
for (auto &SG : SyncPipeline) {
SmallVector<SUnit *, 32> TempCollection = SG.Collection;
SG.Collection.clear();
auto SchedBarr = llvm::find_if(TempCollection, [](SUnit *SU) {
return SU->getInstr()->getOpcode() == A... | subq $0x178, %rsp # imm = 0x178
movq %rdi, 0x170(%rsp)
movq 0x170(%rsp), %rax
movq %rax, 0x8(%rsp)
addq $0x308, %rax # imm = 0x308
movq %rax, 0x168(%rsp)
movq 0x168(%rsp), %rdi
callq 0x10d7c40
movq %rax, 0x160(%rsp)
movq 0x168(%rsp), %rdi
callq 0x10d8560
movq %rax, 0x158(%rsp)
movq 0x160(%rsp), %r... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
void (anonymous namespace)::PipelineSolver::greedyFind<std::reverse_iterator<int*>>(std::vector<std::pair<llvm::SUnit*, llvm::SUnit*>, std::allocator<std::pair<llvm::SUnit*, llvm::SUnit*>>>&, std::reverse_iterator<int*>, std::reverse_iterator<int*>) | void PipelineSolver::greedyFind(
std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges, T I, T E) {
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
int BestNodeCost = -1;
int TempCost;
SchedGroup *BestGroup = nullptr;
int BestGroupID = -1;
auto &SyncPipeline = CurrPipeline[Cur... | subq $0xc8, %rsp
movq %rdx, 0x18(%rsp)
movq %rcx, 0x20(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
movq %rcx, 0xa8(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x28(%rsp)
movq %rax, %rdi
addq $0x20, %rdi
movslq 0x34bc(%rax), %rsi
callq 0x10d5ef0
movq %rax, %rdi
movq 0x28(%rsp), %rax
movslq 0x34b8(... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::AMDGPUPostLegalizerCombinerImpl::AMDGPUPostLegalizerCombinerImpl(llvm::MachineFunction&, llvm::CombinerInfo&, llvm::TargetPassConfig const*, llvm::GISelKnownBits&, llvm::GISelCSEInfo*, (anonymous namespace)::AMDGPUPostLegalizerCombinerImplRuleConfig const&, llvm::GCNSubtarget const&, llvm::Machin... | AMDGPUPostLegalizerCombinerImpl::AMDGPUPostLegalizerCombinerImpl(
MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig,
const GCNSubtarget &STI, MachineDominatorTree *MDT, const Legal... | subq $0x48, %rsp
movq 0x68(%rsp), %rax
movq 0x60(%rsp), %rax
movq 0x58(%rsp), %rax
movq 0x50(%rsp), %rax
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq %r9, 0x18(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x38(%rsp), %rsi
movq 0x30(%rsp), %r... | /Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp |
(anonymous namespace)::AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(llvm::Module&) | bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
LLVMContext &Ctx = M.getContext();
IRBuilder<> Builder(Ctx);
Type *I32Ty = Type::getInt32Ty(Ctx);
// Instead of creating global variables, the printf format strings are
// extracted and passed as metadata. This avoids polluting llvm's symbol... | subq $0xc28, %rsp # imm = 0xC28
movq %rdi, 0xc20(%rsp)
movq %rsi, 0xc18(%rsp)
movq 0xc20(%rsp), %rax
movq %rax, 0x1f8(%rsp)
movq 0xc18(%rsp), %rdi
callq 0x7de120
movq %rax, 0xc10(%rsp)
movq 0xc10(%rsp), %rax
movq %rax, 0x1e8(%rsp)
leaq 0xb70(%rsp), %rdi
callq 0x7b2080
movq 0x1e8(%rsp), %rsi
movq 0xb70(%rsp),... | /Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp |
llvm::SmallDenseMap<llvm::Instruction*, llvm::detail::DenseSetEmpty, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseSetPair<llvm::Instruction*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
if (AtLeast > InlineBuckets)
AtLeast = std::max<unsigned>(64, NextPowerOf2(AtLeast-1));
if (Small) {
// First move the inline buckets into a temporary storage.
AlignedCharArrayUnion<BucketT[InlineBuckets]> TmpStorage;
BucketT *TmpBegin = reinterpret_cast<Bu... | subq $0x98, %rsp
movq %rdi, 0x90(%rsp)
movl %esi, 0x8c(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x18(%rsp)
cmpl $0x4, 0x8c(%rsp)
jbe 0x11235d0
movl $0x40, 0x88(%rsp)
movl 0x8c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x84(%rsp)
leaq 0x88(%rsp), %rdi
leaq 0x84(%rsp), %rsi
callq... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::Instruction*, llvm::detail::DenseSetEmpty, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseSetPair<llvm::Instruction*>>, llvm::Instruction*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseSetPair<llvm::Instr... | void clear() {
incrementEpoch();
if (getNumEntries() == 0 && getNumTombstones() == 0) return;
// If the capacity of the array is huge, and the # elements used is small,
// shrink the array.
if (getNumEntries() * 4 < getNumBuckets() && getNumBuckets() > 64) {
shrink_and_clear();
return;
... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x548460
movq 0x18(%rsp), %rdi
callq 0x11234b0
cmpl $0x0, %eax
jne 0x1123e9b
movq 0x18(%rsp), %rdi
callq 0x11234e0
cmpl $0x0, %eax
jne 0x1123e9b
jmp 0x1123f60
movq 0x18(%rsp), %rdi
callq 0x11234b0
movq 0x18(%rsp), %rdi
shll $0x2, %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUPromoteAllocaImpl::getLocalSizeYZ(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&) | std::pair<Value *, Value *>
AMDGPUPromoteAllocaImpl::getLocalSizeYZ(IRBuilder<> &Builder) {
Function &F = *Builder.GetInsertBlock()->getParent();
const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(TM, F);
if (!IsAMDHSA) {
Function *LocalSizeYFn =
Intrinsic::getDeclaration(Mod, Intrinsic::r600_read_loca... | subq $0x3e8, %rsp # imm = 0x3E8
movq %rdi, 0x3d0(%rsp)
movq %rsi, 0x3c8(%rsp)
movq 0x3d0(%rsp), %rax
movq %rax, 0xd8(%rsp)
movq 0x3c8(%rsp), %rdi
callq 0xa7e320
movq %rax, %rdi
callq 0xa4a790
movq %rax, %rcx
movq 0xd8(%rsp), %rax
movq %rcx, 0x3c0(%rsp)
movq (%rax), %rdi
movq 0x3c0(%rsp), %rsi
callq 0xc041a0
... | /Target/AMDGPU/AMDGPUPromoteAlloca.cpp |
void llvm::call_once<llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(llvm::GCNSubtarget const&)::$_0&>(std::once_flag&, llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(llvm::GCNSubtarget const&)::$_0&) | void call_once(once_flag &flag, Function &&F, Args &&... ArgList) {
#if LLVM_THREADING_USE_STD_CALL_ONCE
std::call_once(flag, std::forward<Function>(F),
std::forward<Args>(ArgList)...);
#else
// For other platforms we use a generic (if brittle) version based on our
// atomics.
sys::ca... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq 0x8(%rsp), %rsi
callq 0x115aa60
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/Support/Threading.h |
extendLow32IntoHigh32(llvm::MachineIRBuilder&, llvm::Register, llvm::Register, unsigned int, llvm::RegisterBank const&, bool) | static void extendLow32IntoHigh32(MachineIRBuilder &B,
Register Hi32Reg, Register Lo32Reg,
unsigned ExtOpc,
const RegisterBank &RegBank,
bool IsBooleanSrc = false) {
if (ExtOpc == AM... | subq $0x198, %rsp # imm = 0x198
movb %r9b, %al
movl %esi, 0x194(%rsp)
movl %edx, 0x190(%rsp)
movq %rdi, 0x188(%rsp)
movl %ecx, 0x184(%rsp)
movq %r8, 0x178(%rsp)
andb $0x1, %al
movb %al, 0x177(%rsp)
cmpl $0x85, 0x184(%rsp)
jne 0x114d89f
movq 0x188(%rsp), %rax
movq %rax, 0x30(%rsp)
movl 0x194(%rsp), %eax
movl ... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(llvm::MachineInstr const&) const | const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
for (un... | subq $0xd8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0xc8(%rsp), %rdi
callq 0x734270
movq %rax, %rdi
callq 0x813820
movq %rax, 0xc0(%rsp)
movq 0xc0(%rsp), %rdi
callq 0x813830
movq %rax, 0xb8(%rsp)
movq 0xc8(%rsp), %rdi
callq 0x732d60
movl %eax, %eax
movl %eax, %e... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
llvm::MemoryDependenceWrapperPass& llvm::Pass::getAnalysisID<llvm::MemoryDependenceWrapperPass>(void const*) const | AnalysisType &Pass::getAnalysisID(AnalysisID PI) const {
assert(PI && "getAnalysis for unregistered pass!");
assert(Resolver&&"Pass has not been inserted into a PassManager object!");
// PI *must* appear in AnalysisImpls. Because the number of passes used
// should be a small number, we just do a linear search... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rax
movq 0x8(%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x882a30
movq %rax, (%rsp)
movq (%rsp), %rdi
movq 0x8(%rsp), %rsi
movq (%rdi), %rax
callq *0x60(%rax)
addq $0x18, %rsp
retq
nopl (%rax)
| /llvm/PassAnalysisSupport.h |
(anonymous namespace)::SplitModuleLogger& (anonymous namespace)::operator<<<char [31]>((anonymous namespace)::SplitModuleLogger&, char const (&) [31]) | static SplitModuleLogger &operator<<(SplitModuleLogger &SML, const Ty &Val) {
static_assert(
!std::is_same_v<Ty, Value>,
"do not print values to logs directly, use handleName instead!");
LLVM_DEBUG(dbgs() << Val);
if (SML.hasLogFile())
SML.logfile() << Val;
return SML;
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
jmp 0x1168340
movq 0x10(%rsp), %rdi
callq 0x116a940
testb $0x1, %al
jne 0x1168350
jmp 0x1168367
movq 0x10(%rsp), %rdi
callq 0x116a960
movq %rax, %rdi
movq 0x8(%rsp), %rsi
callq 0x41be30
movq 0x10(%rsp), %rax
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%ra... | /Target/AMDGPU/AMDGPUSplitModule.cpp |
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