name string | code string | asm string | file string |
|---|---|---|---|
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::DenseMap<unsig... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xcc31ee
movl $0x0, 0x14(%rsp)
jmp 0xcc320e
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::MachineBasicBlock const*, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*... | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xcc1ad0
movq %rax, 0x18(%rsp)
callq 0xcc1af0
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0xcc4ec8
movq 0x8(%rsp), %rax
movq (%rax), %rdi
callq 0xcc1aa0
mo... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, llvm::... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
bool llvm::LiveRange::findIndexesLiveAt<llvm::SmallVector<llvm::SlotIndex, 32u>&, std::back_insert_iterator<llvm::SmallVector<llvm::SlotIndex, 32u>>>(llvm::SmallVector<llvm::SlotIndex, 32u>&, std::back_insert_iterator<llvm::SmallVector<llvm::SlotIndex, 32u>>) const | bool findIndexesLiveAt(Range &&R, OutputIt O) const {
assert(llvm::is_sorted(R));
auto Idx = R.begin(), EndIdx = R.end();
auto Seg = segments.begin(), EndSeg = segments.end();
bool Found = false;
while (Idx != EndIdx && Seg != EndSeg) {
// if the Seg is lower find first segment tha... | subq $0x88, %rsp
movq %rdx, 0x80(%rsp)
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x78(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x70(%rsp), %rdi
callq 0xcc5c30
movq %rax, 0x68(%rsp)
movq 0x70(%rsp), %rdi
callq 0xcc5c40
movq 0x10(%rsp), %rdi
movq %rax, 0x60(%rsp)
callq 0xb3ac20
movq 0x10(%rsp), %rdi
movq %rax, 0x58(... | /llvm/CodeGen/LiveInterval.h |
void llvm::sort<__gnu_cxx::__normal_iterator<llvm::SlotIndex*, std::vector<llvm::SlotIndex, std::allocator<llvm::SlotIndex>>>>(__gnu_cxx::__normal_iterator<llvm::SlotIndex*, std::vector<llvm::SlotIndex, std::allocator<llvm::SlotIndex>>>, __gnu_cxx::__normal_iterator<llvm::SlotIndex*, std::vector<llvm::SlotIndex, std::a... | inline void sort(IteratorTy Start, IteratorTy End) {
if constexpr (detail::sort_trivially_copyable<IteratorTy>::value) {
// Forward trivially copyable types to array_pod_sort. This avoids a large
// amount of code bloat for a minor performance hit.
array_pod_sort(Start, End);
} else {
#ifdef EXPENSIVE_C... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq 0x8(%rsp), %rsi
callq 0xcc69f0
addq $0x28, %rsp
retq
nopw %cs:(%rax,%rax)
| /llvm/ADT/STLExtras.h |
llvm::DenseMap<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseM... | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xccc770
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xccc7c0
testb $0x1, %al
jne 0xccc746
jmp 0xccc751
movq (%rsp), %rdi
callq 0xccc830
jmp 0xccc763
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBi... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xccc78e
movl $0x0, 0x14(%rsp)
jmp 0xccc7ae
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::DenseMap<unsigned int, llvm::LaneBi... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0xccc9b0
cmpl $0x0, %eax
jne 0xccc9f1
jmp 0xccca8d
callq 0xccc8f0
movl %eax, 0x1c(%rsp)
callq 0xcccaa0
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0xccc900
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0xccc910
movq %rax, 0x8(%rsp)
m... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>>, unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>>:... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq 0x58(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0xccd830
movq 0x10(%rsp), %rdi
movq %rax, 0x40(%rsp)
callq 0xcccd60
movl %eax, 0x3c(%rsp)
cmpl $0x0, 0x3c(%rsp)
jne 0xccd6f2
movq 0x48(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x67(%rsp)
... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineInstr*, llvm::MachineInstr*, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::MachineInstr*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xcce7c0
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xb0c150
testb $0x1, %al
jne 0xcce796
jmp 0xcce7a1
movq (%rsp), %rdi
callq 0xb0c1c0
jmp 0xcce7b3
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
llvm::R600InstrInfo::PredicateInstruction(llvm::MachineInstr&, llvm::ArrayRef<llvm::MachineOperand>) const | bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const {
int PIdx = MI.findFirstPredOperandIdx();
if (MI.getOpcode() == R600::CF_ALU) {
MI.getOperand(8).setImm(0);
return true;
}
if (MI.getOpcode() == R600::DOT_4) {
... | subq $0xf8, %rsp
movq %rdx, 0xe0(%rsp)
movq %rcx, 0xe8(%rsp)
movq %rdi, 0xd8(%rsp)
movq %rsi, 0xd0(%rsp)
movq 0xd8(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0xd0(%rsp), %rdi
callq 0x341c5c0
movl %eax, 0xcc(%rsp)
movq 0xd0(%rsp), %rdi
callq 0x72bbb0
cmpl $0x16f, %eax # imm = 0x16F
jne 0xce0f47
movq 0xd0(%rsp), %... | /Target/AMDGPU/R600InstrInfo.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>, llvm::WeakTrackingVH, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value ... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0xb8, %rsp
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
movq %rdx, 0x98(%rsp)
movq 0xa8(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0xceec60
movq 0x10(%rsp), %rdi
movq %rax, 0x90(%rsp)
callq 0xceec70
movl %eax, 0x8c(%rsp)
cmpl $0x0, 0x8c(%rsp)
jne 0xceeac0
movq 0x98(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0xb7(%rsp)
... | /llvm/ADT/DenseMap.h |
llvm::BasicTTIImplBase<llvm::R600TTIImpl>::getScalarizationOverhead(llvm::VectorType*, bool, bool, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getScalarizationOverhead(VectorType *InTy, bool Insert,
bool Extract,
TTI::TargetCostKind CostKind) {
if (isa<ScalableVectorType>(InTy))
return InstructionCost::getInvalid();
auto *Ty = cast<FixedVectorTy... | subq $0x78, %rsp
movb %cl, %al
movb %dl, %cl
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
andb $0x1, %cl
movb %cl, 0x57(%rsp)
andb $0x1, %al
movb %al, 0x56(%rsp)
movl %r8d, 0x50(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x78e830
testb $0x1, %al
jne 0xd0452e
jmp 0xd04557
xorl %eax, %ea... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::R600TTIImpl>::getCommonMaskedMemoryOpCost(unsigned int, llvm::Type*, llvm::Align, bool, bool, llvm::TargetTransformInfo::TargetCostKind, unsigned int) | InstructionCost getCommonMaskedMemoryOpCost(unsigned Opcode, Type *DataTy,
Align Alignment,
bool VariableMask,
bool IsGatherScatter,
TTI... | subq $0x288, %rsp # imm = 0x288
movl %r8d, 0x54(%rsp)
movl %ecx, %r8d
movl 0x54(%rsp), %ecx
movb %r9b, %al
movl 0x298(%rsp), %r9d
movl 0x290(%rsp), %r9d
movb %r8b, 0x277(%rsp)
movq %rdi, 0x268(%rsp)
movl %esi, 0x264(%rsp)
movq %rdx, 0x258(%rsp)
andb $0x1, %cl
movb %cl, 0x257(%rsp)
andb $0x1, %al
movb %al, 0x... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::R600TTIImpl>::getInterleavedMemoryOpCost(unsigned int, llvm::Type*, unsigned int, llvm::ArrayRef<unsigned int>, llvm::Align, unsigned int, llvm::TargetTransformInfo::TargetCostKind, bool, bool) | InstructionCost getInterleavedMemoryOpCost(
unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
bool UseMaskForCond = false, bool UseMaskForGaps = false) {
// We cannot scalarize scalable vectors, so retu... | subq $0x428, %rsp # imm = 0x428
movq %r9, %r10
movq %r8, %r11
movl %ecx, 0x94(%rsp)
movq %rdx, %rax
movl 0x94(%rsp), %edx
movq %rax, 0x98(%rsp)
movl %esi, %eax
movq 0x98(%rsp), %rsi
movl %eax, 0xa4(%rsp)
movq %rdi, %r8
movl 0xa4(%rsp), %edi
movb 0x450(%rsp), %al
movb 0x448(%rsp), %cl
movl 0x440(%rsp), %r9d
m... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::detail::UniqueFunctionBase<bool, llvm::StringRef>::UniqueFunctionBase<llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::setStartStopPasses(llvm::TargetPassConfig::StartStopInfo const&) const::'lambda0'(llvm::StringRef), llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R6... | UniqueFunctionBase(CallableT Callable, CalledAs<CalledAsT>) {
bool IsInlineStorage = true;
void *CallableAddr = getInlineStorage();
if (sizeof(CallableT) > InlineStorageSize ||
alignof(CallableT) > alignof(decltype(StorageUnion.InlineStorage))) {
IsInlineStorage = false;
// Allocate out-... | subq $0x58, %rsp
leaq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
movq %rdi, 0x48(%rsp)
movq 0x48(%rsp), %rdi
movq %rdi, 0x10(%rsp)
addq $0x18, %rdi
callq 0xc2c9f0
movq 0x10(%rsp), %rdi
movb $0x1, 0x47(%rsp)
callq 0xc14730
movq %rax, 0x38(%rsp)
movb $0x0, 0x47(%rsp)
movq $0x18, 0x30(%rsp)
movq $0x8, 0x28(%rsp)
movq 0x30(%rsp... | /llvm/ADT/FunctionExtras.h |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddIRPass::operator()<llvm::PreISelIntrinsicLoweringPass>(llvm::PreISelIntrinsicLoweringPass&&, llvm::StringRef) | void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
bool Required = false;
if const... | subq $0x78, %rsp
movq %rdx, 0x68(%rsp)
movq %rcx, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x10(%rsp)
movb $0x0, 0x57(%rsp)
movq 0x20(%rax), %rdi
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x40(%rsp), %rsi
movq 0x48(%rsp), ... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddIRPass::operator()<llvm::PrintFunctionPass>(llvm::PrintFunctionPass&&, llvm::StringRef) | void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
bool Required = false;
if const... | subq $0x48, %rsp
movq %rdx, 0x38(%rsp)
movq %rcx, 0x40(%rsp)
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x27(%rsp)
callq 0xc341b0
movb %al, %cl
movq 0x8(%rsp), %rax
andb $0x1, %cl
movb %cl, 0x27(%rsp)
movq 0x20(%rax), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddMachinePass::operator()<llvm::MachineSinkingPass>(llvm::MachineSinkingPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | subq $0x78, %rsp
movb %dl, %al
movq %rcx, 0x68(%rsp)
movq %r8, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
andb $0x1, %al
movb %al, 0x57(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
testb $0x1, 0x57(%rsp)
jne 0xd1be36
movq 0x8(%rsp), %rax
movq 0x20(%rax), %rdi
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)
... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseSetPair<llvm::MachineInstr*>>, llvm::MachineInstr*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseSetPair<llvm::MachineIn... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xd285ee
movl $0x0, 0x14(%rsp)
jmp 0xd2860e
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>>, unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>>::begin() | inline iterator begin() {
// When the map is empty, avoid the overhead of advancing/retreating past
// empty buckets.
if (empty())
return end();
if (shouldReverseIterate<KeyT>())
return makeIterator(getBucketsEnd() - 1, getBuckets(), *this);
return makeIterator(getBuckets(), getBucketsEn... | subq $0x38, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xd2f610
testb $0x1, %al
jne 0xd2ee3e
jmp 0xd2ee57
movq 0x18(%rsp), %rdi
callq 0xd2dde0
movq %rax, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
jmp 0xd2eede
callq 0x547e50
testb $0x1, %al
jne 0xd2ee62
jmp 0xd2eea3
movq 0x18(%rsp), %rdi
callq 0... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineInstr*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseSetPair<llvm::MachineInstr*>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movl 0x10(%rdi), %eax
movl %eax, 0x1c(%rsp)
movl 0x8(%rdi), %eax
movl %eax, 0x18(%rsp)
callq 0xd240f0
movl $0x0, 0x14(%rsp)
cmpl $0x0, 0x18(%rsp)
je 0xd2f81a
movl $0x40, 0x10(%rsp)
movl 0x18(%rsp), %edi
callq 0x91b7e0
movl %eax, %ecx
addl $0... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SIFoldOperands::tryToFoldACImm(llvm::MachineOperand const&, llvm::MachineInstr*, unsigned int, llvm::SmallVectorImpl<(anonymous namespace)::FoldCandidate>&) const | bool SIFoldOperands::tryToFoldACImm(
const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList) const {
const MCInstrDesc &Desc = UseMI->getDesc();
if (UseOpIdx >= Desc.getNumOperands())
return false;
if (!AMDGPU::isSISrcInlinableOperand(Desc, Us... | subq $0x2f8, %rsp # imm = 0x2F8
movq %rdi, 0x2e8(%rsp)
movq %rsi, 0x2e0(%rsp)
movq %rdx, 0x2d8(%rsp)
movl %ecx, 0x2d4(%rsp)
movq %r8, 0x2c8(%rsp)
movq 0x2e8(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x2d8(%rsp), %rdi
callq 0x7349e0
movq %rax, 0x2c0(%rsp)
movl 0x2d4(%rsp), %eax
movl %eax, 0x34(%rsp)
movq 0x2c0(%... | /Target/AMDGPU/SIFoldOperands.cpp |
(anonymous namespace)::FoldCandidate::FoldCandidate(llvm::MachineInstr*, unsigned int, llvm::MachineOperand*, bool, int) | FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp,
bool Commuted_ = false,
int ShrinkOp = -1) :
UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
Kind(FoldOp->getType()),
Commuted(Commuted_) {
if (FoldOp->isImm()) {
ImmToFold =... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movl %edx, 0x24(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movl %r9d, 0x10(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq $0x0, 0x8(%rax)
movl 0x10(%rsp), %ecx
movl %ecx, 0x10(... | /Target/AMDGPU/SIFoldOperands.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [25], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(char const (&) [25], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, (%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq (%rsp), %rdi
addq $0x80, %rdi
callq 0x76e5e0
movq (%rsp), %rsi
leaq 0x89975e6(%rip), %rax # 0x96defe... | /llvm/Support/CommandLine.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>>>, unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llv... | const_iterator makeConstIterator(const BucketT *P, const BucketT *E,
const DebugEpochBase &Epoch,
const bool NoAdvance=false) const {
if (shouldReverseIterate<KeyT>()) {
const BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x547e50
testb $0x1, %al
jne 0xd4a366
jmp 0xd4a3d2
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<int, std::vector<llvm::SIRegisterInfo::SpilledReg, std::allocator<llvm::SIRegisterInfo::SpilledReg>>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, std::vector<llvm::SIRegisterInfo::SpilledReg, std::allocator<llvm::SIRegisterInfo::SpilledReg>>>, true>::DenseMapIterator(llvm::deta... | DenseMapIterator(pointer Pos, pointer E, const DebugEpochBase &Epoch,
bool NoAdvance = false)
: DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) {
assert(isHandleInSync() && "invalid construction!");
if (NoAdvance) return;
if (shouldReverseIterate<KeyT>()) {
RetreatPastEm... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x5481a0
movq 0x8(%rsp), %rax
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq 0x20(%rsp), %rcx
m... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::WaitcntGeneratorGFX12Plus::getWaitEventMask() const | const unsigned *getWaitEventMask() const override {
assert(ST);
static const unsigned WaitEventMaskForInstGFX12Plus[NUM_INST_CNTS] = {
eventMask({VMEM_ACCESS, VMEM_READ_ACCESS}),
eventMask({LDS_ACCESS, GDS_ACCESS}),
eventMask({EXP_GPR_LOCK, GDS_GPR_LOCK, VMW_GPR_LOCK, EXP_PARAM_ACCESS,
... | movq %rdi, -0x8(%rsp)
leaq 0x5856214(%rip), %rax # 0x65b5f00
retq
nopl (%rax)
| /Target/AMDGPU/SIInsertWaitcnts.cpp |
llvm::SmallVectorImpl<std::tuple<llvm::MachineBasicBlock*, __gnu_cxx::__normal_iterator<llvm::MachineBasicBlock**, std::vector<llvm::MachineBasicBlock*, std::allocator<llvm::MachineBasicBlock*>>>, __gnu_cxx::__normal_iterator<llvm::MachineBasicBlock**, std::vector<llvm::MachineBasicBlock*, std::allocator<llvm::MachineB... | void assignRemote(SmallVectorImpl &&RHS) {
this->destroy_range(this->begin(), this->end());
if (!this->isSmall())
free(this->begin());
this->BeginX = RHS.BeginX;
this->Size = RHS.Size;
this->Capacity = RHS.Capacity;
RHS.resetToSmall();
} | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0xd65700
movq 0x10(%rsp), %rdi
movq %rax, 0x8(%rsp)
callq 0xd656c0
movq 0x8(%rsp), %rdi
movq %rax, %rsi
callq 0xd65bd0
movq 0x10(%rsp), %rdi
callq 0xd65f20
testb $0x1, %al
jne 0xd66449
movq 0x10(%rsp), %rdi
ca... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<llvm::MachineBasicBlock*, bool, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, bool>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
llvm::SIInstrInfo::areLoadsFromSameBasePtr(llvm::SDNode*, llvm::SDNode*, long&, long&) const | bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
int64_t &Offset0,
int64_t &Offset1) const {
if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
return false;
unsigned Opc0 = Load0->getMachineOpco... | subq $0xb8, %rsp
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
movq %rdx, 0x98(%rsp)
movq %rcx, 0x90(%rsp)
movq %r8, 0x88(%rsp)
movq 0xa8(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0xa0(%rsp), %rdi
callq 0x97c390
testb $0x1, %al
jne 0xd7064f
jmp 0xd70660
movq 0x98(%rsp), %rdi
callq 0x97c390
testb $0x1, %al
jne 0xd7066d
movb ... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::insertVectorSelect(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::Register, llvm::ArrayRef<llvm::MachineOperand>, llvm::Register, llvm::Register) const | void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, Register DstReg,
ArrayRef<MachineOperand> Cond,
Register Tru... | subq $0x6e8, %rsp # imm = 0x6E8
movl 0x700(%rsp), %eax
leaq 0x6f0(%rsp), %r10
movq %r10, 0x150(%rsp)
movq %rdx, 0x6e0(%rsp)
movl %r8d, 0x6dc(%rsp)
movl %r9d, 0x6d8(%rsp)
movl %eax, 0x6d4(%rsp)
movq %rdi, 0x6c8(%rsp)
movq %rsi, 0x6c0(%rsp)
movq %rcx, 0x6b8(%rsp)
movq 0x6c8(%rsp), %rax
movq %rax, 0x148(%rsp)
m... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::reverseBranchCondition(llvm::SmallVectorImpl<llvm::MachineOperand>&) const | bool SIInstrInfo::reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
if (Cond.size() != 2) {
return true;
}
if (Cond[0].isImm()) {
Cond[0].setImm(-Cond[0].getImm());
return false;
}
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x3a8dca0
cmpq $0x2, %rax
je 0xd838d5
movb $0x1, 0x27(%rsp)
jmp 0xd83937
movq 0x10(%rsp), %rdi
xorl %eax, %eax
movl %eax, %esi
callq 0x8ff6a0
movq %rax, %rdi
callq 0x737c60
testb $0x1, %al
jne 0xd838f1
jmp 0xd83932
movq 0x10(%rsp),... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::convertNonUniformIfRegion(llvm::MachineBasicBlock*, llvm::MachineBasicBlock*) const | void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
MachineBasicBlock *IfEnd) const {
MachineBasicBlock::iterator TI = IfEntry->getFirstTerminator();
assert(TI != IfEntry->end());
MachineInstr *Branch = &(*TI);
MachineFunction *MF = IfEntry->getPa... | subq $0x158, %rsp # imm = 0x158
movq %rdi, 0x150(%rsp)
movq %rsi, 0x148(%rsp)
movq %rdx, 0x140(%rsp)
movq 0x150(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x148(%rsp), %rdi
callq 0x33700d0
movq %rax, 0x138(%rsp)
leaq 0x138(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x130(%rsp)
movq 0x148(%rsp), %rdi
callq 0x73fb50
mo... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::getKillTerminatorFromPseudo(unsigned int) const | const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {
switch (Opcode) {
case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
return get(AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR);
case AMDGPU::SI_KILL_I1_PSEUDO:
return get(AMDGPU::SI_KILL_I1_TERMINATOR);
default:
llvm_unreachable("... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %eax
subl $0xee6, %eax # imm = 0xEE6
je 0xda3326
jmp 0xda3324
jmp 0xda3340
movq 0x8(%rsp), %rdi
addq $0x8, %rdi
movl $0xee7, %esi # imm = 0xEE7
callq 0x47b180
movq %rax, 0x20(%r... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::hasAnyModifiersSet(llvm::MachineInstr const&) const::$_0::operator()(unsigned int) const | bool SIInstrInfo::canShrink(const MachineInstr &MI,
const MachineRegisterInfo &MRI) const {
const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
// Can't shrink instruction with three operands.
if (Src2) {
switch (MI.getOpcode()) {
default: return false;
... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rax
movq (%rax), %rdi
movq 0x8(%rax), %rsi
movl 0xc(%rsp), %edx
callq 0xd8bac0
andb $0x1, %al
addq $0x18, %rsp
retq
nopl (%rax)
| /Target/AMDGPU/SIInstrInfo.cpp |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::TargetInstrInfo::RegSubRegPair, llvm::detail::DenseSetEmpty, 4u, llvm::DenseMapInfo<llvm::TargetInstrInfo::RegSubRegPair, void>, llvm::detail::DenseSetPair<llvm::TargetInstrInfo::RegSubRegPair>>, llvm::TargetInstrInfo::RegSubRegPair, llvm::detail::DenseSetEmpty, llvm::DenseM... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xda7dd0
callq 0xda7ea0
movq %rax, 0x38(%rsp)
callq 0xda8180
movq %rax, 0x30(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x28(%rsp), ... | /llvm/ADT/DenseMap.h |
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed(llvm::CCState&, llvm::MachineFunction&, llvm::SIRegisterInfo const&, llvm::SIMachineFunctionInfo&) const | void SITargetLowering::allocateSpecialInputVGPRsFixed(
CCState &CCInfo, MachineFunction &MF,
const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
if (!Reg)
report_fatal_error("failed to allocated VGPR for implicit arguments");
const unsigned M... | subq $0xe8, %rsp
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
movq %rdx, 0xd0(%rsp)
movq %rcx, 0xc8(%rsp)
movq %r8, 0xc0(%rsp)
movq 0xd8(%rsp), %rdi
movl $0x206, %esi # imm = 0x206
callq 0xb66550
movl %eax, 0xb8(%rsp)
movl 0xb8(%rsp), %esi
leaq 0xbc(%rsp), %rdi
callq 0x733b40
leaq 0xbc(%rsp), %rdi
callq 0x72c... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::lowerSET_FPENV(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op);
if (Op.getOperand(1).getValueType() != MVT::i64)
return Op;
SDValue Input = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op.getOperand(1));
SDValue NewModeReg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Inpu... | subq $0x538, %rsp # imm = 0x538
movq %rsi, 0x518(%rsp)
movl %edx, 0x520(%rsp)
movq %rdi, 0x510(%rsp)
movq %rcx, 0x508(%rsp)
movq 0x518(%rsp), %rax
movq %rax, 0x4e8(%rsp)
movq 0x520(%rsp), %rax
movq %rax, 0x4f0(%rsp)
movq 0x4e8(%rsp), %rsi
movl 0x4f0(%rsp), %edx
leaq 0x4f8(%rsp), %rdi
callq 0x98cf60
leaq 0x51... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::bundleInstWithWaitcnt(llvm::MachineInstr&) const | void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
MachineBasicBlock *MBB = MI.getParent();
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
auto I = MI.getIterator();
auto E = std::next(I);
BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
.addImm(0);
MIBundl... | subq $0xd8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, (%rsp)
movq 0xc8(%rsp), %rdi
callq 0x73fb40
movq (%rsp), %rdi
movq %rax, 0xc0(%rsp)
callq 0xdb6050
movq %rax, %rdi
callq 0xbdd4d0
movq %rax, 0xb8(%rsp)
movq 0xc8(%rsp), %rdi
callq 0x76c210
movq %rax, 0xb0(%rsp)
movq 0xb0(%rsp)... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::LowerRETURNADDR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
MVT VT = Op.getSimpleValueType();
SDLoc DL(Op);
// Checking the depth
if (Op.getConstantOperandVal(0) != 0)
return DAG.getConstant(0, DL, VT);
MachineFunction &MF = DAG.getMachineFun... | subq $0x168, %rsp # imm = 0x168
movq %rsi, 0x148(%rsp)
movl %edx, 0x150(%rsp)
movq %rdi, 0x140(%rsp)
movq %rcx, 0x138(%rsp)
movq 0x140(%rsp), %rax
movq %rax, 0x38(%rsp)
leaq 0x148(%rsp), %rdi
callq 0x9dc070
movb %al, 0x137(%rsp)
movq 0x148(%rsp), %rax
movq %rax, 0x110(%rsp)
movq 0x150(%rsp), %rax
movq %rax, ... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::lowerTrapHsaQueuePtr(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::lowerTrapHsaQueuePtr(
SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op);
SDValue Chain = Op.getOperand(0);
SDValue QueuePtr;
// For code object version 5, QueuePtr is passed through implicit kernarg.
const Module *M = DAG.getMachineFunction().getFunction().getParent();
if (A... | subq $0x2e8, %rsp # imm = 0x2E8
movq %rsi, 0x2c8(%rsp)
movl %edx, 0x2d0(%rsp)
movq %rdi, 0x2c0(%rsp)
movq %rcx, 0x2b8(%rsp)
movq 0x2c0(%rsp), %rax
movq %rax, 0x78(%rsp)
movq 0x2c8(%rsp), %rax
movq %rax, 0x298(%rsp)
movq 0x2d0(%rsp), %rax
movq %rax, 0x2a0(%rsp)
movq 0x298(%rsp), %rsi
movl 0x2a0(%rsp), %edx
le... | /Target/AMDGPU/SIISelLowering.cpp |
isKnownNonNull(llvm::SDValue, llvm::SelectionDAG&, llvm::AMDGPUTargetMachine const&, unsigned int) | static bool isKnownNonNull(SDValue Val, SelectionDAG &DAG,
const AMDGPUTargetMachine &TM, unsigned AddrSpace) {
if (isa<FrameIndexSDNode>(Val) || isa<GlobalAddressSDNode>(Val) ||
isa<BasicBlockSDNode>(Val))
return true;
if (auto *ConstVal = dyn_cast<ConstantSDNode>(Val))
re... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movl %esi, 0x38(%rsp)
movq %rdx, 0x28(%rsp)
movq %rcx, 0x20(%rsp)
movl %r8d, 0x1c(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x9964c0
testb $0x1, %al
jne 0xe01558
leaq 0x30(%rsp), %rdi
callq 0xe3a230
testb $0x1, %al
jne 0xe01558
leaq 0x30(%rsp), %rdi
callq 0xe3a250
testb $0x1, %al
jne 0xe0... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SmallVectorImpl<llvm::SDValue>::resize(unsigned long, llvm::SDValue) | void resize(size_type N, ValueParamT NV) {
if (N == this->size())
return;
if (N < this->size()) {
this->truncate(N);
return;
}
// N > this->size(). Defer to append.
this->append(N - this->size(), NV);
} | subq $0x58, %rsp
movq %rdx, 0x48(%rsp)
movl %ecx, 0x50(%rsp)
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x20(%rsp)
callq 0x3a8dca0
movq %rax, %rcx
movq 0x20(%rsp), %rax
cmpq %rcx, %rax
jne 0xe0ecef
jmp 0xe0ed64
movq 0x18(%rsp), %rdi
movq 0x38... | /llvm/ADT/SmallVector.h |
llvm::SITargetLowering::widenLoad(llvm::LoadSDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
if (Ld->getAlign() < Align(4) || Ld->isDivergent())
return SDValue();
// FIXME: Constant loads should all be marked invariant.
unsigned AS = Ld->getAddressSpace();
if (AS != AMDGPUAS::CONSTANT_A... | subq $0x468, %rsp # imm = 0x468
movq %rdi, 0x450(%rsp)
movq %rsi, 0x448(%rsp)
movq %rdx, 0x440(%rsp)
movq 0x440(%rsp), %rax
movq 0x10(%rax), %rax
movq %rax, 0x438(%rsp)
movq 0x448(%rsp), %rdi
callq 0x9e24e0
movb %al, 0x437(%rsp)
leaq 0x436(%rsp), %rdi
movl $0x4, %esi
callq 0x4e37b0
movb 0x437(%rsp), %al
movz... | /Target/AMDGPU/SIISelLowering.cpp |
getFPTernOp(llvm::SelectionDAG&, unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDNodeFlags) | static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
EVT VT, SDValue A, SDValue B, SDValue C,
SDValue GlueChain, SDNodeFlags Flags) {
if (GlueChain->getNumValues() <= 1) {
return DAG.getNode(Opcode, SL, VT, {A, B, C}, Flags);
}
... | subq $0x238, %rsp # imm = 0x238
movl %ecx, 0x54(%rsp)
movq %rdi, %rax
movl 0x54(%rsp), %edi
movw %r9w, %cx
movb %dil, %r9b
leaq 0x270(%rsp), %rdi
movq %rdi, 0x58(%rsp)
leaq 0x260(%rsp), %r10
movq %r10, 0x60(%rsp)
leaq 0x250(%rsp), %r10
movq %r10, 0x68(%rsp)
leaq 0x240(%rsp), %r10
movq %r10, 0x70(%rsp)
movb %... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::isCanonicalized(llvm::SelectionDAG&, llvm::SDValue, unsigned int) const | bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
unsigned MaxDepth) const {
unsigned Opcode = Op.getOpcode();
if (Opcode == ISD::FCANONICALIZE)
return true;
if (auto *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
const auto &F = CFP->getValueAPF();
... | subq $0x2b8, %rsp # imm = 0x2B8
movq %rdx, 0x2a0(%rsp)
movl %ecx, 0x2a8(%rsp)
movq %rdi, 0x298(%rsp)
movq %rsi, 0x290(%rsp)
movl %r8d, 0x28c(%rsp)
movq 0x298(%rsp), %rax
movq %rax, 0x98(%rsp)
leaq 0x2a0(%rsp), %rdi
callq 0x98d4c0
movl %eax, 0x288(%rsp)
cmpl $0x99, 0x288(%rsp)
jne 0xe1be2c
movb $0x1, 0x2b7(%r... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::getRegForInlineAsmConstraint(llvm::TargetRegisterInfo const*, llvm::StringRef, llvm::MVT) const | std::pair<unsigned, const TargetRegisterClass *>
SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
StringRef Constraint,
MVT VT) const {
const SIRegisterInfo *TRI = static_cast<const SIRegisterIn... | subq $0x228, %rsp # imm = 0x228
movb %r8b, %al
movq %rdx, 0x208(%rsp)
movq %rcx, 0x210(%rsp)
movb %al, 0x207(%rsp)
movq %rdi, 0x1f8(%rsp)
movq %rsi, 0x1f0(%rsp)
movq 0x1f8(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x1f0(%rsp), %rax
movq %rax, 0x1e8(%rsp)
movq $0x0, 0x1e0(%rsp)
leaq 0x208(%rsp), %rdi
callq 0x3f3... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::checkAsmConstraintVal(llvm::SDValue, llvm::StringRef, unsigned long) const | bool SITargetLowering::checkAsmConstraintVal(SDValue Op, StringRef Constraint,
uint64_t Val) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'I':
return AMDGPU::isInlinableIntLiteral(Val);
case 'J':
return isInt<16>(Val);
cas... | subq $0xe8, %rsp
movq %rsi, 0xd0(%rsp)
movl %edx, 0xd8(%rsp)
movq %rcx, 0xc0(%rsp)
movq %r8, 0xc8(%rsp)
movq %rdi, 0xb8(%rsp)
movq %r9, 0xb0(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x28(%rsp)
leaq 0xc0(%rsp), %rdi
callq 0x3f3670
cmpq $0x1, %rax
jne 0xe2f721
xorl %eax, %eax
movl %eax, %esi
leaq 0xc0(%rsp), %rdi
callq 0x4... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::getPrefLoopAlignment(llvm::MachineLoop*) const | Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
const Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
const Align CacheLineAlign = Align(64);
// Pre-GFX10 target did not benefit from loop alignment
if (!ML || DisableLoopAlignment || !getSubtarget()->hasInstPrefetch() ||
... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x178(%rsp)
movq %rsi, 0x170(%rsp)
movq 0x178(%rsp), %rdi
movq %rdi, 0x20(%rsp)
movq 0x170(%rsp), %rsi
callq 0x36f4580
movb %al, 0x16f(%rsp)
leaq 0x16e(%rsp), %rdi
movl $0x40, %esi
callq 0x4e37b0
cmpq $0x0, 0x170(%rsp)
je 0xe3126c
leaq 0x892c7ac(%rip), %rdi # 0x97... | /Target/AMDGPU/SIISelLowering.cpp |
(anonymous namespace)::SILoadStoreOptimizer::extractConstOffset(llvm::MachineOperand const&) const | std::optional<int32_t>
SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
if (Op.isImm())
return Op.getImm();
if (!Op.isReg())
return std::nullopt;
MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 ||
!Def->getOperan... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x40(%rsp), %rdi
callq 0x737c60
testb $0x1, %al
jne 0xe49288
jmp 0xe492ab
movq 0x40(%rsp), %rdi
callq 0x72c4f0
movq %rax, 0x38(%rsp)
leaq 0x50(%rsp), %rdi
leaq 0x38(%rsp), %rsi
callq 0xe493b0
jmp 0xe49362
movq ... | /Target/AMDGPU/SILoadStoreOptimizer.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress>>, llvm::MachineInstr*, (anonymous namespace)::SILoa... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xe49210
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0xe46980
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0xe49602
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rsp)
... | /llvm/ADT/DenseMap.h |
std::pair<llvm::MachineInstr*, long> const* llvm::SmallVectorTemplateCommon<std::pair<llvm::MachineInstr*, long>, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<std::pair<llvm::MachineInstr*, long>, true>>(llvm::SmallVectorTemplateBase<std::pair<llvm::MachineInstr*, long>, true>*, std::pair<llvm:... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movq 0x38(%rsp), %rdi
callq 0x3a8dca0
addq 0x28(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x38(%rsp), %rdi
callq 0x3a8dab0
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
ja 0xe49dc4
movq 0x30... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movl 0x10(%rdi), %eax
movl %eax, 0x1c(%rsp)
movl 0x8(%rdi), %eax
movl %eax, 0x18(%rsp)
callq 0xe51fc0
movl $0x0, 0x14(%rsp)
cmpl $0x0, 0x18(%rsp)
je 0xe51f7a
movl $0x40, 0x10(%rsp)
movl 0x18(%rsp), %edi
callq 0x91b7e0
movl %eax, %ecx
addl $0... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress>>, llvm::MachineInstr*, (anonymous namespace)::SILoadStor... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xe46980
cmpl $0x0, %eax
jne 0xe51fe2
jmp 0xe5207a
callq 0xe468c0
movq %rax, 0x28(%rsp)
callq 0xe49220
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0xe468d0
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0xe468e0
movq %rax, 0x... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SILowerControlFlow::emitIf(llvm::MachineInstr&) | void SILowerControlFlow::emitIf(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock::iterator I(&MI);
Register SaveExecReg = MI.getOperand(0).getReg();
MachineOperand& Cond = MI.getOperand(1);
assert(Cond.getSubReg() == AMDGPU::NoSubRegister... | subq $0x318, %rsp # imm = 0x318
movq %rdi, 0x310(%rsp)
movq %rsi, 0x308(%rsp)
movq 0x310(%rsp), %rax
movq %rax, 0x98(%rsp)
movq 0x308(%rsp), %rdi
callq 0x73fb40
movq %rax, 0x300(%rsp)
movq 0x308(%rsp), %rdi
callq 0x73ff30
movq %rax, 0x2f8(%rsp)
movq 0x308(%rsp), %rsi
leaq 0x2f0(%rsp), %rdi
callq 0x86efe0
mov... | /Target/AMDGPU/SILowerControlFlow.cpp |
(anonymous namespace)::SILowerControlFlow::emitEndCf(llvm::MachineInstr&) | MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock::iterator InsPt = MBB.begin();
// If we have instructions that aren't prolog instructions, split the block
// and emit a terminator instruct... | subq $0x2b8, %rsp # imm = 0x2B8
movq %rdi, 0x2b0(%rsp)
movq %rsi, 0x2a8(%rsp)
movq 0x2b0(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x2a8(%rsp), %rdi
callq 0x73fb40
movq %rax, 0x2a0(%rsp)
movq 0x2a8(%rsp), %rdi
callq 0x73ff30
movq %rax, 0x298(%rsp)
movq 0x2a0(%rsp), %rdi
callq 0x73fe80
movq %rax, 0x290(%rsp)
mov... | /Target/AMDGPU/SILowerControlFlow.cpp |
(anonymous namespace)::SILowerControlFlow::removeMBBifRedundant(llvm::MachineBasicBlock&) | bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) {
for (auto &I : MBB.instrs()) {
if (!I.isDebugInstr() && !I.isUnconditionalBranch())
return false;
}
assert(MBB.succ_size() == 1 && "MBB has more than one successor");
MachineBasicBlock *Succ = *MBB.succ_begin();
MachineBasicBl... | subq $0x128, %rsp # imm = 0x128
movq %rdi, 0x118(%rsp)
movq %rsi, 0x110(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x110(%rsp), %rdi
callq 0xaf6780
movq %rax, 0xf8(%rsp)
movq %rdx, 0x100(%rsp)
leaq 0xf8(%rsp), %rax
movq %rax, 0x108(%rsp)
movq 0x108(%rsp), %rdi
callq 0xafe030
movq %rax, 0xf0(%rsp... | /Target/AMDGPU/SILowerControlFlow.cpp |
llvm::DenseMapBase<llvm::DenseMap<int, std::vector<llvm::SIRegisterInfo::SpilledReg, std::allocator<llvm::SIRegisterInfo::SpilledReg>>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, std::vector<llvm::SIRegisterInfo::SpilledReg, std::allocator<llvm::SIRegisterInfo::SpilledReg>>>>, int, std::vector<llvm:... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x20(%rsp), %rsi
leaq 0x18(%rsp), %rdx
callq 0xe772f0
testb $0x1, %al
jne 0xe67a72
movb $0x0, 0x37(%rsp)
jmp 0xe67ab6
movq 0x18(%rsp), %rdi
callq 0xe72a80
movq %rax, %rdi
callq 0xe72a90
callq 0xd574f0
movl %eax... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<int, llvm::SIMachineFunctionInfo::VGPRSpillToAGPR, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::SIMachineFunctionInfo::VGPRSpillToAGPR>, false>::operator++() | inline DenseMapIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
assert(Ptr != End && "incrementing end() iterator");
if (shouldReverseIterate<KeyT>()) {
--Ptr;
RetreatPastEmptyBuckets();
return *this;
}
++Ptr;
AdvancePastEmptyBuc... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0xb5f430
testb $0x1, %al
jne 0xe6894d
jmp 0xe6896b
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x68, %rax
movq %rax, (%rdi)
callq 0xd59210
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0xe68987
movq (%rsp), %rdi
movq (%rdi), %rax
addq $0x68... | /llvm/ADT/DenseMap.h |
std::enable_if<unvalidatedMappingTraits<llvm::yaml::SIArgumentInfo, llvm::yaml::EmptyContext>::value, void>::type llvm::yaml::yamlize<llvm::yaml::SIArgumentInfo, llvm::yaml::EmptyContext>(llvm::yaml::IO&, llvm::yaml::SIArgumentInfo&, bool, llvm::yaml::EmptyContext&) | std::enable_if_t<unvalidatedMappingTraits<T, Context>::value, void>
yamlize(IO &io, T &Val, bool, Context &Ctx) {
if (yamlizeMappingEnumInput<T, Context>(io, Val))
return;
if (has_FlowTraits<MappingTraits<T>>::value) {
io.beginFlowMapping();
detail::doMapping(io, Val, Ctx);
io.endFlowMapping();
} ... | subq $0x28, %rsp
movb %dl, %al
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq %rcx, 0x8(%rsp)
movq 0x20(%rsp), %rdi
movq 0x18(%rsp), %rsi
callq 0xe6f9a0
testb $0x1, %al
jne 0xe6ec50
jmp 0xe6ec52
jmp 0xe6ec7c
movq 0x20(%rsp), %rdi
movq (%rdi), %rax
callq *0x68(%rax)
movq 0x20(%rsp),... | /llvm/Support/YAMLTraits.h |
llvm::SmallVectorImpl<unsigned char>::operator=(llvm::SmallVectorImpl<unsigned char> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)
cmpq 0x60(%rsp), %rax
jne 0xe73b6e
movq 0x40(%rsp), %rax
movq %rax, 0x70(%rsp)
jmp 0xe73d17
movq 0x60(%rsp), %rdi
callq 0x3a8dfc0
movq 0x40(%rsp), %rdi
movq %rax, 0x58(%rsp)
callq 0x3a8dfc0
movq %rax, 0x50(%rsp)
mov... | /llvm/ADT/SmallVector.h |
llvm::SIScheduleBlock::addPred(llvm::SIScheduleBlock*) | void SIScheduleBlock::addPred(SIScheduleBlock *Pred) {
unsigned PredID = Pred->getID();
// Check if not already predecessor.
for (SIScheduleBlock* P : Preds) {
if (PredID == P->getID())
return;
}
Preds.push_back(Pred);
assert(none_of(Succs,
[=](std::pair<SIScheduleBlock*,
... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x38(%rsp), %rdi
callq 0xe7bd90
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x34(%rsp)
addq $0x400, %rax # imm = 0x400
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rdi
callq 0xe7bdb0
movq %rax, 0x20(%r... | /Target/AMDGPU/SIMachineScheduler.cpp |
llvm::SIScheduleBlockCreator::scheduleInsideBlocks() | void SIScheduleBlockCreator::scheduleInsideBlocks() {
unsigned DAGSize = CurrentBlocks.size();
LLVM_DEBUG(dbgs() << "\nScheduling Blocks\n\n");
// We do schedule a valid scheduling such that a Block corresponds
// to a range of instructions.
LLVM_DEBUG(dbgs() << "First phase: Fast scheduling for Reg Livenes... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x180(%rsp)
movq 0x180(%rsp), %rdi
movq %rdi, 0x28(%rsp)
addq $0x50, %rdi
callq 0xe80f30
movl %eax, 0x17c(%rsp)
jmp 0xe7cfce
jmp 0xe7cfd0
jmp 0xe7cfd2
movl $0x0, 0x178(%rsp)
movl 0x17c(%rsp), %eax
movl %eax, 0x174(%rsp)
movl 0x178(%rsp), %eax
cmpl 0x174(%rsp), %eax
... | /Target/AMDGPU/SIMachineScheduler.cpp |
(anonymous namespace)::SIMemOpAccess::constructFromMIWithMMO(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false> const&) const | std::optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
const MachineBasicBlock::iterator &MI) const {
assert(MI->getNumMemOperands() > 0);
SyncScope::ID SSID = SyncScope::SingleThread;
AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic... | pushq %rbx
subq $0x120, %rsp # imm = 0x120
movq %rdi, 0x40(%rsp)
movq %rdi, 0x48(%rsp)
movq %rsi, 0x118(%rsp)
movq %rdx, 0x110(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x50(%rsp)
movb $0x0, 0x10f(%rsp)
movl $0x0, 0x108(%rsp)
movl $0x0, 0x104(%rsp)
movl $0x0, 0x100(%rsp)
movb $0x1, 0xff(%rsp)
movb $0x0, 0xfe(%... | /Target/AMDGPU/SIMemoryLegalizer.cpp |
(anonymous namespace)::SIMemOpAccess::toSIAtomicScope(unsigned char, (anonymous namespace)::SIAtomicAddrSpace) const | std::optional<std::tuple<SIAtomicScope, SIAtomicAddrSpace, bool>>
SIMemOpAccess::toSIAtomicScope(SyncScope::ID SSID,
SIAtomicAddrSpace InstrAddrSpace) const {
if (SSID == SyncScope::System)
return std::tuple(SIAtomicScope::SYSTEM, SIAtomicAddrSpace::ATOMIC, true);
if (SSID == MMI-... | subq $0x148, %rsp # imm = 0x148
movq %rdi, 0x28(%rsp)
movb %dl, %al
movq %rdi, %rdx
movq %rdx, 0x30(%rsp)
movq %rdi, 0x140(%rsp)
movq %rsi, 0x138(%rsp)
movb %al, 0x137(%rsp)
movl %ecx, 0x130(%rsp)
movq 0x138(%rsp), %rax
movq %rax, 0x38(%rsp)
movzbl 0x137(%rsp), %eax
cmpl $0x1, %eax
jne 0xea0138
movl $0x5, 0x... | /Target/AMDGPU/SIMemoryLegalizer.cpp |
isLogicalOpOnExec(llvm::MachineInstr const&) | static Register isLogicalOpOnExec(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::S_AND_B64:
case AMDGPU::S_OR_B64:
case AMDGPU::S_XOR_B64:
case AMDGPU::S_ANDN2_B64:
case AMDGPU::S_ORN2_B64:
case AMDGPU::S_NAND_B64:
case AMDGPU::S_NOR_B64:
case AMDGPU::S_XNOR_B64: {
const MachineO... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq 0x48(%rsp), %rdi
callq 0x72bbb0
movl %eax, %ecx
movl %ecx, 0x8(%rsp)
subl $0xf7d, %eax # imm = 0xF7D
je 0xeaa994
jmp 0xeaa7b6
movl 0x8(%rsp), %eax
subl $0xf7f, %eax # imm = 0xF7F
je 0xeaa8a5
jmp 0xeaa7c7
movl 0x8(%rsp), %eax
subl $0xf85, %eax ... | /Target/AMDGPU/SIOptimizeExecMasking.cpp |
llvm::DenseMapIterator<llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>, false>::AdvancePastEmptyBuckets() | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xd5d800
movq %rax, 0x18(%rsp)
callq 0xd60d60
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0xeb44b8
movq 0x8(%rsp), %rax
movq (%rax), %rdi
callq 0xeb2e60
mo... | /llvm/ADT/DenseMap.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [33], llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(char const (&) [33], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x3f7700
movq 0x8(%rsp), %rsi
leaq 0x881e268(%rip), %rax # 0x96df180
addq $0x10... | /llvm/Support/CommandLine.h |
(anonymous namespace)::SIPreEmitPeephole::runOnMachineFunction(llvm::MachineFunction&) | bool SIPreEmitPeephole::runOnMachineFunction(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
bool Changed = false;
MF.RenumberBlocks();
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::iterator TermI = MBB.g... | subq $0xb8, %rsp
movq %rdi, 0xb0(%rsp)
movq %rsi, 0xa8(%rsp)
movq 0xb0(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0xa8(%rsp), %rdi
callq 0xbd6260
movq %rax, 0xa0(%rsp)
movq 0xa0(%rsp), %rdi
callq 0xbdd4d0
movq %rax, %rcx
movq 0x8(%rsp), %rax
movq %rcx, 0x38(%rax)
movq 0x38(%rax), %rdi
callq 0xbf6720
movq %rax, %rcx
movq 0x8... | /Target/AMDGPU/SIPreEmitPeephole.cpp |
llvm::SIProgramInfo::reset(llvm::MachineFunction const&) | void SIProgramInfo::reset(const MachineFunction &MF) {
MCContext &Ctx = MF.getContext();
const MCExpr *ZeroExpr = MCConstantExpr::create(0, Ctx);
VGPRBlocks = ZeroExpr;
SGPRBlocks = ZeroExpr;
Priority = 0;
FloatMode = 0;
Priv = 0;
DX10Clamp = 0;
DebugMode = 0;
IEEEMode = 0;
WgpMode = 0;
MemOrd... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movq 0x18(%rsp), %rdi
callq 0x733b80
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rsi
xorl %eax, %eax
movl %eax, %edi
xorl %ecx, %ecx
movl %ecx, %edx
callq 0x396a5d0
movq %rax, %rcx
movq (%rsp), %rax
movq %rcx, 0x8(%rsp)
mov... | /Target/AMDGPU/SIProgramInfo.cpp |
llvm::SIRegisterInfo::getFrameRegister(llvm::MachineFunction const&) const | Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
// During ISel lowering we always reserve the stack pointer in entry and chain
// functions, but never act... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq 0x138(%rax), %rdi
callq 0xc048c0
movq %rax, 0x8(%rsp)
movq 0x10(%rsp), %rdi
callq 0xbd86a0
movq %rax, (%rsp)
movq (%rsp), %rdi
callq 0xec6fa0
testb $0x1, %al
jne 0xec6f31
jmp 0xec6f63
movq 0x8(%rsp), %rdi
movq 0x10(%rsp), %rsi
callq... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SIRegisterInfo::shouldRealignStack(llvm::MachineFunction const&) const | bool SIRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
// On entry or in chain functions, the base address is 0, so it can't possibly
// need any more alignment.
// FIXME: Should be able to specify the entry frame alig... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
movq 0x10(%rsp), %rdi
callq 0xbd86a0
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rdi
callq 0xec6fa0
testb $0x1, %al
jne 0xec7076
jmp 0xec707d
movb $0x0, 0x27(%rsp)
jmp 0xec7091
movq (%rsp), %rdi
movq 0x10(%rsp), %rsi
callq 0x... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SGPRSpillBuilder::readWriteTmpVGPR(unsigned int, bool) | void readWriteTmpVGPR(unsigned Offset, bool IsLoad) {
if (SavedExecReg) {
// Spill needed lanes
TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
} else {
// The modify and restore of exec clobber SCC, which we would have to save
// and restore. FIXME: We probably would need to ... | subq $0xf8, %rsp
movb %dl, %al
movq %rdi, 0xf0(%rsp)
movl %esi, 0xec(%rsp)
andb $0x1, %al
movb %al, 0xeb(%rsp)
movq 0xf0(%rsp), %rdi
movq %rdi, 0x28(%rsp)
addq $0x3c, %rdi
callq 0x72c560
cmpl $0x0, %eax
je 0xecd59c
movq 0x28(%rsp), %rsi
movq 0x70(%rsi), %rdi
movl 0x40(%rsi), %edx
movl 0xec(%rsp), %ecx
movb 0xeb(%rsp), ... | /Target/AMDGPU/SIRegisterInfo.cpp |
getAlignedAGPRClassForBitWidth(unsigned int) | static const TargetRegisterClass *
getAlignedAGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth == 64)
return &AMDGPU::AReg_64_Align2RegClass;
if (BitWidth == 96)
return &AMDGPU::AReg_96_Align2RegClass;
if (BitWidth == 128)
return &AMDGPU::AReg_128_Align2RegClass;
if (BitWidth == 160)
return... | movl %edi, -0xc(%rsp)
cmpl $0x40, -0xc(%rsp)
jne 0xed2b8c
leaq 0x86f516e(%rip), %rax # 0x95c7cf0
movq %rax, -0x8(%rsp)
jmp 0xed2cc7
cmpl $0x60, -0xc(%rsp)
jne 0xed2ba4
leaq 0x86f58a6(%rip), %rax # 0x95c8440
movq %rax, -0x8(%rsp)
jmp 0xed2cc7
cmpl $0x80, -0xc(%rsp)
jne 0xed2bbf
leaq 0x86f611b(%rip), %rax # 0x95c8c... | /Target/AMDGPU/SIRegisterInfo.cpp |
(anonymous namespace)::SIShrinkInstructions::runOnMachineFunction(llvm::MachineFunction&) | bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
this->MF = &MF;
MRI = &MF.getRegInfo();
ST = &MF.getSubtarget<GCNSubtarget>();
TII = ST->getInstrInfo();
TRI = &TII->getRegisterInfo();
unsigned VCCReg = ST->isWave32() ? AMDGPU::... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x228(%rsp)
movq %rsi, 0x220(%rsp)
movq 0x228(%rsp), %rax
movq %rax, 0xa8(%rsp)
movq 0x220(%rsp), %rdi
callq 0x727890
movq 0xa8(%rsp), %rdi
movq %rax, %rsi
callq 0x312ea30
testb $0x1, %al
jne 0xed6f7a
jmp 0xed6f87
movb $0x0, 0x237(%rsp)
jmp 0xed8029
movq 0xa8(%rsp),... | /Target/AMDGPU/SIShrinkInstructions.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, char>>, llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xedc37e
movl $0x0, 0x14(%rsp)
jmp 0xedc39e
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, char>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0xedc3e7
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0xedc40f
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
shlq... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SIWholeQuadMode::analyzeFunction(llvm::MachineFunction&) | char SIWholeQuadMode::analyzeFunction(MachineFunction &MF) {
std::vector<WorkItem> Worklist;
char GlobalFlags = scanInstructions(MF, Worklist);
while (!Worklist.empty()) {
WorkItem WI = Worklist.back();
Worklist.pop_back();
if (WI.MI)
propagateInstruction(*WI.MI, Worklist);
else
prop... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x30(%rsp), %rdi
callq 0xede600
movq 0x10(%rsp), %rdi
movq 0x48(%rsp), %rsi
leaq 0x30(%rsp), %rdx
callq 0xede610
movb %al, 0x2f(%rsp)
leaq 0x30(%rsp), %rdi
callq 0xedef90
xorb $-0x1, %al
testb $0x1, %al
jne 0xe... | /Target/AMDGPU/SIWholeQuadMode.cpp |
llvm::DenseMap<llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, char>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movl 0x10(%rdi), %eax
movl %eax, 0x1c(%rsp)
movl 0x8(%rdi), %eax
movl %eax, 0x18(%rsp)
callq 0xedc6c0
movl $0x0, 0x14(%rsp)
cmpl $0x0, 0x18(%rsp)
je 0xede5ba
movl $0x40, 0x10(%rsp)
movl 0x18(%rsp), %edi
callq 0x91b7e0
movl %eax, %ecx
addl $0... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SIWholeQuadMode::fromStrictMode(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, char, char) | void SIWholeQuadMode::fromStrictMode(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Before,
Register SavedOrig, char NonStrictState,
char CurrentStrictState) {
MachineInstr *MI;
assert(SavedOrig);
... | subq $0xe8, %rsp
movl %r8d, 0x20(%rsp)
movl %ecx, %eax
movl 0x20(%rsp), %ecx
movl %eax, 0x24(%rsp)
movq %rdx, %r8
movl 0x24(%rsp), %edx
movb %r9b, %al
movq %r8, 0xe0(%rsp)
movl %edx, 0xdc(%rsp)
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movb %cl, 0xc7(%rsp)
movb %al, 0xc6(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x28(%r... | /Target/AMDGPU/SIWholeQuadMode.cpp |
(anonymous namespace)::SIWholeQuadMode::toStrictMode(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, char) | void SIWholeQuadMode::toStrictMode(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Before,
Register SaveOrig, char StrictStateNeeded) {
MachineInstr *MI;
assert(SaveOrig);
assert(StrictStateNeeded == StateStrictWWM ||
StrictStateNe... | subq $0xd8, %rsp
movb %r8b, %al
movq %rdx, 0xd0(%rsp)
movl %ecx, 0xcc(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movb %al, 0xb7(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x18(%rsp)
movsbl 0xb7(%rsp), %eax
cmpl $0x2, %eax
jne 0xee7cba
movq 0xb8(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x90(... | /Target/AMDGPU/SIWholeQuadMode.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, char>>, llvm::MachineInstr const*, char, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr c... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xee8e80
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0xedc5a0
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0xee8d32
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rsp)
... | /llvm/ADT/DenseMap.h |
recursivelyVisitUsers(llvm::GlobalValue&, llvm::SmallPtrSetImpl<llvm::Function*>&) | static void
recursivelyVisitUsers(GlobalValue &GV,
SmallPtrSetImpl<Function *> &FuncsToAlwaysInline) {
SmallVector<User *, 16> Stack(GV.users());
SmallPtrSet<const Value *, 8> Visited;
while (!Stack.empty()) {
User *U = Stack.pop_back_val();
if (!Visited.insert(U).second)
con... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x160(%rsp)
movq %rsi, 0x158(%rsp)
movq 0x160(%rsp), %rdi
callq 0x7ba270
movq %rax, 0xb8(%rsp)
movq %rdx, 0xc0(%rsp)
leaq 0xc8(%rsp), %rdi
leaq 0xb8(%rsp), %rsi
callq 0xeebd00
leaq 0x58(%rsp), %rdi
callq 0xeebd60
leaq 0xc8(%rsp), %rdi
callq 0x3a8dce0
xorb $-0x1, %al... | /Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp |
llvm::User** llvm::SmallVectorImpl<llvm::User*>::insert<llvm::Value::user_iterator_impl<llvm::User>, void>(llvm::User**, llvm::Value::user_iterator_impl<llvm::User>, llvm::Value::user_iterator_impl<llvm::User>) | iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(From, To);
return this->begin()+InsertElt;
}
... | subq $0xe8, %rsp
movq %rdx, 0xd8(%rsp)
movq %rcx, 0xd0(%rsp)
movq %rdi, 0xc8(%rsp)
movq %rsi, 0xc0(%rsp)
movq 0xc8(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x20(%rsp)
callq 0xeec510
movq 0x18(%rsp), %rdi
movq %rax, %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
sarq $0x3, %rax
movq %rax, 0xb8(%rsp... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::AMDGPUAnnotateKernelFeatures::runOnSCC(llvm::CallGraphSCC&) | bool AMDGPUAnnotateKernelFeatures::runOnSCC(CallGraphSCC &SCC) {
bool Changed = false;
for (CallGraphNode *I : SCC) {
Function *F = I->getFunction();
// Ignore functions with graphics calling conventions, these are currently
// not allowed to have kernel arguments.
if (!F || F->isDeclaration() || A... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, (%rsp)
movb $0x0, 0x37(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rdi
callq 0xeed810
movq %rax, 0x20(%rsp)
movq 0x28(%rsp), %rdi
callq 0xeed840
movq %rax, 0x18(%rsp)
leaq 0x20(%rsp), %rdi
leaq 0x18(%rs... | /Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp |
llvm::initializeAMDGPUArgumentUsageInfoPass(llvm::PassRegistry&) | void ArgDescriptor::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const {
if (!isSet()) {
OS << "<not set>\n";
return;
}
if (isRegister())
OS << "Reg " << printReg(getRegister(), TRI);
else
OS << "Stack offset " << getStackOffset();
if (isMasked()) {
OS ... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x7ddcb0
movq %rax, 0x8(%rsp)
leaq 0x886dc35(%rip), %rdi # 0x975e4a4
leaq 0x1a(%rip), %rsi # 0xef0890
leaq 0x8(%rsp), %rdx
callq 0x7ddbd0
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nop
| /Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp |
llvm::AMDGPUArgumentUsageInfo::print(llvm::raw_ostream&, llvm::Module const*) const | void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
for (const auto &FI : ArgInfoMap) {
OS << "Arguments for " << FI.first->getName() << '\n'
<< " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
<< " DispatchPtr: " << FI.second.DispatchPtr
<< " QueuePtr:... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdx, 0x50(%rsp)
movq 0x60(%rsp), %rax
addq $0x20, %rax
movq %rax, 0x48(%rsp)
movq 0x48(%rsp), %rdi
callq 0xef1500
movq %rax, 0x38(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x48(%rsp), %rdi
callq 0xef15d0
movq %rax, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
leaq 0x38(%rsp... | /Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp |
llvm::AMDGPUFunctionArgInfo::getPreloadedValue(llvm::AMDGPUFunctionArgInfo::PreloadedValue) const | std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
AMDGPUFunctionArgInfo::getPreloadedValue(
AMDGPUFunctionArgInfo::PreloadedValue Value) const {
switch (Value) {
case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
... | subq $0x258, %rsp # imm = 0x258
movq %rdi, 0x88(%rsp)
movq %rdi, %rax
movq %rax, 0x90(%rsp)
movq %rdi, 0x250(%rsp)
movq %rsi, 0x248(%rsp)
movl %edx, 0x244(%rsp)
movq 0x248(%rsp), %rax
movq %rax, 0x98(%rsp)
movl 0x244(%rsp), %eax
movq %rax, 0xa0(%rsp)
movq 0xa0(%rsp), %rax
leaq 0x58c680d(%rip), %rcx # 0x67b... | /Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function const*, llvm::AMDGPUFunctionArgInfo, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseMapPair<llvm::Function const*, llvm::AMDGPUFunctionArgInfo>>, llvm::Function const*, llvm::AMDGPUFunctionArgInfo, llvm::DenseMapInfo<llvm::Function const*, void>, llv... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0xef24ce
movl $0x0, 0x14(%rsp)
jmp 0xef24ee
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $... | /llvm/ADT/DenseMap.h |
llvm::IRBuilderBase::CreateFSub(llvm::Value*, llvm::Value*, llvm::Twine const&, llvm::MDNode*) | Value *CreateFSub(Value *L, Value *R, const Twine &Name = "",
MDNode *FPMD = nullptr) {
if (IsFPConstrained)
return CreateConstrainedFPBinOp(Intrinsic::experimental_constrained_fsub,
L, R, nullptr, Name, FPMD);
if (Value *V = Folder.FoldBinOpFMF(I... | subq $0xd8, %rsp
movq %rdi, 0xc8(%rsp)
movq %rsi, 0xc0(%rsp)
movq %rdx, 0xb8(%rsp)
movq %rcx, 0xb0(%rsp)
movq %r8, 0xa8(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x50(%rsp)
testb $0x1, 0x6c(%rax)
je 0xefbae6
movq 0xc0(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0xb0(%rsp), %rax
movq ... | /llvm/IR/IRBuilder.h |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [29], llvm::cl::desc, llvm::cl::initializer<int>>(char const (&) [29], llvm::cl::desc const&, llvm::cl::initializer<int> const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x76e5e0
movq 0x8(%rsp), %rsi
leaq 0x87e2e28(%rip), %rax # 0x96defe0
addq $0x10... | /llvm/Support/CommandLine.h |
llvm::DenseMap<llvm::BasicBlock const*, std::optional<bool>, llvm::DenseMapInfo<llvm::BasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock const*, std::optional<bool>>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0xeff340
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0xeff390
testb $0x1, %al
jne 0xeff316
jmp 0xeff321
movq (%rsp), %rdi
callq 0xeff400
jmp 0xeff333
movq (%rsp), %rax
mov... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::BasicBlock const*, std::optional<bool>, llvm::DenseMapInfo<llvm::BasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock const*, std::optional<bool>>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0xeff3c7
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0xeff3ef
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
shlq... | /llvm/ADT/DenseMap.h |
llvm::IRPosition::getAnchorValue() const | Value &getAnchorValue() const {
switch (getEncodingBits()) {
case ENC_VALUE:
case ENC_RETURNED_VALUE:
case ENC_FLOATING_FUNCTION:
return *getAsValuePtr();
case ENC_CALL_SITE_ARGUMENT_USE:
return *(getAsUsePtr()->getUser());
default:
llvm_unreachable("Unkown encoding!");
};
... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rdi
movq %rdi, (%rsp)
callq 0xf022e0
movsbl %al, %eax
subl $0x3, %eax
jb 0xf02223
jmp 0xf02221
jmp 0xf02233
movq (%rsp), %rdi
callq 0xf022f0
movq %rax, 0x10(%rsp)
jmp 0xf0224b
movq (%rsp), %rdi
callq 0xf02300
movq %rax, %rdi
callq 0x78d120
movq %rax, 0x10(%rsp)
jmp... | /llvm/Transforms/IPO/Attributor.h |
(anonymous namespace)::AAAMDAttributesFunction::getAsStr[abi:cxx11](llvm::Attributor*) const | const std::string getAsStr(Attributor *) const override {
std::string Str;
raw_string_ostream OS(Str);
OS << "AMDInfo[";
for (auto Attr : ImplicitAttrs)
if (isAssumed(Attr.first))
OS << ' ' << Attr.second;
OS << " ]";
return OS.str();
} | subq $0xc8, %rsp
movq %rdi, (%rsp)
movq %rdi, %rax
movq %rax, 0x8(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x90(%rsp), %rdi
callq 0x3490c0
leaq 0x58(%rsp), %rdi
leaq 0x90(%rsp), %rsi
callq 0x3f8120
leaq 0x58(%rsp), %rdi
leaq 0x58b54e8(%rip)... | /Target/AMDGPU/AMDGPUAttributor.cpp |
(anonymous namespace)::AAAMDGPUNoAGPR::manifest(llvm::Attributor&) | ChangeStatus manifest(Attributor &A) override {
if (!getAssumed())
return ChangeStatus::UNCHANGED;
LLVMContext &Ctx = getAssociatedFunction()->getContext();
return A.manifestAttrs(getIRPosition(),
{Attribute::get(Ctx, "amdgpu-no-agpr")});
} | subq $0x88, %rsp
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x78(%rsp), %rdi
movq %rdi, 0x18(%rsp)
addq $0x50, %rdi
callq 0xf0b5f0
testb $0x1, %al
jne 0xf0c948
movl $0x1, 0x84(%rsp)
jmp 0xf0ca18
movq 0x18(%rsp), %rdi
addq $0x40, %rdi
callq 0xf024c0
movq %rax, %rdi
callq 0x3033f40
movq 0x18(%rsp), %rdi
movq %rax, ... | /Target/AMDGPU/AMDGPUAttributor.cpp |
llvm::SmallPtrSetIterator<llvm::Instruction*>::operator++() | inline SmallPtrSetIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
if (shouldReverseIterate()) {
--Bucket;
RetreatIfNotValid();
return *this;
}
++Bucket;
AdvanceIfNotValid();
return *this;
} | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0x786eb0
testb $0x1, %al
jne 0xf11f9d
jmp 0xf11fbb
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x8, %rax
movq %rax, (%rdi)
callq 0x786f70
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0xf11fd7
movq (%rsp), %rdi
movq (%rdi), %rax
addq $0x8, ... | /llvm/ADT/SmallPtrSet.h |
llvm::DenseMapIterator<llvm::SmallPtrSet<llvm::Instruction*, 4u> const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SmallPtrSet<llvm::Instruction*, 4u> const*, void>, llvm::detail::DenseSetPair<llvm::SmallPtrSet<llvm::Instruction*, 4u> const*>, false>::operator++() | inline DenseMapIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
assert(Ptr != End && "incrementing end() iterator");
if (shouldReverseIterate<KeyT>()) {
--Ptr;
RetreatPastEmptyBuckets();
return *this;
}
++Ptr;
AdvancePastEmptyBuc... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0xf118e0
testb $0x1, %al
jne 0xf121fd
jmp 0xf1221b
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x8, %rax
movq %rax, (%rdi)
callq 0xf11a70
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0xf12237
movq (%rsp), %rdi
movq (%rdi), %rax
addq $0x8, ... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::PointerIntPair<llvm::Instruction const*, 1u, llvm::ExplorationDirection, llvm::PointerLikeTypeTraits<llvm::Instruction const*>, llvm::PointerIntPairInfo<llvm::Instruction const*, 1u, llvm::PointerLikeTypeTraits<llvm::Instruction const*>>>, llvm::detail::DenseSetEmpty, llvm::Dense... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xf12440
cmpl $0x0, %eax
jne 0xf123a2
jmp 0xf1243a
callq 0xf12450
movq %rax, 0x28(%rsp)
callq 0xf12460
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0xf12470
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0xf12480
movq %rax, 0x... | /llvm/ADT/DenseMap.h |
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