name string | code string | asm string | file string |
|---|---|---|---|
(anonymous namespace)::WebAssemblyReplacePhysRegs::runOnMachineFunction(llvm::MachineFunction&) | bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG({
dbgs() << "********** Replace Physical Registers **********\n"
<< "********** Function: " << MF.getName() << '\n';
});
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &TRI = *MF.getSubtarget<WebAssemblySub... | subq $0xe8, %rsp
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
jmp 0x1f9b119
movq 0xd8(%rsp), %rdi
callq 0x73cca0
movq %rax, 0xd0(%rsp)
movq 0xd8(%rsp), %rdi
callq 0x1f19da0
movq %rax, %rdi
callq 0x1f13b90
movq %rax, 0xc8(%rsp)
movb $0x0, 0xc7(%rsp)
movl $0x1, 0xc0(%rsp)
cmpl $0xf, 0xc0(%rsp)
jae 0x1f9b3ca
cmpl $0x2, 0xc... | /Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp |
llvm::WebAssembly::SortRegionInfo::getBottom(llvm::WebAssemblyException const*) | MachineBasicBlock *SortRegionInfo::getBottom(const WebAssemblyException *WE) {
MachineBasicBlock *Bottom = WE->getHeader();
for (MachineBasicBlock *MBB : WE->blocks())
if (MBB->getNumber() > Bottom->getNumber())
Bottom = MBB;
return Bottom;
} | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x48(%rsp), %rdi
callq 0x1f9c8b0
movq %rax, 0x40(%rsp)
movq 0x48(%rsp), %rdi
callq 0x1f9c8c0
movq %rax, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
leaq 0x28(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0xd6ae20
movq %rax, 0x20(%rsp)
movq 0x38(%rsp... | /Target/WebAssembly/WebAssemblySortRegion.cpp |
(anonymous namespace)::WebAssemblyMemIntrinsicResults::runOnMachineFunction(llvm::MachineFunction&) | bool WebAssemblyMemIntrinsicResults::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG({
dbgs() << "********** Memory Intrinsic Results **********\n"
<< "********** Function: " << MF.getName() << '\n';
});
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &MDT = getAnalysis<MachineDominatorT... | subq $0x98, %rsp
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0x1f9e556
movq 0x88(%rsp), %rdi
callq 0x73cca0
movq 0x10(%rsp), %rdi
movq %rax, 0x80(%rsp)
callq 0x88b270
movq %rax, %rdi
callq 0x88b290
movq %rax, 0x78(%rsp)
movq 0x88(%rsp), %rdi
callq 0x1f19da0
movq %rax, %rd... | /Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp |
llvm::WebAssemblyDebugValueManager::WebAssemblyDebugValueManager(llvm::MachineInstr*) | WebAssemblyDebugValueManager::WebAssemblyDebugValueManager(MachineInstr *Def)
: Def(Def) {
if (!Def->getMF()->getFunction().getSubprogram())
return;
// This code differs from MachineInstr::collectDebugValues in that it scans
// the whole BB, not just contiguous DBG_VALUEs, until another definition to
/... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x48(%rsp), %rax
movq %rax, (%rdi)
addq $0x8, %rdi
callq 0xe449d0
movq 0x10(%rsp), %rdi
addq $0x20, %rdi
xorl %esi, %esi
callq 0x72e210
movq 0x48(%rsp), %rdi
callq 0x741a30
movq %rax, %rdi
callq 0x727890
movq %... | /Target/WebAssembly/WebAssemblyDebugValueManager.cpp |
isSameScalarConst(llvm::MachineInstr const*, llvm::MachineInstr const*) | static bool isSameScalarConst(const MachineInstr *A, const MachineInstr *B) {
if (A->getOpcode() != B->getOpcode() ||
!WebAssembly::isScalarConst(A->getOpcode()) ||
!WebAssembly::isScalarConst(B->getOpcode()))
return false;
const MachineOperand &OpA = A->getOperand(1), &OpB = B->getOperand(1);
if ... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rdi
callq 0x72bbb0
movl %eax, 0x1c(%rsp)
movq 0x30(%rsp), %rdi
callq 0x72bbb0
movl %eax, %ecx
movl 0x1c(%rsp), %eax
cmpl %ecx, %eax
jne 0x1fa080c
movq 0x38(%rsp), %rdi
callq 0x72bbb0
movl %eax, %edi
callq 0x1fa0730
testb $0x1, %al
jne 0x1fa0... | /Target/WebAssembly/WebAssemblyDebugValueManager.cpp |
llvm::WebAssemblyTargetLowering::computeKnownBitsForTargetNode(llvm::SDValue, llvm::KnownBits&, llvm::APInt const&, llvm::SelectionDAG const&, unsigned int) const | void WebAssemblyTargetLowering::computeKnownBitsForTargetNode(
const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
const SelectionDAG &DAG, unsigned Depth) const {
switch (Op.getOpcode()) {
default:
break;
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = Op.getConstantOperandVal(0);
... | subq $0x68, %rsp
movl 0x70(%rsp), %eax
movq %rsi, 0x58(%rsp)
movl %edx, 0x60(%rsp)
movq %rdi, 0x50(%rsp)
movq %rcx, 0x48(%rsp)
movq %r8, 0x40(%rsp)
movq %r9, 0x38(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x98d4c0
subl $0x2e, %eax
je 0x1fab8db
jmp 0x1fab8d6
jmp 0x1fab971
leaq 0x58(%rsp), %rdi
xorl %esi, %esi
callq 0x992840
mov... | /Target/WebAssembly/WebAssemblyISelLowering.cpp |
llvm::WebAssemblyTargetLowering::getPreferredVectorAction(llvm::MVT) const | TargetLoweringBase::LegalizeTypeAction
WebAssemblyTargetLowering::getPreferredVectorAction(MVT VT) const {
if (VT.isFixedLengthVector()) {
MVT EltVT = VT.getVectorElementType();
// We have legal vector types with these lane types, so widening the
// vector would let us use some of the lanes directly witho... | subq $0x28, %rsp
movb %sil, %al
movb %al, 0x26(%rsp)
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x26(%rsp), %rdi
callq 0x7ac540
testb $0x1, %al
jne 0x1fab9ad
jmp 0x1fabacf
leaq 0x26(%rsp), %rdi
callq 0x5350f0
movb %al, 0x17(%rsp)
leaq 0x16(%rsp), %rdi
movl $0x5, %esi
callq 0x5345c0
leaq 0x17(... | /Target/WebAssembly/WebAssemblyISelLowering.cpp |
callingConvSupported(unsigned int) | static bool callingConvSupported(CallingConv::ID CallConv) {
// We currently support the language-independent target-independent
// conventions. We don't yet have a way to annotate calls with properties like
// "cold", and we don't have any call-clobbered registers, so these are mostly
// all handled the same.
... | movl %edi, -0x4(%rsp)
movb $0x1, %al
cmpl $0x0, -0x4(%rsp)
movb %al, -0x5(%rsp)
je 0x1fadfbb
movb $0x1, %al
cmpl $0x8, -0x4(%rsp)
movb %al, -0x5(%rsp)
je 0x1fadfbb
movb $0x1, %al
cmpl $0x9, -0x4(%rsp)
movb %al, -0x5(%rsp)
je 0x1fadfbb
movb $0x1, %al
cmpl $0xe, -0x4(%rsp)
movb %al, -0x5(%rsp)
je 0x1fadfbb
movb $0x1, %al... | /Target/WebAssembly/WebAssemblyISelLowering.cpp |
bool llvm::PatternMatch::Shuffle_match<llvm::PatternMatch::ThreeOps_match<llvm::PatternMatch::class_match<llvm::Value>, llvm::PatternMatch::class_match<llvm::Value>, llvm::PatternMatch::cstval_pred_ty<llvm::PatternMatch::is_zero_int, llvm::ConstantInt, true>, 62u>, llvm::PatternMatch::class_match<llvm::Value>, llvm::Pa... | bool match(OpTy *V) {
if (auto *I = dyn_cast<ShuffleVectorInst>(V)) {
return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)) &&
Mask.match(I->getShuffleMask());
}
return false;
} | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x40(%rsp), %rdi
callq 0xa969b0
movq %rax, 0x38(%rsp)
cmpq $0x0, 0x38(%rsp)
je 0x1fbd52a
movq 0x38(%rsp), %rdi
xorl %esi, %esi
callq 0xa49ab0
movq 0x20(%rsp), %rdi
movq %rax, %rsi
callq 0x1fbd540
movb %al, %cl
... | /llvm/IR/PatternMatch.h |
(anonymous namespace)::WebAssemblyFastISel::copyValue(unsigned int) | unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
Register ResultReg = createResultReg(MRI.getRegClass(Reg));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::COPY),
ResultReg)
.addReg(Reg);
return ResultReg;
} | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movl %esi, 0x4c(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x30(%rax), %rax
movq %rax, (%rsp)
movl 0x4c(%rsp), %esi
leaq 0x44(%rsp), %rdi
callq 0x72e210
movq (%rsp), %rdi
movl 0x44(%rsp), %esi
callq 0x83a650
movq 0x8(%rsp), %rdi
movq %rax, %rsi
callq 0x3ed2180
movl %eax... | /Target/WebAssembly/WebAssemblyFastISel.cpp |
llvm::X86AsmPrinter::PrintIntelMemReference(llvm::MachineInstr const*, unsigned int, llvm::raw_ostream&, char const*) | void X86AsmPrinter::PrintIntelMemReference(const MachineInstr *MI,
unsigned OpNo, raw_ostream &O,
const char *Modifier) {
const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
unsigned ScaleVal = MI->getOperand(... | subq $0x88, %rsp
movq %rdi, 0x80(%rsp)
movq %rsi, 0x78(%rsp)
movl %edx, 0x74(%rsp)
movq %rcx, 0x68(%rsp)
movq %r8, 0x60(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x78(%rsp), %rdi
movl 0x74(%rsp), %esi
addl $0x0, %esi
callq 0x72c4d0
movq %rax, 0x58(%rsp)
movq 0x78(%rsp), %rdi
movl 0x74(%rsp), %esi
addl $0x1,... | /Target/X86/X86AsmPrinter.cpp |
getSrcIdx(llvm::MachineInstr const*, unsigned int) | static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) {
if (X86II::isKMasked(MI->getDesc().TSFlags)) {
// Skip mask operand.
++SrcIdx;
if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
// Skip passthru operand.
++SrcIdx;
}
}
return SrcIdx;
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
callq 0x7349e0
movq 0x18(%rax), %rdi
callq 0x1fdf9a0
testb $0x1, %al
jne 0x1fdebe6
jmp 0x1fdec17
movl 0xc(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xc(%rsp)
movq 0x10(%rsp), %rdi
callq 0x7349e0
movq 0x18(%rax), %rdi
callq 0x1fdf9c0
testb $0... | /Target/X86/X86MCInstLower.cpp |
printConstant(llvm::APFloat const&, llvm::raw_ostream&, bool) | static void printConstant(const APFloat &Flt, raw_ostream &CS,
bool PrintZero = false) {
SmallString<32> Str;
// Force scientific notation to distinguish from integers.
if (PrintZero)
APFloat::getZero(Flt.getSemantics()).toString(Str, 0, 0);
else
Flt.toString(Str, 0, 0);
CS <... | subq $0x78, %rsp
movb %dl, %al
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
andb $0x1, %al
movb %al, 0x67(%rsp)
leaq 0x28(%rsp), %rdi
callq 0xb47130
testb $0x1, 0x67(%rsp)
je 0x1fe00b5
movq 0x70(%rsp), %rdi
callq 0x41c790
movq %rax, %rsi
leaq 0x8(%rsp), %rdi
xorl %edx, %edx
callq 0xe1d650
leaq 0x8(%rsp), %rdi
leaq 0x28(... | /Target/X86/X86MCInstLower.cpp |
convertTailJumpOpcode(unsigned int) | static unsigned convertTailJumpOpcode(unsigned Opcode) {
switch (Opcode) {
case X86::TAILJMPr:
Opcode = X86::JMP32r;
break;
case X86::TAILJMPm:
Opcode = X86::JMP32m;
break;
case X86::TAILJMPr64:
Opcode = X86::JMP64r;
break;
case X86::TAILJMPm64:
Opcode = X86::JMP64m;
break;
c... | movl %edi, -0x4(%rsp)
movl -0x4(%rsp), %eax
addl $0xffffed10, %eax # imm = 0xFFFFED10
movl %eax, %ecx
movq %rcx, -0x10(%rsp)
subl $0x9, %eax
ja 0x1fe075c
movq -0x10(%rsp), %rax
leaq 0x4f9605f(%rip), %rcx # 0x6f76764
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x7a2, -0x4(%rsp) # imm = 0x7A2... | /Target/X86/X86MCInstLower.cpp |
llvm::X86RegisterInfo::getReservedRegs(llvm::MachineFunction const&) const | BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const X86FrameLowering *TFI = getFrameLowering(MF);
// Set the floating point control register as reserved.
Reserved.set(X86::FPCW);
// Set the floating point status register as reserved.
Reserv... | subq $0x2f8, %rsp # imm = 0x2F8
movq %rdi, 0x28(%rsp)
movq %rdi, %rax
movq %rax, 0x20(%rsp)
movq %rdi, 0x2f0(%rsp)
movq %rsi, 0x2e8(%rsp)
movq %rdx, 0x2e0(%rsp)
movq 0x2e8(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movb $0x0, 0x2df(%rsp)
addq $0x8, %rdi
callq 0x73d670
movq 0x28(%rsp), %rdi
movl %eax, %esi
xorl %edx, ... | /Target/X86/X86RegisterInfo.cpp |
llvm::X86RegisterInfo::eliminateFrameIndex(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, int, unsigned int, llvm::RegScavenger*) const | bool
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
... | subq $0x108, %rsp # imm = 0x108
movq %rsi, 0xf8(%rsp)
movq %rdi, 0xf0(%rsp)
movl %edx, 0xec(%rsp)
movl %ecx, 0xe8(%rsp)
movq %r8, 0xe0(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x28(%rsp)
leaq 0xf8(%rsp), %rdi
callq 0x7410f0
movq %rax, 0xd8(%rsp)
movq 0xd8(%rsp), %rdi
callq 0x73fb40
movq %rax, 0xd0(%rsp)
movq 0... | /Target/X86/X86RegisterInfo.cpp |
llvm::SmallSetIterator<unsigned short, 8u, std::less<unsigned short>>::SmallSetIterator(llvm::SmallSetIterator<unsigned short, 8u, std::less<unsigned short>>&&) | SmallSetIterator(SmallSetIterator &&Other) : isSmall(Other.isSmall) {
if (isSmall)
VecIter = std::move(Other.VecIter);
else
// Use placement new, to make sure SetIter is properly constructed, even
// if it is not trivially copy-able (e.g. in MSVC).
new (&SetIter) SetIterTy(std::move(Othe... | movq %rdi, -0x8(%rsp)
movq %rsi, -0x10(%rsp)
movq -0x8(%rsp), %rax
movq %rax, -0x18(%rsp)
movq -0x10(%rsp), %rcx
movb 0x8(%rcx), %cl
andb $0x1, %cl
movb %cl, 0x8(%rax)
testb $0x1, 0x8(%rax)
je 0x1fea1ba
movq -0x18(%rsp), %rax
movq -0x10(%rsp), %rcx
movq (%rcx), %rcx
movq %rcx, (%rax)
jmp 0x1fea1ca
movq -0x18(%rsp), %ra... | /llvm/ADT/SmallSet.h |
(anonymous namespace)::X86PassConfig::addRegAssignAndRewriteOptimized() | bool X86PassConfig::addRegAssignAndRewriteOptimized() {
// Don't support tile RA when RA is specified by command line "-regalloc".
if (!isCustomizedRegAlloc() && EnableTileRAPass) {
// Allocate tile register first.
addPass(createGreedyRegisterAllocator(onlyAllocateTileRegisters));
addPass(createX86TileC... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x370b130
testb $0x1, %al
jne 0x1fef7f9
leaq 0x778743d(%rip), %rdi # 0x9776be0
addq $0x80, %rdi
callq 0x3f1b60
testb $0x1, %al
jne 0x1fef7b5
jmp 0x1fef7f9
leaq 0x10(%rsp), %rdi
leaq 0x51f(%rip), %rsi # 0x1fefce0
callq 0xc113... | /Target/X86/X86TargetMachine.cpp |
llvm::BasicTTIImplBase<llvm::X86TTIImpl>::getCmpSelInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::CmpInst::Predicate, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
CmpInst::Predicate VecPred,
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) {
const TargetLoweringBase *TLI = ge... | subq $0x188, %rsp # imm = 0x188
movq 0x190(%rsp), %rax
movq %rdi, 0x170(%rsp)
movl %esi, 0x16c(%rsp)
movq %rdx, 0x160(%rsp)
movq %rcx, 0x158(%rsp)
movl %r8d, 0x154(%rsp)
movl %r9d, 0x150(%rsp)
movq 0x170(%rsp), %rdi
movq %rdi, 0x38(%rsp)
callq 0x1ff43c0
movq %rax, 0x148(%rsp)
movq 0x148(%rsp), %rdi
movl 0x16... | /llvm/CodeGen/BasicTTIImpl.h |
(anonymous namespace)::WinEHStatePass::addStateStores(llvm::Function&, llvm::WinEHFuncInfo&) | void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) {
// Mark the registration node. The backend needs to know which alloca it is so
// that it can recover the original frame pointer.
IRBuilder<> Builder(RegNode->getNextNode());
Value *RegNodeI8 = Builder.CreateBitCast(RegNode, Builder.get... | subq $0x8f8, %rsp # imm = 0x8F8
movq %rdi, 0x8f0(%rsp)
movq %rsi, 0x8e8(%rsp)
movq %rdx, 0x8e0(%rsp)
movq 0x8f0(%rsp), %rax
movq %rax, 0xb0(%rsp)
movq 0x90(%rax), %rdi
addq $0x18, %rdi
callq 0x7cd0e0
movq %rax, 0x90(%rsp)
leaq 0x840(%rsp), %rdi
callq 0x7b2080
movq 0x90(%rsp), %rsi
movq 0x840(%rsp), %rcx
movq... | /Target/X86/X86WinEHState.cpp |
(anonymous namespace)::WinEHStatePass::unlinkExceptionRegistration(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&) | void WinEHStatePass::unlinkExceptionRegistration(IRBuilder<> &Builder) {
// Clone Link into the current BB for better address mode folding.
if (auto *GEP = dyn_cast<GetElementPtrInst>(Link)) {
GEP = cast<GetElementPtrInst>(GEP->clone());
Builder.Insert(GEP);
Link = GEP;
}
LLVMContext &C = Builder.g... | subq $0xf8, %rsp
movq %rdi, 0xf0(%rsp)
movq %rsi, 0xe8(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0xa8(%rax), %rdi
callq 0xa97c00
movq %rax, 0xe0(%rsp)
cmpq $0x0, 0xe0(%rsp)
je 0x2027be9
movq 0xe0(%rsp), %rdi
callq 0x307c540
movq %rax, %rdi
callq 0x14f7ed0
movq %rax, 0xe0(%rsp)
movq 0xe8(%rsp), %rax
movq %r... | /Target/X86/X86WinEHState.cpp |
getPredState(llvm::DenseMap<llvm::BasicBlock*, int, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, int>>&, llvm::Function&, int, llvm::BasicBlock*) | static int getPredState(DenseMap<BasicBlock *, int> &FinalStates, Function &F,
int ParentBaseState, BasicBlock *BB) {
// The entry block has no predecessors but we know that the prologue always
// sets us up with a fixed state.
if (&F.getEntryBlock() == BB)
return ParentBaseState;
/... | subq $0x98, %rsp
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movl %edx, 0x7c(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
callq 0x7df0f0
cmpq 0x70(%rsp), %rax
jne 0x20284e4
movl 0x7c(%rsp), %eax
movl %eax, 0x94(%rsp)
jmp 0x2028649
movq 0x70(%rsp), %rdi
callq 0x2024ed0
testb $0x1, %al
jne 0x20284f4
jmp 0x2028504
mo... | /Target/X86/X86WinEHState.cpp |
llvm::DenseMap<llvm::BasicBlock*, int, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, int>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0x2029bd0
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0x2029c20
testb $0x1, %al
jne 0x2029ba6
jmp 0x2029bb1
movq (%rsp), %rdi
callq 0x2029c90
jmp 0x2029bc3
movq (%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>>* llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>>>, llvm::B... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x202d430
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x202d250
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>>>, llvm::BasicBlock*, llvm::TinyPtrVector<llvm::BasicBlock*>, llvm::DenseMapInfo<llvm::BasicBlock... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x202d250
cmpl $0x0, %eax
jne 0x202e9d2
jmp 0x202ea72
callq 0x202d260
movq %rax, 0x28(%rsp)
callq 0x202d270
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0x202d810
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0x202d820
movq %... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock const*, int, llvm::DenseMapInfo<llvm::BasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock const*, int>>, llvm::BasicBlock const*, int, llvm::DenseMapInfo<llvm::BasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock const*, int>>::destro... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x202f2c0
cmpl $0x0, %eax
jne 0x202f222
jmp 0x202f2ba
callq 0x202f2d0
movq %rax, 0x28(%rsp)
callq 0x202f2e0
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0x202f2f0
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0x202f300
movq %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::X86CallFrameOptimization::isLegal(llvm::MachineFunction&) | bool X86CallFrameOptimization::isLegal(MachineFunction &MF) {
if (NoX86CFOpt.getValue())
return false;
// We can't encode multiple DW_CFA_GNU_args_size or DW_CFA_def_cfa_offset
// in the compact unwind encoding that Darwin uses. So, bail if there
// is a danger of that being generated.
if (STI->isTargetD... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq %rax, (%rsp)
leaq 0x77443da(%rip), %rdi # 0x9776d88
addq $0x80, %rdi
callq 0x16070c0
testb $0x1, (%rax)
je 0x20329c9
movb $0x0, 0x77(%rsp)
jmp 0x2032bff
movq (%rsp), %rax
movq 0x48(%rax), %rdi
callq 0x2034470
testb $0x1, %al
jne 0... | /Target/X86/X86CallFrameOptimization.cpp |
(anonymous namespace)::X86CallFrameOptimization::adjustCallSequence(llvm::MachineFunction&, (anonymous namespace)::X86CallFrameOptimization::CallContext const&) | void X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF,
const CallContext &Context) {
// Ok, we can in fact do the transformation for this call.
// Do not remove the FrameSetup instruction, but adjust the parameters.
// PEI will end up finalizing th... | subq $0x388, %rsp # imm = 0x388
movq %rdi, 0x380(%rsp)
movq %rsi, 0x378(%rsp)
movq %rdx, 0x370(%rsp)
movq 0x380(%rsp), %rax
movq %rax, 0xe0(%rsp)
movq 0x370(%rsp), %rax
movq (%rax), %rax
movq %rax, 0x368(%rsp)
leaq 0x368(%rsp), %rdi
callq 0x73ff20
movq %rax, %rdi
callq 0x73fb40
movq %rax, %rcx
movq 0xe0(%rsp... | /Target/X86/X86CallFrameOptimization.cpp |
(anonymous namespace)::X86CallFrameOptimization::canFoldIntoRegPush(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register) | MachineInstr *X86CallFrameOptimization::canFoldIntoRegPush(
MachineBasicBlock::iterator FrameSetup, Register Reg) {
// Do an extremely restricted form of load folding.
// ISel will often create patterns like:
// movl 4(%edi), %eax
// movl 8(%edi), %ecx
// movl 12(%edi), %edx
// movl %edx, 8(... | subq $0x58, %rsp
movq %rsi, 0x48(%rsp)
movl %edx, 0x44(%rsp)
movq %rdi, 0x38(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x44(%rsp), %rdi
callq 0x744f60
testb $0x1, %al
jne 0x2035318
movq $0x0, 0x50(%rsp)
jmp 0x203541d
movq 0x10(%rsp), %rax
movq 0x50(%rax), %rdi
movl 0x44(%rsp), %eax
movl %eax, 0x34(%rsp)
mo... | /Target/X86/X86CallFrameOptimization.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineOperand*, llvm::MachineInstr*, llvm::DenseMapInfo<llvm::MachineOperand*, void>, llvm::detail::DenseMapPair<llvm::MachineOperand*, llvm::MachineInstr*>>, llvm::MachineOperand*, llvm::MachineInstr*, llvm::DenseMapInfo<llvm::MachineOperand*, void>, llvm::detail::DenseMapPair<... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0x203a5be
movl $0x0, 0x14(%rsp)
jmp 0x203a5de
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq... | /llvm/ADT/DenseMap.h |
llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::~CodeGenPassBuilder() | explicit CodeGenPassBuilder(TargetMachineT &TM,
const CGPassBuilderOption &Opts,
PassInstrumentationCallbacks *PIC)
: TM(TM), Opt(Opts), PIC(PIC) {
// Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
// substitutePass(&P... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, 0x8(%rsp)
addq $0x128, %rdi # imm = 0x128
callq 0xc13d20
movq 0x8(%rsp), %rdi
addq $0x98, %rdi
callq 0xc13d70
movq 0x8(%rsp), %rdi
addq $0x8, %rdi
callq 0xc13dc0
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/Passes/CodeGenPassBuilder.h |
llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::addISelPasses(llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::AddIRPass&) const | void CodeGenPassBuilder<Derived, TargetMachineT>::addISelPasses(
AddIRPass &addPass) const {
derived().addGlobalMergePass(addPass);
if (TM.useEmulatedTLS())
addPass(LowerEmuTLSPass());
addPass(PreISelIntrinsicLoweringPass(TM));
derived().addIRPasses(addPass);
derived().addCodeGenPrepare(addPass);
... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x20400f0
movq %rax, %rdi
movq 0x48(%rsp), %rsi
callq 0x2042700
movq 0x10(%rsp), %rax
movq (%rax), %rdi
callq 0x3aff850
testb $0x1, %al
jne 0x20404bd
jmp 0x20404ef
movq 0x48(%rsp), %rax
movq %rax, 0x8(%rsp)
ca... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::AddIRPass::operator()<llvm::VerifierPass>(llvm::VerifierPass&&, llvm::StringRef) | void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
bool Required = false;
if const... | subq $0x48, %rsp
movq %rdx, 0x38(%rsp)
movq %rcx, 0x40(%rsp)
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x27(%rsp)
callq 0xc327b0
movb %al, %cl
movq 0x8(%rsp), %rax
andb $0x1, %cl
movb %cl, 0x27(%rsp)
movq 0x20(%rax), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::AddIRPass::operator()<llvm::MergeICmpsPass>(llvm::MergeICmpsPass&&, llvm::StringRef) | void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
bool Required = false;
if const... | subq $0x48, %rsp
movq %rdx, 0x38(%rsp)
movq %rcx, 0x40(%rsp)
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x27(%rsp)
movq 0x20(%rax), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x10(%rsp), %rsi
movq 0x18(%rsp), %... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::AddMachinePass::operator()<llvm::RequireAnalysisPass<llvm::LiveIntervalsAnalysis, llvm::MachineFunction, llvm::AnalysisManager<llvm::MachineFunction>>>(llvm::RequireAnalysisPass<llvm::LiveIntervalsAnalysis, llvm::Machin... | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | subq $0x78, %rsp
movb %dl, %al
movq %rcx, 0x68(%rsp)
movq %r8, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
andb $0x1, %al
movb %al, 0x57(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
testb $0x1, 0x57(%rsp)
jne 0x2047476
movq 0x8(%rsp), %rax
movq 0x20(%rax), %rdi
movq 0x68(%rsp), %rax
movq %rax, 0x40(%rsp)... | /llvm/Passes/CodeGenPassBuilder.h |
(anonymous namespace)::X86DomainReassignment::visitRegister((anonymous namespace)::Closure&, llvm::Register, (anonymous namespace)::RegDomain&, llvm::SmallVectorImpl<unsigned int>&) | void X86DomainReassignment::visitRegister(Closure &C, Register Reg,
RegDomain &Domain,
SmallVectorImpl<unsigned> &Worklist) {
if (!Reg.isVirtual())
return;
if (EnclosedEdges.test(Register::virtReg2Index(Reg)))
return;
if... | subq $0x58, %rsp
movl %edx, 0x54(%rsp)
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rcx, 0x38(%rsp)
movq %r8, 0x30(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x18(%rsp)
leaq 0x54(%rsp), %rdi
callq 0x744f60
testb $0x1, %al
jne 0x204db79
jmp 0x204dc55
movq 0x18(%rsp), %rax
addq $0x50, %rax
movq %rax, 0x10(%rsp)
movl 0x5... | /Target/X86/X86DomainReassignment.cpp |
llvm::X86II::getMemoryOperandNo(unsigned long) | inline int getMemoryOperandNo(uint64_t TSFlags) {
bool HasVEX_4V = TSFlags & X86II::VEX_4V;
bool HasEVEX_K = TSFlags & X86II::EVEX_K;
switch (TSFlags & X86II::FormMask) {
default:
llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
case X86II::Pseudo:
case X86II::RawFrm:
case X86II::Ad... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rax
shrq $0x27, %rax
andl $0x1, %eax
movb %al, 0x17(%rsp)
movq 0x18(%rsp), %rax
shrq $0x29, %rax
andl $0x1, %eax
movb %al, 0x16(%rsp)
movq 0x18(%rsp), %rax
andl $0x7f, %eax
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rax
leaq 0x4f3d766(%rip), %rcx # 0x6f8b658
movslq ... | /Target/X86/MCTargetDesc/X86BaseInfo.h |
llvm::DILocation::cloneWithDiscriminator(unsigned int) const | const DILocation *
DILocation::cloneWithDiscriminator(unsigned Discriminator) const {
DIScope *Scope = getScope();
// Skip all parent DILexicalBlockFile that already have a discriminator
// assigned. We do not want to have nested DILexicalBlockFiles that have
// mutliple discriminators because only the leaf DIL... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movl %esi, 0x5c(%rsp)
movq 0x60(%rsp), %rdi
movq %rdi, 0x38(%rsp)
callq 0x14d3da0
movq %rax, 0x50(%rsp)
movq 0x50(%rsp), %rdi
callq 0x20528d0
movq %rax, 0x48(%rsp)
xorl %eax, %eax
cmpq $0x0, 0x48(%rsp)
movb %al, 0x37(%rsp)
je 0x2050b02
movq 0x48(%rsp), %rdi
callq 0x2052740
cmpl $0... | /llvm/IR/DebugInfoMetadata.h |
llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::StringRef, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<llvm::StringRef, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<llvm::StringRef, unsigned int>, unsigned int>>, std::pair<llvm::StringRef, unsigned int>, unsigned int, llvm::DenseMapInfo<st... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0x2050d2e
movl $0x0, 0x14(%rsp)
jmp 0x2050d4e
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::PHINode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::PHINode*, void>, llvm::detail::DenseSetPair<llvm::PHINode*>>, llvm::PHINode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::PHINode*, void>, llvm::detail::DenseSetPair<llvm::PHINode*>>::getMinBucketToReserveF... | unsigned getMinBucketToReserveForEntries(unsigned NumEntries) {
// Ensure that "NumEntries * 4 < NumBuckets * 3"
if (NumEntries == 0)
return 0;
// +1 is required because of the strict equality.
// For example if NumEntries is 48, we need to return 401.
return NextPowerOf2(NumEntries * 4 / 3 + ... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movl %esi, 0x4(%rsp)
cmpl $0x0, 0x4(%rsp)
jne 0x205890e
movl $0x0, 0x14(%rsp)
jmp 0x205892e
movl 0x4(%rsp), %eax
shll $0x2, %eax
movl $0x3, %ecx
xorl %edx, %edx
divl %ecx
addl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseSetPair<llvm::PHINode*>* llvm::DenseMapBase<llvm::DenseMap<llvm::PHINode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::PHINode*, void>, llvm::detail::DenseSetPair<llvm::PHINode*>>, llvm::PHINode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::PHINode*, void>, llvm::detail::DenseSetP... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x2058ce0
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x2058b30
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
bool (anonymous namespace)::X86LowerAMXIntrinsics::lowerTileLoadStore<true>(llvm::Instruction*) | bool X86LowerAMXIntrinsics::lowerTileLoadStore(Instruction *TileLoadStore) {
Value *M, *N, *Ptr, *Stride, *Tile;
if (IsTileLoad)
match(TileLoadStore,
m_Intrinsic<Intrinsic::x86_tileloadd64_internal>(
m_Value(M), m_Value(N), m_Value(Ptr), m_Value(Stride)));
else
match(TileLoadStore,... | subq $0x448, %rsp # imm = 0x448
movq %rdi, 0x440(%rsp)
movq %rsi, 0x438(%rsp)
movq 0x440(%rsp), %rax
movq %rax, 0xb8(%rsp)
movq 0x438(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0x430(%rsp), %rdi
callq 0x7bed40
movq %rax, 0x3c0(%rsp)
leaq 0x428(%rsp), %rdi
callq 0x7bed40
movq %rax, 0x3b8(%rsp)
leaq 0x420(%rsp), %... | /Target/X86/X86LowerAMXIntrinsics.cpp |
(anonymous namespace)::FixupBWInstPass::tryReplaceCopy(llvm::MachineInstr*) const | MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
assert(MI->getNumExplicitOperands() == 2);
auto &OldDest = MI->getOperand(0);
auto &OldSrc = MI->getOperand(1);
Register NewDestReg = getSuperRegDestIfDead(MI);
if (!NewDestReg)
return nullptr;
Register NewSrcReg = getX86SubSuperR... | subq $0x118, %rsp # imm = 0x118
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x100(%rsp), %rdi
xorl %esi, %esi
callq 0x73fa00
movq %rax, 0xf8(%rsp)
movq 0x100(%rsp), %rdi
movl $0x1, %esi
callq 0x73fa00
movq 0x30(%rsp), %rdi
movq %rax, 0xf0(%rsp)
movq 0x100(%... | /Target/X86/X86FixupBWInsts.cpp |
(anonymous namespace)::FixupLEAPass::processInstructionForSlowLEA(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::MachineBasicBlock&) | void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
MachineBasicBlock &MBB) {
MachineInstr &MI = *I;
const unsigned Opcode = MI.getOpcode();
const MachineOperand &Dst = MI.getOperand(0);
const MachineOperand &Base = MI.getOperan... | subq $0x198, %rsp # imm = 0x198
movq %rdi, 0x190(%rsp)
movq %rsi, 0x188(%rsp)
movq %rdx, 0x180(%rsp)
movq 0x190(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x188(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x178(%rsp)
movq 0x178(%rsp), %rdi
callq 0x72bbb0
movl %eax, 0x174(%rsp)
movq 0x178(%rsp), %rdi
xorl %esi, %esi
ca... | /Target/X86/X86FixupLEAs.cpp |
(anonymous namespace)::FixupLEAPass::processInstrForSlow3OpLEA(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::MachineBasicBlock&, bool) | void FixupLEAPass::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
MachineBasicBlock &MBB,
bool OptIncDec) {
MachineInstr &MI = *I;
const unsigned LEAOpcode = MI.getOpcode();
const MachineOperand &Dest = MI.get... | subq $0x4a8, %rsp # imm = 0x4A8
movb %cl, %al
movq %rdi, 0x4a0(%rsp)
movq %rsi, 0x498(%rsp)
movq %rdx, 0x490(%rsp)
andb $0x1, %al
movb %al, 0x48f(%rsp)
movq 0x4a0(%rsp), %rax
movq %rax, 0x130(%rsp)
movq 0x498(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x480(%rsp)
movq 0x480(%rsp), %rdi
callq 0x72bbb0
movl %eax, 0... | /Target/X86/X86FixupLEAs.cpp |
(anonymous namespace)::X86FixupVectorConstantsPass::runOnMachineFunction(llvm::MachineFunction&) | bool X86FixupVectorConstantsPass::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "Start X86FixupVectorConstants\n";);
bool Changed = false;
ST = &MF.getSubtarget<X86Subtarget>();
TII = ST->getInstrInfo();
SM = &ST->getSchedModel();
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr... | subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
jmp 0x208a76a
movb $0x0, 0x57(%rsp)
movq 0x58(%rsp), %rdi
callq 0x1fd1260
movq %rax, %rcx
movq 0x8(%rsp), %rax
movq %rcx, 0x40(%rax)
movq 0x40(%rax), %rdi
callq 0x1fd1320
movq %rax, %rcx
movq 0x8(%rsp), %rax
movq %rc... | /Target/X86/X86FixupVectorConstants.cpp |
rebuildConstant(llvm::LLVMContext&, llvm::Type*, llvm::APInt const&, unsigned int) | static Constant *rebuildConstant(LLVMContext &Ctx, Type *SclTy,
const APInt &Bits, unsigned NumSclBits) {
unsigned BitWidth = Bits.getBitWidth();
if (NumSclBits == 8) {
SmallVector<uint8_t> RawBits;
for (unsigned I = 0; I != BitWidth; I += 8)
RawBits.push_back(Bits.ex... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x228(%rsp)
movq %rsi, 0x220(%rsp)
movq %rdx, 0x218(%rsp)
movl %ecx, 0x214(%rsp)
movq 0x218(%rsp), %rdi
callq 0x79a0c0
movl %eax, 0x210(%rsp)
cmpl $0x8, 0x214(%rsp)
jne 0x208e564
leaq 0x1d0(%rsp), %rdi
callq 0x208f120
movl $0x0, 0x1cc(%rsp)
movl 0x1cc(%rsp), %eax
cm... | /Target/X86/X86FixupVectorConstants.cpp |
getSplatableConstant(llvm::Constant const*, unsigned int) | static std::optional<APInt> getSplatableConstant(const Constant *C,
unsigned SplatBitWidth) {
const Type *Ty = C->getType();
assert((Ty->getPrimitiveSizeInBits() % SplatBitWidth) == 0 &&
"Illegal splat width");
if (std::optional<APInt> Bits = extractConst... | subq $0x178, %rsp # imm = 0x178
movq %rdi, 0x18(%rsp)
movq %rdi, %rax
movq %rax, 0x20(%rsp)
movq %rdi, 0x170(%rsp)
movq %rsi, 0x168(%rsp)
movl %edx, 0x164(%rsp)
movq 0x168(%rsp), %rdi
callq 0x782840
movq %rax, 0x158(%rsp)
movq 0x168(%rsp), %rsi
leaq 0x140(%rsp), %rdi
callq 0x208e930
leaq 0x140(%rsp), %rdi
ca... | /Target/X86/X86FixupVectorConstants.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [25], llvm::cl::desc, llvm::cl::initializer<int>, llvm::cl::OptionHidden>(char const (&) [25], llvm::cl::desc const&, llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, (%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq (%rsp), %rdi
addq $0x80, %rdi
callq 0x76e5e0
movq (%rsp), %rsi
leaq 0x764f0e6(%rip), %rax # 0x96defe... | /llvm/Support/CommandLine.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, long, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, long>>, llvm::MachineBasicBlock*, long, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*,... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x2096d10
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0x2096a30
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0x2096bc2
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rs... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::FPS::handleTwoArgFP(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&) | void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr &MI = *I;
unsigned NumOperands = MI.getDesc().getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP ... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x160(%rsp)
movq %rsi, 0x158(%rsp)
movq 0x160(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x158(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x150(%rsp)
movq 0x150(%rsp), %rdi
callq 0x7349e0
movq %rax, %rdi
callq 0x5beba0
movl %eax, 0x14c(%rsp)
movq 0x150(%rsp), %rdi
xorl %esi,... | /Target/X86/X86FloatingPoint.cpp |
(anonymous namespace)::X86DAGToDAGISel::isProfitableToFormMaskedOp(llvm::SDNode*) const | bool X86DAGToDAGISel::isProfitableToFormMaskedOp(SDNode *N) const {
assert(
(N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SELECTS) &&
"Unexpected opcode!");
// If the operation has additional users, the operation will be duplicated.
// Check the use count to prevent that.
// FIXME: A... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x8(%rsp), %rdi
movl $0x1, %esi
callq 0x981ab0
movq %rax, %rdi
callq 0x98daa0
andb $0x1, %al
addq $0x18, %rsp
retq
nopl (%rax)
| /Target/X86/X86ISelDAGToDAG.cpp |
isFoldableUseOfShuffle(llvm::SDNode*) | static bool isFoldableUseOfShuffle(SDNode *N) {
for (auto *U : N->uses()) {
unsigned Opc = U->getOpcode();
// VPERMV/VPERMV3 shuffles can never fold their index operands.
if (Opc == X86ISD::VPERMV && U->getOperand(0).getNode() == N)
return false;
if (Opc == X86ISD::VPERMV3 && U->getOperand(1).ge... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0x98fe00
movq %rax, 0x20(%rsp)
movq %rdx, 0x28(%rsp)
leaq 0x20(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rdi
callq 0x98fe50
movq %rax, 0x18(%rsp)
movq 0x30(%rsp), %rdi
callq 0x98fe70
movq %rax, 0x10(%rsp)
leaq 0x18(%rsp), %rdi
leaq 0x10(%rsp),... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::shouldExpandAtomicLoadInIR(llvm::LoadInst*) const | TargetLowering::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
Type *MemType = LI->getType();
if (!LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
!Subtarget.useSoftFloat()) {
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled,... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x60(%rsp), %rdi
callq 0x782840
movq %rax, 0x58(%rsp)
movq 0x60(%rsp), %rdi
callq 0x7e0fc0
movq %rax, %rdi
movl $0x1c, %esi
callq 0x304e750
testb $0x1, %al
jne 0x2183ca9
movq 0x10(%rsp), %rax
movq 0x4e0f8(%rax)... | /Target/X86/X86ISelLowering.cpp |
truncateVectorWithPACK(unsigned int, llvm::EVT, llvm::SDValue, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::X86Subtarget const&) | static SDValue truncateVectorWithPACK(unsigned Opcode, EVT DstVT, SDValue In,
const SDLoc &DL, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
assert((Opcode == X86ISD::PACKSS || Opcode == X86ISD::PACKUS) &&
"Unexpected PACK opco... | subq $0xae8, %rsp # imm = 0xAE8
movb %sil, %al
movq 0xaf8(%rsp), %rsi
movq 0xaf0(%rsp), %rsi
movb %al, 0xac8(%rsp)
movq %rdx, 0xad0(%rsp)
movq %rcx, 0xab8(%rsp)
movl %r8d, 0xac0(%rsp)
movl %edi, 0xab4(%rsp)
movq %r9, 0xaa8(%rsp)
movq 0xaf8(%rsp), %rdi
callq 0x1ffff40
testb $0x1, %al
jne 0x21d32df
leaq 0xad8(... | /Target/X86/X86ISelLowering.cpp |
widenSubVector(llvm::SDValue, bool, llvm::X86Subtarget const&, llvm::SelectionDAG&, llvm::SDLoc const&, unsigned int) | static SDValue widenSubVector(SDValue Vec, bool ZeroNewElements,
const X86Subtarget &Subtarget, SelectionDAG &DAG,
const SDLoc &dl, unsigned WideSizeInBits) {
assert(Vec.getValueSizeInBits() <= WideSizeInBits &&
(WideSizeInBits % Vec.getScalarValueS... | subq $0x98, %rsp
movb %dl, %al
movl 0xa0(%rsp), %edx
movq %rdi, 0x78(%rsp)
movl %esi, 0x80(%rsp)
andb $0x1, %al
movb %al, 0x77(%rsp)
movq %rcx, 0x68(%rsp)
movq %r8, 0x60(%rsp)
movq %r9, 0x58(%rsp)
movl 0xa0(%rsp), %eax
movq %rax, 0x18(%rsp)
leaq 0x78(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x98fdc0
movq 0x10(%rsp), %rd... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::emitEHSjLjLongJmp(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
X86TargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
MachineBasicBlock *MBB) const {
const MIMetadata MIMD(MI);
MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &MRI = MF->getRegInfo();
... | subq $0x2b8, %rsp # imm = 0x2B8
movq %rdi, 0x2b0(%rsp)
movq %rsi, 0x2a8(%rsp)
movq %rdx, 0x2a0(%rsp)
movq 0x2b0(%rsp), %rax
movq %rax, 0x70(%rsp)
movq 0x2a8(%rsp), %rsi
leaq 0x288(%rsp), %rdi
callq 0x839c30
movq 0x2a0(%rsp), %rdi
callq 0x73fb50
movq %rax, %rcx
movq 0x70(%rsp), %rax
movq %rcx, 0x280(%rsp)
mov... | /Target/X86/X86ISelLowering.cpp |
getTargetShuffleInputs(llvm::SDValue, llvm::APInt const&, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SmallVectorImpl<int>&, llvm::APInt&, llvm::APInt&, llvm::SelectionDAG const&, unsigned int, bool) | static bool getTargetShuffleInputs(SDValue Op, const APInt &DemandedElts,
SmallVectorImpl<SDValue> &Inputs,
SmallVectorImpl<int> &Mask,
APInt &KnownUndef, APInt &KnownZero,
const S... | subq $0x88, %rsp
movb 0xa8(%rsp), %al
movl 0xa0(%rsp), %r10d
movq 0x98(%rsp), %r10
movq 0x90(%rsp), %r10
movq %rdi, 0x70(%rsp)
movl %esi, 0x78(%rsp)
movq %rdx, 0x68(%rsp)
movq %rcx, 0x60(%rsp)
movq %r8, 0x58(%rsp)
movq %r9, 0x50(%rsp)
andb $0x1, %al
movb %al, 0x4f(%rsp)
cmpl $0x6, 0xa0(%rsp)
jb 0x21f9160
movb $0x0, 0x8... | /Target/X86/X86ISelLowering.cpp |
combineBT(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&) | static SDValue combineBT(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) {
SDValue N1 = N->getOperand(1);
// BT ignores high bits in the bit index operand.
unsigned BitWidth = N1.getValueSizeInBits();
APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWi... | subq $0x88, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movq %rdx, 0x60(%rsp)
movq 0x70(%rsp), %rdi
movl $0x1, %esi
callq 0x981ab0
movups (%rax), %xmm0
movaps %xmm0, 0x50(%rsp)
leaq 0x50(%rsp), %rdi
callq 0x9a2fc0
movb %dl, 0x30(%rsp)
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x38(%rsp)
movb 0x30(%rsp... | /Target/X86/X86ISelLowering.cpp |
bool llvm::PatternMatch::CmpClass_match<llvm::PatternMatch::class_match<llvm::Value>, llvm::PatternMatch::cstval_pred_ty<llvm::PatternMatch::is_all_ones, llvm::ConstantInt, true>, llvm::ICmpInst, llvm::CmpInst::Predicate, false>::match<llvm::Instruction>(llvm::Instruction*) | bool match(OpTy *V) {
if (auto *I = dyn_cast<Class>(V)) {
if (L.match(I->getOperand(0)) && R.match(I->getOperand(1))) {
if (Predicate)
*Predicate = I->getPredicate();
return true;
} else if (Commutable && L.match(I->getOperand(1)) &&
R.match(I->getOperand(0))) ... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x20(%rsp), %rdi
callq 0x11292d0
movq %rax, 0x18(%rsp)
cmpq $0x0, 0x18(%rsp)
je 0x22695ba
movq 0x10(%rsp), %rax
addq $0x8, %rax
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %rdi
xorl %esi, %esi
callq 0x7d7fb0
movq 0x8... | /llvm/IR/PatternMatch.h |
scaleShuffleElements(llvm::ArrayRef<int>, unsigned int, llvm::SmallVectorImpl<int>&) | static bool scaleShuffleElements(ArrayRef<int> Mask, unsigned NumDstElts,
SmallVectorImpl<int> &ScaledMask) {
unsigned NumSrcElts = Mask.size();
assert(((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts) == 0) &&
"Illegal shuffle scale factor");
// Narrowing is ... | subq $0xb8, %rsp
movq %rdi, 0xa0(%rsp)
movq %rsi, 0xa8(%rsp)
movl %edx, 0x9c(%rsp)
movq %rcx, 0x90(%rsp)
leaq 0xa0(%rsp), %rdi
callq 0x78ac80
movl %eax, 0x8c(%rsp)
movl 0x9c(%rsp), %eax
cmpl 0x8c(%rsp), %eax
jb 0x22789bc
movl 0x9c(%rsp), %eax
xorl %edx, %edx
divl 0x8c(%rsp)
movl %eax, 0x88(%rsp)
movl 0x88(%rsp), %edi
m... | /Target/X86/X86ISelLowering.cpp |
getV4X86ShuffleImm(llvm::ArrayRef<int>) | static unsigned getV4X86ShuffleImm(ArrayRef<int> Mask) {
assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask ... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x38(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x2279ad0
movq %rax, 0x10(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x78b010
movq %rax, %rcx
movq 0x10(%rsp), %rax
subq %rcx, %rax
sarq $0x2, %rax
movl %eax, 0x2c(%rsp)
movslq 0x2c(%rsp), %rsi
leaq 0x30(%rsp), %rdi
callq 0x7b5b10
movl (%ra... | /Target/X86/X86ISelLowering.cpp |
lowerShuffleAsDecomposedShuffleMerge(llvm::SDLoc const&, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, llvm::X86Subtarget const&, llvm::SelectionDAG&) | static SDValue lowerShuffleAsDecomposedShuffleMerge(
const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
const X86Subtarget &Subtarget, SelectionDAG &DAG) {
int NumElts = Mask.size();
int NumLanes = VT.getSizeInBits() / 128;
int NumEltsPerLane = NumElts / NumLanes;
// Shuffle the input... | subq $0x6a8, %rsp # imm = 0x6A8
movq %rdi, %rax
movq 0x6c8(%rsp), %rdi
movq 0x6c0(%rsp), %rdi
leaq 0x6b0(%rsp), %rdi
movq %rdi, 0x98(%rsp)
movb %sil, 0x697(%rsp)
movq %rdx, 0x680(%rsp)
movl %ecx, 0x688(%rsp)
movq %r8, 0x670(%rsp)
movl %r9d, 0x678(%rsp)
movq %rax, 0x668(%rsp)
callq 0x78ac80
movl %eax, 0x664(%... | /Target/X86/X86ISelLowering.cpp |
matchPMADDWD(llvm::SelectionDAG&, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::EVT, llvm::X86Subtarget const&) | static SDValue matchPMADDWD(SelectionDAG &DAG, SDValue Op0, SDValue Op1,
const SDLoc &DL, EVT VT,
const X86Subtarget &Subtarget) {
// Example of pattern we try to detect:
// t := (v8i32 mul (sext (v8i16 x0), (sext (v8i16 x1))))
//(add (build_vector (extract_... | subq $0x298, %rsp # imm = 0x298
movq 0x2b0(%rsp), %rax
leaq 0x2a0(%rsp), %rax
movq %rax, 0x70(%rsp)
movq %rsi, 0x278(%rsp)
movl %edx, 0x280(%rsp)
movq %rcx, 0x268(%rsp)
movl %r8d, 0x270(%rsp)
movq %rdi, 0x260(%rsp)
movq %r9, 0x258(%rsp)
movq 0x2b0(%rsp), %rdi
callq 0x1ffff40
testb $0x1, %al
jne 0x23296e2
lea... | /Target/X86/X86ISelLowering.cpp |
promoteExtBeforeAdd(llvm::SDNode*, llvm::SelectionDAG&, llvm::X86Subtarget const&) | static SDValue promoteExtBeforeAdd(SDNode *Ext, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
if (Ext->getOpcode() != ISD::SIGN_EXTEND &&
Ext->getOpcode() != ISD::ZERO_EXTEND)
return SDValue();
// TODO: This should be valid for other integer types.
EVT VT = Ext-... | subq $0x298, %rsp # imm = 0x298
movq %rdi, 0x280(%rsp)
movq %rsi, 0x278(%rsp)
movq %rdx, 0x270(%rsp)
movq 0x280(%rsp), %rdi
callq 0x97c400
cmpl $0xd4, %eax
je 0x234f49d
movq 0x280(%rsp), %rdi
callq 0x97c400
cmpl $0xd5, %eax
je 0x234f49d
leaq 0x288(%rsp), %rdi
xorl %esi, %esi
movl $0x10, %edx
callq 0x348990
l... | /Target/X86/X86ISelLowering.cpp |
combineRedundantDWordShuffle(llvm::SDValue, llvm::MutableArrayRef<int>, llvm::SDLoc const&, llvm::SelectionDAG&) | static SDValue combineRedundantDWordShuffle(SDValue N,
MutableArrayRef<int> Mask,
const SDLoc &DL,
SelectionDAG &DAG) {
assert(N.getOpcode() == X86ISD::PSHUFD &&
"Called with so... | subq $0x428, %rsp # imm = 0x428
movq %rdi, 0x408(%rsp)
movl %esi, 0x410(%rsp)
movq %rdx, 0x3f8(%rsp)
movq %rcx, 0x400(%rsp)
movq %r8, 0x3f0(%rsp)
movq %r9, 0x3e8(%rsp)
leaq 0x358(%rsp), %rdi
callq 0x9e3f00
leaq 0x408(%rsp), %rdi
xorl %esi, %esi
callq 0x98cd00
movq (%rax), %rcx
movq %rcx, 0x348(%rsp)
movq 0x8... | /Target/X86/X86ISelLowering.cpp |
EmitTailCallStoreRetAddr(llvm::SelectionDAG&, llvm::MachineFunction&, llvm::SDValue, llvm::SDValue, llvm::EVT, unsigned int, int, llvm::SDLoc const&) | static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
SDValue Chain, SDValue RetAddrFrIdx,
EVT PtrVT, unsigned SlotSize,
int FPDiff, const SDLoc &dl) {
// Store the return ... | pushq %rbx
subq $0x180, %rsp # imm = 0x180
movq 0x1b0(%rsp), %rax
movl 0x1a8(%rsp), %eax
movl 0x1a0(%rsp), %eax
leaq 0x190(%rsp), %rax
movq %rax, 0x68(%rsp)
movq %rdx, 0x160(%rsp)
movl %ecx, 0x168(%rsp)
movq %r8, 0x150(%rsp)
movl %r9d, 0x158(%rsp)
movq %rdi, 0x148(%rsp)
movq %rsi, 0x140(%rsp)
cmpl $0x0, 0x1a... | /Target/X86/X86ISelLoweringCall.cpp |
getNegativeIsTrueBoolVec(llvm::Constant*, llvm::DataLayout const&) | static Constant *getNegativeIsTrueBoolVec(Constant *V, const DataLayout &DL) {
VectorType *IntTy = VectorType::getInteger(cast<VectorType>(V->getType()));
V = ConstantExpr::getBitCast(V, IntTy);
V = ConstantFoldCompareInstOperands(CmpInst::ICMP_SGT,
Constant::getNullValue(Int... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
callq 0x782840
movq %rax, %rdi
callq 0x784140
movq %rax, %rdi
callq 0xa4afe0
movq %rax, (%rsp)
movq 0x10(%rsp), %rdi
movq (%rsp), %rsi
xorl %edx, %edx
callq 0x2f5ba60
movq %rax, 0x10(%rsp)
movq (%rsp), %rdi
callq 0x2f5be30
movq %rax, %rsi... | /Target/X86/X86InstCombineIntrinsic.cpp |
llvm::X86::getCondSrcNoFromDesc(llvm::MCInstrDesc const&) | int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
unsigned Opcode = MCID.getOpcode();
if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode) ||
X86::isCFCMOVCC(Opcode) || X86::isCCMPCC(Opcode) ||
X86::isCTESTCC(Opcode)))
return -1;
// Assume that condition code is alw... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rdi
callq 0x7f0ea0
movl %eax, 0x14(%rsp)
movl 0x14(%rsp), %edi
callq 0x291c4a0
testb $0x1, %al
jne 0x23bd54f
movl 0x14(%rsp), %edi
callq 0x291cd50
testb $0x1, %al
jne 0x23bd54f
movl 0x14(%rsp), %edi
callq 0x291c3a0
testb $0x1, %al
jne 0x23bd54f
movl 0x14(%rsp), %... | /Target/X86/X86InstrInfo.cpp |
llvm::X86::getConstantFromPool(llvm::MachineInstr const&, unsigned int) | const Constant *X86::getConstantFromPool(const MachineInstr &MI,
unsigned OpNo) {
assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) &&
"Unexpected number of operands!");
const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg);
if (!Index.i... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movl %esi, 0x44(%rsp)
movq 0x48(%rsp), %rdi
movl 0x44(%rsp), %esi
addl $0x2, %esi
callq 0x72c4d0
movq %rax, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0x737b30
movb %al, %cl
movb $0x1, %al
testb $0x1, %cl
movb %al, 0xf(%rsp)
jne 0x23bde9c
jmp 0x23bdeba
movq 0x38(%rsp), %rdi
callq 0x72... | /Target/X86/X86InstrInfo.cpp |
llvm::X86InstrInfo::analyzeBranchPredicate(llvm::MachineBasicBlock&, llvm::TargetInstrInfo::MachineBranchPredicate&, bool) const | bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
MachineBranchPredicate &MBP,
bool AllowModify) const {
using namespace std::placeholders;
SmallVector<MachineOperand, 4> Cond;
SmallVector<MachineInstr *, 4> CondB... | subq $0x1e8, %rsp # imm = 0x1E8
movb %cl, %al
movq %rdi, 0x1d8(%rsp)
movq %rsi, 0x1d0(%rsp)
movq %rdx, 0x1c8(%rsp)
andb $0x1, %al
movb %al, 0x1c7(%rsp)
movq 0x1d8(%rsp), %rax
movq %rax, 0x30(%rsp)
leaq 0x130(%rsp), %rdi
callq 0x8fa8a0
leaq 0x100(%rsp), %rdi
callq 0x91be70
movq 0x30(%rsp), %rdi
movq 0x1d0(%rs... | /Target/X86/X86InstrInfo.cpp |
llvm::X86InstrInfo::shouldScheduleLoadsNear(llvm::SDNode*, llvm::SDNode*, long, long, unsigned int) const | bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const {
assert(Offset2 > Offset1);
if ((Offset2 - Offset1) / 8 > 64)
return false;
unsigned Opc1 ... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq %rcx, 0x40(%rsp)
movq %r8, 0x38(%rsp)
movl %r9d, 0x34(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x38(%rsp), %rax
subq 0x40(%rsp), %rax
movl $0x8, %ecx
cqto
idivq %rcx
cmpq $0x40, %rax
jle 0x23d3c40
movb $0x0, 0x67(%rsp)
... | /Target/X86/X86InstrInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<unsigned int, std::allocator<unsigned int>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<unsigned int, std::allocator<unsigned int>>>>, unsigned int, std::vector<unsigned int, std::allocator<unsigned int>>, llvm... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x23e1fe0
callq 0x23e20a0
movl %eax, 0x3c(%rsp)
callq 0x23e3970
movl %eax, 0x38(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x30(%rs... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, int, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, int>>, llvm::MachineInstr*, int, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, int>>::makeIterator(llvm::detail::Den... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xc8f360
testb $0x1, %al
jne 0x23e6316
jmp 0x23e6382
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%r... | /llvm/ADT/DenseMap.h |
auto llvm::callable_detail::Callable<llvm::ImmutableGraph<llvm::MachineInstr*, int>::Node const* (*)(llvm::ImmutableGraph<llvm::MachineInstr*, int>::Edge const&), true>::convertIn<llvm::ImmutableGraph<llvm::MachineInstr*, int>::Node const* (*&)(llvm::ImmutableGraph<llvm::MachineInstr*, int>::Edge const&)>(llvm::Immutab... | static constexpr auto convertIn(In &&I) {
if constexpr (IsPtr) {
// Pointer... just echo it back.
return I;
} else {
// Must be a function reference. Return its address.
return &I;
}
} | movq %rdi, -0x8(%rsp)
movq -0x8(%rsp), %rax
movq (%rax), %rax
retq
nop
| /llvm/ADT/STLExtras.h |
(anonymous namespace)::X86LoadValueInjectionLoadHardeningPass::insertFences(llvm::MachineFunction&, (anonymous namespace)::MachineGadgetGraph&, llvm::ImmutableGraph<llvm::MachineInstr*, int>::EdgeSet&) const | int X86LoadValueInjectionLoadHardeningPass::insertFences(
MachineFunction &MF, MachineGadgetGraph &G,
EdgeSet &CutEdges /* in, out */) const {
int FencesInserted = 0;
for (const Node &N : G.nodes()) {
for (const Edge &E : N.edges()) {
if (CutEdges.contains(E)) {
MachineInstr *MI = N.getVal... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x160(%rsp)
movq %rsi, 0x158(%rsp)
movq %rdx, 0x150(%rsp)
movq %rcx, 0x148(%rsp)
movq 0x160(%rsp), %rax
movq %rax, 0x28(%rsp)
movl $0x0, 0x144(%rsp)
movq 0x150(%rsp), %rdi
callq 0x23ea760
movq %rax, 0x128(%rsp)
movq %rdx, 0x130(%rsp)
leaq 0x128(%rsp), %rax
movq %rax... | /Target/X86/X86LoadValueInjectionLoadHardening.cpp |
llvm::DenseMap<(anonymous namespace)::MemOpKey, llvm::SmallVector<llvm::MachineInstr*, 16u>, llvm::DenseMapInfo<(anonymous namespace)::MemOpKey, void>, llvm::detail::DenseMapPair<(anonymous namespace)::MemOpKey, llvm::SmallVector<llvm::MachineInstr*, 16u>>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0x23f31b0
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0x23f3200
testb $0x1, %al
jne 0x23f3186
jmp 0x23f3191
movq (%rsp), %rdi
callq 0x23f3270
jmp 0x23f31a3
movq (%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<(anonymous namespace)::MemOpKey, llvm::SmallVector<llvm::MachineInstr*, 16u>, llvm::DenseMapInfo<(anonymous namespace)::MemOpKey, void>, llvm::detail::DenseMapPair<(anonymous namespace)::MemOpKey, llvm::SmallVector<llvm::MachineInstr*, 16u>>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0x23f3237
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0x23f3260
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
imulq $0xb8, %rax,... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::X86PartialReduction::trySADReplacement(llvm::Instruction*) | bool X86PartialReduction::trySADReplacement(Instruction *Op) {
if (!ST->hasSSE2())
return false;
// TODO: There's nothing special about i32, any integer type above i16 should
// work just as well.
if (!cast<VectorType>(Op->getType())->getElementType()->isIntegerTy(32))
return false;
Value *LHS;
if... | subq $0x868, %rsp # imm = 0x868
movq %rdi, 0x858(%rsp)
movq %rsi, 0x850(%rsp)
movq 0x858(%rsp), %rax
movq %rax, 0xf8(%rsp)
movq 0x28(%rax), %rdi
callq 0x1ffff40
testb $0x1, %al
jne 0x23fa221
movb $0x0, 0x867(%rsp)
jmp 0x23faffe
movq 0x850(%rsp), %rdi
callq 0x782840
movq %rax, %rdi
callq 0x784140
movq %rax, %... | /Target/X86/X86PartialReduction.cpp |
(anonymous namespace)::X86OutgoingValueHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
auto SPReg =
MIRBuilder.... | subq $0x158, %rsp # imm = 0x158
movq %r8, 0x144(%rsp)
movq %r9, 0x14c(%rsp)
movq %rdi, 0x138(%rsp)
movq %rsi, 0x130(%rsp)
movq %rdx, 0x128(%rsp)
movq %rcx, 0x120(%rsp)
movq 0x138(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x28(%rax), %rdi
xorl %esi, %esi
callq 0x783fb0
movl %eax, %esi
xorl %edi, %edi
callq 0x7f6... | /Target/X86/GISel/X86CallLowering.cpp |
(anonymous namespace)::X86IncomingValueHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
auto &MFI = MIRBuilder.getMF().getFrameInfo();
// Byval is assumed to be writable memory, but other stack passed arguments
// are not.
... | subq $0x98, %rsp
movq %r8, 0x84(%rsp)
movq %r9, 0x8c(%rsp)
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq %rdx, 0x68(%rsp)
movq %rcx, 0x60(%rsp)
movq 0x78(%rsp), %rax
movq %rax, (%rsp)
movq 0x8(%rax), %rdi
callq 0x7f4fa0
movq %rax, %rdi
callq 0x73fb60
movq %rax, 0x58(%rsp)
leaq 0x84(%rsp), %rdi
callq 0x8001f0
xorb $-... | /Target/X86/GISel/X86CallLowering.cpp |
(anonymous namespace)::X86InstructionSelector::selectAnyext(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineFunction&) const | bool X86InstructionSelector::selectAnyext(MachineInstr &I,
MachineRegisterInfo &MRI,
MachineFunction &MF) const {
assert((I.getOpcode() == TargetOpcode::G_ANYEXT) && "unexpected instruction");
const Register DstReg = I.getOperand(0... | subq $0x128, %rsp # imm = 0x128
movq %rdi, 0x118(%rsp)
movq %rsi, 0x110(%rsp)
movq %rdx, 0x108(%rsp)
movq %rcx, 0x100(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x110(%rsp), %rdi
xorl %esi, %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x72c500
movl %eax, 0xfc(%rsp)
movq 0x110(%rsp), %rdi
movl $0x1,... | /Target/X86/GISel/X86InstructionSelector.cpp |
llvm::DenseMapIterator<llvm::Value const*, llvm::Register, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Register>, false>::AdvancePastEmptyBuckets() | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xb56d40
movq %rax, 0x18(%rsp)
callq 0xb57030
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x2471a98
movq 0x8(%rsp), %rax
movq (%rax), %rdi
callq 0x1ba4010
... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::X86FastISel::X86SelectIntToFP(llvm::Instruction const*, bool) | bool X86FastISel::X86SelectIntToFP(const Instruction *I, bool IsSigned) {
// The target-independent selection algorithm in FastISel already knows how
// to select a SINT_TO_FP if the target is SSE but not AVX.
// Early exit if the subtarget doesn't have AVX.
// Unsigned conversion requires avx512.
bool HasAVX... | subq $0x118, %rsp # imm = 0x118
movb %dl, %al
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
andb $0x1, %al
movb %al, 0xff(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0xb0(%rax), %rdi
callq 0x1fe2740
movb %al, %cl
movq 0x50(%rsp), %rax
andb $0x1, %cl
movb %cl, 0xfe(%rsp)
movq 0xb0(%rax), %rdi
call... | /Target/X86/X86FastISel.cpp |
verifyTables() | static void verifyTables() {
#ifndef NDEBUG
static std::atomic<bool> TableChecked(false);
if (!TableChecked.load(std::memory_order_relaxed)) {
assert(llvm::is_sorted(Groups) && llvm::is_sorted(RoundGroups) &&
llvm::is_sorted(BroadcastGroups) && "FMA3 tables not sorted!");
TableChecked.store(true,... | retq
nopw %cs:(%rax,%rax)
nopl (%rax,%rax)
| /Target/X86/X86InstrFMA3Info.cpp |
getOptimalRepmovsType(llvm::X86Subtarget const&, llvm::Align) | static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
Align Alignment) {
uint64_t Align = Alignment.value();
assert((Align != 0) && "Align is normalized");
assert(isPowerOf2_64(Align) && "Align is a power of 2");
switch (Align) {
case 1:
return MVT::i8;
case 2:... | subq $0x28, %rsp
movb %sil, %al
movb %al, 0x26(%rsp)
movq %rdi, 0x18(%rsp)
leaq 0x26(%rsp), %rdi
callq 0x647330
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, 0x8(%rsp)
subq $0x1, %rax
je 0x24dd9fb
jmp 0x24dd9e1
movq 0x8(%rsp), %rax
subq $0x2, %rax
je 0x24dda0c
jmp 0x24dd9ee
movq 0x8(%rsp), %rax
subq $0x4, %rax... | /Target/X86/X86SelectionDAGInfo.cpp |
(anonymous namespace)::XCoreAsmPrinter::emitGlobalVariable(llvm::GlobalVariable const*) | void XCoreAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
// Check to see if this is a special global used by LLVM, if so, emit it.
if (!GV->hasInitializer() || emitSpecialLLVMGlobal(GV))
return;
const DataLayout &DL = getDataLayout();
OutStreamer->switchSection(getObjFileLowering().SectionForGl... | subq $0xd8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0xc8(%rsp), %rdi
callq 0xbd7620
testb $0x1, %al
jne 0x24ddcb7
jmp 0x24ddccf
movq 0x50(%rsp), %rdi
movq 0xc8(%rsp), %rsi
callq 0x3c64920
testb $0x1, %al
jne 0x24ddccf
jmp 0x24ddcd4
jmp 0x24de109
movq 0x50(%rsp),... | /Target/XCore/XCoreAsmPrinter.cpp |
(anonymous namespace)::XCoreAsmPrinter::PrintAsmOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
const char *ExtraCode, raw_ostream &O) {
// Print the operand if there is no operand modifier.
if (!ExtraCode || !ExtraCode[0]) {
printOperand(MI, OpNo, O);
return false;
}
// Otherwise fa... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movl %edx, 0x1c(%rsp)
movq %rcx, 0x10(%rsp)
movq %r8, 0x8(%rsp)
movq 0x28(%rsp), %rax
movq %rax, (%rsp)
cmpq $0x0, 0x10(%rsp)
je 0x24de6c7
movq 0x10(%rsp), %rax
cmpb $0x0, (%rax)
jne 0x24de6e5
movq (%rsp), %rdi
movq 0x20(%rsp), %rsi
movl 0x1c(%rsp), %edx
movq... | /Target/XCore/XCoreAsmPrinter.cpp |
llvm::BasicTTIImplBase<llvm::XCoreTTIImpl>::isLegalAddressingMode(llvm::Type*, llvm::GlobalValue*, long, bool, long, unsigned int, llvm::Instruction*, long) | bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
Instruction *I = nullptr,
int64_t ScalableOffset = 0) {
TargetLoweringBase::AddrMode AM;
AM.Bas... | subq $0x68, %rsp
movb %r8b, %al
movq 0x80(%rsp), %r8
movq 0x78(%rsp), %r8
movl 0x70(%rsp), %r8d
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdx, 0x50(%rsp)
movq %rcx, 0x48(%rsp)
andb $0x1, %al
movb %al, 0x47(%rsp)
movq %r9, 0x38(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x10(%rsp), %rdi
callq 0x784b00... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::XCoreTTIImpl>::preferToKeepConstantsAttached(llvm::Instruction const&, llvm::Function const&) const | bool preferToKeepConstantsAttached(const Instruction &Inst,
const Function &Fn) const {
switch (Inst.getOpcode()) {
default:
break;
case Instruction::SDiv:
case Instruction::SRem:
case Instruction::UDiv:
case Instruction::URem: {
if (!isa<Constant... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x60(%rsp), %rdi
callq 0x785480
movl %eax, %ecx
movl %ecx, %eax
addl $-0x13, %eax
movl %ecx, 0x24(%rsp)
subl $0x2, %eax
jb 0x24f4dcc
jmp 0x24f4db9
movl 0x24(%rsp), %eax
addl $-0x16, %eax
s... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::XCoreTargetObjectFile::Initialize(llvm::MCContext&, llvm::TargetMachine const&) | void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
BSSSection = Ctx.getELFSection(".dp.bss", ELF::SHT_NOBITS,
ELF::SHF_ALLOC | ELF::SHF_WRITE |
ELF::XCORE_SHF_DP_SEC... | subq $0x268, %rsp # imm = 0x268
movq %rdi, 0x260(%rsp)
movq %rsi, 0x258(%rsp)
movq %rdx, 0x250(%rsp)
movq 0x260(%rsp), %rdi
movq %rdi, 0x68(%rsp)
movq 0x258(%rsp), %rsi
movq 0x250(%rsp), %rdx
callq 0x36f6970
movq 0x258(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x228(%rsp), %rdi
leaq 0x4b7d8a6(%rip), %rsi # 0x7... | /Target/XCore/XCoreTargetObjectFile.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [18], llvm::cl::NumOccurrencesFlag, llvm::cl::desc, llvm::cl::OptionHidden, llvm::cl::value_desc, llvm::cl::initializer<int>>(char const (&) [18], llvm::cl::NumOccurrencesFlag const&, llvm::cl::desc const&, llvm::cl::OptionHidden const&, llvm:... | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x48, %rsp
movq 0x50(%rsp), %rax
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq %r9, 0x18(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x76e5e0
movq 0x8... | /llvm/Support/CommandLine.h |
void llvm::sort<llvm::WeakTrackingVH*>(llvm::WeakTrackingVH*, llvm::WeakTrackingVH*) | inline void sort(IteratorTy Start, IteratorTy End) {
if constexpr (detail::sort_trivially_copyable<IteratorTy>::value) {
// Forward trivially copyable types to array_pod_sort. This avoids a large
// amount of code bloat for a minor performance hit.
array_pod_sort(Start, End);
} else {
#ifdef EXPENSIVE_C... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq 0x8(%rsp), %rsi
callq 0x24fe170
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/ADT/STLExtras.h |
llvm::XCoreTargetLowering::LowerVASTART(llvm::SDValue, llvm::SelectionDAG&) const | SDValue XCoreTargetLowering::
LowerVASTART(SDValue Op, SelectionDAG &DAG) const
{
SDLoc dl(Op);
// vastart stores the address of the VarArgsFrameIndex slot into the
// memory location argument
MachineFunction &MF = DAG.getMachineFunction();
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
SDValue A... | pushq %rbx
subq $0x190, %rsp # imm = 0x190
movq %rsi, 0x170(%rsp)
movl %edx, 0x178(%rsp)
movq %rdi, 0x168(%rsp)
movq %rcx, 0x160(%rsp)
movups 0x170(%rsp), %xmm0
movaps %xmm0, 0x140(%rsp)
movq 0x140(%rsp), %rsi
movl 0x148(%rsp), %edx
leaq 0x150(%rsp), %rdi
movq %rdi, 0x78(%rsp)
callq 0x98cf60
movq 0x160(%rsp)... | /Target/XCore/XCoreISelLowering.cpp |
llvm::XCoreTargetLowering::LowerUMUL_LOHI(llvm::SDValue, llvm::SelectionDAG&) const | SDValue XCoreTargetLowering::
LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
{
assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
"Unexpected operand to lower!");
SDLoc dl(Op);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant... | subq $0x208, %rsp # imm = 0x208
movq %rsi, 0x1e8(%rsp)
movl %edx, 0x1f0(%rsp)
movq %rdi, 0x1e0(%rsp)
movq %rcx, 0x1d8(%rsp)
movups 0x1e8(%rsp), %xmm0
movaps %xmm0, 0x1b0(%rsp)
movq 0x1b0(%rsp), %rsi
movl 0x1b8(%rsp), %edx
leaq 0x1c8(%rsp), %rdi
movq %rdi, 0x78(%rsp)
callq 0x98cf60
leaq 0x1e8(%rsp), %rdi
movq... | /Target/XCore/XCoreISelLowering.cpp |
llvm::XCoreTargetLowering::LowerCCCCallTo(llvm::SDValue, llvm::SDValue, unsigned int, bool, bool, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, llvm::SmallVectorImpl<llvm::SDValue> const&, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDVal... | SDValue XCoreTargetLowering::LowerCCCCallTo(
SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
SelectionDAG &DAG, S... | subq $0xec8, %rsp # imm = 0xEC8
movq %rcx, 0x140(%rsp)
movl %edx, %eax
movq 0x140(%rsp), %rdx
movl %eax, 0x14c(%rsp)
movq %rsi, %r10
movl 0x14c(%rsp), %esi
movq 0xf08(%rsp), %rax
movq 0xf00(%rsp), %rax
movq 0xef8(%rsp), %rax
movq 0xef0(%rsp), %rax
movq 0xee8(%rsp), %rax
movq 0xee0(%rsp), %rax
movb 0xed8(%rsp... | /Target/XCore/XCoreISelLowering.cpp |
void llvm::AArch64InstPrinter::printSVERegOp<(char)100>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
switch (suffix) {
case 0:
case 'b':
case 'h':
case 's':
case 'd':
case 'q':
break;
default: llvm_unreac... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movl %edx, 0x34(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x38(%rsp), %rdi
movl 0x34(%rsp), %esi
callq 0x47b650
movq %rax, %rdi
callq 0x47b300
movl %eax, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x10(%... | /Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp |
void llvm::AArch64InstPrinter::printSVERegOp<(char)104>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
switch (suffix) {
case 0:
case 'b':
case 'h':
case 's':
case 'd':
case 'q':
break;
default: llvm_unreac... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movl %edx, 0x34(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x38(%rsp), %rdi
movl 0x34(%rsp), %esi
callq 0x47b650
movq %rax, %rdi
callq 0x47b300
movl %eax, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x10(%... | /Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp |
void llvm::AArch64InstPrinter::printZPRasFPR<16>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Base;
switch (Width) {
case 8: Base = AArch64::B0; break;
case 16: Base = AArch64::H0; break;
case 32... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movl %edx, 0x34(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq 0x40(%rsp), %rax
movq %rax, (%rsp)
movl $0x4d, 0x1c(%rsp)
movq 0x38(%rsp), %rdi
movl 0x34(%rsp), %esi
callq 0x47b650
movq %rax, %rdi
callq 0x47b300
movl %eax, 0x18(%rsp)
movq 0x20(%rsp), %r... | /Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp |
llvm::AArch64InstPrinter::printAlignedLabel(llvm::MCInst const*, unsigned long, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum);
... | subq $0xd8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq %rdx, 0xc0(%rsp)
movl %ecx, 0xbc(%rsp)
movq %r8, 0xb0(%rsp)
movq %r9, 0xa8(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0xc8(%rsp), %rdi
movl 0xbc(%rsp), %esi
callq 0x47b650
movq %rax, 0xa0(%rsp)
movq 0xa0(%rsp), %rdi
callq 0x47b5d0
testb $0x1, ... | /Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp |
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