name string | code string | asm string | file string |
|---|---|---|---|
bool (anonymous namespace)::AVRExpandPseudo::expand<301u>(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
unsigned Imm = MI.getOperand(2).getImm();
switch (Imm) {
case 6:
return expandASRB6Rd(MBB, MBBI);
case 7:
return expandASRB7Rd(MBB, MBBI);
default:
llvm_unreachable("unimplemented asrbn");
return... | subq $0x48, %rsp
movq %rdx, 0x38(%rsp)
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, (%rsp)
leaq 0x38(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movl $0x2, %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x72c4f0
movl %eax, 0x1c(%rsp)
movl 0x1c(%rsp), %eax
subl $0x6,... | /Target/AVR/AVRExpandPseudoInsts.cpp |
(anonymous namespace)::AVRExpandPseudo::expandLSLW12Rd(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
bool DstIsKill = MI.getOperand(1).isKill();
bool ImpIsDead = MI.getOperand(3).isDead();
TRI->spli... | subq $0x108, %rsp # imm = 0x108
movq %rdx, 0x100(%rsp)
movq %rdi, 0xf8(%rsp)
movq %rsi, 0xf0(%rsp)
movq 0xf8(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x100(%rsp), %rdi
callq 0x7410f0
movq %rax, 0xe8(%rsp)
leaq 0xe4(%rsp), %rdi
xorl %esi, %esi
callq 0x72e210
leaq 0xe0(%rsp), %rdi
xorl %esi, %esi
callq 0x72e210
... | /Target/AVR/AVRExpandPseudoInsts.cpp |
llvm::AVRInstrInfo::getOppositeCondition(llvm::AVRCC::CondCodes) const | AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
switch (CC) {
default:
llvm_unreachable("Invalid condition!");
case AVRCC::COND_EQ:
return AVRCC::COND_NE;
case AVRCC::COND_NE:
return AVRCC::COND_EQ;
case AVRCC::COND_SH:
return AVRCC::COND_LO;
case AVRCC::COND... | movq %rdi, -0x10(%rsp)
movl %esi, -0x14(%rsp)
movl -0x14(%rsp), %eax
movq %rax, -0x20(%rsp)
movq -0x20(%rsp), %rax
leaq 0x54d270a(%rip), %rcx # 0x694f3a8
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x1, -0x4(%rsp)
jmp 0x147ccf5
movl $0x0, -0x4(%rsp)
jmp 0x147ccf5
movl $0x5, -0x4(%rsp)
jmp 0x147ccf5
mo... | /Target/AVR/AVRInstrInfo.cpp |
(anonymous namespace)::AVRDAGToDAGISel::selectIndexedProgMemLoad(llvm::LoadSDNode const*, llvm::MVT, int) | unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT,
int Bank) {
// Progmem indexed loads only work in POSTINC mode.
if (LD->getExtensionType() != ISD::NON_EXTLOAD ||
LD->getAddressingMode() != ISD::POST_INC)
return 0;
// Fe... | subq $0x28, %rsp
movb %dl, %al
movb %al, 0x23(%rsp)
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movl %ecx, 0xc(%rsp)
movq 0x10(%rsp), %rdi
callq 0x98b790
cmpl $0x0, %eax
jne 0x1482316
movq 0x10(%rsp), %rdi
callq 0x98b770
cmpl $0x3, %eax
je 0x1482320
movl $0x0, 0x24(%rsp)
jmp 0x148236e
movl $0x0, 0x8(%rsp)
movq 0x10(%rs... | /Target/AVR/AVRISelDAGToDAG.cpp |
llvm::AVRRegisterInfo::getLargestLegalSuperClass(llvm::TargetRegisterClass const*, llvm::MachineFunction const&) const | const TargetRegisterClass *
AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
return &AVR::DRE... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0x73c170
movq %rax, %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0x2f(%rsp), %rdi
movl $0x6, %esi
... | /Target/AVR/AVRRegisterInfo.cpp |
llvm::AVRTargetLowering::AVRTargetLowering(llvm::AVRTargetMachine const&, llvm::AVRSubtarget const&) | AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
: TargetLowering(TM), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
// Compute de... | subq $0x2a8, %rsp # imm = 0x2A8
movq %rdi, 0x2a0(%rsp)
movq %rsi, 0x298(%rsp)
movq %rdx, 0x290(%rsp)
movq 0x2a0(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x298(%rsp), %rsi
callq 0x4056c30
movq 0x10(%rsp), %rax
leaq 0x816aecb(%rip), %rcx # 0x95f16f0
addq $0x10, %rcx
movq %rcx, (%rax)
movq 0x290(%rsp), %rcx
mov... | /Target/AVR/AVRISelLowering.cpp |
(anonymous namespace)::BPFPassConfig::addMachineSSAOptimization() | void BPFPassConfig::addMachineSSAOptimization() {
addPass(createBPFMISimplifyPatchablePass());
// The default implementation must be called first as we want eBPF
// Peephole ran at last.
TargetPassConfig::addMachineSSAOptimization();
const BPFSubtarget *Subtarget = getBPFTargetMachine().getSubtargetImpl();
... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
callq 0x14c1b40
movq (%rsp), %rdi
movq %rax, %rsi
callq 0x3709160
movq (%rsp), %rdi
callq 0x370af40
movq (%rsp), %rdi
callq 0x14a12e0
movq %rax, %rdi
callq 0x14a1300
movq %rax, 0x8(%rsp)
leaq 0x82c281f(%rip), %rdi # 0x9763a48
addq $0x80, %... | /Target/BPF/BPFTargetMachine.cpp |
llvm::unique_function<void ()>& llvm::SmallVectorTemplateBase<llvm::unique_function<void ()>, false>::growAndEmplaceBack<llvm::BPFTargetMachine::registerPassBuilderCallbacks(llvm::PassBuilder&)::$_16>(llvm::BPFTargetMachine::registerPassBuilderCallbacks(llvm::PassBuilder&)::$_16&&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
xorl %eax, %eax
movl %eax, %esi
leaq 0x30(%rsp), %rdx
callq 0xc50320
movq 0x10(%rsp), %rdi
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0x3a8dca0
movq 0x8(%rsp), %rdi
shlq $0x5, %rax
addq %... | /llvm/ADT/SmallVector.h |
llvm::StringRef llvm::getTypeName<llvm::BPFAbstractMemberAccessPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x54abfa0(%rip), %rsi # 0x6951b3b
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x500fccc(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
std::enable_if<!std::is_same_v<llvm::SimplifyCFGPass, llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>>, void>::type llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::addPass<llvm::SimplifyCFGPass>(llvm::SimplifyCFGPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x20(%rsp)
movl $0x20, %edi
callq 0x349070
movq %rax, %rdi
movq %rdi, 0x18(%rsp)
movq 0x48(%rsp), %rax
movq (%rax), %rcx
movq %rcx, 0x28(%rsp)
movq 0x8(%rax), %rcx
movq %rcx, 0x30(%rsp)
movq 0x10(%rax), %rax
movq %rax, 0x38(%r... | /llvm/IR/PassManager.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::getTypeLegalizationCost(llvm::Type*) const | std::pair<InstructionCost, MVT> getTypeLegalizationCost(Type *Ty) const {
LLVMContext &C = Ty->getContext();
EVT MTy = getTLI()->getValueType(DL, Ty);
InstructionCost Cost = 1;
// We keep legalizing the type until we find a legal kind. We assume that
// the only operation that costs anything is the... | subq $0xc8, %rsp
movq %rdi, 0x8(%rsp)
movq %rdi, 0x10(%rsp)
movq %rsi, 0xc0(%rsp)
movq %rdx, 0xb8(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0xb8(%rsp), %rdi
callq 0x7914b0
movq 0x18(%rsp), %rdi
movq %rax, 0xb0(%rsp)
callq 0x14aaf10
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq 0x8(%rax), %rsi
movq 0xb8(%rsp),... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::getEstimatedNumberOfCaseClusters(llvm::SwitchInst const&, unsigned int&, llvm::ProfileSummaryInfo*, llvm::BlockFrequencyInfo*) | unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
unsigned &JumpTableSize,
ProfileSummaryInfo *PSI,
BlockFrequencyInfo *BFI) {
/// Try to find the estimated number of clu... | subq $0x1f8, %rsp # imm = 0x1F8
movq %rdi, 0x1e8(%rsp)
movq %rsi, 0x1e0(%rsp)
movq %rdx, 0x1d8(%rsp)
movq %rcx, 0x1d0(%rsp)
movq %r8, 0x1c8(%rsp)
movq 0x1e8(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x1e0(%rsp), %rdi
callq 0x7862f0
movq 0x20(%rsp), %rdi
movl %eax, 0x1c4(%rsp)
callq 0x14aaf10
movq 0x20(%rsp), %r... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::improveShuffleKindFromMask(llvm::TargetTransformInfo::ShuffleKind, llvm::ArrayRef<int>, llvm::VectorType*, int&, llvm::VectorType*&) const | TTI::ShuffleKind improveShuffleKindFromMask(TTI::ShuffleKind Kind,
ArrayRef<int> Mask,
VectorType *Ty, int &Index,
VectorType *&SubTy) const {
if (Mask.empty())
return Kind... | subq $0xd8, %rsp
movq 0xe0(%rsp), %rax
movq %rdx, 0xc0(%rsp)
movq %rcx, 0xc8(%rsp)
movq %rdi, 0xb8(%rsp)
movl %esi, 0xb4(%rsp)
movq %r8, 0xa8(%rsp)
movq %r9, 0xa0(%rsp)
leaq 0xc0(%rsp), %rdi
callq 0x7b5970
testb $0x1, %al
jne 0x14ba051
jmp 0x14ba064
movl 0xb4(%rsp), %eax
movl %eax, 0xd4(%rsp)
jmp 0x14ba3bc
movq 0xa8(%r... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::getBroadcastShuffleOverhead(llvm::FixedVectorType*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getBroadcastShuffleOverhead(FixedVectorType *VTy,
TTI::TargetCostKind CostKind) {
InstructionCost Cost = 0;
// Broadcast cost is equal to the cost of extracting the zero'th element
// plus the cost of inserting it into every element of the result... | subq $0x98, %rsp
movq %rdi, 0x80(%rsp)
movq %rsi, 0x78(%rsp)
movl %edx, 0x74(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x10(%rsp)
xorl %eax, %eax
movl %eax, 0x1c(%rsp)
movl %eax, %esi
movq %rsi, 0x20(%rsp)
leaq 0x88(%rsp), %rdi
callq 0x7828c0
movq 0x10(%rsp), %rdi
callq 0x14ac0a0
movl 0x1c(%rsp), %r8d
movq 0x20(%rsp), %r9... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::getExtendedReductionCost(unsigned int, bool, llvm::Type*, llvm::VectorType*, llvm::FastMathFlags, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
Type *ResTy, VectorType *Ty,
FastMathFlags FMF,
TTI::TargetCostKind CostKind) {
// Without any native support, t... | subq $0xc8, %rsp
movb %dl, %al
movl 0xd0(%rsp), %edx
movl %r9d, 0xb4(%rsp)
movq %rdi, 0xa8(%rsp)
movl %esi, 0xa4(%rsp)
andb $0x1, %al
movb %al, 0xa3(%rsp)
movq %rcx, 0x98(%rsp)
movq %r8, 0x90(%rsp)
movq 0xa8(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x98(%rsp), %rdi
movq 0x90(%rsp), %rsi
callq 0x795b20
movq 0x28(%rsp), %r... | /llvm/CodeGen/BasicTTIImpl.h |
(anonymous namespace)::BPFMIPreEmitPeephole::adjustBranch() | bool BPFMIPreEmitPeephole::adjustBranch() {
bool Changed = false;
int CurrNumInsns = 0;
DenseMap<MachineBasicBlock *, int> SoFarNumInsns;
DenseMap<MachineBasicBlock *, MachineBasicBlock *> FollowThroughBB;
std::vector<MachineBasicBlock *> MBBs;
MachineBasicBlock *PrevBB = nullptr;
for (MachineBasicBlock ... | subq $0x518, %rsp # imm = 0x518
movq %rdi, 0x510(%rsp)
movq 0x510(%rsp), %rax
movq %rax, 0x158(%rsp)
movb $0x0, 0x50f(%rsp)
movl $0x0, 0x508(%rsp)
leaq 0x4f0(%rsp), %rdi
xorl %esi, %esi
callq 0x14bfbd0
leaq 0x4d8(%rsp), %rdi
xorl %esi, %esi
callq 0x109d520
leaq 0x4c0(%rsp), %rdi
callq 0x1179930
movq 0x158(%r... | /Target/BPF/BPFMIPeephole.cpp |
llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, int>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, int>>, llvm::MachineBasicBlock*, int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, l... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x14c0430
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x14bffc0
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
llvm::BTFTypeDeclTag::BTFTypeDeclTag(unsigned int, int, llvm::StringRef) | BTFTypeDeclTag::BTFTypeDeclTag(uint32_t BaseTypeId, int ComponentIdx,
StringRef Tag)
: Tag(Tag) {
Kind = BTF::BTF_KIND_DECL_TAG;
BTFType.Info = Kind << 24;
BTFType.Type = BaseTypeId;
Info = ComponentIdx;
} | subq $0x28, %rsp
movq %rcx, 0x18(%rsp)
movq %r8, 0x20(%rsp)
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movl %edx, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x14c33e0
movq (%rsp), %rax
leaq 0x812dc2c(%rip), %rcx # 0x95f3400
addq $0x10, %rcx
movq %rcx, (%rax)
movq 0x18(%rsp), %rcx
movq %rcx, 0x20(%rax)
mo... | /Target/BPF/BTFDebug.cpp |
llvm::BTFDebug::visitArrayType(llvm::DICompositeType const*, unsigned int&) | void BTFDebug::visitArrayType(const DICompositeType *CTy, uint32_t &TypeId) {
// Visit array element type.
uint32_t ElemTypeId;
const DIType *ElemType = CTy->getBaseType();
visitTypeEntry(ElemType, ElemTypeId, false, false);
// Visit array dimensions.
DINodeArray Elements = CTy->getElements();
for (int I... | subq $0xb8, %rsp
movq %rdi, 0xb0(%rsp)
movq %rsi, 0xa8(%rsp)
movq %rdx, 0xa0(%rsp)
movq 0xb0(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0xa8(%rsp), %rdi
callq 0x14c7ff0
movq 0x10(%rsp), %rdi
movq %rax, 0x90(%rsp)
movq 0x90(%rsp), %rsi
leaq 0x9c(%rsp), %rdx
xorl %r8d, %r8d
movl %r8d, %ecx
callq 0x14c8010
movq 0xa8(%rsp), %r... | /Target/BPF/BTFDebug.cpp |
llvm::BTFDebug::constructLineInfo(llvm::MCSymbol*, llvm::DIFile const*, unsigned int, unsigned int) | void BTFDebug::constructLineInfo(MCSymbol *Label, const DIFile *File,
uint32_t Line, uint32_t Column) {
std::string FileName = populateFileContent(File);
BTFLineInfo LineInfo;
LineInfo.Label = Label;
LineInfo.FileNameOff = addString(FileName);
// If file content is not availa... | subq $0xb8, %rsp
movq %rdi, 0xb0(%rsp)
movq %rsi, 0xa8(%rsp)
movq %rdx, 0xa0(%rsp)
movl %ecx, 0x9c(%rsp)
movl %r8d, 0x98(%rsp)
movq 0xb0(%rsp), %rsi
movq %rsi, 0x8(%rsp)
movq 0xa0(%rsp), %rdx
leaq 0x78(%rsp), %rdi
callq 0x14c9830
movq 0xa8(%rsp), %rax
movq %rax, 0x60(%rsp)
leaq 0x50(%rsp), %rdi
leaq 0x78(%rsp), %rsi
ca... | /Target/BPF/BTFDebug.cpp |
llvm::BTFDebug::processGlobalValue(llvm::MachineOperand const&) | void BTFDebug::processGlobalValue(const MachineOperand &MO) {
// check whether this is a candidate or not
if (MO.isGlobal()) {
const GlobalValue *GVal = MO.getGlobal();
auto *GVar = dyn_cast<GlobalVariable>(GVal);
if (!GVar) {
// Not a global variable. Maybe an extern function reference.
pro... | subq $0xa8, %rsp
movq %rdi, 0xa0(%rsp)
movq %rsi, 0x98(%rsp)
movq 0xa0(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x98(%rsp), %rdi
callq 0x739700
testb $0x1, %al
jne 0x14cd9aa
jmp 0x14cdb7e
movq 0x98(%rsp), %rdi
callq 0x733850
movq %rax, 0x90(%rsp)
movq 0x90(%rsp), %rdi
callq 0x1176610
movq %rax, 0x88(%rsp)
cmpq $0x0, 0x88... | /Target/BPF/BTFDebug.cpp |
(anonymous namespace)::BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(llvm::Function&) | bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) {
std::vector<CallInst *> PreserveArrayIndexCalls;
std::vector<CallInst *> PreserveUnionIndexCalls;
std::vector<CallInst *> PreserveStructIndexCalls;
bool Found = false;
for (auto &BB : F)
for (auto &I : BB) {
auto *Call ... | subq $0x188, %rsp # imm = 0x188
movq %rdi, 0x180(%rsp)
movq %rsi, 0x178(%rsp)
movq 0x180(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x160(%rsp), %rdi
callq 0x14f3c50
leaq 0x148(%rsp), %rdi
callq 0x14f3c50
leaq 0x130(%rsp), %rdi
callq 0x14f3c50
movb $0x0, 0x12f(%rsp)
movq 0x178(%rsp), %rax
movq %rax, 0x120(%rsp)
... | /Target/BPF/BPFAbstractMemberAccess.cpp |
(anonymous namespace)::BPFAbstractMemberAccess::IsValidAIChain(llvm::MDNode const*, unsigned int, llvm::MDNode const*) | bool BPFAbstractMemberAccess::IsValidAIChain(const MDNode *ParentType,
uint32_t ParentAI,
const MDNode *ChildType) {
if (!ChildType)
return true; // preserve_field_info, no type comparison needed.
const DIType *PType = st... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movl %edx, 0x5c(%rsp)
movq %rcx, 0x50(%rsp)
cmpq $0x0, 0x50(%rsp)
jne 0x14ed249
movb $0x1, 0x77(%rsp)
jmp 0x14ed3d5
movq 0x60(%rsp), %rdi
callq 0x14eda20
movq %rax, %rdi
callq 0x14ed9c0
movq %rax, 0x48(%rsp)
movq 0x50(%rsp), %rdi
callq 0x14eda20
movq %rax, %r... | /Target/BPF/BPFAbstractMemberAccess.cpp |
(anonymous namespace)::BPFCheckAndAdjustIR::removeCompareBuiltin(llvm::Module&) | bool BPFCheckAndAdjustIR::removeCompareBuiltin(Module &M) {
// Remove __builtin_bpf_compare()'s which are used to prevent
// certain IR optimizations. Now major IR optimizations are done,
// remove them.
bool Changed = false;
CallInst *ToBeDeleted = nullptr;
for (Function &F : M)
for (auto &BB : F)
... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x160(%rsp)
movq %rsi, 0x158(%rsp)
movb $0x0, 0x157(%rsp)
movq $0x0, 0x148(%rsp)
movq 0x158(%rsp), %rax
movq %rax, 0x140(%rsp)
movq 0x140(%rsp), %rdi
callq 0x8e3f20
movq %rax, 0x138(%rsp)
movq 0x140(%rsp), %rdi
callq 0x8e3f50
movq %rax, 0x130(%rsp)
leaq 0x138(%rsp),... | /Target/BPF/BPFCheckAndAdjustIR.cpp |
removeGEPBuiltinsInFunc(llvm::Function&) | static bool removeGEPBuiltinsInFunc(Function &F) {
SmallVector<CallInst *> GEPLoads;
SmallVector<CallInst *> GEPStores;
for (auto &BB : F)
for (auto &Insn : BB)
if (auto *Call = dyn_cast<CallInst>(&Insn))
if (auto *Called = Call->getCalledFunction())
switch (Called->getIntrinsicID()) {... | subq $0x118, %rsp # imm = 0x118
movq %rdi, 0x108(%rsp)
leaq 0xc8(%rsp), %rdi
callq 0x10572c0
leaq 0x88(%rsp), %rdi
callq 0x10572c0
movq 0x108(%rsp), %rax
movq %rax, 0x80(%rsp)
movq 0x80(%rsp), %rdi
callq 0x7df3c0
movq %rax, 0x78(%rsp)
movq 0x80(%rsp), %rdi
callq 0x7df3f0
movq %rax, 0x70(%rsp)
leaq 0x78(%rsp)... | /Target/BPF/BPFCheckAndAdjustIR.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>, llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>::makeIterator(llvm::detail::DenseMapP... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x14fbf70
testb $0x1, %al
jne 0x14fbec6
jmp 0x14fbf32
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%... | /llvm/ADT/DenseMap.h |
llvm::BPFTargetLowering::getTargetNodeName(unsigned int) const | const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((BPFISD::NodeType)Opcode) {
case BPFISD::FIRST_NUMBER:
break;
case BPFISD::RET_GLUE:
return "BPFISD::RET_GLUE";
case BPFISD::CALL:
return "BPFISD::CALL";
case BPFISD::SELECT_CC:
return "BPFISD::SELECT_CC";
case... | movq %rdi, -0x10(%rsp)
movl %esi, -0x14(%rsp)
movl -0x14(%rsp), %eax
addl $0xfffffe1b, %eax # imm = 0xFFFFFE1B
movl %eax, %ecx
movq %rcx, -0x20(%rsp)
subl $0x6, %eax
ja 0x1517eb9
movq -0x20(%rsp), %rax
leaq 0x543c836(%rip), %rcx # 0x6954690
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
jmp 0x1517eb9
lea... | /Target/BPF/BPFISelLowering.cpp |
llvm::HexagonInstrInfo::removeBranch(llvm::MachineBasicBlock&, int*) const | unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
MachineBasicBlock::iterator I = MBB.end();
unsigned... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
jmp 0x1520fd5
movq 0x40(%rsp), %rdi
callq 0x73fef0
movq %rax, 0x30(%rsp)
movl $0x0, 0x2c(%rsp)
movq 0x40(%rsp), %rdi
callq 0x73fe80
movq %rax, 0x20(%rsp)
leaq 0x30(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x73fec0
testb $0x1, %al
jne 0x15... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::PredicateInstruction(llvm::MachineInstr&, llvm::ArrayRef<llvm::MachineOperand>) const | bool HexagonInstrInfo::PredicateInstruction(
MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
isEndLoopN(Cond[0].getImm())) {
LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
return false;
}
int Opc = MI.getOpcode();
asser... | subq $0x118, %rsp # imm = 0x118
movq %rdx, 0x100(%rsp)
movq %rcx, 0x108(%rsp)
movq %rdi, 0xf8(%rsp)
movq %rsi, 0xf0(%rsp)
movq 0xf8(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0x100(%rsp), %rdi
callq 0xad0f60
testb $0x1, %al
jne 0x152b5e9
leaq 0x100(%rsp), %rdi
xorl %eax, %eax
movl %eax, %esi
callq 0x8fece0
movq ... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::StringRef llvm::getTypeName<llvm::HexagonLoopIdiomRecognitionPass>() | inline StringRef getTypeName() {
#if defined(__clang__) || defined(__GNUC__)
StringRef Name = __PRETTY_FUNCTION__;
StringRef Key = "DesiredTypeName = ";
Name = Name.substr(Name.find(Key));
assert(!Name.empty() && "Unable to find the template parameter!");
Name = Name.drop_front(Key.size());
assert(Name.en... | subq $0x78, %rsp
leaq 0x56614a0(%rip), %rsi # 0x6baae5b
leaq 0x50(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x3ee9c0
leaq 0x4f6beac(%rip), %rsi # 0x64b587d
leaq 0x40(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x3ee9c0
movq 0x8(%rsp), %rdi
movups 0x40(%rsp), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x20(%rsp), %rsi
movq 0x28(%rsp)... | /llvm/Support/TypeName.h |
llvm::HexagonTTIImpl::getCmpSelInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::CmpInst::Predicate, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
Type *CondTy,
CmpInst::Predicate VecPred,
TTI::TargetCostKind CostKind,
... | subq $0xa8, %rsp
movq 0xb0(%rsp), %rax
movq %rdi, 0x90(%rsp)
movl %esi, 0x8c(%rsp)
movq %rdx, 0x80(%rsp)
movq %rcx, 0x78(%rsp)
movl %r8d, 0x74(%rsp)
movl %r9d, 0x70(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x80(%rsp), %rdi
callq 0x784bf0
testb $0x1, %al
jne 0x15609b8
jmp 0x1560a92
cmpl $0x0, 0x70(%rsp)
jn... | /Target/Hexagon/HexagonTargetTransformInfo.cpp |
llvm::DenseMapIterator<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Instruction*>, false>::operator++() | inline DenseMapIterator& operator++() { // Preincrement
assert(isHandleInSync() && "invalid iterator access!");
assert(Ptr != End && "incrementing end() iterator");
if (shouldReverseIterate<KeyT>()) {
--Ptr;
RetreatPastEmptyBuckets();
return *this;
}
++Ptr;
AdvancePastEmptyBuc... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
callq 0x7ba9e0
testb $0x1, %al
jne 0x157a37d
jmp 0x157a39b
movq (%rsp), %rdi
movq (%rdi), %rax
addq $-0x10, %rax
movq %rax, (%rdi)
callq 0x157aad0
movq (%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0x157a3b7
movq (%rsp), %rdi
movq (%rdi), %rax
addq $... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HvxIdioms::createMul32(llvm::IRBuilderBase&, (anonymous namespace)::HvxIdioms::SValue, (anonymous namespace)::HvxIdioms::SValue) const | auto HvxIdioms::createMul32(IRBuilderBase &Builder, SValue X, SValue Y) const
-> std::pair<Value *, Value *> {
assert(X.Val->getType() == Y.Val->getType());
assert(X.Val->getType() == HvxI32Ty);
Intrinsic::ID V6_vmpy_parts;
std::tie(X, Y) = canonSgn(X, Y);
if (X.Sgn == Signed) {
V6_vmpy_parts = Intr... | subq $0x238, %rsp # imm = 0x238
movq %rdx, 0x218(%rsp)
movl %ecx, 0x220(%rsp)
movq %r8, 0x208(%rsp)
movl %r9d, 0x210(%rsp)
movq %rdi, 0x200(%rsp)
movq %rsi, 0x1f8(%rsp)
movq 0x200(%rsp), %rsi
movq %rsi, 0x70(%rsp)
movq 0x218(%rsp), %rax
movq %rax, 0x1c0(%rsp)
movq 0x220(%rsp), %rax
movq %rax, 0x1c8(%rsp)
mov... | /Target/Hexagon/HexagonVectorCombine.cpp |
llvm::HexagonPacketizerList::canPromoteToDotCur(llvm::MachineInstr const&, llvm::SUnit const*, unsigned int, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::TargetRegisterClass const*) | bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass *RC) {
if (!HII->isHVXVec(MI))
return false;
if (!HII->isHVXVec(*MII))
return false;
// Already a dot new instruction.
i... | subq $0xc8, %rsp
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq %rdx, 0xa8(%rsp)
movl %ecx, 0xa4(%rsp)
movq %r8, 0x98(%rsp)
movq %r9, 0x90(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0xe0(%rax), %rdi
movq 0xb0(%rsp), %rsi
callq 0x152fa70
testb $0x1, %al
jne 0x15985a8
movb $0x0, 0xc7(%rsp)
jmp 0x1598853
mov... | /Target/Hexagon/HexagonVLIWPacketizer.cpp |
llvm::HexagonPacketizerList::promoteToDotNew(llvm::MachineInstr&, llvm::SDep::Kind, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::TargetRegisterClass const*) | bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert(DepType == SDep::Data);
int NewOpcode;
if (RC == &Hexagon::PredRegsRegClass)
NewOpcode = HII->getDotNewPredOp(MI, MBPI);
else
NewOpcode ... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movl %edx, 0x34(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x805e243(%rip), %rax # 0x95f6ae0
cmpq %rax, 0x20(%rsp)
jne 0x15988c7
movq 0x10(%rsp), %rax
movq 0xe0(%rax), %rdi
movq 0x38(%rsp), %rsi
movq 0x... | /Target/Hexagon/HexagonVLIWPacketizer.cpp |
llvm::HexagonPacketizerList::useCallersSP(llvm::MachineInstr&) | bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
case Hexagon::S2_storerh_io:
case Hexagon::S2_storerb_io:
break;
default:
llvm_unreachable("Unexpected instruction");
... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x30(%rsp), %rdi
callq 0x72bbb0
movl %eax, 0x2c(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x14(%rsp)
subl $0x8ed, %eax # imm = 0x8ED
je 0x15989e1
jmp 0x15989c7
movl 0x14(%rsp), %eax
subl $0x8fb, %eax ... | /Target/Hexagon/HexagonVLIWPacketizer.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::HexagonEvaluator::ExtType, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::HexagonEvaluator::ExtType>>, unsigned int, llvm::HexagonEvaluator::ExtType, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned ... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x15a9b40
cmpl $0x0, %eax
jne 0x15a9aa1
jmp 0x15a9b35
callq 0x15a9b50
movl %eax, 0x1c(%rsp)
callq 0x15a9b60
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x15a9b70
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x15a9b80
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonCommonGEP::isHandledGepForm(llvm::GetElementPtrInst*) | bool HexagonCommonGEP::isHandledGepForm(GetElementPtrInst *GepI) {
// No vector GEPs.
if (!GepI->getType()->isPointerTy())
return false;
// No GEPs without any indices. (Is this possible?)
if (GepI->idx_begin() == GepI->idx_end())
return false;
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x782840
movq %rax, %rdi
callq 0x7908d0
testb $0x1, %al
jne 0x15cc04b
movb $0x0, 0x27(%rsp)
jmp 0x15cc07d
movq 0x10(%rsp), %rdi
callq 0x15087c0
movq %rax, 0x8(%rsp)
movq 0x10(%rsp), %rdi
callq 0x15087e0
movq %rax, %rcx
movq 0x8(%rs... | /Target/Hexagon/HexagonCommonGEP.cpp |
preheader(llvm::DominatorTree*, llvm::Loop*) | static BasicBlock *preheader(DominatorTree *DT, Loop *L) {
if (BasicBlock *PH = L->getLoopPreheader())
return PH;
if (!OptSpeculate)
return nullptr;
DomTreeNode *DN = DT->getNode(L->getHeader());
if (!DN)
return nullptr;
return DN->getIDom()->getBlock();
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
callq 0x57bff70
movq %rax, 0x18(%rsp)
cmpq $0x0, 0x18(%rsp)
je 0x15da7e1
movq 0x18(%rsp), %rax
movq %rax, 0x30(%rsp)
jmp 0x15da853
leaq 0x818d838(%rip), %rdi # 0x9768020
addq $0x80, %rdi
callq 0x3f1b60
testb $0x1, %al
jne 0x15da803
mov... | /Target/Hexagon/HexagonCommonGEP.cpp |
llvm::DenseMap<llvm::Use*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Use*, void>, llvm::detail::DenseSetPair<llvm::Use*>>::copyFrom(llvm::DenseMap<llvm::Use*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Use*, void>, llvm::detail::DenseSetPair<llvm::Use*>> const&) | void copyFrom(const DenseMap& other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
if (allocateBuckets(other.NumBuckets)) {
this->BaseT::copyFrom(other);
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x12464d0
movq (%rsp), %rax
movq (%rax), %rdi
movl 0x10(%rax), %eax
movl %eax, %esi
shlq $0x3, %rsi
movl $0x8, %edx
callq 0x3a79dc0
movq (%rsp), %rdi
movq 0x8(%rsp), %rax
movl 0x10(%rax), %esi
callq 0x12444f0
testb... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonConstExtenders::isRegOffOpcode(unsigned int) const | bool HCE::isRegOffOpcode(unsigned Opc) const {
switch (Opc) {
case Hexagon::L2_loadrub_io:
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadruh_io:
case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadri_io:
case Hexagon::L2_loadrd_io:
case Hexagon::L2_loadbzw2_io:
case Hexagon::L2_loadbzw... | movq %rdi, -0x10(%rsp)
movl %esi, -0x14(%rsp)
movl -0x14(%rsp), %eax
movl %eax, -0x18(%rsp)
subl $0x396, %eax # imm = 0x396
je 0x15e651d
jmp 0x15e62ae
movl -0x18(%rsp), %eax
subl $0x5d0, %eax # imm = 0x5D0
je 0x15e651d
jmp 0x15e62bf
movl -0x18(%rsp), %eax
subl $0x5d6, %eax # imm = 0x5D6... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::LatticeCell::add(unsigned int) | bool LatticeCell::add(uint32_t Property) {
bool Changed = convertToProperty();
uint32_t Ps = properties();
if (Ps == (Ps & Property))
return Changed;
Properties = Property & Ps;
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x15f8250
movq (%rsp), %rdi
andb $0x1, %al
movb %al, 0x13(%rsp)
callq 0x15f7460
movl %eax, 0xc(%rsp)
movl 0xc(%rsp), %eax
movl 0xc(%rsp), %ecx
andl 0x14(%rsp), %ecx
cmpl %ecx, %eax
jne 0x15f3bda
movb 0x13(%rsp), %... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::MachineConstPropagator::propagate(llvm::MachineFunction&) | void MachineConstPropagator::propagate(MachineFunction &MF) {
MachineBasicBlock *Entry = GraphTraits<MachineFunction*>::getEntryNode(&MF);
unsigned EntryNum = Entry->getNumber();
// Start with a fake edge, just to process the entry node.
FlowQ.push(CFGEdge(EntryNum, EntryNum));
while (!FlowQ.empty()) {
... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x130(%rsp)
movq %rsi, 0x128(%rsp)
movq 0x130(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x128(%rsp), %rdi
callq 0xd39bf0
movq %rax, 0x120(%rsp)
movq 0x120(%rsp), %rdi
callq 0x951660
movl %eax, %ecx
movq 0x40(%rsp), %rax
movl %ecx, 0x11c(%rsp)
addq $0x118, %rax ... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::HexagonCopyHoisting::getAnalysisUsage(llvm::AnalysisUsage&) const | void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<SlotIndexesWrapperPass>();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addPreserv... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
movq 0x8(%rsp), %rdi
callq 0x10e58f0
movq 0x8(%rsp), %rdi
callq 0xb308c0
movq 0x8(%rsp), %rdi
callq 0xcaef30
movq 0x8(%rsp), %rdi
callq 0xcaef00
movq 0x8(%rsp), %rdi
callq 0x88b140
movq 0x8(%rsp), %rdi
callq 0x88b160
mov... | /Target/Hexagon/HexagonCopyHoisting.cpp |
llvm::HexagonFrameLowering::emitPrologue(llvm::MachineFunction&, llvm::MachineBasicBlock&) const | void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
MachineFrameInfo &MFI = MF.getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
... | subq $0x218, %rsp # imm = 0x218
movq %rdi, 0x210(%rsp)
movq %rsi, 0x208(%rsp)
movq %rdx, 0x200(%rsp)
movq 0x210(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x208(%rsp), %rdi
callq 0x151d3b0
movq %rax, %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, 0x1f8(%rsp)
movq 0x208(%rsp), %rdi
callq 0x73fb60
movq %rax, ... | /Target/Hexagon/HexagonFrameLowering.cpp |
llvm::DenseMap<llvm::TargetRegisterClass const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetRegisterClass const*, void>, llvm::detail::DenseSetPair<llvm::TargetRegisterClass const*>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0x162a337
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0x162a35f
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
sh... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::TargetRegisterClass const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetRegisterClass const*, void>, llvm::detail::DenseSetPair<llvm::TargetRegisterClass const*>, false>::DenseMapIterator(llvm::detail::DenseSetPair<llvm::TargetRegisterClass const*>*, llvm::detail::DenseSetPa... | DenseMapIterator(pointer Pos, pointer E, const DebugEpochBase &Epoch,
bool NoAdvance = false)
: DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) {
assert(isHandleInSync() && "invalid construction!");
if (NoAdvance) return;
if (shouldReverseIterate<KeyT>()) {
RetreatPastEm... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x5481a0
movq 0x8(%rsp), %rax
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq 0x20(%rsp), %rcx
m... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::TargetRegisterClass const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetRegisterClass const*, void>, llvm::detail::DenseSetPair<llvm::TargetRegisterClass const*>, false>::RetreatPastEmptyBuckets() | void RetreatPastEmptyBuckets() {
assert(Ptr >= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr[-1].getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr[-1].getFirst(), Tombstone)))
-... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xcae470
movq %rax, 0x18(%rsp)
callq 0xcaece0
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x16306a0
movq 0x8(%rsp), %rax
movq (%rax), %rdi
addq $-0x8, %rdi... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::TargetRegisterClass const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetRegisterClass const*, void>, llvm::detail::DenseSetPair<llvm::TargetRegisterClass const*>, false>::AdvancePastEmptyBuckets() | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xcae470
movq %rax, 0x18(%rsp)
callq 0xcaece0
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x1630758
movq 0x8(%rsp), %rax
movq (%rax), %rdi
callq 0x162a490
... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>, std::allocator<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, st... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x163be30
cmpl $0x0, %eax
jne 0x163bec1
jmp 0x163bf5d
callq 0x163bd70
movl %eax, 0x1c(%rsp)
callq 0x163bf70
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x163bd80
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x163bd90
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<unsigned int, unsigned short>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<un... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x1644310
callq 0x16443d0
movl %eax, 0x3c(%rsp)
callq 0x1644de0
movl %eax, 0x38(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x30(%rs... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>, std::allocator<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned in... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq 0x58(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x1646450
movq 0x10(%rsp), %rdi
movq %rax, 0x40(%rsp)
callq 0x163be30
movl %eax, 0x3c(%rsp)
cmpl $0x0, 0x3c(%rsp)
jne 0x1646312
movq 0x48(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x67(%rs... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::IFOrdering::stats((anonymous namespace)::RegisterSet const&, unsigned int&, unsigned int&, unsigned int&) const | void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
unsigned &Sum) const {
for (unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) {
UnsignedMap::const_iterator F = UseC.find(R);
assert(F != UseC.end());
unsigned UC = F->second;
if (UC == 0)
Zero++;
Sum += ... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq %rcx, 0x38(%rsp)
movq %r8, 0x30(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x48(%rsp), %rdi
callq 0x1641f10
movl %eax, 0x2c(%rsp)
cmpl $0x0, 0x2c(%rsp)
je 0x164cbe9
movq 0x8(%rsp), %rax
movq (%rax), %rdi
leaq 0x2c(%rsp), ... | /Target/Hexagon/HexagonGenInsert.cpp |
llvm::DenseMapIterator<unsigned int, (anonymous namespace)::HexagonGenMux::DefUseInfo, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::HexagonGenMux::DefUseInfo>, false>::AdvancePastEmptyBuckets() | void AdvancePastEmptyBuckets() {
assert(Ptr <= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr->getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr->getFirst(), Tombstone)))
++Ptr;
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x5479c0
movl %eax, 0x1c(%rsp)
callq 0x5480c0
movl %eax, 0x18(%rsp)
movq 0x10(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0xf(%rsp)
je 0x1650eb6
movq 0x10(%rsp), %rax
movq (%rax), %rdi
callq 0x164ff... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonHardwareLoops::isDead(llvm::MachineInstr const*, llvm::SmallVectorImpl<llvm::MachineInstr*>&) const | bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
SmallVectorImpl<MachineInstr *> &DeadPhis) const {
// Examine each operand.
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
Register Reg = MO.getReg();
if (MRI->use_... | subq $0x108, %rsp # imm = 0x108
movq %rdi, 0xf8(%rsp)
movq %rsi, 0xf0(%rsp)
movq %rdx, 0xe8(%rsp)
movq 0xf8(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0xf0(%rsp), %rdi
callq 0x72c290
movq %rax, 0xd0(%rsp)
movq %rdx, 0xd8(%rsp)
leaq 0xd0(%rsp), %rax
movq %rax, 0xe0(%rsp)
movq 0xe0(%rsp), %rdi
callq 0x72c2e0
movq %... | /Target/Hexagon/HexagonHardwareLoops.cpp |
llvm::HexagonDAGToDAGISel::SelectIntrinsicWChain(llvm::SDNode*) | void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
if (MachineSDNode *L = LoadInstrForLoadIntrinsic(N)) {
StoreInstrForLoadIntrinsic(L, N);
CurDAG->RemoveDeadNode(N);
return;
}
// Handle bit-reverse load intrinsics.
if (SelectBrevLdIntrinsic(N))
return;
if (SelectNewCircIntrinsic(N... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movq 0x18(%rsp), %rsi
callq 0x166bea0
movq %rax, 0x10(%rsp)
cmpq $0x0, 0x10(%rsp)
je 0x166f0b8
movq (%rsp), %rdi
movq 0x10(%rsp), %rsi
movq 0x18(%rsp), %rdx
callq 0x166c2b0
movq (%rsp), %rax
movq 0x38(%rax), %rdi
movq 0... | /Target/Hexagon/HexagonISelDAGToDAG.cpp |
llvm::HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<llvm::SDNode*, std::allocator<llvm::SDNode*>>&&) | void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
for (SDNode *N : Nodes) {
unsigned Opc = N->getOpcode();
if (Opc != ISD::LOAD && Opc != ISD::STORE)
continue;
SDValue Addr = Opc == ISD::LOAD ? N->getOperand(1) : N->getOperand(2);
// Ad... | subq $0x228, %rsp # imm = 0x228
movq %rdi, 0x220(%rsp)
movq %rsi, 0x218(%rsp)
movq 0x220(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x38(%rax), %rax
movq %rax, 0x210(%rsp)
movq 0x218(%rsp), %rax
movq %rax, 0x208(%rsp)
movq 0x208(%rsp), %rdi
callq 0x1674420
movq %rax, 0x200(%rsp)
movq 0x208(%rsp), %rdi
callq 0x16... | /Target/Hexagon/HexagonISelDAGToDAG.cpp |
llvm::SetVector<int, llvm::SmallVector<int, 0u>, llvm::DenseSet<int, llvm::DenseMapInfo<int, void>>, 0u>::insert(int const&) | bool insert(const value_type &X) {
if constexpr (canBeSmall())
if (isSmall()) {
if (!llvm::is_contained(vector_, X)) {
vector_.push_back(X);
if (vector_.size() > N)
makeBig();
return true;
}
return false;
}
bool result = set_.insert(... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rsi
movq %rsi, (%rsp)
movq 0x28(%rsp), %rdx
leaq 0x8(%rsp), %rdi
callq 0xb5edb0
movb 0x18(%rsp), %al
andb $0x1, %al
movb %al, 0x27(%rsp)
testb $0x1, 0x27(%rsp)
je 0x169a5cb
movq (%rsp), %rdi
addq $0x18, %rdi
movq 0x28(%rsp), %rax
movl (%rax)... | /llvm/ADT/SetVector.h |
llvm::DenseMap<llvm::SDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseSetPair<llvm::SDNode*>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movl 0x10(%rdi), %eax
movl %eax, 0x1c(%rsp)
movl 0x8(%rdi), %eax
movl %eax, 0x18(%rsp)
callq 0x1688f50
movl $0x0, 0x14(%rsp)
cmpl $0x0, 0x18(%rsp)
je 0x16a187a
movl $0x40, 0x10(%rsp)
movl 0x18(%rsp), %edi
callq 0x91b7e0
movl %eax, %ecx
addl ... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::SDNode*, llvm::SDNode**, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode**>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(llvm::GlobalAddressSDNode*, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) const {
SDLoc dl(GA);
int64_t Offset = GA->getOffset();
auto PtrVT = getPointerTy(DAG.getDataLayout());
// First generate the TLS symbol address
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGloba... | subq $0x2c8, %rsp # imm = 0x2C8
movq %rdi, 0x2b0(%rsp)
movq %rsi, 0x2a8(%rsp)
movq %rdx, 0x2a0(%rsp)
movq 0x2b0(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x2a8(%rsp), %rsi
leaq 0x290(%rsp), %rdi
movq %rdi, 0x70(%rsp)
callq 0x9817d0
movq 0x2a8(%rsp), %rdi
callq 0x997ec0
movq %rax, 0x288(%rsp)
movq 0x2a0(%rsp), %... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerHvxCttz(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const {
// Lower vector CTTZ into a computation using CTLZ (Hacker's Delight):
// cttz(x) = bitwidth(x) - ctlz(~x & (x-1))
const SDLoc &dl(Op);
MVT ResTy = ty(Op);
SDValue InpV = Op.getOperand(0);
assert(ResTy == ty(InpV));
// Cal... | subq $0x4f8, %rsp # imm = 0x4F8
movq %rsi, 0x4d8(%rsp)
movl %edx, 0x4e0(%rsp)
movq %rdi, 0x4d0(%rsp)
movq %rcx, 0x4c8(%rsp)
movq 0x4d0(%rsp), %rax
movq %rax, 0x18(%rsp)
movups 0x4d8(%rsp), %xmm0
movaps %xmm0, 0x4a0(%rsp)
movq 0x4a0(%rsp), %rsi
movl 0x4a8(%rsp), %edx
leaq 0x4b0(%rsp), %rdi
movq %rdi, 0xf8(%rs... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [33], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(char const (&) [33], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, (%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq (%rsp), %rdi
addq $0x80, %rdi
callq 0x76e5e0
movq (%rsp), %rsi
leaq 0x7fe1456(%rip), %rax # 0x96defe... | /llvm/Support/CommandLine.h |
llvm::DenseMap<unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0x1727957
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0x172797d
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
imulq $0xc, %rax, ... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>>, unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::Dens... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x1727b10
cmpl $0x0, %eax
jne 0x1727c61
jmp 0x1727cf5
callq 0x1727a50
movl %eax, 0x1c(%rsp)
callq 0x1727b60
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x1727a60
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x1727a70
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonDCE::removeOperand(llvm::rdf::NodeAddr<llvm::rdf::InstrNode*>, unsigned int) | void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
auto getOpNum = [MI] (MachineOperand &Op) -> unsigned {
for (unsigned i = 0, n = MI->getNumOperands(); i != n; ++i)
if (&MI->getOperand(i) == &Op)
return i;
ll... | subq $0x158, %rsp # imm = 0x158
movq %rsi, 0x148(%rsp)
movl %edx, 0x150(%rsp)
movq %rdi, 0x140(%rsp)
movl %ecx, 0x13c(%rsp)
movq 0x140(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0x120(%rsp), %rdi
leaq 0x148(%rsp), %rsi
callq 0x1720930
movq 0x120(%rsp), %rdi
callq 0x171c780
movq %rax, 0x130(%rsp)
movq 0x130(%rsp)... | /Target/Hexagon/HexagonRDFOpt.cpp |
llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(llvm::SelectionDAG&, llvm::SDLoc const&, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::Align, bool, bool, llvm::MachinePointerInfo, llvm::MachinePointerInfo) const | SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
ConstantSDNode *ConstantSize = dyn... | pushq %rbx
subq $0x12d0, %rsp # imm = 0x12D0
movl %r8d, %r10d
movq %rcx, %r11
movq %rdi, %r8
movb 0x1318(%rsp), %al
movb 0x1310(%rsp), %cl
leaq 0x1300(%rsp), %rdi
movq %rdi, 0x60(%rsp)
leaq 0x12f0(%rsp), %rbx
movq %rbx, 0x68(%rsp)
leaq 0x12e0(%rsp), %rbx
movq %rbx, 0x70(%rsp)
movq %r11, 0x12b0(%rsp)
movl %r10... | /Target/Hexagon/HexagonSelectionDAGInfo.cpp |
(anonymous namespace)::HexagonSplitDoubleRegs::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
LLVM_DEBUG(dbgs() << "Splitting double registers in function: "
<< MF.getName() << '\n');
auto &ST = MF.getSubtarget<HexagonSubtarget>();
TRI = ST.getRegisterInfo(... | subq $0xa8, %rsp
movq %rdi, 0x98(%rsp)
movq %rsi, 0x90(%rsp)
movq 0x98(%rsp), %rax
movq %rax, (%rsp)
movq 0x90(%rsp), %rdi
callq 0x727890
movq (%rsp), %rdi
movq %rax, %rsi
callq 0x312ea30
testb $0x1, %al
jne 0x172dd52
jmp 0x172dd5f
movb $0x0, 0xa7(%rsp)
jmp 0x172df22
jmp 0x172dd61
jmp 0x172dd63
movq 0x90(%rsp), %rdi
ca... | /Target/Hexagon/HexagonSplitDouble.cpp |
(anonymous namespace)::HexagonSplitDoubleRegs::profit(llvm::Register) const | int32_t HexagonSplitDoubleRegs::profit(Register Reg) const {
assert(Reg.isVirtual());
const MachineInstr *DefI = MRI->getVRegDef(Reg);
switch (DefI->getOpcode()) {
case Hexagon::A2_tfrpi:
case Hexagon::CONST64:
case Hexagon::A2_combineii:
case Hexagon::A4_combineii:
case Hexagon::A4_combineri... | subq $0x28, %rsp
movl %esi, 0x20(%rsp)
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
movq 0x50(%rax), %rdi
movl 0x20(%rsp), %eax
movl %eax, 0xc(%rsp)
movl 0xc(%rsp), %esi
callq 0x34bc760
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x72bbb0
movl %eax, %ecx
movl %ecx, 0x8(%rsp)
subl $0x130, %eax ... | /Target/Hexagon/HexagonSplitDouble.cpp |
llvm::rdf::DeadCodeElimination::processDef(llvm::rdf::NodeAddr<llvm::rdf::DefNode*>, llvm::rdf::DeadCodeElimination::SetQueue<unsigned int>&) | void DeadCodeElimination::processDef(NodeAddr<DefNode*> DA,
SetQueue<NodeId> &WorkQ) {
NodeAddr<InstrNode*> IA = DA.Addr->getOwner(DFG);
for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) {
if (!LiveNodes.count(UA.Id))
WorkQ.push_back(UA.Id);
}
for (NodeAddr<DefNode*> TA : DFG.get... | subq $0x178, %rsp # imm = 0x178
movq %rsi, 0x168(%rsp)
movl %edx, 0x170(%rsp)
movq %rdi, 0x160(%rsp)
movq %rcx, 0x158(%rsp)
movq 0x160(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x168(%rsp), %rdi
movq 0x80(%rax), %rsi
callq 0x35a0c00
movl %edx, 0x130(%rsp)
movq %rax, 0x128(%rsp)
movq 0x128(%rsp), %rax
movq %rax,... | /Target/Hexagon/RDFDeadCode.cpp |
llvm::operator<<(llvm::raw_ostream&, llvm::BitTracker::BitValue const&) | raw_ostream &operator<<(raw_ostream &OS, const BT::BitValue &BV) {
switch (BV.Type) {
case BT::BitValue::Top:
OS << 'T';
break;
case BT::BitValue::Zero:
OS << '0';
break;
case BT::BitValue::One:
OS << '1';
break;
case BT::BitValue::Ref:
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x18(%rsp), %rax
movl (%rax), %eax
movq %rax, 0x8(%rsp)
subq $0x3, %rax
ja 0x174a688
movq 0x8(%rsp), %rax
leaq 0x548dcf4(%rip), %rcx # 0x6bd82e4
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x20(%rsp), %rdi
movl $0x54, %esi
callq 0x3f80a0... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::RegisterCell::rol(unsigned short) | BT::RegisterCell &BT::RegisterCell::rol(uint16_t Sh) {
// Rotate left (i.e. towards increasing bit indices).
// Swap the two parts: [0..W-Sh-1] [W-Sh..W-1]
uint16_t W = width();
Sh = Sh % W;
if (Sh == 0)
return *this;
RegisterCell Tmp(W-Sh);
// Tmp = [0..W-Sh-1].
for (uint16_t i = 0; i < W-Sh; ++i... | subq $0x1d8, %rsp # imm = 0x1D8
movw %si, %ax
movq %rdi, 0x1c8(%rsp)
movw %ax, 0x1c6(%rsp)
movq 0x1c8(%rsp), %rdi
movq %rdi, 0x20(%rsp)
callq 0x15a3f50
movw %ax, 0x1c4(%rsp)
movzwl 0x1c6(%rsp), %eax
movzwl 0x1c4(%rsp), %ecx
cltd
idivl %ecx
movw %dx, %ax
movw %ax, 0x1c6(%rsp)
movzwl 0x1c6(%rsp), %eax
cmpl $0x... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eSUB(llvm::BitTracker::RegisterCell const&, llvm::BitTracker::RegisterCell const&) const | BT::RegisterCell BT::MachineEvaluator::eSUB(const RegisterCell &A1,
const RegisterCell &A2) const {
uint16_t W = A1.width();
assert(W == A2.width());
RegisterCell Res(W);
bool Borrow = false;
uint16_t I;
for (I = 0; I < W; ++I) {
const BitValue &V1 = A1[I];
const BitValue &V2 = A2[I];
if (... | subq $0xe8, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, %rax
movq %rax, 0x18(%rsp)
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
movq %rdx, 0xd0(%rsp)
movq %rcx, 0xc8(%rsp)
movq 0xd0(%rsp), %rdi
callq 0x15a3f50
movq 0x20(%rsp), %rdi
movw %ax, 0xc6(%rsp)
movb $0x0, 0xc5(%rsp)
movzwl 0xc6(%rsp), %esi
callq 0x15b51a0
movb $0x0, 0... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eASR(llvm::BitTracker::RegisterCell const&, unsigned short) const | BT::RegisterCell BT::MachineEvaluator::eASR(const RegisterCell &A1,
uint16_t Sh) const {
uint16_t W = A1.width();
assert(Sh <= W);
RegisterCell Res = RegisterCell::ref(A1);
BitValue Sign = Res[W-1];
Res.rol(W-Sh);
Res.fill(W-Sh, W, Sign);
return Res;
} | subq $0x48, %rsp
movq %rdi, 0x10(%rsp)
movw %cx, %ax
movq %rdi, %rcx
movq %rcx, 0x8(%rsp)
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movw %ax, 0x2e(%rsp)
movq 0x30(%rsp), %rdi
callq 0x15a3f50
movq 0x10(%rsp), %rdi
movw %ax, 0x2c(%rsp)
movb $0x0, 0x2b(%rsp)
movq 0x30(%rsp), %rsi
callq 0x15c43b0
mo... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eORL(llvm::BitTracker::RegisterCell const&, llvm::BitTracker::RegisterCell const&) const | BT::RegisterCell BT::MachineEvaluator::eORL(const RegisterCell &A1,
const RegisterCell &A2) const {
uint16_t W = A1.width();
assert(W == A2.width());
RegisterCell Res(W);
for (uint16_t i = 0; i < W; ++i) {
const BitValue &V1 = A1[i];
const BitValue &V2 = A2[i];
if (V1.is(1) || V2.is(1))
... | subq $0xc8, %rsp
movq %rdi, 0x18(%rsp)
movq %rdi, %rax
movq %rax, 0x10(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
movq %rcx, 0xa8(%rsp)
movq 0xb0(%rsp), %rdi
callq 0x15a3f50
movq 0x18(%rsp), %rdi
movw %ax, 0xa6(%rsp)
movb $0x0, 0xa5(%rsp)
movzwl 0xa6(%rsp), %esi
callq 0x15b51a0
movw $0x0, 0... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::visitUsesOf(llvm::Register) | void BT::visitUsesOf(Register Reg) {
if (Trace)
dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
<< " cell: " << ME.getCell(Reg, Map) << '\n';
for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))
UseQ.push(&UseI);
} | subq $0x238, %rsp # imm = 0x238
movl %esi, 0x234(%rsp)
movq %rdi, 0x228(%rsp)
movq 0x228(%rsp), %rax
movq %rax, 0x20(%rsp)
testb $0x1, 0x138(%rax)
je 0x174ede2
callq 0x3a66bb0
movq %rax, %rdi
leaq 0x54896cb(%rip), %rsi # 0x6bd83ca
callq 0x41be30
movq %rax, %rcx
movq 0x20(%rsp), %rax
movq %rcx, 0x8(%rsp)
mo... | /Target/Hexagon/BitTracker.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, unsigned int>>, llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<l... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xb3ba60
testb $0x1, %al
jne 0x1752276
jmp 0x17522e2
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%r... | /llvm/ADT/DenseMap.h |
llvm::BasicTTIImplBase<llvm::LanaiTTIImpl>::getCommonMaskedMemoryOpCost(unsigned int, llvm::Type*, llvm::Align, bool, bool, llvm::TargetTransformInfo::TargetCostKind, unsigned int) | InstructionCost getCommonMaskedMemoryOpCost(unsigned Opcode, Type *DataTy,
Align Alignment,
bool VariableMask,
bool IsGatherScatter,
TTI... | subq $0x288, %rsp # imm = 0x288
movl %r8d, 0x54(%rsp)
movl %ecx, %r8d
movl 0x54(%rsp), %ecx
movb %r9b, %al
movl 0x298(%rsp), %r9d
movl 0x290(%rsp), %r9d
movb %r8b, 0x277(%rsp)
movq %rdi, 0x268(%rsp)
movl %esi, 0x264(%rsp)
movq %rdx, 0x258(%rsp)
andb $0x1, %cl
movb %cl, 0x257(%rsp)
andb $0x1, %al
movb %al, 0x... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::LanaiTTIImpl>::getOrderedReductionCost(unsigned int, llvm::VectorType*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getOrderedReductionCost(unsigned Opcode, VectorType *Ty,
TTI::TargetCostKind CostKind) {
// Targets must implement a default value for the scalable case, since
// we don't know how many lanes the vector has.
if (isa<ScalableVectorType>(Ty))
ret... | subq $0x108, %rsp # imm = 0x108
movq %rdi, 0xf0(%rsp)
movl %esi, 0xec(%rsp)
movq %rdx, 0xe0(%rsp)
movl %ecx, 0xdc(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x40(%rsp)
leaq 0xe0(%rsp), %rdi
callq 0x78e830
testb $0x1, %al
jne 0x1773545
jmp 0x1773580
xorl %eax, %eax
movl %eax, %edi
callq 0x78a450
movl %edx, 0xd0(%... | /llvm/CodeGen/BasicTTIImpl.h |
(anonymous namespace)::Filler::insertDefsUses(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::MachineInstr, true, true, void, false, void>, false, false>, llvm::SmallSet<unsigned int, 32u, std::less<unsigned int>>&, llvm::SmallSet<unsigned int, 32u, std::less<unsigned int>>&) | void Filler::insertDefsUses(MachineBasicBlock::instr_iterator MI,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) {
// If MI is a call or return, just examine the explicit non-variadic operands.
const MCInstrDesc &MCID = MI->getDesc();
unsi... | subq $0x98, %rsp
movq %rsi, 0x90(%rsp)
movq %rdi, 0x88(%rsp)
movq %rdx, 0x80(%rsp)
movq %rcx, 0x78(%rsp)
leaq 0x90(%rsp), %rdi
callq 0x76c240
movq %rax, %rdi
callq 0x7349e0
movq %rax, 0x70(%rsp)
leaq 0x90(%rsp), %rdi
callq 0x76c240
movq %rax, %rdi
movl $0x1, %esi
callq 0x734350
testb $0x1, %al
jne 0x1778bbc
leaq 0x90(%... | /Target/Lanai/LanaiDelaySlotFiller.cpp |
llvm::SmallSetIterator<unsigned int, 32u, std::less<unsigned int>>::SmallSetIterator(llvm::SmallSetIterator<unsigned int, 32u, std::less<unsigned int>>&&) | SmallSetIterator(SmallSetIterator &&Other) : isSmall(Other.isSmall) {
if (isSmall)
VecIter = std::move(Other.VecIter);
else
// Use placement new, to make sure SetIter is properly constructed, even
// if it is not trivially copy-able (e.g. in MSVC).
new (&SetIter) SetIterTy(std::move(Othe... | movq %rdi, -0x8(%rsp)
movq %rsi, -0x10(%rsp)
movq -0x8(%rsp), %rax
movq %rax, -0x18(%rsp)
movq -0x10(%rsp), %rcx
movb 0x8(%rcx), %cl
andb $0x1, %cl
movb %cl, 0x8(%rax)
testb $0x1, 0x8(%rax)
je 0x17794ea
movq -0x18(%rsp), %rax
movq -0x10(%rsp), %rcx
movq (%rcx), %rcx
movq %rcx, (%rax)
jmp 0x17794fa
movq -0x18(%rsp), %ra... | /llvm/ADT/SmallSet.h |
(anonymous namespace)::LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(llvm::SDValue const&, llvm::InlineAsm::ConstraintCode, std::vector<llvm::SDValue, std::allocator<llvm::SDValue>>&) | bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, AluOp;
switch (ConstraintCode) {
default:
return true;
case InlineAsm::ConstraintCode::m: // memory
if (!selectAddrRr(Op, Op0, Op1,... | subq $0x88, %rsp
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movl %edx, 0x6c(%rsp)
movq %rcx, 0x60(%rsp)
movq 0x78(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x50(%rsp), %rdi
callq 0x98b9c0
leaq 0x40(%rsp), %rdi
callq 0x98b9c0
leaq 0x30(%rsp), %rdi
callq 0x98b9c0
movl 0x6c(%rsp), %eax
subl $0x4, %eax
je 0x177cf6a
jmp 0x177c... | /Target/Lanai/LanaiISelDAGToDAG.cpp |
llvm::LanaiTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const | SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
case ISD::MUL:
return LowerMUL(Op, DAG);
case ISD::BR_CC:
return LowerBR_CC(Op, DAG);
case ISD::ConstantPool:
return LowerConstantPool(Op, DAG);
... | subq $0x208, %rsp # imm = 0x208
movq %rsi, 0x1e8(%rsp)
movl %edx, 0x1f0(%rsp)
movq %rdi, 0x1e0(%rsp)
movq %rcx, 0x1d8(%rsp)
movq 0x1e0(%rsp), %rax
movq %rax, (%rsp)
leaq 0x1e8(%rsp), %rdi
callq 0x98d4c0
movl %eax, %ecx
movl %ecx, 0xc(%rsp)
subl $0xd, %eax
je 0x1784873
jmp 0x1784690
movl 0xc(%rsp), %eax
subl ... | /Target/Lanai/LanaiISelLowering.cpp |
llvm::LanaiTargetLowering::LowerFormalArguments(llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&) const | SDValue LanaiTargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
switch (CallConv) {
case CallingConv::C:
case CallingConv::Fast:
retur... | pushq %rbx
subq $0x80, %rsp
movb %r8b, %al
movq 0xa0(%rsp), %r8
movq 0x98(%rsp), %r8
movq 0x90(%rsp), %r8
movq %rsi, 0x60(%rsp)
movl %edx, 0x68(%rsp)
movq %rdi, 0x58(%rsp)
movl %ecx, 0x54(%rsp)
andb $0x1, %al
movb %al, 0x53(%rsp)
movq %r9, 0x48(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x18(%rsp)
movl 0x54(%rsp), %eax
tes... | /Target/Lanai/LanaiISelLowering.cpp |
llvm::TargetTransformInfoImplCRTPBase<llvm::LoongArchTTIImpl>::getGEPCost(llvm::Type*, llvm::Value const*, llvm::ArrayRef<llvm::Value const*>, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
ArrayRef<const Value *> Operands, Type *AccessType,
TTI::TargetCostKind CostKind) {
assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
auto *BaseGV = dyn_cast<GlobalValue>(Ptr->st... | subq $0x1a8, %rsp # imm = 0x1A8
movl 0x1b0(%rsp), %eax
movq %rcx, 0x188(%rsp)
movq %r8, 0x190(%rsp)
movq %rdi, 0x180(%rsp)
movq %rsi, 0x178(%rsp)
movq %rdx, 0x170(%rsp)
movq %r9, 0x168(%rsp)
movq 0x180(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0x170(%rsp), %rdi
callq 0x316ee60
movq %rax, %rdi
callq 0x736cc0
mov... | /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::ArrayRef<llvm::CalleeSavedInfo>, llvm::TargetRegisterInfo const*) const | bool LoongArchFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
if (CSI.empty())
return true;
MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII = *MF->getSubtarget().g... | pushq %rbx
subq $0xe0, %rsp
movq %rdx, 0xd0(%rsp)
movq %rcx, 0xc0(%rsp)
movq %r8, 0xc8(%rsp)
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq %r9, 0xa8(%rsp)
leaq 0xc0(%rsp), %rdi
callq 0x93ae10
testb $0x1, %al
jne 0x17c537b
jmp 0x17c5388
movb $0x1, 0xdf(%rsp)
jmp 0x17c5578
movq 0xb0(%rsp), %rdi
callq 0x73fb50
movq %ra... | /Target/LoongArch/LoongArchFrameLowering.cpp |
llvm::LoongArchInstrInfo::loadRegFromStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void LoongArchInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DstReg, int FI,
const TargetRegisterClass *RC,
... | subq $0x148, %rsp # imm = 0x148
movl 0x158(%rsp), %eax
movq 0x150(%rsp), %r10
movq %rdx, 0x140(%rsp)
movl %ecx, 0x13c(%rsp)
movl %eax, 0x138(%rsp)
movq %rdi, 0x130(%rsp)
movq %rsi, 0x128(%rsp)
movl %r8d, 0x124(%rsp)
movq %r9, 0x118(%rsp)
movq 0x130(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x128(%rsp), %rdi
cal... | /Target/LoongArch/LoongArchInstrInfo.cpp |
llvm::LoongArchInstrInfo::removeBranch(llvm::MachineBasicBlock&, int*) const | unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
return 0;
if (!I->getDesc().isBranch())
return ... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movq 0x38(%rsp), %rax
movq %rax, (%rsp)
cmpq $0x0, 0x28(%rsp)
je 0x17c7d2f
movq 0x28(%rsp), %rax
movl $0x0, (%rax)
movq 0x30(%rsp), %rdi
movl $0x1, %esi
callq 0x33703f0
movq %rax, 0x20(%rsp)
movq 0x30(%rsp), %rdi
callq 0x73fef0
movq %rax... | /Target/LoongArch/LoongArchInstrInfo.cpp |
llvm::LoongArchInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::ArrayRef<llvm::MachineOperand>, llvm::DebugLoc const&, int*) const | unsigned LoongArchInstrInfo::insertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told ... | subq $0x128, %rsp # imm = 0x128
movq 0x138(%rsp), %rax
movq 0x130(%rsp), %rax
movq %r8, 0x110(%rsp)
movq %r9, 0x118(%rsp)
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
movq %rdx, 0xf8(%rsp)
movq %rcx, 0xf0(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x40(%rsp)
cmpq $0x0, 0x138(%rsp)
je 0x17c7f1d
movq 0x138(%rsp)... | /Target/LoongArch/LoongArchInstrInfo.cpp |
llvm::LoongArchInstrInfo::insertIndirectBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock&, llvm::MachineBasicBlock&, llvm::DebugLoc const&, long, llvm::RegScavenger*) const | void LoongArchInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &DestBB,
MachineBasicBlock &RestoreBB,
const DebugLoc &DL,
... | pushq %rbx
subq $0x260, %rsp # imm = 0x260
movq 0x270(%rsp), %rax
movq %rdi, 0x258(%rsp)
movq %rsi, 0x250(%rsp)
movq %rdx, 0x248(%rsp)
movq %rcx, 0x240(%rsp)
movq %r8, 0x238(%rsp)
movq %r9, 0x230(%rsp)
movq 0x258(%rsp), %rax
movq %rax, 0xa8(%rsp)
movq 0x250(%rsp), %rdi
callq 0x73fb50
movq %rax, 0x228(%rsp)
m... | /Target/LoongArch/LoongArchInstrInfo.cpp |
llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(llvm::IRBuilderBase&, llvm::AtomicRMWInst*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::AtomicOrdering) const | Value *LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(
IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
// In the case of an atomicrmw xchg with a constant 0/-1 operand, replace
// the atomic instruction with an Atom... | subq $0x3b8, %rsp # imm = 0x3B8
movl 0x3c8(%rsp), %eax
movq 0x3c0(%rsp), %rax
movq %rdi, 0x3a8(%rsp)
movq %rsi, 0x3a0(%rsp)
movq %rdx, 0x398(%rsp)
movq %rcx, 0x390(%rsp)
movq %r8, 0x388(%rsp)
movq %r9, 0x380(%rsp)
movq 0x3a8(%rsp), %rax
movq %rax, 0x100(%rsp)
movq 0x398(%rsp), %rdi
callq 0xa7d2a0
movl %eax, ... | /Target/LoongArch/LoongArchISelLowering.cpp |
lowerVECTOR_SHUFFLE_VILVL(llvm::SDLoc const&, llvm::ArrayRef<int>, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&) | static SDValue lowerVECTOR_SHUFFLE_VILVL(const SDLoc &DL, ArrayRef<int> Mask,
MVT VT, SDValue V1, SDValue V2,
SelectionDAG &DAG) {
const auto &Begin = Mask.begin();
const auto &End = Mask.end();
SDValue OriV1 = V1, OriV2 = V2;
i... | subq $0x128, %rsp # imm = 0x128
movb %cl, %al
movq 0x140(%rsp), %rcx
leaq 0x130(%rsp), %rcx
movq %rcx, 0x58(%rsp)
movq %rsi, 0x108(%rsp)
movq %rdx, 0x110(%rsp)
movb %al, 0x107(%rsp)
movq %r8, 0xf0(%rsp)
movl %r9d, 0xf8(%rsp)
movq %rdi, 0xe8(%rsp)
leaq 0x108(%rsp), %rdi
callq 0x78b010
movq %rax, 0xd8(%rsp)
le... | /Target/LoongArch/LoongArchISelLowering.cpp |
llvm::MipsAsmPrinter::emitPseudoIndirectBranch(llvm::MCStreamer&, llvm::MachineInstr const*) | void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
const MachineInstr *MI) {
bool HasLinkReg = false;
bool InMicroMipsMode = Subtarget->inMicroMipsMode();
MCInst TmpInst0;
if (Subtarget->hasMips64r6()) {
// MIPS64r6 should use (JALR64 ZERO_6... | subq $0xe8, %rsp
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
movq %rdx, 0xd0(%rsp)
movq 0xe0(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0xcf(%rsp)
movq 0x358(%rax), %rdi
callq 0x180e5d0
andb $0x1, %al
movb %al, 0xce(%rsp)
leaq 0x48(%rsp), %rdi
callq 0x43f950
movq 0x8(%rsp), %rax
movq 0x358(%rax), %rdi
callq 0x180e610
... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsAsmPrinter::EmitInstrRegReg(llvm::MCSubtargetInfo const&, unsigned int, unsigned int, unsigned int) | void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
unsigned Opcode, unsigned Reg1,
unsigned Reg2) {
MCInst I;
//
// Because of the current td files for Mips32, the operands for MTC1
// appear backwards from their normal asse... | subq $0xd8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movl %edx, 0xc4(%rsp)
movl %ecx, 0xc0(%rsp)
movl %r8d, 0xbc(%rsp)
movq 0xd0(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x38(%rsp), %rdi
callq 0x43f950
cmpl $0x891, 0xc4(%rsp) # imm = 0x891
jne 0x18112a5
movl 0xc0(%rsp), %eax
movl %eax, 0x34(%rsp)
movl 0xbc(%rsp), ... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsAsmPrinter::EmitFPCallStub(char const*, llvm::Mips16HardFloatInfo::FuncSignature const*) | void MipsAsmPrinter::EmitFPCallStub(
const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
using namespace Mips16HardFloatInfo;
MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
bool LE = getDataLayout().isLittleEndian();
// Construct a local MCSubtargetInfo here.
... | subq $0x528, %rsp # imm = 0x528
movq %rdi, 0x520(%rsp)
movq %rsi, 0x518(%rsp)
movq %rdx, 0x510(%rsp)
movq 0x520(%rsp), %rax
movq %rax, 0xa0(%rsp)
movq 0x48(%rax), %rax
movq %rax, 0x88(%rsp)
movq 0x518(%rsp), %rsi
leaq 0x4d0(%rsp), %rdi
movq %rdi, 0x80(%rsp)
callq 0x3ee9c0
movq 0x80(%rsp), %rsi
leaq 0x4e0(%rs... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::BasicTTIImplBase<llvm::MipsTTIImpl>::getScalarizationOverhead(llvm::VectorType*, llvm::ArrayRef<llvm::Value const*>, llvm::ArrayRef<llvm::Type*>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getScalarizationOverhead(VectorType *RetTy,
ArrayRef<const Value *> Args,
ArrayRef<Type *> Tys,
TTI::TargetCostKind CostKind) {
InstructionCost Cost = getScalarizationOver... | subq $0xc8, %rsp
movl 0xd0(%rsp), %eax
movq %rdx, 0xa8(%rsp)
movq %rcx, 0xb0(%rsp)
movq %r8, 0x98(%rsp)
movq %r9, 0xa0(%rsp)
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq 0x90(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x88(%rsp), %rsi
movl 0xd0(%rsp), %r8d
movl $0x1, %edx
xorl %ecx, %ecx
callq 0x1822710
movl %edx, 0x80(... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::MipsTTIImpl>::getOrderedReductionCost(unsigned int, llvm::VectorType*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getOrderedReductionCost(unsigned Opcode, VectorType *Ty,
TTI::TargetCostKind CostKind) {
// Targets must implement a default value for the scalable case, since
// we don't know how many lanes the vector has.
if (isa<ScalableVectorType>(Ty))
ret... | subq $0x108, %rsp # imm = 0x108
movq %rdi, 0xf0(%rsp)
movl %esi, 0xec(%rsp)
movq %rdx, 0xe0(%rsp)
movl %ecx, 0xdc(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x40(%rsp)
leaq 0xe0(%rsp), %rdi
callq 0x78e830
testb $0x1, %al
jne 0x182f575
jmp 0x182f5b0
xorl %eax, %eax
movl %eax, %edi
callq 0x78a450
movl %edx, 0xd0(%... | /llvm/CodeGen/BasicTTIImpl.h |
void llvm::SmallVectorTemplateBase<(anonymous namespace)::ReduceEntry, true>::uninitialized_copy<(anonymous namespace)::ReduceEntry const, (anonymous namespace)::ReduceEntry>((anonymous namespace)::ReduceEntry const*, (anonymous namespace)::ReduceEntry const*, (anonymous namespace)::ReduceEntry*, std::enable_if<std::is... | static void uninitialized_copy(
T1 *I, T1 *E, T2 *Dest,
std::enable_if_t<std::is_same<std::remove_const_t<T1>, T2>::value> * =
nullptr) {
// Use memcpy for PODs iterated by pointers (which includes SmallVector
// iterators): std::uninitialized_copy optimizes to memmove, but we can
// u... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq %rdx, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq 0x20(%rsp), %rax
cmpq 0x18(%rsp), %rax
je 0x1836cce
movq 0x10(%rsp), %rdi
movq 0x20(%rsp), %rsi
movq 0x18(%rsp), %rax
movq 0x20(%rsp), %rcx
subq %rcx, %rax
movl $0x28, %ecx
cqto
idivq %rcx
imulq $0x28, %rax, %rd... | /llvm/ADT/SmallVector.h |
llvm::MipsCallLowering::lowerReturn(llvm::MachineIRBuilder&, llvm::Value const*, llvm::ArrayRef<llvm::Register>, llvm::FunctionLoweringInfo&) const | bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<Register> VRegs,
FunctionLoweringInfo &FLI) const {
MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
if (Val != nullptr && !isSuppo... | subq $0xd48, %rsp # imm = 0xD48
movq %rcx, 0xd30(%rsp)
movq %r8, 0xd38(%rsp)
movq %rdi, 0xd28(%rsp)
movq %rsi, 0xd20(%rsp)
movq %rdx, 0xd18(%rsp)
movq %r9, 0xd10(%rsp)
movq 0xd28(%rsp), %rax
movq %rax, 0x58(%rsp)
movq 0xd20(%rsp), %rdi
movl $0x28f, %esi # imm = 0x28F
callq 0x3c44790
movq %rax, 0xd... | /Target/Mips/MipsCallLowering.cpp |
llvm::MipsCCState::PreAnalyzeReturnForVectorFloat(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&) | void MipsCCState::PreAnalyzeReturnForVectorFloat(
const SmallVectorImpl<ISD::OutputArg> &Outs) {
for (unsigned i = 0; i < Outs.size(); ++i) {
ISD::OutputArg Out = Outs[i];
OriginalRetWasFloatVector.push_back(
originalEVTTypeIsVectorFloat(Out.ArgVT));
}
} | subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x0, 0x64(%rsp)
movl 0x64(%rsp), %eax
movq %rax, 0x8(%rsp)
movq 0x68(%rsp), %rdi
callq 0x3a8dca0
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x1848fa5
movq 0x68(%rsp), %rdi
movl 0x64(%rsp), %eax
m... | /Target/Mips/MipsCCState.cpp |
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