name string | code string | asm string | file string |
|---|---|---|---|
(anonymous namespace)::MipsConstantIslands::fixupImmediateBr((anonymous namespace)::MipsConstantIslands::ImmBranch&) | bool MipsConstantIslands::fixupImmediateBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
unsigned TargetOperand = branchTargetOperand(MI);
MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB();
// Check to see if the DestBB is already in-range.
if (isBBInRange(MI, DestBB, Br.MaxDisp))
return fa... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rax
movq %rax, (%rsp)
movq 0x20(%rsp), %rax
movq (%rax), %rax
movq %rax, 0x18(%rsp)
movq 0x18(%rsp), %rdi
callq 0x1851f70
movl %eax, 0x14(%rsp)
movq 0x18(%rsp), %rdi
movl 0x14(%rsp), %esi
callq 0x73fa00
movq %rax, %rdi
callq 0x734c10
movq (%... | /Target/Mips/MipsConstantIslandPass.cpp |
(anonymous namespace)::MipsConstantIslands::createNewWater(unsigned int, unsigned int, llvm::MachineBasicBlock*&) | void MipsConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned UserOffset,
MachineBasicBlock *&NewMBB) {
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
MachineBasicBlock *User... | subq $0x138, %rsp # imm = 0x138
movq %rdi, 0x130(%rsp)
movl %esi, 0x12c(%rsp)
movl %edx, 0x128(%rsp)
movq %rcx, 0x120(%rsp)
movq 0x130(%rsp), %rdi
movq %rdi, 0x48(%rsp)
addq $0xa8, %rdi
movl 0x12c(%rsp), %eax
movl %eax, %esi
callq 0x184f620
movq %rax, 0x118(%rsp)
movq 0x118(%rsp), %rax
movq (%rax), %rax
movq... | /Target/Mips/MipsConstantIslandPass.cpp |
(anonymous namespace)::MipsConstantIslands::isBBInRange(llvm::MachineInstr*, llvm::MachineBasicBlock*, unsigned int) | bool MipsConstantIslands::isBBInRange
(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned MaxDisp) {
unsigned PCAdj = 4;
unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movl %ecx, 0x24(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movl $0x4, 0x20(%rsp)
movq 0x30(%rsp), %rsi
callq 0x1850690
movl %eax, %ecx
movq 0x8(%rsp), %rax
addl 0x20(%rsp), %ecx
movl %ecx, 0x1c(%rsp)
addq $0x38, %rax
movq %rax, 0x1... | /Target/Mips/MipsConstantIslandPass.cpp |
llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineInstr*>* llvm::DenseMapBase<llvm::SmallDenseMap<llvm::MachineBasicBlock*, llvm::MachineInstr*, 2u, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineInstr*>>, llvm::MachineBasicBlock*, l... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x18587b0
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x1857c50
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
void llvm::cl::parser<CompactBranchPolicy>::addLiteralOption<int>(llvm::StringRef, int const&, llvm::StringRef) | void addLiteralOption(StringRef Name, const DT &V, StringRef HelpStr) {
#ifndef NDEBUG
if (findOption(Name) != Values.size())
report_fatal_error("Option '" + Name + "' already exists!");
#endif
OptionInfo X(Name, static_cast<DataType>(V), HelpStr);
Values.push_back(X);
AddLiteralOption(Owner, Name... | subq $0x98, %rsp
movq %rsi, 0x88(%rsp)
movq %rdx, 0x90(%rsp)
movq %r8, 0x78(%rsp)
movq %r9, 0x80(%rsp)
movq %rdi, 0x70(%rsp)
movq %rcx, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, (%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x68(%rsp), %rax
movl (%rax), %ecx
movq ... | /llvm/Support/CommandLine.h |
llvm::cl::parser<CompactBranchPolicy>::OptionInfo const* llvm::SmallVectorTemplateCommon<llvm::cl::parser<CompactBranchPolicy>::OptionInfo, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<llvm::cl::parser<CompactBranchPolicy>::OptionInfo, false>>(llvm::SmallVectorTemplateBase<llvm::cl::parser<Comp... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dca0
addq 0x38(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dab0
movq %rax, %rcx
movq 0x18(%rsp), %rax
cmpq %rcx, %rax
ja 0x185a647
movq 0... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::MipsExpandPseudo::expandMBB(llvm::MachineBasicBlock&) | bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
Modified |= expandMI(MBB, MBBI, NMBBI);
MBBI = NMBBI;
}
return Modified;
} | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, (%rsp)
movb $0x0, 0x37(%rsp)
movq 0x38(%rsp), %rdi
callq 0x73fe80
movq %rax, 0x28(%rsp)
movq 0x38(%rsp), %rdi
callq 0x73fef0
movq %rax, 0x20(%rsp)
leaq 0x28(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x73fec0
testb $0x1, %al
jne ... | /Target/Mips/MipsExpandPseudo.cpp |
llvm::MachineInstr** llvm::SmallVectorImpl<llvm::MachineInstr*>::insert_one_impl<llvm::MachineInstr*>(llvm::MachineInstr**, llvm::MachineInstr*&&) | iterator insert_one_impl(iterator I, ArgType &&Elt) {
// Callers ensure that ArgType is derived from T.
static_assert(
std::is_same<std::remove_const_t<std::remove_reference_t<ArgType>>,
T>::value,
"ArgType must be derived from T!");
if (I == this->end()) { // Importan... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq 0x58(%rsp), %rdi
movq %rdi, 0x28(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x30(%rsp)
callq 0x7f0490
movq %rax, %rcx
movq 0x30(%rsp), %rax
cmpq %rcx, %rax
jne 0x1864c43
movq 0x28(%rsp), %rdi
movq 0x48(%rsp), %rax
movq (%rax), %rsi
call... | /llvm/ADT/SmallVector.h |
llvm::MipsTargetLowering::getNumRegistersForCallingConv(llvm::LLVMContext&, unsigned int, llvm::EVT) const | unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
CallingConv::ID CC,
EVT VT) const {
if (VT.isVector()) {
if (VT.isPow2VectorType() && VT.getVectorElementType().isR... | subq $0xc8, %rsp
movb %cl, %al
movb %al, 0xb0(%rsp)
movq %r8, 0xb8(%rsp)
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
movl %edx, 0x9c(%rsp)
movq 0xa8(%rsp), %rax
movq %rax, 0x30(%rsp)
leaq 0xb0(%rsp), %rdi
callq 0x7b92c0
testb $0x1, %al
jne 0x1873d92
jmp 0x1873ed7
leaq 0xb0(%rsp), %rdi
callq 0xa05fb0
movb %al, %cl
xorl ... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::lowerEH_RETURN(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
const {
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MipsFI->setCallsEhReturn();
SDValue Chain = Op.ge... | subq $0x2c8, %rsp # imm = 0x2C8
movq %rsi, 0x2a8(%rsp)
movl %edx, 0x2b0(%rsp)
movq %rdi, 0x2a0(%rsp)
movq %rcx, 0x298(%rsp)
movq 0x2a0(%rsp), %rax
movq %rax, 0x68(%rsp)
movq 0x298(%rsp), %rdi
callq 0x985ce0
movq %rax, 0x290(%rsp)
movq 0x290(%rsp), %rdi
callq 0x1808220
movq %rax, 0x288(%rsp)
movq 0x288(%rsp),... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::lowerShiftLeftParts(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
SDValue Shamt = Op.getOperand(2);
// if shamt < (VT.... | subq $0x608, %rsp # imm = 0x608
movq %rsi, 0x5e8(%rsp)
movl %edx, 0x5f0(%rsp)
movq %rdi, 0x5e0(%rsp)
movq %rcx, 0x5d8(%rsp)
movq 0x5e0(%rsp), %rax
movq %rax, 0x38(%rsp)
movups 0x5e8(%rsp), %xmm0
movaps %xmm0, 0x5b0(%rsp)
movq 0x5b0(%rsp), %rsi
movl 0x5b8(%rsp), %edx
leaq 0x5c8(%rsp), %rdi
movq %rdi, 0xf8(%rs... | /Target/Mips/MipsISelLowering.cpp |
llvm::SDValue llvm::MipsTargetLowering::getAddrNonPICSym64<llvm::GlobalAddressSDNode>(llvm::GlobalAddressSDNode*, llvm::SDLoc const&, llvm::EVT, llvm::SelectionDAG&) const | SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG) const {
SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
SDValue Highest =
DAG.getNode(MipsISD::Highest, DL, Ty,
... | subq $0x408, %rsp # imm = 0x408
movb %cl, %al
movb %al, 0x3e8(%rsp)
movq %r8, 0x3f0(%rsp)
movq %rdi, 0x3e0(%rsp)
movq %rsi, 0x3d8(%rsp)
movq %rdx, 0x3d0(%rsp)
movq %r9, 0x3c8(%rsp)
movq 0x3e0(%rsp), %rdi
movq %rdi, 0x38(%rsp)
movq 0x3d8(%rsp), %rsi
movups 0x3e8(%rsp), %xmm0
movaps %xmm0, 0x3a0(%rsp)
movq 0x3... | /Target/Mips/MipsISelLowering.h |
llvm::SDValue llvm::MipsTargetLowering::getAddrGlobalLargeGOT<llvm::GlobalAddressSDNode>(llvm::GlobalAddressSDNode*, llvm::SDLoc const&, llvm::EVT, llvm::SelectionDAG&, unsigned int, unsigned int, llvm::SDValue, llvm::MachinePointerInfo const&) const | SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG, unsigned HiFlag,
unsigned LoFlag, SDValue Chain,
const MachinePointerInfo &PtrInfo) const {
SDValue Hi = DAG.getNode(MipsISD::G... | pushq %rbx
subq $0x2b0, %rsp # imm = 0x2B0
movb %cl, %al
movq 0x2e0(%rsp), %rcx
leaq 0x2d0(%rsp), %rcx
movq %rcx, 0x80(%rsp)
movl 0x2c8(%rsp), %ecx
movl 0x2c0(%rsp), %ecx
movb %al, 0x290(%rsp)
movq %r8, 0x298(%rsp)
movq %rdi, 0x288(%rsp)
movq %rsi, 0x280(%rsp)
movq %rdx, 0x278(%rsp)
movq %r9, 0x270(%rsp)
mov... | /Target/Mips/MipsISelLowering.h |
llvm::MipsLegalizerInfo::legalizeCustom(llvm::LegalizerHelper&, llvm::MachineInstr&, llvm::LostDebugLocObserver&) const | bool MipsLegalizerInfo::legalizeCustom(
LegalizerHelper &Helper, MachineInstr &MI,
LostDebugLocObserver &LocObserver) const {
using namespace TargetOpcode;
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
const LLT s32 = LLT::scalar(32);
const LLT s6... | subq $0xa38, %rsp # imm = 0xA38
movq %rdi, 0xa28(%rsp)
movq %rsi, 0xa20(%rsp)
movq %rdx, 0xa18(%rsp)
movq %rcx, 0xa10(%rsp)
movq 0xa20(%rsp), %rax
movq (%rax), %rax
movq %rax, 0xa08(%rsp)
movq 0xa08(%rsp), %rdi
callq 0x800310
movq %rax, 0xa00(%rsp)
movl $0x20, %edi
callq 0x7f5450
movq %rax, 0x9f8(%rsp)
movl ... | /Target/Mips/MipsLegalizerInfo.cpp |
(anonymous namespace)::ExpandPseudo::expandBuildPairF64(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, bool) const | bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
bool FP64) const {
// For fpxx and when mthc1 is not available, use:
// spill + reload via ldc1
//
// The case where dmtc1 is available doesn... | pushq %rbx
subq $0xc0, %rsp
movb %cl, %al
movq %rdx, 0xb0(%rsp)
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
andb $0x1, %al
movb %al, 0x9f(%rsp)
movq 0xa8(%rsp), %rax
movq %rax, 0x38(%rsp)
leaq 0xb0(%rsp), %rdi
callq 0x73ff20
movq %rax, %rdi
callq 0x732d60
movl %eax, %ecx
xorl %eax, %eax
cmpl $0x4, %ecx
movb %al, 0x43(%... | /Target/Mips/MipsSEFrameLowering.cpp |
llvm::MipsSEInstrInfo::storeRegToStack(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, long) const | void MipsSEInstrInfo::
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
int64_t Offset) const {
DebugLoc DL;
MachineMemOperand *MMO = GetMemOperan... | subq $0x288, %rsp # imm = 0x288
movb %r8b, %al
movq 0x2a0(%rsp), %r8
movq 0x298(%rsp), %r8
movq 0x290(%rsp), %r8
movq %rdx, 0x280(%rsp)
movl %ecx, 0x27c(%rsp)
movq %rdi, 0x270(%rsp)
movq %rsi, 0x268(%rsp)
andb $0x1, %al
movb %al, 0x267(%rsp)
movl %r9d, 0x260(%rsp)
movq 0x270(%rsp), %rax
movq %rax, 0xc0(%rsp)... | /Target/Mips/MipsSEInstrInfo.cpp |
llvm::MipsSEDAGToDAGISel::selectVSplatMaskL(llvm::SDValue, llvm::SDValue&) const | bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
APInt ImmValue;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0);
if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
ImmValue.getBitWidth() == Elt... | subq $0x1b8, %rsp # imm = 0x1B8
movq %rsi, 0x1a0(%rsp)
movl %edx, 0x1a8(%rsp)
movq %rdi, 0x198(%rsp)
movq %rcx, 0x190(%rsp)
movq 0x198(%rsp), %rax
movq %rax, 0x40(%rsp)
leaq 0x180(%rsp), %rdi
callq 0x40b580
leaq 0x1a0(%rsp), %rdi
callq 0x988cf0
movq %rax, %rdi
xorl %esi, %esi
callq 0x97c3d0
movb %al, 0x160(%... | /Target/Mips/MipsSEISelDAGToDAG.cpp |
llvm::MipsSETargetLowering::lowerLOAD(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadSDNode &Nd = *cast<LoadSDNode>(Op);
if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
return MipsTargetLowering::lowerLOAD(Op, DAG);
// Replace a double precision load with two i32 loads and a buildpair64.
SDLoc DL(Op);
... | pushq %r14
pushq %rbx
subq $0x3d8, %rsp # imm = 0x3D8
movq %rsi, 0x3b8(%rsp)
movl %edx, 0x3c0(%rsp)
movq %rdi, 0x3b0(%rsp)
movq %rcx, 0x3a8(%rsp)
movq 0x3b0(%rsp), %rax
movq %rax, 0xc0(%rsp)
leaq 0x3b8(%rsp), %rdi
callq 0x9e3ef0
movq %rax, 0x3a0(%rsp)
movq 0x3a0(%rsp), %rdi
callq 0x98ac30
movb %al, 0x390(%rs... | /Target/Mips/MipsSEISelLowering.cpp |
llvm::MipsSETargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue
MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
SDValue Val;
switch (N->getOpcode()) {
case ISD::AND:
Val = performANDCombine(N, DAG, DCI, Subtarget);
break;
case ISD::OR:
Val = performORCombine(N, DAG, DCI, Subtarget);
bre... | subq $0x148, %rsp # imm = 0x148
movq %rdi, 0x130(%rsp)
movq %rsi, 0x128(%rsp)
movq %rdx, 0x120(%rsp)
movq 0x130(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x120(%rsp), %rax
movq 0x10(%rax), %rax
movq %rax, 0x118(%rsp)
leaq 0x108(%rsp), %rdi
callq 0x98b9c0
movq 0x128(%rsp), %rdi
callq 0x97c400
movl %eax, %ecx
movl... | /Target/Mips/MipsSEISelLowering.cpp |
llvm::MipsSETargetLowering::emitLD_F16_PSEUDO(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
MachineBasicBlock *BB) const {
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
Register Wd = ... | subq $0x1c8, %rsp # imm = 0x1C8
movq %rdi, 0x1c0(%rsp)
movq %rsi, 0x1b8(%rsp)
movq %rdx, 0x1b0(%rsp)
movq 0x1c0(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0x4e0f8(%rax), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x1a8(%rsp)
movq 0x1b0(%rsp), %rdi
callq 0x73fb50
movq %rax, %rdi
callq 0x73cca0
movq %rax,... | /Target/Mips/MipsSEISelLowering.cpp |
llvm::MipsSETargetLowering::emitFPROUND_PSEUDO(llvm::MachineInstr&, llvm::MachineBasicBlock*, bool) const | MachineBasicBlock *
MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
MachineBasicBlock *BB,
bool IsFGR64) const {
// Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
// here. It's technically doable to ... | subq $0x368, %rsp # imm = 0x368
movb %cl, %al
movq %rdi, 0x360(%rsp)
movq %rsi, 0x358(%rsp)
movq %rdx, 0x350(%rsp)
andb $0x1, %al
movb %al, 0x34f(%rsp)
movq 0x360(%rsp), %rax
movq %rax, 0xe0(%rsp)
movq 0x4e0f8(%rax), %rdi
callq 0x1814930
movb %al, %cl
xorl %eax, %eax
testb $0x1, %cl
movb %al, 0xeb(%rsp)
jne ... | /Target/Mips/MipsSEISelLowering.cpp |
llvm::Mips16InstrInfo::restoreFrame(unsigned int, long, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
MachineFunction *MF = MBB.getParent();
MachineFrameI... | subq $0x148, %rsp # imm = 0x148
movq %r8, 0x140(%rsp)
movq %rdi, 0x138(%rsp)
movl %esi, 0x134(%rsp)
movq %rdx, 0x128(%rsp)
movq %rcx, 0x120(%rsp)
movq 0x138(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x120(%rsp), %rdi
callq 0x73fef0
movq %rax, 0x110(%rsp)
leaq 0x140(%rsp), %rdi
leaq 0x110(%rsp), %rsi
callq 0x73f... | /Target/Mips/Mips16InstrInfo.cpp |
llvm::Mips16TargetLowering::emitSelT16(unsigned int, unsigned int, llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
// To "insert" a... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x228(%rsp)
movl %esi, 0x224(%rsp)
movl %edx, 0x220(%rsp)
movq %rcx, 0x218(%rsp)
movq %r8, 0x210(%rsp)
movq 0x228(%rsp), %rax
movq %rax, 0x90(%rsp)
leaq 0x7e61a04(%rip), %rdi # 0x976e778
addq $0x80, %rdi
callq 0x3f1b60
testb $0x1, %al
jne 0x190cd86
jmp 0x190cd9b
m... | /Target/Mips/Mips16ISelLowering.cpp |
(anonymous namespace)::MipsFastISel::computeAddress(llvm::Value const*, (anonymous namespace)::MipsFastISel::Address&) | bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
const User *U = nullptr;
unsigned Opcode = Instruction::UserOp1;
if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
// Don't walk into other basic blocks unless the object is an alloca from
// another block, otherwise it may not ha... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x158(%rsp)
movq %rsi, 0x150(%rsp)
movq %rdx, 0x148(%rsp)
movq 0x158(%rsp), %rax
movq %rax, 0x30(%rsp)
movq $0x0, 0x140(%rsp)
movl $0x3a, 0x13c(%rsp)
movq 0x150(%rsp), %rdi
callq 0x78c230
movq %rax, 0x130(%rsp)
cmpq $0x0, 0x130(%rsp)
je 0x1918b18
movq 0x30(%rsp), %r... | /Target/Mips/MipsFastISel.cpp |
(anonymous namespace)::MipsFastISel::emitIntSExt(llvm::MVT, unsigned int, llvm::MVT, unsigned int) | bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
return false;
if (Subtarget->hasMips32r2())
return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
return emitIntSExt32r1(SrcVT, SrcR... | subq $0x28, %rsp
movb %cl, %al
movb %sil, %cl
movb %cl, 0x26(%rsp)
movb %al, 0x25(%rsp)
movq %rdi, 0x18(%rsp)
movl %edx, 0x14(%rsp)
movl %r8d, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
leaq 0xf(%rsp), %rdi
movl $0x7, %esi
callq 0x5345c0
leaq 0x25(%rsp), %rdi
leaq 0xf(%rsp), %rsi
callq 0x7ad500
movb %al, %cl
xo... | /Target/Mips/MipsFastISel.cpp |
(anonymous namespace)::MSP430BSel::measureFunction(llvm::SmallVector<int, 16u>&, llvm::MachineBasicBlock*) | unsigned MSP430BSel::measureFunction(OffsetVector &BlockOffsets,
MachineBasicBlock *FromBB) {
// Give the blocks of the function a dense, in-order, numbering.
MF->RenumberBlocks(FromBB);
MachineFunction::iterator Begin;
if (FromBB == nullptr) {
Begin = MF->begin();
} ... | subq $0xc8, %rsp
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x38(%rax), %rdi
movq 0xb0(%rsp), %rsi
callq 0x3400c80
leaq 0xa8(%rsp), %rdi
callq 0xe52d50
cmpq $0x0, 0xb0(%rsp)
jne 0x19349fd
movq 0x28(%rsp), %rax
movq 0x38(%rax), %rdi
callq 0x7edfc0
m... | /Target/MSP430/MSP430BranchSelector.cpp |
(anonymous namespace)::MSP430DAGToDAGISel::SelectAddr(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
SDValue &Base, SDValue &Disp) {
MSP430ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
if (AM.BaseType == MSP430ISelAddressMode::RegBase)
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(MSP43... | subq $0x308, %rsp # imm = 0x308
movq %rsi, 0x2f0(%rsp)
movl %edx, 0x2f8(%rsp)
movq %rdi, 0x2e8(%rsp)
movq %rcx, 0x2e0(%rsp)
movq %r8, 0x2d8(%rsp)
movq 0x2e8(%rsp), %rax
movq %rax, 0x98(%rsp)
leaq 0x288(%rsp), %rdi
callq 0x19379c0
movq 0x98(%rsp), %rdi
movq 0x2f0(%rsp), %rax
movq %rax, 0x278(%rsp)
movq 0x2f8(... | /Target/MSP430/MSP430ISelDAGToDAG.cpp |
void llvm::cl::parser<llvm::MSP430Subtarget::HWMultEnum>::addLiteralOption<int>(llvm::StringRef, int const&, llvm::StringRef) | void addLiteralOption(StringRef Name, const DT &V, StringRef HelpStr) {
#ifndef NDEBUG
if (findOption(Name) != Values.size())
report_fatal_error("Option '" + Name + "' already exists!");
#endif
OptionInfo X(Name, static_cast<DataType>(V), HelpStr);
Values.push_back(X);
AddLiteralOption(Owner, Name... | subq $0x98, %rsp
movq %rsi, 0x88(%rsp)
movq %rdx, 0x90(%rsp)
movq %r8, 0x78(%rsp)
movq %r9, 0x80(%rsp)
movq %rdi, 0x70(%rsp)
movq %rcx, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, (%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x68(%rsp), %rax
movl (%rax), %ecx
movq ... | /llvm/Support/CommandLine.h |
llvm::MSP430TargetLowering::LowerGlobalAddress(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
EVT PtrVT = Op.getValueType();
// Create the ... | subq $0x138, %rsp # imm = 0x138
movq %rsi, 0x118(%rsp)
movl %edx, 0x120(%rsp)
movq %rdi, 0x110(%rsp)
movq %rcx, 0x108(%rsp)
leaq 0x118(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0xa1a070
movq %rax, %rdi
callq 0x997eb0
movq 0x10(%rsp), %rdi
movq %rax, 0x100(%rsp)
callq 0xa1a070
movq %rax, %rdi
callq 0x997ec0
mov... | /Target/MSP430/MSP430ISelLowering.cpp |
llvm::NVPTXAsmPrinter::lowerToMCInst(llvm::MachineInstr const*, llvm::MCInst&) | void NVPTXAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
OutMI.setOpcode(MI->getOpcode());
// Special: Do not mangle symbol operand of CALL_PROTOTYPE
if (MI->getOpcode() == NVPTX::CALL_PROTOTYPE) {
const MachineOperand &MO = MI->getOperand(0);
OutMI.addOperand(GetSymbolRef(
OutCo... | subq $0xc8, %rsp
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0xb0(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0xb8(%rsp), %rdi
callq 0x72bbb0
movq 0x20(%rsp), %rdi
movl %eax, %esi
callq 0x43f990
movq 0xb8(%rsp), %rdi
callq 0x72bbb0
cmpl $0x168, %eax ... | /Target/NVPTX/NVPTXAsmPrinter.cpp |
llvm::NVPTXAsmPrinter::encodeVirtualRegister(unsigned int) | unsigned NVPTXAsmPrinter::encodeVirtualRegister(unsigned Reg) {
if (Register::isVirtualRegister(Reg)) {
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC];
unsigned RegNum = RegMap[Reg];
// Encode the register class in the upper 4 bits
/... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movl %esi, 0x34(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x34(%rsp), %edi
callq 0x745010
testb $0x1, %al
jne 0x194c7d9
jmp 0x194c927
movq 0x8(%rsp), %rax
movq 0x348(%rax), %rax
movq %rax, (%rsp)
movl 0x34(%rsp), %esi
leaq 0x24(%rsp), %rdi
callq 0x72e210
movq (%rsp), %... | /Target/NVPTX/NVPTXAsmPrinter.cpp |
llvm::NVPTXAsmPrinter::printReturnValStr(llvm::Function const*, llvm::raw_ostream&) | void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
const DataLayout &DL = getDataLayout();
const NVPTXSubtarget &STI = TM.getSubtarget<NVPTXSubtarget>(*F);
const auto *TLI = cast<NVPTXTargetLowering>(STI.getTargetLowering());
Type *Ty = F->getReturnType();
bool isABI = (STI.getSmVe... | subq $0x298, %rsp # imm = 0x298
movq %rdi, 0x290(%rsp)
movq %rsi, 0x288(%rsp)
movq %rdx, 0x280(%rsp)
movq 0x290(%rsp), %rdi
movq %rdi, 0x40(%rsp)
callq 0x3c61840
movq %rax, %rcx
movq 0x40(%rsp), %rax
movq %rcx, 0x278(%rsp)
movq 0x38(%rax), %rdi
movq 0x288(%rsp), %rsi
callq 0x194d0f0
movq %rax, 0x270(%rsp)
mo... | /Target/NVPTX/NVPTXAsmPrinter.cpp |
llvm::detail::DenseSetPair<llvm::GlobalVariable const*>* llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable const*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable const*>>, llvm::GlobalVariable const*, llvm::detail::DenseSetEmpty, ... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x1957d40
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x1957050
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::TargetRegisterClass const*, llvm::DenseMap<unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>>, llvm::DenseMapInfo<llvm::TargetRegisterClass const*, void>, llvm::detail::DenseMapPair<llvm::TargetRegisterClass... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x1959b70
cmpl $0x0, %eax
jne 0x1959ac2
jmp 0x1959b62
callq 0x1959b80
movq %rax, 0x28(%rsp)
callq 0x1959b90
movq 0x8(%rsp), %rdi
movq %rax, 0x20(%rsp)
callq 0x1959ba0
movq 0x8(%rsp), %rdi
movq %rax, 0x18(%rsp)
callq 0x1959bb0
movq %... | /llvm/ADT/DenseMap.h |
PromoteScalarIntegerPTX(llvm::EVT const&, llvm::MVT*) | static bool PromoteScalarIntegerPTX(const EVT &VT, MVT *PromotedVT) {
if (VT.isScalarInteger()) {
switch (PowerOf2Ceil(VT.getFixedSizeInBits())) {
default:
llvm_unreachable(
"Promotion is not suitable for scalars of size larger than 64-bits");
case 1:
*PromotedVT = MVT::i1;
bre... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq 0x48(%rsp), %rdi
callq 0xa7f9c0
testb $0x1, %al
jne 0x196b601
jmp 0x196b708
movq 0x48(%rsp), %rdi
callq 0x7ac2a0
movq %rax, %rdi
callq 0x5710b0
decq %rax
movq %rax, 0x8(%rsp)
movq 0x8(%rsp), %rax
leaq 0x52b27bd(%rip), %rcx # 0x6c1dde4
movslq (%rcx,%rax... | /Target/NVPTX/NVPTXISelLowering.cpp |
PerformREMCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&, llvm::CodeGenOptLevel) | static SDValue PerformREMCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
CodeGenOptLevel OptLevel) {
assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
// Don't do anything at less than -O2.
if (OptLevel < CodeGenOptLevel... | subq $0x198, %rsp # imm = 0x198
movq %rdi, 0x180(%rsp)
movq %rsi, 0x178(%rsp)
movl %edx, 0x174(%rsp)
cmpl $0x2, 0x174(%rsp)
jge 0x197ee3e
leaq 0x188(%rsp), %rdi
xorl %esi, %esi
movl $0x10, %edx
callq 0x348990
leaq 0x188(%rsp), %rdi
callq 0x98b9c0
jmp 0x197f1fe
movq 0x178(%rsp), %rax
movq 0x10(%rax), %rax
mov... | /Target/NVPTX/NVPTXISelLowering.cpp |
llvm::DenseMapIterator<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::GlobalVariable*, llvm::sys::SmartMutex<false>>>, llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::GlobalVari... | iterator find_as(const LookupKeyT &Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*this,... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x28(%rsp), %rsi
leaq 0x20(%rsp), %rdx
callq 0x19bdee0
testb $0x1, %al
jne 0x19bde5d
jmp 0x19bdebb
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x19ba080
testb $0x1, %al
jne 0x19bde72
jmp 0x19bde83
movq 0x... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorTemplateBase<bool, true>::growAndAssign(unsigned long, bool) | void growAndAssign(size_t NumElts, T Elt) {
// Elt has been copied in case it's an internal reference, side-stepping
// reference invalidation problems without losing the realloc optimization.
this->set_size(0);
this->grow(NumElts);
std::uninitialized_fill_n(this->begin(), NumElts, Elt);
this->s... | subq $0x28, %rsp
movb %dl, %al
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %eax, %eax
movl %eax, %esi
callq 0x3a8e020
movq 0x8(%rsp), %rdi
movq 0x18(%rsp), %rsi
callq 0x104f8e0
movq 0x8(%rsp), %rdi
callq 0x1048120
movq %rax, %rdi
movq 0... | /llvm/ADT/SmallVector.h |
llvm::NVPTXInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool) const | void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
const MachineRegisterInfo &MRI = MBB.getParent()->... | subq $0x118, %rsp # imm = 0x118
movb 0x120(%rsp), %al
movq %rdx, 0x110(%rsp)
movl %r8d, 0x10c(%rsp)
movl %r9d, 0x108(%rsp)
movq %rdi, 0x100(%rsp)
movq %rsi, 0xf8(%rsp)
movq %rcx, 0xf0(%rsp)
andb $0x1, %al
movb %al, 0xef(%rsp)
movq 0x100(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0xf8(%rsp), %rdi
callq 0x73fb50
m... | /Target/NVPTX/NVPTXInstrInfo.cpp |
(anonymous namespace)::NVPTXLowerUnreachable::isLoweredToTrap(llvm::UnreachableInst const&) const | bool NVPTXLowerUnreachable::isLoweredToTrap(const UnreachableInst &I) const {
if (!TrapUnreachable)
return false;
if (!NoTrapAfterNoreturn)
return true;
const CallInst *Call = dyn_cast_or_null<CallInst>(I.getPrevNode());
return Call && Call->doesNotReturn();
} | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x10(%rsp)
testb $0x1, 0x1c(%rax)
jne 0x19dce05
movb $0x0, 0x37(%rsp)
jmp 0x19dce58
movq 0x10(%rsp), %rax
testb $0x1, 0x1d(%rax)
jne 0x19dce17
movb $0x1, 0x37(%rsp)
jmp 0x19dce58
movq 0x20(%rsp), %rdi
addq $0x18, %rdi
callq 0x... | /Target/NVPTX/NVPTXLowerUnreachable.cpp |
(anonymous namespace)::NVPTXReplaceImageHandles::runOnMachineFunction(llvm::MachineFunction&) | bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
InstrsToRemove.clear();
for (MachineBasicBlock &MBB : MF)
for (MachineInstr &MI : MBB)
Changed |= processInstr(MI);
// Now clean up any handle-access instructions
// This is needed in debug mode when c... | subq $0xa8, %rsp
movq %rdi, 0xa0(%rsp)
movq %rsi, 0x98(%rsp)
movq 0xa0(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movb $0x0, 0x97(%rsp)
addq $0x38, %rdi
callq 0xd2f680
movq 0x98(%rsp), %rax
movq %rax, 0x88(%rsp)
movq 0x88(%rsp), %rdi
callq 0x7edfc0
movq %rax, 0x80(%rsp)
movq 0x88(%rsp), %rdi
callq 0x7edff0
movq %rax, 0x78(%rsp)
... | /Target/NVPTX/NVPTXReplaceImageHandles.cpp |
llvm::PPCRegisterInfo::lowerPrepareProbedAlloca(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | void PPCRegisterInfo::lowerPrepareProbedAlloca(
MachineBasicBlock::iterator II) const {
MachineInstr &MI = *II;
// Get the instruction's basic block.
MachineBasicBlock &MBB = *MI.getParent();
// Get the basic block's function.
MachineFunction &MF = *MBB.getParent();
const PPCSubtarget &Subtarget = MF.ge... | subq $0x128, %rsp # imm = 0x128
movq %rsi, 0x120(%rsp)
movq %rdi, 0x118(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x18(%rsp)
leaq 0x120(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x110(%rsp)
movq 0x110(%rsp), %rdi
callq 0x73fb40
movq %rax, 0x108(%rsp)
movq 0x108(%rsp), %rdi
callq 0x73fb50
movq %rax, 0x100(%rsp)
mov... | /Target/PowerPC/PPCRegisterInfo.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [35], llvm::cl::desc, llvm::cl::OptionHidden>(char const (&) [35], llvm::cl::desc const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x3f7700
movq 0x8(%rsp), %rsi
leaq 0x7be0f38(%rip), %rax # 0x96df180
addq $0x10... | /llvm/Support/CommandLine.h |
llvm::PPCTargetLowering::getNegatedExpression(llvm::SDValue, llvm::SelectionDAG&, bool, bool, llvm::TargetLoweringBase::NegatibleCost&, unsigned int) const | SDValue PPCTargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
bool LegalOps, bool OptForSize,
NegatibleCost &Cost,
unsigned Depth) const {
if (Depth > Select... | subq $0x328, %rsp # imm = 0x328
movl %r8d, 0x44(%rsp)
movq %rcx, %rax
movl 0x44(%rsp), %ecx
movq %rax, 0x48(%rsp)
movl %edx, %eax
movq 0x48(%rsp), %rdx
movl %eax, 0x54(%rsp)
movq %rsi, %r8
movl 0x54(%rsp), %esi
movb %r9b, %al
movl 0x338(%rsp), %r9d
movq 0x330(%rsp), %r9
movq %r8, 0x308(%rsp)
movl %esi, 0x310... | /Target/PowerPC/PPCISelLowering.cpp |
isBLACompatibleAddress(llvm::SDValue, llvm::SelectionDAG&) | static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return nullptr;
int Addr = C->getZExtValue();
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
SignExtend32<26>(Addr) != Addr)
return nullptr; // Top 6 bits have... | subq $0xc8, %rsp
movq %rdi, 0xb0(%rsp)
movl %esi, 0xb8(%rsp)
movq %rdx, 0xa8(%rsp)
leaq 0xb0(%rsp), %rdi
callq 0x996090
movq %rax, 0xa0(%rsp)
cmpq $0x0, 0xa0(%rsp)
jne 0x1b9117f
movq $0x0, 0xc0(%rsp)
jmp 0x1b912c5
movq 0xa0(%rsp), %rdi
callq 0x98b8c0
movl %eax, 0x9c(%rsp)
movl 0x9c(%rsp), %eax
andl $0x3, %eax
cmpl $0x0... | /Target/PowerPC/PPCISelLowering.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::SDNode*, llvm::EVT, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::EVT>>, llvm::SDNode*, llvm::EVT, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::EVT>>::LookupBucketFor<llvm::SDNode const*>(... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x1b98080
movq 0x18(%rsp), %rdi
movq %rax, 0x50(%rsp)
callq 0x1b97aa0
movl %eax, 0x4c(%rsp)
cmpl $0x0, 0x4c(%rsp)
jne 0x1b98762
movq 0x58(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x77(%rs... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::PPCLoopInstrFormPrep::chainCommoning(llvm::Loop*, llvm::SmallVector<(anonymous namespace)::Bucket, 16u>&) | bool PPCLoopInstrFormPrep::chainCommoning(Loop *L,
SmallVector<Bucket, 16> &Buckets) {
bool MadeChange = false;
if (Buckets.empty())
return MadeChange;
SmallSet<BasicBlock *, 16> BBChanged;
for (auto &Bucket : Buckets) {
if (prepareBasesForCommoningChains(Buc... | subq $0x128, %rsp # imm = 0x128
movq %rdi, 0x118(%rsp)
movq %rsi, 0x110(%rsp)
movq %rdx, 0x108(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x107(%rsp)
movq 0x108(%rsp), %rdi
callq 0x3a8dce0
testb $0x1, %al
jne 0x1bbf2b7
jmp 0x1bbf2cc
movb 0x107(%rsp), %al
andb $0x1, %al
movb %al, 0x127(%rsp)... | /Target/PowerPC/PPCLoopInstrFormPrep.cpp |
(anonymous namespace)::PPCLoopInstrFormPrep::prepareBaseForUpdateFormChain((anonymous namespace)::Bucket&) | bool PPCLoopInstrFormPrep::prepareBaseForUpdateFormChain(Bucket &BucketChain) {
// We have a choice now of which instruction's memory operand we use as the
// base for the generated PHI. Always picking the first instruction in each
// bucket does not work well, specifically because that instruction might
// be ... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x8(%rsp)
movl $0x0, 0x44(%rsp)
movq 0x48(%rsp), %rdi
addq $0x8, %rdi
callq 0x3a8dca0
movl %eax, 0x40(%rsp)
movl 0x44(%rsp), %eax
cmpl 0x40(%rsp), %eax
je 0x1bc1b99
movq 0x48(%rsp), %rdi
addq $0x8, %rdi
movslq 0x44(%rsp), %rsi... | /Target/PowerPC/PPCLoopInstrFormPrep.cpp |
emitVFROUND_NOEXCEPT_MASK(llvm::MachineInstr&, llvm::MachineBasicBlock*, unsigned int) | static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
MachineBasicBlock *BB,
unsigned CVTXOpc) {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getI... | subq $0x2f8, %rsp # imm = 0x2F8
movq %rdi, 0x2f0(%rsp)
movq %rsi, 0x2e8(%rsp)
movl %edx, 0x2e4(%rsp)
movq 0x2f0(%rsp), %rdi
callq 0x73ff30
movq %rax, %rsi
leaq 0x2d8(%rsp), %rdi
callq 0x740150
movq 0x2e8(%rsp), %rdi
callq 0x73fb50
movq %rax, %rdi
callq 0x73c170
movq %rax, %rdi
movq (%rdi), %rax
callq *0x80(%... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::CanLowerReturn(unsigned int, llvm::MachineFunction&, bool, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, llvm::LLVMContext&) const | bool RISCVTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
RVVArgDispatcher Dispatcher{&MF,... | pushq %r14
pushq %rbx
subq $0x458, %rsp # imm = 0x458
movb %cl, %al
movq %rdi, 0x448(%rsp)
movl %esi, 0x444(%rsp)
movq %rdx, 0x438(%rsp)
andb $0x1, %al
movb %al, 0x437(%rsp)
movq %r8, 0x428(%rsp)
movq %r9, 0x420(%rsp)
movq 0x448(%rsp), %rax
movq %rax, 0x48(%rsp)
leaq 0x290(%rsp), %rdi
callq 0x7f5b30
movl 0x4... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::emitLeadingFence(llvm::IRBuilderBase&, llvm::Instruction*, llvm::AtomicOrdering) const | Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
Instruction *Inst,
AtomicOrdering Ord) const {
if (Subtarget.hasStdExtZtso()) {
if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::Sequent... | subq $0xc8, %rsp
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq %rdx, 0xa8(%rsp)
movl %ecx, 0xa4(%rsp)
movq 0xb8(%rsp), %rax
movq 0x4e0f8(%rax), %rdi
callq 0x1c44980
testb $0x1, %al
jne 0x1d85d20
jmp 0x1d85d9c
leaq 0xa8(%rsp), %rdi
callq 0x7caac0
testb $0x1, %al
jne 0x1d85d33
jmp 0x1d85d8b
cmpl $0x7, 0xa4(%rsp)
jne 0... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::emitTrailingFence(llvm::IRBuilderBase&, llvm::Instruction*, llvm::AtomicOrdering) const | Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
Instruction *Inst,
AtomicOrdering Ord) const {
if (Subtarget.hasStdExtZtso()) {
if (isa<StoreInst>(Inst) && Ord == AtomicOrdering::Seq... | subq $0xc8, %rsp
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq %rdx, 0xa8(%rsp)
movl %ecx, 0xa4(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x4e0f8(%rax), %rdi
callq 0x1c44980
testb $0x1, %al
jne 0x1d85ed5
jmp 0x1d85f51
leaq 0xa8(%rsp), %rdi
callq 0x7caae0
testb $0x1, %al
jne 0x1d85ee8
jmp 0x1d85f40
cmpl ... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(llvm::IRBuilderBase&, llvm::AtomicRMWInst*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::AtomicOrdering) const | Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
// In the case of an atomicrmw xchg with a constant 0/-1 operand, replace
// the atomic instruction with an AtomicRM... | subq $0x3b8, %rsp # imm = 0x3B8
movl 0x3c8(%rsp), %eax
movq 0x3c0(%rsp), %rax
movq %rdi, 0x3a8(%rsp)
movq %rsi, 0x3a0(%rsp)
movq %rdx, 0x398(%rsp)
movq %rcx, 0x390(%rsp)
movq %r8, 0x388(%rsp)
movq %r9, 0x380(%rsp)
movq 0x3a8(%rsp), %rax
movq %rax, 0x100(%rsp)
movq 0x398(%rsp), %rdi
callq 0xa7d2a0
movl %eax, ... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(llvm::IRBuilderBase&, llvm::AtomicCmpXchgInst*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::Value*, llvm::AtomicOrdering) const | Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
unsigned XLen = Subtarget.getXLen();
Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
... | subq $0x218, %rsp # imm = 0x218
movl 0x228(%rsp), %eax
movq 0x220(%rsp), %rax
movq %rdi, 0x210(%rsp)
movq %rsi, 0x208(%rsp)
movq %rdx, 0x200(%rsp)
movq %rcx, 0x1f8(%rsp)
movq %r8, 0x1f0(%rsp)
movq %r9, 0x1e8(%rsp)
movq 0x210(%rsp), %rax
movq 0x4e0f8(%rax), %rdi
callq 0x1be8810
movl %eax, 0x1e4(%rsp)
movq 0x2... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(llvm::SelectionDAG&, llvm::SDLoc const&, llvm::SDValue const*, unsigned int, llvm::MVT, llvm::EVT, std::optional<unsigned int>) const | SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
... | subq $0x328, %rsp # imm = 0x328
movq 0x340(%rsp), %rax
leaq 0x330(%rsp), %r10
movq %r10, 0x70(%rsp)
movb %r9b, 0x30f(%rsp)
movq %rax, 0x304(%rsp)
movq %rdi, 0x2f8(%rsp)
movq %rsi, 0x2f0(%rsp)
movq %rdx, 0x2e8(%rsp)
movq %rcx, 0x2e0(%rsp)
movl %r8d, 0x2dc(%rsp)
leaq 0x304(%rsp), %rdi
callq 0xcd0610
andb $0x1,... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::isLegalStridedLoadStore(llvm::EVT, llvm::Align) const | bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
Align Alignment) const {
if (!Subtarget.hasVInstructions())
return false;
// Only support fixed vectors if we know the minimum vector size.
if (DataType.isFixedLengthVector() && !Subtarget.useRVV... | subq $0x88, %rsp
movb %cl, %al
movb %sil, %cl
movb %cl, 0x70(%rsp)
movq %rdx, 0x78(%rsp)
movb %al, 0x6f(%rsp)
movq %rdi, 0x60(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x4e0f8(%rax), %rdi
callq 0x1c047c0
testb $0x1, %al
jne 0x1d8a315
movb $0x0, 0x87(%rsp)
jmp 0x1d8a417
leaq 0x70(%rsp), %rdi
callq 0x7abaf0
... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore(llvm::IntrinsicInst*, llvm::StoreInst*) const | bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
StoreInst *SI) const {
assert(SI->isSimple());
IRBuilder<> Builder(SI);
// Only interleave2 supported at present.
if (II->getIntrinsicID() != Intrinsic::vector_interleave2)
... | subq $0x248, %rsp # imm = 0x248
movq %rdi, 0x238(%rsp)
movq %rsi, 0x230(%rsp)
movq %rdx, 0x228(%rsp)
movq 0x238(%rsp), %rax
movq %rax, 0x50(%rsp)
movq 0x228(%rsp), %rax
movq %rax, 0x58(%rsp)
leaq 0x188(%rsp), %rdi
callq 0x7b2080
movq 0x58(%rsp), %rsi
movq 0x188(%rsp), %rcx
movq 0x190(%rsp), %r8
leaq 0x198(%r... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::SmallVectorImpl<llvm::RVVArgDispatcher::RVVArgInfo>::insert(llvm::RVVArgDispatcher::RVVArgInfo*, unsigned long, llvm::RVVArgDispatcher::RVVArgInfo) | iterator insert(iterator I, size_type NumToInsert, ValueParamT Elt) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(NumToInsert, Elt);
return this->be... | subq $0x98, %rsp
movq %rcx, 0x88(%rsp)
movq %rdi, 0x80(%rsp)
movq %rsi, 0x78(%rsp)
movq %rdx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x78(%rsp), %rax
movq %rax, 0x20(%rsp)
callq 0x1c40540
movq 0x18(%rsp), %rdi
movq %rax, %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
sarq $0x3, %rax
movq %rax, 0x68(%rs... | /llvm/ADT/SmallVector.h |
lowerVECTOR_SHUFFLEAsRotate(llvm::ShuffleVectorSDNode*, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDLoc DL(SVN);
EVT VT = SVN->getValueType(0);
unsigned RotateAmt;
MVT RotateVT;
if (!isLegalBitRotat... | subq $0x228, %rsp # imm = 0x228
movq %rdi, 0x210(%rsp)
movq %rsi, 0x208(%rsp)
movq %rdx, 0x200(%rsp)
movq 0x210(%rsp), %rsi
leaq 0x1f0(%rsp), %rdi
callq 0x9817d0
movq 0x210(%rsp), %rdi
xorl %esi, %esi
callq 0x97c3d0
movb %al, 0x1e0(%rsp)
movq %rdx, 0x1e8(%rsp)
leaq 0x1db(%rsp), %rdi
callq 0xa1fa70
movq 0x210... | /Target/RISCV/RISCVISelLowering.cpp |
isDeinterleaveShuffle(llvm::MVT, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, llvm::RISCVSubtarget const&) | static bool isDeinterleaveShuffle(MVT VT, MVT ContainerVT, SDValue V1,
SDValue V2, ArrayRef<int> Mask,
const RISCVSubtarget &Subtarget) {
// Need to be able to widen the vector.
if (VT.getScalarSizeInBits() >= Subtarget.getELen())
return false;... | subq $0x88, %rsp
movb %sil, %al
movb %dil, %sil
movq 0xa0(%rsp), %rdi
leaq 0x90(%rsp), %rdi
movq %rdi, 0x28(%rsp)
movb %sil, 0x86(%rsp)
movb %al, 0x85(%rsp)
movq %rdx, 0x70(%rsp)
movl %ecx, 0x78(%rsp)
movq %r8, 0x60(%rsp)
movl %r9d, 0x68(%rsp)
leaq 0x86(%rsp), %rdi
callq 0x534d70
movq %rax, 0x30(%rsp)
movq 0xa0(%rsp), ... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::SmallVectorImpl<llvm::EVT>::assign(unsigned long, llvm::EVT) | void assign(size_type NumElts, ValueParamT Elt) {
// Note that Elt could be an internal reference.
if (NumElts > this->capacity()) {
this->growAndAssign(NumElts, Elt);
return;
}
// Assign over existing elements.
std::fill_n(this->begin(), std::min(NumElts, this->size()), Elt);
if (N... | subq $0x78, %rsp
movb %dl, %al
movb %al, 0x68(%rsp)
movq %rcx, 0x70(%rsp)
movq %rdi, 0x60(%rsp)
movq %rsi, 0x58(%rsp)
movq 0x60(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x38(%rsp)
callq 0x3a8dab0
movq %rax, %rcx
movq 0x38(%rsp), %rax
cmpq %rcx, %rax
jbe 0x1d9ac83
movq 0x30(%rsp), %rdi
movq 0x5... | /llvm/ADT/SmallVector.h |
EmitLoweredCascadedSelect(llvm::MachineInstr&, llvm::MachineInstr&, llvm::MachineBasicBlock*, llvm::RISCVSubtarget const&) | static MachineBasicBlock *
EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
MachineBasicBlock *ThisMBB,
const RISCVSubtarget &Subtarget) {
// Select_FPRX_ (rs1, rs2, imm, rs4, (Select_FPRX_ rs1, rs2, imm, rs4, rs5)
// Without this, custom-inser... | subq $0x2a8, %rsp # imm = 0x2A8
movq %rdi, 0x2a0(%rsp)
movq %rsi, 0x298(%rsp)
movq %rdx, 0x290(%rsp)
movq %rcx, 0x288(%rsp)
movq 0x288(%rsp), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x280(%rsp)
movq 0x2a0(%rsp), %rdi
callq 0x73ff30
movq %rax, 0x278(%rsp)
movq 0x290(%rsp), %rdi
callq 0x9112f0
movq... | /Target/RISCV/RISCVISelLowering.cpp |
(anonymous namespace)::RISCVMoveMerge::mergeMoveSARegPair(llvm::MachineBasicBlock&) | bool RISCVMoveMerge::mergeMoveSARegPair(MachineBasicBlock &MBB) {
bool Modified = false;
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
MBBI != E;) {
// Check if the instruction can be compressed to C.MV instruction. If it
// can, return Dest/Src register pair.
auto RegPair ... | subq $0x88, %rsp
movq %rdi, 0x80(%rsp)
movq %rsi, 0x78(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x18(%rsp)
movb $0x0, 0x77(%rsp)
movq 0x78(%rsp), %rdi
callq 0x73fe80
movq %rax, 0x68(%rsp)
movq 0x78(%rsp), %rdi
callq 0x73fef0
movq %rax, 0x60(%rsp)
leaq 0x68(%rsp), %rdi
leaq 0x60(%rsp), %rsi
callq 0x73fec0
testb $0x1, %al
... | /Target/RISCV/RISCVMoveMerger.cpp |
(anonymous namespace)::RISCVMoveMerge::findMatchingInst(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int, llvm::DestSourcePair const&) | MachineBasicBlock::iterator
RISCVMoveMerge::findMatchingInst(MachineBasicBlock::iterator &MBBI,
unsigned InstOpcode,
const DestSourcePair &RegPair) {
MachineBasicBlock::iterator E = MBBI->getParent()->end();
// Track which register units have been m... | subq $0xd8, %rsp
movq %rdi, 0xc8(%rsp)
movq %rsi, 0xc0(%rsp)
movl %edx, 0xbc(%rsp)
movq %rcx, 0xb0(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0xc0(%rsp), %rdi
callq 0x73ff20
movq %rax, %rdi
callq 0x73fb40
movq %rax, %rdi
callq 0x73fef0
movq 0x38(%rsp), %rdi
movq %rax, 0xa8(%rsp)
addq $0x48, %rdi
callq 0x91b... | /Target/RISCV/RISCVMoveMerger.cpp |
(anonymous namespace)::RISCVPushPopOpt::adjustRetVal(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&) | bool RISCVPushPopOpt::adjustRetVal(MachineBasicBlock::iterator &MBBI) {
MachineBasicBlock::reverse_iterator RE = MBBI->getParent()->rend();
// Track which register units have been modified and used between the POP
// insn and the last assignment to register a0.
ModifiedRegUnits.clear();
UsedRegUnits.clear();
... | subq $0x88, %rsp
movq %rdi, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x78(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x70(%rsp), %rdi
callq 0x73ff20
movq %rax, %rdi
callq 0x73fb40
movq %rax, %rdi
callq 0x8c83b0
movq 0x8(%rsp), %rdi
movq %rax, 0x68(%rsp)
addq $0x48, %rdi
callq 0x91b410
movq 0x8(%rsp), %rdi
addq $0x98, %rdi
call... | /Target/RISCV/RISCVPushPopOptimizer.cpp |
llvm::InsertNOPLoad::~InsertNOPLoad() | class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
public:
static char ID;
InsertNOPLoad();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after "
"e... | pushq %rax
movq %rdi, (%rsp)
movq (%rsp), %rdi
callq 0x1dc32c0
popq %rax
retq
| /Target/Sparc/LeonPasses.h |
llvm::SparcTargetLowering::getConstraintType(llvm::StringRef) const | SparcTargetLowering::ConstraintType
SparcTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'r':
case 'f':
case 'e':
return C_RegisterClass;
case 'I': // SIMM13
return C_Immediate;
}
}
... | subq $0x48, %rsp
movq %rsi, 0x30(%rsp)
movq %rdx, 0x38(%rsp)
movq %rdi, 0x28(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x3f3670
cmpq $0x1, %rax
jne 0x1debd6a
xorl %eax, %eax
movl %eax, %esi
leaq 0x30(%rsp), %rdi
callq 0x412900
movsbl %al, %eax
movl %eax, 0xc(%rsp)
subl $0x49, %eax
je... | /Target/Sparc/SparcISelLowering.cpp |
llvm::SparcTargetLowering::getSingleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo&, char const*) const | TargetLowering::ConstraintWeight SparcTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo &info,
const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but a... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp)
movl $0xffffffff, 0x24(%rsp) # imm = 0xFFFFFFFF
movq 0x30(%rsp), %rax
movq 0x78(%rax), %rax
movq %rax, 0x18(%rsp)
cmpq $0x0, 0x18(%rsp)
jne 0x1debde5
movl $0x0, 0x44(%rsp)
jmp 0x1debe53
movq 0x2... | /Target/Sparc/SparcISelLowering.cpp |
printFormattedRegName(llvm::MCAsmInfo const*, unsigned int, llvm::raw_ostream&) | static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
raw_ostream &OS) {
const char *RegName = SystemZInstPrinter::getRegisterName(RegNo);
if (MAI->getAssemblerDialect() == AD_HLASM) {
// Skip register prefix so that only register number is left
assert(isa... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq %rdx, 0x10(%rsp)
movl 0x1c(%rsp), %esi
leaq 0x4(%rsp), %rdi
callq 0x40c480
movl 0x4(%rsp), %edi
callq 0x28ac400
movq %rax, 0x8(%rsp)
movq 0x20(%rsp), %rdi
callq 0x6aed70
cmpl $0x1, %eax
jne 0x1dfedb2
movq 0x10(%rsp), %rdi
movq 0x8(%rsp), %rsi
addq $0x1, ... | /Target/SystemZ/SystemZAsmPrinter.cpp |
llvm::SystemZInstrInfo::getBranchInfo(llvm::MachineInstr const&) const | SystemZII::Branch
SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
case SystemZ::BR:
case SystemZ::BI:
case SystemZ::J:
case SystemZ::JG:
return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
SystemZ::CCMASK_ANY, &MI.ge... | subq $0x48, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, 0x28(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x38(%rsp), %rdi
callq 0x72bbb0
movl %eax, %ecx
movl %ecx, 0x34(%rsp)
subl $0x2, %eax
je 0x1e07973
jmp 0x1e07663
movl 0x34(%rsp), %eax
subl $0x269, %eax # imm = 0x269
je 0x1e0776f
jmp 0x1e07674
movl ... | /Target/SystemZ/SystemZInstrInfo.cpp |
(anonymous namespace)::SystemZTDCPass::convertICmp(llvm::CmpInst&) | void SystemZTDCPass::convertICmp(CmpInst &I) {
Value *Op0 = I.getOperand(0);
auto *Const = dyn_cast<ConstantInt>(I.getOperand(1));
auto Pred = I.getPredicate();
// All our icmp rules involve comparisons with consts.
if (!Const)
return;
if (auto *Cast = dyn_cast<BitCastInst>(Op0)) {
// Check for icmp... | subq $0xa8, %rsp
movq %rdi, 0xa0(%rsp)
movq %rsi, 0x98(%rsp)
movq 0xa0(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x98(%rsp), %rdi
xorl %esi, %esi
callq 0x7d7fb0
movq %rax, 0x90(%rsp)
movq 0x98(%rsp), %rdi
movl $0x1, %esi
callq 0x7d7fb0
movq %rax, %rdi
callq 0x7829c0
movq %rax, 0x88(%rsp)
movq 0x98(%rsp), %rdi
callq 0x78a99... | /Target/SystemZ/SystemZTDC.cpp |
llvm::DenseMap<llvm::Instruction*, unsigned int, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, unsigned int>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
movl 0x10(%rdi), %eax
movl %eax, 0x1c(%rsp)
movl 0x8(%rdi), %eax
movl %eax, 0x18(%rsp)
callq 0xc3aa90
movl $0x0, 0x14(%rsp)
cmpl $0x0, 0x18(%rsp)
je 0x1e36b1a
movl $0x40, 0x10(%rsp)
movl 0x18(%rsp), %edi
callq 0x91b7e0
movl %eax, %ecx
addl $... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SystemZElimCompare::fuseCompareOperations(llvm::MachineInstr&, llvm::SmallVectorImpl<llvm::MachineInstr*>&) | bool SystemZElimCompare::fuseCompareOperations(
MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
// See whether we have a single branch with which to fuse.
if (CCUsers.size() != 1)
return false;
MachineInstr *Branch = CCUsers[0];
SystemZII::FusedCompareType Type;
switch (Branch->getO... | subq $0x118, %rsp # imm = 0x118
movq %rdi, 0x108(%rsp)
movq %rsi, 0x100(%rsp)
movq %rdx, 0xf8(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0xf8(%rsp), %rdi
callq 0x3a8dca0
cmpq $0x1, %rax
je 0x1e3aa6c
movb $0x0, 0x117(%rsp)
jmp 0x1e3b0a5
movq 0xf8(%rsp), %rdi
xorl %eax, %eax
movl %eax, %esi
callq ... | /Target/SystemZ/SystemZElimCompare.cpp |
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo&, char const*) const | TargetLowering::ConstraintWeight SystemZTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo &info,
const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but... | subq $0x78, %rsp
movq %rdi, 0x68(%rsp)
movq %rsi, 0x60(%rsp)
movq %rdx, 0x58(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0xffffffff, 0x54(%rsp) # imm = 0xFFFFFFFF
movq 0x60(%rsp), %rax
movq 0x78(%rax), %rax
movq %rax, 0x48(%rsp)
cmpq $0x0, 0x48(%rsp)
jne 0x1e520e8
movl $0x0, 0x74(%rsp)
jmp 0x1e52320
movq 0x... | /Target/SystemZ/SystemZISelLowering.cpp |
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(llvm::TargetRegisterInfo const*, llvm::StringRef, llvm::MVT) const | std::pair<unsigned, const TargetRegisterClass *>
SystemZTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
// GCC Constraint Letters
switch (Constraint[0]) {
default: break;
case 'd': // Data register (eq... | subq $0x2b8, %rsp # imm = 0x2B8
movb %r8b, %al
movq %rdx, 0x298(%rsp)
movq %rcx, 0x2a0(%rsp)
movb %al, 0x297(%rsp)
movq %rdi, 0x288(%rsp)
movq %rsi, 0x280(%rsp)
movq 0x288(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x298(%rsp), %rdi
callq 0x3f3670
cmpq $0x1, %rax
jne 0x1e5298f
xorl %eax, %eax
movl %eax, %esi
leaq... | /Target/SystemZ/SystemZISelLowering.cpp |
emitCmp(llvm::SelectionDAG&, llvm::SDLoc const&, (anonymous namespace)::Comparison&) | static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
if (!C.Op1.getNode()) {
SDNode *Node;
switch (C.Op0.getOpcode()) {
case ISD::INTRINSIC_W_CHAIN:
Node = emitIntrinsicWithCCAndChain(DAG, C.Op0, C.Opcode);
return SDValue(Node, 0);
case ISD::INTRINSIC_WO_CHAIN:
... | subq $0x348, %rsp # imm = 0x348
movq %rdi, 0x330(%rsp)
movq %rsi, 0x328(%rsp)
movq %rdx, 0x320(%rsp)
movq 0x320(%rsp), %rdi
addq $0x10, %rdi
callq 0x981890
cmpq $0x0, %rax
jne 0x1e5e9e2
movq 0x320(%rsp), %rdi
callq 0x98d4c0
subl $0x2e, %eax
je 0x1e5e958
jmp 0x1e5e8ee
movq 0x330(%rsp), %rdi
movq 0x320(%rsp), ... | /Target/SystemZ/SystemZISelLowering.cpp |
llvm::SystemZTargetLowering::combineSIGN_EXTEND(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue SystemZTargetLowering::combineSIGN_EXTEND(
SDNode *N, DAGCombinerInfo &DCI) const {
// Convert (sext (ashr (shl X, C1), C2)) to
// (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
// cheap as narrower ones.
SelectionDAG &DAG = DCI.DAG;
SDValue N0 = N->getOperand(0);
EVT VT = N->getV... | subq $0x338, %rsp # imm = 0x338
movq %rdi, 0x320(%rsp)
movq %rsi, 0x318(%rsp)
movq %rdx, 0x310(%rsp)
movq 0x310(%rsp), %rax
movq 0x10(%rax), %rax
movq %rax, 0x308(%rsp)
movq 0x318(%rsp), %rdi
xorl %esi, %esi
callq 0x981ab0
movq (%rax), %rcx
movq %rcx, 0x2f8(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x300(%rsp)
m... | /Target/SystemZ/SystemZISelLowering.cpp |
llvm::SystemZTargetLowering::combineFP_ROUND(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue SystemZTargetLowering::combineFP_ROUND(
SDNode *N, DAGCombinerInfo &DCI) const {
if (!Subtarget.hasVector())
return SDValue();
// (fpround (extract_vector_elt X 0))
// (fpround (extract_vector_elt X 1)) ->
// (extract_vector_elt (VROUND X) 0)
// (extract_vector_elt (VROUND X) 2)
//
// Th... | subq $0x538, %rsp # imm = 0x538
movq %rdi, 0x520(%rsp)
movq %rsi, 0x518(%rsp)
movq %rdx, 0x510(%rsp)
movq 0x520(%rsp), %rax
movq 0x4e0f8(%rax), %rdi
callq 0x1dfca80
testb $0x1, %al
jne 0x1e84c4d
leaq 0x528(%rsp), %rdi
xorl %esi, %esi
movl $0x10, %edx
callq 0x348990
leaq 0x528(%rsp), %rdi
callq 0x98b9c0
jmp 0... | /Target/SystemZ/SystemZISelLowering.cpp |
combineCCMask(llvm::SDValue&, int&, int&) | static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
// We have a SELECT_CCMASK or BR_CCMASK comparing the condition code
// set by the CCReg instruction using the CCValid / CCMask masks,
// If the CCReg instruction is itself a ICMP testing the condition
// code set by some other instruction, ... | subq $0x98, %rsp
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq 0x80(%rsp), %rax
cmpl $0xe, (%rax)
je 0x1e88766
movb $0x0, 0x97(%rsp)
jmp 0x1e88b3c
movq 0x88(%rsp), %rdi
callq 0x981890
movq %rax, 0x70(%rsp)
movq 0x70(%rsp), %rdi
callq 0x97c400
cmpl $0x1ed, %eax # imm = 0x1ED
je 0x1e88... | /Target/SystemZ/SystemZISelLowering.cpp |
adjustZeroCmp(llvm::SelectionDAG&, llvm::SDLoc const&, (anonymous namespace)::Comparison&) | static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
if (C.ICmpType == SystemZICMP::UnsignedOnly)
return;
auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
if (!ConstOp1 || ConstOp1->getValueSizeInBits(0) > 64)
return;
int64_t Value = ConstOp1->getSExtValue();
if ... | subq $0x98, %rsp
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq %rdx, 0x80(%rsp)
movq 0x80(%rsp), %rax
cmpl $0x1, 0x34(%rax)
jne 0x1e9d402
jmp 0x1e9d58c
movq 0x80(%rsp), %rdi
addq $0x10, %rdi
callq 0x981890
movq %rax, %rdi
callq 0xa89ca0
movq %rax, 0x78(%rsp)
movb $0x1, %al
cmpq $0x0, 0x78(%rsp)
movb %al, 0x1f(%rsp)
... | /Target/SystemZ/SystemZISelLowering.cpp |
getSingleSchedPred(llvm::MachineBasicBlock*, llvm::MachineLoop const*) | static MachineBasicBlock *getSingleSchedPred(MachineBasicBlock *MBB,
const MachineLoop *Loop) {
MachineBasicBlock *PredMBB = nullptr;
if (MBB->pred_size() == 1)
PredMBB = *MBB->pred_begin();
// The loop header has two predecessors, return the latch, but not for a
... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq $0x0, 0x40(%rsp)
movq 0x50(%rsp), %rdi
callq 0x8fe290
cmpl $0x1, %eax
jne 0x1ea6057
movq 0x50(%rsp), %rdi
callq 0x91de90
movq %rax, 0x38(%rsp)
leaq 0x38(%rsp), %rdi
callq 0x8ff670
movq (%rax), %rax
movq %rax, 0x40(%rsp)
movq 0x50(%rsp), %rdi
callq 0x8fe2... | /Target/SystemZ/SystemZMachineScheduler.cpp |
emitLEAzzi(llvm::MCStreamer&, llvm::MCOperand&, llvm::MCOperand&, llvm::MCSubtargetInfo const&) | static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD,
const MCSubtargetInfo &STI) {
MCInst LEAInst;
LEAInst.setOpcode(VE::LEAzii);
LEAInst.addOperand(RD);
MCOperand CZero = MCOperand::createImm(0);
LEAInst.addOperand(CZero);
LEAInst.addOperand(CZero);
LEAIns... | subq $0xf8, %rsp
movq %rdi, 0xf0(%rsp)
movq %rsi, 0xe8(%rsp)
movq %rdx, 0xe0(%rsp)
movq %rcx, 0xd8(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x43f950
leaq 0x58(%rsp), %rdi
movl $0x302, %esi # imm = 0x302
callq 0x43f990
movq 0xe0(%rsp), %rax
movq (%rax), %rcx
movq %rcx, 0x48(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x50... | /Target/VE/VEAsmPrinter.cpp |
(anonymous namespace)::VEAsmPrinter::printOperand(llvm::MachineInstr const*, int, llvm::raw_ostream&) | void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
break;
case Machi... | subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movl %edx, 0x64(%rsp)
movq %rcx, 0x58(%rsp)
movq 0x68(%rsp), %rdi
movl 0x64(%rsp), %esi
callq 0x72c4d0
movq %rax, 0x50(%rsp)
movq 0x50(%rsp), %rdi
callq 0x7333f0
movzbl %al, %ecx
testb %al, %al
je 0x1ec1e3f
jmp 0x1ec1e3d
jmp 0x1ec1eb1
movq 0x58(%rsp), %rdi
le... | /Target/VE/VEAsmPrinter.cpp |
llvm::isMImmVal(unsigned long) | inline static bool isMImmVal(uint64_t Val) {
if (Val == 0) {
// (0)1 is 0
return true;
}
if (isMask_64(Val)) {
// (m)0 patterns
return true;
}
// (m)1 patterns
return (Val & (UINT64_C(1) << 63)) && isShiftedMask_64(Val);
} | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
cmpq $0x0, 0x8(%rsp)
jne 0x1edd4a8
movb $0x1, 0x17(%rsp)
jmp 0x1edd4f2
movq 0x8(%rsp), %rdi
callq 0x472670
testb $0x1, %al
jne 0x1edd4b8
jmp 0x1edd4bf
movb $0x1, 0x17(%rsp)
jmp 0x1edd4f2
movabsq $-0x8000000000000000, %rcx # imm = 0x8000000000000000
andq 0x8(%rsp), %rcx
xorl %eax, %... | /Target/VE/VE.h |
llvm::VEInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const | bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
MachineBasicBlock::iterator I = MBB.getLastNonDebug... | subq $0x98, %rsp
movb %r9b, %al
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq %r8, 0x68(%rsp)
andb $0x1, %al
movb %al, 0x67(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x80(%rsp), %rdi
movl $0x1, %esi
callq 0x33703f0
movq %rax, 0x58(%rsp)
movq 0x80(%rsp), %rdi
ca... | /Target/VE/VEInstrInfo.cpp |
llvm::VETargetLowering::shouldExpandAtomicRMWInIR(llvm::AtomicRMWInst*) const | TargetLowering::AtomicExpansionKind
VETargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// We have TS1AM implementation for i8/i16/i32/i64, so use it.
if (AI->getOperation() == AtomicRMWInst::Xchg) {
return AtomicExpansionKind::None;
}
// FIXME: Support "ATMAM" instruction for LOAD_ADD/SU... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq %rsi, (%rsp)
movq (%rsp), %rdi
callq 0xa7d2a0
cmpl $0x0, %eax
jne 0x1ef4f75
movl $0x0, 0x14(%rsp)
jmp 0x1ef4f7d
movl $0x4, 0x14(%rsp)
movl 0x14(%rsp), %eax
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
| /Target/VE/VEISelLowering.cpp |
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(llvm::SDValue, llvm::SelectionDAG&) const | SDValue VETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
MVT VT = Op.getOperand(0).getSimpleValueType();
// Special treatment for packed V64 types.
assert(VT... | subq $0x598, %rsp # imm = 0x598
movq %rsi, 0x570(%rsp)
movl %edx, 0x578(%rsp)
movq %rdi, 0x568(%rsp)
movq %rcx, 0x560(%rsp)
leaq 0x570(%rsp), %rdi
movq %rdi, 0x30(%rsp)
xorl %esi, %esi
movl %esi, 0xb4(%rsp)
callq 0x98cd00
movq %rax, %rdi
callq 0x9dc070
movq 0x30(%rsp), %rdi
movl 0xb4(%rsp), %esi
movb %al, 0x... | /Target/VE/VEISelLowering.cpp |
std::pair<llvm::DenseMapIterator<llvm::MCSymbol*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseSetPair<llvm::MCSymbol*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::De... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | subq $0x88, %rsp
movq %rdi, 0x20(%rsp)
movq %rdi, 0x28(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x30(%rsp)
movq 0x78(%rsp), %rsi
leaq 0x68(%rsp), %rdx
callq 0x19f5d00
testb $0x1, %al
jne 0x1f19fa5
jmp 0x1f1a01f
movq 0x68(%rsp), %rax
movq %rax, 0x18(%rsp)
c... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::StringRef, unsigned int, llvm::DenseMapInfo<llvm::StringRef, void>, llvm::detail::DenseMapPair<llvm::StringRef, unsigned int>>, llvm::StringRef, unsigned int, llvm::DenseMapInfo<llvm::StringRef, void>, llvm::detail::DenseMapPair<llvm::StringRef, unsigned int>>::makeIterator(llvm:... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0x571890
testb $0x1, %al
jne 0x1f1b9f6
jmp 0x1f1ba62
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%r... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::WebAssemblyCFGStackify::placeMarkers(llvm::MachineFunction&) | void WebAssemblyCFGStackify::placeMarkers(MachineFunction &MF) {
// We allocate one more than the number of blocks in the function to
// accommodate for the possible fake block we may insert at the end.
ScopeTops.resize(MF.getNumBlockIDs() + 1);
// Place the LOOP for MBB if MBB is the header of a loop.
for (a... | subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x8(%rsp)
addq $0x38, %rax
movq %rax, 0x10(%rsp)
movq 0x68(%rsp), %rdi
callq 0x9519e0
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, %eax
movl %eax, %esi
callq 0x1f48e50
movq 0x68(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0x60(... | /Target/WebAssembly/WebAssemblyCFGStackify.cpp |
llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, llvm::MachineInstr*>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::MachineInstr*, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, llvm::MachineInstr*>>, llvm::Machin... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x548460
movq 0x10(%rsp), %rdi
callq 0x1f479c0
movq 0x10(%rsp), %rdi
addl $0x1, %eax
movl %eax, 0x24(%rsp)
callq 0x1f470f0
movl %eax, 0x20(%rsp)
movl 0x24(%rsp), %ea... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void... | inline iterator begin() {
// When the map is empty, avoid the overhead of advancing/retreating past
// empty buckets.
if (empty())
return end();
if (shouldReverseIterate<KeyT>())
return makeIterator(getBucketsEnd() - 1, getBuckets(), *this);
return makeIterator(getBuckets(), getBucketsEn... | subq $0x38, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0x1f512d0
testb $0x1, %al
jne 0x1f5131e
jmp 0x1f51337
movq 0x18(%rsp), %rdi
callq 0x1f513d0
movq %rax, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
jmp 0x1f513be
callq 0xd63750
testb $0x1, %al
jne 0x1f51342
jmp 0x1f51383
movq 0x18(%rsp), %rdi
... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, false>::DenseMapIterator(llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>*, llvm::d... | DenseMapIterator(pointer Pos, pointer E, const DebugEpochBase &Epoch,
bool NoAdvance = false)
: DebugEpochBase::HandleBase(&Epoch), Ptr(Pos), End(E) {
assert(isHandleInSync() && "invalid construction!");
if (NoAdvance) return;
if (shouldReverseIterate<KeyT>()) {
RetreatPastEm... | subq $0x38, %rsp
movb %r8b, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
andb $0x1, %al
movb %al, 0x17(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x5481a0
movq 0x8(%rsp), %rax
movq 0x28(%rsp), %rcx
movq %rcx, (%rax)
movq 0x20(%rsp), %rcx
m... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::WebAssemblyCFGStackify::getBranchDepth(llvm::SmallVectorImpl<std::pair<llvm::MachineBasicBlock const*, llvm::MachineInstr const*>> const&, llvm::MachineBasicBlock const*) | unsigned WebAssemblyCFGStackify::getBranchDepth(
const SmallVectorImpl<EndMarkerInfo> &Stack, const MachineBasicBlock *MBB) {
unsigned Depth = 0;
for (auto X : reverse(Stack)) {
if (X.first == MBB)
break;
++Depth;
}
assert(Depth < Stack.size() && "Branch destination should be in scope");
ret... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movl $0x0, 0x3c(%rsp)
movq 0x48(%rsp), %rsi
leaq 0x20(%rsp), %rdi
callq 0x1f52560
leaq 0x20(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rsi
leaq 0x18(%rsp), %rdi
callq 0x1f525c0
movq 0x30(%rsp), %rsi
leaq 0x10(%rsp), %rdi
callq 0... | /Target/WebAssembly/WebAssemblyCFGStackify.cpp |
llvm::DenseMap<std::pair<llvm::Function*, llvm::FunctionType*>, llvm::Function*, llvm::DenseMapInfo<std::pair<llvm::Function*, llvm::FunctionType*>, void>, llvm::detail::DenseMapPair<std::pair<llvm::Function*, llvm::FunctionType*>, llvm::Function*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0x1f6db00
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0x1f6db50
testb $0x1, %al
jne 0x1f6dad6
jmp 0x1f6dae1
movq (%rsp), %rdi
callq 0x1f6dbc0
jmp 0x1f6daf3
movq (%rsp), %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<int, llvm::Function*, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Function*>>, int, llvm::Function*, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Function*>>::destroyAll() | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x1f781b0
cmpl $0x0, %eax
jne 0x1f79241
jmp 0x1f792d5
callq 0x1f780f0
movl %eax, 0x1c(%rsp)
callq 0x1f792e0
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x1f78100
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x1f78110
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
llvm::InstVisitor<(anonymous namespace)::OptimizeReturned, void>::delegateCallInst(llvm::CallInst&) | RetTy delegateCallInst(CallInst &I) {
if (const Function *F = I.getCalledFunction()) {
switch (F->getIntrinsicID()) {
default: DELEGATE(IntrinsicInst);
case Intrinsic::dbg_declare: DELEGATE(DbgDeclareInst);
case Intrinsic::dbg_value: DELEGATE(DbgValueInst);
case I... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %rdi
callq 0x7893a0
movq %rax, 0x10(%rsp)
cmpq $0x0, 0x10(%rsp)
je 0x1f8a3d1
movq 0x10(%rsp), %rdi
callq 0x78c590
movl %eax, %ecx
movl %ecx, 0x4(%rsp)
testl %eax, %eax
je 0x1f8a3cd
jmp 0x1f8a23d
movl... | /llvm/IR/InstVisitor.h |
void llvm::SmallVectorTemplateBase<llvm::LiveInterval*, true>::uninitialized_copy<llvm::LiveInterval*, llvm::LiveInterval*>(llvm::LiveInterval**, llvm::LiveInterval**, llvm::LiveInterval**, std::enable_if<std::is_same<std::remove_const<llvm::LiveInterval*>::type, llvm::LiveInterval*>::value, void>::type*) | static void uninitialized_copy(
T1 *I, T1 *E, T2 *Dest,
std::enable_if_t<std::is_same<std::remove_const_t<T1>, T2>::value> * =
nullptr) {
// Use memcpy for PODs iterated by pointers (which includes SmallVector
// iterators): std::uninitialized_copy optimizes to memmove, but we can
// u... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq %rdx, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq 0x20(%rsp), %rax
cmpq 0x18(%rsp), %rax
je 0x1f95e08
movq 0x10(%rsp), %rdi
movq 0x20(%rsp), %rsi
movq 0x18(%rsp), %rdx
movq 0x20(%rsp), %rax
subq %rax, %rdx
sarq $0x3, %rdx
shlq $0x3, %rdx
callq 0x348690
addq $0x... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*>, std::allocator<std::pair<llvm::SlotIndex, llvm::MachineInstr*>>>, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x28(%rsp), %rsi
leaq 0x20(%rsp), %rdx
callq 0x1f90f40
testb $0x1, %al
jne 0x1f95efd
jmp 0x1f95f5b
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xb3a6a0
testb $0x1, %al
jne 0x1f95f12
jmp 0x1f95f23
movq 0x1... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*>, std::allocator<std::pair<llvm::SlotIndex, llvm::MachineInstr*>>>, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*... | void destroyAll() {
if (getNumBuckets() == 0) // Nothing to do.
return;
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(P->... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x1f90aa0
cmpl $0x0, %eax
jne 0x1f96091
jmp 0x1f9612d
callq 0x1f909d0
movl %eax, 0x1c(%rsp)
callq 0x1f911b0
movq (%rsp), %rdi
movl %eax, 0x18(%rsp)
callq 0x1f909f0
movq (%rsp), %rdi
movq %rax, 0x10(%rsp)
callq 0x1f90a00
movq %rax, 0x8(... | /llvm/ADT/DenseMap.h |
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