name string | code string | asm string | file string |
|---|---|---|---|
bsplib::Bsmp::Bsmp(ompi_communicator_t*, unsigned long, unsigned long) | Bsmp::Bsmp(MPI_Comm comm, size_t max_msg_size, size_t small_exch_size)
: m_set_tag_size_counter(0)
, m_recv_tag_size(0)
, m_send_tag_size(0)
, m_next_tag_size(0)
, m_total_n_messages(0)
, m_total_payload(0)
, m_send_empty(true)
, m_a2a(comm, max_msg_size, small_exch_size )
, m_tag_bu... | pushq %rbx
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movups %xmm0, 0x10(%rdi)
movups %xmm0, (%rdi)
movb $0x1, 0x30(%rdi)
addq $0x38, %rdi
movsd 0x199a(%rip), %xmm0 # 0xf010
movsd 0x199a(%rip), %xmm1 # 0xf018
xorl %r8d, %r8d
callq 0x8278
movl $0x10, %eax
movq %rax, 0x1b0(%rbx)
xorps %xmm0, %xmm... | /wijnand-suijlen[P]bsponmpi/src/bsmp.cc |
bsplib::Bsmp::sync(bool) | void Bsmp::sync( bool dummy )
{
m_payloads.clear();
m_tag_buffer.clear();
m_payload_buffer.clear();
if (!dummy) {
#ifdef PROFILE
TicToc t( TicToc::BSMP);
#endif
const unsigned marker = 0;
for (int p = 0; p < m_a2a.nprocs(); ++p ) {
serial( m_a2a, p, marker );
serial( m_a2a... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp # imm = 0x1D8
movq %rdi, %rbx
movq 0x1d8(%rdi), %rax
cmpq %rax, 0x1e0(%rdi)
je 0xd6f7
movq %rax, 0x1e0(%rbx)
xorl %eax, %eax
movq %rax, 0x1d0(%rbx)
movq %rax, 0x210(%rbx)
testb %sil, %sil
jne 0xd908
leaq 0x38(%rbx), %r15
cmpl... | /wijnand-suijlen[P]bsponmpi/src/bsmp.cc |
bool (anonymous namespace)::AArch64Operand::isGPR64<42u>() const | bool isGPR64() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[RegClassID].contains(getReg());
} | xorl %eax, %eax
cmpl $0x4, 0x30(%rdi)
jne 0x78afea
cmpl $0x0, 0x4c(%rdi)
jne 0x78afea
pushq %rax
movq (%rdi), %rax
callq *0x38(%rax)
movl %eax, %ecx
shrl $0x3, %ecx
leaq 0x4d6c12d(%rip), %rdx # 0x54f70f0
movzwl 0x556(%rdx), %esi
cmpl %esi, %ecx
jae 0x78afe4
movq 0x548(%rdx), %rdx
movzbl (%rdx,%rcx), %ecx
andl $0x7, %... | /Target/AArch64/AsmParser/AArch64AsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::ParseDirective(llvm::AsmToken) | bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getString();
if (isHsaAbi(getSTI())) {
if (IDVal == ".amdhsa_kernel")
return ParseDirectiveAMDHSAKernel();
if (IDVal == ".amdhsa_code_object_version")
return ParseDirectiveAMDHSACodeObjectVersion();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %rdi, %rbx
movq 0x8(%rsi), %r15
movq 0x10(%rsi), %r14
callq 0x28a01f2
movq %rax, %rdi
callq 0x22c3588
movb $0x1, %bpl
leaq -0xb(%r14), %r12
testb %al, %al
je 0x78e44e
cmpq $0x9, %r12
ja 0x78e4a5
leaq 0x22bc... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::AMDGPUAsmParser::validateMAIAccWrite(llvm::MCInst const&, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>> const&) | bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
const OperandVector &Operands) {
const unsigned Opc = Inst.getOpcode();
if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)
return true;
const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movb $0x1, %bl
cmpl $0x7e00, (%rsi) # imm = 0x7E00
jne 0x7c77a1
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r14
movl $0x7e00, %edi # imm = 0x7E00
movl $0x16, %esi
callq 0x22c1c3c
movswq %ax, %rax
movl %eax, %eax
movq 0x10(%r12), %... | /Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
(anonymous namespace)::ARMAsmParser::checkEarlyTargetMatchPredicate(llvm::MCInst&, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>> const&) | unsigned
ARMAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) {
unsigned Opc = Inst.getOpcode();
switch (Opc) {
// Prevent the mov r8 r8 encoding for nop being selected when the v6/thumb 2
// encoding is available.
case ARM::tMO... | pushq %r14
pushq %rbx
pushq %rax
cmpl $0x116d, (%rsi) # imm = 0x116D
jne 0x7d2995
movq %rdx, %r14
movq %rdi, %rbx
movq (%rdx), %rax
movq (%rax), %rdi
movq (%rdi), %rax
callq *0x20(%rax)
testb %al, %al
je 0x7d2995
movq (%r14), %rax
movq (%rax), %rax
movl 0x90(%rax), %edx
cmpq $0x3, %rdx
jne 0x7d2995
movq 0x88(%r... | /Target/ARM/AsmParser/ARMAsmParser.cpp |
(anonymous namespace)::SparcAsmParser::tryParseRegister(llvm::MCRegister&, llvm::SMLoc&, llvm::SMLoc&) | ParseStatus SparcAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = Parser.getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
Reg = Sparc::NoRegister;
if (getLexer().getKind() != AsmToken::Percent)
ret... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %r15
movq %rdi, %r14
movq 0x130(%rdi), %rdi
callq 0x289f67c
movq %rax, %rbx
movq %rax, %rdi
callq 0x289f0f6
movq %rax, (%r13)
movq %rbx, %rdi
callq 0x289f0fc
movq %rax, (%r12)
movl $0x0, (%r15)
movq 0x8(%r... | /Target/Sparc/AsmParser/SparcAsmParser.cpp |
(anonymous namespace)::WebAssemblyAsmParser::addBlockTypeOperand(llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand>>>&, llvm::SMLoc, llvm::WebAssembly::BlockType) | void addBlockTypeOperand(OperandVector &Operands, SMLoc NameLoc,
WebAssembly::BlockType BT) {
if (BT != WebAssembly::BlockType::Void) {
wasm::WasmSignature Sig({static_cast<wasm::ValType>(BT)}, {});
TC.setLastSig(Sig);
NestingStack.back().Sig = Sig;
}
Operands.pu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %rbx
cmpl $0x40, %ecx
je 0x852361
movq %rdi, %r15
leaq 0x10(%rsp), %rdx
movl %ebp, -0x4(%rdx)
leaq 0x20(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x100000000, %rax # imm = 0x100000000
mov... | /Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp |
(anonymous namespace)::AArch64ExpandPseudo::expandCALL_RVMARKER(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AArch64ExpandPseudo::expandCALL_RVMARKER(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
// Expand CALL_RVMARKER pseudo to:
// - a branch to the call target, followed by
// - the special `mov x29, x29` marker, and
// - another branch, to the runtime function
// Mark the sequence as bundl... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r13
movq 0x20(%rdx), %r15
cmpw $0x1ad, 0x44(%rdx) # imm = 0x1AD
jne 0x91a2de
movups 0x20(%r15), %xmm0
movups 0x30(%r15), %xmm1
leaq 0x50(%rsp), %r8
movaps %xmm1, 0x10(%r8)
movaps %xmm0, (%... | /Target/AArch64/AArch64ExpandPseudoInsts.cpp |
llvm::AArch64TargetLowering::EmitZTInstr(llvm::MachineInstr&, llvm::MachineBasicBlock*, unsigned int, bool) const | MachineBasicBlock *AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *BB,
unsigned Opcode,
bool Op0IsDef) const {
const TargetInstrInfo... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r8d, %ebp
movl %ecx, %r15d
movq %rdx, 0x8(%rsp)
movq %rsi, %r14
movq 0x4e0f8(%rdi), %rbx
movq 0x38(%rsi), %rsi
movq %rsi, (%rsp)
testq %rsi, %rsi
je 0x959ba1
movq %rsp, %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movq (%rsp), %rsi
movq %r... | /Target/AArch64/AArch64ISelLowering.cpp |
llvm::EVT::getHalfNumVectorElementsVT(llvm::LLVMContext&) const | EVT getHalfNumVectorElementsVT(LLVMContext &Context) const {
EVT EltVT = getVectorElementType();
auto EltCnt = getVectorElementCount();
assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!");
return EVT::getVectorVT(Context, EltVT, EltCnt.divideCoefficientBy(2));
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r15
movzbl (%rdi), %eax
testq %rax, %rax
je 0x969e9a
leaq 0x260b0d0(%rip), %rcx # 0x2f74f60
movb -0x1(%rax,%rcx), %bpl
xorl %r14d, %r14d
jmp 0x969ea7
movq %r15, %rdi
callq 0x1a41ecc
movl %eax, %ebp
movq %rdx, %r14
movq %r15, %rdi
callq... | /llvm/CodeGen/ValueTypes.h |
llvm::detail::PassModel<llvm::MachineFunction, llvm::ExpandPostRAPseudosPass, llvm::AnalysisManager<llvm::MachineFunction>>::run(llvm::MachineFunction&, llvm::AnalysisManager<llvm::MachineFunction>&) | PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM,
ExtraArgTs... ExtraArgs) override {
return Pass.run(IR, AM, ExtraArgs...);
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
leaq 0x20(%rdi), %rax
movq %rax, (%rdi)
movq %rax, 0x8(%rdi)
movl $0x2, %eax
movq %rax, 0x10(%rdi)
xorl %ecx, %ecx
movl %ecx, 0x18(%rdi)
leaq 0x50(%rdi), %rdx
movq %rdx, 0x30(%rdi)
movq %rdx, 0x38(%rdi)
movq %rax, 0x40(%rdi)
movl %ecx, 0x48(%rdi)
leaq 0x4c139a3(%rip), %rdx ... | /llvm/IR/PassManagerInternal.h |
std::enable_if<!std::is_same_v<llvm::ImplicitNullChecksPass, llvm::PassManager<llvm::MachineFunction, llvm::AnalysisManager<llvm::MachineFunction>>>, void>::type llvm::PassManager<llvm::MachineFunction, llvm::AnalysisManager<llvm::MachineFunction>>::addPass<llvm::ImplicitNullChecksPass>(llvm::ImplicitNullChecksPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
pushq $0x10
popq %rdi
callq 0x6ea880
leaq 0x4a15348(%rip), %rcx # 0x5469b70
movq %rcx, (%rax)
movq %rsp, %r14
movq %rax, (%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0x761c24
movq (%r14), %rdi
testq %rdi, %rdi
je 0xa5484a
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x8, %... | /llvm/IR/PassManager.h |
llvm::detail::PassModel<llvm::MachineFunction, llvm::FEntryInserterPass, llvm::AnalysisManager<llvm::MachineFunction>>::run(llvm::MachineFunction&, llvm::AnalysisManager<llvm::MachineFunction>&) | PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM,
ExtraArgTs... ExtraArgs) override {
return Pass.run(IR, AM, ExtraArgs...);
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
leaq 0x20(%rdi), %rax
movq %rax, (%rdi)
movq %rax, 0x8(%rdi)
movl $0x2, %eax
movq %rax, 0x10(%rdi)
xorl %ecx, %ecx
movl %ecx, 0x18(%rdi)
leaq 0x50(%rdi), %rdx
movq %rdx, 0x30(%rdi)
movq %rdx, 0x38(%rdi)
movq %rax, 0x40(%rdi)
movl %ecx, 0x48(%rdi)
leaq 0x4c1326b(%rip), %rdx ... | /llvm/IR/PassManagerInternal.h |
llvm::BasicTTIImplBase<llvm::GCNTTIImpl>::getScalarizationOverhead(llvm::VectorType*, llvm::APInt const&, bool, bool, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getScalarizationOverhead(VectorType *InTy,
const APInt &DemandedElts,
bool Insert, bool Extract,
TTI::TargetCostKind CostKind) {
/// FIXME: a bitfield is not a reasonable ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movl %r9d, 0x14(%rsp)
movl %r8d, 0x1c(%rsp)
movl %ecx, 0x18(%rsp)
movq %rdi, 0x20(%rsp)
xorl %r14d, %r14d
cmpb $0x13, 0x8(%rsi)
jne 0xa5cf03
movl $0x1, %r14d
jmp 0xa5cfda
movq %rsi, %r13
movl 0x20(%rsi), %ebx
testl %ebx, %ebx
jle 0xa5cfd... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::GCNTTIImpl::getNumberOfRegisters(unsigned int) const | unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const {
// NB: RCID is not an RCID. In fact it is 0 or 1 for scalar or vector
// registers. See getRegisterClassForType for the implementation.
// In this case vector registers are not vector in terms of
// VGPRs, but those which can hold multiple values.... | movl $0x4, %eax
retq
| /Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
llvm::GCNTTIImpl::getTypeLegalizationCost(llvm::Type*) const | std::pair<InstructionCost, MVT>
GCNTTIImpl::getTypeLegalizationCost(Type *Ty) const {
std::pair<InstructionCost, MVT> Cost = BaseT::getTypeLegalizationCost(Ty);
auto Size = DL.getTypeSizeInBits(Ty);
// Maximum load or store can handle 8 dwords for scalar and 4 for
// vector ALU. Let's assume anything above 8 dw... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
callq 0xa5cd4c
movq 0x8(%r15), %rdi
movq %r14, %rsi
callq 0x889af0
movq %rsp, %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x20a1bec
cmpq $0x101, %rax # imm = 0x101
jb 0xa600f5
movq %rsp, %rdi
callq 0x20a1be... | /Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
llvm::BasicTTIImplBase<llvm::GCNTTIImpl>::getArithmeticInstrCost(unsigned int, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTransformInfo::OperandValueInfo, llvm::ArrayRef<llvm::Value const*>, llvm::Instruction const*) | InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef<const Value *> Args = std::nullopt,
const Instruct... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r9, 0x18(%rsp)
movq %r8, %r15
movl %ecx, %r12d
movq %rdx, %rbx
movl %esi, %r13d
movq %rdi, %r14
movq 0x18(%rdi), %rbp
movq %rbp, %rdi
callq 0x1a26a8c
testl %r12d, %r12d
je 0xa601ac
addq $0x8, %r14
leaq 0x100(%rsp), %rax
movups (%ra... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::GCNTTIImpl>::getScalarizationOverhead(llvm::VectorType*, llvm::ArrayRef<llvm::Value const*>, llvm::ArrayRef<llvm::Type*>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getScalarizationOverhead(VectorType *RetTy,
ArrayRef<const Value *> Args,
ArrayRef<Type *> Tys,
TTI::TargetCostKind CostKind) {
InstructionCost Cost = getScalarizationOver... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r9, 0x10(%rsp)
movq %r8, 0x8(%rsp)
movq %rcx, %r13
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r15
movl 0x50(%rsp), %r8d
movl $0x1, %edx
xorl %ecx, %ecx
callq 0xa5ce3e
movq %rax, %rbx
movl %edx, %ebp
movq %r15, %rdi
testq %r13, %r1... | /llvm/CodeGen/BasicTTIImpl.h |
bool llvm::PatternMatch::bind_const_intval_ty::match<llvm::Value>(llvm::Value*) | static bool classof(const Value *V) {
return V->getValueID() == ConstantIntVal;
} | cmpb $0x11, (%rsi)
jne 0xa6628f
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x18(%rsi), %r15
movl 0x20(%rsi), %ebp
cmpl $0x41, %ebp
jb 0xa66292
movq %r15, %rdi
callq 0x2060a38
subl %eax, %ebp
cmpl $0x40, %ebp
jbe 0xa66292
xorl %eax, %eax
jmp 0xa662a8
xorl %eax, %eax
retq
... | /llvm/IR/Constants.h |
bool llvm::PatternMatch::BinaryOp_match<llvm::PatternMatch::IntrinsicID_match, llvm::PatternMatch::bind_const_intval_ty, 27u, false>::match<llvm::Value const>(llvm::Value const*) | inline bool match(unsigned Opc, OpTy *V) {
if (V->getValueID() == Value::InstructionVal + Opc) {
auto *I = cast<BinaryOperator>(V);
return (L.match(I->getOperand(0)) && R.match(I->getOperand(1))) ||
(Commutable && L.match(I->getOperand(1)) &&
R.match(I->getOperand(0)));
}
... | cmpb $0x38, (%rsi)
jne 0xa662f2
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq -0x40(%rsi), %rsi
callq 0x89e9f4
testb %al, %al
je 0xa662e8
addq $0x8, %rbx
movq -0x20(%r14), %rsi
movq %rbx, %rdi
callq 0xa6625e
movl %eax, %ecx
movb $0x1, %al
testb %cl, %cl
jne 0xa662ea
xorl %eax, %eax
addq $0x8, %r... | /llvm/IR/PatternMatch.h |
llvm::AMDGPUUnifyMetadataPass::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) | PreservedAnalyses AMDGPUUnifyMetadataPass::run(Module &M,
ModuleAnalysisManager &AM) {
return unifyMetadataImpl(M) ? PreservedAnalyses::none()
: PreservedAnalyses::all();
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movq %rdx, %rdi
callq 0xa6820d
leaq 0x20(%rbx), %rdx
leaq 0x50(%rbx), %rcx
testb %al, %al
je 0xa681cc
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 0x10(%rbx)
movups %xmm0, 0x30(%rbx)
movups %xmm0, 0x40(%rbx)
movups %xmm0, 0x50(%rbx)
movups %xmm0, 0x20(%rbx)
movq %rdx... | /Target/AMDGPU/AMDGPUUnifyMetadata.cpp |
(anonymous namespace)::GCNDPPCombine::combineDPPMov(llvm::MachineInstr&) const | bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||
MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp ||
MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
auto *DstOpnd = TII->getNamedOp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x158, %rsp # imm = 0x158
movq %rsi, %r14
movq %rdi, %rbx
movq 0x40(%rdi), %rdi
movl $0xb, %edx
callq 0xac9260
movl 0x4(%rax), %esi
leal -0x1(%rsi), %eax
cmpl $0x3fffffff, %eax # imm = 0x3FFFFFFF
jb 0xa6907b
movq 0x38(%rbx), %rdi
m... | /Target/AMDGPU/GCNDPPCombine.cpp |
llvm::SmallVectorTemplateBase<llvm::MachineOperand*, true>::push_back(llvm::MachineOperand*) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0xa69981
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x208ec4e
... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::GCNDPPCombine::createDPPInst(llvm::MachineInstr&, llvm::MachineInstr&, llvm::TargetInstrInfo::RegSubRegPair, llvm::MachineOperand*, bool, bool) const | MachineInstr *GCNDPPCombine::createDPPInst(
MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
MachineOperand *OldOpndValue, bool CombBCZ, bool IsShrinkable) const {
assert(CombOldVGPR.Reg);
if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) {
auto *Src1 = TII->getNamedOperand(Ori... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rcx, %r14
movq %rdx, 0x50(%rsp)
movq %rsi, %r12
movq %rdi, %r15
movq %rcx, %r13
shrq $0x20, %r13
testq %r8, %r8
sete %al
movl %r9d, 0x64(%rsp)
orb %r9b, %al
jne 0xa69a03
movq %r8, %rbp
cmpb $0x1, (%r8)
jne 0xa69a03
movq 0x40(%r15),... | /Target/AMDGPU/GCNDPPCombine.cpp |
llvm::GCNIterativeScheduler::getRegionPressure(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | GCNRegPressure
GCNIterativeScheduler::getRegionPressure(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End)
const {
// For the purpose of pressure tracking bottom inst of the region should
// be also processed. End is either BB end, BB terminator inst or sc... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r12
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq 0x18(%rdx), %rbp
addq $0x30, %rbp
cmpq %rcx, %rbp
jne 0xa6af41
movq %rsp, %r13
movq %r12, (%r13)
movq %r13, %rdi
callq 0x8abce2
movq (%r13), %r12
testq %r12, %r12
je 0xa6af50... | /Target/AMDGPU/GCNIterativeScheduler.cpp |
llvm::GCNIterativeScheduler::enterRegion(llvm::MachineBasicBlock*, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, unsigned int) | void GCNIterativeScheduler::enterRegion(MachineBasicBlock *BB, // overridden
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
BaseClass::enterRegion(BB... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %r8d, %ebp
movq %rcx, %rbx
movq %rdx, %r14
movq %rdi, %r15
callq 0x1933290
cmpl $0x3, %ebp
jb 0xa6b0bf
leaq 0x14a0(%r15), %r12
leaq 0x1440(%r15), %rdi
movl $0x38, %esi
movl $0x3, %edx
callq 0x85e84c
movq %rax, %r13
movq %r14, (%rax)
movq ... | /Target/AMDGPU/GCNIterativeScheduler.cpp |
llvm::GCNIterativeScheduler::scheduleMinReg(bool) | void GCNIterativeScheduler::scheduleMinReg(bool force) {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
const auto TgtOcc = MFI->getOccupancy();
sortRegionsByPressure(TgtOcc);
auto MaxPressure = Regions.front()->MaxPressure;
for (auto *R : Regions) {
if (!force && R->MaxPressure.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movl %esi, %ebx
movq %rdi, %r14
movq 0x20(%rdi), %rax
movq 0x30(%rax), %rax
movl 0x3a8(%rax), %esi
movl %esi, 0xc(%rsp)
callq 0xa6bd34
movq 0x14a0(%r14), %r15
movq (%r15), %rax
movq 0x24(%rax), %rcx
movq %rcx, 0... | /Target/AMDGPU/GCNIterativeScheduler.cpp |
llvm::GCNIterativeScheduler::BuildDAG::~BuildDAG() | ~BuildDAG() {
Sch.BaseClass::exitRegion();
Sch.BaseClass::finishBlock();
} | pushq %rbx
movq %rdi, %rbx
movq (%rdi), %rdi
callq 0x19ef650
movq (%rbx), %rdi
callq 0x193273c
movq 0x58(%rbx), %rdi
leaq 0x68(%rbx), %rax
cmpq %rax, %rdi
je 0xa6c194
callq 0x6ea8c0
movq 0x8(%rbx), %rdi
addq $0x18, %rbx
cmpq %rbx, %rdi
je 0xa6c1a7
popq %rbx
jmp 0x6ea8c0
popq %rbx
retq
nop
| /Target/AMDGPU/GCNIterativeScheduler.cpp |
llvm::cl::opt<double, false, llvm::cl::parser<double>>::printOptionValue(unsigned long, bool) const | void printOptionValue(size_t GlobalWidth, bool Force) const override {
if (Force || !this->getDefault().compare(this->getValue())) {
cl::printOptionDiff<ParserClass>(*this, Parser, this->getValue(),
this->getDefault(), GlobalWidth);
}
} | movq %rsi, %rcx
movq %rdi, %rsi
testl %edx, %edx
je 0xa70156
subq $0x18, %rsp
leaq 0xa0(%rsi), %rdi
movsd 0x80(%rsi), %xmm0
leaq 0x49fb2e8(%rip), %rax # 0x546b410
movq %rsp, %rdx
movq %rax, (%rdx)
movq 0x90(%rsi), %rax
movq %rax, 0x8(%rdx)
movb 0x98(%rsi), %al
movb %al, 0x10(%rdx)
leaq 0x49fb2a7(%rip), %rax # 0x546... | /llvm/Support/CommandLine.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>::FindAndConstruct... | value_type& FindAndConstruct(KeyT &&Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, std::move(Key));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xa7357c
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xa739d0
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xa739da
movl (%rbx), %ecx
movl %ecx, (%rax)
movq $0x0... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>* llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::Den... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xa73a25
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<unsigned int, (anonymous namespace)::GCNRewritePartialRegUses::SubRegInfo>* llvm::DenseMapBase<llvm::SmallDenseMap<unsigned int, (anonymous namespace)::GCNRewritePartialRegUses::SubRegInfo, 4u, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, (anonymous namespa... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq %rdx, (%rsp)
movl (%rdi), %ecx
movl %ecx, %eax
shrl %eax
movl $0x4, %esi
testb $0x1, %cl
jne 0xa7588f
movl 0x10(%rbx), %esi
leal 0x4(,%rax,4), %ecx
leal (%rsi,%rsi,2), %edx
cmpl %edx, %ecx
jae 0xa758c4
notl %eax
addl %esi, %eax
subl 0x4(%rbx), %eax
m... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<unsigned int, llvm::BitVector, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::BitVector>, false>, bool> llvm::DenseMapBase<llvm::SmallDenseMap<unsigned int, llvm::BitVector, 4u, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<un... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xa76126
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xa7609a
xorl %ecx, %ecx
jmp 0xa760ea
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::SmallDenseMap<unsigned int, llvm::BitVector, 4u, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::BitVector>>, unsigned int, llvm::BitVector, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::BitVector>>::LookupBuck... | const BucketT *getBuckets() const {
return Small ? getInlineBuckets() : getLargeRep()->Buckets;
} | leaq 0x8(%rdi), %rcx
testb $0x1, (%rdi)
cmoveq 0x8(%rdi), %rcx
movl $0x4, %r8d
cmovel 0x10(%rdi), %r8d
testl %r8d, %r8d
je 0xa761b4
pushq %rbx
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %edi
decl %r8d
andl %r8d, %edi
movl $0x1, %r10d
xorl %r9d, %r9d
movl %edi, %r11d
leaq (%r11,%r11,4), %rbx
shlq $0x... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<std::pair<llvm::TargetRegisterClass const*, unsigned int>, unsigned int const*, llvm::DenseMapInfo<std::pair<llvm::TargetRegisterClass const*, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<llvm::TargetRegisterClass const*, unsigned int>, unsigned int const*>, false>, bool> ... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xa76aa0
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xa76a40
xorl %ecx, %ecx
jmp 0xa76a68
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineInstr*, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::DenseMap<unsigned int, llvm::Lane... | DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
std::vector<SlotIndex> Indexes;
Indexes.reserve(std::distance(R.begin(), R.end()));
auto &SII = *LIS.getSlotIndexes();
for (MachineInstr *I : R) {
auto SI = SII.getInstructionIndex(*I);
Indexes.p... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x288, %rsp # imm = 0x288
movq %rcx, 0x10(%rsp)
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %rbx
xorps %xmm0, %xmm0
leaq 0x40(%rsp), %rdi
movaps %xmm0, (%rdi)
movq $0x0, 0x10(%rdi)
movq 0x8(%rsi), %rsi
subq (%r15), %rsi
sarq $0x3, %rsi
ca... | /Target/AMDGPU/GCNRegPressure.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, llvm::SUnit*, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SUnit*>>, llvm::MachineInstr*, llvm::SUnit*, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm:... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xa7c775
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jne... | /llvm/ADT/DenseMap.h |
llvm::Automaton<unsigned long>::Automaton(llvm::Automaton<unsigned long> const&) | Automaton(const Automaton &Other)
: M(Other.M), State(Other.State), Transcribe(Other.Transcribe) {
// Transcriber is not thread-safe, so create a new instance on copy.
if (Other.Transcriber)
Transcriber = std::make_shared<internal::NfaTranscriber>(
Other.Transcriber->getTransitionInfo());
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rdi, %rbx
movq (%rsi), %rax
movq %rax, (%rdi)
movq 0x8(%rsi), %rax
movq %rax, 0x8(%rdi)
testq %rax, %rax
je 0xa84994
movq 0x4b7b17a(%rip), %rcx # 0x55ffb00
cmpb $0x0, (%rcx)
je 0xa84990
incl 0x8(%rax)
jmp 0xa84994
lock
incl 0x8(%rax)
xorps %xmm0, %xmm0
movu... | /llvm/Support/Automaton.h |
llvm::R600InstrInfo::fitsReadPortLimitations(std::vector<llvm::MachineInstr*, std::allocator<llvm::MachineInstr*>> const&, llvm::DenseMap<unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>> const&, std::vector<llvm::R600InstrInfo::BankSwizzle, std:... | bool
R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
const DenseMap<unsigned, unsigned> &PV,
std::vector<BankSwizzle> &ValidSwizzle,
bool isLastAluTrans)
const {
//Tod... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %r8d, 0x38(%rsp)
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, 0x30(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 0x40(%rsp)
movq $0x0, 0x50(%rsp)
movq (%rcx), %rax
cmpq %rax, 0x8(%rcx)
je 0xa86166
movq %rax, 0x8(%rbx)
movq (%rsi), %r13
movq ... | /Target/AMDGPU/R600InstrInfo.cpp |
llvm::R600AsmPrinter::emitInstruction(llvm::MachineInstr const*) | void R600AsmPrinter::emitInstruction(const MachineInstr *MI) {
R600_MC::verifyInstructionPredicates(MI->getOpcode(),
getSubtargetInfo().getFeatureBits());
const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
R600MCInstLower MCInstLowering(OutContext, STI, *this);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rsi, %r15
movq %rdi, %rbx
movzwl 0x44(%rsi), %ebp
callq 0x1792d7e
leaq 0xd8(%rax), %rsi
movl %ebp, %edi
callq 0x15085c8
movq 0x58(%rbx), %rax
movq 0x10(%rax), %rdx
movq 0x48(%rbx), %rsi
leaq 0x18(%rsp), %rdi
movq %rbx, %rcx
callq 0... | /Target/AMDGPU/R600MCInstLower.cpp |
GetArgMD(llvm::MDNode*, unsigned int) | static MDVector
GetArgMD(MDNode *KernelMDNode, unsigned OpIdx) {
MDVector Res;
for (unsigned i = 0; i < NumKernelArgMDNodes; ++i) {
MDNode *Node = cast<MDNode>(KernelMDNode->getOperand(i + 1));
Res.push_back(Node->getOperand(OpIdx));
}
return Res;
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, 0x8(%rdi)
leaq -0x10(%rsi), %r15
movl %edx, %r12d
movl $0x1, %r13d
movq (%r15), %rax
testb $0x2, %al
jne 0xa8a1f3
addl %eax, %eax
... | /Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp |
llvm::ValueMap<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>::operator[](llvm::Value const* const&) | ValueT &operator[](const KeyT &Key) {
return Map[Wrap(Key)];
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
movq (%rsi), %rsi
movq %rsp, %r14
movq %r14, %rdi
callq 0xa8a394
leaq 0x49e2a15(%rip), %rax # 0x546ccb0
movq %rax, (%r14)
movq %rbx, 0x20(%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0xa8ad62
movq %rax, %rbx
movq 0x18(%r14), %rax
cmpq $-0x2000, %rax # imm... | /llvm/IR/ValueMap.h |
llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>::deleted() | void deleted() override {
// Make a copy that won't get changed even when *this is destroyed.
ValueMapCallbackVH Copy(*this);
typename Config::mutex_type *M = Config::getMutex(Copy.Map->Data);
std::unique_lock<typename Config::mutex_type> Guard;
if (M)
Guard = std::unique_lock<typename Config:... | pushq %r14
pushq %rbx
subq $0x38, %rsp
movq %rdi, %r14
leaq 0x18(%rsp), %rbx
leaq 0x8(%rdi), %rdx
movl 0x8(%rdi), %esi
shrl %esi
andl $0x3, %esi
movq %rbx, %rdi
callq 0xa3c580
leaq 0x49e28aa(%rip), %rax # 0x546ccb0
movq %rax, -0x8(%rbx)
movq 0x20(%r14), %rdi
movq %rdi, 0x18(%rbx)
movq $0x0, (%rsp)
movb $0x0, 0x8(%rsp... | /llvm/IR/ValueMap.h |
llvm::ValueMap<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>::insert(std::pair<llvm::Value const*, llvm::WeakTrackingVH>&&) | std::pair<iterator, bool> insert(std::pair<KeyT, ValueT> &&KV) {
auto MapResult =
Map.insert(std::make_pair(Wrap(KV.first), std::move(KV.second)));
return std::make_pair(iterator(MapResult.first), MapResult.second);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x80, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdx), %rsi
leaq 0x18(%rsp), %r12
movq %r12, %rdi
callq 0xa8a394
leaq 0x49e2392(%rip), %rax # 0x546ccb0
movq %rax, (%r12)
movq %r15, 0x20(%r12)
addq $0x8, %r14
leaq 0x40(%rsp), %r13
movq %r13,... | /llvm/IR/ValueMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>, llvm::WeakTrackingVH, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const... | unsigned getNumBuckets() const {
return NumBuckets;
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl 0x10(%rdi), %r12d
testq %r12, %r12
je 0xa8afae
leaq 0x38(%rsp), %rbx
movl $0x2, %eax
movq %rax, (%rbx)
xorl %ecx, %ecx
movq %rcx, 0x8(%rbx)
movq $-0x1000, 0x10(%rbx) # imm = 0xF000
leaq 0x49e1dd4(%rip), %rdx # 0x546ccb0
movq %rdx, -0x8(%rbx)
movq %r... | /llvm/ADT/DenseMap.h |
llvm::createR600VectorRegMerger() | llvm::FunctionPass *llvm::createR600VectorRegMerger() {
return new R600VectorRegMerger();
} | pushq %rax
movl $0x90, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4b8c532(%rip), %rdx # 0x56175a8
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x49e1c4d(%rip), %rdx # 0x546cce0
movq %rdx, (%rax)
movups %xmm0, 0x40(%rax)
movup... | /Target/AMDGPU/R600OptimizeVectorRegisters.cpp |
llvm::createR600Packetizer() | llvm::FunctionPass *llvm::createR600Packetizer() {
return new R600Packetizer();
} | pushq %rax
movl $0x38, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4b897ce(%rip), %rdx # 0x56175b0
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x49defa9(%rip), %rcx # 0x546cda8
movq %rcx, (%rax)
popq %rcx
retq
| /Target/AMDGPU/R600Packetizer.cpp |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddMachinePass::operator()<llvm::VirtRegRewriterPass>(llvm::VirtRegRewriterPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rsi, %r13
movq %rdi, %r12
testl %edx, %edx
jne 0xa9bd9d
movq 0x20(%r12), %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0xa99872
testb %al, %al
je 0xa9bdf1
leaq 0x8(%r12), %r15
movq %r15, %rdi
movq %r13, %rsi
callq 0xa53ac8
movq 0x2... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddMachinePass::operator()<llvm::MachineBlockPlacementPass>(llvm::MachineBlockPlacementPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rsi, %r13
movq %rdi, %r12
testl %edx, %edx
jne 0xa9c059
movq 0x20(%r12), %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0xa99872
testb %al, %al
je 0xa9c0ad
leaq 0x8(%r12), %r15
movq %r15, %rdi
movq %r13, %rsi
callq 0xa54cd4
movq 0x2... | /llvm/Passes/CodeGenPassBuilder.h |
(anonymous namespace)::SIFixSGPRCopies::processPHINode(llvm::MachineInstr&) | void SIFixSGPRCopies::processPHINode(MachineInstr &MI) {
bool AllAGPRUses = true;
SetVector<const MachineInstr *> worklist;
SmallSet<const MachineInstr *, 4> Visited;
SetVector<MachineInstr *> PHIOperands;
worklist.insert(&MI);
Visited.insert(&MI);
// HACK to make MIR tests with no uses happy
bool HasUs... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %r15
movq %rdi, %rbx
xorl %eax, %eax
leaq 0x68(%rsp), %rcx
movl %eax, -0x18(%rcx)
xorps %xmm0, %xmm0
movaps %xmm0, -0x28(%rcx)
movq %rcx, -0x10(%rcx)
movq %rax, -0x8(%rcx)
leaq 0xa8(%rsp), %rcx
movq %rcx, -0x20(%rcx)
movq %rcx... | /Target/AMDGPU/SIFixSGPRCopies.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>>, unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>>::erase(unsigned int const&) | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rdx
callq 0x8ccde6
testb %al, %al
je 0xaa3483
movq 0x8(%rsp), %rcx
movl $0xfffffffe, (%rcx) # imm = 0xFFFFFFFE
movq 0x8(%rbx), %xmm0
paddd 0x26d1012(%rip), %xmm0 # 0x3174490
movq %xmm0, 0x8(%rbx)
addq $0x10, %rsp
popq %rbx
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::DenseMap<unsigned int, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseSetPair<unsigned int>>::operator=(llvm::DenseMap<unsigned int, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseSetPair<unsigned int>>&&) | DenseMap& operator=(DenseMap &&other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
init(0);
swap(other);
return *this;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
movl 0x10(%rbx), %esi
shlq $0x2, %rsi
movl $0x4, %edx
callq 0x2085c39
xorl %eax, %eax
movl %eax, 0x10(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movq (%r14), %rcx
movq %rcx, (%rbx)
movq $0x0, (%r14)
movl 0x8(%r14), %ecx
movl %ecx, 0x8... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineInstr*, llvm::SetVector<unsigned int, llvm::SmallVector<unsigned int, 0u>, llvm::DenseSet<unsigned int, llvm::DenseMapInfo<unsigned int, void>>, 0u>, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SetVector<unsigned int, llvm::SmallVector... | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | pushq %rbp
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x8(%rdi), %ebp
movl 0x10(%rdi), %r14d
callq 0xaa0f3e
testl %ebp, %ebp
je 0xaa4c6f
decl %ebp
je 0xaa4c73
bsrl %ebp, %eax
xorl $0x1f, %eax
jmp 0xaa4c78
xorl %ebp, %ebp
jmp 0xaa4c8e
movl $0x20, %eax
movb $0x21, %cl
subb %al, %cl
movl $0x1, %eax
shll %cl, %eax
cmpl $0x... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::TargetInstrInfo::RegSubRegPair, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetInstrInfo::RegSubRegPair, void>, llvm::detail::DenseSetPair<llvm::TargetInstrInfo::RegSubRegPair>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::TargetInstrInfo::RegSubRegPair, llvm... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xaaacd8
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xaaac9a
xorl %ecx, %ecx
jmp 0xaaacb3
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
llvm::SIInstrInfo::isStackAccess(llvm::MachineInstr const&, int&) const | unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
if (!Addr || !Addr->isFI())
return Register();
assert(!MI.memoperands_empty() &&
(*MI.memoperands_begin())... | pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %r14
movq %rsi, %rbx
movzwl 0x44(%rsi), %ebp
movl %ebp, %edi
movl $0x1, %esi
callq 0x22c1c3c
movl %eax, %ecx
cmpw $-0x1, %ax
sete %sil
movq 0x20(%rbx), %rdx
testq %rdx, %rdx
sete %dil
xorl %eax, %eax
orb %sil, %dil
jne 0xaddc82
movswq %cx, %rcx
movl %ecx, %ecx
shlq $0x5, %rcx... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::MachineInstr::isConditionalBranch(llvm::MachineInstr::QueryType) const | bool isConditionalBranch(QueryType Type = AnyInBundle) const {
return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
} | pushq %r14
pushq %rbx
pushq %rax
movl %esi, %ebx
movq %rdi, %r14
movl $0xa, %esi
movl %ebx, %edx
callq 0x877c7c
testb %al, %al
je 0xb51b96
movq %r14, %rdi
movl $0x8, %esi
movl %ebx, %edx
callq 0x877c7c
testb %al, %al
je 0xb51b9a
xorl %eax, %eax
jmp 0xb51bab
movq %r14, %rdi
movl $0xb, %esi
movl %ebx, %edx
callq 0x877c7c... | /llvm/CodeGen/MachineInstr.h |
(anonymous namespace)::AMDGPUGlobalISelDivergenceLowering::AMDGPUGlobalISelDivergenceLowering() | AMDGPUGlobalISelDivergenceLowering() : MachineFunctionPass(ID) {
initializeAMDGPUGlobalISelDivergenceLoweringPass(
*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a988dc(%rip), %rcx # 0x56193e8
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4909297(%rip), %rax # 0x5489dc0
movq %rax, (%rdi)
callq 0x1baa13c
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x4a988... | /Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp |
llvm::AMDGPUInstructionSelector::selectPHI(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
const Register DefReg = I.getOperand(0).getReg();
const LLT DefTy = MRI->getType(DefReg);
// S1 G_PHIs should not be selected in instruction-select, instead:
// - divergent S1 G_PHI should go through lane mask merging algorithm
// and be fu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %r15
movq %rdi, %r14
movq 0x20(%rsi), %rax
movl 0x4(%rax), %ebx
movq 0x48(%rdi), %rax
testl %ebx, %ebx
jns 0xb93602
movl %ebx, %ecx
andl $0x7fffffff, %ecx # imm = 0x7FFFFFFF
cmpl %ecx, 0x1d0(%rax)
jbe 0xb93602
movq 0x1c8(%rax), %rdx
movq (%rdx,%rcx... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::LiveVariables::VarInfo::removeKill(llvm::MachineInstr&) | bool removeKill(MachineInstr &MI) {
std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
if (I == Kills.end())
return false;
Kills.erase(I);
return true;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rdx
movq %rsi, (%rdx)
movq 0x20(%rdi), %rdi
movq 0x28(%rbx), %rsi
callq 0xa8c823
movq %rax, %r14
movq 0x28(%rbx), %r15
cmpq %r15, %rax
je 0xcd2103
leaq 0x8(%r14), %rsi
cmpq %r15, %rsi
je 0xcd20fe
movq %r15, %rdx
subq %rsi, %rdx
movq %r14... | /llvm/CodeGen/LiveVariables.h |
llvm::ARMBaseInstrInfo::createMIROperandComment[abi:cxx11](llvm::MachineInstr const&, llvm::MachineOperand const&, unsigned int, llvm::TargetRegisterInfo const*) const | std::string ARMBaseInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
const TargetRegisterInfo *TRI) const {
// First, let's see if there is a generic comment for this operand
std::string GenericComment =
TargetInstrInfo::createMIROperandComment(MI, ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movl %r8d, %ebp
movq %rcx, %r14
movq %rdx, %r15
movq %rdi, %rbx
movq %rsp, %r12
movq %r12, %rdi
callq 0x1a22f26
movq 0x8(%r12), %rax
testq %rax, %rax
je 0xcd3100
leaq 0x10(%rbx), %rdx
movq %rdx, (%rbx)
leaq 0x10(%rsp), %rcx
movq -0x10(%rcx), %rsi
c... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::duplicate(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstr const&) const | MachineInstr &
ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
const MachineInstr &Orig) const {
MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
MachineBasicBlock::instr_iterator I = Cloned.getIterator();
for (;;) {
switch (I->g... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
callq 0x1a20862
movq %rax, %r14
leaq 0x4(%rsp), %r15
movq %rax, %r12
movzwl 0x44(%r12), %eax
cmpl $0x2f7, %eax # imm = 0x2F7
je 0xcd94e7
cmpl $0x2ae, %eax # imm = 0x2AE
jne 0xcd9516
movq 0x20(%rbx), %rdi
movq 0x20(%r12), %rax
m... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::extraSizeToPredicateInstructions(llvm::MachineFunction const&, unsigned int) const | unsigned
ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,
unsigned NumInsts) const {
// Thumb2 needs a 2-byte IT instruction to predicate up to 4 instructions.
// ARM has a condition code field in every predicable instruction, using it
... | movq 0x50(%rdi), %rcx
xorl %eax, %eax
cmpb $0x1, 0x192(%rcx)
jne 0xcd9e92
testb $0x1, 0x161(%rcx)
je 0xcd9e92
movb 0x1b6(%rcx), %cl
xorl %eax, %eax
testl %edx, %edx
setne %al
subl %eax, %edx
xorb $0x1, %cl
addb %cl, %cl
shrl %cl, %edx
addl %eax, %edx
addl %edx, %edx
movl %edx, %eax
retq
nop
| /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::SmallVectorTemplateBase<std::pair<llvm::MachineOperand*, llvm::ARMCC::CondCodes>, true>::push_back(std::pair<llvm::MachineOperand*, llvm::ARMCC::CondCodes>) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r14
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0xcdbd26
movq (%r14), %rax
movl 0x8(%r14), %ecx
shlq $0x4, %rcx
movq %r15, (%rax,%rcx)
movl %ebx, 0x8(%rax,%rcx)
incl 0x8(%r14)
popq %rbx
popq %r14
popq %r15
retq
incq %rdx
leaq 0x10(%r14), %rs... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::ARMPipelinerLoopInfo::bumpCrossIterationPressure(llvm::RegPressureTracker&, std::map<unsigned int, std::bitset<32ul>, std::less<unsigned int>, std::allocator<std::pair<unsigned int const, std::bitset<32ul>>>> const&) | void ARMPipelinerLoopInfo::bumpCrossIterationPressure(RegPressureTracker &RPT,
const IterNeeds &CIN) {
// Increase pressure by the amounts in CrossIterationNeeds
for (const auto &N : CIN) {
int Cnt = N.second.count() - N.second[SEEN_AS_LIVE] * 2;
for (in... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x18(%rsi), %r15
movq %rsi, (%rsp)
leaq 0x8(%rsi), %r12
cmpq %r12, %r15
je 0xce5bd8
movabsq $0x3333333333333333, %rbp # imm = 0x3333333333333333
xorl %r14d, %r14d
movq 0x28(%r15), %rax
movq %rax, %rcx
shrq %rcx
movabsq $0x... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::ARMBranchTargets, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x38, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4935733(%rip), %rdx # 0x561cbd4
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x47afea2(%rip), %rcx # 0x5497360
movq %rcx, (%rax)
popq %rcx
retq
nop
| /llvm/PassSupport.h |
llvm::ARMCallLowering::lowerReturn(llvm::MachineIRBuilder&, llvm::Value const*, llvm::ArrayRef<llvm::Register>, llvm::FunctionLoweringInfo&) const | bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<Register> VRegs,
FunctionLoweringInfo &FLI) const {
assert(!Val == VRegs.empty() && "Return value without a vreg");
auto const &ST = MIRBuilder.getMF().getS... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %r8, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq %rdx, %r12
movq %rsi, %rbx
movq 0x8(%rsi), %rax
movq 0x10(%rax), %rax
testb $0x1, 0x163(%rax)
movl $0x32f, %ecx # imm = 0x32F
movl $0x3c7, %edx # imm = 0x3C7
cmovnel %e... | /Target/ARM/ARMCallLowering.cpp |
(anonymous namespace)::ARMOutgoingValueHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
"Unsupported size");
LLT p0 = LLT::pointer(0, 32);
LLT s32 = LLT::... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, 0x10(%rsp)
movq %rdx, %rbx
movq %rdx, 0x8(%rsp)
movq %rdi, %r15
movq 0x8(%rdi), %rdi
movl $0x102, %eax # imm = 0x102
leaq 0x30(%rsp), %r12
movq %rax, (%r12)
xorl %r14d, %r14d
movl %r14d, 0x8(%r12)
leaq 0x18(%rsp), %... | /Target/ARM/ARMCallLowering.cpp |
llvm::ARMBankConflictHazardRecognizer::getHazardType(llvm::SUnit*, int) | ScheduleHazardRecognizer::HazardType
ARMBankConflictHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
MachineInstr &L0 = *SU->getInstr();
if (!L0.mayLoad() || L0.mayStore() || L0.getNumMemOperands() != 1)
return NoHazard;
auto MO0 = *L0.memoperands().begin();
auto BaseVal0 = MO0->getValue();
auto ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rdi, %rbp
movq (%rsi), %r14
movq %r14, %rdi
movl $0x1, %esi
callq 0x87b3a6
xorl %r15d, %r15d
testb %al, %al
je 0xd0176b
movq %r14, %rdi
movl $0x1, %esi
callq 0x87b3ca
testb %al, %al
jne 0xd0176b
movq 0x30(%r14), %rcx
cmpq $0x8, %rc... | /Target/ARM/ARMHazardRecognizer.cpp |
(anonymous namespace)::ARMDAGToDAGISel::isShifterOpProfitable(llvm::SDValue const&, llvm::ARM_AM::ShiftOpc, unsigned int) | bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
ARM_AM::ShiftOpc ShOpcVal,
unsigned ShAmt) {
if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
return true;
if (Shift.hasOneUse())
return true;
// R ... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq 0x108(%rdi), %rax
movl 0x1a8(%rax), %eax
movb $0x1, %bl
cmpl $0x11, %eax
ja 0xd14a70
movl %ecx, %ebp
movl $0x22012, %ecx # imm = 0x22012
btl %eax, %ecx
jae 0xd14a70
movl %edx, %r15d
movq %rdi, %r14
movq (%rsi), %rdi
movl 0x8(%rsi), %edx
movl $0x1, %es... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectMVE_VSHLC(llvm::SDNode*, bool) | void ARMDAGToDAGISel::SelectMVE_VSHLC(SDNode *N, bool Predicated) {
SDLoc Loc(N);
SmallVector<SDValue, 8> Ops;
// One vector input, followed by a 32-bit word of bits to shift in
// and then an immediate shift count
Ops.push_back(N->getOperand(1));
Ops.push_back(N->getOperand(2));
int32_t ImmValue = N->ge... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x18(%rsp)
testq %rsi, %rsi
je 0xd1cd1e
leaq 0x18(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%rbx), %eax
movl %eax, 0x20(%rsp)
leaq 0x68(%rsp), %... | /Target/ARM/ARMISelDAGToDAG.cpp |
getIntOperandsFromRegisterString(llvm::StringRef, llvm::SelectionDAG*, llvm::SDLoc const&, std::vector<llvm::SDValue, std::allocator<llvm::SDValue>>&) | static void getIntOperandsFromRegisterString(StringRef RegString,
SelectionDAG *CurDAG,
const SDLoc &DL,
std::vector<SDValue> &Ops) {
SmallVector<StringRef, 5> Fields;
RegString.spl... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %r8, %rbx
movq %rcx, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
leaq 0x48(%rsp), %rax
movq %rdi, (%rax)
movq %rsi, 0x8(%rax)
leaq 0x68(%rsp), %rdx
movq %rdx, -0x10(%rdx)
movabsq $0x500000000, %rcx # imm = 0x500000000
movq %rcx, -0x8(%rdx... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, unsigned int) | bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
SDValue &OffImm,
unsigned Shift) {
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM;
switch (Opcode) {
case ISD::LOAD:
AM = cast<... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rcx, %rbx
movq %rdx, %r14
movl $0x1, %r9d
movl %r8d, %ecx
shll %cl, %r9d
movl 0x18(%rdx), %eax
cmpl $0x23, %eax
je 0xd1e387
cmpl $0xb, %eax
jne 0xd1e38c
movq %r14, %rax
jmp 0xd1e38e
xorl %eax, %eax
movzwl 0x1e(%rsi), %r13d
testq %r... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbx
movq %rcx, %r15
movq %rsi, %r14
movq %rdi, %r12
movl 0x18(%rdx), %eax
cmpl $0x23, %eax
je 0xd1e60b
cmpl $0xb, %eax
je 0xd1e60b
xorl %edx, %edx
testq %rdx, %rdx
je 0xd1e620
movq 0x58(%rdx), %rax
cmpl $0x41, 0x20(%rax)
jb 0x... | /Target/ARM/ARMISelDAGToDAG.cpp |
void (anonymous namespace)::ARMDAGToDAGISel::AddMVEPredicateToOps<llvm::SmallVector<llvm::SDValue, 8u>>(llvm::SmallVector<llvm::SDValue, 8u>&, llvm::SDLoc, llvm::SDValue, llvm::SDValue) | void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
SDValue PredicateMask,
SDValue Inactive) {
Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
Ops.push_back(PredicateMask);
Ops.push_b... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %r8d, %ebp
movq %rcx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq 0x38(%rdi), %rdi
movl $0x0, (%rsp)
movl $0x1, %esi
movl $0x7, %ecx
xorl %r8d, %r8d
movl $0x1, %r9d
callq 0x1f4f39a
movq %rbx, %rdi
movq %rax, %rsi
callq 0x94e6cc
movq %rbx, %rdi
movq %r15, %rsi
mo... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::hasNoVMLxHazardUse(llvm::SDNode*) const | bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
if (OptLevel == CodeGenOptLevel::None)
return true;
if (!Subtarget->hasVMLxHazards())
return true;
if (!N->hasOneUse())
return false;
SDNode *Use = *N->use_begin();
if (Use->getOpcode() == ISD::CopyToReg)
return true;
if (Use->is... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movb $0x1, %bl
cmpl $0x0, 0x68(%rdi)
je 0xd204cf
movq 0x108(%rdi), %rax
cmpb $0x1, 0x18a(%rax)
jne 0xd204cf
movq 0x38(%rsi), %rax
testq %rax, %rax
je 0xd204cd
cmpq $0x0, 0x20(%rax)
je 0xd204d9
xorl %ebx, %ebx
movl %ebx, %eax
addq $0x18, %rsp
popq %rbx
popq %r14
retq
movq 0x10(%rax... | /Target/ARM/ARMISelDAGToDAG.cpp |
llvm::ARMTargetLowering::getEffectiveCallingConv(unsigned int, bool) const | CallingConv::ID
ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
bool isVarArg) const {
switch (CC) {
default:
report_fatal_error("Unsupported calling convention");
case CallingConv::ARM_AAPCS:
case CallingConv::ARM_APCS:
case CallingConv::GHC:
ca... | pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebx
cmpl $0x14, %esi
ja 0xd23b07
movq %rdi, %r14
movl %esi, %eax
leaq 0x28b99a9(%rip), %rcx # 0x35dd44c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x4e0f8(%r14), %rdi
callq 0xc9f0fa
movl $0x42, %esi
testb %al, %al
je 0xd23b83
movq 0x4e0f8(%r14), %rax
cmpb $... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::CCAssignFnForNode(unsigned int, bool, bool) const | CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
bool Return,
bool isVarArg) const {
switch (getEffectiveCallingConv(CC, isVarArg)) {
default:
report_fatal_error("Unsupported calling convention"... | pushq %rbx
movl %edx, %ebx
movl %ecx, %edx
callq 0xd23a8c
cmpl $0x41, %eax
jg 0xd23be0
addl $-0x8, %eax
cmpl $0xb, %eax
ja 0xd23c54
leaq 0x28b98d6(%rip), %rcx # 0x35dd4a0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
testb %bl, %bl
je 0xd23c39
leaq 0x75fca(%rip), %rax # 0xd99ba8
jmp 0xd23c52
cmpl $0x42, %... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::getARMCmp(llvm::SDValue, llvm::SDValue, llvm::ISD::CondCode, llvm::SDValue&, llvm::SelectionDAG&, llvm::SDLoc const&) const | SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMcc, SelectionDAG &DAG,
const SDLoc &dl) const {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getZExtVal... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rcx, %r13
movl %edx, %r14d
movq %rsi, %rbx
movq %rdi, %r12
movl 0x18(%rcx), %eax
cmpl $0x23, %eax
je 0xd2e146
cmpl $0xb, %eax
jne 0xd2e14b
movq %r13, %rcx
jmp 0xd2e14d
xorl %ecx, %ecx
testq %rcx, %rcx
je 0xd2e16d
movl %r14d, 0x28(%... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerINT_TO_FP(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
if (VT.isVector())
return LowerVectorINT_TO_FP(Op, DAG);
if (isUnsupportedFloatingType(VT)) {
RTLIB::Libcall LC;
if (Op.getOpcode() == ISD::SINT_TO_FP)
LC = RTLIB::getSINTTOFP(Op.getOpera... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rcx, 0x58(%rsp)
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
movq 0x30(%rsi), %r13
movl %edx, %r12d
shlq $0x4, %r12
movb (%r13,%r12), %r14b
movq 0x8(%r13,%r12), %rax
movb %r14b, 0xb0(%rsp)
movq %rax, 0x... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerRETURNADDR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setReturnAddressIsTaken(true);
if (verifyReturnAddressArgumentIsConstant(Op, DAG))
return SDValue();
EVT VT = Op.getValueType();... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r13
movq %rdi, %r12
movq 0x28(%rcx), %r15
movq 0x38(%r15), %rax
movb $0x1, 0x26(%rax)
callq 0x1fbe702
testb %al, %al
je 0xd33f5f
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp 0xd3414b
movq 0x30(%r13), ... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerFRAMEADDR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
const ARMBaseRegisterInfo &ARI =
*static_cast<const ARMBaseRegisterInfo*>(RegInfo);
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setFrameAddressIsTaken(true);
EVT VT = Op.get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rcx, %rbp
movq %rsi, %r13
movq 0x4e100(%rdi), %r15
movq 0x28(%rcx), %r12
movq 0x38(%r12), %rax
movb $0x1, 0x25(%rax)
movq 0x30(%rsi), %rax
movl %edx, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %bl
movq 0x8(%rax,%rcx), %r14
movq 0x48(%r... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerRESET_FPMODE(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerRESET_FPMODE(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue Chain = Op->getOperand(0);
// To get the default FP mode all control bits are cleared:
// FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
SDValue Ops[] = {Cha... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rcx, %rbx
movq %rsi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x20(%rsp)
testq %rsi, %rsi
je 0xd3608c
leaq 0x20(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%r15), %eax
leaq 0x20(%rsp), %r14
movl %eax, 0x8(%r14)
movq 0x28(%r1... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
LLVM_DEBUG(dbgs() << "Lowering node: "; Op.dump());
switch (Op.getOpcode()) {
default: llvm_unreachable("Don't know how to custom lower this!");
case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
case ISD::ConstantPoo... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rcx, %r14
movl %edx, %ebx
movq %rsi, %r13
movq %rdi, %r15
movl 0x18(%rsi), %eax
cmpl $0x117, %eax # imm = 0x117
jle 0xd3cc40
cmpl $0x148, %eax # imm = 0x148
jg 0xd3cc08
cmpl $0x136, %... | /Target/ARM/ARMISelLowering.cpp |
LowerFP_TO_INT_SAT(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
EVT VT = Op.getValueType();
EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
EVT FromVT = Op.getOperand(0).getValueType();
if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT ==... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rdx, %rbx
movl %esi, %r15d
movq %rdi, %r14
movq 0x30(%rdi), %rdx
movl %esi, %esi
shlq $0x4, %rsi
movb (%rdx,%rsi), %al
movq 0x8(%rdx,%rsi), %rdx
movb %al, 0x40(%rsp)
movq %rdx, 0x48(%rsp)
movq 0x28(%rdi), %rdx
movq 0x28(%rdx), %rdi... | /Target/ARM/ARMISelLowering.cpp |
LowerVSETCC(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
bool Invert = false;
bool Swap = false;
unsigned Opc = ARMCC::AL;
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
SDValue CC = Op.getOperand(2);
EVT VT = Op.getValueType();
ISD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x2b8, %rsp # imm = 0x2B8
movq %rcx, %r13
movq %rdx, 0x98(%rsp)
movq %rdi, %rbx
movq 0x28(%rdi), %rax
movq 0x30(%rdi), %rcx
movq (%rax), %r15
movl 0x8(%rax), %r12d
movl 0xc(%rax), %edx
movl %edx, 0x80(%rsp)
movq 0x28(%rax), %rdx
movq %rd... | /Target/ARM/ARMISelLowering.cpp |
LowerSDIV(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
EVT VT = Op.getValueType();
assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
"unexpected type for custom-lowering ISD::SDIV");
SDLoc dl(Op);
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOpe... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x148, %rsp # imm = 0x148
movq %rcx, %r15
movq %rdx, %rbx
movq %rdi, %r14
movq 0x30(%rdi), %rax
movl %esi, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %bpl
movq 0x48(%rdi), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0xd439c8
leaq 0x30(%rs... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::isDesirableToCommuteXorWithShift(llvm::SDNode const*) const | bool ARMTargetLowering::isDesirableToCommuteXorWithShift(
const SDNode *N) const {
assert(N->getOpcode() == ISD::XOR &&
(N->getOperand(0).getOpcode() == ISD::SHL ||
N->getOperand(0).getOpcode() == ISD::SRL) &&
"Expected XOR(SHIFT) pattern");
// Only commute if the entire NOT mask is... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rsi, %rbx
movq 0x28(%rsi), %rcx
movq 0x28(%rcx), %rax
movl 0x18(%rax), %edx
cmpl $0x23, %edx
je 0xd546a0
cmpl $0xb, %edx
je 0xd546a0
xorl %eax, %eax
movq (%rcx), %rcx
movq 0x28(%rcx), %rcx
movq 0x28(%rcx), %r14
movl 0x18(%r14), %ecx
cmpl $0x23, %ecx
je 0xd546bc
cm... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::PerformCMOVToBFICombine(llvm::SDNode*, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
// If we have a CMOV, OR and AND combination such as:
// if (x & CN)
// y |= CM;
//
// And:
// * CN is a single bit;
// * All bits covered by CM are known zero in y
//
// Then we can convert this into... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x138, %rsp # imm = 0x138
movq %rdx, 0x80(%rsp)
movq %rsi, %r15
movq %rdi, 0x40(%rsp)
movq 0x28(%rsi), %rax
movq (%rax), %rbp
movl 0x8(%rax), %ebx
movq 0x28(%rax), %r12
movl 0x30(%rax), %r13d
movq 0x50(%rax), %rax
movq 0x58(%rax), %rdi
a... | /Target/ARM/ARMISelLowering.cpp |
PerformANDCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&, llvm::ARMSubtarget const*) | static SDValue PerformANDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *Subtarget) {
// Attempt to use immediate-form VBIC
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
SDLoc dl(N);
EVT VT =... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdx, %r14
movq %rdi, %rbx
movq 0x28(%rdi), %rax
movq 0x28(%rax), %rbp
xorl %r12d, %r12d
cmpl $0x9b, 0x18(%rbp)
cmovneq %r12, %rbp
movq %rsi, %r15
movq 0x48(%rdi), %rsi
movq %rsi, 0x58(%rsp)
testq %rsi, %rsi
je 0xd5ec40
leaq 0x58(%r... | /Target/ARM/ARMISelLowering.cpp |
PerformVMOVrhCombine(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue PerformVMOVrhCombine(SDNode *N, SelectionDAG &DAG) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
// fold (VMOVrh (fpconst x)) -> const x
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0)) {
APFloat V = C->getValueAPF();
return DAG.getConstant(V.bitcastToAPInt().get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq 0x30(%rdi), %rdx
movq (%rax), %r12
movl 0x18(%r12), %ecx
cmpl $0x24, %ecx
je 0xd610b2
cmpl $0xc, %ecx
jne 0xd610b7
movq %r12, %rsi
jmp 0xd610b9
xorl %esi, %esi
movb (%rdx), %bpl
... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::isTruncateFree(llvm::Type*, llvm::Type*) const | bool isIntegerTy() const { return getTypeID() == IntegerTyID; } | cmpb $0xd, 0x8(%rsi)
jne 0xd68691
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
cmpb $0xd, 0x8(%rdx)
jne 0xd68694
movq %rsi, %rdi
callq 0x1bb4c4e
movq %rsp, %r14
movq %rax, (%r14)
movb %dl, 0x8(%r14)
movq %r14, %rdi
callq 0x20a1bec
movq %rax, %r15
movq %rbx, %rdi
callq 0x1bb4c4e
movq %rax, (%r14)
mo... | /llvm/IR/Type.h |
llvm::KnownBits::sext(unsigned int) const | KnownBits sext(unsigned BitWidth) const {
return KnownBits(Zero.sext(BitWidth), One.sext(BitWidth));
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r15
movq %r15, %rdi
callq 0x2061858
addq $0x10, %r14
leaq 0x10(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
movl %ebp, %edx
callq 0x2061858
movl 0x8(%r15), %eax
movl %eax, 0x8(%rbx)
movq (%... | /llvm/Support/KnownBits.h |
llvm::ARMTargetLowering::getInlineAsmMemConstraint(llvm::StringRef) const | InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
return InlineAsm::ConstraintCode::Q;
if (ConstraintCode.size() == 2) {
if (ConstraintCode[0] == 'U') {
switch(ConstraintCode[1]) {
default:
... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpq $0x2, %rdx
je 0xd6f4ac
cmpq $0x1, %rbx
jne 0xd6f4d5
leaq 0x40d959c(%rip), %rsi # 0x4e48a33
movq %r14, %rdi
movq %rbx, %rdx
callq 0x6eabe0
testl %eax, %eax
je 0xd6f4e8
cmpq $0x2, %rbx
jne 0xd6f4d5
cmpb $0x55, (%r14)
jne 0xd6f4d5
movb... | /Target/ARM/ARMISelLowering.h |
PerformExtractEltToVMOVRRD(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) | static SDValue
PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
EVT VT = N->getValueType(0);
SDLoc dl(N);
if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||
!DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64))
return SDValue();
SDValue Ext = SDValue(N, 0);
if (Ext.g... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x30(%rdi), %rax
movb (%rax), %bpl
movq 0x48(%rdi), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0xd77d26
leaq 0x30(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%r14), %eax
movl %eax, 0x38(... | /Target/ARM/ARMISelLowering.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, unsigned int>>, llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, unsigned int>>::moveFromOldBuckets(llvm::detai... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xd79b0f
movq (%r15), %rax
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,8), %rcx
movq $0x0, (%rax)
movl $0xffffffff, 0x8(%rax) # imm = 0xFFFFFFFF
addq $0x18,... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::ARMParallelDSP::getAnalysisUsage(llvm::AnalysisUsage&) const | void getAnalysisUsage(AnalysisUsage &AU) const override {
FunctionPass::getAnalysisUsage(AU);
AU.addRequired<AssumptionCacheTracker>();
AU.addRequired<ScalarEvolutionWrapperPass>();
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
callq 0x1ba49de
leaq 0x48bafaa(%rip), %rsi # 0x5638eb8
movq %rbx, %rdi
callq 0x1ba4e4a
leaq 0x48bf4e7(%rip), %r14 # 0x563d404
movq %rbx, %rdi
movq %r14, %rsi
callq 0x1ba4e4a
leaq 0x48baeb9(%rip), %rsi # 0x5638de8
movq %rbx, %rdi
callq 0x1ba4e4a
leaq 0x48cf382(%rip)... | /Target/ARM/ARMParallelDSP.cpp |
bool (anonymous namespace)::ARMParallelDSP::IsNarrowSequence<16u>(llvm::Value*) | bool ARMParallelDSP::IsNarrowSequence(Value *V) {
if (auto *SExt = dyn_cast<SExtInst>(V)) {
if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
return false;
if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) {
// Check that this load could be paired.
return LoadPairs.count(Ld) ... | cmpb $0x45, (%rsi)
jne 0xd7fd6b
pushq %rbx
movq -0x20(%rsi), %rsi
movq 0x8(%rsi), %rax
movl $0xffffff00, %ecx # imm = 0xFFFFFF00
andl 0x8(%rax), %ecx
cmpl $0x1000, %ecx # imm = 0x1000
jne 0xd7fd6e
cmpb $0x3d, (%rsi)
jne 0xd7fd6e
movq %rdi, %rbx
movq 0x60(%rdi), %rdx
leaq 0x58(%rdi), %rcx
movq %rcx, %rax... | /Target/ARM/ARMParallelDSP.cpp |
llvm::SmallDenseMap<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>, 8u, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>>>::init(unsigned int) | void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %eax
movl %eax, %ecx
orl $0x1, %ecx
movl %ecx, (%rdi)
cmpl $0x9, %esi
jb 0xd85a20
movl %esi, %ebp
andl $-0x2, %eax
movl %eax, (%rbx)
movl %esi, %eax
shlq $0x3, %rax
leaq (%rax,%rax,8), %rdi
movl $0x8, %esi
callq 0x2085c34
movq %rax, 0x8(%rbx)
movl %ebp, 0x10... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>>* llvm::DenseMapBase<llvm::SmallDenseMap<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>, 8u, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SmallVector<llvm::Register... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl (%rdi), %edx
movl %edx, %ecx
shrl %ecx
movl $0x8, %esi
testb $0x1, %dl
jne 0xd85cc5
movl 0x10(%rbx), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xd85cfc
notl %ecx
addl %esi, %ecx
subl 0x... | /llvm/ADT/DenseMap.h |
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