name string | code string | asm string | file string |
|---|---|---|---|
char* llvm::hashing::detail::hash_combine_recursive_helper::combine_data<llvm::DILocation const*>(unsigned long&, char*, char*, llvm::DILocation const*) | char *combine_data(size_t &length, char *buffer_ptr, char *buffer_end, T data) {
if (!store_and_advance(buffer_ptr, buffer_end, data)) {
// Check for skew which prevents the buffer from being packed, and do
// a partial store into the buffer to fill it. This is only a concern
// with the variadic ... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rcx, %r14
movq %rdx, %r13
movq %rsi, %r15
movq %rdi, %rbx
movq %r8, (%rsp)
leaq 0x8(%rdx), %rax
cmpq %rcx, %rax
ja 0xd86269
movq (%rsp), %rcx
movq %rcx, (%r13)
movq %rax, %r13
cmpq %r14, %rax
jbe 0xd86302
movq %r14, %r12
subq %r13, %r12
movq ... | /llvm/ADT/Hashing.h |
isRegInClass(llvm::MachineOperand const&, llvm::TargetRegisterClass const*) | bool isReg() const { return OpKind == MO_Register; } | cmpb $0x0, (%rdi)
jne 0xd918b8
movl 0x4(%rdi), %eax
leal -0x1(%rax), %ecx
cmpl $0x3ffffffe, %ecx # imm = 0x3FFFFFFE
ja 0xd918b8
movq (%rsi), %rcx
movl %eax, %edx
shrl $0x3, %edx
movzwl 0x16(%rcx), %esi
cmpl %esi, %edx
jae 0xd918b8
movq 0x8(%rcx), %rcx
movzbl (%rcx,%rdx), %ecx
andl $0x7, %eax
btl %eax, %ecx
setb %... | /llvm/CodeGen/MachineOperand.h |
llvm::cl::opt<llvm::TPLoop::MemTransfer, false, llvm::cl::parser<llvm::TPLoop::MemTransfer>>::getValueExpectedFlagDefault() const | enum ValueExpected getValueExpectedFlagDefault() const {
// If there is an ArgStr specified, then we are of the form:
//
// -opt=O2 or -opt O2 or -optO2
//
// In which case, the value is required. Otherwise if an arg str has not
// been specified, we are of the form:
//
// -... | movq 0xa0(%rdi), %rcx
xorl %eax, %eax
cmpq $0x1, 0x18(%rcx)
adcl $0x2, %eax
retq
| /llvm/Support/CommandLine.h |
llvm::SmallVectorTemplateBase<llvm::cl::parser<llvm::TPLoop::MemTransfer>::OptionInfo, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r14
movq %rsp, %r8
movl $0x30, %ecx
movq %r14, %rsi
callq 0x208eb04
movq %rax, %r15
movl 0x8(%rbx), %ecx
testq %rcx, %rcx
je 0xd964eb
movq (%rbx), %rax
leaq (%rcx,%rcx,2), %rcx
shlq $0x4, %rcx
addq %rax, %rcx
xorl %... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::ARMSLSHardening::ARMSLSHardening() | ARMSLSHardening() : MachineFunctionPass(ID) {
initializeARMSLSHardeningPass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4887708(%rip), %rcx # 0x561dce4
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4703b87(%rip), %rax # 0x549a180
movq %rax, (%rdi)
callq 0x1baa13c
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x48876... | /Target/ARM/ARMSLSHardening.cpp |
llvm::ARMBasicBlockUtils::adjustBBOffsetsAfter(llvm::MachineBasicBlock*) | void ARMBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
assert(BB->getParent() == &MF &&
"Basic block is not a child of the current function.\n");
unsigned BBNum = BB->getNumber();
LLVM_DEBUG(dbgs() << "Adjust block:\n"
<< " - name: " << BB->getName() << "\n"
<< ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq (%rdi), %rax
movq 0x70(%rax), %rcx
subq 0x68(%rax), %rcx
movl 0x18(%rsi), %r15d
shrq $0x3, %rcx
leal 0x1(%r15), %eax
movq %rcx, 0x8(%rsp)
cmpl %ecx, %eax
jae 0xd97ad5
movq %rdi, %rbx
leal 0x2(%r15), %ecx
movq %rcx, 0x10(%rsp)
movl %... | /Target/ARM/ARMBasicBlockInfo.cpp |
llvm::ARM::createFastISel(llvm::FunctionLoweringInfo&, llvm::TargetLibraryInfo const*) | FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) {
if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
return new ARMFastISel(funcInfo, libInfo);
return nullptr;
} | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r15
movq %rdi, %rbx
movq 0x8(%rdi), %rax
movq 0x10(%rax), %rdi
callq 0xc9f3f8
testb %al, %al
je 0xd9a464
movl $0xf0, %edi
callq 0x6ea880
movq %rax, %r14
movq %rax, %rdi
movq %rbx, %rsi
movq %r15, %rdx
xorl %ecx, %ecx
callq 0x1edfdee
leaq 0x4700198(%rip), %rax # 0x549a580
m... | /Target/ARM/ARMFastISel.cpp |
llvm::AVRAsmPrinter::printOperand(llvm::MachineInstr const*, unsigned int, llvm::raw_ostream&) | void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI);
break;
case... | pushq %rbx
subq $0x50, %rsp
movq %rcx, %rbx
movq 0x20(%rsi), %rcx
movl %edx, %edx
shlq $0x5, %rdx
leaq (%rcx,%rdx), %rax
movzbl (%rcx,%rdx), %ecx
leaq 0x283b1cb(%rip), %rdx # 0x35e7940
movslq (%rdx,%rcx,4), %rcx
addq %rdx, %rcx
jmpq *%rcx
movl 0x4(%rax), %eax
movq 0x318(%rdi), %rsi
movl %eax, %edi
callq 0x157dd8c
mov... | /Target/AVR/AVRAsmPrinter.cpp |
llvm::AVRAsmPrinter::PrintAsmOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) {
// Default asm printer can only deal with some extra codes,
// so try it first.
if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
return false;
c... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r8, %rbx
movq %rcx, %r13
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r14
callq 0x17a6918
testb %al, %al
je 0xdac9b8
movq 0x20(%r12), %rax
movl %r15d, %esi
shlq $0x5, %rsi
addq %rax, %rsi
testq %r13, %r13
je 0xdac991
movzbl (%r13),... | /Target/AVR/AVRAsmPrinter.cpp |
llvm::AVRTargetObjectFile::SelectSectionForGlobal(llvm::GlobalObject const*, llvm::SectionKind, llvm::TargetMachine const&) const | MCSection *AVRTargetObjectFile::SelectSectionForGlobal(
const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
// Global values in flash memory are placed in the progmem*.data section
// unless they already have a user assigned section.
const auto &AVRTM = static_cast<const AVRTargetMachin... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %rax
movl 0x8(%rax), %eax
shrl $0x8, %eax
decl %eax
cmpl $0x5, %eax
ja 0xdae116
testb $0x4, 0x23(%r14)
jne 0xdae116
movl %ebp, %eax
andb $-0x4, %al
cmpb $0x8, %al
je 0xdae0a9
movz... | /Target/AVR/AVRTargetObjectFile.cpp |
(anonymous namespace)::AVRExpandPseudo::expandLPMBELPMB(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, bool) | bool AVRExpandPseudo::expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM) {
MachineInstr &MI = *MBBI;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>()... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %ecx, %r13d
movq %rdx, %rbx
movq %rsi, %r15
movq 0x20(%rdx), %rax
movl 0x4(%rax), %ecx
movl %ecx, 0x4(%rsp)
movl 0x20(%rax), %ebp
movl 0x24(%rax), %ecx
movl %ecx, 0x14(%rsp)
xorl %r14d, %r14d
btl $0x18, %ebp
setae %sil
movq 0x20(%r1... | /Target/AVR/AVRExpandPseudoInsts.cpp |
std::enable_if<!std::is_same_v<llvm::BPFIRPeepholePass, llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>>, void>::type llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::addPass<llvm::BPFIRPeepholePass>(llvm::BPFIRPeepholePass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
pushq $0x10
popq %rdi
callq 0x6ea880
leaq 0x46d3660(%rip), %rcx # 0x549dfc8
movq %rcx, (%rax)
movq %rsp, %r14
movq %rax, (%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0x761fa8
movq (%r14), %rdi
testq %rdi, %rdi
je 0xdca98a
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x8, %... | /llvm/IR/PassManager.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, int>>, llvm::MachineBasicBlock*, int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, int>>::... | value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, Key);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xdd5e40
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xdd6203
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xdd5ed2
movq (%rbx), %rcx
movq %rcx, (%rax)
movl $0x0... | /llvm/ADT/DenseMap.h |
llvm::BTFTypeEnum::completeType(llvm::BTFDebug&) | void BTFTypeEnum::completeType(BTFDebug &BDebug) {
if (IsCompleted)
return;
IsCompleted = true;
BTFType.NameOff = BDebug.addString(ETy->getName());
DINodeArray Elements = ETy->getElements();
for (const auto Element : Elements) {
const auto *Enum = cast<DIEnumerator>(Element);
struct BTF::BTFEnu... | cmpb $0x0, 0x9(%rdi)
jne 0xdd7baa
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movb $0x1, 0x9(%rdi)
movq 0x20(%rdi), %rdi
movl $0x2, %esi
callq 0x8779f0
addq $0x1f8, %rbx # imm = 0x1F8
movq %rbx, %rdi
movq %rax, %rsi
callq 0xdd87fe
movl %eax, 0x... | /Target/BPF/BTFDebug.cpp |
llvm::BTFTypeEnum64::emitType(llvm::MCStreamer&) | void BTFTypeEnum64::emitType(MCStreamer &OS) {
BTFTypeBase::emitType(OS);
for (const auto &Enum : EnumValues) {
OS.emitInt32(Enum.NameOff);
OS.AddComment("0x" + Twine::utohexstr(Enum.Val_Lo32));
OS.emitInt32(Enum.Val_Lo32);
OS.AddComment("0x" + Twine::utohexstr(Enum.Val_Hi32));
OS.emitInt32(Enum... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %rbx
movq %rdi, %r14
callq 0xdd746c
movq 0x28(%r14), %r15
movq 0x30(%r14), %rax
cmpq %rax, %r15
je 0xdd7e9b
movq %rax, 0x8(%rsp)
movw $0xf03, %r14w # imm = 0xF03
movl (%r15), %esi
movq (%rbx), %rax
movq %rbx, %rdi
mo... | /Target/BPF/BTFDebug.cpp |
llvm::BTFKindDataSec::BTFKindDataSec(llvm::AsmPrinter*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>) | BTFKindDataSec::BTFKindDataSec(AsmPrinter *AsmPrt, std::string SecName)
: Asm(AsmPrt), Name(SecName) {
Kind = BTF::BTF_KIND_DATASEC;
BTFType.Info = Kind << 24;
BTFType.Size = 0;
} | pushq %rbx
movq %rdi, %rbx
movb $0x0, 0x9(%rdi)
leaq 0x46c66e1(%rip), %rax # 0x549ec50
movq %rax, (%rdi)
movq %rsi, 0x20(%rdi)
addq $0x28, %rdi
leaq 0x38(%rbx), %rax
movq %rax, 0x28(%rbx)
movq (%rdx), %rsi
movq 0x8(%rdx), %rdx
addq %rsi, %rdx
callq 0x75afb0
xorps %xmm0, %xmm0
movups %xmm0, 0x48(%rbx)
movq $0x0, 0x58(... | /Target/BPF/BTFDebug.cpp |
llvm::BTFKindDataSec::completeType(llvm::BTFDebug&) | void BTFKindDataSec::completeType(BTFDebug &BDebug) {
BTFType.NameOff = BDebug.addString(Name);
BTFType.Info |= Vars.size();
} | pushq %rbx
movq %rdi, %rbx
movq 0x28(%rdi), %rax
movq 0x30(%rdi), %rdx
leaq 0x1f8(%rsi), %rdi
movq %rax, %rsi
callq 0xdd87fe
movl %eax, 0x10(%rbx)
movq 0x50(%rbx), %rax
subq 0x48(%rbx), %rax
shrq $0x3, %rax
imull $0xaaaaaaab, %eax, %eax # imm = 0xAAAAAAAB
orl %eax, 0x14(%rbx)
popq %rbx
retq
nop
| /Target/BPF/BTFDebug.cpp |
llvm::BTFStringTable::addString(llvm::StringRef) | uint32_t BTFStringTable::addString(StringRef S) {
// Check whether the string already exists.
for (auto &OffsetM : OffsetToIdMap) {
if (Table[OffsetM.second] == S)
return OffsetM.first;
}
// Not find, add to the string table.
uint32_t Offset = Size;
OffsetToIdMap[Offset] = Table.size();
Table.pu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdx, %rbx
movq %rsi, 0x8(%rsp)
movq 0x20(%rdi), %r12
leaq 0x10(%rdi), %r15
cmpq %r15, %r12
sete %r13b
movq %rdi, 0x10(%rsp)
je 0xdd8882
movq 0x38(%rdi), %r14
movl 0x24(%r12), %eax
shlq $0x5, %rax
movq 0x8(%r14,%rax), %rdx
cmpq %rbx... | /Target/BPF/BTFDebug.cpp |
llvm::BTFDebug::addType(std::unique_ptr<llvm::BTFTypeBase, std::default_delete<llvm::BTFTypeBase>>, llvm::DIType const*) | uint32_t BTFDebug::addType(std::unique_ptr<BTFTypeBase> TypeEntry,
const DIType *Ty) {
TypeEntry->setId(TypeEntries.size() + 1);
uint32_t Id = TypeEntry->getId();
DIToIdMap[Ty] = Id;
TypeEntries.push_back(std::move(TypeEntry));
return Id;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
leaq 0x8(%rsp), %rsi
movq %rdx, (%rsi)
movq (%rbx), %rax
leaq 0x248(%rdi), %r14
movq 0x250(%rdi), %r15
subq 0x248(%rdi), %r15
shrq $0x3, %r15
incl %r15d
movl %r15d, 0xc(%rax)
addq $0x260, %rdi # imm = 0x260
callq 0xdde40e
movl %r15d, (%rax)
mo... | /Target/BPF/BTFDebug.cpp |
llvm::SmallVectorTemplateBase<llvm::MDString const*, true>::push_back(llvm::MDString const*) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0xdd9471
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x208ec4e
... | /llvm/ADT/SmallVector.h |
llvm::BTFDebug::processGlobals(bool) | void BTFDebug::processGlobals(bool ProcessingMapDef) {
// Collect all types referenced by globals.
const Module *M = MMI->getModule();
for (const GlobalVariable &Global : M->globals()) {
// Decide the section name.
StringRef SecName;
std::optional<SectionKind> GVKind;
if (!Global.isDeclarationFor... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movl %esi, 0x84(%rsp)
movq %rdi, 0x8(%rsp)
movq 0x10(%rdi), %rax
movq 0x990(%rax), %r13
movq 0x10(%r13), %r14
addq $0x8, %r13
cmpq %r13, %r14
je 0xddc74c
movq 0x8(%rsp), %rax
leaq 0x340(%rax), %rcx
movq %rcx, 0x68(%rsp)
leaq 0x348(%rax),... | /Target/BPF/BTFDebug.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>, llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>::FindAndConstruct(llvm::Value* const&... | value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, Key);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xde7f9a
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xde7f90
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xde802c
movq (%rbx), %rcx
movq %rcx, (%rax)
movq $0x0... | /llvm/ADT/DenseMap.h |
llvm::BPFInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool) const | void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
BuildM... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r9d, %ebx
movl %r8d, %ebp
movq %rcx, %r13
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leaq 0x46b7747(%rip), %rax # 0x549fb38
movq (%rax), %rdi
movl %r8d, %esi
movl %r9d, %edx
callq 0xccbf0a
testb %al, %al
je 0xde84bf
movq (%r... | /Target/BPF/BPFInstrInfo.cpp |
llvm::BPFInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool IsKill, int FI,
const TargetRegisterClass *RC,
c... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movl %r9d, 0x1c(%rsp)
movl %r8d, %r14d
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq 0xa0(%rsp), %rbx
movq $0x0, 0x10(%rsp)
leaq 0x30(%rsi), %rax
cmpq %rdx, %rax
je 0xde911f
leaq 0x38(%r15), %rsi
leaq 0x10(%rsp), %... | /Target/BPF/BPFInstrInfo.cpp |
llvm::BPFTargetLowering::ReplaceNodeResults(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const | void BPFTargetLowering::ReplaceNodeResults(
SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
const char *Msg;
uint32_t Opcode = N->getOpcode();
switch (Opcode) {
default:
report_fatal_error("unhandled custom legalization: " + Twine(Opcode));
case ISD::ATOMIC_LOAD_ADD:
case ISD:... | pushq %r15
pushq %r14
pushq %rbx
subq $0x80, %rsp
movq %rcx, %rbx
movl 0x18(%rsi), %eax
leal -0x14c(%rax), %ecx
cmpl $0x7, %ecx
ja 0xdf3f1e
movl $0xd7, %edx
btl %ecx, %edx
jae 0xdf3f1e
movq %rsi, %r14
leaq 0x27f8b6f(%rip), %rcx # 0x35ec9fc
leaq 0x27f8ba3(%rip), %r15 # 0x35eca37
cmpb $0x0, 0x4e0f3(%rdi)
cmovneq %rcx... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::LowerSELECT_CC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue TrueV = Op.getOperand(2);
SDValue FalseV = Op.getOperand(3);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDLoc DL(Op);
if (!getHas... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rcx, 0x38(%rsp)
movl %edx, 0x24(%rsp)
movq %rsi, %r14
movq %rdi, %r12
movq 0x28(%rsi), %rax
movq (%rax), %rbx
movl 0x8(%rax), %ebp
movq 0x28(%rax), %r13
movl 0x30(%rax), %ecx
movl %ecx, 0x10(%rsp)
movups 0x50(%rax), %xmm0
movaps %x... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::EmitInstrWithCustomInserter(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const {
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
unsigned Opc = MI.getOpcode();
bool isS... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rdx, %r13
movq %rsi, %r15
movq %rdi, %rbx
movq 0x20(%rdx), %rax
movq 0x10(%rax), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x40(%rsp)
movq 0x38(%r15), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xdf6661
leaq 0x10(%rsp... | /Target/BPF/BPFISelLowering.cpp |
llvm::HexagonAsmPrinter::runOnMachineFunction(llvm::MachineFunction&) | bool runOnMachineFunction(MachineFunction &Fn) override {
Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
const bool Modified = AsmPrinter::runOnMachineFunction(Fn);
// Emit the XRay table for this function.
emitXRayTable();
return Modified;
} | pushq %rbx
movq %rdi, %rbx
movq 0x10(%rsi), %rax
movq %rax, 0x318(%rdi)
movq (%rdi), %rax
callq *0xb8(%rax)
movq %rbx, %rdi
callq 0x17967da
movq %rbx, %rdi
callq 0x179dd7c
xorl %eax, %eax
popq %rbx
retq
| /Target/Hexagon/HexagonAsmPrinter.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [23], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [23], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x465899... | /llvm/Support/CommandLine.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [15], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [15], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x46588d... | /llvm/Support/CommandLine.h |
llvm::HexagonInstrInfo::findLoopInstr(llvm::MachineBasicBlock*, unsigned int, llvm::MachineBasicBlock*, llvm::SmallPtrSet<llvm::MachineBasicBlock*, 8u>&) const | MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
unsigned EndLoopOp, MachineBasicBlock *TargetBB,
SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
unsigned LOOPi;
unsigned LOOPr;
if (EndLoopOp == Hexagon::ENDLOOP0) {
LOOPi = Hexagon::J2_loop0i;
LOOPr = Hexagon::J2_loop... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r8, 0x8(%rsp)
movq %rcx, 0x10(%rsp)
movl %edx, %ebp
movq %rdi, 0x18(%rsp)
xorl %eax, %eax
cmpl $0x141, %edx # imm = 0x141
setne %cl
movq 0x40(%rsi), %r15
movq %rsi, 0x28(%rsp)
movq 0x48(%rsi), %rdx
movq %rdx, 0x20(%rsp)
... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const | bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) cons... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
xorl %r15d, %r15d
movq %r15, (%rdx)
movq %r15, (%rcx)
movl $0x0, 0x8(%r8)
leaq 0x30(%rsi), %r13
movq 0x38(%rsi), %rax
cmpq %rax, %r13
je 0xdf9f91
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %rbp
movq %r13, %rdx
movq (%rdx), %rdx
andq $-0x... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned int) const | bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
return Opcode == Hexagon::J2_jumpt ||
Opcode == Hexagon::J2_jumptpt ||
Opcode == Hexagon::J2_jumpf ||
Opcode == Hexagon::J2_jumpfpt ||
Opcode == Hexagon::J2_jumptnew ||
Opcode == Hexagon::... | leal -0x52b(%rsi), %ecx
cmpl $0x1a, %ecx
setb %dl
movl $0x3c0000f, %eax # imm = 0x3C0000F
shrl %cl, %eax
andb %dl, %al
retq
| /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::ArrayRef<llvm::MachineOperand>, llvm::DebugLoc const&, int*) const | unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
const DebugLoc &D... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %r8, %r12
movq %rcx, %r13
movq %rdx, %rbp
movq %rsi, %r14
movq %rdi, (%rsp)
movl $0x541, %r15d # imm = 0x541
testq %r9, %r9
je 0xdfa150
cmpb $0x1, (%r12)
jne 0xdfa150
movl 0x10(%r12), %r15d
movq 0... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::getCondOpcode(int, bool) const | int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
enum Hexagon::PredSense inPredSense;
inPredSense = invertPredicate ? Hexagon::PredSense_false :
Hexagon::PredSense_true;
int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
if (CondOpcode >= 0) //... | xorb $0x1, %dl
movzbl %dl, %eax
movzwl %si, %edi
movl %eax, %esi
jmp 0xdf929b
| /Target/Hexagon/HexagonInstrInfo.cpp |
GetSymbolRef(llvm::MachineOperand const&, llvm::MCSymbol const*, llvm::HexagonAsmPrinter&, bool) | static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
HexagonAsmPrinter &Printer, bool MustExtend) {
MCContext &MC = Printer.OutContext;
const MCExpr *ME;
// Populate the relocation type based on Hexagon target flags
// set on an operand
MCSymbolRefExpr... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %ebx
movq %rsi, %rax
movq %rdi, %r15
movq 0x48(%rdx), %r14
movl (%rdi), %edx
movl %edx, %esi
shrl $0x8, %esi
andl $0xf7f, %esi # imm = 0xF7F
decl %esi
xorl %ecx, %ecx
cmpb $0x1, %dl
movl $0x0, %edx
sbbl %edx, %edx
orl %esi, %edx
cmpl $0x9, %ed... | /Target/Hexagon/HexagonMCInstLower.cpp |
bool llvm::any_of<llvm::LiveInterval&, llvm::HexagonRegisterInfo::shouldCoalesce(llvm::MachineInstr*, llvm::TargetRegisterClass const*, unsigned int, llvm::TargetRegisterClass const*, unsigned int, llvm::TargetRegisterClass const*, llvm::LiveIntervals&) const::$_0>(llvm::LiveInterval&, llvm::HexagonRegisterInfo::should... | Callable() = default; | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq (%rdi), %rbx
movl 0x8(%rdi), %r12d
leaq (%r12,%r12,2), %rax
leaq (%rbx,%rax,8), %r15
cmpq $0x4, %r12
jae 0xe07370
movq %r15, %rcx
subq %rbx, %rcx
sarq $0x3, %rcx
movabsq $-0x5555555555555555, %rax # imm = 0xAAAAAAAAAAAAAAAB
imulq %rcx, %rax
cmpq $0x1, %rax
je ... | /llvm/ADT/STLExtras.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [24], llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [24], llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%rbx)
movb %bpl, 0x91(%rbx)
leaq 0x464a33c(%rip), %rax # 0x5451ec0
movq %rax... | /llvm/Support/CommandLine.h |
llvm::HexagonSubtarget::isHVXVectorType(llvm::EVT, bool) const | bool HexagonSubtarget::isHVXVectorType(EVT VecTy, bool IncludeBool) const {
if (!VecTy.isSimple())
return false;
if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
return false;
MVT ElemTy = VecTy.getSimpleVT().getVectorElementType();
if (!IncludeBool && ElemTy == MVT::i1)
return fal... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movb %sil, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
leal -0x11(%rsi), %eax
cmpb $-0x54, %al
ja 0xe08924
leal 0x77(%rsi), %eax
xorl %r15d, %r15d
cmpb $0x35, %al
jb 0xe08927
movq %rdi, %rbx
cmpl $0x0, 0x13c(%rdi)
jle 0xe08927
movl %ecx, %ebp
movzb... | /Target/Hexagon/HexagonSubtarget.cpp |
llvm::HexagonSubtarget::restoreLatency(llvm::SUnit*, llvm::SUnit*) const | void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
MachineInstr *SrcI = Src->getInstr();
for (auto &I : Src->Succs) {
if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
continue;
Register DepR = I.getReg();
int DefIdx = -1;
for (unsigned OpNum = 0; OpNum < SrcI->getNumOperand... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x20(%rsp)
movl 0x80(%rsi), %esi
testq %rsi, %rsi
je 0xe09e96
movq %rdx, %rbx
movq 0x20(%rsp), %rax
movq (%rax), %r12
movq 0x78(%rax), %rdi
shlq $0x4, %rsi
addq %rdi, %rsi
movq 0x18(%rsp), %rax
leaq 0x1a8... | /Target/Hexagon/HexagonSubtarget.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [19], llvm::cl::OptionHidden, llvm::cl::initializer<bool>>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [19], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x6ea2b0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x206a93a
movl (%r14), %eax
movzwl 0xa(%r12), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx
orl %eax, %ecx... | /llvm/Support/CommandLine.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::SUnit*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SUnit*>>, unsigned int, llvm::SUnit*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SUnit*>>::moveFromOldBuckets(llvm::detail::Den... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xe0ac47
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x3, %ecx
negq %rcx
addq %rdx,... | /llvm/ADT/DenseMap.h |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [13], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(char const (&) [13], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x4646b64(%rip), %rax # 0x5451e80
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [14], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [14], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x464647... | /llvm/Support/CommandLine.h |
llvm::TargetTransformInfo::Model<llvm::HexagonTTIImpl>::getRegisterClassName(unsigned int) const | const char *getRegisterClassName(unsigned ClassID) const {
switch (ClassID) {
default:
return "Generic::Unknown Register Class";
case 0:
return "Generic::ScalarRC";
case 1:
return "Generic::VectorRC";
}
} | cmpl $0x1, %esi
leaq 0x235d243(%rip), %rax # 0x316b5f7
leaq 0x235d20a(%rip), %rcx # 0x316b5c5
cmoveq %rax, %rcx
testl %esi, %esi
leaq 0x235d21d(%rip), %rax # 0x316b5e5
cmovneq %rcx, %rax
retq
nop
| /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::BasicTTIImplBase<llvm::HexagonTTIImpl>::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) | std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) {
return BaseT::simplifyDemandedVect... | pushq %r14
pushq %rbx
subq $0x38, %rsp
movq 0x58(%rsp), %rbx
movl 0x8(%rcx), %eax
movl %eax, 0x8(%rsp)
cmpl $0x40, %eax
ja 0xe0f045
movq (%rcx), %rax
movq %rax, (%rsp)
jmp 0xe0f050
movq %rsp, %rdi
movq %rcx, %rsi
callq 0x205f300
xorps %xmm0, %xmm0
movaps %xmm0, 0x20(%rsp)
movaps %xmm0, 0x10(%rsp)
movq 0x10(%rbx), %rax
... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::HexagonTargetObjectFile::Initialize(llvm::MCContext&, llvm::TargetMachine const&) | void HexagonTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
SmallDataSection =
getContext().getELFSection(".sdata", ELF::SHT_PROGBITS,
ELF::SHF_WRITE | ELF::SHF_ALLOC |
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
callq 0x1a27dc6
movq 0x388(%rbx), %rdi
leaq 0x2a2f151(%rip), %rax # 0x3842c1d
leaq 0x8(%rsp), %r14
movq %rax, (%r14)
movw $0x103, %bp # imm = 0x103
movw %bp, 0x20(%r14)
movw $0x101, %r13w # imm = 0... | /Target/Hexagon/HexagonTargetObjectFile.cpp |
isSmallDataSection(llvm::StringRef) | static bool isSmallDataSection(StringRef Sec) {
// sectionName is either ".sdata" or ".sbss". Looking for an exact match
// obviates the need for checks for section names such as ".sdatafoo".
if (Sec == ".sdata" || Sec == ".sbss" || Sec == ".scommon")
return true;
// If either ".sdata." or ".sbss." is a sub... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq %rdi, 0x8(%rsp)
movq %rsi, 0x10(%rsp)
cmpq $0x5, %rsi
je 0xe1495b
cmpq $0x8, %rbx
je 0xe14977
cmpq $0x6, %rbx
jne 0xe1498d
leaq 0x2a2e2e1(%rip), %rsi # 0x3842c1d
movq %r14, %rdi
movq %rbx, %rdx
callq 0x6eabe0
testl %eax, %eax
je 0xe149ec
cmpq... | /Target/Hexagon/HexagonTargetObjectFile.cpp |
llvm::DenseMap<unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x8(%rdi), %eax
movl 0x10(%rdi), %esi
testl %eax, %eax
je 0xe185b6
decl %eax
je 0xe185ba
bsrl %eax, %eax
xorl $0x1f, %eax
jmp 0xe185bf
xorl %ebp, %ebp
jmp 0xe185d5
movl $0x20, %eax
movb $0x21, %cl
subb %al, %cl
movl $0x1, %eax
shll %cl, %eax
cmpl $0x41, %eax
movl $0... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [19], llvm::cl::OptionHidden>(char const (&) [19], llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%rbx)
movb %bpl, 0x91(%rbx)
leaq 0x463900e(%rip), %rax # 0x5451ec0
movq %rax, 0x88(%rbx)
lea... | /llvm/Support/CommandLine.h |
(anonymous namespace)::AlignVectors::getAddrInfo(llvm::Instruction&) const | auto AlignVectors::getAddrInfo(Instruction &In) const
-> std::optional<AddrInfo> {
if (auto *L = isCandidate<LoadInst>(&In))
return AddrInfo(HVC, L, L->getPointerOperand(), L->getType(),
L->getAlign());
if (auto *S = isCandidate<StoreInst>(&In))
return AddrInfo(HVC, S, S->getPointerO... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
cmpb $0x3d, (%rdx)
jne 0xe2045b
movzwl 0x2(%r15), %eax
andl $0x301, %eax # imm = 0x301
jne 0xe2045b
movq 0x30(%r14), %rsi
movq -0x20(%r15), %rcx
movq 0x8(%r15), %r8
jmp 0xe2047d
cmpb $0x3e, (%r15)
jne 0xe204a2
movzwl 0x2(%r15), ... | /Target/Hexagon/HexagonVectorCombine.cpp |
llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Instruction*>>::operator=(llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instru... | DenseMap& operator=(DenseMap &&other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
init(0);
swap(other);
return *this;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
movl 0x10(%rbx), %esi
shlq $0x4, %rsi
movl $0x8, %edx
callq 0x2085c39
xorl %eax, %eax
movl %eax, 0x10(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movq (%r14), %rcx
movq %rcx, (%rbx)
movq $0x0, (%r14)
movl 0x8(%r14), %ecx
movl %ecx, 0x8... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AlignVectors::makeTestIfUnaligned(llvm::IRBuilderBase&, llvm::Value*, int) const | auto AlignVectors::makeTestIfUnaligned(IRBuilderBase &Builder, Value *AlignVal,
int Alignment) const -> Value * {
auto *AlignTy = AlignVal->getType();
Value *And = Builder.CreateAnd(
AlignVal, ConstantInt::get(AlignTy, Alignment - 1), "and");
Value *Zero = ConstantInt:... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %r15
decl %edx
movslq %edx, %rsi
movq %r15, %rdi
xorl %edx, %edx
callq 0x1af5402
leaq 0x3df46cc(%rip), %rcx # 0x4c17b10
leaq 0x8(%rsp), %r12
movq %rcx, (%r12)
movw $0x103, %bp # imm = 0x... | /Target/Hexagon/HexagonVectorCombine.cpp |
(anonymous namespace)::AlignVectors::ByteSpan::values() const | auto AlignVectors::ByteSpan::values() const -> SmallVector<Value *, 8> {
SmallVector<Value *, 8> Values(Blocks.size());
for (int i = 0, e = Blocks.size(); i != e; ++i)
Values[i] = Blocks[i].Seg.Val;
return Values;
} | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq 0x8(%rsi), %rsi
subq (%rbx), %rsi
movq %rdi, %r14
sarq $0x3, %rsi
movabsq $-0x5555555555555555, %r15 # imm = 0xAAAAAAAAAAAAAAAB
imulq %r15, %rsi
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, 0x8(%rdi)
callq 0x... | /Target/Hexagon/HexagonVectorCombine.cpp |
llvm::HexagonPacketizerList::isLegalToPacketizeTogether(llvm::SUnit*, llvm::SUnit*) | bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
assert(SUI->getInstr() && SUJ->getInstr());
MachineInstr &I = *SUI->getInstr();
MachineInstr &J = *SUJ->getInstr();
// Clear IgnoreDepMIs when Packet starts.
if (CurrentPacketMIs.size() == 1)
IgnoreDepMIs.clear();
Machine... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq (%rsi), %r12
movq (%rdx), %r13
movq 0x30(%rdi), %rax
subq 0x28(%rdi), %rax
cmpq $0x8, %rax
jne 0xe2bc38
movq 0xa8(%rbx), %rax
cmpq %rax, 0xb0(%rbx)
je 0xe2bc38
movq %rax, 0xb0(%rbx)
mo... | /Target/Hexagon/HexagonVLIWPacketizer.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [20], llvm::cl::OptionHidden, llvm::cl::initializer<unsigned int>>(char const (&) [20], llvm::cl::OptionHidden const&, llvm::cl::initializer<unsigned int> const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movl $0x0, 0x80(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%rbx)
movb $0x0, 0x94(%rbx)
leaq 0x46244a7(%rip), %rax # 0x5451e80
movq %rax, 0x88(%rbx)
lea... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonBitSimplify::replaceReg(llvm::Register, llvm::Register, llvm::MachineRegisterInfo&) | bool HexagonBitSimplify::replaceReg(Register OldR, Register NewR,
MachineRegisterInfo &MRI) {
if (!OldR.isVirtual() || !NewR.isVirtual())
return false;
auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
decltype(End) NextI;
for (auto I = Begin; I != End; I = NextI) {
... | pushq %r15
pushq %r14
pushq %rbx
movl %esi, %ebx
testl %esi, %edi
jns 0xe3116f
movl %edi, %esi
movq %rdx, %rdi
callq 0x8eed0c
movq %rax, %r14
testq %rax, %rax
je 0xe31167
movq %r14, %r15
movq %r15, %rdi
movq 0x18(%r15), %r15
testq %r15, %r15
je 0xe3115b
testb $0x1, 0x3(%r15)
jne 0xe3114b
movl %ebx, %esi
callq 0x18f9732... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::HexagonBitSimplify::getSubregMask(llvm::BitTracker::RegisterRef const&, unsigned int&, unsigned int&, llvm::MachineRegisterInfo&) | bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI) {
const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
if (RR.Sub == 0) {
Begin = 0;
Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC);
return true;
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movl (%rdi), %eax
andl $0x7fffffff, %eax # imm = 0x7FFFFFFF
movq 0x38(%rcx), %rdx
shlq $0x4, %rax
movq (%rdx,%rax), %r12
andq $-0x8, %r12
cmpl $0x0, 0x4(%rdi)
movl $0x0, (%rsi)
je 0xe3393c
movq %rsi, %r14
movq %rdi, %r15
movq (%r12), %ra... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::BitSimplification::genExtractHalf(llvm::MachineInstr*, llvm::BitTracker::RegisterRef, llvm::BitTracker::RegisterCell const&) | bool BitSimplification::genExtractHalf(MachineInstr *MI,
BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) {
RegHalf L;
// Check for halfword in low 16 bits, zeros elsewhere.
if (!matchHalf(RD.Reg, RC, 0, L) || !HBS::isZero(RC, 16, 16))
return false;
unsigned Opc = MI->getOpcode();
Ma... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r13
movq %rdi, %r14
leaq 0x28(%rsp), %r8
movq $0x0, (%r8)
xorl %ebp, %ebp
movl %r15d, %esi
movq %rcx, %rdx
xorl %ecx, %ecx
callq 0xe37d4a
testb %al, %al
je 0xe36e5f
movq (%rbx), %rax
cmpl $0x1,... | /Target/Hexagon/HexagonBitSimplify.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, unsigned int>>, llvm::MachineBasicBlock*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::... | value_type& FindAndConstruct(KeyT &&Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, std::move(Key));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xab9f28
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xe3ffe5
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xab9fba
movq (%rbx), %rcx
movq %rcx, (%rax)
movl $0x0... | /llvm/ADT/DenseMap.h |
llvm::createHexagonConstExtenders() | FunctionPass *llvm::createHexagonConstExtenders() {
return new HexagonConstExtenders();
} | pushq %rax
movl $0x90, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x47dd30d(%rip), %rdx # 0x5622694
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x465f4bc(%rip), %rdx # 0x54a4860
movq %rdx, (%rax)
movups %xmm0, 0x38(%rax)
movup... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::RangeTree::update((anonymous namespace)::RangeTree::Node*) | Node *update(Node *N) {
assert(N != nullptr);
N->Height = 1 + std::max(height(N->Left), height(N->Right));
if (N->Left)
N->MaxEnd = std::max(N->MaxEnd, N->Left->MaxEnd);
if (N->Right)
N->MaxEnd = std::max(N->MaxEnd, N->Right->MaxEnd);
return N;
} | movq %rdi, %rax
movq 0x18(%rdi), %rcx
xorl %esi, %esi
movl $0x0, %edi
testq %rcx, %rcx
je 0xe4b185
movl (%rcx), %edi
movq 0x20(%rax), %rdx
testq %rdx, %rdx
je 0xe4b190
movl (%rdx), %esi
cmpl %esi, %edi
cmoval %edi, %esi
incl %esi
movl %esi, (%rax)
testq %rcx, %rcx
je 0xe4b1ac
movl 0x8(%rax), %esi
movl 0x8(%rcx), %ecx
c... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::HexagonConstEvaluator::evaluateHexLogical(llvm::MachineInstr const&, (anonymous namespace)::MachineConstPropagator::CellMap const&, (anonymous namespace)::MachineConstPropagator::CellMap&) | bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
const CellMap &Inputs, CellMap &Outputs) {
unsigned Opc = MI.getOpcode();
if (MI.getNumOperands() != 3)
return false;
const MachineOperand &Src1 = MI.getOperand(1);
const MachineOperand &Src2 = MI.getOperand(2);
RegisterSubReg R1... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %rcx, 0x120(%rsp)
movzwl 0x28(%rsi), %eax
movzbl 0x2a(%rsi), %ecx
shll $0x10, %ecx
orl %eax, %ecx
cmpl $0x3, %ecx
jne 0xe5026d
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
movzwl 0x44(%rsi), %ecx
movq 0x... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::MachineConstEvaluator::evaluateCMPri(unsigned int, (anonymous namespace)::RegisterSubReg const&, llvm::APInt const&, (anonymous namespace)::MachineConstPropagator::CellMap const&, bool&) | bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
const APInt &A2, const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS;
if (!getCell(R1, Inputs, LS))
return false;
if (LS.isProperty())
return evaluateCMPpi(Cmp, LS.properties(), A2, Resu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %r9, %r14
movq %rcx, 0x10(%rsp)
movl %esi, 0xc(%rsp)
leaq 0x30(%rsp), %rcx
movb (%rcx), %al
andb $-0x40, %al
incb %al
movb %al, (%rcx)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%rcx)
movups %xmm0, 0x18(%rcx)
movq %rdx, %rsi
movq %r8, %rd... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::LatticeCell::meet((anonymous namespace)::LatticeCell const&) | bool LatticeCell::meet(const LatticeCell &L) {
bool Changed = false;
if (L.isBottom())
Changed = setBottom();
if (isBottom() || L.isTop())
return Changed;
if (isTop()) {
*this = L;
// L can be neither Top nor Bottom, so *this must have changed.
return true;
}
// Top/bottom cases covered... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movb (%rsi), %al
andb $0x3, %al
cmpb $0x2, %al
jne 0xe522f3
movb (%rbx), %al
movl %eax, %ecx
andb $0x3, %cl
cmpb $0x2, %cl
setne %bpl
andb $-0x40, %al
orb $0x2, %al
movb %al, (%rbx)
jmp 0xe522f5
xorl %ebp, %ebp
movb (%rbx), %al
andb ... | /Target/Hexagon/HexagonConstPropagation.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::MachineInstr*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MachineInstr*>>, unsigned int, llvm::MachineInstr*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MachineInstr*>>::FindAndC... | value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, Key);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xe574d6
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xe5792c
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xe5755a
movl (%rbx), %ecx
movl %ecx, (%rax)
movq $0x0... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonEarlyIfConversion::updatePhiNodes(llvm::MachineBasicBlock*, (anonymous namespace)::FlowPattern const&) | void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
const FlowPattern &FP) {
// Visit all PHI nodes in the WhereB block and generate MUX instructions
// in the split block. Update the PHI nodes with the values of the MUX.
auto NonPHI = WhereB->getFirstNonPHI();
for (auto I = WhereB->b... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, 0x58(%rsp)
movq %rsi, %rdi
callq 0x189fea6
movq 0x38(%r14), %r12
movq %rax, 0x68(%rsp)
cmpq %rax, %r12
je 0xe5a605
movq %rbx, %rdx
movq %rbx, 0x20(%rsp)
movzwl 0x28(%r12), %eax
movzbl 0x2a(%r12)... | /Target/Hexagon/HexagonEarlyIfConv.cpp |
(anonymous namespace)::HexagonExpandCondsets::updateLiveness(std::set<llvm::Register, std::less<llvm::Register>, std::allocator<llvm::Register>> const&, bool, bool, bool) | void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
bool Recalc, bool UpdateKills,
bool UpdateDeads) {
UpdateKills |= UpdateDeads;
for (Register R : RegSet) {
if (!R.isVirtual()) {
assert(R.isPhy... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %edx, 0x4(%rsp)
movq %rsi, %r14
movq 0x18(%rsi), %r12
addq $0x8, %r14
cmpq %r14, %r12
je 0xe5c1f2
movl %ecx, %ebp
movq %rdi, %r15
movl %ecx, (%rsp)
movl 0x20(%r12), %r13d
testl %r13d, %r13d
jns 0xe5c1de
cmpb $0x0, 0x4(%rsp)
je 0xe5c13e
mo... | /Target/Hexagon/HexagonExpandCondsets.cpp |
llvm::DenseMap<llvm::VNInfo*, llvm::VNInfo*, llvm::DenseMapInfo<llvm::VNInfo*, void>, llvm::detail::DenseMapPair<llvm::VNInfo*, llvm::VNInfo*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonFixupHwLoops::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
return fixupLoopInstrs(MF);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %rbx
movq (%rsi), %rsi
callq 0x1ba4a72
testb %al, %al
je 0xe5e624
xorl %r12d, %r12d
jmp 0xe5e981
xorps %xmm0, %xmm0
movaps %xmm0, 0x50(%rsp)
movl $0x0, 0x60(%rsp)
movq 0x10(%rbx), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq ... | /Target/Hexagon/HexagonFixupHwLoops.cpp |
llvm::DenseMap<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<unsigned int, unsigned short>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<unsigned int, unsigne... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::BitVector::test(llvm::BitVector const&) const | size_t size() const { return Size; } | movl 0x8(%rdi), %ecx
movl 0x8(%rsi), %eax
cmpl %ecx, %eax
movl %ecx, %edx
cmovbl %eax, %edx
testl %edx, %edx
je 0xe71d64
movq (%rdi), %r8
movq (%rsi), %rsi
cmpq %rax, %rcx
cmovbq %rcx, %rax
xorl %r9d, %r9d
movq (%rsi,%r9,8), %r10
notq %r10
testq %r10, (%r8,%r9,8)
jne 0xe71d89
incq %r9
cmpl %r9d, %eax
jne 0xe71d4d
jmp 0... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::IFOrdering::stats((anonymous namespace)::RegisterSet const&, unsigned int&, unsigned int&, unsigned int&) const | void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
unsigned &Sum) const {
for (unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) {
UnsignedMap::const_iterator F = UseC.find(R);
assert(F != UseC.end());
unsigned UC = F->second;
if (UC == 0)
Zero++;
Sum += ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbx
movq %rcx, 0x10(%rsp)
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl 0x40(%rsi), %edx
xorl %ebp, %ebp
movq %rsi, %rdi
xorl %esi, %esi
movl $0x1, %ecx
callq 0x931bda
movl %eax, %ecx
orl $0x80000000, %ecx # imm =... | /Target/Hexagon/HexagonGenInsert.cpp |
llvm::createHexagonGenMux() | FunctionPass *llvm::createHexagonGenMux() {
return new HexagonGenMux();
} | pushq %rax
movl $0x48, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x47b0fac(%rip), %rdx # 0x5623ff4
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x463230b(%rip), %rcx # 0x54a5370
movq %rcx, (%rax)
movups %xmm0, 0x38(%rax)
popq ... | /Target/Hexagon/HexagonGenMux.cpp |
(anonymous namespace)::HexagonHardwareLoops::createPreheaderForLoop(llvm::MachineLoop*) | MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
MachineLoop *L) {
if (MachineBasicBlock *TmpPH = MLI->findLoopPreheader(L, SpecPreheader))
return TmpPH;
if (!HWCreatePreheader)
return nullptr;
MachineBasicBlock *Header = L->getHeader();
MachineBasicBlock *Latch = L->getLoopLatch(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x158, %rsp # imm = 0x158
movq %rsi, %rbx
movq %rdi, %r13
movq 0x38(%rdi), %rdi
movzbl 0x47aad20(%rip), %edx # 0x5624140
xorl %ecx, %ecx
callq 0x18f58c6
movq %rax, %rbp
testq %rax, %rax
je 0xe79437
movq %rbp, %r12
jmp 0xe79c17
cmpb $0x... | /Target/Hexagon/HexagonHardwareLoops.cpp |
llvm::HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(llvm::HexagonTargetMachine&, llvm::CodeGenOptLevel) | HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
CodeGenOptLevel OptLevel)
: SelectionDAGISelLegacy(
ID, std::make_unique<HexagonDAGToDAGISel>(tm, OptLevel)) {} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rbx
movl $0x1f8, %edi # imm = 0x1F8
callq 0x6ea880
movq %rax, %r15
movq %rax, %rdi
movq %r14, %rsi
movl %ebp, %edx
callq 0xe86b78
movq %rsp, %r14
movq %r15, (%r14)
leaq 0x47a6434(%rip), %rsi # 0x5624488
movq ... | /Target/Hexagon/HexagonISelDAGToDAG.cpp |
(anonymous namespace)::LeafPrioQueue::pop() | WeightedLeaf pop() {
if (HaveConst) {
HaveConst = false;
return ConstElt;
}
std::pop_heap(Q.begin(), Q.end(), WeightedLeaf::Compare);
return Q.pop_back_val();
} | movq %rdi, %rax
cmpb $0x1, 0xd0(%rsi)
jne 0xe8615f
movb $0x0, 0xd0(%rsi)
movq 0xe8(%rsi), %rcx
movq %rcx, 0x10(%rax)
movups 0xd8(%rsi), %xmm0
movups %xmm0, (%rax)
retq
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movl 0x8(%rsi), %r8d
cmpq $0x2, %r8
jb 0xe86300
movq (%rsi), %rcx
shlq $0x3, %r8
leaq (%r8,%r8,2)... | /Target/Hexagon/HexagonISelDAGToDAG.cpp |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::Value const*, int, 4u, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, int>>, llvm::Value const*, int, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, int>>::clear() | unsigned getNumEntries() const {
return NumEntries;
} | movl (%rdi), %eax
cmpl $0x1, %eax
ja 0xe865b3
cmpl $0x0, 0x4(%rdi)
je 0xe866a8
leal (%rax,%rax), %edx
andl $-0x4, %edx
movl $0x4, %ecx
testb $0x1, %al
jne 0xe865c5
movl 0x10(%rdi), %ecx
cmpl %ecx, %edx
setae %dl
cmpl $0x41, %ecx
setb %sil
orb %dl, %sil
je 0xe87a9a
testb $0x1, %al
jne 0xe865e4
movq 0x8(%rdi), %rax
jmp 0... | /llvm/ADT/DenseMap.h |
llvm::SmallDenseMap<llvm::SDNode*, int, 4u, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, int>>::init(unsigned int) | void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %eax
movl %eax, %ecx
orl $0x1, %ecx
movl %ecx, (%rdi)
cmpl $0x5, %esi
jb 0xe86c00
movl %esi, %ebp
andl $-0x2, %eax
movl %eax, (%rbx)
movl %esi, %edi
shlq $0x4, %rdi
movl $0x8, %esi
callq 0x2085c34
movq %rax, 0x8(%rbx)
movl %ebp, 0x10(%rbx)
leaq 0x8(%rbx), %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::Value const*, int, 4u, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, int>>, llvm::Value const*, int, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, int>>::moveFromOldBuckets(llvm::de... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rdi), %rax
andl $0x1, (%rdi)
movl $0x0, 0x4(%rdi)
cmoveq 0x8(%rdi), %rax
movl $0x4, %ecx
cmovel 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xe8751c
movl %ecx, %ecx
movabsq $0xfffffffffffffff, %rdx... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<llvm::SDValue, int>* llvm::DenseMapBase<llvm::SmallDenseMap<llvm::SDValue, int, 4u, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, int>>, llvm::SDValue, int, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, int>>::InsertInt... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl (%rdi), %edx
movl %edx, %ecx
shrl %ecx
movl $0x4, %esi
testb $0x1, %dl
jne 0xe87817
movl 0x10(%rbx), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xe87851
notl %ecx
addl %esi, %ecx
subl 0x... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::SDValue, int, 4u, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, int>>, llvm::SDValue, int, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseMapPair<llvm::SDValue, int>>::FindAndConstruct(llvm::SDValue&&) | value_type& FindAndConstruct(KeyT &&Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, std::move(Key));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xe87734
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xe87a8f
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xe877f2
movq (%rbx), %rcx
movq %rcx, (%rax)
movl 0x8(... | /llvm/ADT/DenseMap.h |
llvm::SmallDenseMap<llvm::Value const*, int, 4u, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, int>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldSize = this->size();
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldSize) {
NewNumBuckets = 1 << (Log2_32_Ceil(OldSize) + 1);
if (NewNumBuckets > InlineBuckets && NewNumBuckets < 64u)
NewNumBuckets = ... | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %edx
xorl %ebp, %ebp
cmpl $0x2, %edx
jb 0xe87ad7
movl %edx, %eax
shrl %eax
decl %eax
je 0xe87ab9
bsrl %eax, %eax
xorl $0x1f, %eax
jmp 0xe87abe
movl $0x20, %eax
movb $0x21, %cl
subb %al, %cl
movl $0x1, %esi
shll %cl, %esi
addl $-0x1c, %eax
cmpl $0x3, %eax
mov... | /llvm/ADT/DenseMap.h |
llvm::HvxSelector::completeToPerfect(llvm::ArrayRef<unsigned int>, unsigned int) | SmallVector<uint32_t, 8>
HvxSelector::completeToPerfect(ArrayRef<uint32_t> Completions, unsigned Width) {
// Pick a completion if there are multiple possibilities. For now just
// select any valid completion.
SmallVector<uint32_t, 8> Comps(Completions);
for (unsigned I = 0; I != Width; ++I) {
uint32_t P = ... | pushq %r14
pushq %rbx
pushq %rax
movl %ecx, %ebx
movq %rdi, %r14
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, 0x8(%rdi)
leaq (%rsi,%rdx,4), %rdx
callq 0x8a3a6c
testl %ebx, %ebx
je 0xe88ef4
movq (%r14), %rax
movl %ebx, %ecx
xorl %edx, %edx
movl (%rax,%rdx,4), %es... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::HvxSelector::selectShuffle(llvm::SDNode*) | void HvxSelector::selectShuffle(SDNode *N) {
DEBUG_WITH_TYPE("isel", {
dbgs() << "Starting " << __func__ << " on node:\n";
N->dump(&DAG);
});
MVT ResTy = N->getValueType(0).getSimpleVT();
// Assume that vector shuffles operate on vectors of bytes.
assert(ResTy.isVector() && ResTy.getVectorElementType(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1068, %rsp # imm = 0x1068
movq %rsi, %r15
movq %rdi, %r14
movq 0x30(%rsi), %rax
movzbl (%rax), %ebp
movb (%rax), %cl
movq 0x8(%rax), %rax
leaq 0x840(%rsp), %r12
movb %cl, (%r12)
movq %rax, 0x8(%r12)
movq 0x58(%rsi), %r13
movq %r12, %rdi... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::HvxSelector::shuffs2((anonymous namespace)::ShuffleMask, (anonymous namespace)::OpRef, (anonymous namespace)::OpRef, (anonymous namespace)::ResultStack&) | OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
if (isUndef(SM.Mask))
return OpRef::undef(getSingleVT(MVT::i8));
OpRef C = contracting(SM, Va, Vb, Results);
if (C.isValid())
return ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x838, %rsp # imm = 0x838
movq %rsi, 0x58(%rsp)
movq %rdi, %r12
movq 0x878(%rsp), %rax
testq %rax, %rax
sete %cl
je 0xe8a741
movq 0x870(%rsp), %rdi
cmpl $-0x1, (%rdi)
jne 0xe8a741
shlq $0x2, %rax
movl $0x4, %esi
cmpq %rsi, %rax
sete %cl
... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::HvxSelector::packs((anonymous namespace)::ShuffleMask, (anonymous namespace)::OpRef, (anonymous namespace)::OpRef, (anonymous namespace)::ResultStack&, llvm::MutableArrayRef<int>, unsigned int) | OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
ResultStack &Results, MutableArrayRef<int> NewMask,
unsigned Options) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
if (!Va.isValid() || !Vb.isValid())
return OpRef::fail();
if (Vb.isUnd... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x788, %rsp # imm = 0x788
movq %rcx, %r14
movq %rsi, %r12
movq %rdi, %rbx
cmpq $0x0, 0x7d8(%rsp)
setne %cl
movl 0x7e8(%rsp), %eax
btl $0x1c, %eax
setae %sil
orb %cl, %sil
cmpb $0x1, %sil
jne 0xe8d203
leaq 0x7f0(%rsp), %r15
cmpq $0x0, (%r... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(llvm::SDValue, llvm::SelectionDAG&) const | SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDLoc dl(Op);
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
} | pushq %rbp
pushq %r14
pushq %rbx
subq $0x30, %rsp
movq %rcx, %rbx
movq %rsi, %r14
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x20(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xe98507
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%r14), %eax
leaq 0x10(%rsp), %r14... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerVASTART(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
// VASTART stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MachineFunction &MF = DAG.getMachineFunction();
HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
SDVal... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1f8, %rsp # imm = 0x1F8
movq %rcx, %rbx
movq %rsi, %r14
movq %rdi, %r13
movq 0x28(%rcx), %r12
movq 0x30(%r12), %rax
movl 0x10(%rax), %esi
movq %rcx, %rdi
movl $0x7, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq 0x1f50aba
movq %rax, %r15
m... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::extractVectorPred(llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::extractVectorPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl, MVT ValTy, MVT ResTy,
SelectionDAG &DAG) const {
// Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
// without any co... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %r9, 0x48(%rsp)
movl %r8d, %r15d
movq %rcx, %rbx
movq %rdi, 0x60(%rsp)
movzbl 0x160(%rsp), %ebp
movq %rsi, 0x30(%rsp)
movq 0x30(%rsi), %rax
movl %edx, 0x28(%rsp)
movl %edx, %ecx
shlq $0x4, %rcx
movzbl (%rax... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::insertVectorPred(llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::insertVectorPred(SDValue VecV, SDValue ValV,
SDValue IdxV, const SDLoc &dl,
MVT ValTy, SelectionDAG &DAG) const {
MVT VecTy = ty(VecV);
unsigned VecLen = VecTy.getVectorNumElements();
if (ValTy == MVT::... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %r9, %rbx
movl %r8d, 0x28(%rsp)
movq %rcx, %rbp
movl %edx, %r14d
movq %rsi, %r13
movq %rdi, %rdx
movb 0x150(%rsp), %sil
movq 0x30(%r13), %rax
movl %r14d, %ecx
shlq $0x4, %rcx
movzbl (%rax,%rcx), %r15d
leal ... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
SelectionDAG &DAG) const {
return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
ty(Op), ty(Op), DAG);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rcx, %r10
movl %edx, %r13d
movq %rsi, %r14
movq 0x28(%rsi), %rax
movq (%rax), %rdx
movl 0x8(%rax), %ebx
movq 0x28(%rax), %rbp
movl 0x30(%rax), %r12d
movq 0x48(%rsi), %rsi
movq %rsi, 0x18(%rsp)
testq %rsi, %rsi
je 0xea0da8
movq %rdi... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerINSERT_VECTOR_ELT(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {
return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
SDLoc(Op), ty(Op).getVectorElementType(), DAG);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, %r12
movq %rsi, %r14
movq 0x28(%rsi), %rax
movq (%rax), %r13
movl 0x8(%rax), %ebx
movq 0x28(%rax), %rbp
movl 0x30(%rax), %r8d
movups 0x50(%rax), %xmm0
movaps %xmm0, 0x40(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x30(%rsp)
testq ... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerLoad(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerLoad(SDValue Op, SelectionDAG &DAG) const {
MVT Ty = ty(Op);
const SDLoc &dl(Op);
LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
MVT MemTy = LN->getMemoryVT().getSimpleVT();
ISD::LoadExtType ET = LN->getExtensionType();
bool LoadPred = MemTy == MVT::v2i1 || MemTy == MV... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x148, %rsp # imm = 0x148
movq %rcx, %r14
movq %rsi, %r12
movq %rdi, 0xb8(%rsp)
movq 0x30(%rsi), %rax
movl %edx, 0x9c(%rsp)
movl %edx, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %al
movb %al, 0x87(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x88(... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(llvm::EVT, unsigned int, llvm::Align, llvm::MachineMemOperand::Flags, unsigned int*) const | bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
unsigned *Fast) const {
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
if (Fast)
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %r9d, %ebp
movl %esi, %r15d
movq %rdi, %r14
movq 0x30(%rsp), %rbx
movq 0x4e100(%rdi), %rdi
xorl %edx, %edx
movl $0x1, %ecx
callq 0xe08746
testb %al, %al
je 0xea31ce
movzbl %r15b, %esi
movzwl %bp, %edx
movq %r14, %rdi
movq %rbx, %rcx
addq $0x8, %rsp
popq %rbx
p... | /Target/Hexagon/HexagonISelLowering.cpp |
void llvm::cl::apply<llvm::cl::opt<int, false, llvm::cl::parser<int>>, char [18], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(llvm::cl::opt<int, false, llvm::cl::parser<int>>*, char const (&) [18], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x6ea2b0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x206a93a
movl (%r12), %eax
movzwl 0xa(%r14), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
llvm::HexagonTargetLowering::extractHvxSubvectorReg(llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV,
SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const {
MVT VecTy = ty(VecV);
unsigned HwLen = Subtarget.getVectorLength();
unsigned Idx = IdxV.getNode()->getAsZExtVal();
MVT ElemTy = VecTy.getVectorElementTyp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %r8d, %ebp
movq %rcx, %r12
movl %edx, 0x1c(%rsp)
movq 0x30(%rcx), %rax
movl %r8d, %ecx
shlq $0x4, %rcx
movq 0x4e100(%rdi), %rdx
movq 0x90(%rsp), %r8
movq 0x58(%r8), %r8
cmpl $0x41, 0x20(%r8)
movq %r9, 0x30(%rsp)
movq %rdi, 0x38(%rsp... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::LowerHvxExtractSubvector(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG)
const {
SDValue SrcV = Op.getOperand(0);
MVT SrcTy = ty(SrcV);
MVT DstTy = ty(Op);
SDValue IdxV = Op.getOperand(1);
unsigned Idx = IdxV.getNode()->getAsZExtVal();
assert(Idx % DstTy.getVectorNumElements() == 0);
(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movl %edx, %r15d
movq %rsi, %r13
movq 0x28(%rsi), %rax
movq 0x30(%rsi), %r9
movq (%rax), %rbp
movl 0x8(%rax), %r10d
movq 0x30(%rbp), %rdx
movq %r10, %rsi
shlq $0x4, %rsi
movzbl (%rdx,%rsi), %r12d
movl %r15d, %edx
shlq $0x4, %rdx
movb (%r... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::LowerHvxFpExtend(llvm::SDValue, llvm::SelectionDAG&) const | SDValue HexagonTargetLowering::LowerHvxFpExtend(SDValue Op,
SelectionDAG &DAG) const {
// This conversion only applies to QFloat. IEEE extension from f16 to f32
// is legal (done via a pattern).
assert(Subtarget.useHVXQFloatOps());
assert(Op->getOpcode() == ISD::... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rcx, %rbx
movq %rsi, %r15
movq 0x28(%rsi), %rax
movq 0x30(%rsi), %rcx
movl %edx, %edx
shlq $0x4, %rdx
movb (%rcx,%rdx), %bpl
movq (%rax), %rcx
movl 0x8(%rax), %eax
movq 0x30(%rcx), %rcx
shlq $0x4, %rax
movb (%rcx,%rax), %r14b
movq ... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
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