name string | code string | asm string | file string |
|---|---|---|---|
llvm::HexagonTargetLowering::LowerHvxOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const | void
HexagonTargetLowering::LowerHvxOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
unsigned Opc = N->getOpcode();
SDValue Op(N, 0);
SDValue Inp0; // Optional first argument.
if (N->getNumOperands() > 0)
Inp0 = Op.getOperand(0);
switch (Opc) {
case IS... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl 0x18(%rsi), %eax
cmpw $0x0, 0x40(%rsi)
je 0xeb3b1a
movq 0x28(%r15), %rcx
movq (%rcx), %rbp
movl 0x8(%rcx), %r13d
jmp 0xeb3b1f
xorl %ebp, %ebp
xorl %r13d, %r13d
cmpl $0x15e, %... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::combineConcatVectorsBeforeLegal(llvm::SDValue, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue
HexagonTargetLowering::combineConcatVectorsBeforeLegal(
SDValue Op, DAGCombinerInfo &DCI) const {
// Fold
// concat (shuffle x, y, m1), (shuffle x, y, m2)
// into
// shuffle (concat x, y), undef, m3
if (Op.getNumOperands() != 2)
return SDValue();
SelectionDAG &DAG = DCI.DAG;
const SDL... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x328, %rsp # imm = 0x328
cmpw $0x2, 0x40(%rsi)
jne 0xeb42d2
movq %rsi, %r14
movq 0x10(%rcx), %rbx
movq 0x48(%rsi), %rsi
movq %rsi, 0x40(%rsp)
testq %rsi, %rsi
je 0xeb4226
leaq 0x40(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
(anonymous namespace)::Simplifier::~Simplifier() | Rule(StringRef N, FuncType F) : Name(N), Fn(F) {} | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movq (%rdi), %r14
movq 0x8(%rdi), %r15
cmpq %r15, %r14
je 0xebb73c
addq $0x10, %r14
movq 0x10(%r14), %rax
testq %rax, %rax
je 0xebb72c
movq %r14, %rdi
movq %r14, %rsi
movl $0x3, %edx
callq *%rax
leaq 0x30(%r14), %rax
addq $0x20, %r14
cmpq %r15, %r14
movq %rax, %r14
jne 0... | /Target/Hexagon/HexagonLoopIdiomRecognition.cpp |
(anonymous namespace)::Simplifier::addRule(llvm::StringRef, std::function<llvm::Value* (llvm::Instruction*, llvm::LLVMContext&)> const&) | void addRule(StringRef N, const Rule::FuncType &F) {
Rules.push_back(Rule(N, F));
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorps %xmm0, %xmm0
movaps %xmm0, 0x40(%rsp)
movaps %xmm0, 0x50(%rsp)
movq 0x10(%rcx), %rax
testq %rax, %rax
je 0xebb7eb
movq %rcx, %r14
leaq 0x40(%rsp), %r13
movq %r13, %rdi
movq %rcx, %rsi... | /Target/Hexagon/HexagonLoopIdiomRecognition.cpp |
llvm::DenseMap<llvm::AssertingVH<llvm::Value>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::AssertingVH<llvm::Value>, void>, llvm::detail::DenseSetPair<llvm::AssertingVH<llvm::Value>>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xebe9dc
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
llvm::HexagonVLIWResourceModel::hasDependence(llvm::SUnit const*, llvm::SUnit const*) | bool HexagonVLIWResourceModel::hasDependence(const SUnit *SUd,
const SUnit *SUu) {
const auto *QII = static_cast<const HexagonInstrInfo *>(TII);
// Enable .cur formation.
if (QII->mayBeCurLoad(*SUd->getInstr()))
return false;
if (QII->canExecuteInBundle(*SUd->g... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq 0x8(%rdi), %r12
movq (%rsi), %rsi
movq %r12, %rdi
callq 0xe03808
testb %al, %al
jne 0xebf8f2
movq (%r14), %rsi
movq (%rbx), %rdx
movq %r12, %rdi
callq 0xe04010
testb %al, %al
je 0xebf900
xorl %eax, %eax
addq $0x8... | /Target/Hexagon/HexagonMachineScheduler.cpp |
(anonymous namespace)::HexagonNewValueJump::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
<< "********** Function: " << MF.getName() << "\n");
if (skipFunction(MF.getFunction()))
return false;
// If we move NewValueJump before register al... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %rbx
movq %rdi, %r14
movq (%rsi), %rsi
callq 0x1ba4a72
testb %al, %al
jne 0xec0bf5
movq 0x10(%rbx), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x38(%r14)
movq 0x10(%rbx), %rdi
movq (%rdi), %r... | /Target/Hexagon/HexagonNewValueJump.cpp |
llvm::rdf::RegisterAggrMap<llvm::MachineBasicBlock*>::RegisterAggrMap(llvm::rdf::PhysicalRegisterInfo const&) | RegisterAggrMap(const PhysicalRegisterInfo &pri) : Empty(pri) {} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq (%rsi), %rax
movl 0x2c(%rax), %r15d
leal 0x3f(%r15), %esi
shrl $0x6, %esi
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, 0x8(%rdi)
xorl %r12d, %r12d
xorl %edx, %edx
callq 0... | /llvm/CodeGen/RDFRegisters.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>>, unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::Dens... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0xec5bde
movl 0x10(%rbx), %ecx
leaq (%rcx,%rcx,2), %rdx
shlq $0x2, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::DenseMap<unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xec589c
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>* llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, unsigned int>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, unsigned int>>>, unsigned int, std::pair<unsign... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xec5cad
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [30], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [30], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x6ea2b0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x206a93a
movl (%r12), %eax
movzwl 0xa(%r14), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonCP::interpretAsCopy(llvm::MachineInstr const*, std::map<llvm::rdf::RegisterRef, llvm::rdf::RegisterRef, std::less<llvm::rdf::RegisterRef>, std::allocator<std::pair<llvm::rdf::RegisterRef const, llvm::rdf::RegisterRef>>>&) | bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
EM.insert(std::make_pair(DstR, SrcR));
};
DataFlowGraph &DFG = getDFG();
unsigned Opc = MI->getOpcode();
switch (Opc) {
case Hexagon::A2_combinew: {
con... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %rbx
movq 0x10(%rdi), %r14
movzwl 0x44(%rsi), %eax
cmpl $0x396, %eax # imm = 0x396
je 0xec7953
cmpl $0x3f1, %eax # imm = 0x3F1
je 0xec7968
cmpl $0x3a6, %eax # imm = 0x3A6
jne 0xec79d1
movq 0x20... | /Target/Hexagon/HexagonRDFOpt.cpp |
initializeHexagonSplitConst32AndConst64PassOnce(llvm::PassRegistry&) | bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
auto &HST = Fn.getSubtarget<HexagonSubtarget>();
auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
auto &TLOF = *HTM.getObjFileLowering();
if (HST.useSmallData() && TLOF.isSmallDataEnabled(HTM))
return false;... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl $0x50, %edi
callq 0x6ea880
movq %rax, %r14
leaq 0x29a5bc1(%rip), %rax # 0x386de98
movq %rax, (%r14)
movq $0x23, 0x8(%r14)
leaq 0x29a5bd3(%rip), %rax # 0x386debc
movq %rax, 0x10(%r14)
movq $0x15, 0x18(%r14)
leaq 0x475df44(%rip), %rax # 0x5626240
movq %rax, 0x20... | /Target/Hexagon/HexagonSplitConst32AndConst64.cpp |
(anonymous namespace)::HexagonSplitDoubleRegs::isFixedInstr(llvm::MachineInstr const*) const | bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
if (MI->mayLoadOrStore())
if (MemRefsFixed || isVolatileInstr(MI))
return true;
if (MI->isDebugInstr())
return false;
unsigned Opc = MI->getOpcode();
switch (Opc) {
default:
return true;
case TargetOpcode::PH... | pushq %rbx
movq %rdi, %rbx
movl $0x1, %esi
callq 0x87b3a6
testb %al, %al
jne 0xeca96d
movq %rbx, %rdi
movl $0x1, %esi
callq 0x87b3ca
testb %al, %al
je 0xeca9ed
movb $0x1, %al
cmpb $0x0, 0x475ba12(%rip) # 0x5626388
jne 0xecab68
movq 0x30(%rbx), %rsi
xorl %ecx, %ecx
movl $0x0, %edx
cmpq $0x8, %rsi
jb 0xeca9c8
movq %rsi... | /Target/Hexagon/HexagonSplitDouble.cpp |
llvm::BitTracker::RegisterCell::cat(llvm::BitTracker::RegisterCell const&) | BT::RegisterCell &BT::RegisterCell::cat(const RegisterCell &RC) {
// Append the cell given as the argument to the "this" cell.
// Bit 0 of RC becomes bit W of the result, where W is this->width().
uint16_t W = width(), WRC = RC.width();
Bits.resize(W+WRC);
for (uint16_t i = 0; i < WRC; ++i)
Bits[i+W] = RC... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movzwl 0x8(%rdi), %r12d
movzwl 0x8(%rsi), %r15d
leal (%r15,%r12), %esi
callq 0xe3823a
testq %r15, %r15
je 0xed50d4
shll $0x2, %r12d
leaq (%r12,%r12,2), %rax
shll $0x2, %r15d
leaq (%r15,%r15,2), %rcx
xorl %edx, %edx
movq (%r14), %rsi
... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eADD(llvm::BitTracker::RegisterCell const&, llvm::BitTracker::RegisterCell const&) const | BT::RegisterCell BT::MachineEvaluator::eADD(const RegisterCell &A1,
const RegisterCell &A2) const {
uint16_t W = A1.width();
assert(W == A2.width());
RegisterCell Res(W);
bool Carry = false;
uint16_t I;
for (I = 0; I < W; ++I) {
const BitValue &V1 = A1[I];
const BitValue &V2 = A2[I];
if (!... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rdx, %r15
movq %rdi, %rbx
movl 0x8(%rdx), %r13d
movzwl %r13w, %r12d
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x2000000000, %rax # imm = 0x2000000000
movq %rax, 0x8(%rdi)
movq %r12, %rsi
callq 0xe3823a
testw %r... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eXOR(llvm::BitTracker::RegisterCell const&, llvm::BitTracker::RegisterCell const&) const | BT::RegisterCell BT::MachineEvaluator::eXOR(const RegisterCell &A1,
const RegisterCell &A2) const {
uint16_t W = A1.width();
assert(W == A2.width());
RegisterCell Res(W);
for (uint16_t i = 0; i < W; ++i) {
const BitValue &V1 = A1[i];
const BitValue &V2 = A2[i];
if (V1.is(0))
Res[i] = Bit... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, %r14
movzwl 0x8(%rdx), %r12d
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x2000000000, %rax # imm = 0x2000000000
movq %rax, 0x8(%rdi)
movq %r12, %rsi
callq 0xe3823a
testq %r12, %r12
je 0xed6321
shll $0x2, %r12d
le... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::visit(llvm::MachineInstr const&) | void BT::visit(const MachineInstr &MI) {
assert(!MI.isBranch() && "Only non-branches are allowed");
InstrExec.insert(&MI);
visitNonBranch(MI);
// Make sure to flush all the pending use updates.
runUseQueue();
// The call to visitNonBranch could propagate the changes until a branch
// is actually visited. ... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
addq $0x50, %rdi
movq %rsp, %rsi
movq %r14, (%rsi)
callq 0xe533c6
movq %rbx, %rdi
movq %r14, %rsi
callq 0xed77a2
movq %rbx, %rdi
callq 0xed857c
movq 0x100(%rbx), %rax
cmpq 0xe0(%rbx), %rax
je 0xed8573
leaq 0xd0(%rbx), %r14
movq %r14, %rdi
callq 0xed9a8e
m... | /Target/Hexagon/BitTracker.cpp |
llvm::HexagonBlockRanges::RangeList::subtract(llvm::HexagonBlockRanges::IndexRange const&) | void HexagonBlockRanges::RangeList::subtract(const IndexRange &Range) {
// Cannot assume that the list is unionized (i.e. contains only non-
// overlapping ranges.
RangeList T;
for (iterator Next, I = begin(); I != end(); I = Next) {
IndexRange &Rg = *I;
if (Rg.overlaps(Range)) {
T.addsub(Rg, Rang... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0x0, 0x10(%rsp)
movq (%rdi), %r15
cmpq 0x8(%rdi), %r15
je 0xeda194
movq %rsi, %r14
movq %rsp, %r12
movq %r15, %rdi
movq %r14, %rsi
callq 0xed9c78
testb %al, %al
je 0xeda18a
movq %r12, %rdi
movq %r1... | /Target/Hexagon/HexagonBlockRanges.cpp |
llvm::HexagonBlockRanges::InstrIndexMap::getInstr(llvm::HexagonBlockRanges::IndexType) const | MachineInstr *HexagonBlockRanges::InstrIndexMap::getInstr(IndexType Idx) const {
auto F = Map.find(Idx);
return (F != Map.end()) ? F->second : nullptr;
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0xc(%rsp), %rax
movl %esi, (%rax)
addq $0x10, %rdi
movq %rax, %rsi
callq 0xedc7ca
addq $0x18, %rbx
cmpq %rbx, %rax
je 0xeda2c2
movq 0x28(%rax), %rax
jmp 0xeda2c4
xorl %eax, %eax
addq $0x10, %rsp
popq %rbx
retq
| /Target/Hexagon/HexagonBlockRanges.cpp |
llvm::TargetTransformInfo::Model<llvm::LanaiTTIImpl>::getScalingFactorCost(llvm::Type*, llvm::GlobalValue*, llvm::StackOffset, bool, long, unsigned int) | InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
StackOffset BaseOffset, bool HasBaseReg,
int64_t Scale,
unsigned AddrSpace) override {
return Impl.getScalingFactorCost(Ty, BaseGV,... | pushq %rbx
subq $0x30, %rsp
movq %rsi, %rax
movl 0x48(%rsp), %r10d
movq 0x40(%rsp), %rsi
xorps %xmm0, %xmm0
movq %rsp, %r11
movaps %xmm0, (%r11)
movups %xmm0, 0x18(%r11)
movq %rdx, (%r11)
movq %rcx, 0x8(%r11)
movb %r9b, 0x10(%r11)
movq %rsi, 0x18(%r11)
movq %r8, 0x20(%r11)
movq 0x10(%rdi), %rsi
movq 0x20(%rdi), %rdi
mo... | /llvm/Analysis/TargetTransformInfo.h |
llvm::TargetTransformInfo::Model<llvm::LoongArchTTIImpl>::getVectorInstrCost(llvm::Instruction const&, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind, unsigned int) | InstructionCost getVectorInstrCost(const Instruction &I, Type *Val,
TTI::TargetCostKind CostKind,
unsigned Index) override {
return Impl.getVectorInstrCost(I, Val, CostKind, Index);
} | movq %rsi, %rax
movzbl (%rsi), %esi
cmpl $0x5b, %esi
jne 0xef501d
movq -0x60(%rax), %r9
movq -0x40(%rax), %rax
jmp 0xef5022
xorl %eax, %eax
xorl %r9d, %r9d
pushq %rax
addq $0x8, %rdi
addl $-0x1d, %esi
movq %rax, (%rsp)
callq 0xef606e
popq %rcx
retq
nop
| /llvm/Analysis/TargetTransformInfo.h |
llvm::TargetTransformInfoImplCRTPBase<llvm::LoongArchTTIImpl>::getInstructionCost(llvm::User const*, llvm::ArrayRef<llvm::Value const*>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getInstructionCost(const User *U,
ArrayRef<const Value *> Operands,
TTI::TargetCostKind CostKind) {
using namespace llvm::PatternMatch;
auto *TargetTTI = static_cast<T *>(this);
// Handle non-intrinsic calls, invokes,... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movl %r8d, %ebp
movq %rcx, %r13
movq %rsi, %r14
movq %rdi, %rbx
movzbl (%rsi), %eax
cmpl $0x1d, %eax
jb 0xef6490
leal -0x22(%rax), %ecx
cmpl $0x33, %ecx
ja 0xef6490
movabsq $0x8000000000041, %rsi # imm = 0x8000... | /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::BasicTTIImplBase<llvm::LoongArchTTIImpl>::getCastInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::TargetTransformInfo::CastContextHint, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) {
if (BaseT::getCastInstrCost(Opcode, Dst, Src, CCH... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movl %r9d, %ebx
movl %r8d, %r15d
movq %rcx, %r13
movq %rdx, %r12
movl %esi, %ebp
movq %rdi, %r14
movq 0xe0(%rsp), %rax
addq $0x8, %rdi
movq %rax, (%rsp)
movq %rdi, 0x88(%rsp)
callq 0x8a2fcc
xorl %ecx, %ecx
xorl %esi, %esi
testq %rax, %ra... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::LoongArchTTIImpl>::getMemoryOpCost(unsigned int, llvm::Type*, llvm::MaybeAlign, unsigned int, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::Instruction const*) | InstructionCost
getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
unsigned AddressSpace, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
const Instruction *I = nullptr) {
assert(!Src->isVoidTy() &&... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %r9d, %r13d
movq %rdx, %r15
movl %esi, %ebp
movq %rdi, %r12
movq 0x8(%rdi), %rsi
movq 0x18(%rdi), %rdi
movl $0x1, %ecx
callq 0x88c7e0
cmpb $0x1, %al
jne 0xef92c4
xorl %ebx, %ebx
movl $0x4, %r14d
jmp 0xef93ef
movq %rsp, %rbx
movq %rb... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::LoongArchTTIImpl>::getMinMaxReductionCost(unsigned int, llvm::VectorType*, llvm::FastMathFlags, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
FastMathFlags FMF,
TTI::TargetCostKind CostKind) {
// Targets must implement a default value for the scalable case, since
// we don't know how many lanes th... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movl %r8d, 0x44(%rsp)
movl %ecx, 0x40(%rsp)
movl %esi, 0x3c(%rsp)
movq %rdi, 0x30(%rsp)
cmpb $0x13, 0x8(%rdx)
jne 0xefb467
movl $0x1, %r12d
xorl %r14d, %r14d
jmp 0xefb89f
movq %rdx, %rbp
movl 0x20(%rdx), %eax
te... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::LoongArchTTIImpl::getRegisterBitWidth(llvm::TargetTransformInfo::RegisterKind) const | TypeSize LoongArchTTIImpl::getRegisterBitWidth(
TargetTransformInfo::RegisterKind K) const {
TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K);
switch (K) {
case TargetTransformInfo::RGK_Scalar:
return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
case TargetTransformInfo::RGK_FixedW... | cmpl $0x2, %esi
je 0xefd6ee
cmpl $0x1, %esi
jne 0xefd6f5
movq 0x10(%rdi), %rax
cmpb $0x0, 0x122(%rax)
je 0xefd709
movl $0x100, %eax # imm = 0x100
jmp 0xefd71e
movl $0x20, %eax
jmp 0xefd71e
movq 0x10(%rdi), %rax
movzbl 0x128(%rax), %eax
shll $0x5, %eax
addq $0x20, %rax
jmp 0xefd71e
cmpb $0x0, 0x124(%rax)
movl... | /Target/LoongArch/LoongArchTargetTransformInfo.cpp |
llvm::MipsAsmPrinter::emitFrameDirective() | void MipsAsmPrinter::emitFrameDirective() {
const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
Register stackReg = RI.getFrameRegister(*MF);
unsigned returnReg = RI.getRARegister();
unsigned stackSize = MF->getFrameInfo().getStackSize();
getTargetStreamer().emitFrame(stackReg, stackSize, ... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x58(%rdi), %rax
movq 0x10(%rax), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r14
movq 0x58(%rbx), %rsi
movq (%rax), %rax
movq %r14, %rdi
callq *0x258(%rax)
movl 0x14(%r14), %ecx
movq 0x50(%rbx), %rsi
movq 0x58(%rbx), %rdx
movq 0x38(%rdx), %rdx
movl 0x30(%r... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::TargetTransformInfo::Model<llvm::MipsTTIImpl>::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) | std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) override {
return Impl.simplifyDeman... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r9, %rbx
movq %r8, 0x18(%rsp)
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq 0x88(%rsp), %rbp
movl 0x8(%rcx), %eax
movl %eax, 0x10(%rsp)
cmpl $0x40, %eax
ja 0xf314d3
movq (%rcx), %rax
movq %rax, 0x8(%rsp)
jmp 0xf314e0
leaq 0x... | /llvm/Analysis/TargetTransformInfo.h |
llvm::TargetTransformInfo::Model<llvm::MipsTTIImpl>::getRegisterClassName(unsigned int) const | const char *getRegisterClassName(unsigned ClassID) const {
switch (ClassID) {
default:
return "Generic::Unknown Register Class";
case 0:
return "Generic::ScalarRC";
case 1:
return "Generic::VectorRC";
}
} | cmpl $0x1, %esi
leaq 0x2239cff(%rip), %rax # 0x316b5f7
leaq 0x2239cc6(%rip), %rcx # 0x316b5c5
cmoveq %rax, %rcx
testl %esi, %esi
leaq 0x2239cd9(%rip), %rax # 0x316b5e5
cmovneq %rcx, %rax
retq
nop
| /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::MipsTargetObjectFile::IsConstantInSmallSection(llvm::DataLayout const&, llvm::Constant const*, llvm::TargetMachine const&) const | const MipsSubtarget *getSubtargetImpl() const {
if (Subtarget)
return Subtarget;
return &DefaultSubtarget;
} | movq 0x4a8(%rcx), %rax
addq $0x4b0, %rcx # imm = 0x4B0
testq %rax, %rax
cmovneq %rax, %rcx
cmpb $0x1, 0x137(%rcx)
jne 0xf3a68e
cmpb $0x1, 0x46ecb1b(%rip) # 0x5627170
jne 0xf3a68e
subq $0x18, %rsp
movq 0x8(%rdx), %rax
movq %rsi, %rdi
movq %rax, %rsi
callq 0x889a8a
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
movb... | /Target/Mips/MipsTargetMachine.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [13], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::initializer<bool>>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [13], llvm::cl::OptionHidden const&, llvm::cl::desc const&, llvm::cl::initializer<bool> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x6ea2b0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x206a93a
movl (%r12), %eax
movzwl 0xa(%rbx), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
whichFPParamVariantNeeded(llvm::Function&) | size_t arg_size() const { return NumArgs; } | movq 0x60(%rdi), %rcx
movl $0x6, %eax
testq %rcx, %rcx
je 0xf3cbd5
cmpq $0x1, %rcx
jne 0xf3cb89
movq 0x18(%rdi), %rax
movq 0x10(%rax), %rax
movq 0x8(%rax), %rax
movzbl 0x8(%rax), %ecx
xorl %eax, %eax
cmpl $0x3, %ecx
setne %al
leal (%rax,%rax,2), %edx
addl $0x3, %edx
xorl %eax, %eax
cmpl $0x2, %ecx
jmp 0xf3cbd2
movq 0x1... | /llvm/IR/Function.h |
llvm::Mips16DAGToDAGISel::selectMULT(llvm::SDNode*, unsigned int, llvm::SDLoc const&, llvm::EVT, bool, bool) | std::pair<SDNode *, SDNode *>
Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, const SDLoc &DL, EVT Ty,
bool HasLo, bool HasHi) {
SDNode *Lo = nullptr, *Hi = nullptr;
SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %r9, %rbx
movl %r8d, %ebp
movq %rcx, %r14
movq %rdi, %r15
movb 0x90(%rsp), %r13b
movq 0x38(%rdi), %rdi
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movups 0x28(%rax), %xmm1
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
xorl %r12d, %r1... | /Target/Mips/Mips16ISelDAGToDAG.cpp |
(anonymous namespace)::MipsIncomingValueAssigner::assignArg(unsigned int, llvm::EVT, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::CallLowering::ArgInfo const&, llvm::ISD::ArgFlagsTy, llvm::CCState&) | bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State_) override {
MipsCCState &State = static_cast<MipsCCState &>(State_);
if (IsReturn)
St... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %r9d, %ebp
movl %r8d, %r12d
movl %esi, %r15d
movq %rdi, %rbx
movq 0x60(%rsp), %r14
leaq 0x50(%rsp), %r13
movq 0x48(%rsp), %rax
movq (%rax), %rsi
cmpb $0x1, 0x30(%rdi)
jne 0xf42fb5
movq 0x28(%rbx), %rdx
movq %r14, %rdi
callq 0xf43004
jmp 0... | /Target/Mips/MipsCallLowering.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [41], llvm::cl::initializer<bool>, llvm::cl::desc, llvm::cl::OptionHidden>(char const (&) [41], llvm::cl::initializer<bool> const&, llvm::cl::desc const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x450e18... | /llvm/Support/CommandLine.h |
llvm::cl::opt<CompactBranchPolicy, false, llvm::cl::parser<CompactBranchPolicy>>::printOptionValue(unsigned long, bool) const | void printOptionValue(size_t GlobalWidth, bool Force) const override {
if (Force || !this->getDefault().compare(this->getValue())) {
cl::printOptionDiff<ParserClass>(*this, Parser, this->getValue(),
this->getDefault(), GlobalWidth);
}
} | movq %rsi, %r8
movq %rdi, %rsi
testl %edx, %edx
je 0xf471f8
subq $0x18, %rsp
leaq 0x98(%rsi), %rdi
movl 0x80(%rsi), %eax
leaq 0x88(%rsi), %rcx
leaq 0x4569be1(%rip), %r9 # 0x54b0dc0
leaq 0x8(%rsp), %rdx
movq %r9, (%rdx)
movb $0x1, 0xc(%rdx)
movl %eax, 0x8(%rdx)
callq 0x2070330
addq $0x18, %rsp
retq
cmpb $0x1, 0x94(%r... | /llvm/Support/CommandLine.h |
(anonymous namespace)::MipsDelaySlotFiller::terminateSearch(llvm::MachineInstr const&) const | bool MipsDelaySlotFiller::terminateSearch(const MachineInstr &Candidate) const {
return (Candidate.isTerminator() || Candidate.isCall() ||
Candidate.isPosition() || Candidate.isInlineAsm() ||
Candidate.hasUnmodeledSideEffects());
} | pushq %rbx
movq %rdi, %rbx
movl $0x9, %esi
movl $0x1, %edx
callq 0x877c7c
testb %al, %al
jne 0xf48f7a
movq %rbx, %rdi
movl $0x7, %esi
movl $0x1, %edx
callq 0x877c7c
testb %al, %al
jne 0xf48f7a
movl 0x44(%rbx), %eax
decl %eax
cmpw $0x6, %ax
jae 0xf48f7e
movb $0x1, %al
popq %rbx
retq
movq %rbx, %rdi
popq %rbx
jmp 0x18e52... | /Target/Mips/MipsDelaySlotFiller.cpp |
bool (anonymous namespace)::MipsDelaySlotFiller::searchRange<llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>>(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, (anonymous namespace)::RegDefsUses&, (anonymous na... | bool MipsDelaySlotFiller::searchRange(MachineBasicBlock &MBB, IterTy Begin,
IterTy End, RegDefsUses &RegDU,
InspectMemInstr &IM, Iter Slot,
IterTy &Filler) const {
for (IterTy I = Begin; I != End;) {
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r9, %r14
movq %r8, %r15
movq %rcx, 0x10(%rsp)
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, 0x20(%rsp)
cmpq %r12, %rbx
je 0xf492ae
movq %rbx, %rbp
testq %rbx, %rbx
je 0xf49096
testb $0x4, (%rbp)
movq %rbp, %rax
jne 0xf490ac
testb $0x8... | /Target/Mips/MipsDelaySlotFiller.cpp |
(anonymous namespace)::MipsInstructionSelector::select(llvm::MachineInstr&)::Instr& llvm::SmallVectorTemplateBase<(anonymous namespace)::MipsInstructionSelector::select(llvm::MachineInstr&)::Instr, true>::growAndEmplaceBack<llvm::Mips::$_0, llvm::Register&, llvm::Register&, int>(llvm::Mips::$_0&&, llvm::Register&, llvm... | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
} | pushq %rbx
movq %rdi, %rbx
movl (%rsi), %eax
movl (%rcx), %ecx
movl (%rdx), %esi
shlq $0x20, %rsi
orq %rax, %rsi
movl (%r8), %edx
shlq $0x20, %rdx
orq %rcx, %rdx
callq 0xf5ae1c
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
shlq $0x4, %rcx
addq %rcx, %rax
addq $-0x10, %rax
popq %rbx
retq
nop
| /llvm/ADT/SmallVector.h |
llvm::MipsTargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
const {
SelectionDAG &DAG = DCI.DAG;
unsigned Opc = N->getOpcode();
switch (Opc) {
default: break;
case ISD::SDIVREM:
case ISD::UDIVREM:
return performDivRemCombine(N, DAG, DCI, Subtarget);
case ISD::SELECT:
return ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %r14
movq 0x10(%rdx), %r13
movl 0x18(%rsi), %eax
xorl %r15d, %r15d
xorl %ebp, %ebp
cmpl $0xb9, %eax
jg 0xf5c6ab
cmpl $0x40, %eax
jle 0xf5c794
leal -0x41(%rax), %ecx
cmpl $0x2, %ecx
jae 0xf5c7fa
cmpl $... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::lowerVASTART(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
SDLoc DL(Op);
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
getPointer... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rcx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movq 0x28(%rcx), %r12
movq 0x30(%r12), %r13
movq 0x48(%rsi), %rsi
movq %rsi, 0x40(%rsp)
testq %rsi, %rsi
je 0xf5f54a
leaq 0x40(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%r15), %... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::lowerRETURNADDR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
if (verifyReturnAddressArgumentIsConstant(Op, DAG))
return SDValue();
// check the depth
if (Op.getConstantOperandVal(0) != 0) {
DAG.getContext()->emitError(
"return addr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
callq 0x1fbe702
testb %al, %al
jne 0xf60be1
movq 0x28(%r14), %rax
movq (%rax), %rax
movq 0x58(%rax), %rax
cmpl $0x41, 0x20(%rax)
jb 0xf60bb9
movq 0x18(%rax), %rax
jmp 0xf60b... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::lowerShiftLeftParts(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
SDValue Shamt = Op.getOperand(2);
// if shamt < (VT.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp # imm = 0x1D8
movq %rcx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x70(%rsp)
testq %rsi, %rsi
je 0xf60fcd
leaq 0x70(%rsp), %rdi
movl $0x1, %edx
callq 0x1b8dbe0
movl 0x44(%r14), %eax
leaq 0x70(%rsp... | /Target/Mips/MipsISelLowering.cpp |
llvm::SDValue llvm::MipsTargetLowering::getAddrLocal<llvm::GlobalAddressSDNode>(llvm::GlobalAddressSDNode*, llvm::SDLoc const&, llvm::EVT, llvm::SelectionDAG&, bool) const | SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
bool IsN32OrN64) const {
unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
getTa... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %r9, %r14
movq %r8, %rbx
movl %ecx, %ebp
movq %rdx, %r12
movq %rdx, 0x58(%rsp)
movq %rsi, %r15
movq %rsi, 0x60(%rsp)
movb 0x140(%rsp), %r13b
movq 0x28(%r9), %rsi
movq 0x30(%rsi), %rdi
callq 0xf7b322
movq %r... | /Target/Mips/MipsISelLowering.h |
llvm::MipsTargetLowering::LowerFormalArguments(llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&) const | SDValue MipsTargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.ge... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x558, %rsp # imm = 0x558
movq %r9, 0x78(%rsp)
movl %r8d, %r10d
movl %ecx, %ebx
movq %rdi, %r12
movq 0x598(%rsp), %r14
movq %rsi, 0x48(%rsp)
movl %edx, 0x50(%rsp)
movq 0x28(%r14), %rcx
movq 0x30(%rcx), %r13
movq 0x38(%rcx), %rax
movq %ra... | /Target/Mips/MipsISelLowering.cpp |
UnpackFromArgumentSlot(llvm::SDValue, llvm::CCValAssign const&, llvm::EVT, llvm::SDLoc const&, llvm::SelectionDAG&) | static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
EVT ArgVT, const SDLoc &DL,
SelectionDAG &DAG) {
MVT LocVT = VA.getLocVT();
EVT ValVT = VA.getValVT();
// Shift into the upper bits if necessary.
switch (VA.getL... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %r9, %rbx
movq %rdx, %r12
movl %esi, %ebp
movq %rdi, %r15
movb %cl, 0xd8(%rsp)
movq %r8, 0xe0(%rsp)
movb 0x16(%rdx), %r13b
movb 0x15(%rdx), %dl
movl 0x14(%r12), %eax
shrl %eax
andl $0x3f, %eax
addl $-0x4, %eax
cmpl $0x2, %eax
ja 0xf... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsFrameLowering::estimateStackSize(llvm::MachineFunction const&) const | uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
int64_t Size = 0;
// Iterate over fixed sized objects which are incoming arguments.
for (int I = MFI.getObjectIndexBegin()... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rsi, %rbx
movq 0x38(%rsi), %r14
movq 0x18(%rdi), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r15
movl 0x20(%r14), %eax
testl %eax, %eax
je 0xf74c83
negl %eax
movq 0x8(%r14), %rcx
addq $0x8, %rcx
incq %rax
xorl %r12d, %r12d
cmpq $0x0, -0x8(%rcx)
jle 0... | /Target/Mips/MipsFrameLowering.cpp |
llvm::MipsFrameLowering::eliminateCallFramePseudoInstr(llvm::MachineFunction&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | MachineBasicBlock::iterator MipsFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
if (!hasReservedCallFrame(MF)) {
int64_t Amount = I->getOp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r15
movq 0x18(%rdi), %rdi
callq 0xf2fcfe
movl (%rax), %ebp
movq (%r15), %rax
movq %r15, %rdi
movq %r12, %rsi
callq *0xd0(%rax)
testb %al, %al
jne 0xf74da9
cmpl $0x3, %ebp
movl $0x14e, %eax # imm... | /Target/Mips/MipsFrameLowering.cpp |
llvm::MipsFunctionInfo::createEhDataRegsFI(llvm::MachineFunction&) | void MipsFunctionInfo::createEhDataRegsFI(MachineFunction &MF) {
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
for (int &I : EhDataRegFI) {
const TargetRegisterClass &RC =
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
? Mips::GPR64RegClass
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x10(%rsi), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r15
xorl %r12d, %r12d
leaq 0x45316e3(%rip), %r13 # 0x54ad570
leaq 0x45321dc(%rip), %rbp # 0x54ae070
movq 0x8(%rbx), %rax
cmpl $0x3, 0x4a0... | /Target/Mips/MipsMachineFunction.cpp |
llvm::MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(llvm::MachineInstr const*, llvm::MachineInstr const*, unsigned int) | void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
const MachineInstr *MI, const MachineInstr *CopyInst, unsigned Op) {
assert((CopyInst->getOperand(Op).getReg().isPhysical()) &&
"Copies of non physical registers should not be considered here.\n");
const MachineFunction &MF... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq %rdx, %rdi
callq 0x18e4030
movq 0x10(%rax), %rdi
movq 0x28(%rax), %r12
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r13
movq %r15, %rdi
callq 0x18e4030
movq 0x10(%rax), %r... | /Target/Mips/MipsRegisterBankInfo.cpp |
llvm::SystemZInstrInfo::convertToThreeAddress(llvm::MachineInstr&, llvm::LiveVariables*, llvm::LiveIntervals*) const | MachineInstr *
SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
LiveIntervals *LIS) const {
MachineBasicBlock *MBB = MI.getParent();
// Try to convert an AND into an RISBG-type instruction.
// TODO: It might be beneficial to select RISBG and sho... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rcx, %rbp
movq %rdx, 0x20(%rsp)
movq %rsi, %rbx
movq %rdi, %r12
movzwl 0x44(%rsi), %ecx
xorl %edi, %edi
addl $0xfffffe50, %ecx # imm = 0xFFFFFE50
cmpl $0x8, %ecx
ja 0x11c6feb
movl $0xf, %eax
movl $0x20, %edx
leaq 0x2a0e904(%r... | /Target/SystemZ/SystemZInstrInfo.cpp |
llvm::SystemZInstrInfo::prepareCompareSwapOperands(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
int &DestFrameIndex,
int &SrcFrameIndex) const {
// Check for MVC 0(Length,FI1),0(FI2)
const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
if (MI.getO... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq 0x18(%rsi), %rbx
leaq 0x18(%rsp), %r15
movq %r15, -0x10(%r15)
movabsq $0x400000000, %rax # imm = 0x400000000
movq %rax, -0x8(%r15)
testq %rsi, %rsi
je 0x11c8dbe
testb $0x4, (%rsi)
je 0x11c8dbe
jmp 0x11c8dc4
movq 0x8(%rsi), %rsi... | /Target/SystemZ/SystemZInstrInfo.cpp |
llvm::GR128BitGetRawAllocationOrder(llvm::MachineFunction const&) | iterator begin() const { return RegsBegin; } | leaq 0x4384385(%rip), %rax # 0x554ec70
movq 0x280(%rax), %rcx
movzwl 0x294(%rax), %eax
movq %rcx, -0x28(%rsp)
movq %rax, -0x20(%rsp)
leaq 0x2a0be36(%rip), %rax # 0x3bd6740
movq %rax, -0x18(%rsp)
movq $0x8, -0x10(%rsp)
movq 0x10(%rdi), %rax
movl 0x17c(%rax), %ecx
movl 0x184(%rax), %eax
xorl $0x4, %eax
xorl $0xf, %ec... | /llvm/MC/MCRegisterInfo.h |
llvm::createWebAssemblyRegNumbering() | FunctionPass *llvm::createWebAssemblyRegNumbering() {
return new WebAssemblyRegNumbering();
} | pushq %rax
movl $0x38, %edi
callq 0x6ea880
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x43c08e2(%rip), %rdx # 0x5630aac
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x426d6e9(%rip), %rcx # 0x54dd8d0
movq %rcx, (%rax)
popq %rcx
retq
| /Target/WebAssembly/WebAssemblyRegNumbering.cpp |
llvm::X86TargetLowering::LowerWin64_FP_TO_INT128(llvm::SDValue, llvm::SelectionDAG&, llvm::SDValue&) const | SDValue X86TargetLowering::LowerWin64_FP_TO_INT128(SDValue Op,
SelectionDAG &DAG,
SDValue &Chain) const {
assert(Subtarget.isTargetWin64() && "Unexpected target");
EVT VT = Op.getValueType();
bool IsStrict = Op->... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %r8, %r14
movq %rcx, %rbx
movq %rsi, %r13
movq %rdi, 0x70(%rsp)
movq 0x30(%rsi), %rax
movl %edx, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %bpl
movq 0x8(%rax,%rcx), %r12
movq %rsi, %rdi
callq 0x95d174
movl %eax, %r15d
movq 0x28(%r13), ... | /Target/X86/X86ISelLowering.cpp |
bool llvm::any_of<llvm::SmallVector<llvm::SDValue, 16u>&, combineX86ShufflesRecursively(llvm::ArrayRef<llvm::SDValue>, int, llvm::SDValue, llvm::ArrayRef<int>, llvm::ArrayRef<llvm::SDNode const*>, unsigned int, unsigned int, bool, bool, bool, llvm::SelectionDAG&, llvm::X86Subtarget const&)::$_4>(llvm::SmallVector<llvm:... | Callable() = default; | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq (%rdi), %rbx
movl 0x8(%rdi), %r13d
movq %r13, %r12
shlq $0x4, %r12
addq %rbx, %r12
movl %esi, 0xc(%rsp)
cmpq $0x4, %r13
jae 0x13eccc9
movq %r12, %rax
subq %rbx, %rax
sarq $0x4, %rax
cmpq $0x1, %rax
je 0x13ecd33
cmpq $0x2, %rax
je 0x13eccb0
mov... | /llvm/ADT/STLExtras.h |
std::pair<llvm::DenseMapIterator<llvm::CodeViewDebug::LocalVarDef, unsigned int, llvm::DenseMapInfo<llvm::CodeViewDebug::LocalVarDef, void>, llvm::detail::DenseMapPair<llvm::CodeViewDebug::LocalVarDef, unsigned int>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::CodeViewDebug::LocalVarDef, unsigned int, llvm::D... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r13
movq %rsi, %rdi
movq %rdx, %rsi
movq %r13, %rdx
callq 0x17e6f5c
movl %eax, %ecx
movq (%r13), %rax
testb %cl, %cl
je 0x17e6f12
xorl %ecx, %ecx
jmp 0x17e6f32
movq %r... | /llvm/ADT/DenseMap.h |
std::pair<llvm::Function const*, std::unique_ptr<llvm::CodeViewDebug::FunctionInfo, std::default_delete<llvm::CodeViewDebug::FunctionInfo>>>& llvm::SmallVectorTemplateBase<std::pair<llvm::Function const*, std::unique_ptr<llvm::CodeViewDebug::FunctionInfo, std::default_delete<llvm::CodeViewDebug::FunctionInfo>>>, false>... | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r12
movq %rdx, %r13
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %rbp
movl $0x10, %ecx
movq %r15, %rsi
xorl %edx, %edx
movq %rbp, %r8
callq 0x208eb04
movq %rax, %r14
movl 0x8(%rbx), %eax
shlq $0x4, %rax
movq (%r13), %rcx
movq (... | /llvm/ADT/SmallVector.h |
llvm::detail::DenseMapPair<llvm::OffsetAndUnitID, llvm::MCSymbol*>* llvm::DenseMapBase<llvm::DenseMap<llvm::OffsetAndUnitID, llvm::MCSymbol*, llvm::DenseMapInfo<llvm::OffsetAndUnitID, void>, llvm::detail::DenseMapPair<llvm::OffsetAndUnitID, llvm::MCSymbol*>>, llvm::OffsetAndUnitID, llvm::MCSymbol*, llvm::DenseMapInfo<l... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x17ee5c0
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::MachineRegisterInfo::constrainRegAttrs(llvm::Register, llvm::Register, unsigned int) | bool
MachineRegisterInfo::constrainRegAttrs(Register Reg,
Register ConstrainingReg,
unsigned MinNumRegs) {
const LLT RegTy = getType(Reg);
const LLT ConstrainingRegTy = getType(ConstrainingReg);
if (RegTy.isValid() && ConstrainingRegTy.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %r8d
movl %esi, %ebp
movq %rdi, %rbx
testl %esi, %esi
jns 0x1930407
movl %ebp, %eax
andl $0x7fffffff, %eax # imm = 0x7FFFFFFF
cmpl %eax, 0x1d0(%rbx)
jbe 0x1930407
movl %eax, %eax
movq 0x1c8(%rbx), %rcx
movq (%rcx,%rax,8), %rax... | /CodeGen/MachineRegisterInfo.cpp |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [37], llvm::cl::initializer<int>, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [37], llvm::cl::initializer<int> const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x6ea2b0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x206a93a
movq (%r14), %rax
movl (%rax), %eax
movl %eax, 0x80(%r12)
movb $0x1, 0x94(%r12)
movl %eax, 0x90(%r12)
movu... | /llvm/Support/CommandLine.h |
llvm::SmallDenseMap<llvm::MachineBasicBlock const*, std::unique_ptr<llvm::CoalescingBitVector<unsigned long>, std::default_delete<llvm::CoalescingBitVector<unsigned long>>>, 4u, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, std::unique_ptr<llvm::Coa... | void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %eax
movl %eax, %ecx
orl $0x1, %ecx
movl %ecx, (%rdi)
cmpl $0x5, %esi
jb 0x1a56502
movl %esi, %ebp
andl $-0x2, %eax
movl %eax, (%rbx)
movl %esi, %edi
shlq $0x4, %rdi
movl $0x8, %esi
callq 0x2085c34
movq %rax, 0x8(%rbx)
movl %ebp, 0x10(%rbx)
leaq 0x8(%rbx), %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::MemLocFragmentFill::coalesceFragments(llvm::BasicBlock&, llvm::PointerUnion<llvm::Instruction const*, llvm::DbgRecord const*>, unsigned int, unsigned int, unsigned int, unsigned int, llvm::DebugLoc, llvm::IntervalMap<unsigned int, unsigned int, 16u, llvm::IntervalMapHalfOpenInfo<unsigned int>> co... | void coalesceFragments(BasicBlock &BB, VarLocInsertPt Before, unsigned Var,
unsigned StartBit, unsigned EndBit, unsigned Base,
DebugLoc DL, const FragsInMemMap &FragMap) {
if (!CoalesceAdjacentFragments)
return;
// We've inserted the location into the map.... | cmpb $0x1, 0x18(%rdi)
jne 0x1a910c5
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movl %r9d, %ebp
movl %r8d, %r13d
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, 0xc(%rsp)
movq 0xb0(%rsp), %rax
leaq 0x28(%rsp), %rcx
movq %rax, -0x18(%rcx)
movq %rcx, -0x10(%rcx)
movabsq $... | /CodeGen/AssignmentTrackingAnalysis.cpp |
llvm::InterferenceCache::get(llvm::MCRegister) | InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
unsigned char E = PhysRegEntries[PhysReg.id()];
if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
if (!Entries[E].valid(LIUArray, TRI))
Entries[E].revalidate(LIUArray, TRI);
return &Entries[E];
}
// No valid entry e... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x18(%rdi), %rax
movl %esi, %r15d
movzbl (%rax,%r15), %eax
cmpq $0x1f, %rax
ja 0x1aa83ab
imulq $0x2d0, %rax, %rax # imm = 0x2D0
cmpl %esi, 0x30(%rbx,%rax)
jne 0x1aa83ab
leaq (%rbx,%rax), %r14
addq $0x30, %r14
movq (%rbx), %r15
movq 0x8(%rb... | /CodeGen/InterferenceCache.cpp |
std::pair<llvm::DenseMapIterator<llvm::LiveInterval*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::LiveInterval*, void>, llvm::detail::DenseSetPair<llvm::LiveInterval*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::LiveInterval*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::LiveInterval*, voi... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0x1aaca56
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0x1aaca18
xorl %ecx, %ecx
jmp 0x1aaca31
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %r... | /llvm/ADT/DenseMap.h |
llvm::MachineModuleSlotTracker::processMachineModule(llvm::AbstractSlotTrackerStorage*, llvm::Module const*, bool) | void MachineModuleSlotTracker::processMachineModule(
AbstractSlotTrackerStorage *AST, const Module *M,
bool ShouldInitializeAllMetadata) {
if (ShouldInitializeAllMetadata) {
for (const Function &F : *M) {
if (&F != &TheFunction)
continue;
MDNStartSlot = AST->getNextMetadataSlot();
... | testl %ecx, %ecx
je 0x1ab01f0
movq 0x20(%rdx), %rax
addq $0x18, %rdx
cmpq %rdx, %rax
je 0x1ab01f0
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movq 0x70(%rdi), %rcx
leaq -0x38(%rax), %r15
testq %rax, %rax
cmoveq %rax, %r15
cmpq %rcx, %r15
je 0x1ab01b1
movq 0x8(%rax), %rax
cmpq %rdx, %rax
jne 0x1ab01... | /CodeGen/MachineModuleSlotTracker.cpp |
llvm::ConstantRange::smul_fast(llvm::ConstantRange const&) const | ConstantRange ConstantRange::smul_fast(const ConstantRange &Other) const {
if (isEmptySet() || Other.isEmptySet())
return getEmpty();
APInt Min = getSignedMin();
APInt Max = getSignedMax();
APInt OtherMin = Other.getSignedMin();
APInt OtherMax = Other.getSignedMax();
bool O1, O2, O3, O4;
auto Muls =... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x1ae3236
testb %al, %al
jne 0x1af0578
movq %r12, %rdi
callq 0x1ae3236
testb %al, %al
je 0x1af059b
movl 0x8(%r14), %esi
movq %rbx, %rdi
xorl %edx, %edx
callq 0x1ae2d98... | /IR/ConstantRange.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MDNode*, void>, llvm::detail::DenseSetPair<llvm::MDNode*>>, llvm::MDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MDNode*, void>, llvm::detail::DenseSetPair<llvm::MDNode*>>::LookupBucketFor<llvm::M... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x1b1c4a6
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movq (%r11), %rbx
cmpq %rbx, (%rsi)
jne 0x1b1c46d
movq %... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseSetPair<llvm::MDNode*>* llvm::DenseMapBase<llvm::DenseMap<llvm::MDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MDNode*, void>, llvm::detail::DenseSetPair<llvm::MDNode*>>, llvm::MDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MDNode*, void>, llvm::detail::DenseSetPair<ll... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x1b1c501
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::at::VarRecord::VarRecord(llvm::DbgVariableRecord*) | VarRecord(DbgVariableRecord *DVR)
: Var(DVR->getVariable()), DL(getDebugValueLoc(DVR)) {} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x48(%rsi), %rdi
callq 0x1b384e0
movq %rax, (%rbx)
leaq 0x8(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq 0x1b16cc0
movq %r15, %rdi
callq 0x1b3a2e8
movq %rax, %r14
movq (%r15), %rsi
testq %rsi, %rsi
je 0x1b1d950
leaq 0x8(%rsp), %... | /llvm/IR/DebugInfo.h |
llvm::DenseMap<llvm::AllocaInst const*, llvm::SmallSetVector<llvm::at::VarRecord, 2u>, llvm::DenseMapInfo<llvm::AllocaInst const*, void>, llvm::detail::DenseMapPair<llvm::AllocaInst const*, llvm::SmallSetVector<llvm::at::VarRecord, 2u>>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x10(%rdi), %r15d
decl %esi
movl %esi, %eax
shrl %eax
orl %esi, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x10, %eax
orl %ecx, %eax
incl %ea... | /llvm/ADT/DenseMap.h |
void llvm::SmallVectorImpl<llvm::DbgAssignIntrinsic*>::append<llvm::at::DbgAssignIt, void>(llvm::at::DbgAssignIt, llvm::at::DbgAssignIt) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
xorl %r12d, %r12d
cmpq %rdx, %rsi
je 0x1b1f80c
movq %r15, %rax
movq 0x8(%rax), %rax
incq %r12
cmpq %r14, %rax
jne 0x1b1f800
movl 0x8(%rbx), %edx
movl 0xc(%rbx), %eax
addq %r12, %rdx
cmpq %rax, %rdx
jbe 0x1b1f82b
leaq ... | /llvm/ADT/SmallVector.h |
llvm::DbgVariableIntrinsic::getFragmentOrEntireVariable() const | DIExpression::FragmentInfo getFragmentOrEntireVariable() const {
DIExpression::FragmentInfo VariableSlice(0, 0);
// Get the fragment or variable size, or zero.
if (auto Sz = getFragmentSizeInBits())
VariableSlice.SizeInBits = *Sz;
if (auto Frag = getExpression()->getFragmentInfo())
VariableS... | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %r15
callq 0x1b76094
movq %rax, %rbx
xorl %r14d, %r14d
testb $0x1, %dl
cmoveq %r14, %rbx
movl 0x4(%r15), %eax
shll $0x5, %eax
subq %rax, %r15
movq 0x40(%r15), %rax
movq 0x18(%rax), %rax
movq 0x10(%rax), %rsi
movq 0x18(%rax), %rdx
leaq 0x8(%rsp), %r15
movq %r1... | /llvm/IR/IntrinsicInst.h |
llvm::DILocation::getImpl(llvm::LLVMContext&, unsigned int, unsigned int, llvm::Metadata*, llvm::Metadata*, bool, llvm::Metadata::StorageType, bool) | DILocation *DILocation::getImpl(LLVMContext &Context, unsigned Line,
unsigned Column, Metadata *Scope,
Metadata *InlinedAt, bool ImplicitCode,
StorageType Storage, bool ShouldCreate) {
// Fixup column.
adjustColumn(Colum... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movl %r9d, 0x10(%rsp)
movq %r8, %r13
movq %rcx, %rbx
movl %esi, 0x14(%rsp)
movq %rdi, %r14
xorl %r12d, %r12d
cmpl $0x10000, %edx # imm = 0x10000
cmovbl %edx, %r12d
cmpl $0x0, 0x80(%rsp)
jne 0x1b1fc80
movb 0x88(%rsp), %bpl
movq (... | /IR/DebugInfoMetadata.cpp |
llvm::DISubrange::getImpl(llvm::LLVMContext&, llvm::Metadata*, llvm::Metadata*, llvm::Metadata*, llvm::Metadata*, llvm::Metadata::StorageType, bool) | DISubrange *DISubrange::getImpl(LLVMContext &Context, Metadata *CountNode,
Metadata *LB, Metadata *UB, Metadata *Stride,
StorageType Storage, bool ShouldCreate) {
DEFINE_GETIMPL_LOOKUP(DISubrange, (CountNode, LB, UB, Stride));
Metadata *Ops[] = {CountN... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r9d, %ebx
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r14
testl %r9d, %r9d
jne 0x1b21885
movb 0x70(%rsp), %r15b
movq (%r14), %r12
leaq 0x2b8(%r12), %rdi
leaq 0x10(%rsp), %rsi
movq %rbp, (%rsi)
movq %r13, 0x8(%rsi)
movq %rcx, (%rsp)... | /IR/DebugInfoMetadata.cpp |
llvm::DICompileUnit::nameTableKindString(llvm::DICompileUnit::DebugNameTableKind) | const char *DICompileUnit::nameTableKindString(DebugNameTableKind NTK) {
switch (NTK) {
case DebugNameTableKind::Default:
return nullptr;
case DebugNameTableKind::GNU:
return "GNU";
case DebugNameTableKind::Apple:
return "Apple";
case DebugNameTableKind::None:
return "None";
}
return nullp... | decl %edi
cmpl $0x2, %edi
ja 0x1b23530
movl %edi, %eax
leaq 0x30be658(%rip), %rcx # 0x4be1b80
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
retq
xorl %eax, %eax
retq
nop
| /IR/DebugInfoMetadata.cpp |
llvm::DILexicalBlockFile* llvm::MDNode::storeImpl<llvm::DILexicalBlockFile, llvm::DenseSet<llvm::DILexicalBlockFile*, llvm::MDNodeInfo<llvm::DILexicalBlockFile>>>(llvm::DILexicalBlockFile*, llvm::Metadata::StorageType, llvm::DenseSet<llvm::DILexicalBlockFile*, llvm::MDNodeInfo<llvm::DILexicalBlockFile>>&) | T *MDNode::storeImpl(T *N, StorageType Storage, StoreT &Store) {
switch (Storage) {
case Uniqued:
Store.insert(N);
break;
case Distinct:
N->storeDistinctInContext();
break;
case Temporary:
break;
}
return N;
} | subq $0x28, %rsp
movq %rdi, 0x8(%rsp)
cmpl $0x1, %esi
je 0x1b241c2
testl %esi, %esi
jne 0x1b241c7
leaq 0x10(%rsp), %rdi
leaq 0x8(%rsp), %rax
leaq 0x7(%rsp), %rcx
movq %rdx, %rsi
movq %rax, %rdx
callq 0x1b2fe30
jmp 0x1b241c7
callq 0x1b91620
movq 0x8(%rsp), %rax
addq $0x28, %rsp
retq
nop
| /IR/MetadataImpl.h |
llvm::DITemplateValueParameter* llvm::MDNode::storeImpl<llvm::DITemplateValueParameter, llvm::DenseSet<llvm::DITemplateValueParameter*, llvm::MDNodeInfo<llvm::DITemplateValueParameter>>>(llvm::DITemplateValueParameter*, llvm::Metadata::StorageType, llvm::DenseSet<llvm::DITemplateValueParameter*, llvm::MDNodeInfo<llvm::... | T *MDNode::storeImpl(T *N, StorageType Storage, StoreT &Store) {
switch (Storage) {
case Uniqued:
Store.insert(N);
break;
case Distinct:
N->storeDistinctInContext();
break;
case Temporary:
break;
}
return N;
} | subq $0x28, %rsp
movq %rdi, 0x8(%rsp)
cmpl $0x1, %esi
je 0x1b24942
testl %esi, %esi
jne 0x1b24947
leaq 0x10(%rsp), %rdi
leaq 0x8(%rsp), %rax
leaq 0x7(%rsp), %rcx
movq %rdx, %rsi
movq %rax, %rdx
callq 0x1b32276
jmp 0x1b24947
callq 0x1b91620
movq 0x8(%rsp), %rax
addq $0x28, %rsp
retq
nop
| /IR/MetadataImpl.h |
llvm::DIGlobalVariable* llvm::MDNode::storeImpl<llvm::DIGlobalVariable, llvm::DenseSet<llvm::DIGlobalVariable*, llvm::MDNodeInfo<llvm::DIGlobalVariable>>>(llvm::DIGlobalVariable*, llvm::Metadata::StorageType, llvm::DenseSet<llvm::DIGlobalVariable*, llvm::MDNodeInfo<llvm::DIGlobalVariable>>&) | T *MDNode::storeImpl(T *N, StorageType Storage, StoreT &Store) {
switch (Storage) {
case Uniqued:
Store.insert(N);
break;
case Distinct:
N->storeDistinctInContext();
break;
case Temporary:
break;
}
return N;
} | subq $0x28, %rsp
movq %rdi, 0x8(%rsp)
cmpl $0x1, %esi
je 0x1b24b6e
testl %esi, %esi
jne 0x1b24b73
leaq 0x10(%rsp), %rdi
leaq 0x8(%rsp), %rax
leaq 0x7(%rsp), %rcx
movq %rdx, %rsi
movq %rax, %rdx
callq 0x1b32ca0
jmp 0x1b24b73
callq 0x1b91620
movq 0x8(%rsp), %rax
addq $0x28, %rsp
retq
nop
| /IR/MetadataImpl.h |
llvm::lexMIToken(llvm::StringRef, llvm::MIToken&, llvm::function_ref<void (char const*, llvm::Twine const&)>) | StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
ErrorCallbackType ErrorCallback) {
auto C = skipComment(skipWhitespace(Cursor(Source)));
if (C.isEOF()) {
Token.reset(MIToken::Eof, C.remaining());
return C.remaining();
}
C = skipMachineOperandComment(C);
if (Cu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %r8, %r14
movq %rcx, %r13
movq %rdx, %r15
leaq (%rdi,%rsi), %r12
movq %rdi, 0x50(%rsp)
leaq -0x1(%rdi), %rbp
movq %rsi, 0x48(%rsp)
movq %rsi, %rcx
movq %rcx, %rbx
testq %rcx, %rcx
jle 0x1c5ded6
movsbl 0x1(%... | /CodeGen/MIRParser/MILexer.cpp |
maybeLexSubRegisterIndex((anonymous namespace)::Cursor, llvm::MIToken&, llvm::function_ref<void (char const*, llvm::Twine const&)>) | StringRef remaining() const { return StringRef(Ptr, End - Ptr); } | movq %rsi, %rax
subq %rdi, %rax
cmpq $0x8, %rax
jb 0x1c5f9f4
movabsq $0x2e67657262757325, %rax # imm = 0x2E67657262757325
cmpq %rax, (%rdi)
je 0x1c5f9f9
xorl %edx, %edx
xorl %eax, %eax
retq
subq $0x28, %rsp
movq %rcx, 0x18(%rsp)
movq %r8, 0x20(%rsp)
movups 0x18(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0x8d, %ecx
movl $0... | /CodeGen/MIRParser/MILexer.cpp |
maybeLexSymbol((anonymous namespace)::Cursor, llvm::MIToken&) | static Cursor maybeLexSymbol(Cursor C, MIToken &Token) {
MIToken::TokenKind Kind;
unsigned Length = 1;
if (C.peek() == ':' && C.peek(1) == ':') {
Kind = MIToken::coloncolon;
Length = 2;
} else
Kind = symbolToken(C.peek());
if (Kind == MIToken::Error)
return std::nullopt;
auto Range = C;
C.... | movq %rdx, %rcx
movq %rsi, %rdx
movq %rdi, %rax
subq %rdi, %rsi
testq %rsi, %rsi
jle 0x1c60764
cmpq $0x1, %rsi
je 0x1c6075a
cmpb $0x3a, (%rax)
jne 0x1c6075a
cmpb $0x3a, 0x1(%rax)
jne 0x1c6075a
movl $0x7, %edi
movl $0x2, %esi
jmp 0x1c607f0
testq %rsi, %rsi
jle 0x1c60764
movb (%rax), %sil
jmp 0x1c60766
xorl %esi, %esi
mo... | /CodeGen/MIRParser/MILexer.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MDNode*, llvm::SmallVector<llvm::Instruction*, 4u>, llvm::DenseMapInfo<llvm::MDNode*, void>, llvm::detail::DenseMapPair<llvm::MDNode*, llvm::SmallVector<llvm::Instruction*, 4u>>>, llvm::MDNode*, llvm::SmallVector<llvm::Instruction*, 4u>, llvm::DenseMapInfo<llvm::MDNode*, void>, l... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %eax
testq %rax, %rax
je 0x1d02488
pushq %r15
pushq %r14
pushq %rbx
movq (%rdi), %rbx
imulq $0x38, %rax, %r14
addq $0x18, %rbx
movl $0x1000, %r15d # imm = 0x1000
movq -0x18(%rbx), %rax
orq %r15, %rax
cmpq $-0x1000, %rax # imm = 0xF000
je 0x1d02479
movq -0x10(%rbx), %rdi
cmpq %rdi, %rb... | /llvm/ADT/DenseMap.h |
llvm::hoistRegion(llvm::DomTreeNodeBase<llvm::BasicBlock>*, llvm::AAResults*, llvm::LoopInfo*, llvm::DominatorTree*, llvm::AssumptionCache*, llvm::TargetLibraryInfo*, llvm::Loop*, llvm::MemorySSAUpdater&, llvm::ScalarEvolution*, llvm::ICFLoopSafetyInfo*, llvm::SinkAndHoistLICMFlags&, llvm::OptimizationRemarkEmitter*, b... | bool llvm::hoistRegion(DomTreeNode *N, AAResults *AA, LoopInfo *LI,
DominatorTree *DT, AssumptionCache *AC,
TargetLibraryInfo *TLI, Loop *CurLoop,
MemorySSAUpdater &MSSAU, ScalarEvolution *SE,
ICFLoopSafetyInfo *SafetyInfo,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x368, %rsp # imm = 0x368
movq %r9, 0x288(%rsp)
movq %r8, 0x198(%rsp)
movq %rdx, %r14
movq %rsi, 0x290(%rsp)
movq 0x3b8(%rsp), %r12
movq 0x3a8(%rsp), %rax
movq 0x3a0(%rsp), %r15
movq %rdx, 0x1e8(%rsp)
movq %rcx, 0x18(%rsp)
movq %rcx, 0x1... | /Transforms/Scalar/LICM.cpp |
isSafeToExecuteUnconditionally(llvm::Instruction&, llvm::DominatorTree const*, llvm::TargetLibraryInfo const*, llvm::Loop const*, llvm::LoopSafetyInfo const*, llvm::OptimizationRemarkEmitter*, llvm::Instruction const*, llvm::AssumptionCache*, bool) | static bool isSafeToExecuteUnconditionally(
Instruction &Inst, const DominatorTree *DT, const TargetLibraryInfo *TLI,
const Loop *CurLoop, const LoopSafetyInfo *SafetyInfo,
OptimizationRemarkEmitter *ORE, const Instruction *CtxI,
AssumptionCache *AC, bool AllowSpeculation) {
if (AllowSpeculation &&
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x368, %rsp # imm = 0x368
movq %r9, %rbx
movq %r8, %r12
movq %rcx, %r14
movq %rsi, %r13
movq %rdi, %r15
cmpb $0x0, 0x3b0(%rsp)
je 0x1d7186f
movq %rdx, %r8
movq 0x3a8(%rsp), %rdx
movq 0x3a0(%rsp), %rsi
movq %r15, %rdi
movq %r13, %rcx
movl... | /Transforms/Scalar/LICM.cpp |
llvm::cl::SubCommand::unregisterSubCommand() | void SubCommand::unregisterSubCommand() {
GlobalParser->unregisterSubCommand(this);
} | pushq %rbx
movq %rdi, %rbx
movq 0x360e333(%rip), %rax # 0x5678fb0
testq %rax, %rax
jne 0x206ac9c
leaq 0x360e327(%rip), %rdi # 0x5678fb0
leaq 0xb036(%rip), %rsi # 0x2075cc6
leaq 0xb0fd(%rip), %rdx # 0x2075d94
callq 0x2085b64
movq 0x360e30d(%rip), %rdi # 0x5678fb0
addq $0x118, %rdi # imm = 0x11... | /Support/CommandLine.cpp |
llvm::DenseMap<llvm::StringRef, llvm::vfs::RedirectingFileSystemParser::KeyStatus, llvm::DenseMapInfo<llvm::StringRef, void>, llvm::detail::DenseMapPair<llvm::StringRef, llvm::vfs::RedirectingFileSystemParser::KeyStatus>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x10(%rdi), %r15d
decl %esi
movl %esi, %eax
shrl %eax
orl %esi, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x10, %eax
orl %ecx, %eax
incl %ea... | /llvm/ADT/DenseMap.h |
llvm::vfs::RedirectingFileSystem::Entry::~Entry() | virtual ~Entry() = default; | leaq 0x34f2fe5(%rip), %rax # 0x55a1f90
addq $0x10, %rax
movq %rax, (%rdi)
movq 0x10(%rdi), %rax
addq $0x20, %rdi
cmpq %rdi, %rax
je 0x20aefcd
movq (%rdi), %rsi
incq %rsi
movq %rax, %rdi
jmp 0x6ea0d0
retq
| /llvm/Support/VirtualFileSystem.h |
llvm::cl::opt<double, false, llvm::cl::parser<double>>::opt<char [22], llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [22], llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorl %esi, %esi
xorl %edx, %edx
callq 0x75d9e4
xorps %xmm0, %xmm0
movups %xmm0, 0x90(%rbx)
movups %xmm0, 0x80(%rbx)
movb $0x0, 0x98(%rbx)
leaq 0x33522b2(%rip), %rax # 0x546b3e0
addq $0x10, %rax
movq ... | /llvm/Support/CommandLine.h |
llvm::memtag::getPC(llvm::Triple const&, llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&) | Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB) {
Module *M = IRB.GetInsertBlock()->getParent()->getParent();
if (TargetTriple.getArch() == Triple::aarch64)
return memtag::readRegister(IRB, "pc");
return IRB.CreatePtrToInt(IRB.GetInsertBlock()->getParent(),
IRB.getIntPtr... | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
cmpl $0x3, 0x20(%rdi)
jne 0x2172b52
leaq 0xe14382(%rip), %rsi # 0x2f86ec0
movl $0x2, %edx
movq %rbx, %rdi
addq $0x28, %rsp
popq %rbx
popq %r14
jmp 0x2172a46
movq 0x30(%rbx), %rax
movq 0x48(%rbx), %rsi
movq 0x48(%rax), %r14
movl $0x120, %edi # imm = 0x... | /Transforms/Utils/MemoryTaggingSupport.cpp |
llvm::PredicateInfoBuilder::buildPredicateInfo() | void PredicateInfoBuilder::buildPredicateInfo() {
DT.updateDFSNumbers();
// Collect operands to rename from all conditional branch terminators, as well
// as assume statements.
SmallVector<Value *, 8> OpsToRename;
for (auto *DTN : depth_first(DT.getRootNode())) {
BasicBlock *BranchBB = DTN->getBlock();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x238, %rsp # imm = 0x238
movq %rdi, %rbx
movq 0x10(%rdi), %rdi
callq 0x1b3de68
leaq 0x108(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
movq 0x10(%rbx), %rax
movq 0x30(%rax)... | /Transforms/Utils/PredicateInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<std::pair<unsigned int, unsigned int>, llvm::PHINode*, llvm::DenseMapInfo<std::pair<unsigned int, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<unsigned int, unsigned int>, llvm::PHINode*>>, std::pair<unsigned int, unsigned int>, llvm::PHINode*, llvm::DenseMapInfo<std::pai... | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %ecx
testl %ecx, %ecx
jne 0x217f3c3
cmpl $0x0, 0xc(%rdi)
je 0x217f403
shll $0x2, %ecx
movl 0x10(%rdi), %eax
cmpl %eax, %ecx
setae %cl
cmpl $0x41, %eax
setb %dl
orb %cl, %dl
je 0x2182280
testq %rax, %rax
je 0x217f3fb
movq (%rdi), %rcx
shlq $0x4, %rax
addq %rcx, %rax
movq $-0x1, (%rcx)
addq $0x10, %rcx
cm... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorTemplateBase<llvm::CoroSaveInst*, true>::push_back(llvm::CoroSaveInst*) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x22de79d
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x208ec4e... | /llvm/ADT/SmallVector.h |
llvm::coro::Shape::emitAlloc(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::Value*, llvm::CallGraph*) const | Value *coro::Shape::emitAlloc(IRBuilder<> &Builder, Value *Size,
CallGraph *CG) const {
switch (ABI) {
case coro::ABI::Switch:
llvm_unreachable("can't allocate memory in coro switch-lowering");
case coro::ABI::Retcon:
case coro::ABI::RetconOnce: {
auto Alloc = RetconLoweri... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rcx, %rbx
movq %rsi, %r15
movq %rdx, 0x8(%rsp)
movq 0x158(%rdi), %r14
movq 0x18(%r14), %rax
movq 0x10(%rax), %rax
movq 0x8(%rax), %rax
leaq 0x10(%rsp), %r8
movw $0x101, 0x20(%r8) # imm = 0x101
xorl %r12d, %r12d
movq %rsi, %rdi
movq %rdx, %rsi
movq... | /Transforms/Coroutines/Coroutines.cpp |
emitSetAndGetSwiftErrorValueAround(llvm::Instruction*, llvm::AllocaInst*, llvm::coro::Shape&) | static Value *emitSetAndGetSwiftErrorValueAround(Instruction *Call,
AllocaInst *Alloca,
coro::Shape &Shape) {
auto ValueTy = Alloca->getAllocatedType();
IRBuilder<> Builder(Call);
// Load the current value from the ... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc0, %rsp
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r13
movq 0x48(%rsi), %r12
leaq 0x30(%rsp), %r14
movq %r14, %rdi
movq %r13, %rsi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq 0x89b1fa
leaq 0x8(%rsp), %r9
movw $0x101, 0x20(%r9) # imm = 0x10... | /Transforms/Coroutines/CoroFrame.cpp |
emitSetSwiftErrorValue(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::Value*, llvm::coro::Shape&) | static Value *emitSetSwiftErrorValue(IRBuilder<> &Builder, Value *V,
coro::Shape &Shape) {
// Make a fake function pointer as a sort of intrinsic.
auto FnTy = FunctionType::get(Builder.getPtrTy(),
{V->getType()}, false);
auto Fn = ConstantPointe... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movq 0x48(%rdi), %rdi
xorl %esi, %esi
callq 0x1bb5058
movq 0x8(%r15), %rcx
leaq 0x18(%rsp), %r12
movq %rcx, (%r12)
movl $0x1, %edx
movq %rax, %rdi
movq %r12, %rsi
xorl %ecx, %ecx
callq 0x1bb515e
movq ... | /Transforms/Coroutines/CoroFrame.cpp |
llvm::SmallDenseMap<llvm::Instruction*, unsigned int, 8u, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, unsigned int>>::init(unsigned int) | void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %eax
movl %eax, %ecx
orl $0x1, %ecx
movl %ecx, (%rdi)
cmpl $0x9, %esi
jb 0x22e9bb2
movl %esi, %ebp
andl $-0x2, %eax
movl %eax, (%rbx)
movl %esi, %edi
shlq $0x4, %rdi
movl $0x8, %esi
callq 0x2085c34
movq %rax, 0x8(%rbx)
movl %ebp, 0x10(%rbx)
leaq 0x8(%rbx), %... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<llvm::Instruction*, unsigned int, 8u, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, unsigned int>>, llvm::Instruction*, unsigned int, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, unsigne... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rdi), %rax
andl $0x1, (%rdi)
movl $0x0, 0x4(%rdi)
cmoveq 0x8(%rdi), %rax
movl $0x8, %ecx
cmovel 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x22ea74c
movl %ecx, %ecx
movabsq $0xfffffffffffffff, %rd... | /llvm/ADT/DenseMap.h |
Subsets and Splits
SQL Console for LLM4Binary/decompile-bench
Filters out entries with file names ending in .cpp, providing a basic subset of the dataset that excludes C++ files.