name string | code string | asm string | file string |
|---|---|---|---|
LowerPREFETCH(llvm::SDValue, llvm::SelectionDAG&) | static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
SDLoc DL(Op);
unsigned IsWrite = Op.getConstantOperandVal(2);
unsigned Locality = Op.getConstantOperandVal(3);
unsigned IsData = Op.getConstantOperandVal(4);
bool IsStream = !Locality;
// When the locality number is set
if (Locality) {
// ... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rdi), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0x9dcd99
leaq 0x30(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14), %eax
movl %eax, 0x38(%rsp)
movq 0x28(%r14), %rax
movq 0x50(%rax), %rcx
movq 0x58(%r... | /Target/AArch64/AArch64ISelLowering.cpp |
changeIntCCToAArch64CC(llvm::ISD::CondCode) | static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
switch (CC) {
default:
llvm_unreachable("Unknown condition code!");
case ISD::SETNE:
return AArch64CC::NE;
case ISD::SETEQ:
return AArch64CC::EQ;
case ISD::SETGT:
return AArch64CC::GT;
case ISD::SETGE:
return AArch64CC... | movslq %edi, %rax
leaq 0x2a79d9f(%rip), %rcx # 0x34655f8
movl -0x28(%rcx,%rax,4), %eax
retq
| /Target/AArch64/AArch64ISelLowering.cpp |
llvm::APInt::isMask() const | bool isMask() const {
if (isSingleWord())
return isMask_64(U.VAL);
unsigned Ones = countTrailingOnesSlowCase();
return (Ones > 0) && ((Ones + countLeadingZerosSlowCase()) == BitWidth);
} | pushq %rbp
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x8(%rdi), %r14d
cmpl $0x40, %r14d
ja 0xa2b676
movq (%rbx), %rax
testq %rax, %rax
setne %cl
leaq 0x1(%rax), %rdx
testq %rax, %rdx
sete %al
andb %cl, %al
jmp 0xa2b698
movq %rbx, %rdi
callq 0x1c83022
testl %eax, %eax
je 0xa2b696
movl %eax, %ebp
movq %rbx, %rdi
callq 0... | /llvm/ADT/APInt.h |
llvm::SDNode::hasPredecessorHelper(llvm::SDNode const*, llvm::SmallPtrSetImpl<llvm::SDNode const*>&, llvm::SmallVectorImpl<llvm::SDNode const*>&, unsigned int, bool) | static bool hasPredecessorHelper(const SDNode *N,
SmallPtrSetImpl<const SDNode *> &Visited,
SmallVectorImpl<const SDNode *> &Worklist,
unsigned int MaxSteps = 0,
bool TopologicalPr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r8d, %ebp
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r13
movq %rdi, %r15
leaq 0x48(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
movq %rsi, %rdi
movq %r15, %rsi
callq ... | /llvm/CodeGen/SelectionDAGNodes.h |
llvm::IRBuilderBase::CreatePointerCast(llvm::Value*, llvm::Type*, llvm::Twine const&) | Value *CreatePointerCast(Value *V, Type *DestTy,
const Twine &Name = "") {
if (V->getType() == DestTy)
return V;
if (auto *VC = dyn_cast<Constant>(V))
return Insert(Folder.CreatePointerCast(VC, DestTy), Name);
return Insert(CastInst::CreatePointerCast(V, DestTy), Name)... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r12
cmpq %rdx, 0x8(%rsi)
je 0xa2cd65
movq %rcx, %r14
movq %rdx, %r15
movq %rdi, %rbx
movb (%r12), %bpl
cmpb $0x15, %bpl
ja 0xa2cd1e
movq 0x50(%rbx), %rdi
movq (%rdi), %rax
movq %r12, %rsi
movq %r15, %rdx
callq *0x88(%rax)
mov... | /llvm/IR/IRBuilder.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, std::unique_ptr<llvm::DomTreeNodeBase<llvm::BasicBlock>, std::default_delete<llvm::DomTreeNodeBase<llvm::BasicBlock>>>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, std::unique_ptr<llvm::DomTreeNodeBase<llvm::BasicBlock>,... | unsigned getNumBuckets() const {
return NumBuckets;
} | pushq %r15
pushq %r14
pushq %rbx
movl 0x10(%rdi), %r14d
testq %r14, %r14
je 0xa674d9
movq (%rdi), %rbx
shlq $0x4, %r14
addq $0x8, %rbx
movl $0x1000, %r15d # imm = 0x1000
movq -0x8(%rbx), %rax
orq %r15, %rax
cmpq $-0x1000, %rax # imm = 0xF000
je 0xa674cf
movq (%rbx), %rsi
testq %rsi, %rsi
je 0xa674c8
m... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AArch64FastISel::emitLogicalOp(unsigned int, llvm::MVT, llvm::Value const*, llvm::Value const*) | unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
const Value *LHS, const Value *RHS) {
// Canonicalize immediates to the RHS first.
if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
std::swap(LHS, RHS);
// Canonicalize mul by power-of-2 to the RHS... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %r15
movq %rcx, %r12
movl %edx, %r14d
movl %esi, %ebp
movq %rdi, %rbx
cmpb $0x11, (%rcx)
jne 0xa7975c
cmpb $0x11, (%r15)
movq %r12, %rax
cmoveq %r15, %rax
cmovneq %r15, %r12
movq %rax, %r15
movq 0x10(%r12), %rax
testq %rax, %rax
je 0... | /Target/AArch64/AArch64FastISel.cpp |
llvm::DiagnosticInfoIROptimization::DiagnosticInfoIROptimization(llvm::DiagnosticKind, llvm::DiagnosticSeverity, char const*, llvm::Function const&, llvm::DiagnosticLocation const&, llvm::Twine const&) | DiagnosticInfoIROptimization(enum DiagnosticKind Kind,
enum DiagnosticSeverity Severity,
const char *PassName, const Function &Fn,
const DiagnosticLocation &Loc, const Twine &Msg)
: DiagnosticInfoOptimizationBase(Kind, Se... | pushq %r14
pushq %rbx
subq $0x28, %rsp
movl %esi, %eax
movq %rdi, %rbx
movq 0x40(%rsp), %rsi
movl %eax, 0x8(%rdi)
movb %dl, 0xc(%rdi)
leaq 0x4d5c1fc(%rip), %rax # 0x57f3778
addq $0x10, %rax
movq %rax, (%rdi)
movq %r8, 0x10(%rdi)
movups (%r9), %xmm0
movups %xmm0, 0x18(%rdi)
movq %rcx, 0x28(%rdi)
leaq 0x347be9e(%rip), ... | /llvm/IR/DiagnosticInfo.h |
llvm::SmallVectorTemplateBase<std::function<void (llvm::AnalysisManager<llvm::Loop, llvm::LoopStandardAnalysisResults&>&)>, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x20, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x1cba3de
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0xaaba10
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0xaab9fc
call... | /llvm/ADT/SmallVector.h |
llvm::SmallVectorTemplateBase<std::function<void (llvm::AnalysisManager<llvm::MachineFunction>&)>, false>::moveElementsForGrow(std::function<void (llvm::AnalysisManager<llvm::MachineFunction>&)>*) | size_t size() const { return Size; } | pushq %r14
pushq %rbx
pushq %rax
movl 0x8(%rdi), %eax
testq %rax, %rax
je 0xaabc49
movq (%rdi), %rcx
shlq $0x5, %rax
addq $0x18, %rcx
xorl %edx, %edx
xorps %xmm0, %xmm0
movups %xmm0, (%rsi,%rdx)
movq $0x0, 0x10(%rsi,%rdx)
movq (%rcx,%rdx), %r8
movq %r8, 0x18(%rsi,%rdx)
cmpq $0x0, -0x8(%rcx,%rdx)
je 0xaabc40
leaq (%rsi,... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::GCNPassConfig::addPreISel() | bool GCNPassConfig::addPreISel() {
AMDGPUPassConfig::addPreISel();
if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createSinkingPass());
if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createAMDGPULateCodeGenPreparePass());
// Merge divergent exit nodes. StructurizeCFG won't recognize t... | pushq %rbx
movq %rdi, %rbx
callq 0xaa8a3a
movq 0x70(%rbx), %rdi
callq 0x1d068c4
testl %eax, %eax
jle 0xaad2f8
callq 0x258e1f5
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
movq 0x70(%rbx), %rdi
callq 0x1d068c4
testl %eax, %eax
jle 0xaad315
callq 0xc37369
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
leaq 0x4c4e734(... | /Target/AMDGPU/AMDGPUTargetMachine.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [39], llvm::cl::desc, llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [39], llvm::cl::desc const&, llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7512e0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movups (%r12), %xmm0
movups %xmm0, 0x20(%rbx)
movq (%r15), %rax
movb (%rax), %cl
movb %cl, ... | /llvm/Support/CommandLine.h |
llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::AddIRPass::~AddIRPass() | ~AddIRPass() {
if (!FPM.isEmpty())
MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
leaq 0x8(%rdi), %rbx
movq 0x8(%rdi), %rax
cmpq 0x10(%rdi), %rax
je 0xaafa79
movq (%rdi), %r14
movq %rsp, %r15
movq %r15, %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq 0xab0a12
movq %r14, %rdi
movq %r15, %rsi
callq 0xab09be
movq (%r15), %rdi
testq %rdi, %rdi
je 0xaafa79
mov... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::verifyStartStop(llvm::TargetPassConfig::StartStopInfo const&) const | Error CodeGenPassBuilder<Derived, TargetMachineT>::verifyStartStop(
const TargetPassConfig::StartStopInfo &Info) const {
if (Started && Stopped)
return Error::success();
if (!Started)
return make_error<StringError>(
"Can't find start pass \"" +
PIC->getPassNameForClassName(Info.Star... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
movb 0x1b8(%rsi), %al
cmpb $0x1, %al
jne 0xab0366
cmpb $0x1, 0x1b9(%rsi)
jne 0xab0331
movq $0x0, (%rbx)
jmp 0xab03dc
testb %al, %al
je 0xab0366
cmpb $0x0, 0x1b9(%rsi)
jne 0xab0325
movq 0x90(%rsi), %rdi
movq 0x20(%rdx), %rsi
movq 0x28(%rdx), %r... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::unique_function<bool (llvm::StringRef)>& llvm::SmallVectorImpl<llvm::unique_function<bool (llvm::StringRef)>>::emplace_back<llvm::CodeGenPassBuilder<llvm::AMDGPUCodeGenPassBuilder, llvm::AMDGPUTargetMachine>::setStartStopPasses(llvm::TargetPassConfig::StartStopInfo const&) const::'lambda0'(llvm::StringRef)>(llvm:... | reference emplace_back(ArgTypes &&... Args) {
if (LLVM_UNLIKELY(this->size() >= this->capacity()))
return this->growAndEmplaceBack(std::forward<ArgTypes>(Args)...);
::new ((void *)this->end()) T(std::forward<ArgTypes>(Args)...);
this->set_size(this->size() + 1);
return this->back();
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl 0x8(%rdi), %r14d
cmpl 0xc(%rdi), %r14d
jae 0xab05eb
movq (%rbx), %r15
shlq $0x5, %r14
movq 0x10(%rsi), %rax
movq %rax, 0x10(%rsp)
movups (%rsi), %xmm0
movaps %xmm0, (%rsp)
movq $0x0, 0x18(%r15,%r14)
movl $0x18, %edi
movl $0x8, %esi
callq 0x1cac6bd
m... | /llvm/ADT/SmallVector.h |
llvm::RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Module>>::printPipeline(llvm::raw_ostream&, llvm::function_ref<llvm::StringRef (llvm::StringRef)>) | void printPipeline(raw_ostream &OS,
function_ref<StringRef(StringRef)> MapClassName2PassName) {
auto ClassName = AnalysisT::name();
auto PassName = MapClassName2PassName(ClassName);
OS << "require<" << PassName << '>';
} | pushq %r15
pushq %r14
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
callq 0xab11f2
movq %rbx, %rdi
movq %rax, %rsi
callq *%r14
movq %rax, %rbx
movq %rdx, %r14
leaq 0x29bb90d(%rip), %rsi # 0x346cab6
movl $0x8, %edx
movq %r15, %rdi
callq 0x7c4562
movq %rax, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq 0x7c45... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::RequireAnalysisPass<llvm::CollectorMetadataAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Module>>, llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>>, void>::type llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::addPass<llvm::RequireAnal... | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
pushq $0x10
popq %rdi
callq 0x751940
leaq 0x4c4847e(%rip), %rcx # 0x56f9720
movq %rcx, (%rax)
movq %rsp, %r14
movq %rax, (%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0xab0ac8
movq (%r14), %rdi
testq %rdi, %rdi
je 0xab12c4
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x8, %... | /llvm/IR/PassManager.h |
llvm::RequireAnalysisPass<llvm::CollectorMetadataAnalysis, llvm::Module, llvm::AnalysisManager<llvm::Module>>::printPipeline(llvm::raw_ostream&, llvm::function_ref<llvm::StringRef (llvm::StringRef)>) | void printPipeline(raw_ostream &OS,
function_ref<StringRef(StringRef)> MapClassName2PassName) {
auto ClassName = AnalysisT::name();
auto PassName = MapClassName2PassName(ClassName);
OS << "require<" << PassName << '>';
} | pushq %r15
pushq %r14
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
callq 0xab13ce
movq %rbx, %rdi
movq %rax, %rsi
callq *%r14
movq %rax, %rbx
movq %rdx, %r14
leaq 0x29bb731(%rip), %rsi # 0x346cab6
movl $0x8, %edx
movq %r15, %rdi
callq 0x7c4562
movq %rax, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq 0x7c45... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::WinEHPreparePass, llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>>, void>::type llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::addPass<llvm::WinEHPreparePass>(llvm::WinEHPreparePass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
pushq $0x10
popq %rdi
callq 0x751940
movb (%rbx), %cl
leaq 0x4c44855(%rip), %rdx # 0x56f9d60
movq %rdx, (%rax)
movb %cl, 0x8(%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
movq %r14, %rdi
movq %rbx, %rsi
callq 0xab2b52
movq (%rbx), %rdi
testq %rdi, %rdi
je 0xa... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::PrintMIRPreparePass, llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>>, void>::type llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::addPass<llvm::PrintMIRPreparePass>(llvm::PrintMIRPreparePass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
pushq $0x10
popq %rdi
callq 0x751940
movq (%rbx), %rcx
leaq 0x4c44490(%rip), %rdx # 0x56f9f60
movq %rdx, (%rax)
movq %rcx, 0x8(%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
movq %r14, %rdi
movq %rbx, %rsi
callq 0xab0ac8
movq (%rbx), %rdi
testq %rdi, %rdi
je 0... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::PeepholeOptimizerPass, llvm::PassManager<llvm::MachineFunction, llvm::AnalysisManager<llvm::MachineFunction>>>, void>::type llvm::PassManager<llvm::MachineFunction, llvm::AnalysisManager<llvm::MachineFunction>>::addPass<llvm::PeepholeOptimizerPass>(llvm::PeepholeOptimizerPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
pushq $0x10
popq %rdi
callq 0x751940
leaq 0x4c41490(%rip), %rcx # 0x56fa1e0
movq %rcx, (%rax)
movq %rsp, %r14
movq %rax, (%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0xab6160
movq (%r14), %rdi
testq %rdi, %rdi
je 0xab8d72
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x8, %... | /llvm/IR/PassManager.h |
std::enable_if<!std::is_same_v<llvm::AMDGPUPrintfRuntimeBindingPass, llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>>, void>::type llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::addPass<llvm::AMDGPUPrintfRuntimeBindingPass>(llvm::AMDGPUPrintfRuntimeBindingPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
pushq $0x10
popq %rdi
callq 0x751940
leaq 0x4c3d26a(%rip), %rcx # 0x56fad20
movq %rcx, (%rax)
movq %rsp, %r14
movq %rax, (%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0xab0ac8
movq (%r14), %rdi
testq %rdi, %rdi
je 0xabdad8
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x8, %... | /llvm/IR/PassManager.h |
llvm::DenseMap<llvm::AnalysisKey*, std::unique_ptr<llvm::detail::AnalysisPassConcept<llvm::Function, llvm::AnalysisManager<llvm::Function>::Invalidator>, std::default_delete<llvm::detail::AnalysisPassConcept<llvm::Function, llvm::AnalysisManager<llvm::Function>::Invalidator>>>, llvm::DenseMapInfo<llvm::AnalysisKey*, vo... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::detail::AnalysisPassModel<llvm::Function, llvm::AMDGPUAA, llvm::AnalysisManager<llvm::Function>::Invalidator>::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) | std::unique_ptr<AnalysisResultConcept<IRUnitT, InvalidatorT>>
run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM,
ExtraArgTs... ExtraArgs) override {
return std::make_unique<ResultModelT>(
Pass.run(IR, AM, std::forward<ExtraArgTs>(ExtraArgs)...));
} | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rdx, %rdi
callq 0x1a28d16
movq %rax, %r14
movl $0x10, %edi
callq 0x751940
leaq 0x4c3be99(%rip), %rcx # 0x56fb110
movq %rcx, (%rax)
movq %r14, 0x8(%rax)
movq %rax, (%rbx)
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
| /llvm/IR/PassManagerInternal.h |
bool llvm::PatternMatch::match_combine_and<llvm::PatternMatch::IntrinsicID_match, llvm::PatternMatch::Argument_match<llvm::PatternMatch::deferredval_ty<llvm::Value>>>::match<llvm::Value>(llvm::Value*) | bool match(ITy *V) {
if (L.match(V))
if (R.match(V))
return true;
return false;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
callq 0x9041a6
testb %al, %al
je 0xac0c2c
cmpb $0x55, (%rbx)
jne 0xac0c2c
movl 0x8(%r14), %eax
movl 0x4(%rbx), %ecx
shll $0x5, %ecx
subq %rcx, %rbx
shlq $0x5, %rax
movq 0x10(%r14), %rcx
movq (%rcx), %rcx
cmpq (%rbx,%rax), %rcx
je 0xac0c36
xorl %eax, %eax
... | /llvm/IR/PatternMatch.h |
llvm::GCNTTIImpl::getArithmeticReductionCost(unsigned int, llvm::VectorType*, std::optional<llvm::FastMathFlags>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost
GCNTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
std::optional<FastMathFlags> FMF,
TTI::TargetCostKind CostKind) {
if (TTI::requiresOrderedReduction(FMF))
return BaseT::getArithmeticReductionCost(O... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movl %r8d, %ebx
movq %rcx, %r15
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %r12
movabsq $0x100000001, %rax # imm = 0x100000001
andq %rcx, %rax
movabsq $0x100000000, %rcx # imm = 0x100000000
cmpq %rcx, %rax
jne 0xac8f01
movq %r12, %rdi
mov... | /Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
getCallArgsTotalAllocaSize(llvm::CallBase const*, llvm::DataLayout const&) | static unsigned getCallArgsTotalAllocaSize(const CallBase *CB,
const DataLayout &DL) {
// If we have a pointer to a private array passed into a function
// it will not be optimized out, leaving scratch usage.
// This function calculates the total size in bytes of the mem... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rsi, %rbx
leaq 0x38(%rsp), %rax
movq %rax, -0x20(%rax)
movq %rax, -0x18(%rax)
movq $0x8, -0x10(%rax)
movl $0x0, -0x8(%rax)
movl 0x4(%rdi), %eax
shll $0x5, %eax
movq %rdi, %r12
subq %rax, %r12
callq 0x8f171e
cmpq %rax, %r12
je 0xaca... | /Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [32], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [32], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> cons... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq %rsi, %rdi
callq 0x7512e0
movq %r13, %rdi
movq %r12, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r15), %eax
movzwl 0xa(%r13), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
llvm::BasicTTIImplBase<llvm::GCNTTIImpl>::getBroadcastShuffleOverhead(llvm::FixedVectorType*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getBroadcastShuffleOverhead(FixedVectorType *VTy,
TTI::TargetCostKind CostKind) {
InstructionCost Cost = 0;
// Broadcast cost is equal to the cost of extracting the zero'th element
// plus the cost of inserting it into every element of the result... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ecx
movq %rsi, %rbx
movq $0x0, (%rsp)
xorl %r12d, %r12d
movq %rdi, %r14
movl $0x3d, %esi
movq %rbx, %rdx
movl %ecx, %r15d
xorl %r8d, %r8d
xorl %r9d, %r9d
callq 0xac94d6
movq %rax, %r13
xorl %ebp, %ebp
cmpl $0x1, %edx
sete %bp... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::GCNTTIImpl>::getExtractSubvectorOverhead(llvm::VectorType*, llvm::TargetTransformInfo::TargetCostKind, int, llvm::FixedVectorType*) | InstructionCost getExtractSubvectorOverhead(VectorType *VTy,
TTI::TargetCostKind CostKind,
int Index,
FixedVectorType *SubVTy) {
assert(VTy && SubVTy &&
"Can only extr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %rax
movl 0x20(%r8), %esi
testl %esi, %esi
je 0xacd632
movq %rdi, 0x20(%rsp)
xorl %r14d, %r14d
xorl %r13d, %r13d
xorl %ebp, %ebp
movq %r8, 0x18(%rsp)
movl %edx, 0xc(%rsp)
movq %rcx, 0x30(%rsp)
movq %rax, 0x28(%rsp)
movl %esi, ... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::AMDGPUUnifyDivergentExitNodesPass::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) | PreservedAnalyses
AMDGPUUnifyDivergentExitNodesPass::run(Function &F,
FunctionAnalysisManager &AM) {
DominatorTree *DT = nullptr;
if (RequireAndPreserveDomTree)
DT = &AM.getResult<DominatorTreeAnalysis>(F);
const auto &PDT = AM.getResult<PostDominatorTreeAnalysis>(F);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rcx, %r15
movq %rdx, %r14
movq %rdi, %rbx
leaq 0x4e4aa88(%rip), %rax # 0x59182a8
cmpb $0x1, 0x80(%rax)
jne 0xacd844
leaq 0x4e0d670(%rip), %rsi # 0x58daea0
movq %r15, %rdi
movq %r14, %rdx
callq 0x1a7f6e0
movq %rax, %r12
addq $0x... | /Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp |
void llvm::SmallVectorImpl<llvm::BasicBlock*>::append<llvm::PredIterator<llvm::BasicBlock, llvm::Value::user_iterator_impl<llvm::User>>, void>(llvm::PredIterator<llvm::BasicBlock, llvm::Value::user_iterator_impl<llvm::User>>, llvm::PredIterator<llvm::BasicBlock, llvm::Value::user_iterator_impl<llvm::User>>) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
xorl %r12d, %r12d
cmpq %rdx, %rsi
je 0xaceced
movq %r15, %rax
movq 0x8(%rax), %rax
testq %rax, %rax
je 0xacece5
movq 0x18(%rax), %rcx
movb (%rcx), %cl
cmpb $0x1d, %cl
setae %dl
movzbl %cl, %ecx
addl $-0x1e, %ecx
cmpl ... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::unifyMetadataImpl(llvm::Module&) | bool unifyMetadataImpl(Module &M) {
const char *Vers[] = {kOCLMD::SpirVer, kOCLMD::OCLVer};
const char *Exts[] = {kOCLMD::UsedExt, kOCLMD::UsedOptCoreFeat,
kOCLMD::CompilerOptions, kOCLMD::LLVMIdent};
bool Changed = false;
for (auto &I : Vers)
Changed |= unifyVersionMD(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rdi, %rbp
xorl %r13d, %r13d
leaq 0x4c2c94a(%rip), %r15 # 0x56fbba0
xorl %r14d, %r14d
movq %rdi, 0x8(%rsp)
movq %r13, %rbx
movq (%r14,%r15), %r12
testq %r12, %r12
je 0xacf277
movq %r12, %rdi
callq 0x7512e0
movq %rax, %r13
jmp 0xac... | /Target/AMDGPU/AMDGPUUnifyMetadata.cpp |
llvm::GCNUpwardRPTracker::recede(llvm::MachineInstr const&) | void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
assert(MRI && "call reset first");
LastTrackedMI = &MI;
if (MI.isDebugInstr())
return;
// Kill all defs.
GCNRegPressure DefPressure, ECDefPressure;
bool HasECDefs = false;
for (const MachineOperand &MO : MI.all_defs()) {
if (!MO.getReg()... | movq %rsi, 0x50(%rdi)
movl 0x44(%rsi), %eax
addl $-0xd, %eax
cmpw $0x5, %ax
jb 0xad8606
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x138, %rsp # imm = 0x138
movq %rdi, %r9
pxor %xmm0, %xmm0
movdqa %xmm0, 0x60(%rsp)
xorl %eax, %eax
movq %rax, 0x70(%rsp)
movq %rax, 0x90(%rsp)
movdq... | /Target/AMDGPU/GCNRegPressure.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::DenseMap<unsigned int, llvm::LaneBitmask, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::LaneBitmask>>, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicB... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
leaq 0x10(%rsp), %r14
movq %rax, %rsi
movq %r14, %rdx
callq 0xae3766
movl 0x10(%rbx), %edx
shlq $0x5, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x18, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::GCNSchedStage::checkScheduling() | void GCNSchedStage::checkScheduling() {
// Check the results of scheduling.
PressureAfter = DAG.getRealRegPressure(RegionIdx);
LLVM_DEBUG(dbgs() << "Pressure after scheduling: " << print(PressureAfter));
LLVM_DEBUG(dbgs() << "Region: " << RegionIdx << ".\n");
if (PressureAfter.getSGPRNum() <= S.SGPRCriticalL... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movq 0x8(%rdi), %rsi
movl 0x40(%rdi), %edx
leaq 0x8(%rsp), %r15
movq %r15, %rdi
callq 0xadeea8
leaq 0x78(%rbx), %r14
movq 0x10(%r15), %rax
movq %rax, 0x88(%rbx)
movups (%r15), %xmm0
movups %xmm0, 0x78(%rbx)
movl 0x78(%rbx), %ecx
mov... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::GCNScheduleDAGMILive::updateRegionBoundaries(llvm::SmallVectorImpl<std::pair<llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>>>&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstr*, bool) | void GCNScheduleDAGMILive::updateRegionBoundaries(
SmallVectorImpl<std::pair<MachineBasicBlock::iterator,
MachineBasicBlock::iterator>> &RegionBoundaries,
MachineBasicBlock::iterator MI, MachineInstr *NewMI, bool Removing) {
unsigned I = 0, E = RegionBoundaries.size();
// Searc... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x8(%rsi), %eax
testl %eax, %eax
je 0xae2382
movq 0x18(%rdx), %rdi
movq (%rbx), %r9
xorl %esi, %esi
movq (%r9), %r10
cmpq 0x18(%r10), %rdi
je 0xae2384
incl %esi
addq $0x10, %r9
cmpl %esi, %eax
jne 0xae236b
movl %eax, %esi
jmp 0xae2384
xorl %esi... | /Target/AMDGPU/GCNSchedStrategy.cpp |
llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>* llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>>, unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm:... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xae5895
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>>, unsigned int, llvm::GCNRegPressure, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::GCNRegPressure>>::move... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xae5bd2
movq (%r15), %rcx
leaq (%rax,%rax,8), %rdx
leaq (%rdx,%rdx,2), %rdx
addq %rdx, %rax
addq $-0x1c, %rax
shrq $0x2, %rax
movabsq $0x4924924924924925... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorTemplateBase<std::pair<llvm::MachineOperand*, long>, true>::push_back(std::pair<llvm::MachineOperand*, long>) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0xaec04e
movq (%r14), %rax
movl 0x8(%r14), %ecx
shlq $0x4, %rcx
movq %r15, (%rax,%rcx)
movq %rbx, 0x8(%rax,%rcx)
incl 0x8(%r14)
popq %rbx
popq %r14
popq %r15
retq
incq %rdx
leaq 0x10(%r14), %rs... | /llvm/ADT/SmallVector.h |
llvm::R600InstrInfo::ExtractSrcs(llvm::MachineInstr&, llvm::DenseMap<unsigned int, unsigned int, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned int>> const&, unsigned int&) const | std::vector<std::pair<int, unsigned>>
R600InstrInfo::ExtractSrcs(MachineInstr &MI,
const DenseMap<unsigned, unsigned> &PV,
unsigned &ConstCount) const {
ConstCount = 0;
const std::pair<int, unsigned> DummyPair(-1, 0);
std::vector<std::pair<int, unsigned>> Resu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rcx, 0x50(%rsp)
movq %rsi, %r12
movq %rdi, %rbp
movq %r8, 0x38(%rsp)
movl $0x0, (%r8)
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
movq %rax, 0x28(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0x0, 0x10(%rdi)
leaq 0x58(%rs... | /Target/AMDGPU/R600InstrInfo.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>, llvm::WeakTrackingVH, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value ... | unsigned getNumBuckets() const {
return NumBuckets;
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movl 0x10(%rdi), %eax
testl %eax, %eax
je 0xaf0d90
movq (%rdi), %rcx
leaq 0x8(%rsp), %rdi
movq $0x2, (%rdi)
xorl %r8d, %r8d
movq %r8, 0x8(%rdi)
movq $-0x1000, 0x10(%rdi) # imm = 0xF000
leaq 0x4c0c6b1(%rip), %r9 # 0x56fd3a0
movq %r9, -0x8(%rdi)
movq %r8, 0x18(%rdi)
movl 0x18(... | /llvm/ADT/DenseMap.h |
llvm::ValueHandleBase::operator=(llvm::Value*) | Value *operator=(Value *RHS) {
if (getValPtr() == RHS)
return RHS;
if (isValid(getValPtr()))
RemoveFromUseList();
setValPtr(RHS);
if (isValid(getValPtr()))
AddToUseList();
return RHS;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq 0x10(%rdi), %rax
cmpq %rsi, %rax
je 0xaf1423
movq %rdi, %r14
cmpq $-0x2000, %rax # imm = 0xE000
je 0xaf1400
cmpq $-0x1000, %rax # imm = 0xF000
je 0xaf1400
testq %rax, %rax
je 0xaf1400
movq %r14, %rdi
callq 0x1a927b6
movq %rbx, 0x10(%r14)
cmpq $-0x2... | /llvm/IR/ValueHandle.h |
llvm::DenseMap<unsigned int, std::vector<llvm::MachineInstr*, std::allocator<llvm::MachineInstr*>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<llvm::MachineInstr*, std::allocator<llvm::MachineInstr*>>>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xaf2204
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
llvm::R600TargetMachine::getTargetTransformInfo(llvm::Function const&) const | TargetTransformInfo
R600TargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(R600TTIImpl(this, F));
} | pushq %r14
pushq %rbx
subq $0x78, %rsp
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdi
callq 0xb027dc
movq %rbx, %rdi
movq %r14, %rsi
callq 0xaf5774
movq 0x30(%r14), %rdi
leaq 0x40(%rsp), %rax
cmpq %rax, %rdi
je 0xaf5769
movq 0x40(%rsp), %rsi
incq %rsi
callq 0x7510e0
movq %rbx, %rax
addq $0x78, %rsp
popq %rbx
popq %r14... | /Target/AMDGPU/R600TargetMachine.cpp |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddMachinePass::operator()<llvm::MachineSanitizerBinaryMetadata>(llvm::MachineSanitizerBinaryMetadata&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rsi, %r13
movq %rdi, %r12
testl %edx, %edx
jne 0xb016bb
movq 0x20(%r12), %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0xaffe60
testb %al, %al
je 0xb0170f
leaq 0x8(%r12), %r15
movq %r15, %rdi
movq %r13, %rsi
callq 0xabc008
movq 0x2... | /llvm/Passes/CodeGenPassBuilder.h |
void llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::AddMachinePass::operator()<llvm::TwoAddressInstructionPass>(llvm::TwoAddressInstructionPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rsi, %r13
movq %rdi, %r12
testl %edx, %edx
jne 0xb01ff3
movq 0x20(%r12), %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0xaffe60
testb %al, %al
je 0xb02047
leaq 0x8(%r12), %r15
movq %r15, %rdi
movq %r13, %rsi
callq 0xaba146
movq 0x2... | /llvm/Passes/CodeGenPassBuilder.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseSetPair<llvm::MachineInstr const*>>, llvm::MachineInstr const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::d... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xb09e9e
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movq (%r11), %rbx
cmpq %rbx, (%rsi)
jne 0xb09e65
movq %r1... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::TargetInstrInfo::RegSubRegPair, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::TargetInstrInfo::RegSubRegPair, void>, llvm::detail::DenseSetPair<llvm::TargetInstrInfo::RegSubRegPair>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::TargetInstrInfo::RegSubRegPair, llvm... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xb11278
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xb1123a
xorl %ecx, %ecx
jmp 0xb11253
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>>>, unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llv... | const_iterator find(const_arg_type_t<KeyT> Val) const {
const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeConstIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(... | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rdx
callq 0xb133b6
testb %al, %al
je 0xb1339f
movq 0x8(%rsp), %rax
movl 0x10(%rbx), %ecx
leaq (%rcx,%rcx,2), %rdx
shlq $0x3, %rdx
addq (%rbx), %rdx
jmp 0xb133b0
movl 0x10(%rbx), %eax
leaq (%rax,%rax,2), %rax
shlq $0x3, %rax
addq (%rbx), %rax
movq %rax, %rdx
a... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<unsigned int, llvm::LaneBitmask>>>, unsigned int, std::pair<unsigned int, llvm::LaneBitmask>, llvm::DenseMapInfo<unsigned int, void>, llv... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0xb133b6
movl 0x10(%rbx), %ecx
leaq (%rcx,%rcx,2), %rdx
shlq $0x3, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::SIFrameLowering::emitCSRSpillRestores(llvm::MachineFunction&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc&, llvm::LiveRegUnits&, llvm::Register, llvm::Register) const | void SIFrameLowering::emitCSRSpillRestores(
MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits,
Register FrameReg, Register FramePtrRegScratchCopy) const {
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
const... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x138, %rsp # imm = 0x138
movq %rcx, 0x28(%rsp)
movq %rdx, %r14
movl 0x170(%rsp), %edi
movq 0x10(%rsi), %rax
movq %rsi, 0x30(%rsp)
movq 0x30(%rsi), %rcx
movq %rax, 0x8(%rsp)
leaq 0x370(%rax), %r12
movq %rcx, 0x18(%rsp)
movl 0x490(%rcx), ... | /Target/AMDGPU/SIFrameLowering.cpp |
llvm::PrologEpilogSGPRSpillBuilder::saveToVGPRLane(int) const | void saveToVGPRLane(const int FI) const {
assert(!MFI.isDeadObjectIndex(FI));
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
ArrayRef<SIRegisterInfo::SpilledReg> Spill =
FuncInfo->getSGPRSpillToPhysicalVGPRLanes(FI);
assert(Spill.size() == NumSubRegs);
for (unsigned I = 0; I < Num... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
movq 0x28(%rdi), %rdi
callq 0xb1a52e
movq %rax, 0x38(%rsp)
movl 0x78(%rbx), %eax
testl %eax, %eax
je 0xb1a430
leaq 0x40(%rsp), %r14
xorl %r12d, %r12d
movq %rbx, 0x30(%rsp)
movq 0x38(%rsp), %rbp
cmpl $0x1, %eax
jne 0xb1a2c... | /Target/AMDGPU/SIFrameLowering.cpp |
llvm::SmallVectorImpl<llvm::MachineOperand const*>::assignRemote(llvm::SmallVectorImpl<llvm::MachineOperand const*>&&) | void assignRemote(SmallVectorImpl &&RHS) {
this->destroy_range(this->begin(), this->end());
if (!this->isSmall())
free(this->begin());
this->BeginX = RHS.BeginX;
this->Size = RHS.Size;
this->Capacity = RHS.Capacity;
RHS.resetToSmall();
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq (%rdi), %rdi
leaq 0x10(%r14), %rax
cmpq %rax, %rdi
je 0xb1ba8d
callq 0x751980
movq (%rbx), %rax
movq %rax, (%r14)
movq 0x8(%rbx), %rax
movq %rax, 0x8(%r14)
leaq 0x10(%rbx), %rax
movq %rax, (%rbx)
movq $0x0, 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<llvm::MachineBasicBlock*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, unsigned int>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xb1eb56
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::WaitcntGeneratorPreGFX12::getWaitEventMask() const | const unsigned *getWaitEventMask() const override {
assert(ST);
static const unsigned WaitEventMaskForInstPreGFX12[NUM_INST_CNTS] = {
eventMask({VMEM_ACCESS, VMEM_READ_ACCESS, VMEM_SAMPLER_READ_ACCESS,
VMEM_BVH_READ_ACCESS}),
eventMask({SMEM_ACCESS, LDS_ACCESS, GDS_ACCESS, SQ... | leaq 0x2957459(%rip), %rax # 0x34766e0
retq
| /Target/AMDGPU/SIInsertWaitcnts.cpp |
llvm::SIInstrInfo::getNonSoftWaitcntOpcode(unsigned int) | static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
switch (Opcode) {
case AMDGPU::S_WAITCNT_soft:
return AMDGPU::S_WAITCNT;
case AMDGPU::S_WAITCNT_VSCNT_soft:
return AMDGPU::S_WAITCNT_VSCNT;
case AMDGPU::S_WAIT_LOADCNT_soft:
return AMDGPU::S_WAIT_LOADCNT;
case AMDGPU::S_WAI... | movl %edi, %eax
leal -0x1291(%rax), %ecx
cmpl $0x12, %ecx
ja 0xb1f2f5
movl $0x4a42b, %edx # imm = 0x4A42B
btl %ecx, %edx
jae 0xb1f2f5
movl %ecx, %eax
leaq 0x2957456(%rip), %rcx # 0x3476748
movl (%rcx,%rax,4), %eax
retq
| /Target/AMDGPU/SIInstrInfo.h |
(anonymous namespace)::WaitcntGenerator::WaitcntGenerator(llvm::MachineFunction const&, (anonymous namespace)::InstCounterType) | WaitcntGenerator(const MachineFunction &MF, InstCounterType MaxCounter)
: ST(&MF.getSubtarget<GCNSubtarget>()), TII(ST->getInstrInfo()),
IV(AMDGPU::getIsaVersion(ST->getCPU())), MaxCounter(MaxCounter),
OptNone(MF.getFunction().hasOptNone() ||
MF.getTarget().getOptLevel() == CodeGen... | pushq %rbp
pushq %r14
pushq %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x4bdf51d(%rip), %rax # 0x56ff6b8
movq %rax, (%rdi)
movq 0x10(%rsi), %rax
movq %rax, 0x8(%rdi)
leaq 0x320(%rax), %rcx
movq %rcx, 0x10(%rdi)
movq 0x40(%rax), %rdi
movq 0x48(%rax), %rsi
callq 0x1d1fe83
movq %rax, 0x18(%rbx)
movl %edx,... | /Target/AMDGPU/SIInsertWaitcnts.cpp |
llvm::SIInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void SIInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInf... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movl %r9d, %r15d
movl %r8d, 0x44(%rsp)
movl %ecx, 0x40(%rsp)
movq %rdi, 0x58(%rsp)
movq 0x128(%rsp), %rbx
movq 0x20(%rsi), %r12
movq 0x30(%r12), %rax
movq %rax, 0x50(%rsp)
movq 0x38(%r12), %r13
leaq 0x48(%rsp), %rdi
movq %rsi, 0x60(%rsp)... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::canInsertSelect(llvm::MachineBasicBlock const&, llvm::ArrayRef<llvm::MachineOperand>, llvm::Register, llvm::Register, llvm::Register, int&, int&, int&) const | bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
ArrayRef<MachineOperand> Cond,
Register DstReg, Register TrueReg,
Register FalseReg, int &CondCycles,
int &TrueCycles, i... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq 0x10(%rdx), %rdx
xorl %eax, %eax
addq $0x2, %rdx
cmpq $0x4, %rdx
ja 0xb3153e
movq 0x48(%rsp), %r12
movq 0x40(%rsp), %r15
movq 0x38(%rsp), %r14
movl 0x30(%rsp), %ecx
leaq 0x29454d0(%rip), %rdi # 0x3476940
movslq (%rdi,%rdx,4), %rdx
addq %rdi, %rdx
jmpq *%rdx
... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::legalizeOperands(llvm::MachineInstr&, llvm::MachineDominatorTree*) const | MachineBasicBlock *
SIInstrInfo::legalizeOperands(MachineInstr &MI,
MachineDominatorTree *MDT) const {
MachineFunction &MF = *MI.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineBasicBlock *CreatedBB = nullptr;
// Legalize VOP2
if (isVOP2(MI) || isVOP... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rsi, %rbx
movq 0x10(%rsi), %rax
movq 0x18(%rsi), %rcx
movq 0x20(%rcx), %r14
movq 0x28(%r14), %r9
movq 0x18(%rax), %rax
testl $0x300, %eax # imm = 0x300
je 0xb32a87
movq %r9, %rsi
movq %rbx, %rdx
callq 0xb39552
jmp 0xb32e... | /Target/AMDGPU/SIInstrInfo.cpp |
updateLiveVariables(llvm::LiveVariables*, llvm::MachineInstr&, llvm::MachineInstr&) | static void updateLiveVariables(LiveVariables *LV, MachineInstr &MI,
MachineInstr &NewMI) {
if (LV) {
unsigned NumOps = MI.getNumOperands();
for (unsigned I = 1; I < NumOps; ++I) {
MachineOperand &Op = MI.getOperand(I);
if (Op.isReg() && Op.isKill())
LV->rep... | testq %rdi, %rdi
je 0xb354d2
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rsi, %r14
movzwl 0x28(%rsi), %eax
movzbl 0x2a(%rsi), %r12d
shll $0x10, %r12d
orl %eax, %r12d
cmpl $0x2, %r12d
jb 0xb354c9
movq %rdx, %rbx
movq %rdi, %r15
shll $0x5, %r12d
addq $-0x20, %r12
xorl %r13d, %r13d
movq 0x20(%r14), %rax
m... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::hasVALU32BitEncoding(unsigned int) const | bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
// GFX90A does not have V_MUL_LEGACY_F32_e32.
if (Opcode == AMDGPU::V_MUL_LEGACY_F32_e64 && ST.hasGFX90AInsts())
return false;
int Op32 = AMDGPU::getVOPe32(Opcode);
if (Op32 == -1)
return false;
return pseudoToMCOpcode(Op32) != -1;
} | pushq %rbx
movq %rdi, %rbx
cmpl $0x212f, %esi # imm = 0x212F
jne 0xb35c68
movq 0x1e0(%rbx), %rax
cmpb $0x0, 0x28c(%rax)
jne 0xb35c87
movzwl %si, %edi
callq 0x1d2c648
cmpl $-0x1, %eax
je 0xb35c87
movq %rbx, %rdi
movl %eax, %esi
callq 0xb285fa
cmpl $-0x1, %eax
setne %al
jmp 0xb35c89
xorl %eax, %eax
popq %rbx
re... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::legalizeOperandsVOP2(llvm::MachineRegisterInfo&, llvm::MachineInstr&) const | void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
const MCInstrDesc &InstrDesc = get(Opc);
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
MachineOperand &Src0 = MI.getOperand(Src... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rdx, %r14
movq %rsi, (%rsp)
movq %rdi, %rbx
movzwl 0x44(%rdx), %r13d
movq 0x8(%rdi), %rax
movq %rax, 0x58(%rsp)
movl %r13d, %edi
movl $0x16, %esi
callq 0x1d2adfd
movswl %ax, %r12d
movq 0x20(%r14), %rax
movq %r12, %rcx
shlq $0x5, %r... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::legalizeOperandsVOP3(llvm::MachineRegisterInfo&, llvm::MachineInstr&) const | void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
int VOP3Idx[3] = {
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
AMDGPU::getNa... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rsi, 0x28(%rsp)
movq %rdi, %rbp
movq %rdx, 0x10(%rsp)
movzwl 0x44(%rdx), %r14d
movl %r14d, %edi
movl $0x16, %esi
callq 0x1d2adfd
cwtl
movl %eax, 0x74(%rsp)
movl %r14d, %edi
movl $0x17, %esi
callq 0x1d2adfd
movswl %ax, %ebx
movl %eb... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::legalizeGenericOperand(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::TargetRegisterClass const*, llvm::MachineOperand&, llvm::MachineRegisterInfo&, llvm::DebugLoc const&) const | void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
MachineBasicBlock::iterator I,
const TargetRegisterClass *DstRC,
MachineOperand &Op,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %r9, %r15
movq %r8, %r13
movq %rcx, %rbp
movq %rdx, 0x8(%rsp)
movq %rsi, 0x20(%rsp)
movq %rdi, %r12
movl (%r8), %ebx
movl 0x4(%r8), %edx
shrl $0x8, %ebx
andl $0xfff, %ebx # imm = 0xFFF
leaq 0x50(%rdi), %r14
movq %r14, %rd... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::splitScalarSMulU64(llvm::SIInstrWorklist&, llvm::MachineInstr&, llvm::MachineDominatorTree*) const | void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist,
MachineInstr &Inst,
MachineDominatorTree *MDT) const {
MachineBasicBlock &MBB = *Inst.getParent();
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
Register FullDestR... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x178, %rsp # imm = 0x178
movq %rcx, 0xe8(%rsp)
movq %rdx, %r13
movq %rsi, 0xf0(%rsp)
movq %rdi, %r12
movq 0x18(%rdx), %rax
movq %rax, 0x8(%rsp)
movq 0x20(%rax), %rax
movq 0x28(%rax), %rbx
leaq 0x4bc4295(%rip), %rsi # 0x5702f28
leaq 0x... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::splitScalarSMulPseudo(llvm::SIInstrWorklist&, llvm::MachineInstr&, llvm::MachineDominatorTree*) const | void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist,
MachineInstr &Inst,
MachineDominatorTree *MDT) const {
MachineBasicBlock &MBB = *Inst.getParent();
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
Register ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rcx, 0x80(%rsp)
movq %rdx, %rbx
movq %rsi, 0x88(%rsp)
movq %rdi, %r12
movq 0x18(%rdx), %rax
movq %rax, 0x78(%rsp)
movq 0x20(%rax), %rax
movq 0x28(%rax), %r13
leaq 0x4bc37cb(%rip), %rsi # 0x5702f28
leaq 0x33d3cd4(%rip), %r14 # 0... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::addUsersToMoveToVALUWorklist(llvm::Register, llvm::MachineRegisterInfo&, llvm::SIInstrWorklist&) const | void SIInstrInfo::addUsersToMoveToVALUWorklist(
Register DstReg, MachineRegisterInfo &MRI,
SIInstrWorklist &Worklist) const {
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
E = MRI.use_end(); I != E;) {
MachineInstr &UseMI = *I->getParent();
unsigned OpNo = 0;
switch ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %rbx
movq %rdi, %r14
movq %rdx, %rdi
callq 0x9546c0
testq %rax, %rax
je 0xb435cc
movq %rax, %r15
movl $0xc0201, %ebp # imm = 0xC0201
movq 0x8(%r15), %r12
movzwl 0x44(%r12), %eax
xorl %edx, %edx
cmpl $0x13, %eax
jbe 0xb4357e
leal -0xf6b(%rax), %e... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::isStackAccess(llvm::MachineInstr const&, int&) const | unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
if (!Addr || !Addr->isFI())
return Register();
assert(!MI.memoperands_empty() &&
(*MI.memoperands_begin())... | pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %r14
movq %rsi, %rbx
movzwl 0x44(%rsi), %ebp
movl %ebp, %edi
movl $0x1, %esi
callq 0x1d2adfd
movl %eax, %ecx
cmpw $-0x1, %ax
sete %sil
movq 0x20(%rbx), %rdx
testq %rdx, %rdx
sete %dil
xorl %eax, %eax
orb %sil, %dil
jne 0xb44126
movswq %cx, %rcx
movl %ecx, %ecx
shlq $0x5, %rcx... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::isSGPRStackAccess(llvm::MachineInstr const&, int&) const | unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
assert(Addr && Addr->isFI());
FrameIndex = Addr->getIndex();
return getNamedOperand(MI, AMDGPU::OpName::data)->... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %rbx
movzwl 0x44(%rsi), %ebp
movl %ebp, %edi
movl $0x8, %esi
callq 0x1d2adfd
movswq %ax, %rax
movl %eax, %ecx
shlq $0x5, %rcx
addq 0x20(%rbx), %rcx
xorl %r15d, %r15d
cmpw $-0x1, %ax
cmoveq %r15, %rcx
movl 0x10(%rcx), %eax
movl %eax, (%r14... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SIInstrInfo::splitFlatOffset(long, unsigned int, unsigned long) const | std::pair<int64_t, int64_t>
SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,
uint64_t FlatVariant) const {
int64_t RemainderOffset = COffsetVal;
int64_t ImmField = 0;
bool AllowNegative = allowNegativeFlatOffset(FlatVariant);
const unsigned NumBits = AMDGPU::get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq 0x1e0(%rdi), %rdi
movabsq $0x100000000000000, %r12 # imm = 0x100000000000000
cmpq %r12, %rcx
jne 0xb4542a
cmpb $0x0, 0x295(%rdi)
je 0xb4542a
xorl %ebp, %ebp
jmp 0xb4543d
movb $0x1, %bpl
cmpq $0x1000000, %r15 ... | /Target/AMDGPU/SIInstrInfo.cpp |
llvm::SlotIndexes::replaceMachineInstrInMaps(llvm::MachineInstr&, llvm::MachineInstr&) | SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
Mi2IndexMap::iterator mi2iItr = mi2iMap.find(&MI);
if (mi2iItr == mi2iMap.end())
return SlotIndex();
SlotIndex replaceBaseIndex = mi2iItr->second;
IndexListEntry *miEntry(replaceBaseIndex.listEntry());
ass... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r14
movq %rdi, %r12
leaq 0x78(%rdi), %rbx
movq %rbx, %rdi
callq 0xb46e7c
movl 0x88(%r12), %ecx
shlq $0x4, %rcx
addq 0x78(%r12), %rcx
cmpq %rcx, %rax
je 0xb46e69
movq 0x8(%rax), %r15
movq %r15, %rcx
andq $-0x8, %rcx
movq %r14, 0x10(%rcx)
movq $-0x2... | /llvm/CodeGen/SlotIndexes.h |
llvm::SITargetLowering::lowerGET_ROUNDING(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::lowerGET_ROUNDING(SDValue Op,
SelectionDAG &DAG) const {
SDLoc SL(Op);
assert(Op.getValueType() == MVT::i32);
uint32_t BothRoundHwReg =
AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 0, 4);
SDValue GetRoundBothImm = DAG.g... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movq %rcx, %rbx
movq %rsi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0xb519f0
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r15), %eax
leaq 0x38(%rsp), %r13
movl %ea... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::lowerFP_ROUND(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::f16 &&
"Do not know how to custom lower FP_ROUND for non-f16 type");
SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType();
if (SrcVT != MVT::f64)
return Op;
// TODO: Handle ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x60, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq 0x28(%rsi), %rax
movq (%rax), %r12
movq 0x8(%rax), %rax
movq 0x30(%r12), %rcx
movl %eax, %edx
shlq $0x4, %rdx
cmpb $0xd, (%rcx,%rdx)
jne 0xb66f16
cmpl $0xe2, 0x18(%r14)
jne 0xb66f16
movq %rax, %x... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::adjustLoadValueType(unsigned int, llvm::MemSDNode*, llvm::SelectionDAG&, llvm::ArrayRef<llvm::SDValue>, bool) const | SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
MemSDNode *M,
SelectionDAG &DAG,
ArrayRef<SDValue> Ops,
bool IsIntrinsic)... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, 0x50(%rsp)
movq %r8, 0x48(%rsp)
movq %rcx, %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %r15
movq 0x48(%rdx), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0xb67bcb
leaq 0x30(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::isCFIntrinsic(llvm::SDNode const*) const | unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
switch (Intr->getConstantOperandVal(1)) {
case Intrinsic::amdgcn_if:
return AMDGPUISD::IF;
case Intrinsic::amdgcn_else:
return AMDGPUISD::ELSE;
case Intrinsic::amdgcn_loo... | xorl %eax, %eax
cmpl $0x2f, 0x18(%rsi)
jne 0xb69fa7
movq 0x28(%rsi), %rcx
movq 0x28(%rcx), %rcx
movq 0x58(%rcx), %rcx
cmpl $0x41, 0x20(%rcx)
jb 0xb69f74
movq 0x18(%rcx), %rcx
jmp 0xb69f78
addq $0x18, %rcx
movq (%rcx), %rcx
cmpq $0xb10, %rcx # imm = 0xB10
je 0xb69fa2
cmpq $0x7fb, %rcx # imm = 0x7FB... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::shouldEmitPCReloc(llvm::GlobalValue const*) const | bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x8(%rsi), %rax
movl 0x8(%rax), %eax
shrl $0x8, %eax
orl $0x2, %eax
cmpl $0x6, %eax
jne 0xb6a080
movl $0x1d0, %edi # imm = 0x1D0
addq 0x8(%r14), %rdi
callq 0x1d2e9c8
testb %al, %al
je 0xb6a080
xorl %eax, %eax
jmp 0xb6a08d
movq %r14, %rdi
m... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::lowerTrapEndpgm(llvm::SDValue, llvm::SelectionDAG&) const | SDValue SITargetLowering::lowerTrapEndpgm(
SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op);
SDValue Chain = Op.getOperand(0);
return DAG.getNode(AMDGPUISD::ENDPGM_TRAP, SL, MVT::Other, Chain);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x38, %rsp
movq %rcx, %rbx
movq %rsi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xb6a20b
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14), %eax
leaq 0x10(%rsp), %r15
movl %eax, 0x8(%r15)
movq 0x28(%r14), %rax
movups (%rax)... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::getSegmentAperture(unsigned int, llvm::SDLoc const&, llvm::SelectionDAG&) const | SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const {
if (Subtarget->hasApertureRegs()) {
const unsigned ApertureRegNo = (AS == AMDGPUAS::LOCAL_ADDRESS)
? AMDGPU::SRC_SHARED_BASE
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0xd0, %rsp
movq %rcx, %r14
movq %rdx, %rbx
movl %esi, %ebp
movq 0x4e100(%rdi), %rax
cmpb $0x1, 0x278(%rax)
jne 0xb6a7f8
cmpl $0x3, %ebp
movl $0x1f, %eax
movl $0x18, %esi
cmovel %eax, %esi
xorl %r15d, %r15d
movq %r14, %rdi
movl $0x8, %edx
xorl %ecx, %ecx
callq... | /Target/AMDGPU/SIISelLowering.cpp |
isKnownNonNull(llvm::SDValue, llvm::SelectionDAG&, llvm::AMDGPUTargetMachine const&, unsigned int) | unsigned getOpcode() const { return (unsigned)NodeType; } | movl 0x18(%rdi), %edx
xorl %ecx, %ecx
cmpq $0x27, %rdx
ja 0xb6a98e
movb $0x1, %al
movabsq $0xe00000e040, %r8 # imm = 0xE00000E040
btq %rdx, %r8
jae 0xb6a97b
retq
movabsq $0x800000800, %rax # imm = 0x800000800
btq %rdx, %rax
jae 0xb6a98e
movq %rdi, %rcx
testq %rcx, %rcx
je 0xb6a9b8
pushq %rbx
movq 0x58(%rcx), ... | /llvm/CodeGen/SelectionDAGNodes.h |
llvm::SITargetLowering::lowerWaveID(llvm::SelectionDAG&, llvm::SDValue) const | SDValue SITargetLowering::lowerWaveID(SelectionDAG &DAG, SDValue Op) const {
// With architected SGPRs, waveIDinGroup is in TTMP8[29:25].
if (!Subtarget->hasArchitectedSGPRs())
return {};
SDLoc SL(Op);
MVT VT = MVT::i32;
SDValue TTMP8 = DAG.getCopyFromReg(DAG.getEntryNode(), SL, AMDGPU::TTMP8, VT);
retu... | pushq %r15
pushq %r14
pushq %rbx
subq $0x80, %rsp
movq 0x4e100(%rdi), %rax
cmpb $0x1, 0x2ed(%rax)
jne 0xb6e693
movq %rdx, %r14
movq %rsi, %rbx
movq 0x48(%rdx), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0xb6e5ab
leaq 0x30(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14), %eax
leaq 0x30(%rsp), %r14
movl %... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::AdjustInstrPostInstrSelection(llvm::MachineInstr&, llvm::SDNode*) const | const GCNSubtarget *SITargetLowering::getSubtarget() const {
return Subtarget;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq 0x4e100(%rdi), %rbx
movzwl 0x44(%rsi), %eax
movq 0x328(%rbx), %rcx
addq $0x320, %rbx # imm = 0x320
shll $0x5, %eax
subq %rax, %rcx
testb $0x4, 0x19(%rcx)
jne 0xb7dac4
movq 0x10(%rsi), %rax
testb $0x70, 0x1a(%rax)
je 0xb7d... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::checkAsmConstraintVal(llvm::SDValue, llvm::StringRef, unsigned long) const | bool SITargetLowering::checkAsmConstraintVal(SDValue Op, StringRef Constraint,
uint64_t Val) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'I':
return AMDGPU::isInlinableIntLiteral(Val);
case 'J':
return isInt<16>(Val);
cas... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %r9, %rbx
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r14
movq %rsi, 0x8(%rsp)
movl %edx, 0x10(%rsp)
cmpq $0x1, %r8
jne 0xb7ea9f
movzbl (%rcx), %eax
addl $-0x41, %eax
leaq 0x2905e39(%rip), %rcx # 0x34848bc
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmp... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::checkAsmConstraintValA(llvm::SDValue, unsigned long, unsigned int) const | bool SITargetLowering::checkAsmConstraintValA(SDValue Op, uint64_t Val,
unsigned MaxSize) const {
unsigned Size = std::min<unsigned>(Op.getScalarValueSizeInBits(), MaxSize);
bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
if (Size == 16) {
MVT VT = Op.getSimpleV... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %r8d, %ebp
movq %rcx, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movq %rsi, (%rdi)
movl %edx, 0x8(%rdi)
callq 0x9b37dc
cmpl %ebp, %eax
cmovbl %eax, %ebp
movq 0x4e100(%r14), %rax
movb 0x16c(%rax), %r14b
cmpl $0x40, %ebp
je 0xb7ebff
cmpl $0x20, %ebp
je 0xb7ebe7
cmpl $0x10,... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::finalizeLowering(llvm::MachineFunction&) const | void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
MachineRegisterInfo &MRI = MF.getRegInfo();
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
const SIInstrI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rsi, %rbx
movq 0x10(%rsi), %r12
movq 0x28(%rsi), %r15
movq 0x30(%rsi), %rbp
movl $0x370, %eax # imm = 0x370
addq 0x4e100(%rdi), %rax
movq %rax, (%rsp)
cmpb $0x1, 0x6e(%rbp)
movq %rsi, 0x10(%rsp)
movq %rdi, 0x28(%rsp)
mov... | /Target/AMDGPU/SIISelLowering.cpp |
llvm::SITargetLowering::getTargetMMOFlags(llvm::Instruction const&) const | MachineMemOperand::Flags
SITargetLowering::getTargetMMOFlags(const Instruction &I) const {
// Propagate metadata set by AMDGPUAnnotateUniformValues to the MMO of a load.
MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
if (I.getMetadata("amdgpu.noclobber"))
Flags |= MONoClobber;
if (I.getMetadata... | pushq %rbp
pushq %rbx
pushq %rax
movq %rsi, %rbx
cmpq $0x0, 0x30(%rsi)
jne 0xb80bd5
movl $0x20000000, %eax # imm = 0x20000000
andl 0x4(%rbx), %eax
jne 0xb80bd5
xorl %ebp, %ebp
jmp 0xb80bf5
leaq 0x2904246(%rip), %rsi # 0x3484e22
movl $0x10, %edx
movq %rbx, %rdi
callq 0x1a6c1f4
xorl %ebp, %ebp
testq %rax, %rax
se... | /Target/AMDGPU/SIISelLowering.cpp |
DotSrc const* llvm::SmallVectorTemplateCommon<DotSrc, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<DotSrc, true>>(llvm::SmallVectorTemplateBase<DotSrc, true>*, DotSrc const&, unsigned long) | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x8(%rdi), %ecx
movl 0xc(%rdi), %eax
addq %rcx, %rdx
cmpq %rax, %rdx
ja 0xb84fae
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rdi, %r14
movq (%rdi), %rax
shlq $0x5, %rcx
addq %rax, %rcx
cmpq %rbx, %rax
setb... | /llvm/ADT/SmallVector.h |
bool llvm::DenseMapBase<llvm::SmallDenseMap<int, llvm::KernArgPreloadDescriptor, 4u, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::KernArgPreloadDescriptor>>, int, llvm::KernArgPreloadDescriptor, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::KernArgPreloadDescriptor>>::Look... | const BucketT *getBuckets() const {
return Small ? getInlineBuckets() : getLargeRep()->Buckets;
} | leaq 0x8(%rdi), %rcx
testb $0x1, (%rdi)
cmoveq 0x8(%rdi), %rcx
movl $0x4, %r8d
cmovel 0x10(%rdi), %r8d
testl %r8d, %r8d
je 0xb85270
pushq %rbx
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %edi
decl %r8d
andl %r8d, %edi
movl $0x1, %r10d
xorl %r9d, %r9d
movl %edi, %r11d
imulq $0x58, %r11, %rbx
leaq (%rc... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<int, llvm::KernArgPreloadDescriptor, 4u, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::KernArgPreloadDescriptor>>, int, llvm::KernArgPreloadDescriptor, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::KernArgPreloadDescriptor>>::moveFromO... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rdi), %rcx
andl $0x1, (%rdi)
movl $0x0, 0x4(%rdi)
cmoveq 0x8(%rdi), %rcx
movl $0x4, %eax
cmovel 0x10(%rdi), %eax
testl %eax, %eax
je 0xb855bf
movl %eax, %eax
imulq $0x58, %rax, %rax
add... | /llvm/ADT/DenseMap.h |
std::pair<unsigned int, llvm::SDValue>& llvm::SmallVectorTemplateBase<std::pair<unsigned int, llvm::SDValue>, true>::growAndEmplaceBack<llvm::MCRegister, llvm::SDValue&>(llvm::MCRegister&&, llvm::SDValue&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl (%rsi), %eax
leaq 0x8(%rsp), %rsi
movl %eax, (%rsi)
movups (%rdx), %xmm0
movups %xmm0, 0x8(%rsi)
movl $0x1, %edx
callq 0xa2ddca
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups ... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, (anonymous namespace)::SILoadStoreOptimizer::MemAddress>>, llvm::MachineInstr*, (anonymous namespace)::SILoadStor... | ValueT &operator[](KeyT &&Key) {
return FindAndConstruct(std::move(Key)).second;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xb89116
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xb88ff8
movq %rax, (%rsp)
movl 0x8(%r14), %eax
movl 0x10(%r14), %esi
leal 0x4(,%rax,4), %ecx
leal (%rsi,%rsi,2), %edx
cmpl %edx, %ec... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorTemplateBase<std::pair<llvm::MachineInstr*, long>, true>::push_back(std::pair<llvm::MachineInstr*, long>) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0xb89468
movq (%r14), %rax
movl 0x8(%r14), %ecx
shlq $0x4, %rcx
movq %r15, (%rax,%rcx)
movq %rbx, 0x8(%rax,%rcx)
incl 0x8(%r14)
popq %rbx
popq %r14
popq %r15
retq
incq %rdx
leaq 0x10(%r14), %rs... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::SILoadStoreOptimizer::getDataRegClass(llvm::MachineInstr const&) const | const TargetRegisterClass *
SILoadStoreOptimizer::getDataRegClass(const MachineInstr &MI) const {
if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {
return TRI->getRegClassForReg(*MRI, Dst->getReg());
}
if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) {
return TR... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq 0x40(%rdi), %rdi
movl $0xb, %edx
callq 0xb2f76a
movq %rax, %r12
testq %rax, %rax
je 0xb8962d
movq 0x48(%rbx), %rdi
movq 0x50(%rbx), %rsi
movl 0x4(%r12), %edx
callq 0xbbb0de
movq %rax, %r15
jmp 0xb8962d
testq %r12, %r12
jne 0xb89... | /Target/AMDGPU/SILoadStoreOptimizer.cpp |
llvm::Incoming& llvm::SmallVectorTemplateBase<llvm::Incoming, true>::growAndEmplaceBack<llvm::Register&, llvm::MachineBasicBlock*&, llvm::Register>(llvm::Register&, llvm::MachineBasicBlock*&, llvm::Register&&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl (%rsi), %eax
movq (%rdx), %rdx
movl (%rcx), %ecx
leaq 0x8(%rsp), %rsi
movl %eax, (%rsi)
movq %rdx, 0x8(%rsi)
movl %ecx, 0x10(%rsi)
movl $0x1, %edx
callq 0xb92b6a
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%r... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, unsigned int>>, llvm::MachineBasicBlock*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::... | value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, Key);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xb2048a
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xb9301f
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xb2051c
movq (%rbx), %rcx
movq %rcx, (%rax)
movl $0x0... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, bool, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, bool>>, llvm::MachineBasicBlock*, bool, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, bool... | const_iterator find(const_arg_type_t<KeyT> Val) const {
const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeConstIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(... | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
movq %rsp, %rdx
movq %rax, %rsi
callq 0xb935a2
testb %al, %al
je 0xb93749
movq (%rsp), %rax
movl 0x10(%rbx), %edx
shlq $0x4, %rdx
addq (%rbx), %rdx
jmp 0xb93756
movl 0x10(%rbx), %eax
shlq $0x4, %rax
addq (%rbx), %rax
movq %rax, %rdx
addq... | /llvm/ADT/DenseMap.h |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::SILowerWWMCopies, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rbx
subq $0x10, %rsp
movl $0x68, %edi
callq 0x751940
movq %rax, %rbx
xorl %eax, %eax
movq %rax, 0x8(%rbx)
leaq 0x4d0e27a(%rip), %rcx # 0x58a2324
movq %rcx, 0x10(%rbx)
movl $0x2, 0x18(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rbx)
movq %rax, 0x30(%rbx)
leaq 0x4b6cb99(%rip), %rax # 0x5700c60
movq %rax, (%rb... | /llvm/PassSupport.h |
llvm::LiveRange::LiveRange(bool) | LiveRange(bool UseSegmentSet = false)
: segmentSet(UseSegmentSet ? std::make_unique<SegmentSet>()
: nullptr) {} | pushq %rbx
movq %rdi, %rbx
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, 0x8(%rdi)
leaq 0x50(%rdi), %rcx
movq %rcx, 0x40(%rdi)
movq %rax, 0x48(%rdi)
addq $0x60, %rbx
testl %esi, %esi
je 0xb94494
movl $0x30, %edi
callq 0x751940
leaq 0x8(%rax), %rcx
xorps %xmm0, %x... | /llvm/CodeGen/LiveInterval.h |
llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer(llvm::SIRegisterInfo const&) | Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
const SIRegisterInfo &TRI) {
ArgInfo.PrivateSegmentBuffer =
ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
NumUserSGPRs += 4;
return ArgInfo.PrivateSegmentBuffer.getRegister();
... | pushq %rbx
movq %rdi, %rbx
movl $0x143, %eax # imm = 0x143
addl 0x348(%rdi), %eax
movzwl %ax, %eax
leaq 0x8(%rsi), %rdi
leaq 0x4b6e501(%rip), %rcx # 0x57045b8
movq (%rcx), %rcx
movl %eax, %esi
movl $0x3, %edx
callq 0x1b0147e
movabsq $-0x100000000, %rcx # imm = 0xFFFFFFFF00000000
orq %rax, %rcx
movq %rc... | /Target/AMDGPU/SIMachineFunctionInfo.cpp |
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