name string | code string | asm string | file string |
|---|---|---|---|
llvm::SIMachineFunctionInfo::allocateWWMSpill(llvm::MachineFunction&, llvm::Register, unsigned long, llvm::Align) | void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR,
uint64_t Size, Align Alignment) {
// Skip if it is an entry function or the register is already added.
if (isEntryFunction() || WWMSpills.count(VGPR))
return;
// Skip if this is a fun... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movl %edx, 0x4(%rsp)
cmpb $0x0, 0x6e(%rdi)
jne 0xb964dd
movl %r8d, %ebp
movq %rcx, %r14
movq %rsi, %r15
movq %rdi, %r12
leaq 0x418(%rdi), %rbx
leaq 0x4(%rsp), %rsi
movq %rbx, %rdi
callq 0xa5dedc
movl 0x428(%r12), %ecx
shlq $0x3, %rcx
addq 0x418(%r1... | /Target/AMDGPU/SIMachineFunctionInfo.cpp |
llvm::MapVector<llvm::Register, int, llvm::DenseMap<llvm::Register, unsigned int, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, unsigned int>>, llvm::SmallVector<std::pair<llvm::Register, int>, 0u>>::operator[](llvm::Register const&) | ValueT &operator[](const KeyT &Key) {
std::pair<KeyT, typename MapType::mapped_type> Pair = std::make_pair(Key, 0);
std::pair<typename MapType::iterator, bool> Result = Map.insert(Pair);
auto &I = Result.first->second;
if (Result.second) {
Vector.push_back(std::make_pair(Key, ValueT()));
I =... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movl (%rsi), %eax
leaq 0xc(%rsp), %rcx
movl %eax, -0x4(%rcx)
movl $0x0, (%rcx)
leaq 0x10(%rsp), %r15
leaq 0x8(%rsp), %rdx
movq %r15, %rdi
movq %rbx, %rsi
callq 0xb9ca38
movq (%r15), %r12
cmpb $0x1, 0x10(%r15)
jne 0xb967e8
leaq ... | /llvm/ADT/MapVector.h |
void llvm::yaml::IO::processKeyWithDefault<llvm::yaml::SIArgumentInfo, llvm::yaml::EmptyContext>(char const*, std::optional<llvm::yaml::SIArgumentInfo>&, std::optional<llvm::yaml::SIArgumentInfo> const&, bool, llvm::yaml::EmptyContext&) | void IO::processKeyWithDefault(const char *Key, std::optional<T> &Val,
const std::optional<T> &DefaultValue,
bool Required, Context &Ctx) {
assert(!DefaultValue && "std::optional<T> shouldn't have a value!");
void *SaveInfo;
bool UseDefault = true;
c... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x528, %rsp # imm = 0x528
movl %r8d, %ebp
movq %rcx, 0x8(%rsp)
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %rbx
movb $0x1, 0x7(%rsp)
movq (%rdi), %rax
callq *0x10(%rax)
movl %eax, %r13d
movb 0x510(%r14), %r15b
movq (%rbx), %rax
movq %rbx,... | /llvm/Support/YAMLTraits.h |
llvm::yaml::MappingTraits<llvm::yaml::SIArgumentInfo>::mapping(llvm::yaml::IO&, llvm::yaml::SIArgumentInfo&) | static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
YamlIO.mapOptional("queuePtr", AI.QueuePtr);
YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
YamlIO.mapOptional... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x28eb258(%rip), %rsi # 0x3485af9
leaq 0x7(%rsp), %rcx
movq %rbx, %rdx
callq 0xb9aa82
leaq 0x48(%rbx), %rdx
leaq 0x28eb255(%rip), %rsi # 0x3485b0e
leaq 0x7(%rsp), %rcx
movq %r14, %rdi
callq 0xb9aa82
leaq 0x90(%rbx), %rdx
leaq 0x28eb246(%rip), %rs... | /Target/AMDGPU/SIMachineFunctionInfo.h |
std::enable_if<has_SequenceTraits<llvm::SmallVector<llvm::yaml::StringValue, 1u>>::value, void>::type llvm::yaml::yamlize<llvm::SmallVector<llvm::yaml::StringValue, 1u>, llvm::yaml::EmptyContext>(llvm::yaml::IO&, llvm::SmallVector<llvm::yaml::StringValue, 1u>&, bool, llvm::yaml::EmptyContext&) | std::enable_if_t<has_SequenceTraits<T>::value, void>
yamlize(IO &io, T &Seq, bool, Context &Ctx) {
if ( has_FlowTraits< SequenceTraits<T>>::value ) {
unsigned incnt = io.beginFlowSequence();
unsigned count = io.outputting() ? SequenceTraits<T>::size(io, Seq) : incnt;
for(unsigned i=0; i < count; ++i) {
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %rax
callq *0x18(%rax)
movl %eax, %ebp
movq (%rbx), %rax
movq %rbx, %rdi
callq *0x10(%rax)
testb %al, %al
je 0xb9b5d6
movl 0x8(%r15), %ebp
testl %ebp, %ebp
je 0xb9b63b
movl %ebp, %eb... | /llvm/Support/YAMLTraits.h |
void llvm::yaml::IO::processKeyWithDefault<llvm::yaml::FrameIndex, llvm::yaml::EmptyContext>(char const*, std::optional<llvm::yaml::FrameIndex>&, std::optional<llvm::yaml::FrameIndex> const&, bool, llvm::yaml::EmptyContext&) | void IO::processKeyWithDefault(const char *Key, std::optional<T> &Val,
const std::optional<T> &DefaultValue,
bool Required, Context &Ctx) {
assert(!DefaultValue && "std::optional<T> shouldn't have a value!");
void *SaveInfo;
bool UseDefault = true;
c... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %r9, 0x18(%rsp)
movl %r8d, %ebp
movq %rcx, 0x10(%rsp)
movq %rdx, %r14
movq %rsi, %r13
movq %rdi, %rbx
movb $0x1, 0xf(%rsp)
movq (%rdi), %rax
callq *0x10(%rax)
movl %eax, %r12d
movb 0x18(%r14), %r15b
movq (%rbx), %rax
movq %rbx, %rdi... | /llvm/Support/YAMLTraits.h |
void llvm::SIScheduleDAGMI::fillVgprSgprCost<std::_Rb_tree_const_iterator<unsigned int>>(std::_Rb_tree_const_iterator<unsigned int>, std::_Rb_tree_const_iterator<unsigned int>, unsigned int&, unsigned int&) | void
SIScheduleDAGMI::fillVgprSgprCost(_Iterator First, _Iterator End,
unsigned &VgprUsage, unsigned &SgprUsage) {
VgprUsage = 0;
SgprUsage = 0;
for (_Iterator RegI = First; RegI != End; ++RegI) {
Register Reg = *RegI;
// For now only track virtual registers
if (!Reg.... | xorl %eax, %eax
movl %eax, (%rcx)
movl %eax, (%r8)
cmpq %rdx, %rsi
je 0xba1f8e
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r13
movq %rdi, %r12
leaq 0x8(%rsp), %rbp
movl 0x20(%r13), %esi
testl %esi, %esi
jns 0xba1f70
movq 0... | /Target/AMDGPU/SIMachineScheduler.cpp |
(anonymous namespace)::SIGfx6CacheControl::enableRMWCacheBypass(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false> const&, (anonymous namespace)::SIAtomicScope, (anonymous namespace)::SIAtomicAddrSpace) const | bool SIGfx6CacheControl::enableRMWCacheBypass(
const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const {
assert(MI->mayLoad() && MI->mayStore());
bool Changed = false;
/// Do not set GLC for RMW atomic operations as L0/L1 cache is automatically
/// bypassed, a... | xorl %eax, %eax
retq
nop
| /Target/AMDGPU/SIMemoryLegalizer.cpp |
llvm::DenseMap<llvm::MachineInstr*, llvm::MachineInstr*, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::MachineInstr*>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x8(%rdi), %eax
movl 0x10(%rdi), %esi
testl %eax, %eax
je 0xbae204
decl %eax
je 0xbae208
bsrl %eax, %eax
xorl $0x1f, %eax
jmp 0xbae20d
xorl %ebp, %ebp
jmp 0xbae223
movl $0x20, %eax
movb $0x21, %cl
subb %al, %cl
movl $0x1, %eax
shll %cl, %eax
cmpl $0x41, %eax
movl $0... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>>, llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapI... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xbb1dcd
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
findSingleRegDef(llvm::MachineOperand const*, llvm::MachineRegisterInfo const*) | bool isReg() const { return OpKind == MO_Register; } | cmpb $0x0, (%rdi)
je 0xbb453e
xorl %eax, %eax
retq
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x4(%rdi), %eax
movq %rsi, %rdi
movl %eax, %esi
callq 0x17dae82
testq %rax, %rax
je 0xbb4593
movq 0x20(%rax), %r14
movq %rax, %rdi
callq 0x1793cc8
testl %eax, %eax
je 0xbb4593
movl %eax, %ecx
shlq $0x5, %rcx
cmpb $0... | /llvm/CodeGen/MachineOperand.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, unsigned int>>, llvm::MachineInstr*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, unsigned i... | const_iterator find(const_arg_type_t<KeyT> Val) const {
const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeConstIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(... | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
movq %rsp, %rdx
movq %rax, %rsi
callq 0xae6332
testb %al, %al
je 0xbb50dd
movq (%rsp), %rax
movl 0x10(%rbx), %edx
shlq $0x4, %rdx
addq (%rbx), %rdx
jmp 0xbb50ea
movl 0x10(%rbx), %eax
shlq $0x4, %rax
addq (%rbx), %rax
movq %rax, %rdx
addq... | /llvm/ADT/DenseMap.h |
llvm::cl::opt<unsigned int, true, llvm::cl::parser<unsigned int>>::handleOccurrence(unsigned int, llvm::StringRef, llvm::StringRef) | bool handleOccurrence(unsigned pos, StringRef ArgName,
StringRef Arg) override {
typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val))
return true; // Parse error!
this->setValue(Val);
this... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %esi, %ebp
movq %rdi, %rbx
leaq 0xc(%rsp), %rax
movl $0x0, (%rax)
addq $0x98, %rdi
movq %rax, (%rsp)
movq %rbx, %rsi
callq 0x1c8fda8
movl %eax, %r14d
testb %al, %al
jne 0xbb6639
movl 0xc(%rsp), %eax
movq 0x80(%rbx), %rcx
movl %eax, (%rcx)
movw %bp, 0xc(%rbx)
cmpq $... | /llvm/Support/CommandLine.h |
llvm::SGPRSpillBuilder::SGPRSpillBuilder(llvm::SIRegisterInfo const&, llvm::SIInstrInfo const&, bool, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::RegScavenger*) | SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII,
bool IsWave32, MachineBasicBlock::iterator MI, Register Reg,
bool IsKill, int Index, RegScavenger *RS)
: SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),
Index(Index), RS(RS), MBB(MI->get... | pushq %r14
pushq %rbx
pushq %rax
movl %ecx, %r14d
movq %rdi, %rbx
movq 0x30(%rsp), %rax
movl 0x28(%rsp), %ecx
movb 0x20(%rsp), %dil
movl %r9d, (%rbx)
movq %r8, 0x8(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x10(%rbx)
movb %dil, 0x24(%rbx)
leaq 0x38(%r8), %rdi
movq %rdi, 0x28(%rbx)
xorl %edi, %edi
movl %edi, 0x3c(%rbx)
mov... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SIRegisterInfo::getVGPRClassForBitWidth(unsigned int) const | const TargetRegisterClass *
SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const {
if (BitWidth == 1)
return &AMDGPU::VReg_1RegClass;
if (BitWidth == 16)
return &AMDGPU::VGPR_16RegClass;
if (BitWidth == 32)
return &AMDGPU::VGPR_32RegClass;
return ST.needsAlignedVGPRs() ? getAlignedVGPRCl... | cmpl $0x1, %esi
je 0xbc0205
cmpl $0x20, %esi
je 0xbc01fd
cmpl $0x10, %esi
jne 0xbc020d
leaq 0x4b41ca4(%rip), %rax # 0x5701ea0
retq
leaq 0x4b42314(%rip), %rax # 0x5702518
retq
leaq 0x4b41c0c(%rip), %rax # 0x5701e18
retq
movq 0x138(%rdi), %rax
cmpb $0x1, 0x28c(%rax)
jne 0xbc0224
movl %esi, %edi
jmp 0xbc0240
addl $-... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SIRegisterInfo::getAGPRClassForBitWidth(unsigned int) const | const TargetRegisterClass *
SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) const {
if (BitWidth == 16)
return &AMDGPU::AGPR_LO16RegClass;
if (BitWidth == 32)
return &AMDGPU::AGPR_32RegClass;
return ST.needsAlignedVGPRs() ? getAlignedAGPRClassForBitWidth(BitWidth)
... | cmpl $0x10, %esi
je 0xbc026e
cmpl $0x20, %esi
jne 0xbc0276
leaq 0x4b42243(%rip), %rax # 0x57024b0
retq
leaq 0x4b41cb3(%rip), %rax # 0x5701f28
retq
movq 0x138(%rdi), %rax
cmpb $0x1, 0x28c(%rax)
jne 0xbc028d
movl %esi, %edi
jmp 0xbc02a9
addl $-0x40, %esi
roll $0x1b, %esi
cmpl $0x1e, %esi
ja 0xbc02a6
movl %esi, %eax
l... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SIRegisterInfo::getEquivalentSGPRClass(llvm::TargetRegisterClass const*) const | const TargetRegisterClass *
SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const {
unsigned Size = getRegSizeInBits(*VRC);
if (Size == 32)
return &AMDGPU::SGPR_32RegClass;
const TargetRegisterClass *SRC = getSGPRClassForBitWidth(Size);
assert(SRC && "Invalid register class size");
... | subq $0x18, %rsp
movq 0x110(%rdi), %rax
subq 0x108(%rdi), %rax
movq 0x120(%rdi), %rcx
shrq $0x3, %rax
imull 0x130(%rdi), %eax
movq (%rsi), %rdx
movzwl 0x18(%rdx), %edx
addl %eax, %edx
shlq $0x4, %rdx
movl (%rcx,%rdx), %eax
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
movb $0x0, 0x8(%rdi)
callq 0x1cceb6c
cmpl $0x20, %eax
jne ... | /Target/AMDGPU/SIRegisterInfo.cpp |
llvm::SIRegisterInfo::isVGPR(llvm::MachineRegisterInfo const&, llvm::Register) const | static constexpr bool isVirtualRegister(unsigned Reg) {
return Reg & MCRegister::VirtualRegFlag;
} | testl %edx, %edx
js 0xbc080a
movl %edx, %eax
leaq 0x2aa076f(%rip), %rcx # 0x3660f60
movzwl (%rcx,%rax,2), %eax
cmpq $0xffff, %rax # imm = 0xFFFF
je 0xbc0822
leaq 0x4b55aec(%rip), %rcx # 0x57162f0
movq (%rcx,%rax,8), %rax
jmp 0xbc0824
andl $0x7fffffff, %edx # imm = 0x7FFFFFFF
movq 0x38(%rsi), %rax
sh... | /llvm/CodeGen/Register.h |
(anonymous namespace)::SIWholeQuadMode::markInstruction(llvm::MachineInstr&, char, std::vector<(anonymous namespace)::WorkItem, std::allocator<(anonymous namespace)::WorkItem>>&) | void SIWholeQuadMode::markInstruction(MachineInstr &MI, char Flag,
std::vector<WorkItem> &Worklist) {
InstrInfo &II = Instructions[&MI];
assert(!(Flag & StateExact) && Flag != 0);
// Remove any disabled states from the flag. The user that required it gets
// an undefined ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r13
addq $0x98, %rdi
leaq 0x10(%rsp), %rsi
movq %r13, (%rsi)
callq 0xbc72f6
movb (%rax), %cl
movb 0x1(%rax), %dl
notb %dl
andb %bpl, %dl
movl %ecx, %esi
notb %sil
testb %sil, %dl
je 0xbc76d9
or... | /Target/AMDGPU/SIWholeQuadMode.cpp |
llvm::AMDGPUAAResult::getModRefInfoMask(llvm::MemoryLocation const&, llvm::AAQueryInfo&, bool) | ModRefInfo AMDGPUAAResult::getModRefInfoMask(const MemoryLocation &Loc,
AAQueryInfo &AAQI,
bool IgnoreLocals) {
unsigned AS = Loc.Ptr->getType()->getPointerAddressSpace();
if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AM... | movq (%rsi), %rdi
movq 0x8(%rdi), %rax
movl $0xfe, %ecx
andl 0x8(%rax), %ecx
cmpl $0x12, %ecx
jne 0xbca5ff
movq 0x10(%rax), %rax
movq (%rax), %rax
movl $0xfffffd00, %ecx # imm = 0xFFFFFD00
andl 0x8(%rax), %ecx
cmpl $0x400, %ecx # imm = 0x400
jne 0xbca612
xorl %eax, %eax
retq
pushq %rax
movl $0x6, %esi
... | /Target/AMDGPU/AMDGPUAliasAnalysis.cpp |
(anonymous namespace)::AMDGPUAnnotateUniformValues::runOnFunction(llvm::Function&) | bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
if (skipFunction(F))
return false;
UA = &getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
MSSA = &getAnalysis<MemorySSAWrapperPass>().getMSSA();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
isEntryFunc = AMDGPU::isEn... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq %rsi, %r14
callq 0x1a7c502
testb %al, %al
je 0xbcb8bc
xorl %eax, %eax
jmp 0xbcbafe
movq 0x8(%rbx), %rax
movq (%rax), %rdx
movq 0x8(%rax), %rax
xorl %edi, %edi
leaq 0x4d66ee0(%rip), %rcx # 0x59327b0
leaq 0x10(%rdx),... | /Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp |
llvm::PreservedAnalyses::areAllPreserved() const | size_type size() const { return NumNonEmpty - NumTombstones; } | movl 0x44(%rdi), %eax
cmpl 0x48(%rdi), %eax
jne 0xbcfbe0
pushq %rbx
movq %rdi, %rbx
leaq 0x4d0baf1(%rip), %rsi # 0x58db6b0
callq 0x8dcdd6
movq 0x8(%rbx), %rcx
xorl %edx, %edx
cmpq (%rbx), %rcx
sete %dl
movl 0x10(%rbx,%rdx,4), %edx
leaq (%rcx,%rdx,8), %rcx
cmpq %rcx, %rax
setne %al
popq %rbx
retq
xorl %eax, %eax
retq
... | /llvm/ADT/SmallPtrSet.h |
llvm::LoopAnalysis::Result* llvm::AnalysisGetter::getAnalysis<llvm::LoopAnalysis>(llvm::Function const&, bool) | typename Analysis::Result *getAnalysis(const Function &F,
bool RequestCachedOnly = false) {
if (!LegacyPass && !FAM)
return nullptr;
if (FAM) {
if (CachedOnly || RequestCachedOnly)
return FAM->getCachedResult<Analysis>(const_cast<Function &>(F));
... | movq %rdi, %rcx
movq (%rdi), %rdi
testq %rdi, %rdi
je 0xbd077c
movq %rsi, %rax
orb 0x10(%rcx), %dl
cmpb $0x1, %dl
jne 0xbd077f
movq %rax, %rsi
jmp 0xbd0798
xorl %eax, %eax
retq
pushq %rax
leaq 0x4d4f1d1(%rip), %rsi # 0x591f958
movq %rax, %rdx
callq 0x1a7f6e0
addq $0x8, %rax
addq $0x8, %rsp
retq
| /llvm/Transforms/IPO/Attributor.h |
llvm::DenseMap<char const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<char const*, void>, llvm::detail::DenseSetPair<char const*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xbd0b5a
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseSetPair<char const*>* llvm::DenseMapBase<llvm::DenseMap<char const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<char const*, void>, llvm::detail::DenseSetPair<char const*>>, char const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<char const*, void>, llvm::detail::DenseSetPair<char const*>>:... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xbd0d8d
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
bool llvm::Attributor::shouldInitialize<llvm::AACallEdges>(llvm::IRPosition const&, bool&) | bool shouldInitialize(const IRPosition &IRP, bool &ShouldUpdateAA) {
if (!AAType::isValidIRPositionForInit(*this, IRP))
return false;
if (Configuration.Allowed && !Configuration.Allowed->count(&AAType::ID))
return false;
// For now we skip anything in naked and optnone functions.
const Fun... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq 0x1090(%rdi), %rdi
testq %rdi, %rdi
je 0xbd27f5
leaq 0x442feb1(%rip), %rax # 0x5002690
leaq 0x10(%rsp), %rsi
movq %rax, (%rsi)
leaq 0x8(%rsp), %rdx
callq 0xbd0cb2
testb %al, %al
je 0xbd2839
movq %r14, %rd... | /llvm/Transforms/IPO/Attributor.h |
llvm::detail::DenseSetPair<llvm::PointerIntPair<llvm::AADepGraphNode*, 1u, unsigned int, llvm::PointerLikeTypeTraits<llvm::AADepGraphNode*>, llvm::PointerIntPairInfo<llvm::AADepGraphNode*, 1u, llvm::PointerLikeTypeTraits<llvm::AADepGraphNode*>>>>* llvm::DenseMapBase<llvm::DenseMap<llvm::PointerIntPair<llvm::AADepGraphN... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xbd2f20
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
bool llvm::function_ref<bool (llvm::Instruction&)>::callback_fn<(anonymous namespace)::AAAMDAttributesFunction::checkForQueuePtr(llvm::Attributor&)::'lambda'(llvm::Instruction&)>(long, llvm::Instruction&) | Value *get() const { return Val; } | movq -0x20(%rsi), %rax
movq 0x8(%rax), %rax
movl $0xfe, %ecx
andl 0x8(%rax), %ecx
cmpl $0x12, %ecx
jne 0xbd335e
movq 0x10(%rax), %rax
movq (%rax), %rax
movl 0x8(%rax), %eax
shrl $0x8, %eax
cmpl $0x5, %eax
je 0xbd336e
cmpl $0x3, %eax
jne 0xbd3374
movq (%rdi), %rcx
movb $0x1, (%rcx)
addl $-0x3, %eax
testl $0xfffffffd, %e... | /llvm/IR/Use.h |
llvm::AAPointerInfo* llvm::Attributor::lookupAAFor<llvm::AAPointerInfo>(llvm::IRPosition const&, llvm::AbstractAttribute const*, llvm::DepClassTy, bool) | AAType *lookupAAFor(const IRPosition &IRP,
const AbstractAttribute *QueryingAA = nullptr,
DepClassTy DepClass = DepClassTy::OPTIONAL,
bool AllowInvalidState = false) {
static_assert(std::is_base_of<AbstractAttribute, AAType>::value,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, %r15
movq %rdi, %r12
addq $0x68, %rdi
leaq 0x442edd1(%rip), %rcx # 0x5002692
leaq 0x8(%rsp), %rax
movq %rcx, (%rax)
movups (%rsi), %xmm0
movups %xmm0, 0x8(%rax)
movq %rsp, %rdx
movq %rax, %rsi
callq 0xb... | /llvm/Transforms/IPO/Attributor.h |
(anonymous namespace)::AAAMDFlatWorkGroupSize const* llvm::Attributor::getOrCreateAAFor<(anonymous namespace)::AAAMDFlatWorkGroupSize>(llvm::IRPosition, llvm::AbstractAttribute const*, llvm::DepClassTy, bool, bool) | const AAType *getOrCreateAAFor(IRPosition IRP,
const AbstractAttribute *QueryingAA,
DepClassTy DepClass, bool ForceUpdate = false,
bool UpdateAfterInit = true) {
if (!shouldPropagateCallBaseContext(IRP))
IRP = I... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movl %r8d, %ebx
movq %rcx, %r14
movq %rdi, %r15
leaq 0x18(%rsp), %rax
movq %rsi, (%rax)
movq %rdx, 0x8(%rax)
movq %rax, %rsi
callq 0x213769a
testb %al, %al
jne 0xbd527e
movq $0x0, 0x20(%rsp)
leaq 0x68(%r15), %r12
leaq 0x2a9e984(%rip), %r... | /llvm/Transforms/IPO/Attributor.h |
(anonymous namespace)::AAAMDSizeRangeAttribute::getAsStr[abi:cxx11](llvm::Attributor*) const | const std::string getAsStr(Attributor *) const override {
std::string Str;
raw_string_ostream OS(Str);
OS << getName() << '[';
OS << getAssumed().getLower() << ',' << getAssumed().getUpper() - 1;
OS << ']';
return OS.str();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc0, %rsp
movq %rsi, %r14
movq %rdi, %rbx
leaq 0xb0(%rsp), %r13
movq %r13, -0x10(%r13)
xorl %eax, %eax
movq %rax, -0x8(%r13)
movb %al, (%r13)
leaq 0x58(%rsp), %r15
movl $0x0, 0x8(%r15)
movb %al, 0x28(%r15)
movl $0x1, 0x2c(%r15)
xorps %xmm0, %xmm0
movups %xmm... | /Target/AMDGPU/AMDGPUAttributor.cpp |
(anonymous namespace)::AMDGPUCodeGenPrepareImpl::getI32Ty(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::Type const*) const | Type *AMDGPUCodeGenPrepareImpl::getI32Ty(IRBuilder<> &B, const Type *T) const {
assert(needsPromotionToI32(T) && "T does not need promotion to i32");
if (T->isIntegerTy())
return B.getInt32Ty();
return FixedVectorType::get(B.getInt32Ty(), cast<FixedVectorType>(T));
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rsi, %rbx
movb 0x8(%rsi), %bpl
movq 0x48(%rdi), %rdi
callq 0x1a89f44
cmpb $0xd, %bpl
jne 0xbe18c0
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
movl 0x20(%rbx), %esi
movq %rax, %rdi
addq $0x8, %rsp
popq %rbx
popq %rbp
jmp 0x1a8aaa8
nop
| /Target/AMDGPU/AMDGPUCodeGenPrepare.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::PHINode const*, bool, llvm::DenseMapInfo<llvm::PHINode const*, void>, llvm::detail::DenseMapPair<llvm::PHINode const*, bool>>, llvm::PHINode const*, bool, llvm::DenseMapInfo<llvm::PHINode const*, void>, llvm::detail::DenseMapPair<llvm::PHINode const*, bool>>::LookupBucketFor... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xbe3075
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jne... | /llvm/ADT/DenseMap.h |
llvm::IRBuilderBase::InsertPointGuard::~InsertPointGuard() | ~InsertPointGuard() {
Builder.restoreIP(InsertPoint(Block, Point));
Builder.SetCurrentDebugLocation(DbgLoc);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq (%rdi), %rdi
movq 0x8(%rbx), %rsi
testq %rsi, %rsi
je 0xbed012
movzwl 0x18(%rbx), %ecx
movq 0x10(%rbx), %rdx
callq 0x90ca4e
jmp 0xbed01f
xorps %xmm0, %xmm0
movups %xmm0, 0x30(%rdi)
movw $0x0, 0x40(%rdi)
movq (%rbx), %r14
movq 0x20(%rbx), %rsi
movq %rsi, (%rsp)
testq... | /llvm/IR/IRBuilder.h |
llvm::AMDGPUInstructionSelector::selectMUBUFAddr64(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectMUBUFAddr64(MachineOperand &Root) const {
Register VAddr;
Register RSrcReg;
Register SOffset;
int64_t Offset = 0;
if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))
return {};
// FIXME: Use defaulted operands for ... | pushq %r15
pushq %r14
pushq %rbx
subq $0x190, %rsp # imm = 0x190
movq %rsi, %r14
movq %rdi, %rbx
xorl %esi, %esi
leaq 0x14(%rsp), %rax
movl %esi, (%rax)
leaq 0x10(%rsp), %rcx
movl %esi, (%rcx)
leaq 0xc(%rsp), %r8
movl %esi, (%r8)
leaq 0x18(%rsp), %r9
movq $0x0, (%r9)
movq %r14, %rdi
movq %rdx, %rsi
movq %rax... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing(
MachineOperand &Root) const {
Register Src;
unsigned Mods;
std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /*IsCanonicalizing=*/false);
return {{
[=](MachineInstrBuilder &MIB) {
MIB.addReg(copyT... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %rsi
xorl %edx, %edx
movl $0x1, %ecx
xorl %r8d, %r8d
callq 0xbfe662
movq %rax, %r13
movq %rax, %rbp
shrq $0x20, %rbp
xorps %xmm0, %xmm0
leaq 0x40(%rsp), %r14
mova... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectImageIntrinsic(llvm::MachineInstr&, llvm::AMDGPU::ImageDimIntrinsicInfo const*) const | bool AMDGPUInstructionSelector::selectImageIntrinsic(
MachineInstr &MI, const AMDGPU::ImageDimIntrinsicInfo *Intr) const {
MachineBasicBlock *MBB = MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
const... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r14
movq 0x18(%rsi), %rax
movq %rax, 0xe0(%rsp)
movl 0x4(%rdx), %edi
movl %edi, 0x18(%rsp)
callq 0x1d2c7ff
movq %rax, %r12
movl 0x8(%r13), %edi
callq 0x1d2c86b
movq %rax, %r15
movq 0x78(%r14), ... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectStackRestore(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectStackRestore(MachineInstr &MI) const {
Register SrcReg = MI.getOperand(0).getReg();
if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))
return false;
MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
Register SP =
Subtarget->getTargetLowering()... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r15
movq 0x20(%rsi), %rax
movl 0x4(%rax), %r12d
movq 0x48(%rdi), %rdx
leaq 0x4af9bb9(%rip), %rsi # 0x5702600
movl %r12d, %edi
callq 0x1882148
movq %rax, %r13
testq %rax, %rax
je 0xc08cce
movq 0x48(%r15), %rd... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::select(llvm::MachineInstr&) | bool AMDGPUInstructionSelector::select(MachineInstr &I) {
if (!I.isPreISelOpcode()) {
if (I.isCopy())
return selectCOPY(I);
return true;
}
switch (I.getOpcode()) {
case TargetOpcode::G_AND:
case TargetOpcode::G_OR:
case TargetOpcode::G_XOR:
if (selectImpl(I, *CoverageInfo))
return ... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x10(%rsi), %rcx
movzwl 0x44(%rsi), %eax
testb $0x1, 0x10(%rcx)
jne 0xc08d17
cmpl $0x13, %eax
jne 0xc090c7
movq %r14, %rdi
movq %rbx, %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0xbf8948
cmpl $0xe1, %eax
jg 0xc08d5e
leal -0x33(%rax), %ecx
cmpl $0x91... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::SmallVectorTemplateBase<llvm::AMDGPUInstructionSelector::GEPInfo, false>::destroy_range(llvm::AMDGPUInstructionSelector::GEPInfo*, llvm::AMDGPUInstructionSelector::GEPInfo*) | static void destroy_range(T *S, T *E) {
while (S != E) {
--E;
E->~T();
}
} | cmpq %rdi, %rsi
je 0xc0add0
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
addq $-0x10, %r14
movq -0x10(%r14), %rdi
cmpq %rdi, %r14
je 0xc0ada7
callq 0x751980
movq -0x28(%r14), %rdi
leaq -0x18(%r14), %rax
cmpq %rdi, %rax
je 0xc0adb9
callq 0x751980
leaq -0x38(%r14), %rax
addq $-0x28, %r14
cmpq %rbx, %r... | /llvm/ADT/SmallVector.h |
AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
SDLoc SL(N);
// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
SDValue Ops[10];
SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
SelectVOP3Mods(N->get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0xd0, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xc10566
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%rbx), %eax
movl %eax, 0x18(%rsp)
movl $0x8, %eax
movq $0x0, 0x28(%rsp,%rax)
mo... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectMAD_64_32(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) {
SDLoc SL(N);
bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32;
unsigned Opc;
if (Subtarget->hasMADIntraFwdBug())
Opc = Signed ? AMDGPU::V_MAD_I64_I32_gfx11_e64
: AMDGPU::V_MAD_U64_U32_gfx11_e64;
else
Opc = Signed ? AMDGPU::V_... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x78, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xc10c5f
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%rbx), %eax
leaq 0x10(%rsp), %r15
movl %eax, 0x8(%r15)
cmpl $0x22d, 0x18(%rbx) # imm ... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::isUnneededShiftMask(llvm::SDNode const*, unsigned int) const | bool AMDGPUDAGToDAGISel::isUnneededShiftMask(const SDNode *N,
unsigned ShAmtBits) const {
assert(N->getOpcode() == ISD::AND);
const APInt &RHS = N->getConstantOperandAPInt(1);
if (RHS.countr_one() >= ShAmtBits)
return true;
const APInt &LHSKnownZeros = CurDAG->... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x40, %rsp
movl %edx, %ebx
movq %rdi, %r15
movq 0x28(%rsi), %r12
movq 0x28(%r12), %rax
movq 0x58(%rax), %rax
leaq 0x18(%rax), %r14
cmpl $0x40, 0x20(%rax)
ja 0xc11efb
movq (%r14), %rax
xorq $-0x1, %rax
je 0xc11f05
bsfq %rax, %rax
jmp 0xc11f0a
movq %r14, %rdi
c... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
llvm::AMDGPUTargetLowering::lowerUnhandledCall(llvm::TargetLowering::CallLoweringInfo&, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::StringRef) const | SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals,
StringRef Reason) const {
SDValue Callee = CLI.Callee;
SelectionDAG &DAG = CLI.DAG;
const Function &Fn = DAG.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %r8, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq %rdx, %r14
movq %rsi, %r15
movq 0x28(%rsi), %rax
movq 0x50(%rsi), %rbx
movq 0x28(%rbx), %rdx
movl 0x18(%rax), %ecx
cmpl $0x2a, %ecx
je 0xc2053b
cmpl $0x12, %ecx
jne 0xc20540
movq %rax, %rsi
... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::lowerFEXP(llvm::SDValue, llvm::SelectionDAG&) const | SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc SL(Op);
SDValue X = Op.getOperand(0);
SDNodeFlags Flags = Op->getFlags();
const bool IsExp10 = Op.getOpcode() == ISD::FEXP10;
if (VT.getScalarType() == MVT::f16) {
// v_exp_f16 (fmul x, log2... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3a8, %rsp # imm = 0x3A8
movq %rcx, %rbx
movq %rsi, %r14
movq %rdi, %r12
movq 0x30(%rsi), %rax
movl %edx, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %dl
movq 0x8(%rax,%rcx), %rax
movb %dl, 0x38(%rsp)
movq %rax, 0x40(%rsp)
movq 0x48(%rsi), %... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::LowerFP_TO_INT(llvm::SDValue, llvm::SelectionDAG&) const | SDValue AMDGPUTargetLowering::LowerFP_TO_INT(const SDValue Op,
SelectionDAG &DAG) const {
SDValue Src = Op.getOperand(0);
unsigned OpOpcode = Op.getOpcode();
EVT SrcVT = Src.getValueType();
EVT DestVT = Op.getValueType();
// Will be selected natively
if (SrcVT =... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %edx, %r15d
movq %rsi, %rbx
movq 0x28(%rsi), %r9
movq (%r9), %rbp
movl 0x8(%r9), %r13d
movq 0x30(%rbp), %rax
movq %r13, %rdx
shlq $0x4, %rdx
movb (%rax,%rdx), %al
movq 0x30(%rsi), %rdx
movl %r15d, %esi
shlq $0x4, %rsi
movb (%rdx,%rs... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::APFloat::add(llvm::APFloat const&, llvm::RoundingMode) | opStatus add(const APFloat &RHS, roundingMode RM) {
assert(&getSemantics() == &RHS.getSemantics() &&
"Should only call on two APFloats with the same semantics");
if (usesLayout<IEEEFloat>(getSemantics()))
return U.IEEE.add(RHS.U.IEEE, RM);
if (usesLayout<DoubleAPFloat>(getSemantics()))
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x8(%rdi), %r15
addq $0x8, %r14
callq 0x1c76792
addq $0x8, %rbx
movsbl %bpl, %edx
movq %r14, %rdi
movq %rbx, %rsi
addq $0x8, %rsp
cmpq %r15, %rax
je 0xc34f10
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x1c78a2e
... | /llvm/ADT/APFloat.h |
llvm::AMDGPUTargetLowering::getTargetNodeName(unsigned int) const | const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((AMDGPUISD::NodeType)Opcode) {
case AMDGPUISD::FIRST_NUMBER: break;
// AMDIL DAG nodes
NODE_NAME_CASE(UMUL);
NODE_NAME_CASE(BRANCH_COND);
// AMDGPU DAG nodes
NODE_NAME_CASE(IF)
NODE_NAME_CASE(ELSE)
NODE_NAME_CASE(LOO... | leal -0x1e6(%rsi), %eax
cmpl $0x62, %eax
ja 0xc35475
leaq 0x2b4db00(%rip), %rcx # 0x3782f64
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
leaq 0x329bb30(%rip), %rax # 0x3ed0fa4
retq
addl $0xfffffc26, %esi # imm = 0xFFFFFC26
cmpl $0x36, %esi
ja 0xc358d4
leaq 0x2b4dc65(%rip), %rax # 0x37830f0
movslq (... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(llvm::SDValue, llvm::SelectionDAG const&, bool, unsigned int) const | bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
const SelectionDAG &DAG,
bool SNaN,
unsigned Depth) const {
unsigned Opcode = Op.g... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %r9d, %ebx
movq %rcx, %r14
movq %rsi, %r15
movl 0x18(%rsi), %eax
movb $0x1, %bpl
cmpl $0x237, %eax # imm = 0x237
jg 0xc36a4d
leal -0x1f7(%rax), %ecx
cmpl $0x23, %ecx
ja 0xc36aa0
leaq 0x2b4c81b(%rip), %rax # 0x37831fc
movslq (%rax,%rcx,4), %rcx
add... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::TargetLoweringBase::getPreferredVectorAction(llvm::MVT) const | unsigned getVectorMinNumElements() const {
assert(SimpleTy >= FIRST_VALUETYPE && SimpleTy <= LAST_VALUETYPE);
static constexpr uint16_t NElemTable[] = {
#define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, NElem, EltTy) NElem,
#include "llvm/CodeGen/GenVT.inc"
#undef GET_VT_ATTR
};
unsigned NEl... | movzbl %sil, %eax
leaq 0x274f9fb(%rip), %rcx # 0x3386810
movzwl -0x2(%rcx,%rax,2), %ecx
addb $0x42, %al
cmpb $-0x35, %al
setb %dl
cmpw $0x1, %cx
sete %sil
movb $0x5, %al
testb %sil, %dl
jne 0xc36e43
leal -0x1(%rcx), %eax
testw %ax, %cx
movl $0x1, %ecx
movl $0x7, %eax
cmovel %ecx, %eax
retq
| /llvm/CodeGenTypes/MachineValueType.h |
bool llvm::PatternMatch::FNeg_match<llvm::PatternMatch::class_match<llvm::Value>>::match<llvm::Use>(llvm::Use*) | inline OneUse_match<T> m_OneUse(const T &SubPattern) {
return SubPattern;
} | pushq %r14
pushq %rbx
pushq %rax
movq (%rsi), %rbx
movq %rbx, %rdi
callq 0x903dce
xorb $0x1, %al
testq %rbx, %rbx
sete %cl
orb %al, %cl
jne 0xc3703c
movzbl (%rbx), %eax
leal -0x1d(%rax), %ecx
cmpl $0x1d, %eax
movzwl 0x2(%rbx), %eax
cmovael %ecx, %eax
cmpl $0x10, %eax
je 0xc36fc1
cmpl $0xc, %eax
jne 0xc3703c
movb $0x1, ... | /llvm/IR/PatternMatch.h |
llvm::SmallVectorTemplateBase<llvm::WeakTrackingVH, false>::moveElementsForGrow(llvm::WeakTrackingVH*) | void SmallVectorTemplateBase<T, TriviallyCopyable>::moveElementsForGrow(
T *NewElts) {
// Move the elements over.
this->uninitialized_move(this->begin(), this->end(), NewElts);
// Destroy the original elements.
destroy_range(this->begin(), this->end());
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x8(%rdi), %eax
testq %rax, %rax
je 0xc391eb
movq %rsi, %r14
movq (%rbx), %r15
shlq $0x3, %rax
leaq (%rax,%rax,2), %r12
movq %r14, %rdi
movl $0x3, %esi
movq %r15, %rdx
callq 0xaa1ac4
addq $0x18, %r15
addq $0x18, %r14
addq $-0x18, %r12
jne 0xc39... | /llvm/ADT/SmallVector.h |
llvm::SmallPtrSetImpl<llvm::Value*>::insert(llvm::Value*) | std::pair<iterator, bool> insert(PtrType Ptr) {
auto p = insert_imp(PtrTraits::getAsVoidPointer(Ptr));
return std::make_pair(makeIterator(p.first), p.second);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %rsi
callq 0x8efa2e
movq 0x8(%r14), %rcx
xorl %esi, %esi
cmpq (%r14), %rcx
sete %sil
movl 0x10(%r14,%rsi,4), %esi
leaq (%rcx,%rsi,8), %rcx
cmpq %rax, %rcx
je 0xc393d3
cmpq $-0x2, (%rax)
jb 0xc393d3
addq $0x8, %rax
cmpq %rcx, %ra... | /llvm/ADT/SmallPtrSet.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>::... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xc39805
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
neg... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::DenseMap<llv... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xc39d65
movq (%r15), %rax
movabsq $0x7ffffffffffffff, %rdx # imm = 0x7FFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ec... | /llvm/ADT/DenseMap.h |
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
Register DstDivReg, DstRemReg;
switch (MI.getOpcode()) {
default:
llvm_unreachable("Une... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %rbx
movzwl 0x44(%rsi), %ecx
movq 0x20(%rsi), %rax
movl 0x4(%rax), %ebp
cmpl $0x37, %ecx
je 0xc4456f
cmpl $0x39, %ecx
jne 0xc44574
movl %ebp, %r15d
xorl %ebp, %ebp
jmp 0xc44578
xorl %r15d, %r15d
jmp 0xc44578
movl 0x24(%rax... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeFExp2(llvm::MachineInstr&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeFExp2(MachineInstr &MI,
MachineIRBuilder &B) const {
// v_exp_f32 is good enough for OpenCL, except it doesn't handle denormals.
// If we have to handle denormals, scale up the input and adjust the result.
Register Dst = MI.getOperand(0).g... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdx, %r14
movq %rsi, %r13
movq 0x20(%rsi), %rax
movl 0x4(%rax), %ebx
movl 0x2c(%rsi), %r15d
movq %r15, 0x38(%rsp)
andl $0xffffff, %r15d # imm = 0xFFFFFF
testl %ebx, %ebx
jns 0xc45c6b
movq 0x18(%r14), %rcx
movl %ebx, %edx
and... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(llvm::MachineIRBuilder&, llvm::Register, llvm::Register, llvm::Register, llvm::Register) const | void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B,
Register DstDivReg,
Register DstRemReg,
Register Numer,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movl %r9d, 0x20(%rsp)
movl %r8d, 0x58(%rsp)
movl %ecx, 0xdc(%rsp)
movl %edx, 0xd8(%rsp)
movq %rsi, %rbx
leaq 0x90(%rsp), %r14
movl %r9d, (%r14)
xorl %r12d, %r12d
movl %r12d, 0x10(%r14)
movl $0x101, %r15d ... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
if (ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
return true;
Register ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq 0x1d8d0(%rdi), %rdi
movb $0x1, %al
cmpl $0x7, 0x1f8(%rdi)
jl 0xc51650
movq 0x20(%rsi), %rax
movl 0x4(%rax), %edi
testl %edi, %edi
jns 0xc51334
movl %edi, %r8d
andl $0x7fffffff, %r8d # imm = 0x7FFFFFFF
cmpl %r8d, 0x1d0(%rdx)
jb... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::fixStoreSourceType(llvm::MachineIRBuilder&, llvm::Register, bool) const | Register AMDGPULegalizerInfo::fixStoreSourceType(
MachineIRBuilder &B, Register VData, bool IsFormat) const {
MachineRegisterInfo *MRI = B.getMRI();
LLT Ty = MRI->getType(VData);
const LLT S16 = LLT::scalar(16);
// Fixup buffer resources themselves needing to be v4i128.
if (hasBufferRsrcWorkaround(Ty))
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r12
movq 0x18(%rsi), %r15
testl %edx, %edx
jns 0xc529fb
movl %ebx, %eax
andl $0x7fffffff, %eax # imm = 0x7FFFFFFF
cmpl %eax, 0x1d0(%r15)
jbe 0xc529fb
movl %eax, %eax
movq 0x1c8(%r15)... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULegalizerInfo::legalizeTrapEndpgm(llvm::MachineInstr&, llvm::MachineRegisterInfo&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeTrapEndpgm(
MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock &BB = B.getMBB();
MachineFunction *MF = BB.getParent();
if (BB.succ_empty() && std::next(MI.getIterator()) == BB.end()) {
Build... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, %r15
movq %rsi, %rbx
movq 0x38(%rcx), %r14
movq 0x20(%r14), %r13
movq 0x58(%r14), %rax
cmpq 0x60(%r14), %rax
jne 0xc55a0e
leaq 0x30(%r14), %r12
cmpq %r12, 0x8(%rbx)
je 0xc55c03
movq %r14, %rdi
movq %rbx, %rsi
xorl %edx, %edx
x... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
getBufferRsrcScalarType(llvm::LLT) | constexpr bool isValid() const { return IsScalar || RawData != 0; } | testq $-0x7, %rdi
sete %al
testb $0x4, %dil
sete %cl
orb %al, %cl
jne 0xc58958
movl %edi, %eax
shrl $0x3, %eax
testb $0x2, %dil
movabsq $0x8000000000000, %rcx # imm = 0x8000000000000
movabsq $0x800000000000000, %rdx # imm = 0x800000000000000
cmoveq %rcx, %rdx
movzwl %ax, %ecx
xorl %eax, %eax
testq %rdi, %rdx
setne %al... | /llvm/CodeGenTypes/LowLevelType.h |
llvm::AMDGPULibCalls::useNative(llvm::CallInst*) | bool AMDGPULibCalls::useNative(CallInst *aCI) {
Function *Callee = aCI->getCalledFunction();
if (!Callee || aCI->isNoBuiltin())
return false;
FuncInfo FInfo;
if (!parseFunctionName(Callee->getName(), FInfo) || !FInfo.isMangled() ||
FInfo.getPrefix() != AMDGPULibFunc::NOPFX ||
getArgType(FInfo) ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq -0x20(%rsi), %rax
xorl %r15d, %r15d
testq %rax, %rax
je 0xc5a563
cmpb $0x0, (%rax)
cmoveq %rax, %r15
testq %r15, %r15
je 0xc5a572
movq 0x18(%r15), %rax
cmpq 0x50(%rbx), %rax
je 0xc5a575
xorl %r15d, %r... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::AMDGPULibCalls::fold_read_write_pipe(llvm::CallInst*, llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::AMDGPULibFunc const&) | bool AMDGPULibCalls::fold_read_write_pipe(CallInst *CI, IRBuilder<> &B,
const FuncInfo &FInfo) {
auto *Callee = CI->getCalledFunction();
if (!Callee->isDeclaration())
return false;
assert(Callee->hasName() && "Invalid read_pipe/write_pipe function");
auto *M = Call... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %rdx, %r12
movq %rsi, %r14
movq -0x20(%rsi), %rax
xorl %r15d, %r15d
testq %rax, %rax
je 0xc5a782
cmpb $0x0, (%rax)
cmoveq %rax, %r15
testq %r15, %r15
je 0xc5a791
movq 0x18(%r15), %rax
cmpq 0x50(%r14), %rax
... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::CallInst* CreateCallEx<llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>>(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::FunctionCallee, llvm::Value*, llvm::Twine const&) | static CallInst *CreateCallEx(IRB &B, FunctionCallee Callee, Value *Arg,
const Twine &Name = "") {
CallInst *R = B.CreateCall(Callee, Arg, Name);
if (Function *F = dyn_cast<Function>(Callee.getCallee()))
R->setCallingConv(F->getCallingConv());
return R;
} | pushq %rbx
subq $0x10, %rsp
movq %r8, %r9
movq %rdx, %rbx
leaq 0x8(%rsp), %rax
movq %rcx, (%rax)
movq $0x0, (%rsp)
movl $0x1, %r8d
movq %rax, %rcx
callq 0x90a53c
cmpb $0x0, (%rbx)
jne 0xc5d7d7
movzwl 0x2(%rbx), %ecx
movzwl 0x2(%rax), %edx
andl $0xfffff003, %edx # imm = 0xFFFFF003
shrl $0x2, %ecx
andl $0xffc, %ecx... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::AMDGPULibCalls::replaceLibCallWithSimpleIntrinsic(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::CallInst*, unsigned int) | void AMDGPULibCalls::replaceLibCallWithSimpleIntrinsic(IRBuilder<> &B,
CallInst *CI,
Intrinsic::ID IntrID) {
if (CI->arg_size() == 2) {
Value *Arg0 = CI->getArgOperand(0);
Value *Arg1 = CI->getArgOper... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x30, %rsp
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdx, %rdi
callq 0x8f171e
movl 0x4(%rbx), %ecx
shll $0x5, %ecx
movq %rbx, %rsi
subq %rcx, %rsi
subq %rsi, %rax
movabsq $0x1fffffffe0, %rcx # imm = 0x1FFFFFFFE0
andq %rax, %rcx
cmpq $0x40, %rcx
jne 0xc5d920
movq (%... | /Target/AMDGPU/AMDGPULibCalls.cpp |
llvm::AMDGPULibCalls::evaluateScalarMathFunc(llvm::AMDGPULibFunc const&, double&, double&, llvm::Constant*, llvm::Constant*) | bool AMDGPULibCalls::evaluateScalarMathFunc(const FuncInfo &FInfo, double &Res0,
double &Res1, Constant *copr0,
Constant *copr1) {
// By default, opr0/opr1/opr3 holds values of float/double type.
// If they are not float/double,... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r9, %r14
movq %rcx, %r15
movq %rdx, %rbx
movq %rsi, %r12
xorl %ebp, %ebp
testq %r8, %r8
je 0xc5dbd9
cmpb $0x12, (%r8)
cmoveq %r8, %rbp
xorl %r13d, %r13d
testq %r14, %r14
je 0xc5dbe9
cmpb $0x12, (%r14)
cmoveq %r14, %r13
xorps %xmm1,... | /Target/AMDGPU/AMDGPULibCalls.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [15], llvm::cl::desc, llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [15], llvm::cl::desc const&, llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7512e0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movups (%r12), %xmm0
movups %xmm0, 0x20(%rbx)
movq (%r15), %rax
movb (%rax), %cl
movb %cl, ... | /llvm/Support/CommandLine.h |
addInstToMergeableList(llvm::IntrinsicInst*, llvm::SmallVector<llvm::SmallVector<llvm::IntrinsicInst*, 4u>, 1u>&, llvm::AMDGPU::ImageDimIntrinsicInfo const*) | void addInstToMergeableList(
IntrinsicInst *II,
SmallVector<SmallVector<IntrinsicInst *, 4>> &MergeableInsts,
const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) {
for (SmallVector<IntrinsicInst *, 4> &IIList : MergeableInsts) {
// Check Dim.
if (IIList.front()->getIntrinsicID() != II->getIntrinsic... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x18(%rsp)
movl 0x8(%rsi), %eax
testq %rax, %rax
sete %bl
je 0xc5e915
movq %rdx, %r14
movq 0x18(%rsp), %rcx
movq (%rcx), %r15
leaq (%rax,%rax,2), %r12
shlq $0x4, %r12
addq %r15, %r12
movq %r12, 0x30(%rsp)... | /Target/AMDGPU/AMDGPUImageIntrinsicOptimizer.cpp |
llvm::SmallVectorImpl<llvm::IntrinsicInst*>::assignRemote(llvm::SmallVectorImpl<llvm::IntrinsicInst*>&&) | void assignRemote(SmallVectorImpl &&RHS) {
this->destroy_range(this->begin(), this->end());
if (!this->isSmall())
free(this->begin());
this->BeginX = RHS.BeginX;
this->Size = RHS.Size;
this->Capacity = RHS.Capacity;
RHS.resetToSmall();
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq (%rdi), %rdi
leaq 0x10(%r14), %rax
cmpq %rax, %rdi
je 0xc5f69f
callq 0x751980
movq (%rbx), %rax
movq %rax, (%r14)
movq 0x8(%rbx), %rax
movq %rax, 0x8(%r14)
leaq 0x10(%rbx), %rax
movq %rax, (%rbx)
movq $0x0, 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::eatLengthPrefixedName(llvm::StringRef&) | static StringRef eatLengthPrefixedName(StringRef& mangledName) {
int const Len = eatNumber(mangledName);
if (Len <= 0 || static_cast<size_t>(Len) > mangledName.size())
return StringRef();
StringRef Res = mangledName.substr(0, Len);
drop_front(mangledName, Len);
return Res;
} | pushq %rbx
movq %rdi, %rbx
callq 0xc61517
testl %eax, %eax
jle 0xc6033d
movl %eax, %ecx
movq 0x8(%rbx), %rsi
xorl %eax, %eax
movl $0x0, %edx
subq %rcx, %rsi
jb 0xc60341
movq (%rbx), %rax
leaq (%rax,%rcx), %rdx
movq %rdx, (%rbx)
movq %rsi, 0x8(%rbx)
movq %rcx, %rdx
jmp 0xc60341
xorl %eax, %eax
xorl %edx, %edx
popq %rbx
... | /Target/AMDGPU/AMDGPULibFunc.cpp |
llvm::AMDGPULibFuncImpl::setName(llvm::StringRef) | void setName(StringRef N) { Name = std::string(N); } | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
leaq 0x10(%rsp), %r15
movq %r15, -0x10(%r15)
addq %rsi, %rdx
movq %rsp, %r14
movq %r14, %rdi
callq 0x7c37bc
addq $0x10, %rbx
movq %rbx, %rdi
movq %r14, %rsi
callq 0x751c10
movq (%r14), %rdi
cmpq %r15, %rdi
je 0xc60427
movq 0x10(%rsp), %rsi
incq %rsi
call... | /Target/AMDGPU/AMDGPULibFunc.h |
llvm::AMDGPULibFunc::parse(llvm::StringRef, llvm::AMDGPULibFunc&) | bool AMDGPULibFunc::parse(StringRef FuncName, AMDGPULibFunc &F) {
if (FuncName.empty()) {
F.Impl = std::unique_ptr<AMDGPULibFuncImpl>();
return false;
}
if (eatTerm(FuncName, "_Z"))
F.Impl = std::make_unique<AMDGPUMangledLibFunc>();
else
F.Impl = std::make_unique<AMDGPUUnmangledLibFunc>();
if... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rdi, 0x8(%rsp)
movq %rsi, 0x10(%rsp)
cmpq $0x1, %rsi
je 0xc60458
testq %rsi, %rsi
je 0xc604af
cmpw $0x5a5f, (%rdi) # imm = 0x5A5F
je 0xc604ce
movl $0x40, %edi
callq 0x751940
leaq 0x20(%rax), %rcx
movq %rcx, 0x10(%rax)
xorl %ecx, %ecx
movq %rcx, 0x18(%... | /Target/AMDGPU/AMDGPULibFunc.cpp |
getIntrinsicParamType(llvm::LLVMContext&, llvm::AMDGPULibFuncBase::Param const&, bool) | static Type* getIntrinsicParamType(
LLVMContext& C,
const AMDGPULibFunc::Param& P,
bool useAddrSpace) {
Type* T = nullptr;
switch (P.ArgType) {
case AMDGPULibFunc::U8:
case AMDGPULibFunc::I8: T = Type::getInt8Ty(C); break;
case AMDGPULibFunc::U16:
case AMDGPULibFunc::I16: T = Type::getInt16Ty(C);... | pushq %rbx
movq %rsi, %rbx
movzbl (%rsi), %eax
cmpl $0x7f, %eax
jg 0xc60dc8
cmpl $0x20, %eax
jle 0xc60e14
addl $-0x21, %eax
leaq 0x2b24cb8(%rip), %rcx # 0x3785a70
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
callq 0x1a89f30
jmp 0xc60deb
leal -0x80(%rax), %ecx
cmpl $0x6, %ecx
jae 0xc60e2c
leaq 0x2b25359(%rip)... | /Target/AMDGPU/AMDGPULibFunc.cpp |
(anonymous namespace)::AMDGPULowerBufferFatPointers::run(llvm::Module&, llvm::TargetMachine const&) | bool AMDGPULowerBufferFatPointers::run(Module &M, const TargetMachine &TM) {
bool Changed = false;
const DataLayout &DL = M.getDataLayout();
// Record the functions which need to be remapped.
// The second element of the pair indicates whether the function has to have
// its arguments or return types adjusted... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x5d8, %rsp # imm = 0x5D8
movq %rsi, 0x1d0(%rsp)
leaq 0x120(%rdi), %rax
leaq 0x4e8(%rsp), %rdx
movq %rdx, -0x10(%rdx)
movabsq $0x300000000, %rcx # imm = 0x300000000
movq %rcx, -0x8(%rdx)
xorps %xmm0, %xmm0
movups %xmm0, 0x1a0(%rsp)
... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
llvm::DenseMap<llvm::Type*, llvm::Type*, llvm::DenseMapInfo<llvm::Type*, void>, llvm::detail::DenseMapPair<llvm::Type*, llvm::Type*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xc640a2
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value const*, llvm::sys::SmartMutex<false>>>, llvm::WeakTrackingVH, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value const*, llvm::WeakTrackingVH, llvm::ValueMapConfig<llvm::Value ... | unsigned getNumBuckets() const {
return NumBuckets;
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movl 0x10(%rdi), %eax
testl %eax, %eax
je 0xc65792
movq (%rdi), %rcx
leaq 0x8(%rsp), %rdi
movq $0x2, (%rdi)
xorl %r8d, %r8d
movq %r8, 0x8(%rdi)
movq $-0x1000, 0x10(%rdi) # imm = 0xF000
leaq 0x4a97cad(%rip), %r9 # 0x56fd3a0
movq %r9, -0x8(%rdi)
movq %r8, 0x18(%rdi)
movl (%rsi... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SplitPtrStructs::visitLoadInst(llvm::LoadInst&) | PtrParts SplitPtrStructs::visitLoadInst(LoadInst &LI) {
if (!isSplitFatPtr(LI.getPointerOperandType()))
return {nullptr, nullptr};
handleMemoryInst(&LI, nullptr, LI.getPointerOperand(), LI.getType(),
LI.getAlign(), LI.getOrdering(), LI.isVolatile(),
LI.getSyncScopeID());
... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %r15
movq -0x20(%rsi), %rbx
movq 0x8(%rbx), %rdi
callq 0xc66712
testb %al, %al
je 0xc66708
movq 0x8(%r14), %r8
movzwl 0x2(%r14), %eax
movl %eax, %ecx
shrb %cl
andb $0x3f, %cl
movl %eax, %r10d
shrl $0x7, %r10d
andl $0x7, %r10d
movzbl 0x48(%r14), %r11d
subq $0x8... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
(anonymous namespace)::SplitPtrStructs::visitAtomicCmpXchgInst(llvm::AtomicCmpXchgInst&) | PtrParts SplitPtrStructs::visitAtomicCmpXchgInst(AtomicCmpXchgInst &AI) {
Value *Ptr = AI.getPointerOperand();
if (!isSplitFatPtr(Ptr->getType()))
return {nullptr, nullptr};
IRB.SetInsertPoint(&AI);
Type *Ty = AI.getNewValOperand()->getType();
AtomicOrdering Order = AI.getMergedOrdering();
SyncScope::I... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %rbx
movq %rdi, %r15
movq -0x60(%rsi), %r13
movq 0x8(%r13), %rdi
callq 0xc66712
testb %al, %al
je 0xc6743a
leaq 0x128(%r15), %rdi
movq %rdi, 0x10(%rsp)
movq %rbx, %rsi
callq 0x9039aa
movq -0x20(%rbx), %rax
movq 0x8(%rax), %rax... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
(anonymous namespace)::SplitPtrStructs::visitICmpInst(llvm::ICmpInst&) | PtrParts SplitPtrStructs::visitICmpInst(ICmpInst &Cmp) {
Value *Lhs = Cmp.getOperand(0);
if (!isSplitFatPtr(Lhs->getType()))
return {nullptr, nullptr};
Value *Rhs = Cmp.getOperand(1);
IRB.SetInsertPoint(&Cmp);
ICmpInst::Predicate Pred = Cmp.getPredicate();
assert((Pred == ICmpInst::ICMP_EQ || Pred == I... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq -0x40(%rsi), %r12
movq 0x8(%r12), %rdi
callq 0xc66712
testb %al, %al
je 0xc679a9
movq -0x20(%rbx), %r13
leaq 0x128(%r14), %r15
movq %r15, %rdi
movq %rbx, %rsi
callq 0x9039aa
movzwl 0x2(%rbx), %ebp
and... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
(anonymous namespace)::SplitPtrStructs::visitShuffleVectorInst(llvm::ShuffleVectorInst&) | PtrParts SplitPtrStructs::visitShuffleVectorInst(ShuffleVectorInst &I) {
// Cast is needed for the same reason as insertelement's.
if (!isSplitFatPtr(cast<Instruction>(I).getType()))
return {nullptr, nullptr};
IRB.SetInsertPoint(&I);
Value *V1 = I.getOperand(0);
Value *V2 = I.getOperand(1);
ArrayRef<in... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %rdi
callq 0xc66712
testb %al, %al
je 0xc682b6
leaq 0x128(%rbx), %r15
movq %r15, %rdi
movq %r14, %rsi
callq 0x9039aa
movq -0x40(%r14), %rsi
movq -0x20(%r14), %r12
movq 0x48(%r14), %rax
movq... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
(anonymous namespace)::SplitPtrStructs::visitFreezeInst(llvm::FreezeInst&) | PtrParts SplitPtrStructs::visitFreezeInst(FreezeInst &I) {
if (!isSplitFatPtr(I.getType()))
return {nullptr, nullptr};
IRB.SetInsertPoint(&I);
auto [Rsrc, Off] = getPtrParts(I.getOperand(0));
Value *RsrcRes = IRB.CreateFreeze(Rsrc, I.getName() + ".rsrc");
copyMetadata(RsrcRes, &I);
Value *OffRes = IRB.... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %rdi
callq 0xc66712
testb %al, %al
je 0xc683da
leaq 0x128(%rbx), %r12
movq %r12, %rdi
movq %r14, %rsi
callq 0x9039aa
movq -0x20(%r14), %rsi
movq %rbx, %rdi
callq 0xc66b5c
movq %rax, %r15
movq %rdx, %r... | /Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp |
llvm::SmallDenseMap<llvm::Instruction*, llvm::Value*, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Value*>>::init(unsigned int) | void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %eax
movl %eax, %ecx
orl $0x1, %ecx
movl %ecx, (%rdi)
cmpl $0x5, %esi
jb 0xc68760
movl %esi, %ebp
andl $-0x2, %eax
movl %eax, (%rbx)
movl %esi, %edi
shlq $0x4, %rdi
movl $0x8, %esi
callq 0x1cac6bd
movq %rax, 0x8(%rbx)
movl %ebp, 0x10(%rbx)
leaq 0x8(%rbx), %r... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPULowerModuleLDS::recordLDSAbsoluteAddress(llvm::Module*, llvm::GlobalVariable*, unsigned int) | static void recordLDSAbsoluteAddress(Module *M, GlobalVariable *GV,
uint32_t Address) {
// Write the specified address into metadata where it can be retrieved by
// the assembler. Format is a half open range, [Address Address+1)
LLVMContext &Ctx = M->getContext();
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movl %edx, %r15d
movq %rsi, %rbx
movq (%rdi), %r14
addq $0x120, %rdi # imm = 0x120
movq %r14, %rsi
movl $0x3, %edx
callq 0x19e9eda
movq %rax, %r12
movl %r15d, %esi
movq %rax, %rdi
xorl %edx, %edx
callq 0x19d310c
movq %rax, %rdi
callq 0x1... | /Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>>, llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xc6f1c6
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movq (%r11), %rbx
cmpq %rbx, (%rsi)
jne 0xc6f18d
movq %r1... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::GlobalVariable*, llvm::Constant*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseMapPair<llvm::GlobalVariable*, llvm::Constant*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
void llvm::SmallVectorImpl<llvm::Metadata*>::append<llvm::MDNode**, void>(llvm::MDNode**, llvm::MDNode**) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
subq %rsi, %rbx
sarq $0x3, %rbx
movl 0x8(%rdi), %edx
movl 0xc(%rdi), %eax
addq %rbx, %rdx
cmpq %rax, %rdx
jbe 0xc7059e
leaq 0x10(%r14), %rsi
movl $0x8, %ecx
movq %r14, %rdi
callq 0x1cba528
movl 0x8(%r14), %eax
testq %rbx, %rbx
jle 0xc705cd... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>>>, llvm... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
leaq 0x10(%rsp), %r14
movq %rax, %rsi
movq %r14, %rdx
callq 0xc70c42
movl 0x10(%rbx), %edx
shlq $0x5, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x18, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>, llvm::Function*, (anonymous namespace... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xc70d62
pushq %rbp
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movq (%rsi), %rsi
movl %esi, %eax
shrl $0x4, %eax
movl %esi, %r8d
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%r11,%r11,4), %r11
leaq (%rdi,%r11,8),... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, (anonymous namespace)::AMDGPULowerModuleLDS::LDSVariableReplacement>>, llvm::Function*, (anonymous namespace)::AM... | void grow(unsigned AtLeast) {
static_cast<DerivedT *>(this)->grow(AtLeast);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movl 0x10(%rdi), %r14d
decl %esi
movl %esi, %eax
shrl %eax
orl %esi, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVari... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xc70bb6
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xc711a2
xorl %ecx, %ecx
jmp 0xc711bb
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseSetPair<llvm::GlobalVariable*>* llvm::DenseMapBase<llvm::DenseMap<llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::GlobalVariable*, void>, llvm::detail::DenseSetPair<llvm::GlobalVariable*>>, llvm::GlobalVariable*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Globa... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xc7122f
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::Function*, llvm::Value*, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, llvm::Value*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, llvm::Value*, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm:... | std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0xc72406
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0xc723c0
xorl %ecx, %ecx
jmp 0xc723e1
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %rdx
... | /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<llvm::Function*, llvm::GlobalVariable*>* llvm::DenseMapBase<llvm::DenseMap<llvm::Function*, llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::Function*, void>, llvm::detail::DenseMapPair<llvm::Function*, llvm::GlobalVariable*>>, llvm::Function*, llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::F... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xc72989
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [31], llvm::cl::desc, llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [31], llvm::cl::desc const&, llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7512e0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movups (%r12), %xmm0
movups %xmm0, 0x20(%rbx)
movq (%r15), %rax
movb (%rax), %cl
movb %cl, ... | /llvm/Support/CommandLine.h |
(anonymous namespace)::MBBMRT::dump(llvm::TargetRegisterInfo const*, int) | void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
dumpDepth(depth);
dbgs() << "MBB: " << getMBB()->getNumber();
dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %edi
callq 0xc7440c
callq 0x1c9e5e1
leaq 0x2b12461(%rip), %rsi # 0x3786c5f
movl $0x5, %edx
movq %rax, %rdi
callq 0x7c4562
movq 0x18(%r14), %rcx
movslq 0x18(%rcx), %rsi
movq %rax, %rdi
callq 0x1ce9e82
callq 0x1c9e5e... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::po_iterator<llvm::MachineBasicBlock*, llvm::SmallPtrSet<llvm::MachineBasicBlock*, 8u>, false, llvm::GraphTraits<llvm::MachineBasicBlock*>>::po_iterator(llvm::MachineBasicBlock*) | po_iterator(NodeRef BB) {
this->insertEdge(std::optional<NodeRef>(), BB);
VisitStack.emplace_back(BB, GT::child_begin(BB), GT::child_end(BB));
traverseChild();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x8(%rsp), %r14
movq %rsi, (%r14)
leaq 0x20(%rdi), %rax
movq %rax, (%rdi)
movq %rax, 0x8(%rdi)
movq $0x8, 0x10(%rdi)
movl $0x0, 0x18(%rdi)
leaq 0x60(%rdi), %r15
leaq 0x70(%rdi), %rax
movq %rax, 0x60(%rdi)
movabsq $0x800000... | /llvm/ADT/PostOrderIterator.h |
(anonymous namespace)::AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned int, llvm::Register) | void AMDGPUMachineCFGStructurizer::replaceRegisterWith(
unsigned Register, class Register NewRegister) {
assert(Register != NewRegister && "Cannot replace a reg with itself");
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
E = MRI->reg_end();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movq 0x50(%rdi), %rax
movl %esi, %ecx
andl $0x7fffffff, %ecx # imm = 0x7FFFFFFF
movl %esi, %edx
shlq $0x3, %rdx
addq 0x130(%rax), %rdx
shlq $0x4, %rcx
testl %esi, %esi
movq 0x38(%rax), %rax
leaq 0x8(%rax,%rcx), ... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
(anonymous namespace)::RegionMRT::getEntry() | MachineBasicBlock *getEntry() {
MRT *Tree = Children.back();
return (Tree->isRegion()) ? Tree->getRegionMRT()->getEntry()
: Tree->getMBBMRT()->getMBB();
} | pushq %rbx
movq %rdi, %rax
movq 0x48(%rax), %rcx
movl 0x50(%rax), %eax
movq -0x8(%rcx,%rax,8), %rbx
movq (%rbx), %rax
movq %rbx, %rdi
callq *0x10(%rax)
movq (%rbx), %rcx
movq %rbx, %rdi
testq %rax, %rax
je 0xc77883
callq *0x10(%rcx)
jmp 0xc7785e
callq *0x18(%rcx)
movq 0x18(%rax), %rax
popq %rbx
retq
| /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
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