name string | code string | asm string | file string |
|---|---|---|---|
(anonymous namespace)::AMDGPUMachineCFGStructurizer::insertUnconditionalBranch(llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DebugLoc const&) | void AMDGPUMachineCFGStructurizer::insertUnconditionalBranch(MachineBasicBlock *MBB,
MachineBasicBlock *Dest,
const DebugLoc &DL) {
LLVM_DEBUG(dbgs() << "Inserting unconditional branch: " << MBB->getNumber()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x175003e
leaq 0x30(%r15), %rcx
cmpq %rcx, %rax
je 0xc77db7
movq 0x40(%r12), %rdi
movq %rax, %rsi
movq %r14, %rdx
callq 0x18bb7ce
cmpq %r14, 0x8(%r15)
je 0xc77de2
movq 0x40(%r12),... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::detail::DenseSetImpl<std::pair<unsigned int, llvm::MachineBasicBlock*>, llvm::DenseMap<std::pair<unsigned int, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<unsigned int, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<unsigned int, llvm::MachineBasicB... | inline iterator begin() {
// When the map is empty, avoid the overhead of advancing/retreating past
// empty buckets.
if (empty())
return end();
if (shouldReverseIterate<KeyT>())
return makeIterator(getBucketsEnd() - 1, getBuckets(), *this);
return makeIterator(getBuckets(), getBucketsEn... | movq (%rdi), %rsi
movl 0x10(%rdi), %r8d
movq %r8, %rcx
shlq $0x4, %rcx
leaq (%rsi,%rcx), %rdx
cmpl $0x0, 0x8(%rdi)
movq %rdx, %rax
je 0xc786c8
movq %rsi, %rax
testq %r8, %r8
je 0xc786c8
movl (%rax), %esi
cmpl $-0x1, %esi
sete %r8b
movq 0x8(%rax), %rdi
cmpq $-0x1000, %rdi # imm = 0xF000
sete %r9b
testb %r9b, %r... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>>, std::pai... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xc79dda
pushq %r15
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %eax
movl 0x8(%rsi), %r8d
movl %eax, %r9d
shrl $0x4, %r9d
shrl $0x9, %eax
xorl %r9d, %eax
movl %r8d, %r9d
shrl $0x4, %r9d
shrl $0x9, %r8d
xorl %r9d, %r8d
shlq $0x20, %rax
orq %rax, %r8
movabsq $-0x40a7b892... | /llvm/ADT/DenseMap.h |
std::tuple<unsigned int, unsigned int, llvm::MachineBasicBlock*> const* llvm::SmallVectorTemplateCommon<std::tuple<unsigned int, unsigned int, llvm::MachineBasicBlock*>, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<std::tuple<unsigned int, unsigned int, llvm::MachineBasicBlock*>, false>>(llvm::... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x8(%rdi), %ecx
movl 0xc(%rdi), %eax
addq %rcx, %rdx
cmpq %rax, %rdx
ja 0xc7a7a8
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rdi, %r14
movq (%rdi), %rax
shlq $0x4, %rcx
addq %rax, %rcx
cmpq %rbx, %rax
setb... | /llvm/ADT/SmallVector.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [39], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [39], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r12), %rax
movb (%rax), %cl
movb %cl, 0x80(%r14)
movb $0x1, 0x91(%r14)
movb (%rax), ... | /llvm/Support/CommandLine.h |
llvm::SmallVectorImpl<std::shared_ptr<(anonymous namespace)::InstructionRule>>::operator=(llvm::SmallVectorImpl<std::shared_ptr<(anonymous namespace)::InstructionRule>>&&) | SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If the RHS isn't small, clear this vector and then steal its buffer.
if (!RHS.isSmall()) {
this->assignRemote(std::move(RHS));
return *this;
}
// If we already... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0xc7d8db
movq %rsi, %rbp
movq (%rsi), %r12
leaq 0x10(%rsi), %r15
cmpq %r15, %r12
je 0xc7d793
movl 0x8(%rbx), %r14d
testq %r14, %r14
je 0xc7d762
movq (%rbx), %r12
shlq $0x4, %r14
movq -0x8(%r12,%r14), %r... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>>, llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::Smal... | value_type& FindAndConstruct(KeyT &&Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, std::move(Key));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xc7dc88
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xc7dc7e
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xc7dd18
movq (%rbx), %rcx
movq %rcx, (%rax)
leaq 0x18... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>>, llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::Smal... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xc7dfc6
movq (%r15), %rcx
leaq (%rax,%rax,4), %rax
leaq -0x28(,%rax,8), %rax
movabsq $-0x3333333333333333, %rdx # imm = 0xCCCCCCCCC... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<int, llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>>, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xc7e478
movq (%r15), %rax
movabsq $0x7ffffffffffffff, %rdx # imm = 0x7FFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x3, %ec... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::IsPermForDSW::~IsPermForDSW() | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
auto MI = SU->getInstr();
if (MI->getOpcode() != AMDGPU::V_PERM_B32_e64)
return false;
bool FitsInGroup = false;
// Does the VALU have a DS_WRITE successor
... | pushq %rbx
movq %rdi, %rbx
leaq 0x4a9afab(%rip), %rax # 0x571bce0
movq %rax, (%rdi)
cmpb $0x1, 0x48(%rdi)
jne 0xc80d54
movb $0x0, 0x48(%rbx)
movq 0x18(%rbx), %rdi
leaq 0x28(%rbx), %rax
cmpq %rax, %rdi
je 0xc80d54
callq 0x751980
movl $0x50, %esi
movq %rbx, %rdi
popq %rbx
jmp 0x7510e0
| /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::IsSuccOfPrevGroup::apply(llvm::SUnit const*, llvm::ArrayRef<llvm::SUnit*>, llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&) | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
SchedGroup *OtherGroup = nullptr;
for (auto &PipeSG : SyncPipe) {
if ((unsigned)PipeSG.getSGID() == SGID - 1) {
OtherGroup = &PipeSG;
}
}
if... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, 0x10(%rsp)
movl 0x8(%r8), %eax
testq %rax, %rax
je 0xc80f08
movq (%r8), %rcx
movl 0x10(%rdi), %edx
decl %edx
imulq $0x188, %rax, %rsi # imm = 0x188
xorl %eax, %eax
cmpl %edx, 0x10(%rcx)
cmoveq %rcx, %rax
addq $0x188, %rcx... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::VMEMSize::apply(llvm::SUnit const*, llvm::ArrayRef<llvm::SUnit*>, llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&) | void PipelineSolver::reset() {
for (auto &SyncPipeline : CurrPipeline) {
for (auto &SG : SyncPipeline) {
SmallVector<SUnit *, 32> TempCollection = SG.Collection;
SG.Collection.clear();
auto SchedBarr = llvm::find_if(TempCollection, [](SUnit *SU) {
return SU->getInstr()->getOpcode() == A... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp # imm = 0x1D8
movq (%rsi), %rbp
cmpw $0x14, 0x44(%rbp)
jne 0xc814e8
xorl %ebx, %ebx
jmp 0xc81740
movq %rcx, %rbx
testq %rcx, %rcx
je 0xc8173e
movq %rdx, %r14
movq 0x8(%rdi), %r13
leaq 0x50(%rsp), %r15
leaq 0x58(%r13), %rsi
mo... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::SchedGroup& llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>::emplace_back<(anonymous namespace)::SchedGroupMask, unsigned int&, unsigned int&, llvm::ScheduleDAGInstrs*&, llvm::SIInstrInfo const*&>((anonymous namespace)::SchedGroupMask&&, unsigned int&, unsigned int&, llvm::ScheduleDAGIns... | size_t size() const { return Size; } | movl 0x8(%rdi), %eax
cmpl 0xc(%rdi), %eax
jae 0xc84666
movq (%rdi), %r10
imulq $0x188, %rax, %rax # imm = 0x188
movl (%rsi), %esi
movl (%rdx), %edx
movl (%rcx), %ecx
movq (%r8), %r8
movq (%r9), %r9
btsq $0x20, %rdx
leaq (%r10,%rax), %r11
addq $0x28, %r11
movl %esi, -0x28(%r11)
movq %rdx, -0x24(%r11)
movl %ecx, -0x... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::MFMAExpInterleaveOpt::EnablesNthMFMA::apply(llvm::SUnit const*, llvm::ArrayRef<llvm::SUnit*>, llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&) | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
bool FoundTrans = false;
unsigned Counter = 1;
auto DAG = SyncPipe[0].DAG;
if (Cache->empty()) {
SmallVector<SUnit *, 8> Worklist;
auto I = DAG->SUni... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %rbx
movq (%r8), %rax
movq 0x178(%rax), %r14
leaq 0x18(%rdi), %r15
cmpl $0x0, 0x20(%rdi)
jne 0xc84aea
movq %rdi, %r12
leaq 0x18(%rsp), %r13
movq %r13, -0x10(%r13)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, ... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMAExpInterleaveOpt::IsFMA::~IsFMA() | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
return SU->getInstr()->getOpcode() == AMDGPU::V_FMA_F32_e64 ||
SU->getInstr()->getOpcode() == AMDGPU::V_PK_FMA_F32;
} | pushq %rbx
movq %rdi, %rbx
leaq 0x4a97105(%rip), %rax # 0x571bce0
movq %rax, (%rdi)
cmpb $0x1, 0x48(%rdi)
jne 0xc84bfa
movb $0x0, 0x48(%rbx)
movq 0x18(%rbx), %rdi
leaq 0x28(%rbx), %rax
cmpq %rax, %rdi
je 0xc84bfa
callq 0x751980
movl $0x50, %esi
movq %rbx, %rdi
popq %rbx
jmp 0x7510e0
| /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMAExpInterleaveOpt::IsExactMFMA::apply(llvm::SUnit const*, llvm::ArrayRef<llvm::SUnit*>, llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&) | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr()))
return false;
if (Cache->empty()) {
auto TempSU = ChainSeed;
auto Depth = Number;
while (De... | testq %rsi, %rsi
je 0xc855ce
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movabsq $-0x7800000000000000, %rax # imm = 0x8800000000000000
movq 0x58(%rdi), %rsi
movq (%rsi), %rdx
movq 0x10(%rdx), %rcx
movq 0x18(%rcx), %rcx
movzwl 0x44(%rdx), %edx
addl $0xffffeb9a, %edx ... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
void llvm::DenseMapBase<llvm::DenseMap<llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm::SmallVector<int, 4u>>>, llvm::SUnit*, llvm::SmallVector<int, 4u>, llvm::DenseMapInfo<llvm::SUnit*, void>, llvm::detail::DenseMapPair<llvm::SUnit*, llvm:... | unsigned getNumEntries() const {
return NumEntries;
} | movq 0x8(%rsi), %rax
movq %rax, 0x8(%rdi)
cmpl $0x0, 0x10(%rdi)
je 0xc85db6
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movl $0x18, %r15d
xorl %r12d, %r12d
movl $0x1000, %r13d # imm = 0x1000
movabsq $0x400000000, %rbp # imm = 0x400000000
mov... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<std::shared_ptr<(anonymous namespace)::InstructionRule>>::operator=(llvm::SmallVectorImpl<std::shared_ptr<(anonymous namespace)::InstructionRule>> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0xc861f8
movq %rsi, %r15
movl 0x8(%rsi), %r14d
movl 0x8(%rbx), %r12d
cmpl %r14d, %r12d
jae 0xc8610a
cmpl %r14d, 0xc(%rbx)
jae 0xc86148
movq %rbx, %rdi
callq 0xc7d8ee
movq %rbx, %rdi
movq %r14, %rsi
call... | /llvm/ADT/SmallVector.h |
llvm::SmallVectorTemplateBase<std::pair<llvm::SUnit*, llvm::SmallVector<int, 4u>>, false>::push_back(std::pair<llvm::SUnit*, llvm::SmallVector<int, 4u>>&&) | void push_back(T &&Elt) {
T *EltPtr = reserveForParamAndGetAddress(Elt);
::new ((void *)this->end()) T(::std::move(*EltPtr));
this->set_size(this->size() + 1);
} | pushq %rbx
movq %rdi, %rbx
movl $0x1, %edx
callq 0xc8695a
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,4), %rdx
movq (%rax), %rsi
leaq 0x18(%rcx,%rdx,8), %rdi
movq %rsi, -0x18(%rdi)
movq %rdi, -0x10(%rdi)
movabsq $0x400000000, %rsi # imm = 0x400000000
movq %rsi, -0x8(%rdi)
cmpl $0x0, 0x10(%rax)
je 0xc862... | /llvm/ADT/SmallVector.h |
llvm::SmallVectorTemplateBase<std::pair<llvm::SUnit*, llvm::SmallVector<int, 4u>>, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x28, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x1cba3de
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0xc8688c
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0xc86878
call... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::PipelineSolver::addEdges(llvm::SmallVectorImpl<(anonymous namespace)::SchedGroup>&, llvm::SUnit*, int, std::vector<std::pair<llvm::SUnit*, llvm::SUnit*>, std::allocator<std::pair<llvm::SUnit*, llvm::SUnit*>>>&) | int PipelineSolver::addEdges(
SmallVectorImpl<SchedGroup> &SyncPipeline, SUnit *SU, int SGID,
std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges) {
// For IsBottomUp, the first SchedGroup in SyncPipeline contains the
// instructions that are the ultimate successors in the resultant mutation.
// Therefo... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movq %r8, 0x18(%rsp)
movq %rdx, 0x10(%rsp)
movq (%rsi), %r12
movl 0x8(%rsi), %eax
cmpb $0x1, 0x34d0(%rdi)
movl %ecx, 0x4(%rsp)
jne 0xc878f5
testq %rax, %rax
je 0xc87a50
imulq $0x188, %rax, %rbx # imm = 0x18... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
void (anonymous namespace)::PipelineSolver::populateReadyList<std::reverse_iterator<int*>>(llvm::SmallVectorImpl<std::pair<int, int>>&, std::reverse_iterator<int*>, std::reverse_iterator<int*>) | void PipelineSolver::populateReadyList(
SmallVectorImpl<std::pair<int, int>> &ReadyList, T I, T E) {
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
auto SyncPipeline = CurrPipeline[CurrSyncGroupIdx];
assert(CurrSU.second.size() >= 1);
for (; I != E; ++I) {
std::vector<std::... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x678, %rsp # imm = 0x678
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
movslq 0x34bc(%rdi), %rax
movq 0x20(%rdi), %rcx
imulq $0xb0, %rax, %rax
movslq 0x34b8(%rdi), %rdx
movq (%rcx,%rax), %rax
leaq (%rdx,%rdx,4), %rcx
m... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [27], llvm::cl::initializer<int>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [27], llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x4a6786a(%rip), %rax # 0x56f1ec8
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::detail::DenseMapPair<llvm::ValueMapCallbackVH<llvm::Function const*, llvm::AMDGPUPerfHintAnalysis::FuncInfo, llvm::ValueMapConfig<llvm::Function const*, llvm::sys::SmartMutex<false>>>, llvm::AMDGPUPerfHintAnalysis::FuncInfo>* llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Function const*, llvm::... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xc8ba9e
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::ValueMap<llvm::Function const*, llvm::AMDGPUPerfHintAnalysis::FuncInfo, llvm::ValueMapConfig<llvm::Function const*, llvm::sys::SmartMutex<false>>>::operator[](llvm::Function const* const&) | ValueT &operator[](const KeyT &Key) {
return Map[Wrap(Key)];
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
movq (%rsi), %rsi
movq %rsp, %r14
movq %r14, %rdi
callq 0xaf0998
leaq 0x4a90a0f(%rip), %rax # 0x571c6c0
movq %rax, (%r14)
movq %rbx, 0x20(%r14)
movq %rbx, %rdi
movq %r14, %rsi
callq 0xc8bdb0
movq %rax, %rbx
movq 0x18(%r14), %rax
cmpq $-0x2000, %rax # imm... | /llvm/IR/ValueMap.h |
(anonymous namespace)::AMDGPUPostLegalizerCombinerImpl::applyUCharToFloat(llvm::MachineInstr&) const | void AMDGPUPostLegalizerCombinerImpl::applyUCharToFloat(
MachineInstr &MI) const {
const LLT S32 = LLT::scalar(32);
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(DstReg);
LLT SrcTy = MRI.getType(SrcReg);
if (SrcTy != S32)
SrcReg = B.b... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x20(%rsi), %rax
movl 0x4(%rax), %r13d
movl 0x24(%rax), %eax
movq 0x10a0(%rdi), %rcx
testl %r13d, %r13d
jns 0xc8ed09
movl %r13d, %edx
andl $0x7fffffff, %edx # imm = 0x7FFFFFFF
cmpl %edx, 0x1d0(%... | /Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp |
llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::SmallDenseSet<llvm::Instruction*, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>>>* llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, llvm::SmallDenseSet<llvm::Instruction*, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>>, llvm::DenseMapInfo<llvm::BasicBlock*, ... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xca23a5
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<llvm::LayoutAlignElem>::operator=(llvm::SmallVectorImpl<llvm::LayoutAlignElem> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0xca421c
movq %rsi, %r15
movl 0x8(%rsi), %r14d
movl 0x8(%rbx), %r12d
cmpl %r14d, %r12d
jae 0xca41bf
cmpl %r14d, 0xc(%rbx)
jae 0xca41d9
movl $0x0, 0x8(%rbx)
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
movq %r14, %rdx
call... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::AMDGPUPromoteAllocaImpl::getWorkitemID(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, unsigned int) | Value *AMDGPUPromoteAllocaImpl::getWorkitemID(IRBuilder<> &Builder,
unsigned N) {
Function *F = Builder.GetInsertBlock()->getParent();
const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(TM, *F);
Intrinsic::ID IntrID = Intrinsic::not_intrinsic;
StringRef AttrName;
s... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r13
movq 0x30(%rsi), %rax
movq 0x48(%rax), %rbx
movq (%rdi), %rdi
movq %rbx, %rsi
callq 0xaa4c76
movq %rax, %r14
movb 0x2c(%r13), %al
cmpl $0x2, %ebp
je 0xca4864
cmpl $0x1, %ebp
jne 0xca487c
te... | /Target/AMDGPU/AMDGPUPromoteAlloca.cpp |
(anonymous namespace)::AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool) | AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
initializeAMDGPURegBankCombinerPass(*PassRegistry::getPassRegistry());
if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4bffb2d(%rip), %rcx # 0x58a517c
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4a7756c(%rip), %rcx # 0x571cbd8
movq %rc... | /Target/AMDGPU/AMDGPURegBankCombiner.cpp |
llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(llvm::MachineInstr const&) const | RegisterBankInfo::InstructionMappings
AMDGPURegisterBankInfo::getInstrAlternativeMappings(
const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
InstructionMappings AltMappings;
switch (MI.getOpcode()) {
case TargetOp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq 0x18(%rdx), %rax
movq 0x20(%rax), %rax
movq 0x28(%rax), %r12
leaq 0x50(%rsp), %rbp
movq %rbp, -0x10(%rbp)
movabsq $0x400000000, %r13 # imm = 0x400000000
movq %r13, -0x8(%rbp)
movz... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
llvm::AMDGPURegisterBankInfo::applyMappingBFE(llvm::MachineIRBuilder&, llvm::RegisterBankInfo::OperandsMapper const&, bool) const | bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B,
const OperandsMapper &OpdMapper,
bool Signed) const {
MachineInstr &MI = OpdMapper.getMI();
MachineRegisterInfo &MRI = OpdMapper.getMRI();
// Insert basic co... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x168, %rsp # imm = 0x168
movl %ecx, 0x10(%rsp)
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movq 0x60(%rdx), %r13
movq 0x68(%rdx), %r14
movq %rdx, %rdi
callq 0x1882c2a
movq 0x20(%r14), %rax
movl 0x4(%rax), %esi
testl %esi, %esi
jns 0... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
llvm::AMDGPURegisterBankInfo::foldInsertEltToCmpSelect(llvm::MachineIRBuilder&, llvm::MachineInstr&, llvm::RegisterBankInfo::OperandsMapper const&) const | bool AMDGPURegisterBankInfo::foldInsertEltToCmpSelect(
MachineIRBuilder &B, MachineInstr &MI,
const OperandsMapper &OpdMapper) const {
MachineRegisterInfo &MRI = *B.getMRI();
Register VecReg = MI.getOperand(1).getReg();
Register Idx = MI.getOperand(3).getReg();
const RegisterBank &IdxBank =
*OpdMa... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x158, %rsp # imm = 0x158
movq %rdx, %r15
movq %rdi, %r12
movq %rsi, 0x30(%rsp)
movq 0x18(%rsi), %r13
movq 0x20(%rdx), %rax
movl 0x24(%rax), %r14d
movl 0x64(%rax), %eax
movl %eax, 0xc(%rsp)
movq %rcx, 0x10(%rsp)
movq 0x70(%rcx), %rax
mov... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
getExtendOp(unsigned int) | static unsigned getExtendOp(unsigned Opc) {
switch (Opc) {
case TargetOpcode::G_ASHR:
case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX:
return TargetOpcode::G_SEXT;
case TargetOpcode::G_LSHR:
case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX:
return TargetOpcode::G_ZEXT;
default:
retu... | cmpl $0xd7, %edi
jg 0xcb6a8d
movl $0x83, %eax
leal -0xd6(%rdi), %ecx
cmpl $0x2, %ecx
jb 0xcb6a8c
cmpl $0x87, %edi
je 0xcb6a98
cmpl $0x88, %edi
jne 0xcb6a9e
retq
addl $0xffffff28, %edi # imm = 0xFFFFFF28
cmpl $0x1, %edi
ja 0xcb6a9e
movl $0x85, %eax
retq
movl $0x7d, %eax
retq
| /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
extendLow32IntoHigh32(llvm::MachineIRBuilder&, llvm::Register, llvm::Register, unsigned int, llvm::RegisterBank const&, bool) | static void extendLow32IntoHigh32(MachineIRBuilder &B,
Register Hi32Reg, Register Lo32Reg,
unsigned ExtOpc,
const RegisterBank &RegBank,
bool IsBooleanSrc = false) {
if (ExtOpc == AM... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %esi, %ebp
movq %rdi, %rbx
cmpl $0x83, %ecx
je 0xcb6ae4
leaq 0x28(%rsp), %rsi
cmpl $0x85, %ecx
jne 0xcb6b16
movl %ebp, (%rsi)
movl $0x1, 0x8(%rsi)
movq %rbx, %rdi
xorl %edx, %edx
callq 0x1dc9434
jmp 0xcb6bc2
movl %edx, %r14d
testb %... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::Register, llvm::Register, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, llvm::Register>>, llvm::Register, llvm::Register, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, llvm::Register>>::LookupBucke... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xcbbaba
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movl (%r11), %ebx
cmpl %ebx, %esi
jne 0xcbba85
movq %r11, (%rdx)
movb $... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::Register, llvm::Register, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, llvm::Register>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::AMDGPURewriteOutArguments, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x30, %edi
callq 0x751940
movq $0x0, 0x8(%rax)
leaq 0x4be8ccc(%rip), %rcx # 0x58a534c
movq %rcx, 0x10(%rax)
movl $0x2, 0x18(%rax)
leaq 0x4a60efe(%rip), %rcx # 0x571d590
movq %rcx, (%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
popq %rcx
retq
| /llvm/PassSupport.h |
std::pair<llvm::ReturnInst*, llvm::StoreInst*>& llvm::SmallVectorImpl<std::pair<llvm::ReturnInst*, llvm::StoreInst*>>::emplace_back<llvm::ReturnInst*&, llvm::StoreInst*&>(llvm::ReturnInst*&, llvm::StoreInst*&) | reference emplace_back(ArgTypes &&... Args) {
if (LLVM_UNLIKELY(this->size() >= this->capacity()))
return this->growAndEmplaceBack(std::forward<ArgTypes>(Args)...);
::new ((void *)this->end()) T(std::forward<ArgTypes>(Args)...);
this->set_size(this->size() + 1);
return this->back();
} | pushq %rbx
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
cmpl 0xc(%rdi), %ecx
jae 0xcbd827
movq (%rbx), %rax
movq %rcx, %rdi
shlq $0x4, %rdi
movq (%rsi), %rsi
movq %rsi, (%rax,%rdi)
movq (%rdx), %rdx
movq %rdx, 0x8(%rax,%rdi)
incl %ecx
movl %ecx, 0x8(%rbx)
movl %ecx, %ecx
shlq $0x4, %rcx
addq %rcx, %rax
addq $-0x10, %rax
popq %... | /llvm/ADT/SmallVector.h |
llvm::detail::DenseMapPair<llvm::ReturnInst*, llvm::SmallVector<std::pair<llvm::Argument*, llvm::Value*>, 4u>>* llvm::DenseMapBase<llvm::DenseMap<llvm::ReturnInst*, llvm::SmallVector<std::pair<llvm::Argument*, llvm::Value*>, 4u>, llvm::DenseMapInfo<llvm::ReturnInst*, void>, llvm::detail::DenseMapPair<llvm::ReturnInst*,... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xcbdc05
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<int, llvm::Type*, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Type*>, false>, bool> llvm::DenseMapBase<llvm::SmallDenseMap<int, llvm::Type*, 4u, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Type*>>, int, llvm::Type*, llvm::DenseMapInfo<in... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r13
movq %rsi, %rdi
movq %rdx, %rsi
movq %r13, %rdx
callq 0xcbe0fa
movl %eax, %ecx
movq (%r13), %rax
testb %cl, %cl
je 0xcbe0a0
xorl %ecx, %ecx
jmp 0xcbe0c0
movq %r14,... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::SmallDenseMap<int, llvm::Type*, 4u, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Type*>>, int, llvm::Type*, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, llvm::Type*>>::moveFromOldBuckets(llvm::detail::DenseMapPair<int, llvm::Type*>*, llvm::detail::Dense... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rdi), %rax
andl $0x1, (%rdi)
movl $0x0, 0x4(%rdi)
cmoveq 0x8(%rdi), %rax
movl $0x4, %ecx
cmovel 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xcbe468
movl %ecx, %ecx
movabsq $0xfffffffffffffff, %rdx... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AMDGPUSetWavePriority::runOnMachineFunction(llvm::MachineFunction&) | bool AMDGPUSetWavePriority::runOnMachineFunction(MachineFunction &MF) {
const unsigned HighPriority = 3;
const unsigned LowPriority = 0;
Function &F = MF.getFunction();
if (skipFunction(F) || !AMDGPU::isEntryFunctionCC(F.getCallingConv()))
return false;
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtar... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x528, %rsp # imm = 0x528
movq %rsi, 0x10(%rsp)
movq (%rsi), %rbx
movq %rdi, 0x28(%rsp)
movq %rbx, %rsi
callq 0x1a7c502
testb %al, %al
jne 0xcbef33
movzwl 0x2(%rbx), %edi
shrl $0x4, %edi
andl $0x3ff, %edi # imm = 0x3FF
callq 0... | /Target/AMDGPU/AMDGPUSetWavePriority.cpp |
llvm::iterator_range<llvm::po_iterator<llvm::MachineFunction*, llvm::SmallPtrSet<llvm::GraphTraits<llvm::MachineFunction*>::NodeRef, 8u>, false, llvm::GraphTraits<llvm::MachineFunction*>>> llvm::post_order<llvm::MachineFunction*>(llvm::MachineFunction* const&) | iterator_range<po_iterator<T>> post_order(const T &G) {
return make_range(po_begin(G), po_end(G));
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x268, %rsp # imm = 0x268
movq %rdi, %rbx
movq (%rsi), %rax
movq 0x148(%rax), %rsi
leaq 0x138(%rsp), %r14
movq %r14, %rdi
callq 0xb2158e
leaq 0x8(%rsp), %r15
movl $0x130, %edx # imm = 0x130
movq %r15, %rdi
xorl %esi, %esi
callq 0x751260
leaq 0x28(%... | /llvm/ADT/PostOrderIterator.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, (anonymous namespace)::MBBInfo, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, (anonymous namespace)::MBBInfo>>, llvm::MachineBasicBlock const*, (anonymous namespace)::MBBInfo, llvm::D... | ValueT &operator[](KeyT &&Key) {
return FindAndConstruct(std::move(Key)).second;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xcbf9e4
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xcbf77c
movq %r14, %rdi
movq %rbx, %rsi
movq %rax, %rdx
callq 0xcbfa7e
movq (%rbx), %rcx
movq %rcx, (%rax)
xorps %xmm0, %xmm0
movups... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SplitModuleLogger& (anonymous namespace)::operator<<<char [15]>((anonymous namespace)::SplitModuleLogger&, char const (&) [15]) | static SplitModuleLogger &operator<<(SplitModuleLogger &SML, const Ty &Val) {
static_assert(
!std::is_same_v<Ty, Value>,
"do not print values to logs directly, use handleName instead!");
LLVM_DEBUG(dbgs() << Val);
if (SML.hasLogFile())
SML.logfile() << Val;
return SML;
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movq (%rdi), %r15
testq %r15, %r15
je 0xcc1f3b
movq %rsi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq 0x7c4562
movq %rbx, %rax
popq %rbx
popq %r14
popq %r15
retq
| /Target/AMDGPU/AMDGPUSplitModule.cpp |
(anonymous namespace)::externalize(llvm::GlobalValue&) | LinkageTypes getLinkage() const { return LinkageTypes(Linkage); } | movl 0x20(%rdi), %eax
movl %eax, %ecx
andl $0xf, %ecx
addl $-0x7, %ecx
cmpl $0x1, %ecx
ja 0xcc1f61
andl $0xffffbfc0, %eax # imm = 0xFFFFBFC0
orl $0x4010, %eax # imm = 0x4010
movl %eax, 0x20(%rdi)
testb $0x10, 0x7(%rdi)
jne 0xcc1f87
subq $0x28, %rsp
leaq 0x2ad20a1(%rip), %rax # 0x3794013
movq %rsp, %rs... | /llvm/IR/GlobalValue.h |
(anonymous namespace)::FunctionWithDependencies& llvm::SmallVectorTemplateBase<(anonymous namespace)::FunctionWithDependencies, false>::growAndEmplaceBack<(anonymous namespace)::SplitModuleLogger&, llvm::CallGraph&, llvm::DenseMap<llvm::Function const*, long, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detai... | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbp
movq %rcx, (%rsp)
movq %rdx, %r13
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x10(%rdi), %rsi
xorl %r12d, %r12d
leaq 0x10(%rsp), %r8
movl $0x30, %ecx
movq %rsi, 0x8(%rsp)
xorl %edx, %edx
callq 0x1cba3de
movq %rax, %r14
movl 0x8(... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm::Function const*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [47], llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [47], llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x7512e0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r14), %eax
movzwl 0xa(%r12), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx
orl %eax, %ecx... | /llvm/Support/CommandLine.h |
(anonymous namespace)::R600MachineCFGStructurizer::needMigrateBlock(llvm::MachineBasicBlock*) const | bool R600MachineCFGStructurizer::needMigrateBlock(MachineBasicBlock *MBB) const {
unsigned BlockSizeThreshold = 30;
unsigned CloneInstrThreshold = 100;
bool MultiplePreds = MBB && (MBB->pred_size() > 1);
if(!MultiplePreds)
return false;
unsigned BlkSize = MBB->size();
return ((BlkSize > BlockSizeThresh... | testq %rdi, %rdi
je 0xcc929b
movq 0x48(%rdi), %rcx
subq 0x40(%rdi), %rcx
shrq $0x3, %rcx
xorl %eax, %eax
cmpl $0x2, %ecx
jb 0xcc929a
movq 0x38(%rdi), %rdx
addq $0x30, %rdi
cmpq %rdi, %rdx
je 0xcc928a
xorl %eax, %eax
movq 0x8(%rdx), %rdx
incl %eax
cmpq %rdi, %rdx
jne 0xcc927f
cmpl $0x1f, %eax
jb 0xcc929b
decl %ecx
imull... | /Target/AMDGPU/R600MachineCFGStructurizer.cpp |
(anonymous namespace)::R600MachineCFGStructurizer::migrateInstruction(llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | void R600MachineCFGStructurizer::migrateInstruction(MachineBasicBlock *SrcMBB,
MachineBasicBlock *DstMBB, MachineBasicBlock::iterator I) {
MachineBasicBlock::iterator SpliceEnd;
//look for the input branchinstr, not the AMDGPU branchinstr
MachineInstr *BranchMI = getNormalBlockBranchInstr(SrcMBB);
if (!Bran... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
callq 0x96669c
movzwl 0x44(%rax), %ecx
leal -0x128(%rcx), %edx
cmpl $0x28, %edx
ja 0xcc92d0
movabsq $0x10000000003, %rsi # imm = 0x10000000003
btq %rdx, %rsi
jb 0xcc92e9
movzwl %cx, %ecx
xorl %edx, %edx
cmpl $0x127, %ecx # im... | /Target/AMDGPU/R600MachineCFGStructurizer.cpp |
llvm::GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(llvm::MachineInstr*) | int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
int FPAtomicToDenormModeWaitStates = 3;
if (!ST.hasFPAtomicToDenormModeHazard())
return 0;
assert(!ST.hasExtendedWaitCounts());
if (MI->getOpcode() != AMDGPU::S_DENORM_MODE)
return 0;
auto IsHazardFn = [](const MachineInst... | movq 0x38(%rdi), %rcx
xorl %eax, %eax
cmpl $0x9, 0x1f8(%rcx)
jne 0xcc9aa5
movq %rsi, %rdx
cmpw $0x1193, 0x44(%rsi) # imm = 0x1193
jne 0xcc9aa5
pushq %rax
leaq 0x6762(%rip), %rdi # 0xcd01e4
leaq 0x6775(%rip), %rcx # 0xcd01fe
leaq 0x7(%rsp), %rsi
leaq 0x6(%rsp), %r8
callq 0xccb3f5
movl %eax, %ecx
movl $0x3,... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
isSendMsgTraceDataOrGDS(llvm::SIInstrInfo const&, llvm::MachineInstr const&) | static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII,
const MachineInstr &MI) {
if (TII.isAlwaysGDS(MI.getOpcode()))
return true;
switch (MI.getOpcode()) {
case AMDGPU::S_SENDMSG:
case AMDGPU::S_SENDMSGHALT:
case AMDGPU::S_TTRACEDATA:
return true;
// These ... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %r15
movzwl 0x44(%rsi), %esi
callq 0xb356de
movb $0x1, %bl
testb %al, %al
jne 0xcca90d
movzwl 0x44(%r14), %edi
cmpl $0x1257, %edi # imm = 0x1257
jg 0xcca8be
cmpl $0xba4, %edi # imm = 0xBA4
je 0xcca90b
cmpl $0xc2c, %edi # imm = 0... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::GCNHazardRecognizer::fixLdsDirectVALUHazard(llvm::MachineInstr*) | int GCNHazardRecognizer::getWaitStatesSinceDef(unsigned Reg,
IsHazardFn IsHazardDef,
int Limit) {
const SIRegisterInfo *TRI = ST.getRegisterInfo();
auto IsHazardFn = [IsHazardDef, TRI, Reg](const MachineInstr &MI) {
r... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq 0x10(%rsi), %rax
movq 0x18(%rax), %rbx
btl $0x1c, %ebx
jae 0xccc1ac
movq %rsi, %r14
movq %rdi, %r15
movq 0x40(%rdi), %rdi
movl $0xb, %edx
callq 0xb2f76a
movl 0x4(%rax), %eax
leaq 0x2f(%rsp), %r13
movb $0x0, (%r13)
leaq 0x70(%rsp), %... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::GCNHazardRecognizer::fixShift64HighRegBug(llvm::MachineInstr*) | bool GCNHazardRecognizer::fixShift64HighRegBug(MachineInstr *MI) {
if (!ST.hasShift64HighRegBug())
return false;
assert(!ST.hasExtendedWaitCounts());
switch (MI->getOpcode()) {
default:
return false;
case AMDGPU::V_LSHLREV_B64_e64:
case AMDGPU::V_LSHRREV_B64_e64:
case AMDGPU::V_ASHRREV_I64_e64:
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq 0x38(%rdi), %rax
xorl %ebp, %ebp
cmpb $0x1, 0x28c(%rax)
jne 0xccca94
testb $0x1, 0x28d(%rax)
jne 0xccca94
movq %rsi, %rbx
movq %rdi, %r13
movzwl 0x44(%rsi), %eax
cmpl $0x14b6, %eax # imm = 0x14B6
je 0xccca4e
cmpl $0x1f62, ... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::GCNHazardRecognizer::checkMAIHazards90A(llvm::MachineInstr*) | unsigned getOpcode() const { return Opcode; } | movzwl 0x44(%rsi), %ecx
movq 0x10(%rsi), %rax
movb 0x1e(%rax), %al
shrb $0x6, %al
leal -0x1466(%rcx), %edx
cmpw $-0x2, %dx
setb %dl
andb %al, %dl
xorl %eax, %eax
cmpb $0x1, %dl
jne 0xcce37b
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %r13
movq %rdi, %r14
movzwl %cx, %eb... | /llvm/CodeGen/MachineInstr.h |
llvm::GCNHazardRecognizer::checkMAIHazards908(llvm::MachineInstr*) | int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) {
int WaitStatesNeeded = 0;
unsigned Opc = MI->getOpcode();
auto IsVALUFn = [](const MachineInstr &MI) {
return SIInstrInfo::isVALU(MI) || MI.isInlineAsm();
};
if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write
const ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rdi, %r14
movq %rsi, 0x10(%rsp)
movzwl 0x44(%rsi), %eax
xorl %ebx, %ebx
movl %eax, 0x8(%rsp)
cmpl $0x1464, %eax # imm = 0x1464
je 0xcce4d8
movl $0x370, %eax # imm = 0x370
addq 0x38(%r14), %rax
leaq 0x1ed5(%rip)... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::GCNHazardRecognizer::checkMFMAPadding(llvm::MachineInstr*) | int GCNHazardRecognizer::checkMFMAPadding(MachineInstr *MI) {
// Early exit if no padding is requested.
if (MFMAPaddingRatio == 0)
return 0;
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
if (!SIInstrInfo::isMFMA(*MI) || MFI->getOccupancy() < 2)
return 0;
int NeighborMFMALat... | xorl %eax, %eax
cmpl $0x0, 0x4bd712d(%rip) # 0x58a58a8
je 0xcce7f9
movq 0x10(%rsi), %rcx
testb $0x40, 0x1e(%rcx)
je 0xcce7f9
movl $0xffffeb9a, %ecx # imm = 0xFFFFEB9A
addl 0x44(%rsi), %ecx
cmpw $-0x3, %cx
ja 0xcce7f9
movq 0x30(%rdi), %rcx
movq 0x30(%rcx), %rcx
cmpl $0x2, 0x3a8(%rcx)
jb 0xcce7f9
pushq %r14
pushq... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::GCNHazardRecognizer::ShouldPreferAnother(llvm::SUnit*) | bool isInstr() const { return isInst && Instr; } | movb 0xfe(%rsi), %cl
shrb $0x3, %cl
movq (%rsi), %rax
testq %rax, %rax
setne %dl
andb %cl, %dl
cmpb $0x1, %dl
jne 0xcce8e1
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
movq %rsp, %rcx
movq $0x0, (%rcx)
movq %rcx, 0x8(%rsp)
movq 0x10(%rax), %rcx
testb $0x40, 0x1e(%rcx)
je 0xcce89b
movl $0xffffeb9a, ... | /llvm/CodeGen/ScheduleDAG.h |
bool llvm::function_ref<bool (llvm::MachineInstr const&, int)>::callback_fn<llvm::GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(llvm::MachineInstr*)::$_1>(long, llvm::MachineInstr const&, int) | unsigned getOpcode() const { return Opcode; } | movq 0x10(%rsi), %rcx
movb $0x1, %al
testb $0x2, 0x18(%rcx)
jne 0xccf3bb
movzwl 0x44(%rsi), %ecx
cmpl $0x128c, %ecx # imm = 0x128C
je 0xccf3a5
cmpl $0x128b, %ecx # imm = 0x128B
jne 0xccf3bc
movq 0x20(%rsi), %rdx
cmpq $0x0, 0x10(%rdx)
je 0xccf3bb
movzwl %cx, %eax
cmpl $0x128c, %eax # imm = ... | /llvm/CodeGen/MachineInstr.h |
bool llvm::function_ref<bool (llvm::MachineInstr const&)>::callback_fn<llvm::GCNHazardRecognizer::fixVcmpxExecWARHazard(llvm::MachineInstr*)::$_0>(long, llvm::MachineInstr const&) | const MCInstrDesc &getDesc() const { return *MCID; } | movq 0x10(%rsi), %rax
testb $0x2, 0x18(%rax)
jne 0xccf498
pushq %rax
movq (%rdi), %rdx
movq %rsi, %rdi
movl $0x1, %esi
xorl %ecx, %ecx
callq 0x1794274
cmpl $-0x1, %eax
setne %al
addq $0x8, %rsp
retq
xorl %eax, %eax
retq
nop
| /llvm/CodeGen/MachineInstr.h |
bool llvm::function_ref<bool (llvm::MachineInstr const&)>::callback_fn<llvm::GCNHazardRecognizer::fixLdsBranchVmemWARHazard(llvm::MachineInstr*)::$_2::operator()(llvm::MachineInstr const&) const::'lambda'(llvm::MachineInstr const&)>(long, llvm::MachineInstr const&) | const MCInstrDesc &getDesc() const { return *MCID; } | movq 0x10(%rsi), %rax
movq 0x18(%rax), %rcx
movl $0x1, %eax
btl $0x19, %ecx
jb 0xccf610
movl $0x2, %eax
testl $0x760000, %ecx # imm = 0x760000
jne 0xccf610
movabsq $0x108000000000000, %rdx # imm = 0x108000000000000
xorl %eax, %eax
testq %rdx, %rcx
setne %al
addl %eax, %eax
testl %eax, %eax
setne %cl
cmpl %eax, ... | /llvm/CodeGen/MachineInstr.h |
llvm::SmallDenseMap<llvm::Register, int, 4u, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, int>>::grow(unsigned int) | void grow(unsigned AtLeast) {
if (AtLeast > InlineBuckets)
AtLeast = std::max<unsigned>(64, NextPowerOf2(AtLeast-1));
if (Small) {
// First move the inline buckets into a temporary storage.
AlignedCharArrayUnion<BucketT[InlineBuckets]> TmpStorage;
BucketT *TmpBegin = reinterpret_cast<Bu... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x28, %rsp
movl %esi, %ebp
movq %rdi, %rbx
cmpl $0x5, %esi
jb 0xccfcd3
decl %ebp
movl %ebp, %eax
shrl %eax
orl %ebp, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %e... | /llvm/ADT/DenseMap.h |
llvm::CodeGenPassBuilder<llvm::R600CodeGenPassBuilder, llvm::R600TargetMachine>::CodeGenPassBuilder(llvm::R600TargetMachine&, llvm::CGPassBuilderOption const&, llvm::PassInstrumentationCallbacks*) | explicit CodeGenPassBuilder(TargetMachineT &TM,
const CGPassBuilderOption &Opts,
PassInstrumentationCallbacks *PIC)
: TM(TM), Opt(Opts), PIC(PIC) {
// Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
// substitutePass(&P... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, (%rdi)
movups (%rdx), %xmm0
movups 0x10(%rdx), %xmm1
movups 0x20(%rdx), %xmm2
movups %xmm0, 0x8(%rdi)
movups %xmm1, 0x18(%rdi)
movups %xmm2, 0x28(%rdi)
movq 0x30(%rdx), %rax
movq %rax, 0x38(... | /llvm/Passes/CodeGenPassBuilder.h |
(anonymous namespace)::R600DAGToDAGISel::SelectADDRVTX_READ(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
SDValue &Offset) {
ConstantSDNode *IMMOffset;
if (Addr.getOpcode() == ISD::ADD &&
(IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
isInt<16>(IMMOffset->getZExtValue())) {
B... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r8, %r13
movq %rcx, %r12
movq %rsi, %rbp
movl 0x18(%rsi), %eax
cmpl $0xb, %eax
je 0xcd311f
cmpl $0x23, %eax
je 0xcd311f
cmpl $0x38, %eax
jne 0xcd3124
movq 0x28(%rbp), %rcx
movq 0x28(%rcx), %rsi
movl 0x18(%rsi), %r8d
cmpl $0x23, %r8... | /Target/AMDGPU/R600ISelDAGToDAG.cpp |
llvm::R600SchedStrategy::initialize(llvm::ScheduleDAGMI*) | void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
DAG = static_cast<ScheduleDAGMILive*>(dag);
const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>();
TII = static_cast<const R600InstrInfo*>(DAG->TII);
TRI = static_cast<... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsi, 0x8(%rdi)
movq 0x10(%rsi), %rdi
movq 0x20(%rsi), %rax
movq 0x10(%rax), %r14
movq %rdi, 0x10(%rbx)
movq 0x18(%rsi), %rax
movq %rax, 0x18(%rbx)
movb 0x331(%r14), %al
xorb $0x1, %al
movb %al, 0x1e8(%rbx)
movq 0x28(%rsi), %rax
movq %rax, 0x20(%rbx)
movq $0x2, 0x1a... | /Target/AMDGPU/R600MachineScheduler.cpp |
llvm::R600SchedStrategy::getInstKind(llvm::SUnit*) | int R600SchedStrategy::getInstKind(SUnit* SU) {
int Opcode = SU->getInstr()->getOpcode();
if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
return IDFetch;
if (TII->isALUInstr(Opcode)) {
return IDAlu;
}
switch (Opcode) {
case R600::PRED_X:
case R600::COPY:
case R600::CONST_CO... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movq (%rsi), %rax
movzwl 0x44(%rax), %r14d
movq 0x10(%rdi), %rdi
movl %r14d, %esi
callq 0xaebc6a
movl $0x1, %ebx
testb %al, %al
jne 0xcd3e56
movq 0x10(%r15), %rdi
movl %r14d, %esi
callq 0xaebbe2
testb %al, %al
jne 0xcd3e56
movq 0x10(%r15), %rdi
movl %r14d, %esi
callq 0xa... | /Target/AMDGPU/R600MachineScheduler.cpp |
llvm::R600SchedStrategy::PopInst(std::vector<llvm::SUnit*, std::allocator<llvm::SUnit*>>&, bool) | SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
if (Q.empty())
return nullptr;
for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend();
It != E; ++It) {
SUnit *SU = *It;
InstructionsGroupCandidate.push_back(SU->getInstr());
if (TII->fitsConstReadLimi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movl %edx, 0x14(%rsp)
movq (%rsi), %rax
movq 0x8(%rsi), %rbp
movq %rax, 0x38(%rsp)
cmpq %rbp, %rax
je 0xcd3fca
movq %rdi, %r15
movq %rsi, 0x28(%rsp)
leaq 0x8(%rsi), %rax
movq %rax, 0x18(%rsp)
leaq 0x1d0(%rdi), %rax
movq %rax, 0x30(%rsp)
... | /Target/AMDGPU/R600MachineScheduler.cpp |
llvm::R600Subtarget::initializeSubtargetDependencies(llvm::Triple const&, llvm::StringRef, llvm::StringRef) | R600Subtarget &R600Subtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef GPU,
StringRef FS) {
SmallString<256> FullFS("+promote-alloca,");
FullFS += FS;
ParseSubtargetFeatur... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x138, %rsp # imm = 0x138
movq %r9, %r13
movq %r8, %rbp
movq %rcx, %r14
movq %rdx, %r15
movq %rdi, %rbx
leaq 0x38(%rsp), %rax
movq %rax, -0x18(%rax)
movq $0x0, -0x10(%rax)
movq $0x100, -0x8(%rax) # imm = 0x100
leaq 0x2ac71dc(%rip), ... | /Target/AMDGPU/R600Subtarget.cpp |
allUsesHaveSourceMods(llvm::MachineInstr&, llvm::MachineRegisterInfo&, unsigned int) | static bool allUsesHaveSourceMods(MachineInstr &MI, MachineRegisterInfo &MRI,
unsigned CostThreshold = 4) {
// Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
// it is truly free to use a source modifier in all cases. If there are
// multiple users but f... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebx
movq %rsi, %r14
movq 0x20(%rdi), %rax
movl 0x4(%rax), %esi
movq %r14, %rdi
callq 0x8e2244
testq %rax, %rax
sete %bpl
je 0xcd5025
movq %rax, %r15
movl %ebx, 0xc(%rsp)
movq $0x0, 0x10(%rsp)
movabsq $0x8c0200000000001, %r13 ... | /Target/AMDGPU/AMDGPUCombinerHelper.cpp |
llvm::R600TargetLowering::ReplaceNodeResults(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const | void R600TargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
switch (N->getOpcode()) {
default:
AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
return;
... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movl 0x18(%rsi), %eax
cmpl $0xdd, %eax
jg 0xcdab29
cmpl $0x41, %eax
je 0xcdab80
cmpl $0x42, %eax
jne 0xcdab71
xorl %edx, %edx
movq %rbx, %r8
addq $0x18, %rsp
popq %rbx
popq %r14
jmp 0xc2a338
cmpl $0xde, %eax
je 0xcdab51
cmpl $0xdf, %eax
jne 0xcdab71
movq 0x30(%rsi)... | /Target/AMDGPU/R600ISelLowering.cpp |
llvm::ARMAsmPrinter::GetARMGVSymbol(llvm::GlobalValue const*, unsigned char) | MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
unsigned char TargetFlags) {
if (Subtarget->isTargetMachO()) {
bool IsIndirect =
(TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
if (!IsIndirect)
return getSymbol(GV);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x318(%rdi), %rdi
movl 0x234(%rdi), %eax
cmpl $0x1, %eax
je 0xcded85
cmpl $0x5, %eax
jne 0xcdede9
testb %bpl, %bpl
jns 0xcdedcd
movq %rbx, %rsi
callq 0xd032fa
testb %al, %al
je 0xcdedc... | /Target/ARM/ARMAsmPrinter.cpp |
llvm::ARMAsmPrinter::PrintAsmMemoryOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum, const char *ExtraCode,
raw_ostream &O) {
// Does this asm operand have a single letter operand modifier?
if (ExtraCode && ExtraCode[0]) {
if (Extr... | pushq %r15
pushq %r14
pushq %rbx
movq %r8, %r14
testq %rcx, %rcx
je 0xcdfe6f
movb (%rcx), %al
testb %al, %al
je 0xcdfe6f
movb $0x1, %bl
cmpb $0x6d, %al
jne 0xcdfebe
cmpb $0x0, 0x1(%rcx)
jne 0xcdfebe
movq 0x20(%rsi), %rax
movl %edx, %ecx
shlq $0x5, %rcx
cmpb $0x0, (%rax,%rcx)
jne 0xcdfebe
addq %rcx, %rax
movl 0x4(%rax),... | /Target/ARM/ARMAsmPrinter.cpp |
getBFLabel(llvm::StringRef, unsigned int, unsigned int, llvm::MCContext&) | static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
unsigned LabelId, MCContext &Ctx) {
MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
+ "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
return Label;
} | subq $0xa8, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x60(%rsp)
leaq 0x2da22e8(%rip), %rax # 0x3a87dc2
movq %rax, 0x68(%rsp)
movw $0x305, 0x78(%rsp) # imm = 0x305
movb $0x5, %al
movb $0x1, %sil
xorl %edi, %edi
testb %dil, %dil
jne 0xce5b05
movl %edx, %edx
movl $0x5, %edi
cmpl $0x1, %edi
jne 0xce5b09
movq %rdx, 0x8(... | /Target/ARM/ARMAsmPrinter.cpp |
llvm::ARMBaseRegisterInfo::getCallPreservedMask(llvm::MachineFunction const&, unsigned int) const | const uint32_t *
ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
if (CC == CallingConv::GHC)
// This is academic because all GHC calls are (supposed to be) tail c... | cmpl $0xa, %edx
je 0xce6e78
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %edx, %ebx
movq %rsi, %r15
movq 0x10(%rsi), %r14
cmpl $0x14, %edx
je 0xce6e3d
cmpl $0x13, %ebx
jne 0xce6e80
leaq 0x2abe278(%rip), %rax # 0x37a50b0
jmp 0xce6f4e
movl 0x22c(%r14), %ecx
movl %ecx, %edx
andl $-0x9, %edx
leaq 0x2abe3b0(%rip... | /Target/ARM/ARMBaseRegisterInfo.cpp |
getPairedGPR(unsigned short, bool, llvm::MCRegisterInfo const*) | static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
const MCRegisterInfo *RI) {
for (MCPhysReg Super : RI->superregs(Reg))
if (ARM::GPRPairRegClass.contains(Super))
return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
return 0;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq (%rdx), %rcx
movq 0x30(%rdx), %rax
movl %edi, %edx
leaq (%rdx,%rdx,2), %rdx
movl 0x8(%rcx,%rdx,8), %ecx
movzwl (%rax,%rcx,2), %r14d
testl %r14d, %r14d
je 0xce788b
leaq (%rax,%rcx,2), %r15
addq $0x2, %r15
movzwl %di, %eax
a... | /Target/ARM/ARMBaseRegisterInfo.cpp |
llvm::ARMBaseRegisterInfo::getFrameRegister(llvm::MachineFunction const&) const | Register
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
const ARMFrameLowering *TFI = getFrameLowering(MF);
if (TFI->hasFP(MF))
return STI.getFramePointerReg();
return ARM::SP;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq 0x10(%rsi), %rbx
movq (%rbx), %rax
movq %rbx, %rdi
callq *0x88(%rax)
movq (%rax), %rcx
movq %rax, %rdi
movq %r14, %rsi
callq *0xc8(%rcx)
movl %eax, %ecx
movl $0x10, %eax
testb %cl, %cl
je 0xce7b2b
movl 0x22c(%rbx), %ecx
movl %ecx, %edx
andl $-0x9, %edx
movl $0x50, %... | /Target/ARM/ARMBaseRegisterInfo.cpp |
llvm::ARMBaseRegisterInfo::needsFrameBaseReg(llvm::MachineInstr*, long) const | bool ARMBaseRegisterInfo::
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
}
// It's the load/store FI references that cause issues, as it can be difficult
// to m... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r14
movzwl 0x44(%rsi), %ecx
xorl %eax, %eax
cmpl $0xf16, %ecx # imm = 0xF16
jg 0xce7e6b
cmpl $0x7cc, %ecx # imm = 0x7CC
jle 0xce7eb3
leal -0x7cd(%rcx), %edx
cmpl $0x14, %e... | /Target/ARM/ARMBaseRegisterInfo.cpp |
llvm::ARMBaseRegisterInfo::getLargestSuperClass(llvm::TargetRegisterClass const*) const | unsigned getID() const { return MC->getID(); } | movq (%rsi), %rax
movzwl 0x18(%rax), %ecx
movl %ecx, %eax
shrl $0x5, %eax
leaq 0x2ab5261(%rip), %rdx # 0x379db10
movl (%rdx,%rax,4), %edi
movl $0x1, %edx
shll %cl, %edx
btl %ecx, %edi
jae 0xce88c6
leaq 0x4a3867b(%rip), %rax # 0x5720f40
retq
leaq 0x2ab3b83(%rip), %rcx # 0x379c450
testl %edx, (%rcx,%rax,4)
je 0xce8... | /llvm/CodeGen/TargetRegisterInfo.h |
std::pair<llvm::DenseMapIterator<llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, unsigned int>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapI... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r13
movq %rsi, %rdi
movq %rdx, %rsi
movq %r13, %rdx
callq 0xce8946
movl %eax, %ecx
movq (%r13), %rax
testb %cl, %cl
je 0xce8a12
xorl %ecx, %ecx
jmp 0xce8a32
movq %r14,... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, unsigned int>>, llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llv... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xce8ced
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
neg... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::StackAdjustingInsts::addExtraBytes(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, unsigned int) | iterator begin() { return (iterator)this->BeginX; } | movq (%rdi), %rax
movl 0x8(%rdi), %r9d
movq %r9, %r8
shlq $0x4, %r8
movq %rax, %rcx
cmpq $0x4, %r9
jae 0xcee25f
addq %r8, %rax
movq %rax, %rdi
subq %rcx, %rdi
sarq $0x4, %rdi
cmpq $0x1, %rdi
je 0xcee252
cmpq $0x2, %rdi
je 0xcee249
cmpq $0x3, %rdi
jne 0xcee25a
cmpq %rsi, (%rcx)
je 0xcee29a
addq $0x10, %rcx
cmpq %rsi, (%... | /llvm/ADT/SmallVector.h |
emitRegPlusImmediate(bool, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::DebugLoc const&, llvm::ARMBaseInstrInfo const&, unsigned int, unsigned int, int, unsigned int, llvm::ARMCC::CondCodes, unsigned int) | static void emitRegPlusImmediate(
bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
... | pushq %r14
pushq %rbx
pushq %rax
movl %r9d, %r10d
movq %r8, %rax
movl 0x38(%rsp), %ebx
movl 0x30(%rsp), %r11d
movl 0x28(%rsp), %r14d
movl 0x20(%rsp), %r9d
testl %edi, %edi
je 0xcee347
movq %rsi, %rdi
movq %rdx, %rsi
movq %rcx, %rdx
movl %r10d, %ecx
movl $0x10, %r8d
pushq %r14
pushq %rax
pushq %rbx
pushq %r11
callq 0xd3... | /Target/ARM/ARMFrameLowering.cpp |
emitAligningInstructions(llvm::MachineFunction&, llvm::ARMFunctionInfo*, llvm::TargetInstrInfo const&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, unsigned int, llvm::Align, bool) | static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
const TargetInstrInfo &TII,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r9, %r13
movq %r8, %r14
movq %rcx, %r15
movq %rdx, (%rsp)
movb 0x108(%rsp), %bl
movq 0x10(%rdi), %rcx
movb $0x1, %al
cmpb $0x0, 0x169(%rcx)
jne 0xcee3a6
movb 0x16b(%rcx), %al
movl $0x1, %ebp
movl %ebx, %ecx
shlq %cl, %rbp
movl 0x10... | /Target/ARM/ARMFrameLowering.cpp |
llvm::ARMFrameLowering::ResolveFrameIndexReference(llvm::MachineFunction const&, int, llvm::Register&, int) const | int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
int FI, Register &FrameReg,
int SPAdj) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const ARMBaseRegisterInfo *RegInfo = static_ca... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %r8d, %r14d
movq %rcx, %rbp
movl %edx, %r13d
movq %rsi, %r15
movq %rdi, %r12
movq 0x10(%rsi), %rdi
movq 0x38(%rsi), %rbx
movq (%rdi), %rax
callq *0xc8(%rax)
movq 0x30(%r15), %rdi
movl 0x20(%rbx), %esi
leal (%rsi,%r13), %ecx
movq 0x8... | /Target/ARM/ARMFrameLowering.cpp |
llvm::cl::opt<ITMode, false, llvm::cl::parser<ITMode>>::getValueExpectedFlagDefault() const | enum ValueExpected getValueExpectedFlagDefault() const {
// If there is an ArgStr specified, then we are of the form:
//
// -opt=O2 or -opt O2 or -optO2
//
// In which case, the value is required. Otherwise if an arg str has not
// been specified, we are of the form:
//
// -... | movq 0xa0(%rdi), %rcx
xorl %eax, %eax
cmpq $0x1, 0x18(%rcx)
adcl $0x2, %eax
retq
| /llvm/Support/CommandLine.h |
void llvm::cl::ValuesClass::apply<llvm::cl::opt<ITMode, false, llvm::cl::parser<ITMode>>>(llvm::cl::opt<ITMode, false, llvm::cl::parser<ITMode>>&) const | size_t size() const { return Size; } | movl 0x8(%rdi), %eax
testq %rax, %rax
je 0xd03a79
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq (%rdi), %r14
leaq (%rax,%rax,4), %rax
leaq (%r14,%rax,8), %r15
addq $0x98, %rbx
movq (%r14), %rsi
movq 0x8(%r14), %rdx
leaq 0x10(%r14), %rcx
movq 0x18(%r14), %r8
movq 0x20(%r14), %r9
movq %rbx, %rdi
callq 0xd03a7a
ad... | /llvm/ADT/SmallVector.h |
llvm::ARMElfTargetObjectFile::getExplicitSectionGlobal(llvm::GlobalObject const*, llvm::SectionKind, llvm::TargetMachine const&) const | MCSection *ARMElfTargetObjectFile::getExplicitSectionGlobal(
const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
// Set execute-only access for the explicit section
if (isExecuteOnlyFunction(GO, SK, TM))
SK = SectionKind::getExecuteOnly();
return TargetLoweringObjectFileELF::getExpli... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
cmpb $0x0, (%rsi)
jne 0xd089bc
movq (%rbx), %rax
movq %rbx, %rdi
movq %r14, %rsi
callq *0x10(%rax)
movl %ebp, %ecx
andl $0xfe, %ecx
cmpl $0x2, %ecx
sete %dl
movl $0x3, %ecx
testb %dl, 0x12b(%rax)
jne 0... | /Target/ARM/ARMTargetObjectFile.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [20], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(char const (&) [20], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x49da75... | /llvm/Support/CommandLine.h |
llvm::ARMTTIImpl::instCombineIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&) const | std::optional<Instruction *>
ARMTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
using namespace PatternMatch;
Intrinsic::ID IID = II.getIntrinsicID();
switch (IID) {
default:
break;
case Intrinsic::arm_neon_vld1: {
Align MemAlign =
getKnownAlignment(II.getArgOperand(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq -0x20(%rdx), %rax
movl 0x24(%rax), %eax
cmpl $0xcf6, %eax # imm = 0xCF6
jg 0xd08f87
leal -0xcc1(%rax), %ecx
cmpl $0x2, %ecx
jb 0xd09008
cmpl $0xca5, %eax # imm = 0xCA5
je 0xd0920... | /Target/ARM/ARMTargetTransformInfo.cpp |
llvm::ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) const | std::optional<Value *> ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
// Compute the demand... | subq $0x28, %rsp
movq 0x38(%rsp), %rax
movq %rdx, 0x8(%rsp)
movq %rax, 0x10(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x20(%rsp)
movq -0x20(%rdx), %rax
movl 0x24(%rax), %eax
cmpl $0xcd3, %eax # imm = 0xCD3
je 0xd0992b
cmpl $0xd2d, %eax # imm = 0xD2D
je 0xd09924
cmpl $0xd09, %eax # imm = 0xD... | /Target/ARM/ARMTargetTransformInfo.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::ValueMapConfig<llvm::Value*, llvm::sys::SmartMutex<false>>>, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::In... | unsigned getNumBuckets() const {
return NumBuckets;
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movl 0x10(%rdi), %eax
testl %eax, %eax
je 0xd13828
movq (%rdi), %rcx
leaq 0x8(%rsp), %rdi
movq $0x2, (%rdi)
xorl %r8d, %r8d
movq %r8, 0x8(%rdi)
movq $-0x1000, 0x10(%rdi) # imm = 0xF000
leaq 0x4a111dd(%rip), %r9 # 0x5724960
movq %r9, -0x8(%rdi)
movq %r8, 0x18(%rdi)
movl 0x18(... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [19], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [19], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r12), %eax
movzwl 0xa(%r14), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
void llvm::SmallVectorImpl<llvm::Value const*>::append<llvm::User::value_op_iterator, void>(llvm::User::value_op_iterator, llvm::User::value_op_iterator) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
subq %rsi, %rbx
sarq $0x5, %rbx
movl 0x8(%rdi), %edx
movl 0xc(%rdi), %eax
addq %rbx, %rdx
cmpq %rax, %rdx
jbe 0xd169dc
leaq 0x10(%r14), %rsi
movl $0x8, %ecx
movq %r14, %rdi
callq 0x1cba528
movl 0x8(%r14), %eax
testq %rbx, %rbx
jle 0xd16a0b... | /llvm/ADT/SmallVector.h |
llvm::cl::parser<llvm::TailPredication::Mode>::parse(llvm::cl::Option&, llvm::StringRef, llvm::StringRef, llvm::TailPredication::Mode&) | bool parse(Option &O, StringRef ArgName, StringRef Arg, DataType &V) {
StringRef ArgVal;
if (Owner.hasArgStr())
ArgVal = Arg;
else
ArgVal = ArgName;
for (size_t i = 0, e = Values.size(); i != e; ++i)
if (Values[i].Name == ArgVal) {
V = Values[i].V.getValue();
return fa... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %rbx
movq 0x8(%rdi), %rax
cmpq $0x0, 0x18(%rax)
cmovneq %r8, %r15
cmovneq %r9, %r14
movl 0x18(%rdi), %eax
testq %rax, %rax
je 0xd1d2c7
movq 0x10(%rdi), %r13
shlq $0x4, %rax
leaq (%rax,%rax,2), %... | /llvm/Support/CommandLine.h |
llvm::ScalarEvolution::getAddExpr(llvm::SCEV const*, llvm::SCEV const*, llvm::SCEV const*, llvm::SCEV::NoWrapFlags, unsigned int) | const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
SCEV::NoWrapFlags Flags = SCEV::FlagAnyWrap,
unsigned Depth = 0) {
SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2};
return getAddExpr(Ops, Flags, Depth);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x40, %rsp
movl %r9d, %ebx
movl %r8d, %ebp
movq %rdi, %r14
leaq 0x18(%rsp), %rax
movq %rsi, -0x18(%rax)
movq %rdx, -0x10(%rax)
movq %rcx, -0x8(%rax)
leaq 0x28(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x300000000, %rcx # imm = 0x300000000
movq %rcx, -0... | /llvm/Analysis/ScalarEvolution.h |
(anonymous namespace)::MVETPAndVPTOptimisations::runOnMachineFunction(llvm::MachineFunction&) | bool MVETPAndVPTOptimisations::runOnMachineFunction(MachineFunction &Fn) {
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
if (!STI.isThumb2() || !STI.hasLOB())
return false;
TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
MRI = &Fn.getRegInfo();
MachineLoopInfo *MLI = &getAna... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x218, %rsp # imm = 0x218
movq %rdi, %r14
movq %rsi, 0x1b0(%rsp)
movq 0x10(%rsi), %rdi
xorl %ebx, %ebx
cmpb $0x1, 0x192(%rdi)
jne 0xd21d3b
testb $0x1, 0x161(%rdi)
je 0xd21d3b
cmpb $0x1, 0x14f(%rdi)
jne 0xd20c06
movq (%rdi), %rax
callq *0... | /Target/ARM/MVETPAndVPTOptimisationsPass.cpp |
findLoopComponents(llvm::MachineLoop*, llvm::MachineRegisterInfo*, llvm::MachineInstr*&, llvm::MachineInstr*&, llvm::MachineInstr*&, llvm::MachineInstr*&) | static bool findLoopComponents(MachineLoop *ML, MachineRegisterInfo *MRI,
MachineInstr *&LoopStart, MachineInstr *&LoopPhi,
MachineInstr *&LoopDec, MachineInstr *&LoopEnd) {
MachineBasicBlock *Header = ML->getHeader();
MachineBasicBlock *Latch = ML->getL... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r9, %rbp
movq %r8, %r13
movq %rcx, %r12
movq %rdx, (%rsp)
movq %rsi, %r14
movq 0x20(%rdi), %rax
movq (%rax), %rbx
callq 0x17a331c
movq %rax, %r15
testq %rbx, %rbx
sete %al
testq %r15, %r15
sete %cl
orb %al, %cl
jne 0xd21ef9
movq $0x0, (%... | /Target/ARM/MVETPAndVPTOptimisationsPass.cpp |
llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(llvm::MachineFunction&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | MachineBasicBlock::iterator Thumb1FrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const Thumb1InstrInfo &TII =
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
const ThumbRegisterInfo *Reg... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, %r12
movq %rcx, 0x8(%rsp)
movq 0x18(%rdi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, %r14
movq 0x18(%r12), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r15
movq (%r12), %rax
movq %r12, %r... | /Target/ARM/Thumb1FrameLowering.cpp |
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